Commit | Line | Data |
---|---|---|
1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
1053d35f RR |
32 | #include <net/mac80211.h> |
33 | #include "iwl-eeprom.h" | |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
38 | #include "iwl-helpers.h" | |
39 | ||
30e553e3 TW |
40 | static const u16 default_tid_to_tx_fifo[] = { |
41 | IWL_TX_FIFO_AC1, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC0, | |
44 | IWL_TX_FIFO_AC1, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC2, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_AC3, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_NONE, | |
57 | IWL_TX_FIFO_AC3 | |
58 | }; | |
59 | ||
4ddbb7d0 TW |
60 | static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv, |
61 | struct iwl_dma_ptr *ptr, size_t size) | |
62 | { | |
63 | ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma); | |
64 | if (!ptr->addr) | |
65 | return -ENOMEM; | |
66 | ptr->size = size; | |
67 | return 0; | |
68 | } | |
69 | ||
70 | static inline void iwl_free_dma_ptr(struct iwl_priv *priv, | |
71 | struct iwl_dma_ptr *ptr) | |
72 | { | |
73 | if (unlikely(!ptr->addr)) | |
74 | return; | |
75 | ||
76 | pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma); | |
77 | memset(ptr, 0, sizeof(*ptr)); | |
78 | } | |
79 | ||
fd4abac5 TW |
80 | /** |
81 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
82 | */ | |
83 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
84 | { | |
85 | u32 reg = 0; | |
86 | int ret = 0; | |
87 | int txq_id = txq->q.id; | |
88 | ||
89 | if (txq->need_update == 0) | |
90 | return ret; | |
91 | ||
92 | /* if we're trying to save power */ | |
93 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
94 | /* wake up nic if it's powered down ... | |
95 | * uCode will wake up, and interrupt us again, so next | |
96 | * time we'll skip this part. */ | |
97 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
98 | ||
99 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
309e731a BC |
100 | IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", |
101 | txq_id, reg); | |
fd4abac5 TW |
102 | iwl_set_bit(priv, CSR_GP_CNTRL, |
103 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
104 | return ret; | |
105 | } | |
106 | ||
fd4abac5 TW |
107 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
108 | txq->q.write_ptr | (txq_id << 8)); | |
fd4abac5 TW |
109 | |
110 | /* else not in power-save mode, uCode will never sleep when we're | |
111 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
112 | } else | |
113 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
114 | txq->q.write_ptr | (txq_id << 8)); | |
115 | ||
116 | txq->need_update = 0; | |
117 | ||
118 | return ret; | |
119 | } | |
120 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
121 | ||
122 | ||
a239a8b4 WYG |
123 | void iwl_free_tfds_in_queue(struct iwl_priv *priv, |
124 | int sta_id, int tid, int freed) | |
125 | { | |
126 | if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed) | |
127 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
128 | else { | |
129 | IWL_ERR(priv, "free more than tfds_in_queue (%u:%d)\n", | |
130 | priv->stations[sta_id].tid[tid].tfds_in_queue, | |
131 | freed); | |
132 | priv->stations[sta_id].tid[tid].tfds_in_queue = 0; | |
133 | } | |
134 | } | |
135 | EXPORT_SYMBOL(iwl_free_tfds_in_queue); | |
136 | ||
1053d35f RR |
137 | /** |
138 | * iwl_tx_queue_free - Deallocate DMA queue. | |
139 | * @txq: Transmit queue to deallocate. | |
140 | * | |
141 | * Empty queue by removing and destroying all BD's. | |
142 | * Free all buffers. | |
143 | * 0-fill, but do not free "txq" descriptor structure. | |
144 | */ | |
a8e74e27 | 145 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 146 | { |
da99c4b6 | 147 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 148 | struct iwl_queue *q = &txq->q; |
1053d35f | 149 | struct pci_dev *dev = priv->pci_dev; |
71c55d90 | 150 | int i; |
1053d35f RR |
151 | |
152 | if (q->n_bd == 0) | |
153 | return; | |
154 | ||
155 | /* first, empty all BD's */ | |
156 | for (; q->write_ptr != q->read_ptr; | |
157 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
7aaa1d79 | 158 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
1053d35f | 159 | |
1053d35f | 160 | /* De-alloc array of command/tx buffers */ |
961ba60a | 161 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 162 | kfree(txq->cmd[i]); |
1053d35f RR |
163 | |
164 | /* De-alloc circular buffer of TFDs */ | |
165 | if (txq->q.n_bd) | |
a8e74e27 | 166 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 167 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
1053d35f RR |
168 | |
169 | /* De-alloc array of per-TFD driver data */ | |
170 | kfree(txq->txb); | |
171 | txq->txb = NULL; | |
172 | ||
c2acea8e JB |
173 | /* deallocate arrays */ |
174 | kfree(txq->cmd); | |
175 | kfree(txq->meta); | |
176 | txq->cmd = NULL; | |
177 | txq->meta = NULL; | |
178 | ||
1053d35f RR |
179 | /* 0-fill queue descriptor structure */ |
180 | memset(txq, 0, sizeof(*txq)); | |
181 | } | |
a8e74e27 | 182 | EXPORT_SYMBOL(iwl_tx_queue_free); |
961ba60a TW |
183 | |
184 | /** | |
185 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
186 | * @txq: Transmit queue to deallocate. | |
187 | * | |
188 | * Empty queue by removing and destroying all BD's. | |
189 | * Free all buffers. | |
190 | * 0-fill, but do not free "txq" descriptor structure. | |
191 | */ | |
3e5d238f | 192 | void iwl_cmd_queue_free(struct iwl_priv *priv) |
961ba60a TW |
193 | { |
194 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
195 | struct iwl_queue *q = &txq->q; | |
196 | struct pci_dev *dev = priv->pci_dev; | |
71c55d90 | 197 | int i; |
961ba60a TW |
198 | |
199 | if (q->n_bd == 0) | |
200 | return; | |
201 | ||
961ba60a TW |
202 | /* De-alloc array of command/tx buffers */ |
203 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
204 | kfree(txq->cmd[i]); | |
205 | ||
206 | /* De-alloc circular buffer of TFDs */ | |
207 | if (txq->q.n_bd) | |
3e5d238f | 208 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 209 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
961ba60a | 210 | |
28142986 RC |
211 | /* deallocate arrays */ |
212 | kfree(txq->cmd); | |
213 | kfree(txq->meta); | |
214 | txq->cmd = NULL; | |
215 | txq->meta = NULL; | |
216 | ||
961ba60a TW |
217 | /* 0-fill queue descriptor structure */ |
218 | memset(txq, 0, sizeof(*txq)); | |
219 | } | |
3e5d238f AK |
220 | EXPORT_SYMBOL(iwl_cmd_queue_free); |
221 | ||
fd4abac5 TW |
222 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
223 | * DMA services | |
224 | * | |
225 | * Theory of operation | |
226 | * | |
227 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
228 | * of buffer descriptors, each of which points to one or more data buffers for | |
229 | * the device to read from or fill. Driver and device exchange status of each | |
230 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
231 | * entries in each circular buffer, to protect against confusing empty and full | |
232 | * queue states. | |
233 | * | |
234 | * The device reads or writes the data in the queues via the device's several | |
235 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
236 | * | |
237 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
238 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
239 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
240 | * Tx queue resumed. | |
241 | * | |
242 | * See more detailed info in iwl-4965-hw.h. | |
243 | ***************************************************/ | |
244 | ||
245 | int iwl_queue_space(const struct iwl_queue *q) | |
246 | { | |
247 | int s = q->read_ptr - q->write_ptr; | |
248 | ||
249 | if (q->read_ptr > q->write_ptr) | |
250 | s -= q->n_bd; | |
251 | ||
252 | if (s <= 0) | |
253 | s += q->n_window; | |
254 | /* keep some reserve to not confuse empty and full situations */ | |
255 | s -= 2; | |
256 | if (s < 0) | |
257 | s = 0; | |
258 | return s; | |
259 | } | |
260 | EXPORT_SYMBOL(iwl_queue_space); | |
261 | ||
262 | ||
1053d35f RR |
263 | /** |
264 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
265 | */ | |
443cfd45 | 266 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
267 | int count, int slots_num, u32 id) |
268 | { | |
269 | q->n_bd = count; | |
270 | q->n_window = slots_num; | |
271 | q->id = id; | |
272 | ||
273 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
274 | * and iwl_queue_dec_wrap are broken. */ | |
275 | BUG_ON(!is_power_of_2(count)); | |
276 | ||
277 | /* slots_num must be power-of-two size, otherwise | |
278 | * get_cmd_index is broken. */ | |
279 | BUG_ON(!is_power_of_2(slots_num)); | |
280 | ||
281 | q->low_mark = q->n_window / 4; | |
282 | if (q->low_mark < 4) | |
283 | q->low_mark = 4; | |
284 | ||
285 | q->high_mark = q->n_window / 8; | |
286 | if (q->high_mark < 2) | |
287 | q->high_mark = 2; | |
288 | ||
289 | q->write_ptr = q->read_ptr = 0; | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | /** | |
295 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
296 | */ | |
297 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 298 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
299 | { |
300 | struct pci_dev *dev = priv->pci_dev; | |
3978e5bc | 301 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
302 | |
303 | /* Driver private data, only for Tx (not command) queues, | |
304 | * not shared with device. */ | |
305 | if (id != IWL_CMD_QUEUE_NUM) { | |
306 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
307 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
308 | if (!txq->txb) { | |
15b1687c | 309 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
310 | "structures failed\n"); |
311 | goto error; | |
312 | } | |
3978e5bc | 313 | } else { |
1053d35f | 314 | txq->txb = NULL; |
3978e5bc | 315 | } |
1053d35f RR |
316 | |
317 | /* Circular buffer of transmit frame descriptors (TFDs), | |
318 | * shared with device */ | |
3978e5bc | 319 | txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr); |
1053d35f | 320 | |
499b1883 | 321 | if (!txq->tfds) { |
3978e5bc | 322 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
323 | goto error; |
324 | } | |
325 | txq->q.id = id; | |
326 | ||
327 | return 0; | |
328 | ||
329 | error: | |
330 | kfree(txq->txb); | |
331 | txq->txb = NULL; | |
332 | ||
333 | return -ENOMEM; | |
334 | } | |
335 | ||
1053d35f RR |
336 | /** |
337 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
338 | */ | |
a8e74e27 SO |
339 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
340 | int slots_num, u32 txq_id) | |
1053d35f | 341 | { |
da99c4b6 | 342 | int i, len; |
73b7d742 | 343 | int ret; |
c2acea8e | 344 | int actual_slots = slots_num; |
1053d35f RR |
345 | |
346 | /* | |
347 | * Alloc buffer array for commands (Tx or other types of commands). | |
348 | * For the command queue (#4), allocate command space + one big | |
349 | * command for scan, since scan command is very huge; the system will | |
350 | * not have two scans at the same time, so only one is needed. | |
351 | * For normal Tx queues (all other queues), no super-size command | |
352 | * space is needed. | |
353 | */ | |
c2acea8e JB |
354 | if (txq_id == IWL_CMD_QUEUE_NUM) |
355 | actual_slots++; | |
356 | ||
357 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
358 | GFP_KERNEL); | |
359 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
360 | GFP_KERNEL); | |
361 | ||
362 | if (!txq->meta || !txq->cmd) | |
363 | goto out_free_arrays; | |
364 | ||
365 | len = sizeof(struct iwl_device_cmd); | |
366 | for (i = 0; i < actual_slots; i++) { | |
367 | /* only happens for cmd queue */ | |
368 | if (i == slots_num) | |
369 | len += IWL_MAX_SCAN_SIZE; | |
da99c4b6 | 370 | |
49898852 | 371 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 372 | if (!txq->cmd[i]) |
73b7d742 | 373 | goto err; |
da99c4b6 | 374 | } |
1053d35f RR |
375 | |
376 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
377 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
378 | if (ret) | |
379 | goto err; | |
1053d35f | 380 | |
1053d35f RR |
381 | txq->need_update = 0; |
382 | ||
1a716557 JB |
383 | /* |
384 | * Aggregation TX queues will get their ID when aggregation begins; | |
385 | * they overwrite the setting done here. The command FIFO doesn't | |
386 | * need an swq_id so don't set one to catch errors, all others can | |
387 | * be set up to the identity mapping. | |
388 | */ | |
389 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
45af8195 JB |
390 | txq->swq_id = txq_id; |
391 | ||
1053d35f RR |
392 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
393 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
394 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
395 | ||
396 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
397 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
398 | ||
399 | /* Tell device where to find queue */ | |
a8e74e27 | 400 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
401 | |
402 | return 0; | |
73b7d742 | 403 | err: |
c2acea8e | 404 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 405 | kfree(txq->cmd[i]); |
c2acea8e JB |
406 | out_free_arrays: |
407 | kfree(txq->meta); | |
408 | kfree(txq->cmd); | |
73b7d742 | 409 | |
73b7d742 | 410 | return -ENOMEM; |
1053d35f | 411 | } |
a8e74e27 SO |
412 | EXPORT_SYMBOL(iwl_tx_queue_init); |
413 | ||
da1bc453 TW |
414 | /** |
415 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
416 | * | |
417 | * Destroy all TX DMA queues and structures | |
418 | */ | |
419 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
420 | { | |
421 | int txq_id; | |
422 | ||
423 | /* Tx queues */ | |
77ca7d9e | 424 | if (priv->txq) { |
88804e2b WYG |
425 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; |
426 | txq_id++) | |
427 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
428 | iwl_cmd_queue_free(priv); | |
429 | else | |
430 | iwl_tx_queue_free(priv, txq_id); | |
77ca7d9e | 431 | } |
4ddbb7d0 TW |
432 | iwl_free_dma_ptr(priv, &priv->kw); |
433 | ||
434 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
88804e2b WYG |
435 | |
436 | /* free tx queue structure */ | |
437 | iwl_free_txq_mem(priv); | |
da1bc453 TW |
438 | } |
439 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
440 | ||
1053d35f RR |
441 | /** |
442 | * iwl_txq_ctx_reset - Reset TX queue context | |
a96a27f9 | 443 | * Destroys all DMA structures and initialize them again |
1053d35f RR |
444 | * |
445 | * @param priv | |
446 | * @return error code | |
447 | */ | |
448 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
449 | { | |
450 | int ret = 0; | |
451 | int txq_id, slots_num; | |
da1bc453 | 452 | unsigned long flags; |
1053d35f | 453 | |
1053d35f RR |
454 | /* Free all tx/cmd queues and keep-warm buffer */ |
455 | iwl_hw_txq_ctx_free(priv); | |
456 | ||
4ddbb7d0 TW |
457 | ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls, |
458 | priv->hw_params.scd_bc_tbls_size); | |
459 | if (ret) { | |
15b1687c | 460 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); |
4ddbb7d0 TW |
461 | goto error_bc_tbls; |
462 | } | |
1053d35f | 463 | /* Alloc keep-warm buffer */ |
4ddbb7d0 | 464 | ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); |
1053d35f | 465 | if (ret) { |
15b1687c | 466 | IWL_ERR(priv, "Keep Warm allocation failed\n"); |
1053d35f RR |
467 | goto error_kw; |
468 | } | |
88804e2b WYG |
469 | |
470 | /* allocate tx queue structure */ | |
471 | ret = iwl_alloc_txq_mem(priv); | |
472 | if (ret) | |
473 | goto error; | |
474 | ||
da1bc453 | 475 | spin_lock_irqsave(&priv->lock, flags); |
1053d35f RR |
476 | |
477 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
478 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
479 | ||
4ddbb7d0 TW |
480 | /* Tell NIC where to find the "keep warm" buffer */ |
481 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
482 | ||
da1bc453 TW |
483 | spin_unlock_irqrestore(&priv->lock, flags); |
484 | ||
da1bc453 | 485 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
486 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
487 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
488 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
489 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
490 | txq_id); | |
491 | if (ret) { | |
15b1687c | 492 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); |
1053d35f RR |
493 | goto error; |
494 | } | |
495 | } | |
496 | ||
497 | return ret; | |
498 | ||
499 | error: | |
500 | iwl_hw_txq_ctx_free(priv); | |
4ddbb7d0 | 501 | iwl_free_dma_ptr(priv, &priv->kw); |
1053d35f | 502 | error_kw: |
4ddbb7d0 TW |
503 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); |
504 | error_bc_tbls: | |
1053d35f RR |
505 | return ret; |
506 | } | |
a33c2f47 | 507 | |
da1bc453 TW |
508 | /** |
509 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
510 | */ | |
511 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
512 | { | |
f3f911d1 | 513 | int ch; |
da1bc453 TW |
514 | unsigned long flags; |
515 | ||
da1bc453 TW |
516 | /* Turn off all Tx DMA fifos */ |
517 | spin_lock_irqsave(&priv->lock, flags); | |
da1bc453 TW |
518 | |
519 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
520 | ||
521 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
f3f911d1 ZY |
522 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { |
523 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
da1bc453 | 524 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
f3f911d1 | 525 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
f056658b | 526 | 1000); |
da1bc453 | 527 | } |
da1bc453 TW |
528 | spin_unlock_irqrestore(&priv->lock, flags); |
529 | ||
530 | /* Deallocate memory for all Tx queues */ | |
531 | iwl_hw_txq_ctx_free(priv); | |
532 | } | |
533 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
534 | |
535 | /* | |
536 | * handle build REPLY_TX command notification. | |
537 | */ | |
538 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
539 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 540 | struct ieee80211_tx_info *info, |
fd4abac5 | 541 | struct ieee80211_hdr *hdr, |
0e7690f1 | 542 | u8 std_id) |
fd4abac5 | 543 | { |
fd7c8a40 | 544 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
545 | __le32 tx_flags = tx_cmd->tx_flags; |
546 | ||
547 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 548 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 549 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 550 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 551 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 552 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
553 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
554 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
555 | } else { | |
556 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
557 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
558 | } | |
559 | ||
fd7c8a40 | 560 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
561 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
562 | ||
563 | ||
564 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 565 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
566 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
567 | ||
fd7c8a40 HH |
568 | if (ieee80211_is_data_qos(fc)) { |
569 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
570 | tx_cmd->tid_tspec = qc[0] & 0xf; |
571 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
572 | } else { | |
573 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
574 | } | |
575 | ||
a326a5d0 | 576 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
fd4abac5 TW |
577 | |
578 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
579 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
580 | ||
581 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
582 | if (ieee80211_is_mgmt(fc)) { |
583 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
584 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
585 | else | |
586 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
587 | } else { | |
588 | tx_cmd->timeout.pm_frame_timeout = 0; | |
589 | } | |
590 | ||
591 | tx_cmd->driver_txop = 0; | |
592 | tx_cmd->tx_flags = tx_flags; | |
593 | tx_cmd->next_frame_len = 0; | |
594 | } | |
595 | ||
596 | #define RTS_HCCA_RETRY_LIMIT 3 | |
597 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
598 | ||
599 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
600 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 601 | struct ieee80211_tx_info *info, |
b58ef214 | 602 | __le16 fc, int is_hcca) |
fd4abac5 | 603 | { |
b58ef214 | 604 | u32 rate_flags; |
76eff18b | 605 | int rate_idx; |
b58ef214 DH |
606 | u8 rts_retry_limit; |
607 | u8 data_retry_limit; | |
fd4abac5 | 608 | u8 rate_plcp; |
2e92e6f2 | 609 | |
b58ef214 | 610 | /* Set retry limit on DATA packets and Probe Responses*/ |
1f0436f4 | 611 | if (ieee80211_is_probe_resp(fc)) |
b58ef214 DH |
612 | data_retry_limit = 3; |
613 | else | |
614 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
615 | tx_cmd->data_retry_limit = data_retry_limit; | |
fd4abac5 | 616 | |
b58ef214 DH |
617 | /* Set retry limit on RTS packets */ |
618 | rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT : | |
619 | RTS_DFAULT_RETRY_LIMIT; | |
620 | if (data_retry_limit < rts_retry_limit) | |
621 | rts_retry_limit = data_retry_limit; | |
622 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
fd4abac5 | 623 | |
b58ef214 DH |
624 | /* DATA packets will use the uCode station table for rate/antenna |
625 | * selection */ | |
fd4abac5 TW |
626 | if (ieee80211_is_data(fc)) { |
627 | tx_cmd->initial_rate_index = 0; | |
628 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
b58ef214 DH |
629 | return; |
630 | } | |
631 | ||
632 | /** | |
633 | * If the current TX rate stored in mac80211 has the MCS bit set, it's | |
634 | * not really a TX rate. Thus, we use the lowest supported rate for | |
635 | * this band. Also use the lowest supported rate if the stored rate | |
636 | * index is invalid. | |
637 | */ | |
638 | rate_idx = info->control.rates[0].idx; | |
639 | if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS || | |
640 | (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY)) | |
641 | rate_idx = rate_lowest_index(&priv->bands[info->band], | |
642 | info->control.sta); | |
643 | /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ | |
644 | if (info->band == IEEE80211_BAND_5GHZ) | |
645 | rate_idx += IWL_FIRST_OFDM_RATE; | |
646 | /* Get PLCP rate for tx_cmd->rate_n_flags */ | |
647 | rate_plcp = iwl_rates[rate_idx].plcp; | |
648 | /* Zero out flags for this packet */ | |
649 | rate_flags = 0; | |
fd4abac5 | 650 | |
b58ef214 DH |
651 | /* Set CCK flag as needed */ |
652 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
653 | rate_flags |= RATE_MCS_CCK_MSK; | |
654 | ||
655 | /* Set up RTS and CTS flags for certain packets */ | |
656 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
657 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
658 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
659 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
660 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
661 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { | |
662 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
663 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
664 | } | |
665 | break; | |
666 | default: | |
667 | break; | |
fd4abac5 TW |
668 | } |
669 | ||
b58ef214 DH |
670 | /* Set up antennas */ |
671 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); | |
672 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
673 | ||
674 | /* Set the rate in the TX cmd */ | |
e7d326ac | 675 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
676 | } |
677 | ||
678 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 679 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
680 | struct iwl_tx_cmd *tx_cmd, |
681 | struct sk_buff *skb_frag, | |
682 | int sta_id) | |
683 | { | |
e039fa4a | 684 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 685 | |
ccc038ab | 686 | switch (keyconf->alg) { |
fd4abac5 TW |
687 | case ALG_CCMP: |
688 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 689 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 690 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 691 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
e1623446 | 692 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
fd4abac5 TW |
693 | break; |
694 | ||
695 | case ALG_TKIP: | |
696 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 697 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 | 698 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
e1623446 | 699 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); |
fd4abac5 TW |
700 | break; |
701 | ||
702 | case ALG_WEP: | |
fd4abac5 | 703 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
704 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
705 | ||
706 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
707 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
708 | ||
709 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 | 710 | |
e1623446 | 711 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
ccc038ab | 712 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
713 | break; |
714 | ||
715 | default: | |
978785a3 | 716 | IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
717 | break; |
718 | } | |
719 | } | |
720 | ||
fd4abac5 TW |
721 | /* |
722 | * start REPLY_TX command process | |
723 | */ | |
e039fa4a | 724 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
725 | { |
726 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 727 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
6ab10ff8 JB |
728 | struct ieee80211_sta *sta = info->control.sta; |
729 | struct iwl_station_priv *sta_priv = NULL; | |
f3674227 TW |
730 | struct iwl_tx_queue *txq; |
731 | struct iwl_queue *q; | |
c2acea8e JB |
732 | struct iwl_device_cmd *out_cmd; |
733 | struct iwl_cmd_meta *out_meta; | |
f3674227 TW |
734 | struct iwl_tx_cmd *tx_cmd; |
735 | int swq_id, txq_id; | |
fd4abac5 TW |
736 | dma_addr_t phys_addr; |
737 | dma_addr_t txcmd_phys; | |
738 | dma_addr_t scratch_phys; | |
be1a71a1 | 739 | u16 len, len_org, firstlen, secondlen; |
fd4abac5 | 740 | u16 seq_number = 0; |
fd7c8a40 | 741 | __le16 fc; |
0e7690f1 | 742 | u8 hdr_len; |
f3674227 | 743 | u8 sta_id; |
fd4abac5 TW |
744 | u8 wait_write_ptr = 0; |
745 | u8 tid = 0; | |
746 | u8 *qc = NULL; | |
747 | unsigned long flags; | |
748 | int ret; | |
749 | ||
750 | spin_lock_irqsave(&priv->lock, flags); | |
751 | if (iwl_is_rfkill(priv)) { | |
e1623446 | 752 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
fd4abac5 TW |
753 | goto drop_unlock; |
754 | } | |
755 | ||
fd7c8a40 | 756 | fc = hdr->frame_control; |
fd4abac5 TW |
757 | |
758 | #ifdef CONFIG_IWLWIFI_DEBUG | |
759 | if (ieee80211_is_auth(fc)) | |
e1623446 | 760 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 761 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 762 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 763 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 764 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
fd4abac5 TW |
765 | #endif |
766 | ||
aa065263 | 767 | /* drop all non-injected data frame if we are not associated */ |
fd7c8a40 | 768 | if (ieee80211_is_data(fc) && |
aa065263 | 769 | !(info->flags & IEEE80211_TX_CTL_INJECTED) && |
d10c4ec8 | 770 | (!iwl_is_associated(priv) || |
05c914fe | 771 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) || |
d10c4ec8 | 772 | !priv->assoc_station_added)) { |
e1623446 | 773 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
fd4abac5 TW |
774 | goto drop_unlock; |
775 | } | |
776 | ||
7294ec95 | 777 | hdr_len = ieee80211_hdrlen(fc); |
fd4abac5 TW |
778 | |
779 | /* Find (or create) index into station table for destination station */ | |
aa065263 GS |
780 | if (info->flags & IEEE80211_TX_CTL_INJECTED) |
781 | sta_id = priv->hw_params.bcast_sta_id; | |
782 | else | |
783 | sta_id = iwl_get_sta_id(priv, hdr); | |
fd4abac5 | 784 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 785 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 786 | hdr->addr1); |
3995bd93 | 787 | goto drop_unlock; |
fd4abac5 TW |
788 | } |
789 | ||
e1623446 | 790 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); |
fd4abac5 | 791 | |
6ab10ff8 JB |
792 | if (sta) |
793 | sta_priv = (void *)sta->drv_priv; | |
794 | ||
795 | if (sta_priv && sta_id != priv->hw_params.bcast_sta_id && | |
796 | sta_priv->asleep) { | |
797 | WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)); | |
798 | /* | |
799 | * This sends an asynchronous command to the device, | |
800 | * but we can rely on it being processed before the | |
801 | * next frame is processed -- and the next frame to | |
802 | * this station is the one that will consume this | |
803 | * counter. | |
804 | * For now set the counter to just 1 since we do not | |
805 | * support uAPSD yet. | |
806 | */ | |
807 | iwl_sta_modify_sleep_tx_count(priv, sta_id, 1); | |
808 | } | |
809 | ||
45af8195 | 810 | txq_id = skb_get_queue_mapping(skb); |
fd7c8a40 HH |
811 | if (ieee80211_is_data_qos(fc)) { |
812 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 813 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
814 | if (unlikely(tid >= MAX_TID_COUNT)) |
815 | goto drop_unlock; | |
f3674227 TW |
816 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
817 | seq_number &= IEEE80211_SCTL_SEQ; | |
818 | hdr->seq_ctrl = hdr->seq_ctrl & | |
c1b4aa3f | 819 | cpu_to_le16(IEEE80211_SCTL_FRAG); |
f3674227 | 820 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
fd4abac5 | 821 | seq_number += 0x10; |
fd4abac5 | 822 | /* aggregation is on for this <sta,tid> */ |
45af8195 | 823 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 824 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
fd4abac5 TW |
825 | } |
826 | ||
fd4abac5 | 827 | txq = &priv->txq[txq_id]; |
45af8195 | 828 | swq_id = txq->swq_id; |
fd4abac5 TW |
829 | q = &txq->q; |
830 | ||
3995bd93 JB |
831 | if (unlikely(iwl_queue_space(q) < q->high_mark)) |
832 | goto drop_unlock; | |
833 | ||
834 | if (ieee80211_is_data_qos(fc)) | |
835 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 | 836 | |
fd4abac5 TW |
837 | /* Set up driver data for this TFD */ |
838 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
839 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
840 | |
841 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b88b15df | 842 | out_cmd = txq->cmd[q->write_ptr]; |
c2acea8e | 843 | out_meta = &txq->meta[q->write_ptr]; |
fd4abac5 TW |
844 | tx_cmd = &out_cmd->cmd.tx; |
845 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
846 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
847 | ||
848 | /* | |
849 | * Set up the Tx-command (not MAC!) header. | |
850 | * Store the chosen Tx queue and TFD index within the sequence field; | |
851 | * after Tx, uCode's Tx response will return this value so driver can | |
852 | * locate the frame within the tx queue and do post-tx processing. | |
853 | */ | |
854 | out_cmd->hdr.cmd = REPLY_TX; | |
855 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
856 | INDEX_TO_SEQ(q->write_ptr))); | |
857 | ||
858 | /* Copy MAC header from skb into command buffer */ | |
859 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
860 | ||
df833b1d RC |
861 | |
862 | /* Total # bytes to be transmitted */ | |
863 | len = (u16)skb->len; | |
864 | tx_cmd->len = cpu_to_le16(len); | |
865 | ||
866 | if (info->control.hw_key) | |
867 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
868 | ||
869 | /* TODO need this for burst mode later on */ | |
870 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id); | |
20594eb0 | 871 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
df833b1d RC |
872 | |
873 | /* set is_hcca to 0; it probably will never be implemented */ | |
b58ef214 | 874 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0); |
df833b1d | 875 | |
22fdf3c9 | 876 | iwl_update_stats(priv, true, fc, len); |
fd4abac5 TW |
877 | /* |
878 | * Use the first empty entry in this queue's command buffer array | |
879 | * to contain the Tx command and MAC header concatenated together | |
880 | * (payload data will be in another buffer). | |
881 | * Size of this varies, due to varying MAC header length. | |
882 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
883 | * of the MAC header (device reads on dword boundaries). | |
884 | * We'll tell device about this padding later. | |
885 | */ | |
886 | len = sizeof(struct iwl_tx_cmd) + | |
887 | sizeof(struct iwl_cmd_header) + hdr_len; | |
888 | ||
889 | len_org = len; | |
be1a71a1 | 890 | firstlen = len = (len + 3) & ~3; |
fd4abac5 TW |
891 | |
892 | if (len_org != len) | |
893 | len_org = 1; | |
894 | else | |
895 | len_org = 0; | |
896 | ||
df833b1d RC |
897 | /* Tell NIC about any 2-byte padding after MAC header */ |
898 | if (len_org) | |
899 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
900 | ||
fd4abac5 TW |
901 | /* Physical address of this Tx command's header (not MAC header!), |
902 | * within command buffer array. */ | |
499b1883 | 903 | txcmd_phys = pci_map_single(priv->pci_dev, |
df833b1d | 904 | &out_cmd->hdr, len, |
96891cee | 905 | PCI_DMA_BIDIRECTIONAL); |
c2acea8e JB |
906 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
907 | pci_unmap_len_set(out_meta, len, len); | |
fd4abac5 TW |
908 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
909 | * first entry */ | |
7aaa1d79 SO |
910 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
911 | txcmd_phys, len, 1, 0); | |
fd4abac5 | 912 | |
df833b1d RC |
913 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
914 | txq->need_update = 1; | |
915 | if (qc) | |
916 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
917 | } else { | |
918 | wait_write_ptr = 1; | |
919 | txq->need_update = 0; | |
920 | } | |
fd4abac5 TW |
921 | |
922 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
923 | * if any (802.11 null frames have no payload). */ | |
be1a71a1 | 924 | secondlen = len = skb->len - hdr_len; |
fd4abac5 TW |
925 | if (len) { |
926 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
927 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
928 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
929 | phys_addr, len, | |
930 | 0, 0); | |
fd4abac5 TW |
931 | } |
932 | ||
fd4abac5 | 933 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
df833b1d RC |
934 | offsetof(struct iwl_tx_cmd, scratch); |
935 | ||
936 | len = sizeof(struct iwl_tx_cmd) + | |
937 | sizeof(struct iwl_cmd_header) + hdr_len; | |
938 | /* take back ownership of DMA buffer to enable update */ | |
939 | pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys, | |
940 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 941 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
499b1883 | 942 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); |
fd4abac5 | 943 | |
d2ee9cd2 RC |
944 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", |
945 | le16_to_cpu(out_cmd->hdr.sequence)); | |
946 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags)); | |
3d816c77 RC |
947 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
948 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
fd4abac5 TW |
949 | |
950 | /* Set up entry for this TFD in Tx byte-count array */ | |
7b80ece4 RC |
951 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
952 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, | |
df833b1d RC |
953 | le16_to_cpu(tx_cmd->len)); |
954 | ||
955 | pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys, | |
956 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 957 | |
be1a71a1 JB |
958 | trace_iwlwifi_dev_tx(priv, |
959 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
960 | sizeof(struct iwl_tfd), | |
961 | &out_cmd->hdr, firstlen, | |
962 | skb->data + hdr_len, secondlen); | |
963 | ||
fd4abac5 TW |
964 | /* Tell device the write index *just past* this latest filled TFD */ |
965 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
966 | ret = iwl_txq_update_write_ptr(priv, txq); | |
967 | spin_unlock_irqrestore(&priv->lock, flags); | |
968 | ||
6ab10ff8 JB |
969 | /* |
970 | * At this point the frame is "transmitted" successfully | |
971 | * and we will get a TX status notification eventually, | |
972 | * regardless of the value of ret. "ret" only indicates | |
973 | * whether or not we should update the write pointer. | |
974 | */ | |
975 | ||
976 | /* avoid atomic ops if it isn't an associated client */ | |
977 | if (sta_priv && sta_priv->client) | |
978 | atomic_inc(&sta_priv->pending_frames); | |
979 | ||
fd4abac5 TW |
980 | if (ret) |
981 | return ret; | |
982 | ||
143b09ef | 983 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
fd4abac5 TW |
984 | if (wait_write_ptr) { |
985 | spin_lock_irqsave(&priv->lock, flags); | |
986 | txq->need_update = 1; | |
987 | iwl_txq_update_write_ptr(priv, txq); | |
988 | spin_unlock_irqrestore(&priv->lock, flags); | |
143b09ef | 989 | } else { |
e4e72fb4 | 990 | iwl_stop_queue(priv, txq->swq_id); |
fd4abac5 | 991 | } |
fd4abac5 TW |
992 | } |
993 | ||
994 | return 0; | |
995 | ||
996 | drop_unlock: | |
997 | spin_unlock_irqrestore(&priv->lock, flags); | |
fd4abac5 TW |
998 | return -1; |
999 | } | |
1000 | EXPORT_SYMBOL(iwl_tx_skb); | |
1001 | ||
1002 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
1003 | ||
1004 | /** | |
1005 | * iwl_enqueue_hcmd - enqueue a uCode command | |
1006 | * @priv: device private data point | |
1007 | * @cmd: a point to the ucode command structure | |
1008 | * | |
1009 | * The function returns < 0 values to indicate the operation is | |
1010 | * failed. On success, it turns the index (> 0) of command in the | |
1011 | * command queue. | |
1012 | */ | |
1013 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
1014 | { | |
1015 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
1016 | struct iwl_queue *q = &txq->q; | |
c2acea8e JB |
1017 | struct iwl_device_cmd *out_cmd; |
1018 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 1019 | dma_addr_t phys_addr; |
fd4abac5 | 1020 | unsigned long flags; |
f3674227 TW |
1021 | int len, ret; |
1022 | u32 idx; | |
1023 | u16 fix_size; | |
fd4abac5 TW |
1024 | |
1025 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
1026 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
1027 | ||
1028 | /* If any of the command structures end up being larger than | |
1029 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
1030 | * we will need to increase the size of the TFD entries */ | |
1031 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
c2acea8e | 1032 | !(cmd->flags & CMD_SIZE_HUGE)); |
fd4abac5 | 1033 | |
7812b167 | 1034 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
1035 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
1036 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
1037 | return -EIO; |
1038 | } | |
1039 | ||
c2acea8e | 1040 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
2d237f71 | 1041 | IWL_ERR(priv, "No space in command queue\n"); |
7812b167 WYG |
1042 | if (iwl_within_ct_kill_margin(priv)) |
1043 | iwl_tt_enter_ct_kill(priv); | |
1044 | else { | |
1045 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); | |
1046 | queue_work(priv->workqueue, &priv->restart); | |
1047 | } | |
fd4abac5 TW |
1048 | return -ENOSPC; |
1049 | } | |
1050 | ||
1051 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
1052 | ||
c2acea8e | 1053 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 1054 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
1055 | out_meta = &txq->meta[idx]; |
1056 | ||
8ce73f3a | 1057 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1058 | out_meta->flags = cmd->flags; |
1059 | if (cmd->flags & CMD_WANT_SKB) | |
1060 | out_meta->source = cmd; | |
1061 | if (cmd->flags & CMD_ASYNC) | |
1062 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
1063 | |
1064 | out_cmd->hdr.cmd = cmd->id; | |
fd4abac5 TW |
1065 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
1066 | ||
1067 | /* At this point, the out_cmd now has all of the incoming cmd | |
1068 | * information */ | |
1069 | ||
1070 | out_cmd->hdr.flags = 0; | |
1071 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
1072 | INDEX_TO_SEQ(q->write_ptr)); | |
c2acea8e | 1073 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 1074 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
c2acea8e | 1075 | len = sizeof(struct iwl_device_cmd); |
df833b1d | 1076 | len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0; |
499b1883 | 1077 | |
fd4abac5 | 1078 | |
ded2ae7c EK |
1079 | #ifdef CONFIG_IWLWIFI_DEBUG |
1080 | switch (out_cmd->hdr.cmd) { | |
1081 | case REPLY_TX_LINK_QUALITY_CMD: | |
1082 | case SENSITIVITY_CMD: | |
e1623446 | 1083 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1084 | "%d bytes at %d[%d]:%d\n", |
1085 | get_cmd_string(out_cmd->hdr.cmd), | |
1086 | out_cmd->hdr.cmd, | |
1087 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1088 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1089 | break; | |
1090 | default: | |
e1623446 | 1091 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1092 | "%d bytes at %d[%d]:%d\n", |
1093 | get_cmd_string(out_cmd->hdr.cmd), | |
1094 | out_cmd->hdr.cmd, | |
1095 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1096 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1097 | } | |
1098 | #endif | |
fd4abac5 TW |
1099 | txq->need_update = 1; |
1100 | ||
518099a8 SO |
1101 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) |
1102 | /* Set up entry in queue's byte count circular buffer */ | |
1103 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
fd4abac5 | 1104 | |
df833b1d RC |
1105 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
1106 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
c2acea8e JB |
1107 | pci_unmap_addr_set(out_meta, mapping, phys_addr); |
1108 | pci_unmap_len_set(out_meta, len, fix_size); | |
df833b1d | 1109 | |
be1a71a1 JB |
1110 | trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); |
1111 | ||
df833b1d RC |
1112 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
1113 | phys_addr, fix_size, 1, | |
1114 | U32_PAD(cmd->len)); | |
1115 | ||
fd4abac5 TW |
1116 | /* Increment and update queue's write index */ |
1117 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1118 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1119 | ||
1120 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1121 | return ret ? ret : idx; | |
1122 | } | |
1123 | ||
6ab10ff8 JB |
1124 | static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb) |
1125 | { | |
1126 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1127 | struct ieee80211_sta *sta; | |
1128 | struct iwl_station_priv *sta_priv; | |
1129 | ||
1130 | sta = ieee80211_find_sta(priv->vif, hdr->addr1); | |
1131 | if (sta) { | |
1132 | sta_priv = (void *)sta->drv_priv; | |
1133 | /* avoid atomic ops if this isn't a client */ | |
1134 | if (sta_priv->client && | |
1135 | atomic_dec_return(&sta_priv->pending_frames) == 0) | |
1136 | ieee80211_sta_block_awake(priv->hw, sta, false); | |
1137 | } | |
1138 | ||
1139 | ieee80211_tx_status_irqsafe(priv->hw, skb); | |
1140 | } | |
1141 | ||
17b88929 TW |
1142 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1143 | { | |
1144 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1145 | struct iwl_queue *q = &txq->q; | |
1146 | struct iwl_tx_info *tx_info; | |
1147 | int nfreed = 0; | |
a120e912 | 1148 | struct ieee80211_hdr *hdr; |
17b88929 TW |
1149 | |
1150 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
15b1687c | 1151 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 TW |
1152 | "is out of range [0-%d] %d %d.\n", txq_id, |
1153 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1154 | return 0; | |
1155 | } | |
1156 | ||
499b1883 TW |
1157 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
1158 | q->read_ptr != index; | |
1159 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 TW |
1160 | |
1161 | tx_info = &txq->txb[txq->q.read_ptr]; | |
6ab10ff8 | 1162 | iwl_tx_status(priv, tx_info->skb[0]); |
a120e912 SG |
1163 | |
1164 | hdr = (struct ieee80211_hdr *)tx_info->skb[0]->data; | |
1165 | if (hdr && ieee80211_is_data_qos(hdr->frame_control)) | |
1166 | nfreed++; | |
17b88929 | 1167 | tx_info->skb[0] = NULL; |
17b88929 | 1168 | |
972cf447 TW |
1169 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1170 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1171 | ||
7aaa1d79 | 1172 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
17b88929 TW |
1173 | } |
1174 | return nfreed; | |
1175 | } | |
1176 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1177 | ||
1178 | ||
1179 | /** | |
1180 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1181 | * | |
1182 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1183 | * need to be reclaimed. As result, some free space forms. If there is | |
1184 | * enough free space (> low mark), wake the stack that feeds us. | |
1185 | */ | |
499b1883 TW |
1186 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
1187 | int idx, int cmd_idx) | |
17b88929 TW |
1188 | { |
1189 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1190 | struct iwl_queue *q = &txq->q; | |
1191 | int nfreed = 0; | |
1192 | ||
499b1883 | 1193 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 1194 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 1195 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 1196 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
1197 | return; |
1198 | } | |
1199 | ||
499b1883 TW |
1200 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1201 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 1202 | |
499b1883 | 1203 | if (nfreed++ > 0) { |
15b1687c | 1204 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 TW |
1205 | q->write_ptr, q->read_ptr); |
1206 | queue_work(priv->workqueue, &priv->restart); | |
1207 | } | |
da99c4b6 | 1208 | |
17b88929 TW |
1209 | } |
1210 | } | |
1211 | ||
1212 | /** | |
1213 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1214 | * @rxb: Rx buffer to reclaim | |
1215 | * | |
1216 | * If an Rx buffer has an async callback associated with it the callback | |
1217 | * will be executed. The attached skb (if present) will only be freed | |
1218 | * if the callback returns 1 | |
1219 | */ | |
1220 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1221 | { | |
2f301227 | 1222 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1223 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1224 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1225 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1226 | int cmd_index; |
9734cb23 | 1227 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
1228 | struct iwl_device_cmd *cmd; |
1229 | struct iwl_cmd_meta *meta; | |
17b88929 TW |
1230 | |
1231 | /* If a Tx command is being handled and it isn't in the actual | |
1232 | * command queue then there a command routing bug has been introduced | |
1233 | * in the queue management code. */ | |
55d6a3cd | 1234 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
01ef9323 WT |
1235 | "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", |
1236 | txq_id, sequence, | |
1237 | priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, | |
1238 | priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { | |
ec741164 | 1239 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 1240 | return; |
01ef9323 | 1241 | } |
17b88929 TW |
1242 | |
1243 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
da99c4b6 | 1244 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; |
c2acea8e | 1245 | meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index]; |
17b88929 | 1246 | |
c33de625 RC |
1247 | pci_unmap_single(priv->pci_dev, |
1248 | pci_unmap_addr(meta, mapping), | |
1249 | pci_unmap_len(meta, len), | |
1250 | PCI_DMA_BIDIRECTIONAL); | |
1251 | ||
17b88929 | 1252 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1253 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
1254 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
1255 | rxb->page = NULL; | |
5696aea6 | 1256 | } else if (meta->callback) |
2f301227 | 1257 | meta->callback(priv, cmd, pkt); |
17b88929 | 1258 | |
499b1883 | 1259 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 1260 | |
c2acea8e | 1261 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 TW |
1262 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
1263 | wake_up_interruptible(&priv->wait_command_queue); | |
1264 | } | |
1265 | } | |
1266 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1267 | ||
30e553e3 TW |
1268 | /* |
1269 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1270 | * Called only when finding queue for aggregation. | |
1271 | * Should never return anything < 7, because they should already | |
1272 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1273 | */ | |
1274 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1275 | { | |
1276 | int txq_id; | |
1277 | ||
1278 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1279 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1280 | return txq_id; | |
1281 | return -1; | |
1282 | } | |
1283 | ||
1284 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1285 | { | |
1286 | int sta_id; | |
1287 | int tx_fifo; | |
1288 | int txq_id; | |
1289 | int ret; | |
1290 | unsigned long flags; | |
1291 | struct iwl_tid_data *tid_data; | |
30e553e3 TW |
1292 | |
1293 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1294 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1295 | else | |
1296 | return -EINVAL; | |
1297 | ||
39aadf8c | 1298 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", |
e174961c | 1299 | __func__, ra, tid); |
30e553e3 TW |
1300 | |
1301 | sta_id = iwl_find_station(priv, ra); | |
3eb92969 WYG |
1302 | if (sta_id == IWL_INVALID_STATION) { |
1303 | IWL_ERR(priv, "Start AGG on invalid station\n"); | |
30e553e3 | 1304 | return -ENXIO; |
3eb92969 | 1305 | } |
082e708a RK |
1306 | if (unlikely(tid >= MAX_TID_COUNT)) |
1307 | return -EINVAL; | |
30e553e3 TW |
1308 | |
1309 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
15b1687c | 1310 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); |
30e553e3 TW |
1311 | return -ENXIO; |
1312 | } | |
1313 | ||
1314 | txq_id = iwl_txq_ctx_activate_free(priv); | |
3eb92969 WYG |
1315 | if (txq_id == -1) { |
1316 | IWL_ERR(priv, "No free aggregation queue available\n"); | |
30e553e3 | 1317 | return -ENXIO; |
3eb92969 | 1318 | } |
30e553e3 TW |
1319 | |
1320 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1321 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1322 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1323 | tid_data->agg.txq_id = txq_id; | |
45af8195 | 1324 | priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id); |
30e553e3 TW |
1325 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1326 | ||
1327 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1328 | sta_id, tid, *ssn); | |
1329 | if (ret) | |
1330 | return ret; | |
1331 | ||
1332 | if (tid_data->tfds_in_queue == 0) { | |
3eb92969 | 1333 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 | 1334 | tid_data->agg.state = IWL_AGG_ON; |
c951ad35 | 1335 | ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid); |
30e553e3 | 1336 | } else { |
e1623446 | 1337 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", |
30e553e3 TW |
1338 | tid_data->tfds_in_queue); |
1339 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1340 | } | |
1341 | return ret; | |
1342 | } | |
1343 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1344 | ||
1345 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1346 | { | |
1347 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1348 | struct iwl_tid_data *tid_data; | |
1349 | int ret, write_ptr, read_ptr; | |
1350 | unsigned long flags; | |
30e553e3 TW |
1351 | |
1352 | if (!ra) { | |
15b1687c | 1353 | IWL_ERR(priv, "ra = NULL\n"); |
30e553e3 TW |
1354 | return -EINVAL; |
1355 | } | |
1356 | ||
e6a6cf4c RC |
1357 | if (unlikely(tid >= MAX_TID_COUNT)) |
1358 | return -EINVAL; | |
1359 | ||
30e553e3 TW |
1360 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) |
1361 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1362 | else | |
1363 | return -EINVAL; | |
1364 | ||
1365 | sta_id = iwl_find_station(priv, ra); | |
1366 | ||
a2f1cbeb WYG |
1367 | if (sta_id == IWL_INVALID_STATION) { |
1368 | IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid); | |
30e553e3 | 1369 | return -ENXIO; |
a2f1cbeb | 1370 | } |
30e553e3 | 1371 | |
827d42c9 JB |
1372 | if (priv->stations[sta_id].tid[tid].agg.state == |
1373 | IWL_EMPTYING_HW_QUEUE_ADDBA) { | |
1374 | IWL_DEBUG_HT(priv, "AGG stop before setup done\n"); | |
9b1cb21c | 1375 | ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid); |
827d42c9 JB |
1376 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1377 | return 0; | |
1378 | } | |
1379 | ||
30e553e3 | 1380 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) |
827d42c9 | 1381 | IWL_WARN(priv, "Stopping AGG while state not ON or starting\n"); |
30e553e3 TW |
1382 | |
1383 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1384 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1385 | txq_id = tid_data->agg.txq_id; | |
1386 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1387 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1388 | ||
1389 | /* The queue is not empty */ | |
1390 | if (write_ptr != read_ptr) { | |
e1623446 | 1391 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); |
30e553e3 TW |
1392 | priv->stations[sta_id].tid[tid].agg.state = |
1393 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1394 | return 0; | |
1395 | } | |
1396 | ||
e1623446 | 1397 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1398 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1399 | ||
1400 | spin_lock_irqsave(&priv->lock, flags); | |
1401 | ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1402 | tx_fifo_id); | |
1403 | spin_unlock_irqrestore(&priv->lock, flags); | |
1404 | ||
1405 | if (ret) | |
1406 | return ret; | |
1407 | ||
c951ad35 | 1408 | ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid); |
30e553e3 TW |
1409 | |
1410 | return 0; | |
1411 | } | |
1412 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1413 | ||
1414 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1415 | { | |
1416 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1417 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1418 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1419 | ||
1420 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1421 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1422 | /* We are reclaiming the last packet of the */ | |
1423 | /* aggregated HW queue */ | |
3fd07a1e TW |
1424 | if ((txq_id == tid_data->agg.txq_id) && |
1425 | (q->read_ptr == q->write_ptr)) { | |
30e553e3 TW |
1426 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); |
1427 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
e1623446 | 1428 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
30e553e3 TW |
1429 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, |
1430 | ssn, tx_fifo); | |
1431 | tid_data->agg.state = IWL_AGG_OFF; | |
c951ad35 | 1432 | ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid); |
30e553e3 TW |
1433 | } |
1434 | break; | |
1435 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1436 | /* We are reclaiming the last packet of the queue */ | |
1437 | if (tid_data->tfds_in_queue == 0) { | |
e1623446 | 1438 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); |
30e553e3 | 1439 | tid_data->agg.state = IWL_AGG_ON; |
c951ad35 | 1440 | ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid); |
30e553e3 TW |
1441 | } |
1442 | break; | |
1443 | } | |
1444 | return 0; | |
1445 | } | |
1446 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1447 | |
653fa4a0 EG |
1448 | /** |
1449 | * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1450 | * | |
1451 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1452 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1453 | */ | |
1454 | static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1455 | struct iwl_ht_agg *agg, | |
1456 | struct iwl_compressed_ba_resp *ba_resp) | |
1457 | ||
1458 | { | |
1459 | int i, sh, ack; | |
1460 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1461 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1462 | u64 bitmap; | |
1463 | int successes = 0; | |
1464 | struct ieee80211_tx_info *info; | |
1465 | ||
1466 | if (unlikely(!agg->wait_for_ba)) { | |
15b1687c | 1467 | IWL_ERR(priv, "Received BA when not expected\n"); |
653fa4a0 EG |
1468 | return -EINVAL; |
1469 | } | |
1470 | ||
1471 | /* Mark that the expected block-ack response arrived */ | |
1472 | agg->wait_for_ba = 0; | |
e1623446 | 1473 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
653fa4a0 EG |
1474 | |
1475 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
3fd07a1e | 1476 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); |
653fa4a0 EG |
1477 | if (sh < 0) /* tbw something is wrong with indices */ |
1478 | sh += 0x100; | |
1479 | ||
1480 | /* don't use 64-bit values for now */ | |
1481 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1482 | ||
1483 | if (agg->frame_count > (64 - sh)) { | |
e1623446 | 1484 | IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size"); |
653fa4a0 EG |
1485 | return -1; |
1486 | } | |
1487 | ||
1488 | /* check for success or failure according to the | |
1489 | * transmitted bitmap and block-ack bitmap */ | |
1490 | bitmap &= agg->bitmap; | |
1491 | ||
1492 | /* For each frame attempted in aggregation, | |
1493 | * update driver's record of tx frame's status. */ | |
1494 | for (i = 0; i < agg->frame_count ; i++) { | |
4aa41f12 | 1495 | ack = bitmap & (1ULL << i); |
653fa4a0 | 1496 | successes += !!ack; |
e1623446 | 1497 | IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n", |
c3056065 | 1498 | ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff, |
653fa4a0 EG |
1499 | agg->start_idx + i); |
1500 | } | |
1501 | ||
1502 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]); | |
1503 | memset(&info->status, 0, sizeof(info->status)); | |
91a55ae6 | 1504 | info->flags |= IEEE80211_TX_STAT_ACK; |
653fa4a0 EG |
1505 | info->flags |= IEEE80211_TX_STAT_AMPDU; |
1506 | info->status.ampdu_ack_map = successes; | |
1507 | info->status.ampdu_ack_len = agg->frame_count; | |
1508 | iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info); | |
1509 | ||
e1623446 | 1510 | IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap); |
653fa4a0 EG |
1511 | |
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | /** | |
1516 | * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1517 | * | |
1518 | * Handles block-acknowledge notification from device, which reports success | |
1519 | * of frames sent via aggregation. | |
1520 | */ | |
1521 | void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1522 | struct iwl_rx_mem_buffer *rxb) | |
1523 | { | |
2f301227 | 1524 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
653fa4a0 | 1525 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; |
653fa4a0 EG |
1526 | struct iwl_tx_queue *txq = NULL; |
1527 | struct iwl_ht_agg *agg; | |
3fd07a1e TW |
1528 | int index; |
1529 | int sta_id; | |
1530 | int tid; | |
653fa4a0 EG |
1531 | |
1532 | /* "flow" corresponds to Tx queue */ | |
1533 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1534 | ||
1535 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1536 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1537 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1538 | ||
1539 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
15b1687c WT |
1540 | IWL_ERR(priv, |
1541 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
653fa4a0 EG |
1542 | return; |
1543 | } | |
1544 | ||
1545 | txq = &priv->txq[scd_flow]; | |
3fd07a1e TW |
1546 | sta_id = ba_resp->sta_id; |
1547 | tid = ba_resp->tid; | |
1548 | agg = &priv->stations[sta_id].tid[tid].agg; | |
653fa4a0 EG |
1549 | |
1550 | /* Find index just before block-ack window */ | |
1551 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1552 | ||
1553 | /* TODO: Need to get this copy more safely - now good for debug */ | |
1554 | ||
e1623446 | 1555 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " |
653fa4a0 EG |
1556 | "sta_id = %d\n", |
1557 | agg->wait_for_ba, | |
e174961c | 1558 | (u8 *) &ba_resp->sta_addr_lo32, |
653fa4a0 | 1559 | ba_resp->sta_id); |
e1623446 | 1560 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " |
653fa4a0 EG |
1561 | "%d, scd_ssn = %d\n", |
1562 | ba_resp->tid, | |
1563 | ba_resp->seq_ctl, | |
1564 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1565 | ba_resp->scd_flow, | |
1566 | ba_resp->scd_ssn); | |
e1623446 | 1567 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n", |
653fa4a0 EG |
1568 | agg->start_idx, |
1569 | (unsigned long long)agg->bitmap); | |
1570 | ||
1571 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1572 | iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1573 | ||
1574 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1575 | * block-ack window (we assume that they've been successfully | |
1576 | * transmitted ... if not, it's too late anyway). */ | |
1577 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1578 | /* calculate mac80211 ampdu sw queue to wake */ | |
653fa4a0 | 1579 | int freed = iwl_tx_queue_reclaim(priv, scd_flow, index); |
a239a8b4 | 1580 | iwl_free_tfds_in_queue(priv, sta_id, tid, freed); |
3fd07a1e TW |
1581 | |
1582 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1583 | priv->mac80211_registered && | |
1584 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
e4e72fb4 | 1585 | iwl_wake_queue(priv, txq->swq_id); |
3fd07a1e TW |
1586 | |
1587 | iwl_txq_check_empty(priv, sta_id, tid, scd_flow); | |
653fa4a0 EG |
1588 | } |
1589 | } | |
1590 | EXPORT_SYMBOL(iwl_rx_reply_compressed_ba); | |
1591 | ||
994d31f7 | 1592 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1593 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
1594 | ||
1595 | const char *iwl_get_tx_fail_reason(u32 status) | |
1596 | { | |
1597 | switch (status & TX_STATUS_MSK) { | |
1598 | case TX_STATUS_SUCCESS: | |
1599 | return "SUCCESS"; | |
1600 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1601 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1602 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1603 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1604 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1605 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1606 | TX_STATUS_ENTRY(DEST_PS); | |
1607 | TX_STATUS_ENTRY(ABORTED); | |
1608 | TX_STATUS_ENTRY(BT_RETRY); | |
1609 | TX_STATUS_ENTRY(STA_INVALID); | |
1610 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1611 | TX_STATUS_ENTRY(TID_DISABLE); | |
1612 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1613 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1614 | TX_STATUS_ENTRY(TX_LOCKED); | |
1615 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1616 | } | |
1617 | ||
1618 | return "UNKNOWN"; | |
1619 | } | |
1620 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1621 | #endif /* CONFIG_IWLWIFI_DEBUG */ |