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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
1053d35f RR |
31 | #include <net/mac80211.h> |
32 | #include "iwl-eeprom.h" | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-sta.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | ||
30e553e3 TW |
39 | static const u16 default_tid_to_tx_fifo[] = { |
40 | IWL_TX_FIFO_AC1, | |
41 | IWL_TX_FIFO_AC0, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC1, | |
44 | IWL_TX_FIFO_AC2, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC3, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_NONE, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_AC3 | |
57 | }; | |
58 | ||
30e553e3 | 59 | |
1053d35f RR |
60 | /** |
61 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
62 | * | |
63 | * Does NOT advance any TFD circular buffer read/write indexes | |
64 | * Does NOT free the TFD itself (which is within circular buffer) | |
65 | */ | |
a33c2f47 | 66 | static int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
1053d35f RR |
67 | { |
68 | struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0]; | |
69 | struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; | |
70 | struct pci_dev *dev = priv->pci_dev; | |
71 | int i; | |
72 | int counter = 0; | |
73 | int index, is_odd; | |
74 | ||
75 | /* Host command buffers stay mapped in memory, nothing to clean */ | |
76 | if (txq->q.id == IWL_CMD_QUEUE_NUM) | |
77 | return 0; | |
78 | ||
79 | /* Sanity check on number of chunks */ | |
80 | counter = IWL_GET_BITS(*bd, num_tbs); | |
81 | if (counter > MAX_NUM_OF_TBS) { | |
82 | IWL_ERROR("Too many chunks: %i\n", counter); | |
83 | /* @todo issue fatal error, it is quite serious situation */ | |
84 | return 0; | |
85 | } | |
86 | ||
87 | /* Unmap chunks, if any. | |
88 | * TFD info for odd chunks is different format than for even chunks. */ | |
89 | for (i = 0; i < counter; i++) { | |
90 | index = i / 2; | |
91 | is_odd = i & 0x1; | |
92 | ||
93 | if (is_odd) | |
94 | pci_unmap_single( | |
95 | dev, | |
96 | IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | | |
97 | (IWL_GET_BITS(bd->pa[index], | |
98 | tb2_addr_hi20) << 16), | |
99 | IWL_GET_BITS(bd->pa[index], tb2_len), | |
100 | PCI_DMA_TODEVICE); | |
101 | ||
102 | else if (i > 0) | |
103 | pci_unmap_single(dev, | |
104 | le32_to_cpu(bd->pa[index].tb1_addr), | |
105 | IWL_GET_BITS(bd->pa[index], tb1_len), | |
106 | PCI_DMA_TODEVICE); | |
107 | ||
108 | /* Free SKB, if any, for this chunk */ | |
109 | if (txq->txb[txq->q.read_ptr].skb[i]) { | |
110 | struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i]; | |
111 | ||
112 | dev_kfree_skb(skb); | |
113 | txq->txb[txq->q.read_ptr].skb[i] = NULL; | |
114 | } | |
115 | } | |
116 | return 0; | |
117 | } | |
1053d35f | 118 | |
a33c2f47 | 119 | static int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, |
fd4abac5 TW |
120 | dma_addr_t addr, u16 len) |
121 | { | |
122 | int index, is_odd; | |
123 | struct iwl_tfd_frame *tfd = ptr; | |
124 | u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs); | |
125 | ||
126 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
73ae98a1 | 127 | if (num_tbs >= MAX_NUM_OF_TBS) { |
fd4abac5 TW |
128 | IWL_ERROR("Error can not send more than %d chunks\n", |
129 | MAX_NUM_OF_TBS); | |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | index = num_tbs / 2; | |
134 | is_odd = num_tbs & 0x1; | |
135 | ||
136 | if (!is_odd) { | |
137 | tfd->pa[index].tb1_addr = cpu_to_le32(addr); | |
138 | IWL_SET_BITS(tfd->pa[index], tb1_addr_hi, | |
139 | iwl_get_dma_hi_address(addr)); | |
140 | IWL_SET_BITS(tfd->pa[index], tb1_len, len); | |
141 | } else { | |
142 | IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16, | |
143 | (u32) (addr & 0xffff)); | |
144 | IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16); | |
145 | IWL_SET_BITS(tfd->pa[index], tb2_len, len); | |
146 | } | |
147 | ||
148 | IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1); | |
149 | ||
150 | return 0; | |
151 | } | |
fd4abac5 TW |
152 | |
153 | /** | |
154 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
155 | */ | |
156 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
157 | { | |
158 | u32 reg = 0; | |
159 | int ret = 0; | |
160 | int txq_id = txq->q.id; | |
161 | ||
162 | if (txq->need_update == 0) | |
163 | return ret; | |
164 | ||
165 | /* if we're trying to save power */ | |
166 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
167 | /* wake up nic if it's powered down ... | |
168 | * uCode will wake up, and interrupt us again, so next | |
169 | * time we'll skip this part. */ | |
170 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
171 | ||
172 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
173 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
174 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
175 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
176 | return ret; | |
177 | } | |
178 | ||
179 | /* restore this queue's parameters in nic hardware. */ | |
180 | ret = iwl_grab_nic_access(priv); | |
181 | if (ret) | |
182 | return ret; | |
183 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
184 | txq->q.write_ptr | (txq_id << 8)); | |
185 | iwl_release_nic_access(priv); | |
186 | ||
187 | /* else not in power-save mode, uCode will never sleep when we're | |
188 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
189 | } else | |
190 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
191 | txq->q.write_ptr | (txq_id << 8)); | |
192 | ||
193 | txq->need_update = 0; | |
194 | ||
195 | return ret; | |
196 | } | |
197 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
198 | ||
199 | ||
1053d35f RR |
200 | /** |
201 | * iwl_tx_queue_free - Deallocate DMA queue. | |
202 | * @txq: Transmit queue to deallocate. | |
203 | * | |
204 | * Empty queue by removing and destroying all BD's. | |
205 | * Free all buffers. | |
206 | * 0-fill, but do not free "txq" descriptor structure. | |
207 | */ | |
da99c4b6 | 208 | static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 209 | { |
da99c4b6 | 210 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 211 | struct iwl_queue *q = &txq->q; |
1053d35f | 212 | struct pci_dev *dev = priv->pci_dev; |
da99c4b6 | 213 | int i, slots_num, len; |
1053d35f RR |
214 | |
215 | if (q->n_bd == 0) | |
216 | return; | |
217 | ||
218 | /* first, empty all BD's */ | |
219 | for (; q->write_ptr != q->read_ptr; | |
220 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
221 | iwl_hw_txq_free_tfd(priv, txq); | |
222 | ||
223 | len = sizeof(struct iwl_cmd) * q->n_window; | |
224 | if (q->id == IWL_CMD_QUEUE_NUM) | |
225 | len += IWL_MAX_SCAN_SIZE; | |
226 | ||
227 | /* De-alloc array of command/tx buffers */ | |
da99c4b6 GG |
228 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? |
229 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
230 | for (i = 0; i < slots_num; i++) | |
231 | kfree(txq->cmd[i]); | |
232 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
233 | kfree(txq->cmd[slots_num]); | |
1053d35f RR |
234 | |
235 | /* De-alloc circular buffer of TFDs */ | |
236 | if (txq->q.n_bd) | |
237 | pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) * | |
238 | txq->q.n_bd, txq->bd, txq->q.dma_addr); | |
239 | ||
240 | /* De-alloc array of per-TFD driver data */ | |
241 | kfree(txq->txb); | |
242 | txq->txb = NULL; | |
243 | ||
244 | /* 0-fill queue descriptor structure */ | |
245 | memset(txq, 0, sizeof(*txq)); | |
246 | } | |
247 | ||
fd4abac5 TW |
248 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
249 | * DMA services | |
250 | * | |
251 | * Theory of operation | |
252 | * | |
253 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
254 | * of buffer descriptors, each of which points to one or more data buffers for | |
255 | * the device to read from or fill. Driver and device exchange status of each | |
256 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
257 | * entries in each circular buffer, to protect against confusing empty and full | |
258 | * queue states. | |
259 | * | |
260 | * The device reads or writes the data in the queues via the device's several | |
261 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
262 | * | |
263 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
264 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
265 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
266 | * Tx queue resumed. | |
267 | * | |
268 | * See more detailed info in iwl-4965-hw.h. | |
269 | ***************************************************/ | |
270 | ||
271 | int iwl_queue_space(const struct iwl_queue *q) | |
272 | { | |
273 | int s = q->read_ptr - q->write_ptr; | |
274 | ||
275 | if (q->read_ptr > q->write_ptr) | |
276 | s -= q->n_bd; | |
277 | ||
278 | if (s <= 0) | |
279 | s += q->n_window; | |
280 | /* keep some reserve to not confuse empty and full situations */ | |
281 | s -= 2; | |
282 | if (s < 0) | |
283 | s = 0; | |
284 | return s; | |
285 | } | |
286 | EXPORT_SYMBOL(iwl_queue_space); | |
287 | ||
288 | ||
1053d35f RR |
289 | /** |
290 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
291 | */ | |
443cfd45 | 292 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
293 | int count, int slots_num, u32 id) |
294 | { | |
295 | q->n_bd = count; | |
296 | q->n_window = slots_num; | |
297 | q->id = id; | |
298 | ||
299 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
300 | * and iwl_queue_dec_wrap are broken. */ | |
301 | BUG_ON(!is_power_of_2(count)); | |
302 | ||
303 | /* slots_num must be power-of-two size, otherwise | |
304 | * get_cmd_index is broken. */ | |
305 | BUG_ON(!is_power_of_2(slots_num)); | |
306 | ||
307 | q->low_mark = q->n_window / 4; | |
308 | if (q->low_mark < 4) | |
309 | q->low_mark = 4; | |
310 | ||
311 | q->high_mark = q->n_window / 8; | |
312 | if (q->high_mark < 2) | |
313 | q->high_mark = 2; | |
314 | ||
315 | q->write_ptr = q->read_ptr = 0; | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | /** | |
321 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
322 | */ | |
323 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 324 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
325 | { |
326 | struct pci_dev *dev = priv->pci_dev; | |
327 | ||
328 | /* Driver private data, only for Tx (not command) queues, | |
329 | * not shared with device. */ | |
330 | if (id != IWL_CMD_QUEUE_NUM) { | |
331 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
332 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
333 | if (!txq->txb) { | |
334 | IWL_ERROR("kmalloc for auxiliary BD " | |
335 | "structures failed\n"); | |
336 | goto error; | |
337 | } | |
338 | } else | |
339 | txq->txb = NULL; | |
340 | ||
341 | /* Circular buffer of transmit frame descriptors (TFDs), | |
342 | * shared with device */ | |
343 | txq->bd = pci_alloc_consistent(dev, | |
344 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
345 | &txq->q.dma_addr); | |
346 | ||
347 | if (!txq->bd) { | |
348 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
349 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
350 | goto error; | |
351 | } | |
352 | txq->q.id = id; | |
353 | ||
354 | return 0; | |
355 | ||
356 | error: | |
357 | kfree(txq->txb); | |
358 | txq->txb = NULL; | |
359 | ||
360 | return -ENOMEM; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
365 | * given Tx queue, and enable the DMA channel used for that queue. | |
366 | * | |
367 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
368 | * channels supported in hardware. | |
369 | */ | |
370 | static int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
16466903 | 371 | struct iwl_tx_queue *txq) |
1053d35f RR |
372 | { |
373 | int rc; | |
374 | unsigned long flags; | |
375 | int txq_id = txq->q.id; | |
376 | ||
377 | spin_lock_irqsave(&priv->lock, flags); | |
378 | rc = iwl_grab_nic_access(priv); | |
379 | if (rc) { | |
380 | spin_unlock_irqrestore(&priv->lock, flags); | |
381 | return rc; | |
382 | } | |
383 | ||
384 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
385 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
386 | txq->q.dma_addr >> 8); | |
387 | ||
388 | /* Enable DMA channel, using same id as for TFD queue */ | |
389 | iwl_write_direct32( | |
390 | priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), | |
391 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
392 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); | |
393 | iwl_release_nic_access(priv); | |
394 | spin_unlock_irqrestore(&priv->lock, flags); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | /** | |
400 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
401 | */ | |
73b7d742 | 402 | static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
1053d35f RR |
403 | int slots_num, u32 txq_id) |
404 | { | |
da99c4b6 | 405 | int i, len; |
73b7d742 | 406 | int ret; |
1053d35f RR |
407 | |
408 | /* | |
409 | * Alloc buffer array for commands (Tx or other types of commands). | |
410 | * For the command queue (#4), allocate command space + one big | |
411 | * command for scan, since scan command is very huge; the system will | |
412 | * not have two scans at the same time, so only one is needed. | |
413 | * For normal Tx queues (all other queues), no super-size command | |
414 | * space is needed. | |
415 | */ | |
da99c4b6 GG |
416 | len = sizeof(struct iwl_cmd); |
417 | for (i = 0; i <= slots_num; i++) { | |
418 | if (i == slots_num) { | |
419 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
420 | len += IWL_MAX_SCAN_SIZE; | |
421 | else | |
422 | continue; | |
423 | } | |
424 | ||
49898852 | 425 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 426 | if (!txq->cmd[i]) |
73b7d742 | 427 | goto err; |
da99c4b6 | 428 | } |
1053d35f RR |
429 | |
430 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
431 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
432 | if (ret) | |
433 | goto err; | |
1053d35f | 434 | |
1053d35f RR |
435 | txq->need_update = 0; |
436 | ||
437 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
438 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
439 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
440 | ||
441 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
442 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
443 | ||
444 | /* Tell device where to find queue */ | |
445 | iwl_hw_tx_queue_init(priv, txq); | |
446 | ||
447 | return 0; | |
73b7d742 TW |
448 | err: |
449 | for (i = 0; i < slots_num; i++) { | |
450 | kfree(txq->cmd[i]); | |
451 | txq->cmd[i] = NULL; | |
452 | } | |
453 | ||
454 | if (txq_id == IWL_CMD_QUEUE_NUM) { | |
455 | kfree(txq->cmd[slots_num]); | |
456 | txq->cmd[slots_num] = NULL; | |
457 | } | |
458 | return -ENOMEM; | |
1053d35f | 459 | } |
da1bc453 TW |
460 | /** |
461 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
462 | * | |
463 | * Destroy all TX DMA queues and structures | |
464 | */ | |
465 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
466 | { | |
467 | int txq_id; | |
468 | ||
469 | /* Tx queues */ | |
470 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
da99c4b6 | 471 | iwl_tx_queue_free(priv, txq_id); |
da1bc453 TW |
472 | |
473 | /* Keep-warm buffer */ | |
474 | iwl_kw_free(priv); | |
475 | } | |
476 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
477 | ||
1053d35f RR |
478 | /** |
479 | * iwl_txq_ctx_reset - Reset TX queue context | |
480 | * Destroys all DMA structures and initialise them again | |
481 | * | |
482 | * @param priv | |
483 | * @return error code | |
484 | */ | |
485 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
486 | { | |
487 | int ret = 0; | |
488 | int txq_id, slots_num; | |
da1bc453 | 489 | unsigned long flags; |
1053d35f RR |
490 | |
491 | iwl_kw_free(priv); | |
492 | ||
493 | /* Free all tx/cmd queues and keep-warm buffer */ | |
494 | iwl_hw_txq_ctx_free(priv); | |
495 | ||
496 | /* Alloc keep-warm buffer */ | |
497 | ret = iwl_kw_alloc(priv); | |
498 | if (ret) { | |
6f147926 | 499 | IWL_ERROR("Keep Warm allocation failed\n"); |
1053d35f RR |
500 | goto error_kw; |
501 | } | |
da1bc453 TW |
502 | spin_lock_irqsave(&priv->lock, flags); |
503 | ret = iwl_grab_nic_access(priv); | |
504 | if (unlikely(ret)) { | |
505 | spin_unlock_irqrestore(&priv->lock, flags); | |
506 | goto error_reset; | |
507 | } | |
1053d35f RR |
508 | |
509 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
510 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
511 | ||
512 | iwl_release_nic_access(priv); | |
513 | spin_unlock_irqrestore(&priv->lock, flags); | |
514 | ||
1053d35f RR |
515 | |
516 | /* Tell nic where to find the keep-warm buffer */ | |
517 | ret = iwl_kw_init(priv); | |
518 | if (ret) { | |
519 | IWL_ERROR("kw_init failed\n"); | |
520 | goto error_reset; | |
521 | } | |
522 | ||
da1bc453 | 523 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
524 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
525 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
526 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
527 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
528 | txq_id); | |
529 | if (ret) { | |
530 | IWL_ERROR("Tx %d queue init failed\n", txq_id); | |
531 | goto error; | |
532 | } | |
533 | } | |
534 | ||
535 | return ret; | |
536 | ||
537 | error: | |
538 | iwl_hw_txq_ctx_free(priv); | |
539 | error_reset: | |
540 | iwl_kw_free(priv); | |
541 | error_kw: | |
542 | return ret; | |
543 | } | |
a33c2f47 | 544 | |
da1bc453 TW |
545 | /** |
546 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
547 | */ | |
548 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
549 | { | |
550 | ||
551 | int txq_id; | |
552 | unsigned long flags; | |
553 | ||
554 | ||
555 | /* Turn off all Tx DMA fifos */ | |
556 | spin_lock_irqsave(&priv->lock, flags); | |
557 | if (iwl_grab_nic_access(priv)) { | |
558 | spin_unlock_irqrestore(&priv->lock, flags); | |
559 | return; | |
560 | } | |
561 | ||
562 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
563 | ||
564 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
565 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
566 | iwl_write_direct32(priv, | |
567 | FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0); | |
568 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, | |
569 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE | |
570 | (txq_id), 200); | |
571 | } | |
572 | iwl_release_nic_access(priv); | |
573 | spin_unlock_irqrestore(&priv->lock, flags); | |
574 | ||
575 | /* Deallocate memory for all Tx queues */ | |
576 | iwl_hw_txq_ctx_free(priv); | |
577 | } | |
578 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
579 | |
580 | /* | |
581 | * handle build REPLY_TX command notification. | |
582 | */ | |
583 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
584 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 585 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
586 | struct ieee80211_hdr *hdr, |
587 | int is_unicast, u8 std_id) | |
588 | { | |
fd7c8a40 | 589 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
590 | __le32 tx_flags = tx_cmd->tx_flags; |
591 | ||
592 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 593 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 594 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 595 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 596 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 597 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
598 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
599 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
600 | } else { | |
601 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
602 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
603 | } | |
604 | ||
fd7c8a40 | 605 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
606 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
607 | ||
608 | ||
609 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 610 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
611 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
612 | ||
fd7c8a40 HH |
613 | if (ieee80211_is_data_qos(fc)) { |
614 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
615 | tx_cmd->tid_tspec = qc[0] & 0xf; |
616 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
617 | } else { | |
618 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
619 | } | |
620 | ||
a326a5d0 | 621 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
fd4abac5 TW |
622 | |
623 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
624 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
625 | ||
626 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
627 | if (ieee80211_is_mgmt(fc)) { |
628 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
629 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
630 | else | |
631 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
632 | } else { | |
633 | tx_cmd->timeout.pm_frame_timeout = 0; | |
634 | } | |
635 | ||
636 | tx_cmd->driver_txop = 0; | |
637 | tx_cmd->tx_flags = tx_flags; | |
638 | tx_cmd->next_frame_len = 0; | |
639 | } | |
640 | ||
641 | #define RTS_HCCA_RETRY_LIMIT 3 | |
642 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
643 | ||
644 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
645 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 646 | struct ieee80211_tx_info *info, |
fd7c8a40 | 647 | __le16 fc, int sta_id, |
fd4abac5 TW |
648 | int is_hcca) |
649 | { | |
650 | u8 rts_retry_limit = 0; | |
651 | u8 data_retry_limit = 0; | |
652 | u8 rate_plcp; | |
653 | u16 rate_flags = 0; | |
2e92e6f2 JB |
654 | int rate_idx; |
655 | ||
e039fa4a | 656 | rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff, |
2e92e6f2 | 657 | IWL_RATE_COUNT - 1); |
fd4abac5 TW |
658 | |
659 | rate_plcp = iwl_rates[rate_idx].plcp; | |
660 | ||
661 | rts_retry_limit = (is_hcca) ? | |
662 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; | |
663 | ||
664 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
665 | rate_flags |= RATE_MCS_CCK_MSK; | |
666 | ||
667 | ||
fd7c8a40 | 668 | if (ieee80211_is_probe_resp(fc)) { |
fd4abac5 TW |
669 | data_retry_limit = 3; |
670 | if (data_retry_limit < rts_retry_limit) | |
671 | rts_retry_limit = data_retry_limit; | |
672 | } else | |
673 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
674 | ||
675 | if (priv->data_retry_limit != -1) | |
676 | data_retry_limit = priv->data_retry_limit; | |
677 | ||
678 | ||
679 | if (ieee80211_is_data(fc)) { | |
680 | tx_cmd->initial_rate_index = 0; | |
681 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
682 | } else { | |
fd7c8a40 HH |
683 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { |
684 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
685 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
686 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
687 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
fd4abac5 TW |
688 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { |
689 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
690 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
691 | } | |
692 | break; | |
693 | default: | |
694 | break; | |
695 | } | |
696 | ||
697 | /* Alternate between antenna A and B for successive frames */ | |
698 | if (priv->use_ant_b_for_management_frame) { | |
699 | priv->use_ant_b_for_management_frame = 0; | |
700 | rate_flags |= RATE_MCS_ANT_B_MSK; | |
701 | } else { | |
702 | priv->use_ant_b_for_management_frame = 1; | |
703 | rate_flags |= RATE_MCS_ANT_A_MSK; | |
704 | } | |
705 | } | |
706 | ||
707 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
708 | tx_cmd->data_retry_limit = data_retry_limit; | |
e7d326ac | 709 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
710 | } |
711 | ||
712 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 713 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
714 | struct iwl_tx_cmd *tx_cmd, |
715 | struct sk_buff *skb_frag, | |
716 | int sta_id) | |
717 | { | |
e039fa4a | 718 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 719 | |
ccc038ab | 720 | switch (keyconf->alg) { |
fd4abac5 TW |
721 | case ALG_CCMP: |
722 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 723 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 724 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 TW |
725 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
726 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); | |
727 | break; | |
728 | ||
729 | case ALG_TKIP: | |
730 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 731 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 TW |
732 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
733 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); | |
734 | break; | |
735 | ||
736 | case ALG_WEP: | |
fd4abac5 | 737 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
738 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
739 | ||
740 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
741 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
742 | ||
743 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 TW |
744 | |
745 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
ccc038ab | 746 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
747 | break; |
748 | ||
749 | default: | |
ccc038ab | 750 | printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
751 | break; |
752 | } | |
753 | } | |
754 | ||
755 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) | |
756 | { | |
757 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
758 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
759 | priv->tx_stats[idx].cnt++; | |
760 | priv->tx_stats[idx].bytes += len; | |
761 | } | |
762 | ||
763 | /* | |
764 | * start REPLY_TX command process | |
765 | */ | |
e039fa4a | 766 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
767 | { |
768 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 769 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
fd4abac5 | 770 | struct iwl_tfd_frame *tfd; |
f3674227 TW |
771 | struct iwl_tx_queue *txq; |
772 | struct iwl_queue *q; | |
773 | struct iwl_cmd *out_cmd; | |
774 | struct iwl_tx_cmd *tx_cmd; | |
775 | int swq_id, txq_id; | |
fd4abac5 TW |
776 | dma_addr_t phys_addr; |
777 | dma_addr_t txcmd_phys; | |
778 | dma_addr_t scratch_phys; | |
fd4abac5 TW |
779 | u16 len, idx, len_org; |
780 | u16 seq_number = 0; | |
fd7c8a40 | 781 | __le16 fc; |
f3674227 TW |
782 | u8 hdr_len, unicast; |
783 | u8 sta_id; | |
fd4abac5 TW |
784 | u8 wait_write_ptr = 0; |
785 | u8 tid = 0; | |
786 | u8 *qc = NULL; | |
787 | unsigned long flags; | |
788 | int ret; | |
789 | ||
790 | spin_lock_irqsave(&priv->lock, flags); | |
791 | if (iwl_is_rfkill(priv)) { | |
792 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); | |
793 | goto drop_unlock; | |
794 | } | |
795 | ||
e039fa4a | 796 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == |
2e92e6f2 | 797 | IWL_INVALID_RATE) { |
fd4abac5 TW |
798 | IWL_ERROR("ERROR: No TX rate available.\n"); |
799 | goto drop_unlock; | |
800 | } | |
801 | ||
802 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
fd4abac5 | 803 | |
fd7c8a40 | 804 | fc = hdr->frame_control; |
fd4abac5 TW |
805 | |
806 | #ifdef CONFIG_IWLWIFI_DEBUG | |
807 | if (ieee80211_is_auth(fc)) | |
808 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
fd7c8a40 | 809 | else if (ieee80211_is_assoc_req(fc)) |
fd4abac5 | 810 | IWL_DEBUG_TX("Sending ASSOC frame\n"); |
fd7c8a40 | 811 | else if (ieee80211_is_reassoc_req(fc)) |
fd4abac5 TW |
812 | IWL_DEBUG_TX("Sending REASSOC frame\n"); |
813 | #endif | |
814 | ||
815 | /* drop all data frame if we are not associated */ | |
fd7c8a40 | 816 | if (ieee80211_is_data(fc) && |
05c914fe | 817 | (priv->iw_mode != NL80211_IFTYPE_MONITOR || |
d10c4ec8 SG |
818 | !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */ |
819 | (!iwl_is_associated(priv) || | |
05c914fe | 820 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) || |
d10c4ec8 | 821 | !priv->assoc_station_added)) { |
fd4abac5 TW |
822 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); |
823 | goto drop_unlock; | |
824 | } | |
825 | ||
826 | spin_unlock_irqrestore(&priv->lock, flags); | |
827 | ||
7294ec95 | 828 | hdr_len = ieee80211_hdrlen(fc); |
fd4abac5 TW |
829 | |
830 | /* Find (or create) index into station table for destination station */ | |
831 | sta_id = iwl_get_sta_id(priv, hdr); | |
832 | if (sta_id == IWL_INVALID_STATION) { | |
e174961c JB |
833 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n", |
834 | hdr->addr1); | |
fd4abac5 TW |
835 | goto drop; |
836 | } | |
837 | ||
838 | IWL_DEBUG_TX("station Id %d\n", sta_id); | |
839 | ||
f3674227 TW |
840 | swq_id = skb_get_queue_mapping(skb); |
841 | txq_id = swq_id; | |
fd7c8a40 HH |
842 | if (ieee80211_is_data_qos(fc)) { |
843 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 844 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
f3674227 TW |
845 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
846 | seq_number &= IEEE80211_SCTL_SEQ; | |
847 | hdr->seq_ctrl = hdr->seq_ctrl & | |
848 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG); | |
849 | hdr->seq_ctrl |= cpu_to_le16(seq_number); | |
fd4abac5 | 850 | seq_number += 0x10; |
fd4abac5 | 851 | /* aggregation is on for this <sta,tid> */ |
e039fa4a | 852 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 TW |
853 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
854 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 TW |
855 | } |
856 | ||
857 | /* Descriptor for chosen Tx queue */ | |
858 | txq = &priv->txq[txq_id]; | |
859 | q = &txq->q; | |
860 | ||
861 | spin_lock_irqsave(&priv->lock, flags); | |
862 | ||
863 | /* Set up first empty TFD within this queue's circular TFD buffer */ | |
864 | tfd = &txq->bd[q->write_ptr]; | |
865 | memset(tfd, 0, sizeof(*tfd)); | |
fd4abac5 TW |
866 | idx = get_cmd_index(q, q->write_ptr, 0); |
867 | ||
868 | /* Set up driver data for this TFD */ | |
869 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
870 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
871 | |
872 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
da99c4b6 | 873 | out_cmd = txq->cmd[idx]; |
fd4abac5 TW |
874 | tx_cmd = &out_cmd->cmd.tx; |
875 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
876 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
877 | ||
878 | /* | |
879 | * Set up the Tx-command (not MAC!) header. | |
880 | * Store the chosen Tx queue and TFD index within the sequence field; | |
881 | * after Tx, uCode's Tx response will return this value so driver can | |
882 | * locate the frame within the tx queue and do post-tx processing. | |
883 | */ | |
884 | out_cmd->hdr.cmd = REPLY_TX; | |
885 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
886 | INDEX_TO_SEQ(q->write_ptr))); | |
887 | ||
888 | /* Copy MAC header from skb into command buffer */ | |
889 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
890 | ||
891 | /* | |
892 | * Use the first empty entry in this queue's command buffer array | |
893 | * to contain the Tx command and MAC header concatenated together | |
894 | * (payload data will be in another buffer). | |
895 | * Size of this varies, due to varying MAC header length. | |
896 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
897 | * of the MAC header (device reads on dword boundaries). | |
898 | * We'll tell device about this padding later. | |
899 | */ | |
900 | len = sizeof(struct iwl_tx_cmd) + | |
901 | sizeof(struct iwl_cmd_header) + hdr_len; | |
902 | ||
903 | len_org = len; | |
904 | len = (len + 3) & ~3; | |
905 | ||
906 | if (len_org != len) | |
907 | len_org = 1; | |
908 | else | |
909 | len_org = 0; | |
910 | ||
911 | /* Physical address of this Tx command's header (not MAC header!), | |
912 | * within command buffer array. */ | |
da99c4b6 GG |
913 | txcmd_phys = pci_map_single(priv->pci_dev, out_cmd, |
914 | sizeof(struct iwl_cmd), PCI_DMA_TODEVICE); | |
915 | txcmd_phys += offsetof(struct iwl_cmd, hdr); | |
fd4abac5 TW |
916 | |
917 | /* Add buffer containing Tx command and MAC(!) header to TFD's | |
918 | * first entry */ | |
919 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); | |
920 | ||
d0f09804 | 921 | if (info->control.hw_key) |
e039fa4a | 922 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); |
fd4abac5 TW |
923 | |
924 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
925 | * if any (802.11 null frames have no payload). */ | |
926 | len = skb->len - hdr_len; | |
927 | if (len) { | |
928 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
929 | len, PCI_DMA_TODEVICE); | |
930 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); | |
931 | } | |
932 | ||
933 | /* Tell NIC about any 2-byte padding after MAC header */ | |
934 | if (len_org) | |
935 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
936 | ||
937 | /* Total # bytes to be transmitted */ | |
938 | len = (u16)skb->len; | |
939 | tx_cmd->len = cpu_to_le16(len); | |
940 | /* TODO need this for burst mode later on */ | |
e039fa4a | 941 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id); |
fd4abac5 TW |
942 | |
943 | /* set is_hcca to 0; it probably will never be implemented */ | |
e039fa4a | 944 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0); |
fd4abac5 | 945 | |
fd7c8a40 | 946 | iwl_update_tx_stats(priv, le16_to_cpu(fc), len); |
fd4abac5 TW |
947 | |
948 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
949 | offsetof(struct iwl_tx_cmd, scratch); | |
950 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
951 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); | |
952 | ||
8b7b1e05 | 953 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
fd4abac5 TW |
954 | txq->need_update = 1; |
955 | if (qc) | |
956 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
957 | } else { | |
958 | wait_write_ptr = 1; | |
959 | txq->need_update = 0; | |
960 | } | |
961 | ||
962 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
963 | ||
964 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
965 | ||
966 | /* Set up entry for this TFD in Tx byte-count array */ | |
967 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); | |
968 | ||
969 | /* Tell device the write index *just past* this latest filled TFD */ | |
970 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
971 | ret = iwl_txq_update_write_ptr(priv, txq); | |
972 | spin_unlock_irqrestore(&priv->lock, flags); | |
973 | ||
974 | if (ret) | |
975 | return ret; | |
976 | ||
143b09ef | 977 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
fd4abac5 TW |
978 | if (wait_write_ptr) { |
979 | spin_lock_irqsave(&priv->lock, flags); | |
980 | txq->need_update = 1; | |
981 | iwl_txq_update_write_ptr(priv, txq); | |
982 | spin_unlock_irqrestore(&priv->lock, flags); | |
143b09ef | 983 | } else { |
f3674227 | 984 | ieee80211_stop_queue(priv->hw, swq_id); |
fd4abac5 | 985 | } |
fd4abac5 TW |
986 | } |
987 | ||
988 | return 0; | |
989 | ||
990 | drop_unlock: | |
991 | spin_unlock_irqrestore(&priv->lock, flags); | |
992 | drop: | |
993 | return -1; | |
994 | } | |
995 | EXPORT_SYMBOL(iwl_tx_skb); | |
996 | ||
997 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
998 | ||
999 | /** | |
1000 | * iwl_enqueue_hcmd - enqueue a uCode command | |
1001 | * @priv: device private data point | |
1002 | * @cmd: a point to the ucode command structure | |
1003 | * | |
1004 | * The function returns < 0 values to indicate the operation is | |
1005 | * failed. On success, it turns the index (> 0) of command in the | |
1006 | * command queue. | |
1007 | */ | |
1008 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
1009 | { | |
1010 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
1011 | struct iwl_queue *q = &txq->q; | |
1012 | struct iwl_tfd_frame *tfd; | |
fd4abac5 | 1013 | struct iwl_cmd *out_cmd; |
fd4abac5 | 1014 | dma_addr_t phys_addr; |
fd4abac5 | 1015 | unsigned long flags; |
f3674227 TW |
1016 | int len, ret; |
1017 | u32 idx; | |
1018 | u16 fix_size; | |
fd4abac5 TW |
1019 | |
1020 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
1021 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
1022 | ||
1023 | /* If any of the command structures end up being larger than | |
1024 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
1025 | * we will need to increase the size of the TFD entries */ | |
1026 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
1027 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
1028 | ||
1029 | if (iwl_is_rfkill(priv)) { | |
1030 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
1031 | return -EIO; | |
1032 | } | |
1033 | ||
1034 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { | |
1035 | IWL_ERROR("No space for Tx\n"); | |
1036 | return -ENOSPC; | |
1037 | } | |
1038 | ||
1039 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
1040 | ||
1041 | tfd = &txq->bd[q->write_ptr]; | |
1042 | memset(tfd, 0, sizeof(*tfd)); | |
1043 | ||
fd4abac5 TW |
1044 | |
1045 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); | |
da99c4b6 | 1046 | out_cmd = txq->cmd[idx]; |
fd4abac5 TW |
1047 | |
1048 | out_cmd->hdr.cmd = cmd->id; | |
1049 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
1050 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
1051 | ||
1052 | /* At this point, the out_cmd now has all of the incoming cmd | |
1053 | * information */ | |
1054 | ||
1055 | out_cmd->hdr.flags = 0; | |
1056 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
1057 | INDEX_TO_SEQ(q->write_ptr)); | |
1058 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) | |
9734cb23 | 1059 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
da99c4b6 GG |
1060 | len = (idx == TFD_CMD_SLOTS) ? |
1061 | IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd); | |
1062 | phys_addr = pci_map_single(priv->pci_dev, out_cmd, len, | |
1063 | PCI_DMA_TODEVICE); | |
1064 | phys_addr += offsetof(struct iwl_cmd, hdr); | |
fd4abac5 TW |
1065 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
1066 | ||
ded2ae7c EK |
1067 | #ifdef CONFIG_IWLWIFI_DEBUG |
1068 | switch (out_cmd->hdr.cmd) { | |
1069 | case REPLY_TX_LINK_QUALITY_CMD: | |
1070 | case SENSITIVITY_CMD: | |
1071 | IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, " | |
1072 | "%d bytes at %d[%d]:%d\n", | |
1073 | get_cmd_string(out_cmd->hdr.cmd), | |
1074 | out_cmd->hdr.cmd, | |
1075 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1076 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1077 | break; | |
1078 | default: | |
1079 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
1080 | "%d bytes at %d[%d]:%d\n", | |
1081 | get_cmd_string(out_cmd->hdr.cmd), | |
1082 | out_cmd->hdr.cmd, | |
1083 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1084 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1085 | } | |
1086 | #endif | |
fd4abac5 TW |
1087 | txq->need_update = 1; |
1088 | ||
1089 | /* Set up entry in queue's byte count circular buffer */ | |
1090 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
1091 | ||
1092 | /* Increment and update queue's write index */ | |
1093 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1094 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1095 | ||
1096 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1097 | return ret ? ret : idx; | |
1098 | } | |
1099 | ||
17b88929 TW |
1100 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1101 | { | |
1102 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1103 | struct iwl_queue *q = &txq->q; | |
1104 | struct iwl_tx_info *tx_info; | |
1105 | int nfreed = 0; | |
1106 | ||
1107 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
1108 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
1109 | "is out of range [0-%d] %d %d.\n", txq_id, | |
1110 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
1115 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1116 | ||
1117 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1118 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); | |
1119 | tx_info->skb[0] = NULL; | |
17b88929 | 1120 | |
972cf447 TW |
1121 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1122 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1123 | ||
1124 | iwl_hw_txq_free_tfd(priv, txq); | |
17b88929 TW |
1125 | nfreed++; |
1126 | } | |
1127 | return nfreed; | |
1128 | } | |
1129 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1130 | ||
1131 | ||
1132 | /** | |
1133 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1134 | * | |
1135 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1136 | * need to be reclaimed. As result, some free space forms. If there is | |
1137 | * enough free space (> low mark), wake the stack that feeds us. | |
1138 | */ | |
1139 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) | |
1140 | { | |
1141 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1142 | struct iwl_queue *q = &txq->q; | |
da99c4b6 GG |
1143 | struct iwl_tfd_frame *bd = &txq->bd[index]; |
1144 | dma_addr_t dma_addr; | |
1145 | int is_odd, buf_len; | |
17b88929 TW |
1146 | int nfreed = 0; |
1147 | ||
1148 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
1149 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
1150 | "is out of range [0-%d] %d %d.\n", txq_id, | |
1151 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1152 | return; | |
1153 | } | |
1154 | ||
1155 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
1156 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1157 | ||
1158 | if (nfreed > 1) { | |
1159 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
1160 | q->write_ptr, q->read_ptr); | |
1161 | queue_work(priv->workqueue, &priv->restart); | |
1162 | } | |
da99c4b6 GG |
1163 | is_odd = (index/2) & 0x1; |
1164 | if (is_odd) { | |
1165 | dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | | |
1166 | (IWL_GET_BITS(bd->pa[index], | |
1167 | tb2_addr_hi20) << 16); | |
1168 | buf_len = IWL_GET_BITS(bd->pa[index], tb2_len); | |
1169 | } else { | |
1170 | dma_addr = le32_to_cpu(bd->pa[index].tb1_addr); | |
1171 | buf_len = IWL_GET_BITS(bd->pa[index], tb1_len); | |
1172 | } | |
1173 | ||
1174 | pci_unmap_single(priv->pci_dev, dma_addr, buf_len, | |
1175 | PCI_DMA_TODEVICE); | |
17b88929 TW |
1176 | nfreed++; |
1177 | } | |
1178 | } | |
1179 | ||
1180 | /** | |
1181 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1182 | * @rxb: Rx buffer to reclaim | |
1183 | * | |
1184 | * If an Rx buffer has an async callback associated with it the callback | |
1185 | * will be executed. The attached skb (if present) will only be freed | |
1186 | * if the callback returns 1 | |
1187 | */ | |
1188 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1189 | { | |
1190 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1191 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1192 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1193 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1194 | int cmd_index; |
9734cb23 | 1195 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
17b88929 TW |
1196 | struct iwl_cmd *cmd; |
1197 | ||
1198 | /* If a Tx command is being handled and it isn't in the actual | |
1199 | * command queue then there a command routing bug has been introduced | |
1200 | * in the queue management code. */ | |
55d6a3cd JB |
1201 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
1202 | "wrong command queue %d, command id 0x%X\n", txq_id, pkt->hdr.cmd)) | |
1203 | return; | |
17b88929 TW |
1204 | |
1205 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
da99c4b6 | 1206 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; |
17b88929 TW |
1207 | |
1208 | /* Input error checking is done when commands are added to queue. */ | |
1209 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
1210 | cmd->meta.source->u.skb = rxb->skb; | |
1211 | rxb->skb = NULL; | |
1212 | } else if (cmd->meta.u.callback && | |
1213 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
1214 | rxb->skb = NULL; | |
1215 | ||
1216 | iwl_hcmd_queue_reclaim(priv, txq_id, index); | |
1217 | ||
1218 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
1219 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
1220 | wake_up_interruptible(&priv->wait_command_queue); | |
1221 | } | |
1222 | } | |
1223 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1224 | ||
30e553e3 TW |
1225 | /* |
1226 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1227 | * Called only when finding queue for aggregation. | |
1228 | * Should never return anything < 7, because they should already | |
1229 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1230 | */ | |
1231 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1232 | { | |
1233 | int txq_id; | |
1234 | ||
1235 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1236 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1237 | return txq_id; | |
1238 | return -1; | |
1239 | } | |
1240 | ||
1241 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1242 | { | |
1243 | int sta_id; | |
1244 | int tx_fifo; | |
1245 | int txq_id; | |
1246 | int ret; | |
1247 | unsigned long flags; | |
1248 | struct iwl_tid_data *tid_data; | |
30e553e3 TW |
1249 | |
1250 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1251 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1252 | else | |
1253 | return -EINVAL; | |
1254 | ||
e174961c JB |
1255 | IWL_WARNING("%s on ra = %pM tid = %d\n", |
1256 | __func__, ra, tid); | |
30e553e3 TW |
1257 | |
1258 | sta_id = iwl_find_station(priv, ra); | |
1259 | if (sta_id == IWL_INVALID_STATION) | |
1260 | return -ENXIO; | |
1261 | ||
1262 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
1263 | IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n"); | |
1264 | return -ENXIO; | |
1265 | } | |
1266 | ||
1267 | txq_id = iwl_txq_ctx_activate_free(priv); | |
1268 | if (txq_id == -1) | |
1269 | return -ENXIO; | |
1270 | ||
1271 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1272 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1273 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1274 | tid_data->agg.txq_id = txq_id; | |
1275 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1276 | ||
1277 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1278 | sta_id, tid, *ssn); | |
1279 | if (ret) | |
1280 | return ret; | |
1281 | ||
1282 | if (tid_data->tfds_in_queue == 0) { | |
1283 | printk(KERN_ERR "HW queue is empty\n"); | |
1284 | tid_data->agg.state = IWL_AGG_ON; | |
1285 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1286 | } else { | |
1287 | IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n", | |
1288 | tid_data->tfds_in_queue); | |
1289 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1290 | } | |
1291 | return ret; | |
1292 | } | |
1293 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1294 | ||
1295 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1296 | { | |
1297 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1298 | struct iwl_tid_data *tid_data; | |
1299 | int ret, write_ptr, read_ptr; | |
1300 | unsigned long flags; | |
30e553e3 TW |
1301 | |
1302 | if (!ra) { | |
1303 | IWL_ERROR("ra = NULL\n"); | |
1304 | return -EINVAL; | |
1305 | } | |
1306 | ||
1307 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1308 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1309 | else | |
1310 | return -EINVAL; | |
1311 | ||
1312 | sta_id = iwl_find_station(priv, ra); | |
1313 | ||
1314 | if (sta_id == IWL_INVALID_STATION) | |
1315 | return -ENXIO; | |
1316 | ||
1317 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) | |
1318 | IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n"); | |
1319 | ||
1320 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1321 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1322 | txq_id = tid_data->agg.txq_id; | |
1323 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1324 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1325 | ||
1326 | /* The queue is not empty */ | |
1327 | if (write_ptr != read_ptr) { | |
1328 | IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n"); | |
1329 | priv->stations[sta_id].tid[tid].agg.state = | |
1330 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1331 | return 0; | |
1332 | } | |
1333 | ||
1334 | IWL_DEBUG_HT("HW queue is empty\n"); | |
1335 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; | |
1336 | ||
1337 | spin_lock_irqsave(&priv->lock, flags); | |
1338 | ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1339 | tx_fifo_id); | |
1340 | spin_unlock_irqrestore(&priv->lock, flags); | |
1341 | ||
1342 | if (ret) | |
1343 | return ret; | |
1344 | ||
1345 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1350 | ||
1351 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1352 | { | |
1353 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1354 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1355 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1356 | ||
1357 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1358 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1359 | /* We are reclaiming the last packet of the */ | |
1360 | /* aggregated HW queue */ | |
1361 | if (txq_id == tid_data->agg.txq_id && | |
1362 | q->read_ptr == q->write_ptr) { | |
1363 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); | |
1364 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
1365 | IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n"); | |
1366 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, | |
1367 | ssn, tx_fifo); | |
1368 | tid_data->agg.state = IWL_AGG_OFF; | |
1369 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1370 | } | |
1371 | break; | |
1372 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1373 | /* We are reclaiming the last packet of the queue */ | |
1374 | if (tid_data->tfds_in_queue == 0) { | |
1375 | IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n"); | |
1376 | tid_data->agg.state = IWL_AGG_ON; | |
1377 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1378 | } | |
1379 | break; | |
1380 | } | |
1381 | return 0; | |
1382 | } | |
1383 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1384 | |
653fa4a0 EG |
1385 | /** |
1386 | * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1387 | * | |
1388 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1389 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1390 | */ | |
1391 | static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1392 | struct iwl_ht_agg *agg, | |
1393 | struct iwl_compressed_ba_resp *ba_resp) | |
1394 | ||
1395 | { | |
1396 | int i, sh, ack; | |
1397 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1398 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1399 | u64 bitmap; | |
1400 | int successes = 0; | |
1401 | struct ieee80211_tx_info *info; | |
1402 | ||
1403 | if (unlikely(!agg->wait_for_ba)) { | |
1404 | IWL_ERROR("Received BA when not expected\n"); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | ||
1408 | /* Mark that the expected block-ack response arrived */ | |
1409 | agg->wait_for_ba = 0; | |
1410 | IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); | |
1411 | ||
1412 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
1413 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4); | |
1414 | if (sh < 0) /* tbw something is wrong with indices */ | |
1415 | sh += 0x100; | |
1416 | ||
1417 | /* don't use 64-bit values for now */ | |
1418 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1419 | ||
1420 | if (agg->frame_count > (64 - sh)) { | |
1421 | IWL_DEBUG_TX_REPLY("more frames than bitmap size"); | |
1422 | return -1; | |
1423 | } | |
1424 | ||
1425 | /* check for success or failure according to the | |
1426 | * transmitted bitmap and block-ack bitmap */ | |
1427 | bitmap &= agg->bitmap; | |
1428 | ||
1429 | /* For each frame attempted in aggregation, | |
1430 | * update driver's record of tx frame's status. */ | |
1431 | for (i = 0; i < agg->frame_count ; i++) { | |
4aa41f12 | 1432 | ack = bitmap & (1ULL << i); |
653fa4a0 EG |
1433 | successes += !!ack; |
1434 | IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", | |
1435 | ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff, | |
1436 | agg->start_idx + i); | |
1437 | } | |
1438 | ||
1439 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]); | |
1440 | memset(&info->status, 0, sizeof(info->status)); | |
1441 | info->flags = IEEE80211_TX_STAT_ACK; | |
1442 | info->flags |= IEEE80211_TX_STAT_AMPDU; | |
1443 | info->status.ampdu_ack_map = successes; | |
1444 | info->status.ampdu_ack_len = agg->frame_count; | |
1445 | iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info); | |
1446 | ||
1447 | IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap); | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | ||
1452 | /** | |
1453 | * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1454 | * | |
1455 | * Handles block-acknowledge notification from device, which reports success | |
1456 | * of frames sent via aggregation. | |
1457 | */ | |
1458 | void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1459 | struct iwl_rx_mem_buffer *rxb) | |
1460 | { | |
1461 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1462 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
1463 | int index; | |
1464 | struct iwl_tx_queue *txq = NULL; | |
1465 | struct iwl_ht_agg *agg; | |
653fa4a0 EG |
1466 | |
1467 | /* "flow" corresponds to Tx queue */ | |
1468 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1469 | ||
1470 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1471 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1472 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1473 | ||
1474 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
6f147926 | 1475 | IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n"); |
653fa4a0 EG |
1476 | return; |
1477 | } | |
1478 | ||
1479 | txq = &priv->txq[scd_flow]; | |
1480 | agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg; | |
1481 | ||
1482 | /* Find index just before block-ack window */ | |
1483 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1484 | ||
1485 | /* TODO: Need to get this copy more safely - now good for debug */ | |
1486 | ||
e174961c | 1487 | IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %pM, " |
653fa4a0 EG |
1488 | "sta_id = %d\n", |
1489 | agg->wait_for_ba, | |
e174961c | 1490 | (u8 *) &ba_resp->sta_addr_lo32, |
653fa4a0 EG |
1491 | ba_resp->sta_id); |
1492 | IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " | |
1493 | "%d, scd_ssn = %d\n", | |
1494 | ba_resp->tid, | |
1495 | ba_resp->seq_ctl, | |
1496 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1497 | ba_resp->scd_flow, | |
1498 | ba_resp->scd_ssn); | |
1499 | IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n", | |
1500 | agg->start_idx, | |
1501 | (unsigned long long)agg->bitmap); | |
1502 | ||
1503 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1504 | iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1505 | ||
1506 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1507 | * block-ack window (we assume that they've been successfully | |
1508 | * transmitted ... if not, it's too late anyway). */ | |
1509 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1510 | /* calculate mac80211 ampdu sw queue to wake */ | |
1511 | int ampdu_q = | |
1512 | scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues; | |
1513 | int freed = iwl_tx_queue_reclaim(priv, scd_flow, index); | |
1514 | priv->stations[ba_resp->sta_id]. | |
1515 | tid[ba_resp->tid].tfds_in_queue -= freed; | |
1516 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && | |
1517 | priv->mac80211_registered && | |
1518 | agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) | |
1519 | ieee80211_wake_queue(priv->hw, ampdu_q); | |
1520 | ||
1521 | iwl_txq_check_empty(priv, ba_resp->sta_id, | |
1522 | ba_resp->tid, scd_flow); | |
1523 | } | |
1524 | } | |
1525 | EXPORT_SYMBOL(iwl_rx_reply_compressed_ba); | |
1526 | ||
994d31f7 | 1527 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1528 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
1529 | ||
1530 | const char *iwl_get_tx_fail_reason(u32 status) | |
1531 | { | |
1532 | switch (status & TX_STATUS_MSK) { | |
1533 | case TX_STATUS_SUCCESS: | |
1534 | return "SUCCESS"; | |
1535 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1536 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1537 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1538 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1539 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1540 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1541 | TX_STATUS_ENTRY(DEST_PS); | |
1542 | TX_STATUS_ENTRY(ABORTED); | |
1543 | TX_STATUS_ENTRY(BT_RETRY); | |
1544 | TX_STATUS_ENTRY(STA_INVALID); | |
1545 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1546 | TX_STATUS_ENTRY(TID_DISABLE); | |
1547 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1548 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1549 | TX_STATUS_ENTRY(TX_LOCKED); | |
1550 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1551 | } | |
1552 | ||
1553 | return "UNKNOWN"; | |
1554 | } | |
1555 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1556 | #endif /* CONFIG_IWLWIFI_DEBUG */ |