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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
1053d35f | 32 | #include <net/mac80211.h> |
253a634c | 33 | |
214d14d4 | 34 | #include "iwl-agn.h" |
1053d35f RR |
35 | #include "iwl-dev.h" |
36 | #include "iwl-core.h" | |
1053d35f RR |
37 | #include "iwl-io.h" |
38 | #include "iwl-helpers.h" | |
253a634c | 39 | #include "iwl-trans-int-pcie.h" |
1053d35f | 40 | |
48d42c42 EG |
41 | /** |
42 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
43 | */ | |
44 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
45 | struct iwl_tx_queue *txq, | |
46 | u16 byte_cnt) | |
47 | { | |
105183b1 EG |
48 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
49 | struct iwl_trans *trans = trans(priv); | |
50 | struct iwl_trans_pcie *trans_pcie = | |
51 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
52 | int write_ptr = txq->q.write_ptr; |
53 | int txq_id = txq->q.id; | |
54 | u8 sec_ctl = 0; | |
55 | u8 sta_id = 0; | |
56 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
57 | __le16 bc_ent; | |
58 | ||
105183b1 EG |
59 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
60 | ||
48d42c42 EG |
61 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
62 | ||
63 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; | |
64 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; | |
65 | ||
66 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
67 | case TX_CMD_SEC_CCM: | |
68 | len += CCMP_MIC_LEN; | |
69 | break; | |
70 | case TX_CMD_SEC_TKIP: | |
71 | len += TKIP_ICV_LEN; | |
72 | break; | |
73 | case TX_CMD_SEC_WEP: | |
74 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
75 | break; | |
76 | } | |
77 | ||
78 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
79 | ||
80 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
81 | ||
82 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
83 | scd_bc_tbl[txq_id]. | |
84 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
85 | } | |
86 | ||
fd4abac5 TW |
87 | /** |
88 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
89 | */ | |
7bfedc59 | 90 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
91 | { |
92 | u32 reg = 0; | |
fd4abac5 TW |
93 | int txq_id = txq->q.id; |
94 | ||
95 | if (txq->need_update == 0) | |
7bfedc59 | 96 | return; |
fd4abac5 | 97 | |
f81c1f48 WYG |
98 | if (priv->cfg->base_params->shadow_reg_enable) { |
99 | /* shadow register enabled */ | |
100 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
101 | txq->q.write_ptr | (txq_id << 8)); | |
102 | } else { | |
103 | /* if we're trying to save power */ | |
63013ae3 | 104 | if (test_bit(STATUS_POWER_PMI, &priv->shrd->status)) { |
f81c1f48 WYG |
105 | /* wake up nic if it's powered down ... |
106 | * uCode will wake up, and interrupt us again, so next | |
107 | * time we'll skip this part. */ | |
108 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
fd4abac5 | 109 | |
f81c1f48 WYG |
110 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
111 | IWL_DEBUG_INFO(priv, | |
112 | "Tx queue %d requesting wakeup," | |
113 | " GP1 = 0x%x\n", txq_id, reg); | |
114 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
115 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
116 | return; | |
117 | } | |
fd4abac5 | 118 | |
f81c1f48 | 119 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fd4abac5 | 120 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 121 | |
f81c1f48 WYG |
122 | /* |
123 | * else not in power-save mode, | |
124 | * uCode will never sleep when we're | |
125 | * trying to tx (during RFKILL, we're not trying to tx). | |
126 | */ | |
127 | } else | |
128 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
129 | txq->q.write_ptr | (txq_id << 8)); | |
130 | } | |
fd4abac5 | 131 | txq->need_update = 0; |
fd4abac5 | 132 | } |
fd4abac5 | 133 | |
214d14d4 JB |
134 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
135 | { | |
136 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
137 | ||
138 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
139 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
140 | addr |= | |
141 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
142 | ||
143 | return addr; | |
144 | } | |
145 | ||
146 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
147 | { | |
148 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
149 | ||
150 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
151 | } | |
152 | ||
153 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
154 | dma_addr_t addr, u16 len) | |
155 | { | |
156 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
157 | u16 hi_n_len = len << 4; | |
158 | ||
159 | put_unaligned_le32(addr, &tb->lo); | |
160 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
161 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
162 | ||
163 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
164 | ||
165 | tfd->num_tbs = idx + 1; | |
166 | } | |
167 | ||
168 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
169 | { | |
170 | return tfd->num_tbs & 0x1f; | |
171 | } | |
172 | ||
4ce7cc2b | 173 | static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta, |
253a634c | 174 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 175 | { |
214d14d4 JB |
176 | int i; |
177 | int num_tbs; | |
178 | ||
214d14d4 JB |
179 | /* Sanity check on number of chunks */ |
180 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
181 | ||
182 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
183 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
184 | /* @todo issue fatal error, it is quite serious situation */ | |
185 | return; | |
186 | } | |
187 | ||
188 | /* Unmap tx_cmd */ | |
189 | if (num_tbs) | |
d5934110 | 190 | dma_unmap_single(priv->bus->dev, |
4ce7cc2b JB |
191 | dma_unmap_addr(meta, mapping), |
192 | dma_unmap_len(meta, len), | |
795414db | 193 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
194 | |
195 | /* Unmap chunks, if any. */ | |
196 | for (i = 1; i < num_tbs; i++) | |
d5934110 | 197 | dma_unmap_single(priv->bus->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 198 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
199 | } |
200 | ||
201 | /** | |
202 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
203 | * @priv - driver private data | |
204 | * @txq - tx queue | |
1359ca4f | 205 | * @index - the index of the TFD to be freed |
4ce7cc2b JB |
206 | * |
207 | * Does NOT advance any TFD circular buffer read/write indexes | |
208 | * Does NOT free the TFD itself (which is within circular buffer) | |
209 | */ | |
1359ca4f EG |
210 | void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
211 | int index) | |
4ce7cc2b JB |
212 | { |
213 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 214 | |
e815407d | 215 | iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index], |
3be3fdb5 | 216 | DMA_TO_DEVICE); |
214d14d4 JB |
217 | |
218 | /* free SKB */ | |
219 | if (txq->txb) { | |
220 | struct sk_buff *skb; | |
221 | ||
1359ca4f | 222 | skb = txq->txb[index].skb; |
214d14d4 JB |
223 | |
224 | /* can be called from irqs-disabled context */ | |
225 | if (skb) { | |
226 | dev_kfree_skb_any(skb); | |
1359ca4f | 227 | txq->txb[index].skb = NULL; |
214d14d4 JB |
228 | } |
229 | } | |
230 | } | |
231 | ||
232 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
233 | struct iwl_tx_queue *txq, | |
234 | dma_addr_t addr, u16 len, | |
4c42db0f | 235 | u8 reset) |
214d14d4 JB |
236 | { |
237 | struct iwl_queue *q; | |
238 | struct iwl_tfd *tfd, *tfd_tmp; | |
239 | u32 num_tbs; | |
240 | ||
241 | q = &txq->q; | |
4ce7cc2b | 242 | tfd_tmp = txq->tfds; |
214d14d4 JB |
243 | tfd = &tfd_tmp[q->write_ptr]; |
244 | ||
245 | if (reset) | |
246 | memset(tfd, 0, sizeof(*tfd)); | |
247 | ||
248 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
249 | ||
250 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
251 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
252 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
253 | IWL_NUM_OF_TBS); | |
254 | return -EINVAL; | |
255 | } | |
256 | ||
257 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
258 | return -EINVAL; | |
259 | ||
260 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
261 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
262 | (unsigned long long)addr); | |
263 | ||
264 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
fd4abac5 TW |
269 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
270 | * DMA services | |
271 | * | |
272 | * Theory of operation | |
273 | * | |
274 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
275 | * of buffer descriptors, each of which points to one or more data buffers for | |
276 | * the device to read from or fill. Driver and device exchange status of each | |
277 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
278 | * entries in each circular buffer, to protect against confusing empty and full | |
279 | * queue states. | |
280 | * | |
281 | * The device reads or writes the data in the queues via the device's several | |
282 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
283 | * | |
284 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
285 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
286 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
287 | * Tx queue resumed. | |
288 | * | |
fd4abac5 TW |
289 | ***************************************************/ |
290 | ||
291 | int iwl_queue_space(const struct iwl_queue *q) | |
292 | { | |
293 | int s = q->read_ptr - q->write_ptr; | |
294 | ||
295 | if (q->read_ptr > q->write_ptr) | |
296 | s -= q->n_bd; | |
297 | ||
298 | if (s <= 0) | |
299 | s += q->n_window; | |
300 | /* keep some reserve to not confuse empty and full situations */ | |
301 | s -= 2; | |
302 | if (s < 0) | |
303 | s = 0; | |
304 | return s; | |
305 | } | |
fd4abac5 | 306 | |
1053d35f RR |
307 | /** |
308 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
309 | */ | |
02aca585 | 310 | int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
311 | int count, int slots_num, u32 id) |
312 | { | |
313 | q->n_bd = count; | |
314 | q->n_window = slots_num; | |
315 | q->id = id; | |
316 | ||
317 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
318 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
319 | if (WARN_ON(!is_power_of_2(count))) |
320 | return -EINVAL; | |
1053d35f RR |
321 | |
322 | /* slots_num must be power-of-two size, otherwise | |
323 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
324 | if (WARN_ON(!is_power_of_2(slots_num))) |
325 | return -EINVAL; | |
1053d35f RR |
326 | |
327 | q->low_mark = q->n_window / 4; | |
328 | if (q->low_mark < 4) | |
329 | q->low_mark = 4; | |
330 | ||
331 | q->high_mark = q->n_window / 8; | |
332 | if (q->high_mark < 2) | |
333 | q->high_mark = 2; | |
334 | ||
335 | q->write_ptr = q->read_ptr = 0; | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
04e1cabe | 340 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
48d42c42 EG |
341 | struct iwl_tx_queue *txq) |
342 | { | |
105183b1 EG |
343 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
344 | struct iwl_trans *trans = trans(priv); | |
345 | struct iwl_trans_pcie *trans_pcie = | |
346 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
347 | int txq_id = txq->q.id; |
348 | int read_ptr = txq->q.read_ptr; | |
349 | u8 sta_id = 0; | |
350 | __le16 bc_ent; | |
351 | ||
105183b1 EG |
352 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
353 | ||
48d42c42 EG |
354 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); |
355 | ||
cefeaa5f | 356 | if (txq_id != priv->shrd->cmd_queue) |
48d42c42 EG |
357 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
358 | ||
359 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
360 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
361 | ||
362 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
363 | scd_bc_tbl[txq_id]. | |
364 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
365 | } | |
366 | ||
367 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, | |
368 | u16 txq_id) | |
369 | { | |
370 | u32 tbl_dw_addr; | |
371 | u32 tbl_dw; | |
372 | u16 scd_q2ratid; | |
373 | ||
105183b1 EG |
374 | struct iwl_trans *trans = trans(priv); |
375 | struct iwl_trans_pcie *trans_pcie = | |
376 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
377 | ||
48d42c42 EG |
378 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
379 | ||
105183b1 | 380 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
381 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
382 | ||
383 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
384 | ||
385 | if (txq_id & 0x1) | |
386 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
387 | else | |
388 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
389 | ||
390 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
396 | { | |
397 | /* Simply stop the queue, but don't change any configuration; | |
398 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
399 | iwl_write_prph(priv, | |
400 | SCD_QUEUE_STATUS_BITS(txq_id), | |
401 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
402 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
403 | } | |
404 | ||
405 | void iwl_trans_set_wr_ptrs(struct iwl_priv *priv, | |
406 | int txq_id, u32 index) | |
407 | { | |
408 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
409 | (index & 0xff) | (txq_id << 8)); | |
410 | iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index); | |
411 | } | |
412 | ||
413 | void iwl_trans_tx_queue_set_status(struct iwl_priv *priv, | |
414 | struct iwl_tx_queue *txq, | |
415 | int tx_fifo_id, int scd_retry) | |
416 | { | |
417 | int txq_id = txq->q.id; | |
418 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; | |
419 | ||
420 | iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id), | |
421 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
422 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
423 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
424 | SCD_QUEUE_STTS_REG_MSK); | |
425 | ||
426 | txq->sched_retry = scd_retry; | |
427 | ||
428 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n", | |
429 | active ? "Activate" : "Deactivate", | |
430 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
431 | } | |
432 | ||
e6bb4c9c | 433 | void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid, |
48d42c42 EG |
434 | int frame_limit) |
435 | { | |
436 | int tx_fifo, txq_id, ssn_idx; | |
437 | u16 ra_tid; | |
438 | unsigned long flags; | |
439 | struct iwl_tid_data *tid_data; | |
440 | ||
105183b1 EG |
441 | struct iwl_trans *trans = trans(priv); |
442 | struct iwl_trans_pcie *trans_pcie = | |
443 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
444 | ||
48d42c42 EG |
445 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) |
446 | return; | |
447 | if (WARN_ON(tid >= MAX_TID_COUNT)) | |
448 | return; | |
449 | ||
f39c95e8 | 450 | spin_lock_irqsave(&priv->shrd->sta_lock, flags); |
48d42c42 EG |
451 | tid_data = &priv->stations[sta_id].tid[tid]; |
452 | ssn_idx = SEQ_TO_SN(tid_data->seq_number); | |
453 | txq_id = tid_data->agg.txq_id; | |
454 | tx_fifo = tid_data->agg.tx_fifo; | |
f39c95e8 | 455 | spin_unlock_irqrestore(&priv->shrd->sta_lock, flags); |
48d42c42 EG |
456 | |
457 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
458 | ||
10b15e6f | 459 | spin_lock_irqsave(&priv->shrd->lock, flags); |
48d42c42 EG |
460 | |
461 | /* Stop this Tx queue before configuring it */ | |
462 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
463 | ||
464 | /* Map receiver-address / traffic-ID to this queue */ | |
465 | iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
466 | ||
467 | /* Set this queue as a chain-building queue */ | |
468 | iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
469 | ||
470 | /* enable aggregations for the queue */ | |
471 | iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id)); | |
472 | ||
473 | /* Place first TFD at index corresponding to start sequence number. | |
474 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
475 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
476 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
477 | iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx); | |
478 | ||
479 | /* Set up Tx window size and frame limit for this queue */ | |
105183b1 | 480 | iwl_write_targ_mem(priv, trans_pcie->scd_base_addr + |
48d42c42 EG |
481 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
482 | sizeof(u32), | |
483 | ((frame_limit << | |
484 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
485 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
486 | ((frame_limit << | |
487 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
488 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
489 | ||
490 | iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); | |
491 | ||
492 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
493 | iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
494 | ||
a0eaad71 EG |
495 | priv->txq[txq_id].sta_id = sta_id; |
496 | priv->txq[txq_id].tid = tid; | |
497 | ||
10b15e6f | 498 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
48d42c42 EG |
499 | } |
500 | ||
e6bb4c9c | 501 | int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
48d42c42 EG |
502 | u16 ssn_idx, u8 tx_fifo) |
503 | { | |
504 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || | |
505 | (IWLAGN_FIRST_AMPDU_QUEUE + | |
506 | priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) { | |
507 | IWL_ERR(priv, | |
508 | "queue number out of range: %d, must be %d to %d\n", | |
509 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
510 | IWLAGN_FIRST_AMPDU_QUEUE + | |
511 | priv->cfg->base_params->num_of_ampdu_queues - 1); | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
516 | ||
517 | iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id)); | |
518 | ||
519 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
520 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
521 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
522 | iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx); | |
523 | ||
524 | iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); | |
525 | iwl_txq_ctx_deactivate(priv, txq_id); | |
526 | iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
fd4abac5 TW |
531 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
532 | ||
533 | /** | |
534 | * iwl_enqueue_hcmd - enqueue a uCode command | |
535 | * @priv: device private data point | |
536 | * @cmd: a point to the ucode command structure | |
537 | * | |
538 | * The function returns < 0 values to indicate the operation is | |
539 | * failed. On success, it turns the index (> 0) of command in the | |
540 | * command queue. | |
541 | */ | |
253a634c | 542 | static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
fd4abac5 | 543 | { |
cefeaa5f | 544 | struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue]; |
fd4abac5 | 545 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
546 | struct iwl_device_cmd *out_cmd; |
547 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 548 | dma_addr_t phys_addr; |
fd4abac5 | 549 | unsigned long flags; |
f3674227 | 550 | u32 idx; |
4ce7cc2b | 551 | u16 copy_size, cmd_size; |
0975cc8f | 552 | bool is_ct_kill = false; |
4ce7cc2b JB |
553 | bool had_nocopy = false; |
554 | int i; | |
555 | u8 *cmd_dest; | |
556 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
557 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
558 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
559 | int trace_idx; | |
560 | #endif | |
fd4abac5 | 561 | |
63013ae3 | 562 | if (test_bit(STATUS_FW_ERROR, &priv->shrd->status)) { |
3083d03c WYG |
563 | IWL_WARN(priv, "fw recovery, no hcmd send\n"); |
564 | return -EIO; | |
565 | } | |
566 | ||
eedb6e35 WYG |
567 | if ((priv->ucode_owner == IWL_OWNERSHIP_TM) && |
568 | !(cmd->flags & CMD_ON_DEMAND)) { | |
569 | IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n"); | |
570 | return -EIO; | |
571 | } | |
572 | ||
4ce7cc2b JB |
573 | copy_size = sizeof(out_cmd->hdr); |
574 | cmd_size = sizeof(out_cmd->hdr); | |
575 | ||
576 | /* need one for the header if the first is NOCOPY */ | |
577 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
578 | ||
579 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
580 | if (!cmd->len[i]) | |
581 | continue; | |
582 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
583 | had_nocopy = true; | |
584 | } else { | |
585 | /* NOCOPY must not be followed by normal! */ | |
586 | if (WARN_ON(had_nocopy)) | |
587 | return -EINVAL; | |
588 | copy_size += cmd->len[i]; | |
589 | } | |
590 | cmd_size += cmd->len[i]; | |
591 | } | |
fd4abac5 | 592 | |
3e41ace5 JB |
593 | /* |
594 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
595 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
596 | * allocated into separate TFDs, then we will need to | |
597 | * increase the size of the buffers. | |
3e41ace5 | 598 | */ |
4ce7cc2b | 599 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 600 | return -EINVAL; |
fd4abac5 | 601 | |
7812b167 | 602 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
603 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
604 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
605 | return -EIO; |
606 | } | |
7b21f00e | 607 | |
3598e177 SG |
608 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
609 | ||
c2acea8e | 610 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
3598e177 SG |
611 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
612 | ||
2d237f71 | 613 | IWL_ERR(priv, "No space in command queue\n"); |
f42e7662 | 614 | is_ct_kill = iwl_check_for_ct_kill(priv); |
0975cc8f | 615 | if (!is_ct_kill) { |
7812b167 | 616 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
e649437f | 617 | iwlagn_fw_error(priv, false); |
7812b167 | 618 | } |
fd4abac5 TW |
619 | return -ENOSPC; |
620 | } | |
621 | ||
4ce7cc2b | 622 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 623 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
624 | out_meta = &txq->meta[idx]; |
625 | ||
8ce73f3a | 626 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
627 | if (cmd->flags & CMD_WANT_SKB) |
628 | out_meta->source = cmd; | |
629 | if (cmd->flags & CMD_ASYNC) | |
630 | out_meta->callback = cmd->callback; | |
fd4abac5 | 631 | |
4ce7cc2b | 632 | /* set up the header */ |
fd4abac5 | 633 | |
4ce7cc2b | 634 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 635 | out_cmd->hdr.flags = 0; |
cefeaa5f EG |
636 | out_cmd->hdr.sequence = |
637 | cpu_to_le16(QUEUE_TO_SEQ(priv->shrd->cmd_queue) | | |
638 | INDEX_TO_SEQ(q->write_ptr)); | |
4ce7cc2b JB |
639 | |
640 | /* and copy the data that needs to be copied */ | |
641 | ||
642 | cmd_dest = &out_cmd->cmd.payload[0]; | |
643 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
644 | if (!cmd->len[i]) | |
645 | continue; | |
646 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
647 | break; | |
648 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
649 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 650 | } |
4ce7cc2b JB |
651 | |
652 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " | |
653 | "%d bytes at %d[%d]:%d\n", | |
654 | get_cmd_string(out_cmd->hdr.cmd), | |
655 | out_cmd->hdr.cmd, | |
656 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
cefeaa5f | 657 | q->write_ptr, idx, priv->shrd->cmd_queue); |
4ce7cc2b | 658 | |
d5934110 | 659 | phys_addr = dma_map_single(priv->bus->dev, &out_cmd->hdr, copy_size, |
795414db | 660 | DMA_BIDIRECTIONAL); |
d5934110 | 661 | if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) { |
2c46f72e JB |
662 | idx = -ENOMEM; |
663 | goto out; | |
664 | } | |
665 | ||
2e724443 | 666 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
667 | dma_unmap_len_set(out_meta, len, copy_size); |
668 | ||
669 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1); | |
670 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
671 | trace_bufs[0] = &out_cmd->hdr; | |
672 | trace_lens[0] = copy_size; | |
673 | trace_idx = 1; | |
674 | #endif | |
675 | ||
676 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
677 | if (!cmd->len[i]) | |
678 | continue; | |
679 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
680 | continue; | |
d5934110 | 681 | phys_addr = dma_map_single(priv->bus->dev, (void *)cmd->data[i], |
3be3fdb5 | 682 | cmd->len[i], DMA_BIDIRECTIONAL); |
d5934110 | 683 | if (dma_mapping_error(priv->bus->dev, phys_addr)) { |
4ce7cc2b | 684 | iwlagn_unmap_tfd(priv, out_meta, |
e815407d | 685 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 686 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
687 | idx = -ENOMEM; |
688 | goto out; | |
689 | } | |
690 | ||
691 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, | |
692 | cmd->len[i], 0); | |
693 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
694 | trace_bufs[trace_idx] = cmd->data[i]; | |
695 | trace_lens[trace_idx] = cmd->len[i]; | |
696 | trace_idx++; | |
697 | #endif | |
698 | } | |
df833b1d | 699 | |
afaf6b57 | 700 | out_meta->flags = cmd->flags; |
2c46f72e JB |
701 | |
702 | txq->need_update = 1; | |
703 | ||
4ce7cc2b JB |
704 | /* check that tracing gets all possible blocks */ |
705 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
706 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
707 | trace_iwlwifi_dev_hcmd(priv, cmd->flags, | |
708 | trace_bufs[0], trace_lens[0], | |
709 | trace_bufs[1], trace_lens[1], | |
710 | trace_bufs[2], trace_lens[2]); | |
711 | #endif | |
df833b1d | 712 | |
fd4abac5 TW |
713 | /* Increment and update queue's write index */ |
714 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 715 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 | 716 | |
2c46f72e | 717 | out: |
fd4abac5 | 718 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
7bfedc59 | 719 | return idx; |
fd4abac5 TW |
720 | } |
721 | ||
17b88929 TW |
722 | /** |
723 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
724 | * | |
725 | * When FW advances 'R' index, all entries between old and new 'R' index | |
726 | * need to be reclaimed. As result, some free space forms. If there is | |
727 | * enough free space (> low mark), wake the stack that feeds us. | |
728 | */ | |
20ba2861 | 729 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) |
17b88929 TW |
730 | { |
731 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
732 | struct iwl_queue *q = &txq->q; | |
733 | int nfreed = 0; | |
734 | ||
499b1883 | 735 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
2e5d04da DH |
736 | IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), " |
737 | "index %d is out of range [0-%d] %d %d.\n", __func__, | |
738 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
739 | return; |
740 | } | |
741 | ||
499b1883 TW |
742 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
743 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 744 | |
499b1883 | 745 | if (nfreed++ > 0) { |
15b1687c | 746 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 747 | q->write_ptr, q->read_ptr); |
e649437f | 748 | iwlagn_fw_error(priv, false); |
17b88929 | 749 | } |
da99c4b6 | 750 | |
17b88929 TW |
751 | } |
752 | } | |
753 | ||
754 | /** | |
755 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
756 | * @rxb: Rx buffer to reclaim | |
757 | * | |
758 | * If an Rx buffer has an async callback associated with it the callback | |
759 | * will be executed. The attached skb (if present) will only be freed | |
760 | * if the callback returns 1 | |
761 | */ | |
762 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
763 | { | |
2f301227 | 764 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
765 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
766 | int txq_id = SEQ_TO_QUEUE(sequence); | |
767 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 768 | int cmd_index; |
c2acea8e JB |
769 | struct iwl_device_cmd *cmd; |
770 | struct iwl_cmd_meta *meta; | |
cefeaa5f | 771 | struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue]; |
3598e177 | 772 | unsigned long flags; |
17b88929 TW |
773 | |
774 | /* If a Tx command is being handled and it isn't in the actual | |
775 | * command queue then there a command routing bug has been introduced | |
776 | * in the queue management code. */ | |
cefeaa5f | 777 | if (WARN(txq_id != priv->shrd->cmd_queue, |
13bb9483 | 778 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
cefeaa5f EG |
779 | txq_id, priv->shrd->cmd_queue, sequence, |
780 | priv->txq[priv->shrd->cmd_queue].q.read_ptr, | |
781 | priv->txq[priv->shrd->cmd_queue].q.write_ptr)) { | |
ec741164 | 782 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 783 | return; |
01ef9323 | 784 | } |
17b88929 | 785 | |
4ce7cc2b | 786 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
787 | cmd = txq->cmd[cmd_index]; |
788 | meta = &txq->meta[cmd_index]; | |
17b88929 | 789 | |
3be3fdb5 | 790 | iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 791 | |
17b88929 | 792 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 793 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
794 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
795 | rxb->page = NULL; | |
2624e96c SG |
796 | } else if (meta->callback) |
797 | meta->callback(priv, cmd, pkt); | |
798 | ||
799 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
17b88929 | 800 | |
20ba2861 | 801 | iwl_hcmd_queue_reclaim(priv, txq_id, index); |
17b88929 | 802 | |
c2acea8e | 803 | if (!(meta->flags & CMD_ASYNC)) { |
63013ae3 | 804 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
91dd6c27 | 805 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 806 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
807 | wake_up_interruptible(&priv->wait_command_queue); |
808 | } | |
3598e177 | 809 | |
dd487449 | 810 | meta->flags = 0; |
3598e177 SG |
811 | |
812 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
17b88929 | 813 | } |
253a634c EG |
814 | |
815 | const char *get_cmd_string(u8 cmd) | |
816 | { | |
817 | switch (cmd) { | |
818 | IWL_CMD(REPLY_ALIVE); | |
819 | IWL_CMD(REPLY_ERROR); | |
820 | IWL_CMD(REPLY_RXON); | |
821 | IWL_CMD(REPLY_RXON_ASSOC); | |
822 | IWL_CMD(REPLY_QOS_PARAM); | |
823 | IWL_CMD(REPLY_RXON_TIMING); | |
824 | IWL_CMD(REPLY_ADD_STA); | |
825 | IWL_CMD(REPLY_REMOVE_STA); | |
826 | IWL_CMD(REPLY_REMOVE_ALL_STA); | |
827 | IWL_CMD(REPLY_TXFIFO_FLUSH); | |
828 | IWL_CMD(REPLY_WEPKEY); | |
829 | IWL_CMD(REPLY_TX); | |
830 | IWL_CMD(REPLY_LEDS_CMD); | |
831 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | |
832 | IWL_CMD(COEX_PRIORITY_TABLE_CMD); | |
833 | IWL_CMD(COEX_MEDIUM_NOTIFICATION); | |
834 | IWL_CMD(COEX_EVENT_CMD); | |
835 | IWL_CMD(REPLY_QUIET_CMD); | |
836 | IWL_CMD(REPLY_CHANNEL_SWITCH); | |
837 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | |
838 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | |
839 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | |
840 | IWL_CMD(POWER_TABLE_CMD); | |
841 | IWL_CMD(PM_SLEEP_NOTIFICATION); | |
842 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | |
843 | IWL_CMD(REPLY_SCAN_CMD); | |
844 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | |
845 | IWL_CMD(SCAN_START_NOTIFICATION); | |
846 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | |
847 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | |
848 | IWL_CMD(BEACON_NOTIFICATION); | |
849 | IWL_CMD(REPLY_TX_BEACON); | |
850 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | |
851 | IWL_CMD(QUIET_NOTIFICATION); | |
852 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | |
853 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | |
854 | IWL_CMD(REPLY_BT_CONFIG); | |
855 | IWL_CMD(REPLY_STATISTICS_CMD); | |
856 | IWL_CMD(STATISTICS_NOTIFICATION); | |
857 | IWL_CMD(REPLY_CARD_STATE_CMD); | |
858 | IWL_CMD(CARD_STATE_NOTIFICATION); | |
859 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | |
860 | IWL_CMD(REPLY_CT_KILL_CONFIG_CMD); | |
861 | IWL_CMD(SENSITIVITY_CMD); | |
862 | IWL_CMD(REPLY_PHY_CALIBRATION_CMD); | |
863 | IWL_CMD(REPLY_RX_PHY_CMD); | |
864 | IWL_CMD(REPLY_RX_MPDU_CMD); | |
865 | IWL_CMD(REPLY_RX); | |
866 | IWL_CMD(REPLY_COMPRESSED_BA); | |
867 | IWL_CMD(CALIBRATION_CFG_CMD); | |
868 | IWL_CMD(CALIBRATION_RES_NOTIFICATION); | |
869 | IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION); | |
870 | IWL_CMD(REPLY_TX_POWER_DBM_CMD); | |
871 | IWL_CMD(TEMPERATURE_NOTIFICATION); | |
872 | IWL_CMD(TX_ANT_CONFIGURATION_CMD); | |
873 | IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF); | |
874 | IWL_CMD(REPLY_BT_COEX_PRIO_TABLE); | |
875 | IWL_CMD(REPLY_BT_COEX_PROT_ENV); | |
876 | IWL_CMD(REPLY_WIPAN_PARAMS); | |
877 | IWL_CMD(REPLY_WIPAN_RXON); | |
878 | IWL_CMD(REPLY_WIPAN_RXON_TIMING); | |
879 | IWL_CMD(REPLY_WIPAN_RXON_ASSOC); | |
880 | IWL_CMD(REPLY_WIPAN_QOS_PARAM); | |
881 | IWL_CMD(REPLY_WIPAN_WEPKEY); | |
882 | IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH); | |
883 | IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION); | |
884 | IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE); | |
c8ac61cf JB |
885 | IWL_CMD(REPLY_WOWLAN_PATTERNS); |
886 | IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER); | |
887 | IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS); | |
888 | IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS); | |
889 | IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL); | |
890 | IWL_CMD(REPLY_WOWLAN_GET_STATUS); | |
253a634c EG |
891 | default: |
892 | return "UNKNOWN"; | |
893 | ||
894 | } | |
895 | } | |
896 | ||
897 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) | |
898 | ||
899 | static void iwl_generic_cmd_callback(struct iwl_priv *priv, | |
900 | struct iwl_device_cmd *cmd, | |
901 | struct iwl_rx_packet *pkt) | |
902 | { | |
903 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
904 | IWL_ERR(priv, "Bad return from %s (0x%08X)\n", | |
905 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | |
906 | return; | |
907 | } | |
908 | ||
909 | #ifdef CONFIG_IWLWIFI_DEBUG | |
910 | switch (cmd->hdr.cmd) { | |
911 | case REPLY_TX_LINK_QUALITY_CMD: | |
912 | case SENSITIVITY_CMD: | |
913 | IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n", | |
914 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | |
915 | break; | |
916 | default: | |
917 | IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n", | |
918 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | |
919 | } | |
920 | #endif | |
921 | } | |
922 | ||
923 | static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
924 | { | |
925 | int ret; | |
926 | ||
927 | /* An asynchronous command can not expect an SKB to be set. */ | |
928 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
929 | return -EINVAL; | |
930 | ||
931 | /* Assign a generic callback if one is not provided */ | |
932 | if (!cmd->callback) | |
933 | cmd->callback = iwl_generic_cmd_callback; | |
934 | ||
63013ae3 | 935 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
253a634c EG |
936 | return -EBUSY; |
937 | ||
938 | ret = iwl_enqueue_hcmd(priv, cmd); | |
939 | if (ret < 0) { | |
940 | IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n", | |
941 | get_cmd_string(cmd->id), ret); | |
942 | return ret; | |
943 | } | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
948 | { | |
949 | int cmd_idx; | |
950 | int ret; | |
951 | ||
6ac2f839 | 952 | lockdep_assert_held(&priv->shrd->mutex); |
253a634c EG |
953 | |
954 | /* A synchronous command can not have a callback set. */ | |
955 | if (WARN_ON(cmd->callback)) | |
956 | return -EINVAL; | |
957 | ||
958 | IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n", | |
959 | get_cmd_string(cmd->id)); | |
960 | ||
63013ae3 | 961 | set_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
253a634c EG |
962 | IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n", |
963 | get_cmd_string(cmd->id)); | |
964 | ||
965 | cmd_idx = iwl_enqueue_hcmd(priv, cmd); | |
966 | if (cmd_idx < 0) { | |
967 | ret = cmd_idx; | |
63013ae3 | 968 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
253a634c EG |
969 | IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n", |
970 | get_cmd_string(cmd->id), ret); | |
971 | return ret; | |
972 | } | |
973 | ||
974 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
63013ae3 | 975 | !test_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status), |
253a634c EG |
976 | HOST_COMPLETE_TIMEOUT); |
977 | if (!ret) { | |
63013ae3 | 978 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status)) { |
253a634c EG |
979 | IWL_ERR(priv, |
980 | "Error sending %s: time out after %dms.\n", | |
981 | get_cmd_string(cmd->id), | |
982 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
983 | ||
63013ae3 | 984 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
253a634c EG |
985 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command" |
986 | "%s\n", get_cmd_string(cmd->id)); | |
987 | ret = -ETIMEDOUT; | |
988 | goto cancel; | |
989 | } | |
990 | } | |
991 | ||
63013ae3 | 992 | if (test_bit(STATUS_RF_KILL_HW, &priv->shrd->status)) { |
253a634c EG |
993 | IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n", |
994 | get_cmd_string(cmd->id)); | |
995 | ret = -ECANCELED; | |
996 | goto fail; | |
997 | } | |
63013ae3 | 998 | if (test_bit(STATUS_FW_ERROR, &priv->shrd->status)) { |
253a634c EG |
999 | IWL_ERR(priv, "Command %s failed: FW Error\n", |
1000 | get_cmd_string(cmd->id)); | |
1001 | ret = -EIO; | |
1002 | goto fail; | |
1003 | } | |
1004 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { | |
1005 | IWL_ERR(priv, "Error: Response NULL in '%s'\n", | |
1006 | get_cmd_string(cmd->id)); | |
1007 | ret = -EIO; | |
1008 | goto cancel; | |
1009 | } | |
1010 | ||
1011 | return 0; | |
1012 | ||
1013 | cancel: | |
1014 | if (cmd->flags & CMD_WANT_SKB) { | |
1015 | /* | |
1016 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1017 | * TX cmd queue. Otherwise in case the cmd comes | |
1018 | * in later, it will possibly set an invalid | |
1019 | * address (cmd->meta.source). | |
1020 | */ | |
cefeaa5f | 1021 | priv->txq[priv->shrd->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
1022 | ~CMD_WANT_SKB; |
1023 | } | |
1024 | fail: | |
1025 | if (cmd->reply_page) { | |
1026 | iwl_free_pages(priv, cmd->reply_page); | |
1027 | cmd->reply_page = 0; | |
1028 | } | |
1029 | ||
1030 | return ret; | |
1031 | } | |
1032 | ||
e6bb4c9c | 1033 | int iwl_trans_pcie_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
253a634c EG |
1034 | { |
1035 | if (cmd->flags & CMD_ASYNC) | |
1036 | return iwl_send_cmd_async(priv, cmd); | |
1037 | ||
1038 | return iwl_send_cmd_sync(priv, cmd); | |
1039 | } | |
1040 | ||
e6bb4c9c EG |
1041 | int iwl_trans_pcie_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags, |
1042 | u16 len, const void *data) | |
253a634c EG |
1043 | { |
1044 | struct iwl_host_cmd cmd = { | |
1045 | .id = id, | |
1046 | .len = { len, }, | |
1047 | .data = { data, }, | |
1048 | .flags = flags, | |
1049 | }; | |
1050 | ||
e6bb4c9c | 1051 | return iwl_trans_pcie_send_cmd(priv, &cmd); |
253a634c | 1052 | } |
a0eaad71 EG |
1053 | |
1054 | /* Frees buffers until index _not_ inclusive */ | |
1055 | void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, | |
1056 | struct sk_buff_head *skbs) | |
a0eaad71 EG |
1057 | { |
1058 | struct iwl_tx_queue *txq = &priv(trans)->txq[txq_id]; | |
1059 | struct iwl_queue *q = &txq->q; | |
1060 | struct iwl_tx_info *tx_info; | |
1061 | struct ieee80211_tx_info *info; | |
1062 | int last_to_free; | |
1063 | ||
1064 | /*Since we free until index _not_ inclusive, the one before index is | |
1065 | * the last we will free. This one must be used */ | |
1066 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
1067 | ||
1068 | if ((index >= q->n_bd) || | |
1069 | (iwl_queue_used(q, last_to_free) == 0)) { | |
1070 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
1071 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
1072 | __func__, txq_id, last_to_free, q->n_bd, | |
1073 | q->write_ptr, q->read_ptr); | |
1074 | return; | |
1075 | } | |
1076 | ||
1077 | IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id, | |
1078 | q->read_ptr, index); | |
1079 | ||
1080 | if (WARN_ON(!skb_queue_empty(skbs))) | |
1081 | return; | |
1082 | ||
1083 | for (; | |
1084 | q->read_ptr != index; | |
1085 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1086 | ||
1087 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1088 | ||
1089 | if (WARN_ON_ONCE(tx_info->skb == NULL)) | |
1090 | continue; | |
1091 | ||
1092 | info = IEEE80211_SKB_CB(tx_info->skb); | |
1093 | info->driver_data[0] = tx_info->ctx; | |
1094 | ||
1095 | __skb_queue_tail(skbs, tx_info->skb); | |
1096 | ||
1097 | tx_info->skb = NULL; | |
1098 | ||
1099 | iwlagn_txq_inval_byte_cnt_tbl(priv(trans), txq); | |
1100 | ||
1101 | iwlagn_txq_free_tfd(priv(trans), txq, txq->q.read_ptr); | |
1102 | } | |
1103 | } |