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iwlagn: SCD configuration for AMPDU moves to transport layer
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl-trans-tx-pcie.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
1053d35f
RR		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
1053d35f
RR		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
fd4abac5 29#include <linux/etherdevice.h>
5a0e3ad6 30#include <linux/slab.h>
253a634c 31#include <linux/sched.h>
1053d35f 32#include <net/mac80211.h>
253a634c 33
214d14d4 34#include "iwl-agn.h"
1053d35f
RR		 35#include "iwl-dev.h"
36#include "iwl-core.h"
1053d35f 37#include "iwl-io.h"
48d42c42 38#include "iwl-sta.h"
1053d35f 39#include "iwl-helpers.h"
253a634c 40#include "iwl-trans-int-pcie.h"
1053d35f 41
48d42c42
EG		 42/* TODO:this file should _not_ include the external API header file
43 * (iwl-trans.h). This is needed as a W/A until reclaim functions will move to
44 * the transport layer */
45#include "iwl-trans.h"
46
47/**
48 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
49 */
50void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
51 struct iwl_tx_queue *txq,
52 u16 byte_cnt)
53{
54 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
55 int write_ptr = txq->q.write_ptr;
56 int txq_id = txq->q.id;
57 u8 sec_ctl = 0;
58 u8 sta_id = 0;
59 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
60 __le16 bc_ent;
61
62 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
63
64 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
65 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
66
67 switch (sec_ctl & TX_CMD_SEC_MSK) {
68 case TX_CMD_SEC_CCM:
69 len += CCMP_MIC_LEN;
70 break;
71 case TX_CMD_SEC_TKIP:
72 len += TKIP_ICV_LEN;
73 break;
74 case TX_CMD_SEC_WEP:
75 len += WEP_IV_LEN + WEP_ICV_LEN;
76 break;
77 }
78
79 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
80
81 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
82
83 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
84 scd_bc_tbl[txq_id].
85 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
86}
87
fd4abac5
TW		 88/**
89 * iwl_txq_update_write_ptr - Send new write index to hardware
90 */
7bfedc59 91void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
fd4abac5
TW		 92{
93 u32 reg = 0;
fd4abac5
TW		 94 int txq_id = txq->q.id;
95
96 if (txq->need_update == 0)
7bfedc59 97 return;
fd4abac5 98
f81c1f48
WYG		 99 if (priv->cfg->base_params->shadow_reg_enable) {
100 /* shadow register enabled */
101 iwl_write32(priv, HBUS_TARG_WRPTR,
102 txq->q.write_ptr | (txq_id << 8));
103 } else {
104 /* if we're trying to save power */
105 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
106 /* wake up nic if it's powered down ...
107 * uCode will wake up, and interrupt us again, so next
108 * time we'll skip this part. */
109 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
fd4abac5 110
f81c1f48
WYG		 111 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
112 IWL_DEBUG_INFO(priv,
113 "Tx queue %d requesting wakeup,"
114 " GP1 = 0x%x\n", txq_id, reg);
115 iwl_set_bit(priv, CSR_GP_CNTRL,
116 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
117 return;
118 }
fd4abac5 119
f81c1f48 120 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fd4abac5 121 txq->q.write_ptr | (txq_id << 8));
fd4abac5 122
f81c1f48
WYG		 123 /*
124 * else not in power-save mode,
125 * uCode will never sleep when we're
126 * trying to tx (during RFKILL, we're not trying to tx).
127 */
128 } else
129 iwl_write32(priv, HBUS_TARG_WRPTR,
130 txq->q.write_ptr | (txq_id << 8));
131 }
fd4abac5 132 txq->need_update = 0;
fd4abac5 133}
fd4abac5 134
214d14d4
JB		 135static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
136{
137 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
138
139 dma_addr_t addr = get_unaligned_le32(&tb->lo);
140 if (sizeof(dma_addr_t) > sizeof(u32))
141 addr |=
142 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
143
144 return addr;
145}
146
147static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
148{
149 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
150
151 return le16_to_cpu(tb->hi_n_len) >> 4;
152}
153
154static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
155 dma_addr_t addr, u16 len)
156{
157 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
158 u16 hi_n_len = len << 4;
159
160 put_unaligned_le32(addr, &tb->lo);
161 if (sizeof(dma_addr_t) > sizeof(u32))
162 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
163
164 tb->hi_n_len = cpu_to_le16(hi_n_len);
165
166 tfd->num_tbs = idx + 1;
167}
168
169static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
170{
171 return tfd->num_tbs & 0x1f;
172}
173
4ce7cc2b 174static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
253a634c 175 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
214d14d4 176{
214d14d4
JB		 177 int i;
178 int num_tbs;
179
214d14d4
JB		 180 /* Sanity check on number of chunks */
181 num_tbs = iwl_tfd_get_num_tbs(tfd);
182
183 if (num_tbs >= IWL_NUM_OF_TBS) {
184 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
185 /* @todo issue fatal error, it is quite serious situation */
186 return;
187 }
188
189 /* Unmap tx_cmd */
190 if (num_tbs)
795414db 191 dma_unmap_single(priv->bus.dev,
4ce7cc2b
JB		 192 dma_unmap_addr(meta, mapping),
193 dma_unmap_len(meta, len),
795414db 194 DMA_BIDIRECTIONAL);
214d14d4
JB		 195
196 /* Unmap chunks, if any. */
197 for (i = 1; i < num_tbs; i++)
795414db 198 dma_unmap_single(priv->bus.dev, iwl_tfd_tb_get_addr(tfd, i),
e815407d 199 iwl_tfd_tb_get_len(tfd, i), dma_dir);
4ce7cc2b
JB		 200}
201
202/**
203 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
204 * @priv - driver private data
205 * @txq - tx queue
1359ca4f 206 * @index - the index of the TFD to be freed
4ce7cc2b
JB		 207 *
208 * Does NOT advance any TFD circular buffer read/write indexes
209 * Does NOT free the TFD itself (which is within circular buffer)
210 */
1359ca4f
EG		 211void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
212 int index)
4ce7cc2b
JB		 213{
214 struct iwl_tfd *tfd_tmp = txq->tfds;
4ce7cc2b 215
e815407d 216 iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index],
3be3fdb5 217 DMA_TO_DEVICE);
214d14d4
JB		 218
219 /* free SKB */
220 if (txq->txb) {
221 struct sk_buff *skb;
222
1359ca4f 223 skb = txq->txb[index].skb;
214d14d4
JB		 224
225 /* can be called from irqs-disabled context */
226 if (skb) {
227 dev_kfree_skb_any(skb);
1359ca4f 228 txq->txb[index].skb = NULL;
214d14d4
JB		 229 }
230 }
231}
232
233int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
234 struct iwl_tx_queue *txq,
235 dma_addr_t addr, u16 len,
4c42db0f 236 u8 reset)
214d14d4
JB		 237{
238 struct iwl_queue *q;
239 struct iwl_tfd *tfd, *tfd_tmp;
240 u32 num_tbs;
241
242 q = &txq->q;
4ce7cc2b 243 tfd_tmp = txq->tfds;
214d14d4
JB		 244 tfd = &tfd_tmp[q->write_ptr];
245
246 if (reset)
247 memset(tfd, 0, sizeof(*tfd));
248
249 num_tbs = iwl_tfd_get_num_tbs(tfd);
250
251 /* Each TFD can point to a maximum 20 Tx buffers */
252 if (num_tbs >= IWL_NUM_OF_TBS) {
253 IWL_ERR(priv, "Error can not send more than %d chunks\n",
254 IWL_NUM_OF_TBS);
255 return -EINVAL;
256 }
257
258 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
259 return -EINVAL;
260
261 if (unlikely(addr & ~IWL_TX_DMA_MASK))
262 IWL_ERR(priv, "Unaligned address = %llx\n",
263 (unsigned long long)addr);
264
265 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
266
267 return 0;
268}
269
fd4abac5
TW		 270/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
271 * DMA services
272 *
273 * Theory of operation
274 *
275 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
276 * of buffer descriptors, each of which points to one or more data buffers for
277 * the device to read from or fill. Driver and device exchange status of each
278 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
279 * entries in each circular buffer, to protect against confusing empty and full
280 * queue states.
281 *
282 * The device reads or writes the data in the queues via the device's several
283 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
284 *
285 * For Tx queue, there are low mark and high mark limits. If, after queuing
286 * the packet for Tx, free space become < low mark, Tx queue stopped. When
287 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
288 * Tx queue resumed.
289 *
fd4abac5
TW		 290 ***************************************************/
291
292int iwl_queue_space(const struct iwl_queue *q)
293{
294 int s = q->read_ptr - q->write_ptr;
295
296 if (q->read_ptr > q->write_ptr)
297 s -= q->n_bd;
298
299 if (s <= 0)
300 s += q->n_window;
301 /* keep some reserve to not confuse empty and full situations */
302 s -= 2;
303 if (s < 0)
304 s = 0;
305 return s;
306}
fd4abac5 307
1053d35f
RR		 308/**
309 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
310 */
02aca585 311int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 312 int count, int slots_num, u32 id)
313{
314 q->n_bd = count;
315 q->n_window = slots_num;
316 q->id = id;
317
318 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
319 * and iwl_queue_dec_wrap are broken. */
3e41ace5
JB		 320 if (WARN_ON(!is_power_of_2(count)))
321 return -EINVAL;
1053d35f
RR		 322
323 /* slots_num must be power-of-two size, otherwise
324 * get_cmd_index is broken. */
3e41ace5
JB		 325 if (WARN_ON(!is_power_of_2(slots_num)))
326 return -EINVAL;
1053d35f
RR		 327
328 q->low_mark = q->n_window / 4;
329 if (q->low_mark < 4)
330 q->low_mark = 4;
331
332 q->high_mark = q->n_window / 8;
333 if (q->high_mark < 2)
334 q->high_mark = 2;
335
336 q->write_ptr = q->read_ptr = 0;
337
338 return 0;
339}
340
48d42c42
EG		 341/*TODO: this functions should NOT be exported from trans module - export it
342 * until the reclaim flow will be brought to the transport module too */
343void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
344 struct iwl_tx_queue *txq)
345{
346 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
347 int txq_id = txq->q.id;
348 int read_ptr = txq->q.read_ptr;
349 u8 sta_id = 0;
350 __le16 bc_ent;
351
352 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
353
354 if (txq_id != priv->cmd_queue)
355 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
356
357 bc_ent = cpu_to_le16(1 | (sta_id << 12));
358 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
359
360 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
361 scd_bc_tbl[txq_id].
362 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
363}
364
365static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
366 u16 txq_id)
367{
368 u32 tbl_dw_addr;
369 u32 tbl_dw;
370 u16 scd_q2ratid;
371
372 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
373
374 tbl_dw_addr = priv->scd_base_addr +
375 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
376
377 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
378
379 if (txq_id & 0x1)
380 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
381 else
382 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
383
384 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
385
386 return 0;
387}
388
389static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
390{
391 /* Simply stop the queue, but don't change any configuration;
392 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
393 iwl_write_prph(priv,
394 SCD_QUEUE_STATUS_BITS(txq_id),
395 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
396 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
397}
398
399void iwl_trans_set_wr_ptrs(struct iwl_priv *priv,
400 int txq_id, u32 index)
401{
402 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
403 (index & 0xff) | (txq_id << 8));
404 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
405}
406
407void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
408 struct iwl_tx_queue *txq,
409 int tx_fifo_id, int scd_retry)
410{
411 int txq_id = txq->q.id;
412 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
413
414 iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
415 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
416 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
417 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
418 SCD_QUEUE_STTS_REG_MSK);
419
420 txq->sched_retry = scd_retry;
421
422 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
423 active ? "Activate" : "Deactivate",
424 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
425}
426
427void iwl_trans_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
428 int frame_limit)
429{
430 int tx_fifo, txq_id, ssn_idx;
431 u16 ra_tid;
432 unsigned long flags;
433 struct iwl_tid_data *tid_data;
434
435 if (WARN_ON(sta_id == IWL_INVALID_STATION))
436 return;
437 if (WARN_ON(tid >= MAX_TID_COUNT))
438 return;
439
440 spin_lock_irqsave(&priv->sta_lock, flags);
441 tid_data = &priv->stations[sta_id].tid[tid];
442 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
443 txq_id = tid_data->agg.txq_id;
444 tx_fifo = tid_data->agg.tx_fifo;
445 spin_unlock_irqrestore(&priv->sta_lock, flags);
446
447 ra_tid = BUILD_RAxTID(sta_id, tid);
448
449 spin_lock_irqsave(&priv->lock, flags);
450
451 /* Stop this Tx queue before configuring it */
452 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
453
454 /* Map receiver-address / traffic-ID to this queue */
455 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
456
457 /* Set this queue as a chain-building queue */
458 iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
459
460 /* enable aggregations for the queue */
461 iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id));
462
463 /* Place first TFD at index corresponding to start sequence number.
464 * Assumes that ssn_idx is valid (!= 0xFFF) */
465 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
466 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
467 iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
468
469 /* Set up Tx window size and frame limit for this queue */
470 iwl_write_targ_mem(priv, priv->scd_base_addr +
471 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
472 sizeof(u32),
473 ((frame_limit <<
474 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
475 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
476 ((frame_limit <<
477 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
478 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
479
480 iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
481
482 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
483 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
484
485 spin_unlock_irqrestore(&priv->lock, flags);
486}
487
488int iwl_trans_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
489 u16 ssn_idx, u8 tx_fifo)
490{
491 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
492 (IWLAGN_FIRST_AMPDU_QUEUE +
493 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
494 IWL_ERR(priv,
495 "queue number out of range: %d, must be %d to %d\n",
496 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
497 IWLAGN_FIRST_AMPDU_QUEUE +
498 priv->cfg->base_params->num_of_ampdu_queues - 1);
499 return -EINVAL;
500 }
501
502 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
503
504 iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id));
505
506 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
507 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
508 /* supposes that ssn_idx is valid (!= 0xFFF) */
509 iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
510
511 iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
512 iwl_txq_ctx_deactivate(priv, txq_id);
513 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
514
515 return 0;
516}
517
fd4abac5
TW		 518/*************** HOST COMMAND QUEUE FUNCTIONS *****/
519
520/**
521 * iwl_enqueue_hcmd - enqueue a uCode command
522 * @priv: device private data point
523 * @cmd: a point to the ucode command structure
524 *
525 * The function returns < 0 values to indicate the operation is
526 * failed. On success, it turns the index (> 0) of command in the
527 * command queue.
528 */
253a634c 529static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
fd4abac5 530{
13bb9483 531 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
fd4abac5 532 struct iwl_queue *q = &txq->q;
c2acea8e
JB		 533 struct iwl_device_cmd *out_cmd;
534 struct iwl_cmd_meta *out_meta;
fd4abac5 535 dma_addr_t phys_addr;
fd4abac5 536 unsigned long flags;
f3674227 537 u32 idx;
4ce7cc2b 538 u16 copy_size, cmd_size;
0975cc8f 539 bool is_ct_kill = false;
4ce7cc2b
JB		 540 bool had_nocopy = false;
541 int i;
542 u8 *cmd_dest;
543#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
544 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
545 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
546 int trace_idx;
547#endif
fd4abac5 548
3083d03c
WYG		 549 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
550 IWL_WARN(priv, "fw recovery, no hcmd send\n");
551 return -EIO;
552 }
553
eedb6e35
WYG		 554 if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
555 !(cmd->flags & CMD_ON_DEMAND)) {
556 IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n");
557 return -EIO;
558 }
559
4ce7cc2b
JB		 560 copy_size = sizeof(out_cmd->hdr);
561 cmd_size = sizeof(out_cmd->hdr);
562
563 /* need one for the header if the first is NOCOPY */
564 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
565
566 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
567 if (!cmd->len[i])
568 continue;
569 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
570 had_nocopy = true;
571 } else {
572 /* NOCOPY must not be followed by normal! */
573 if (WARN_ON(had_nocopy))
574 return -EINVAL;
575 copy_size += cmd->len[i];
576 }
577 cmd_size += cmd->len[i];
578 }
fd4abac5 579
3e41ace5
JB		 580 /*
581 * If any of the command structures end up being larger than
4ce7cc2b
JB		 582 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
583 * allocated into separate TFDs, then we will need to
584 * increase the size of the buffers.
3e41ace5 585 */
4ce7cc2b 586 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
3e41ace5 587 return -EINVAL;
fd4abac5 588
7812b167 589 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
f2f21b49
RC		 590 IWL_WARN(priv, "Not sending command - %s KILL\n",
591 iwl_is_rfkill(priv) ? "RF" : "CT");
fd4abac5
TW		 592 return -EIO;
593 }
7b21f00e 594
3598e177
SG		 595 spin_lock_irqsave(&priv->hcmd_lock, flags);
596
c2acea8e 597 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3598e177
SG		 598 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
599
2d237f71 600 IWL_ERR(priv, "No space in command queue\n");
f42e7662 601 is_ct_kill = iwl_check_for_ct_kill(priv);
0975cc8f 602 if (!is_ct_kill) {
7812b167 603 IWL_ERR(priv, "Restarting adapter due to queue full\n");
e649437f 604 iwlagn_fw_error(priv, false);
7812b167 605 }
fd4abac5
TW		 606 return -ENOSPC;
607 }
608
4ce7cc2b 609 idx = get_cmd_index(q, q->write_ptr);
da99c4b6 610 out_cmd = txq->cmd[idx];
c2acea8e
JB		 611 out_meta = &txq->meta[idx];
612
8ce73f3a 613 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
c2acea8e
JB		 614 if (cmd->flags & CMD_WANT_SKB)
615 out_meta->source = cmd;
616 if (cmd->flags & CMD_ASYNC)
617 out_meta->callback = cmd->callback;
fd4abac5 618
4ce7cc2b 619 /* set up the header */
fd4abac5 620
4ce7cc2b 621 out_cmd->hdr.cmd = cmd->id;
fd4abac5 622 out_cmd->hdr.flags = 0;
13bb9483 623 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
4ce7cc2b
JB		 624 INDEX_TO_SEQ(q->write_ptr));
625
626 /* and copy the data that needs to be copied */
627
628 cmd_dest = &out_cmd->cmd.payload[0];
629 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
630 if (!cmd->len[i])
631 continue;
632 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
633 break;
634 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
635 cmd_dest += cmd->len[i];
ded2ae7c 636 }
4ce7cc2b
JB		 637
638 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
639 "%d bytes at %d[%d]:%d\n",
640 get_cmd_string(out_cmd->hdr.cmd),
641 out_cmd->hdr.cmd,
642 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
643 q->write_ptr, idx, priv->cmd_queue);
644
795414db
EG		 645 phys_addr = dma_map_single(priv->bus.dev, &out_cmd->hdr, copy_size,
646 DMA_BIDIRECTIONAL);
647 if (unlikely(dma_mapping_error(priv->bus.dev, phys_addr))) {
2c46f72e
JB		 648 idx = -ENOMEM;
649 goto out;
650 }
651
2e724443 652 dma_unmap_addr_set(out_meta, mapping, phys_addr);
4ce7cc2b
JB		 653 dma_unmap_len_set(out_meta, len, copy_size);
654
655 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1);
656#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
657 trace_bufs[0] = &out_cmd->hdr;
658 trace_lens[0] = copy_size;
659 trace_idx = 1;
660#endif
661
662 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
663 if (!cmd->len[i])
664 continue;
665 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
666 continue;
795414db 667 phys_addr = dma_map_single(priv->bus.dev, (void *)cmd->data[i],
3be3fdb5 668 cmd->len[i], DMA_BIDIRECTIONAL);
795414db 669 if (dma_mapping_error(priv->bus.dev, phys_addr)) {
4ce7cc2b 670 iwlagn_unmap_tfd(priv, out_meta,
e815407d 671 &txq->tfds[q->write_ptr],
3be3fdb5 672 DMA_BIDIRECTIONAL);
4ce7cc2b
JB		 673 idx = -ENOMEM;
674 goto out;
675 }
676
677 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
678 cmd->len[i], 0);
679#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
680 trace_bufs[trace_idx] = cmd->data[i];
681 trace_lens[trace_idx] = cmd->len[i];
682 trace_idx++;
683#endif
684 }
df833b1d 685
afaf6b57 686 out_meta->flags = cmd->flags;
2c46f72e
JB		 687
688 txq->need_update = 1;
689
4ce7cc2b
JB		 690 /* check that tracing gets all possible blocks */
691 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
692#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
693 trace_iwlwifi_dev_hcmd(priv, cmd->flags,
694 trace_bufs[0], trace_lens[0],
695 trace_bufs[1], trace_lens[1],
696 trace_bufs[2], trace_lens[2]);
697#endif
df833b1d 698
fd4abac5
TW		 699 /* Increment and update queue's write index */
700 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 701 iwl_txq_update_write_ptr(priv, txq);
fd4abac5 702
2c46f72e 703 out:
fd4abac5 704 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
7bfedc59 705 return idx;
fd4abac5
TW		 706}
707
17b88929
TW		 708/**
709 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
710 *
711 * When FW advances 'R' index, all entries between old and new 'R' index
712 * need to be reclaimed. As result, some free space forms. If there is
713 * enough free space (> low mark), wake the stack that feeds us.
714 */
20ba2861 715static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
17b88929
TW		 716{
717 struct iwl_tx_queue *txq = &priv->txq[txq_id];
718 struct iwl_queue *q = &txq->q;
719 int nfreed = 0;
720
499b1883 721 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
2e5d04da
DH		 722 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
723 "index %d is out of range [0-%d] %d %d.\n", __func__,
724 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
17b88929
TW		 725 return;
726 }
727
499b1883
TW		 728 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
729 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
17b88929 730
499b1883 731 if (nfreed++ > 0) {
15b1687c 732 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
17b88929 733 q->write_ptr, q->read_ptr);
e649437f 734 iwlagn_fw_error(priv, false);
17b88929 735 }
da99c4b6 736
17b88929
TW		 737 }
738}
739
740/**
741 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
742 * @rxb: Rx buffer to reclaim
743 *
744 * If an Rx buffer has an async callback associated with it the callback
745 * will be executed. The attached skb (if present) will only be freed
746 * if the callback returns 1
747 */
748void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
749{
2f301227 750 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17b88929
TW		 751 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
752 int txq_id = SEQ_TO_QUEUE(sequence);
753 int index = SEQ_TO_INDEX(sequence);
17b88929 754 int cmd_index;
c2acea8e
JB		 755 struct iwl_device_cmd *cmd;
756 struct iwl_cmd_meta *meta;
13bb9483 757 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
3598e177 758 unsigned long flags;
17b88929
TW		 759
760 /* If a Tx command is being handled and it isn't in the actual
761 * command queue then there a command routing bug has been introduced
762 * in the queue management code. */
13bb9483
JB		 763 if (WARN(txq_id != priv->cmd_queue,
764 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
765 txq_id, priv->cmd_queue, sequence,
766 priv->txq[priv->cmd_queue].q.read_ptr,
767 priv->txq[priv->cmd_queue].q.write_ptr)) {
ec741164 768 iwl_print_hex_error(priv, pkt, 32);
55d6a3cd 769 return;
01ef9323 770 }
17b88929 771
4ce7cc2b 772 cmd_index = get_cmd_index(&txq->q, index);
dd487449
ZY		 773 cmd = txq->cmd[cmd_index];
774 meta = &txq->meta[cmd_index];
17b88929 775
3be3fdb5 776 iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
c33de625 777
17b88929 778 /* Input error checking is done when commands are added to queue. */
c2acea8e 779 if (meta->flags & CMD_WANT_SKB) {
2f301227
ZY		 780 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
781 rxb->page = NULL;
2624e96c
SG		 782 } else if (meta->callback)
783 meta->callback(priv, cmd, pkt);
784
785 spin_lock_irqsave(&priv->hcmd_lock, flags);
17b88929 786
20ba2861 787 iwl_hcmd_queue_reclaim(priv, txq_id, index);
17b88929 788
c2acea8e 789 if (!(meta->flags & CMD_ASYNC)) {
17b88929 790 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
91dd6c27 791 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
d2dfe6df 792 get_cmd_string(cmd->hdr.cmd));
17b88929
TW		 793 wake_up_interruptible(&priv->wait_command_queue);
794 }
3598e177 795
dd487449 796 meta->flags = 0;
3598e177
SG		 797
798 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
17b88929 799}
253a634c
EG		 800
801const char *get_cmd_string(u8 cmd)
802{
803 switch (cmd) {
804 IWL_CMD(REPLY_ALIVE);
805 IWL_CMD(REPLY_ERROR);
806 IWL_CMD(REPLY_RXON);
807 IWL_CMD(REPLY_RXON_ASSOC);
808 IWL_CMD(REPLY_QOS_PARAM);
809 IWL_CMD(REPLY_RXON_TIMING);
810 IWL_CMD(REPLY_ADD_STA);
811 IWL_CMD(REPLY_REMOVE_STA);
812 IWL_CMD(REPLY_REMOVE_ALL_STA);
813 IWL_CMD(REPLY_TXFIFO_FLUSH);
814 IWL_CMD(REPLY_WEPKEY);
815 IWL_CMD(REPLY_TX);
816 IWL_CMD(REPLY_LEDS_CMD);
817 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
818 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
819 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
820 IWL_CMD(COEX_EVENT_CMD);
821 IWL_CMD(REPLY_QUIET_CMD);
822 IWL_CMD(REPLY_CHANNEL_SWITCH);
823 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
824 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
825 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
826 IWL_CMD(POWER_TABLE_CMD);
827 IWL_CMD(PM_SLEEP_NOTIFICATION);
828 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
829 IWL_CMD(REPLY_SCAN_CMD);
830 IWL_CMD(REPLY_SCAN_ABORT_CMD);
831 IWL_CMD(SCAN_START_NOTIFICATION);
832 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
833 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
834 IWL_CMD(BEACON_NOTIFICATION);
835 IWL_CMD(REPLY_TX_BEACON);
836 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
837 IWL_CMD(QUIET_NOTIFICATION);
838 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
839 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
840 IWL_CMD(REPLY_BT_CONFIG);
841 IWL_CMD(REPLY_STATISTICS_CMD);
842 IWL_CMD(STATISTICS_NOTIFICATION);
843 IWL_CMD(REPLY_CARD_STATE_CMD);
844 IWL_CMD(CARD_STATE_NOTIFICATION);
845 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
846 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
847 IWL_CMD(SENSITIVITY_CMD);
848 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
849 IWL_CMD(REPLY_RX_PHY_CMD);
850 IWL_CMD(REPLY_RX_MPDU_CMD);
851 IWL_CMD(REPLY_RX);
852 IWL_CMD(REPLY_COMPRESSED_BA);
853 IWL_CMD(CALIBRATION_CFG_CMD);
854 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
855 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
856 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
857 IWL_CMD(TEMPERATURE_NOTIFICATION);
858 IWL_CMD(TX_ANT_CONFIGURATION_CMD);
859 IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF);
860 IWL_CMD(REPLY_BT_COEX_PRIO_TABLE);
861 IWL_CMD(REPLY_BT_COEX_PROT_ENV);
862 IWL_CMD(REPLY_WIPAN_PARAMS);
863 IWL_CMD(REPLY_WIPAN_RXON);
864 IWL_CMD(REPLY_WIPAN_RXON_TIMING);
865 IWL_CMD(REPLY_WIPAN_RXON_ASSOC);
866 IWL_CMD(REPLY_WIPAN_QOS_PARAM);
867 IWL_CMD(REPLY_WIPAN_WEPKEY);
868 IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH);
869 IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION);
870 IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE);
871 default:
872 return "UNKNOWN";
873
874 }
875}
876
877#define HOST_COMPLETE_TIMEOUT (2 * HZ)
878
879static void iwl_generic_cmd_callback(struct iwl_priv *priv,
880 struct iwl_device_cmd *cmd,
881 struct iwl_rx_packet *pkt)
882{
883 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
884 IWL_ERR(priv, "Bad return from %s (0x%08X)\n",
885 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
886 return;
887 }
888
889#ifdef CONFIG_IWLWIFI_DEBUG
890 switch (cmd->hdr.cmd) {
891 case REPLY_TX_LINK_QUALITY_CMD:
892 case SENSITIVITY_CMD:
893 IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n",
894 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
895 break;
896 default:
897 IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n",
898 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
899 }
900#endif
901}
902
903static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
904{
905 int ret;
906
907 /* An asynchronous command can not expect an SKB to be set. */
908 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
909 return -EINVAL;
910
911 /* Assign a generic callback if one is not provided */
912 if (!cmd->callback)
913 cmd->callback = iwl_generic_cmd_callback;
914
915 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
916 return -EBUSY;
917
918 ret = iwl_enqueue_hcmd(priv, cmd);
919 if (ret < 0) {
920 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
921 get_cmd_string(cmd->id), ret);
922 return ret;
923 }
924 return 0;
925}
926
927static int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
928{
929 int cmd_idx;
930 int ret;
931
932 lockdep_assert_held(&priv->mutex);
933
934 /* A synchronous command can not have a callback set. */
935 if (WARN_ON(cmd->callback))
936 return -EINVAL;
937
938 IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
939 get_cmd_string(cmd->id));
940
941 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
942 IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
943 get_cmd_string(cmd->id));
944
945 cmd_idx = iwl_enqueue_hcmd(priv, cmd);
946 if (cmd_idx < 0) {
947 ret = cmd_idx;
948 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
949 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
950 get_cmd_string(cmd->id), ret);
951 return ret;
952 }
953
954 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
955 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
956 HOST_COMPLETE_TIMEOUT);
957 if (!ret) {
958 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
959 IWL_ERR(priv,
960 "Error sending %s: time out after %dms.\n",
961 get_cmd_string(cmd->id),
962 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
963
964 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
965 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command"
966 "%s\n", get_cmd_string(cmd->id));
967 ret = -ETIMEDOUT;
968 goto cancel;
969 }
970 }
971
972 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
973 IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n",
974 get_cmd_string(cmd->id));
975 ret = -ECANCELED;
976 goto fail;
977 }
978 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
979 IWL_ERR(priv, "Command %s failed: FW Error\n",
980 get_cmd_string(cmd->id));
981 ret = -EIO;
982 goto fail;
983 }
984 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
985 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
986 get_cmd_string(cmd->id));
987 ret = -EIO;
988 goto cancel;
989 }
990
991 return 0;
992
993cancel:
994 if (cmd->flags & CMD_WANT_SKB) {
995 /*
996 * Cancel the CMD_WANT_SKB flag for the cmd in the
997 * TX cmd queue. Otherwise in case the cmd comes
998 * in later, it will possibly set an invalid
999 * address (cmd->meta.source).
1000 */
1001 priv->txq[priv->cmd_queue].meta[cmd_idx].flags &=
1002 ~CMD_WANT_SKB;
1003 }
1004fail:
1005 if (cmd->reply_page) {
1006 iwl_free_pages(priv, cmd->reply_page);
1007 cmd->reply_page = 0;
1008 }
1009
1010 return ret;
1011}
1012
1013int iwl_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1014{
1015 if (cmd->flags & CMD_ASYNC)
1016 return iwl_send_cmd_async(priv, cmd);
1017
1018 return iwl_send_cmd_sync(priv, cmd);
1019}
1020
1021int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags, u16 len,
1022 const void *data)
1023{
1024 struct iwl_host_cmd cmd = {
1025 .id = id,
1026 .len = { len, },
1027 .data = { data, },
1028 .flags = flags,
1029 };
1030
1031 return iwl_send_cmd(priv, &cmd);
1032}
Linux 6.x block layer and io_uring tree(s)