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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
c85eb619 | 71 | #include "iwl-trans.h" |
c17d0681 | 72 | #include "iwl-trans-pcie-int.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
48f20d35 | 75 | #include "iwl-shared.h" |
522376d2 | 76 | #include "iwl-eeprom.h" |
7a10e3e4 | 77 | #include "iwl-agn-hw.h" |
c85eb619 | 78 | |
0439bb62 JB |
79 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
80 | ||
5a878bf6 | 81 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 82 | { |
5a878bf6 EG |
83 | struct iwl_trans_pcie *trans_pcie = |
84 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
85 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
1042db2a | 86 | struct device *dev = trans->dev; |
c85eb619 | 87 | |
5a878bf6 | 88 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
89 | |
90 | spin_lock_init(&rxq->lock); | |
c85eb619 EG |
91 | |
92 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
93 | return -EINVAL; | |
94 | ||
95 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
84c816da DH |
96 | rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
97 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
98 | if (!rxq->bd) |
99 | goto err_bd; | |
c85eb619 EG |
100 | |
101 | /*Allocate the driver's pointer to receive buffer status */ | |
84c816da DH |
102 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), |
103 | &rxq->rb_stts_dma, GFP_KERNEL); | |
c85eb619 EG |
104 | if (!rxq->rb_stts) |
105 | goto err_rb_stts; | |
c85eb619 EG |
106 | |
107 | return 0; | |
108 | ||
109 | err_rb_stts: | |
a0f6b0a2 EG |
110 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
111 | rxq->bd, rxq->bd_dma); | |
c85eb619 EG |
112 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
113 | rxq->bd = NULL; | |
114 | err_bd: | |
115 | return -ENOMEM; | |
116 | } | |
117 | ||
5a878bf6 | 118 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 119 | { |
5a878bf6 EG |
120 | struct iwl_trans_pcie *trans_pcie = |
121 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
122 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
a0f6b0a2 | 123 | int i; |
c85eb619 EG |
124 | |
125 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
126 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
127 | /* In the reset function, these buffers may have been allocated | |
128 | * to an SKB, so we need to unmap and free potential storage */ | |
129 | if (rxq->pool[i].page != NULL) { | |
1042db2a | 130 | dma_unmap_page(trans->dev, rxq->pool[i].page_dma, |
5a878bf6 | 131 | PAGE_SIZE << hw_params(trans).rx_page_order, |
c85eb619 | 132 | DMA_FROM_DEVICE); |
790428b6 EG |
133 | __free_pages(rxq->pool[i].page, |
134 | hw_params(trans).rx_page_order); | |
c85eb619 EG |
135 | rxq->pool[i].page = NULL; |
136 | } | |
137 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
138 | } | |
a0f6b0a2 EG |
139 | } |
140 | ||
fd656935 | 141 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
ab697a9f EG |
142 | struct iwl_rx_queue *rxq) |
143 | { | |
144 | u32 rb_size; | |
145 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
c17d0681 | 146 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
ab697a9f EG |
147 | |
148 | if (iwlagn_mod_params.amsdu_size_8K) | |
149 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
150 | else | |
151 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
152 | ||
153 | /* Stop Rx DMA */ | |
1042db2a | 154 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
ab697a9f EG |
155 | |
156 | /* Reset driver's Rx queue write index */ | |
1042db2a | 157 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
ab697a9f EG |
158 | |
159 | /* Tell device where to find RBD circular buffer in DRAM */ | |
1042db2a | 160 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
ab697a9f EG |
161 | (u32)(rxq->bd_dma >> 8)); |
162 | ||
163 | /* Tell device where in DRAM to update its Rx status */ | |
1042db2a | 164 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, |
ab697a9f EG |
165 | rxq->rb_stts_dma >> 4); |
166 | ||
167 | /* Enable Rx DMA | |
168 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
169 | * the credit mechanism in 5000 HW RX FIFO | |
170 | * Direct rx interrupts to hosts | |
171 | * Rx buffer size 4 or 8k | |
172 | * RB timeout 0x10 | |
173 | * 256 RBDs | |
174 | */ | |
1042db2a | 175 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
ab697a9f EG |
176 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
177 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
178 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
179 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | | |
180 | rb_size| | |
181 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
182 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
183 | ||
184 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
1042db2a | 185 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
ab697a9f EG |
186 | } |
187 | ||
5a878bf6 | 188 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 189 | { |
5a878bf6 EG |
190 | struct iwl_trans_pcie *trans_pcie = |
191 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
192 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
193 | ||
a0f6b0a2 EG |
194 | int i, err; |
195 | unsigned long flags; | |
196 | ||
197 | if (!rxq->bd) { | |
5a878bf6 | 198 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
199 | if (err) |
200 | return err; | |
201 | } | |
202 | ||
203 | spin_lock_irqsave(&rxq->lock, flags); | |
204 | INIT_LIST_HEAD(&rxq->rx_free); | |
205 | INIT_LIST_HEAD(&rxq->rx_used); | |
206 | ||
5a878bf6 | 207 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
208 | |
209 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
210 | rxq->queue[i] = NULL; | |
211 | ||
212 | /* Set us so that we have processed and used all buffers, but have | |
213 | * not restocked the Rx queue with fresh buffers */ | |
214 | rxq->read = rxq->write = 0; | |
215 | rxq->write_actual = 0; | |
216 | rxq->free_count = 0; | |
217 | spin_unlock_irqrestore(&rxq->lock, flags); | |
218 | ||
5a878bf6 | 219 | iwlagn_rx_replenish(trans); |
ab697a9f | 220 | |
fd656935 | 221 | iwl_trans_rx_hw_init(trans, rxq); |
ab697a9f | 222 | |
7b11488f | 223 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f | 224 | rxq->need_update = 1; |
5a878bf6 | 225 | iwl_rx_queue_update_write_ptr(trans, rxq); |
7b11488f | 226 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f | 227 | |
c85eb619 EG |
228 | return 0; |
229 | } | |
230 | ||
5a878bf6 | 231 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 232 | { |
5a878bf6 EG |
233 | struct iwl_trans_pcie *trans_pcie = |
234 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
235 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
236 | ||
a0f6b0a2 EG |
237 | unsigned long flags; |
238 | ||
239 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
240 | * exit now */ | |
241 | if (!rxq->bd) { | |
5a878bf6 | 242 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
243 | return; |
244 | } | |
245 | ||
246 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 247 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
248 | spin_unlock_irqrestore(&rxq->lock, flags); |
249 | ||
1042db2a | 250 | dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
251 | rxq->bd, rxq->bd_dma); |
252 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
253 | rxq->bd = NULL; | |
254 | ||
255 | if (rxq->rb_stts) | |
1042db2a | 256 | dma_free_coherent(trans->dev, |
a0f6b0a2 EG |
257 | sizeof(struct iwl_rb_status), |
258 | rxq->rb_stts, rxq->rb_stts_dma); | |
259 | else | |
5a878bf6 | 260 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
261 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
262 | rxq->rb_stts = NULL; | |
263 | } | |
264 | ||
6d8f6eeb | 265 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
c2c52e8b EG |
266 | { |
267 | ||
268 | /* stop Rx DMA */ | |
1042db2a EG |
269 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
270 | return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, | |
c2c52e8b EG |
271 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
272 | } | |
273 | ||
6d8f6eeb | 274 | static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
02aca585 EG |
275 | struct iwl_dma_ptr *ptr, size_t size) |
276 | { | |
277 | if (WARN_ON(ptr->addr)) | |
278 | return -EINVAL; | |
279 | ||
1042db2a | 280 | ptr->addr = dma_alloc_coherent(trans->dev, size, |
02aca585 EG |
281 | &ptr->dma, GFP_KERNEL); |
282 | if (!ptr->addr) | |
283 | return -ENOMEM; | |
284 | ptr->size = size; | |
285 | return 0; | |
286 | } | |
287 | ||
6d8f6eeb | 288 | static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
1359ca4f EG |
289 | struct iwl_dma_ptr *ptr) |
290 | { | |
291 | if (unlikely(!ptr->addr)) | |
292 | return; | |
293 | ||
1042db2a | 294 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
295 | memset(ptr, 0, sizeof(*ptr)); |
296 | } | |
297 | ||
6d8f6eeb EG |
298 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
299 | struct iwl_tx_queue *txq, int slots_num, | |
300 | u32 txq_id) | |
02aca585 | 301 | { |
ab9e212e | 302 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
02aca585 EG |
303 | int i; |
304 | ||
2c452297 | 305 | if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds)) |
02aca585 EG |
306 | return -EINVAL; |
307 | ||
1359ca4f EG |
308 | txq->q.n_window = slots_num; |
309 | ||
7f90dce1 EG |
310 | txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL); |
311 | txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL); | |
02aca585 EG |
312 | |
313 | if (!txq->meta || !txq->cmd) | |
314 | goto error; | |
315 | ||
dfa2bdba EG |
316 | if (txq_id == trans->shrd->cmd_queue) |
317 | for (i = 0; i < slots_num; i++) { | |
318 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), | |
319 | GFP_KERNEL); | |
320 | if (!txq->cmd[i]) | |
321 | goto error; | |
322 | } | |
02aca585 EG |
323 | |
324 | /* Alloc driver data array and TFD circular buffer */ | |
325 | /* Driver private data, only for Tx (not command) queues, | |
326 | * not shared with device. */ | |
6d8f6eeb | 327 | if (txq_id != trans->shrd->cmd_queue) { |
7f90dce1 EG |
328 | txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]), |
329 | GFP_KERNEL); | |
2c452297 | 330 | if (!txq->skbs) { |
6d8f6eeb | 331 | IWL_ERR(trans, "kmalloc for auxiliary BD " |
02aca585 EG |
332 | "structures failed\n"); |
333 | goto error; | |
334 | } | |
335 | } else { | |
2c452297 | 336 | txq->skbs = NULL; |
02aca585 EG |
337 | } |
338 | ||
339 | /* Circular buffer of transmit frame descriptors (TFDs), | |
340 | * shared with device */ | |
1042db2a | 341 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, |
6d8f6eeb | 342 | &txq->q.dma_addr, GFP_KERNEL); |
02aca585 | 343 | if (!txq->tfds) { |
6d8f6eeb | 344 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
02aca585 EG |
345 | goto error; |
346 | } | |
347 | txq->q.id = txq_id; | |
348 | ||
349 | return 0; | |
350 | error: | |
2c452297 EG |
351 | kfree(txq->skbs); |
352 | txq->skbs = NULL; | |
02aca585 EG |
353 | /* since txq->cmd has been zeroed, |
354 | * all non allocated cmd[i] will be NULL */ | |
dfa2bdba | 355 | if (txq->cmd && txq_id == trans->shrd->cmd_queue) |
02aca585 EG |
356 | for (i = 0; i < slots_num; i++) |
357 | kfree(txq->cmd[i]); | |
358 | kfree(txq->meta); | |
359 | kfree(txq->cmd); | |
360 | txq->meta = NULL; | |
361 | txq->cmd = NULL; | |
362 | ||
363 | return -ENOMEM; | |
364 | ||
365 | } | |
366 | ||
6d8f6eeb | 367 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
02aca585 EG |
368 | int slots_num, u32 txq_id) |
369 | { | |
370 | int ret; | |
371 | ||
372 | txq->need_update = 0; | |
373 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); | |
374 | ||
375 | /* | |
376 | * For the default queues 0-3, set up the swq_id | |
377 | * already -- all others need to get one later | |
378 | * (if they need one at all). | |
379 | */ | |
380 | if (txq_id < 4) | |
381 | iwl_set_swq_id(txq, txq_id, txq_id); | |
382 | ||
383 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
384 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
385 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
386 | ||
387 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
6d8f6eeb | 388 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
02aca585 EG |
389 | txq_id); |
390 | if (ret) | |
391 | return ret; | |
392 | ||
015c15e1 JB |
393 | spin_lock_init(&txq->lock); |
394 | ||
02aca585 EG |
395 | /* |
396 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
397 | * given Tx queue, and enable the DMA channel used for that queue. | |
398 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
1042db2a | 399 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), |
02aca585 EG |
400 | txq->q.dma_addr >> 8); |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
c170b867 EG |
405 | /** |
406 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
407 | */ | |
6d8f6eeb | 408 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
c170b867 | 409 | { |
8ad71bef EG |
410 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
411 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
c170b867 | 412 | struct iwl_queue *q = &txq->q; |
39644e9a | 413 | enum dma_data_direction dma_dir; |
c170b867 EG |
414 | |
415 | if (!q->n_bd) | |
416 | return; | |
417 | ||
39644e9a EG |
418 | /* In the command queue, all the TBs are mapped as BIDI |
419 | * so unmap them as such. | |
420 | */ | |
015c15e1 | 421 | if (txq_id == trans->shrd->cmd_queue) |
39644e9a | 422 | dma_dir = DMA_BIDIRECTIONAL; |
015c15e1 | 423 | else |
39644e9a EG |
424 | dma_dir = DMA_TO_DEVICE; |
425 | ||
015c15e1 | 426 | spin_lock_bh(&txq->lock); |
c170b867 EG |
427 | while (q->write_ptr != q->read_ptr) { |
428 | /* The read_ptr needs to bound by q->n_window */ | |
39644e9a EG |
429 | iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr), |
430 | dma_dir); | |
c170b867 EG |
431 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
432 | } | |
015c15e1 | 433 | spin_unlock_bh(&txq->lock); |
c170b867 EG |
434 | } |
435 | ||
1359ca4f EG |
436 | /** |
437 | * iwl_tx_queue_free - Deallocate DMA queue. | |
438 | * @txq: Transmit queue to deallocate. | |
439 | * | |
440 | * Empty queue by removing and destroying all BD's. | |
441 | * Free all buffers. | |
442 | * 0-fill, but do not free "txq" descriptor structure. | |
443 | */ | |
6d8f6eeb | 444 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
1359ca4f | 445 | { |
8ad71bef EG |
446 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
447 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
1042db2a | 448 | struct device *dev = trans->dev; |
1359ca4f EG |
449 | int i; |
450 | if (WARN_ON(!txq)) | |
451 | return; | |
452 | ||
6d8f6eeb | 453 | iwl_tx_queue_unmap(trans, txq_id); |
1359ca4f EG |
454 | |
455 | /* De-alloc array of command/tx buffers */ | |
dfa2bdba EG |
456 | |
457 | if (txq_id == trans->shrd->cmd_queue) | |
458 | for (i = 0; i < txq->q.n_window; i++) | |
459 | kfree(txq->cmd[i]); | |
1359ca4f EG |
460 | |
461 | /* De-alloc circular buffer of TFDs */ | |
462 | if (txq->q.n_bd) { | |
ab9e212e | 463 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
1359ca4f EG |
464 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
465 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
466 | } | |
467 | ||
468 | /* De-alloc array of per-TFD driver data */ | |
2c452297 EG |
469 | kfree(txq->skbs); |
470 | txq->skbs = NULL; | |
1359ca4f EG |
471 | |
472 | /* deallocate arrays */ | |
473 | kfree(txq->cmd); | |
474 | kfree(txq->meta); | |
475 | txq->cmd = NULL; | |
476 | txq->meta = NULL; | |
477 | ||
478 | /* 0-fill queue descriptor structure */ | |
479 | memset(txq, 0, sizeof(*txq)); | |
480 | } | |
481 | ||
482 | /** | |
483 | * iwl_trans_tx_free - Free TXQ Context | |
484 | * | |
485 | * Destroy all TX DMA queues and structures | |
486 | */ | |
6d8f6eeb | 487 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
1359ca4f EG |
488 | { |
489 | int txq_id; | |
8ad71bef | 490 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1359ca4f EG |
491 | |
492 | /* Tx queues */ | |
8ad71bef | 493 | if (trans_pcie->txq) { |
d6189124 | 494 | for (txq_id = 0; |
6d8f6eeb EG |
495 | txq_id < hw_params(trans).max_txq_num; txq_id++) |
496 | iwl_tx_queue_free(trans, txq_id); | |
1359ca4f EG |
497 | } |
498 | ||
8ad71bef EG |
499 | kfree(trans_pcie->txq); |
500 | trans_pcie->txq = NULL; | |
1359ca4f | 501 | |
9d6b2cb1 | 502 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
1359ca4f | 503 | |
6d8f6eeb | 504 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
505 | } |
506 | ||
02aca585 EG |
507 | /** |
508 | * iwl_trans_tx_alloc - allocate TX context | |
509 | * Allocate all Tx DMA structures and initialize them | |
510 | * | |
511 | * @param priv | |
512 | * @return error code | |
513 | */ | |
6d8f6eeb | 514 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
02aca585 EG |
515 | { |
516 | int ret; | |
517 | int txq_id, slots_num; | |
8ad71bef | 518 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 519 | |
fd656935 | 520 | u16 scd_bc_tbls_size = hw_params(trans).max_txq_num * |
ab9e212e EG |
521 | sizeof(struct iwlagn_scd_bc_tbl); |
522 | ||
02aca585 EG |
523 | /*It is not allowed to alloc twice, so warn when this happens. |
524 | * We cannot rely on the previous allocation, so free and fail */ | |
8ad71bef | 525 | if (WARN_ON(trans_pcie->txq)) { |
02aca585 EG |
526 | ret = -EINVAL; |
527 | goto error; | |
528 | } | |
529 | ||
6d8f6eeb | 530 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
ab9e212e | 531 | scd_bc_tbls_size); |
02aca585 | 532 | if (ret) { |
6d8f6eeb | 533 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
02aca585 EG |
534 | goto error; |
535 | } | |
536 | ||
537 | /* Alloc keep-warm buffer */ | |
9d6b2cb1 | 538 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
02aca585 | 539 | if (ret) { |
6d8f6eeb | 540 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
02aca585 EG |
541 | goto error; |
542 | } | |
543 | ||
7f90dce1 EG |
544 | trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num, |
545 | sizeof(struct iwl_tx_queue), GFP_KERNEL); | |
8ad71bef | 546 | if (!trans_pcie->txq) { |
6d8f6eeb | 547 | IWL_ERR(trans, "Not enough memory for txq\n"); |
02aca585 EG |
548 | ret = ENOMEM; |
549 | goto error; | |
550 | } | |
551 | ||
552 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
6d8f6eeb EG |
553 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
554 | slots_num = (txq_id == trans->shrd->cmd_queue) ? | |
02aca585 | 555 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
556 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
557 | slots_num, txq_id); | |
02aca585 | 558 | if (ret) { |
6d8f6eeb | 559 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
02aca585 EG |
560 | goto error; |
561 | } | |
562 | } | |
563 | ||
564 | return 0; | |
565 | ||
566 | error: | |
ae2c30bf | 567 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
568 | |
569 | return ret; | |
570 | } | |
6d8f6eeb | 571 | static int iwl_tx_init(struct iwl_trans *trans) |
02aca585 EG |
572 | { |
573 | int ret; | |
574 | int txq_id, slots_num; | |
575 | unsigned long flags; | |
576 | bool alloc = false; | |
8ad71bef | 577 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 578 | |
8ad71bef | 579 | if (!trans_pcie->txq) { |
6d8f6eeb | 580 | ret = iwl_trans_tx_alloc(trans); |
02aca585 EG |
581 | if (ret) |
582 | goto error; | |
583 | alloc = true; | |
584 | } | |
585 | ||
7b11488f | 586 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
02aca585 EG |
587 | |
588 | /* Turn off all Tx DMA fifos */ | |
1042db2a | 589 | iwl_write_prph(trans, SCD_TXFACT, 0); |
02aca585 EG |
590 | |
591 | /* Tell NIC where to find the "keep warm" buffer */ | |
1042db2a | 592 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, |
83ed9015 | 593 | trans_pcie->kw.dma >> 4); |
02aca585 | 594 | |
7b11488f | 595 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
02aca585 EG |
596 | |
597 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
6d8f6eeb EG |
598 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
599 | slots_num = (txq_id == trans->shrd->cmd_queue) ? | |
02aca585 | 600 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
601 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
602 | slots_num, txq_id); | |
02aca585 | 603 | if (ret) { |
6d8f6eeb | 604 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
02aca585 EG |
605 | goto error; |
606 | } | |
607 | } | |
608 | ||
609 | return 0; | |
610 | error: | |
611 | /*Upon error, free only if we allocated something */ | |
612 | if (alloc) | |
ae2c30bf | 613 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
614 | return ret; |
615 | } | |
616 | ||
3e10caeb | 617 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
618 | { |
619 | /* | |
620 | * (for documentation purposes) | |
621 | * to set power to V_AUX, do: | |
622 | ||
623 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
1042db2a | 624 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
625 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
626 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
627 | */ | |
628 | ||
1042db2a | 629 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
630 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
631 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
632 | } | |
633 | ||
af634bee EG |
634 | /* PCI registers */ |
635 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
636 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
637 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
638 | ||
639 | static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans) | |
640 | { | |
641 | int pos; | |
642 | u16 pci_lnk_ctl; | |
643 | struct iwl_trans_pcie *trans_pcie = | |
644 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
645 | ||
646 | struct pci_dev *pci_dev = trans_pcie->pci_dev; | |
647 | ||
648 | pos = pci_pcie_cap(pci_dev); | |
649 | pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl); | |
650 | return pci_lnk_ctl; | |
651 | } | |
652 | ||
653 | static void iwl_apm_config(struct iwl_trans *trans) | |
654 | { | |
655 | /* | |
656 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
657 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
658 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
659 | * costs negligible amount of power savings. | |
660 | * If not (unlikely), enable L0S, so there is at least some | |
661 | * power savings, even without L1. | |
662 | */ | |
663 | u16 lctl = iwl_pciexp_link_ctrl(trans); | |
664 | ||
665 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == | |
666 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { | |
667 | /* L1-ASPM enabled; disable(!) L0S */ | |
668 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
669 | dev_printk(KERN_INFO, trans->dev, | |
670 | "L1 Enabled; Disabling L0S\n"); | |
671 | } else { | |
672 | /* L1-ASPM disabled; enable(!) L0S */ | |
673 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
674 | dev_printk(KERN_INFO, trans->dev, | |
675 | "L1 Disabled; Enabling L0S\n"); | |
676 | } | |
f6d0e9be | 677 | trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); |
af634bee EG |
678 | } |
679 | ||
a6c684ee EG |
680 | /* |
681 | * Start up NIC's basic functionality after it has been reset | |
682 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
683 | * NOTE: This does not load uCode nor start the embedded processor | |
684 | */ | |
685 | static int iwl_apm_init(struct iwl_trans *trans) | |
686 | { | |
687 | int ret = 0; | |
688 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
689 | ||
690 | /* | |
691 | * Use "set_bit" below rather than "write", to preserve any hardware | |
692 | * bits already set by default after reset. | |
693 | */ | |
694 | ||
695 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
696 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
697 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
698 | ||
699 | /* | |
700 | * Disable L0s without affecting L1; | |
701 | * don't wait for ICH L0s (ICH bug W/A) | |
702 | */ | |
703 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
704 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
705 | ||
706 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
707 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
708 | ||
709 | /* | |
710 | * Enable HAP INTA (interrupt from management bus) to | |
711 | * wake device's PCI Express link L1a -> L0s | |
712 | */ | |
713 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
714 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
715 | ||
af634bee | 716 | iwl_apm_config(trans); |
a6c684ee EG |
717 | |
718 | /* Configure analog phase-lock-loop before activating to D0A */ | |
719 | if (cfg(trans)->base_params->pll_cfg_val) | |
720 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, | |
721 | cfg(trans)->base_params->pll_cfg_val); | |
722 | ||
723 | /* | |
724 | * Set "initialization complete" bit to move adapter from | |
725 | * D0U* --> D0A* (powered-up active) state. | |
726 | */ | |
727 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
728 | ||
729 | /* | |
730 | * Wait for clock stabilization; once stabilized, access to | |
731 | * device-internal resources is supported, e.g. iwl_write_prph() | |
732 | * and accesses to uCode SRAM. | |
733 | */ | |
734 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
735 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
736 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
737 | if (ret < 0) { | |
738 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
739 | goto out; | |
740 | } | |
741 | ||
742 | /* | |
743 | * Enable DMA clock and wait for it to stabilize. | |
744 | * | |
745 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
746 | * do not disable clocks. This preserves any hardware bits already | |
747 | * set by default in "CLK_CTRL_REG" after reset. | |
748 | */ | |
749 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
750 | udelay(20); | |
751 | ||
752 | /* Disable L1-Active */ | |
753 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
754 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
755 | ||
756 | set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status); | |
757 | ||
758 | out: | |
759 | return ret; | |
760 | } | |
761 | ||
cc56feb2 EG |
762 | static int iwl_apm_stop_master(struct iwl_trans *trans) |
763 | { | |
764 | int ret = 0; | |
765 | ||
766 | /* stop device's busmaster DMA activity */ | |
767 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
768 | ||
769 | ret = iwl_poll_bit(trans, CSR_RESET, | |
770 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
771 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
772 | if (ret) | |
773 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
774 | ||
775 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
776 | ||
777 | return ret; | |
778 | } | |
779 | ||
780 | static void iwl_apm_stop(struct iwl_trans *trans) | |
781 | { | |
782 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
783 | ||
784 | clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status); | |
785 | ||
786 | /* Stop device's DMA activity */ | |
787 | iwl_apm_stop_master(trans); | |
788 | ||
789 | /* Reset the entire device */ | |
790 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
791 | ||
792 | udelay(10); | |
793 | ||
794 | /* | |
795 | * Clear "initialization complete" bit to move adapter from | |
796 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
797 | */ | |
798 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
799 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
800 | } | |
801 | ||
6d8f6eeb | 802 | static int iwl_nic_init(struct iwl_trans *trans) |
392f8b78 | 803 | { |
7b11488f | 804 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
805 | unsigned long flags; |
806 | ||
807 | /* nic_init */ | |
7b11488f | 808 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
a6c684ee | 809 | iwl_apm_init(trans); |
392f8b78 EG |
810 | |
811 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
1042db2a | 812 | iwl_write8(trans, CSR_INT_COALESCING, |
83ed9015 | 813 | IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 814 | |
7b11488f | 815 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 816 | |
3e10caeb | 817 | iwl_set_pwr_vmain(trans); |
392f8b78 | 818 | |
7a10e3e4 | 819 | iwl_nic_config(priv(trans)); |
392f8b78 | 820 | |
a5916977 | 821 | #ifndef CONFIG_IWLWIFI_IDI |
392f8b78 | 822 | /* Allocate the RX queue, or reset if it is already allocated */ |
6d8f6eeb | 823 | iwl_rx_init(trans); |
a5916977 | 824 | #endif |
392f8b78 EG |
825 | |
826 | /* Allocate or reset and init all Tx and Command queues */ | |
6d8f6eeb | 827 | if (iwl_tx_init(trans)) |
392f8b78 EG |
828 | return -ENOMEM; |
829 | ||
0dde86b2 | 830 | if (cfg(trans)->base_params->shadow_reg_enable) { |
392f8b78 | 831 | /* enable shadow regs in HW */ |
1042db2a | 832 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, |
392f8b78 EG |
833 | 0x800FFFFF); |
834 | } | |
835 | ||
6d8f6eeb | 836 | set_bit(STATUS_INIT, &trans->shrd->status); |
392f8b78 EG |
837 | |
838 | return 0; | |
839 | } | |
840 | ||
841 | #define HW_READY_TIMEOUT (50) | |
842 | ||
843 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
6d8f6eeb | 844 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
845 | { |
846 | int ret; | |
847 | ||
1042db2a | 848 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
849 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
850 | ||
851 | /* See if we got it */ | |
1042db2a | 852 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
853 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
854 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
855 | HW_READY_TIMEOUT); | |
856 | ||
6d8f6eeb | 857 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
858 | return ret; |
859 | } | |
860 | ||
861 | /* Note: returns standard 0/-ERROR code */ | |
ebb7678d | 862 | static int iwl_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
863 | { |
864 | int ret; | |
865 | ||
6d8f6eeb | 866 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 867 | |
6d8f6eeb | 868 | ret = iwl_set_hw_ready(trans); |
ebb7678d | 869 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
870 | if (ret >= 0) |
871 | return 0; | |
872 | ||
873 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 874 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
875 | CSR_HW_IF_CONFIG_REG_PREPARE); |
876 | ||
1042db2a | 877 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
878 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
879 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
880 | ||
881 | if (ret < 0) | |
882 | return ret; | |
883 | ||
884 | /* HW should be ready by now, check again. */ | |
6d8f6eeb | 885 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
886 | if (ret >= 0) |
887 | return 0; | |
888 | return ret; | |
889 | } | |
890 | ||
e13c0c59 EG |
891 | #define IWL_AC_UNSET -1 |
892 | ||
893 | struct queue_to_fifo_ac { | |
894 | s8 fifo, ac; | |
895 | }; | |
896 | ||
897 | static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = { | |
898 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
899 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
900 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
901 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
902 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
903 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
904 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
905 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
906 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
907 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
908 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
909 | }; | |
910 | ||
911 | static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = { | |
912 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
913 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
914 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
915 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
916 | { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, }, | |
917 | { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, }, | |
918 | { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, }, | |
919 | { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, }, | |
920 | { IWL_TX_FIFO_BE_IPAN, 2, }, | |
921 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
922 | { IWL_TX_FIFO_AUX, IWL_AC_UNSET, }, | |
923 | }; | |
924 | ||
925 | static const u8 iwlagn_bss_ac_to_fifo[] = { | |
926 | IWL_TX_FIFO_VO, | |
927 | IWL_TX_FIFO_VI, | |
928 | IWL_TX_FIFO_BE, | |
929 | IWL_TX_FIFO_BK, | |
930 | }; | |
931 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
932 | 0, 1, 2, 3, | |
933 | }; | |
934 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
935 | IWL_TX_FIFO_VO_IPAN, | |
936 | IWL_TX_FIFO_VI_IPAN, | |
937 | IWL_TX_FIFO_BE_IPAN, | |
938 | IWL_TX_FIFO_BK_IPAN, | |
939 | }; | |
940 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
941 | 7, 6, 5, 4, | |
942 | }; | |
943 | ||
cf614297 EG |
944 | /* |
945 | * ucode | |
946 | */ | |
947 | static int iwl_load_section(struct iwl_trans *trans, const char *name, | |
0692fe41 | 948 | const struct fw_desc *image, u32 dst_addr) |
cf614297 EG |
949 | { |
950 | dma_addr_t phy_addr = image->p_addr; | |
951 | u32 byte_cnt = image->len; | |
952 | int ret; | |
953 | ||
954 | trans->ucode_write_complete = 0; | |
955 | ||
956 | iwl_write_direct32(trans, | |
957 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
958 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
959 | ||
960 | iwl_write_direct32(trans, | |
961 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
962 | ||
963 | iwl_write_direct32(trans, | |
964 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
965 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
966 | ||
967 | iwl_write_direct32(trans, | |
968 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), | |
969 | (iwl_get_dma_hi_addr(phy_addr) | |
970 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
971 | ||
972 | iwl_write_direct32(trans, | |
973 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
974 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
975 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
976 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
977 | ||
978 | iwl_write_direct32(trans, | |
979 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
980 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
981 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
982 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
983 | ||
984 | IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name); | |
985 | ret = wait_event_timeout(trans->shrd->wait_command_queue, | |
986 | trans->ucode_write_complete, 5 * HZ); | |
987 | if (!ret) { | |
988 | IWL_ERR(trans, "Could not load the %s uCode section\n", | |
989 | name); | |
990 | return -ETIMEDOUT; | |
991 | } | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
0692fe41 JB |
996 | static int iwl_load_given_ucode(struct iwl_trans *trans, |
997 | const struct fw_img *image) | |
cf614297 EG |
998 | { |
999 | int ret = 0; | |
1000 | ||
1001 | ret = iwl_load_section(trans, "INST", &image->code, | |
1002 | IWLAGN_RTC_INST_LOWER_BOUND); | |
1003 | if (ret) | |
1004 | return ret; | |
1005 | ||
1006 | ret = iwl_load_section(trans, "DATA", &image->data, | |
1007 | IWLAGN_RTC_DATA_LOWER_BOUND); | |
1008 | if (ret) | |
1009 | return ret; | |
1010 | ||
1011 | /* Remove all resets to allow NIC to operate */ | |
1012 | iwl_write32(trans, CSR_RESET, 0); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
0692fe41 JB |
1017 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
1018 | const struct fw_img *fw) | |
392f8b78 EG |
1019 | { |
1020 | int ret; | |
e13c0c59 EG |
1021 | struct iwl_trans_pcie *trans_pcie = |
1022 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
c9eec95c | 1023 | bool hw_rfkill; |
392f8b78 | 1024 | |
e13c0c59 EG |
1025 | trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue; |
1026 | trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue; | |
1027 | ||
1028 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo; | |
1029 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo; | |
1030 | ||
1031 | trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0; | |
1032 | trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE; | |
392f8b78 | 1033 | |
496bab39 JB |
1034 | /* This may fail if AMT took ownership of the device */ |
1035 | if (iwl_prepare_card_hw(trans)) { | |
6d8f6eeb | 1036 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
1037 | return -EIO; |
1038 | } | |
1039 | ||
1040 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
c9eec95c JB |
1041 | hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) & |
1042 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
1043 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
392f8b78 | 1044 | |
c9eec95c | 1045 | if (hw_rfkill) { |
6d8f6eeb | 1046 | iwl_enable_interrupts(trans); |
392f8b78 EG |
1047 | return -ERFKILL; |
1048 | } | |
1049 | ||
1042db2a | 1050 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 1051 | |
6d8f6eeb | 1052 | ret = iwl_nic_init(trans); |
392f8b78 | 1053 | if (ret) { |
6d8f6eeb | 1054 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
1055 | return ret; |
1056 | } | |
1057 | ||
1058 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1059 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1060 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
1061 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1062 | ||
1063 | /* clear (again), then enable host interrupts */ | |
1042db2a | 1064 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 1065 | iwl_enable_interrupts(trans); |
392f8b78 EG |
1066 | |
1067 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1068 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1069 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 1070 | |
cf614297 EG |
1071 | /* Load the given image to the HW */ |
1072 | iwl_load_given_ucode(trans, fw); | |
1073 | ||
392f8b78 EG |
1074 | return 0; |
1075 | } | |
1076 | ||
b3c2ce13 EG |
1077 | /* |
1078 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
7b11488f | 1079 | * must be called under the irq lock and with MAC access |
b3c2ce13 | 1080 | */ |
6d8f6eeb | 1081 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
b3c2ce13 | 1082 | { |
7b11488f JB |
1083 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1084 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1085 | ||
1086 | lockdep_assert_held(&trans_pcie->irq_lock); | |
1087 | ||
1042db2a | 1088 | iwl_write_prph(trans, SCD_TXFACT, mask); |
b3c2ce13 EG |
1089 | } |
1090 | ||
ed6a3803 | 1091 | static void iwl_tx_start(struct iwl_trans *trans) |
b3c2ce13 EG |
1092 | { |
1093 | const struct queue_to_fifo_ac *queue_to_fifo; | |
105183b1 EG |
1094 | struct iwl_trans_pcie *trans_pcie = |
1095 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
b3c2ce13 EG |
1096 | u32 a; |
1097 | unsigned long flags; | |
1098 | int i, chan; | |
1099 | u32 reg_val; | |
1100 | ||
7b11488f | 1101 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
b3c2ce13 | 1102 | |
83ed9015 | 1103 | trans_pcie->scd_base_addr = |
1042db2a | 1104 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); |
105183b1 | 1105 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
b3c2ce13 | 1106 | /* reset conext data memory */ |
105183b1 | 1107 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 | 1108 | a += 4) |
1042db2a | 1109 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1110 | /* reset tx status memory */ |
105183b1 | 1111 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 | 1112 | a += 4) |
1042db2a | 1113 | iwl_write_targ_mem(trans, a, 0); |
105183b1 | 1114 | for (; a < trans_pcie->scd_base_addr + |
c91bd124 | 1115 | SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num); |
d6189124 | 1116 | a += 4) |
1042db2a | 1117 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1118 | |
1042db2a | 1119 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, |
105183b1 | 1120 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 EG |
1121 | |
1122 | /* Enable DMA channel */ | |
1123 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
1042db2a | 1124 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
b3c2ce13 EG |
1125 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
1126 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
1127 | ||
1128 | /* Update FH chicken bits */ | |
1042db2a EG |
1129 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); |
1130 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
b3c2ce13 EG |
1131 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
1132 | ||
1042db2a | 1133 | iwl_write_prph(trans, SCD_QUEUECHAIN_SEL, |
c91bd124 | 1134 | SCD_QUEUECHAIN_SEL_ALL(trans)); |
1042db2a | 1135 | iwl_write_prph(trans, SCD_AGGR_SEL, 0); |
b3c2ce13 EG |
1136 | |
1137 | /* initiate the queues */ | |
c91bd124 | 1138 | for (i = 0; i < hw_params(trans).max_txq_num; i++) { |
1042db2a EG |
1139 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0); |
1140 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
1141 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + | |
b3c2ce13 | 1142 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
1042db2a | 1143 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
b3c2ce13 EG |
1144 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
1145 | sizeof(u32), | |
1146 | ((SCD_WIN_SIZE << | |
1147 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1148 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1149 | ((SCD_FRAME_LIMIT << | |
1150 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1151 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1152 | } | |
1153 | ||
1042db2a | 1154 | iwl_write_prph(trans, SCD_INTERRUPT_MASK, |
105183b1 | 1155 | IWL_MASK(0, hw_params(trans).max_txq_num)); |
b3c2ce13 EG |
1156 | |
1157 | /* Activate all Tx DMA/FIFO channels */ | |
6d8f6eeb | 1158 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
b3c2ce13 EG |
1159 | |
1160 | /* map queues to FIFOs */ | |
7a10e3e4 | 1161 | if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
b3c2ce13 EG |
1162 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; |
1163 | else | |
1164 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; | |
1165 | ||
6d8f6eeb | 1166 | iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0); |
b3c2ce13 EG |
1167 | |
1168 | /* make sure all queue are not stopped */ | |
8ad71bef EG |
1169 | memset(&trans_pcie->queue_stopped[0], 0, |
1170 | sizeof(trans_pcie->queue_stopped)); | |
b3c2ce13 | 1171 | for (i = 0; i < 4; i++) |
8ad71bef | 1172 | atomic_set(&trans_pcie->queue_stop_count[i], 0); |
b3c2ce13 EG |
1173 | |
1174 | /* reset to 0 to enable all the queue first */ | |
8ad71bef | 1175 | trans_pcie->txq_ctx_active_msk = 0; |
b3c2ce13 | 1176 | |
effcea16 | 1177 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) < |
72c04ce0 | 1178 | IWLAGN_FIRST_AMPDU_QUEUE); |
effcea16 | 1179 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) < |
72c04ce0 | 1180 | IWLAGN_FIRST_AMPDU_QUEUE); |
b3c2ce13 | 1181 | |
72c04ce0 | 1182 | for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) { |
b3c2ce13 EG |
1183 | int fifo = queue_to_fifo[i].fifo; |
1184 | int ac = queue_to_fifo[i].ac; | |
1185 | ||
8ad71bef | 1186 | iwl_txq_ctx_activate(trans_pcie, i); |
b3c2ce13 EG |
1187 | |
1188 | if (fifo == IWL_TX_FIFO_UNUSED) | |
1189 | continue; | |
1190 | ||
1191 | if (ac != IWL_AC_UNSET) | |
8ad71bef EG |
1192 | iwl_set_swq_id(&trans_pcie->txq[i], ac, i); |
1193 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], | |
1194 | fifo, 0); | |
b3c2ce13 EG |
1195 | } |
1196 | ||
7b11488f | 1197 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
b3c2ce13 EG |
1198 | |
1199 | /* Enable L1-Active */ | |
1042db2a | 1200 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, |
b3c2ce13 EG |
1201 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
1202 | } | |
1203 | ||
ed6a3803 EG |
1204 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) |
1205 | { | |
1206 | iwl_reset_ict(trans); | |
1207 | iwl_tx_start(trans); | |
1208 | } | |
1209 | ||
c170b867 EG |
1210 | /** |
1211 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
1212 | */ | |
6d8f6eeb | 1213 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
c170b867 EG |
1214 | { |
1215 | int ch, txq_id; | |
1216 | unsigned long flags; | |
8ad71bef | 1217 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c170b867 EG |
1218 | |
1219 | /* Turn off all Tx DMA fifos */ | |
7b11488f | 1220 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
c170b867 | 1221 | |
6d8f6eeb | 1222 | iwl_trans_txq_set_sched(trans, 0); |
c170b867 EG |
1223 | |
1224 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 1225 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
1042db2a | 1226 | iwl_write_direct32(trans, |
6d8f6eeb | 1227 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
1042db2a | 1228 | if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, |
c170b867 EG |
1229 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
1230 | 1000)) | |
6d8f6eeb | 1231 | IWL_ERR(trans, "Failing on timeout while stopping" |
c170b867 | 1232 | " DMA channel %d [0x%08x]", ch, |
1042db2a | 1233 | iwl_read_direct32(trans, |
6d8f6eeb | 1234 | FH_TSSR_TX_STATUS_REG)); |
c170b867 | 1235 | } |
7b11488f | 1236 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
c170b867 | 1237 | |
8ad71bef | 1238 | if (!trans_pcie->txq) { |
6d8f6eeb | 1239 | IWL_WARN(trans, "Stopping tx queues that aren't allocated..."); |
c170b867 EG |
1240 | return 0; |
1241 | } | |
1242 | ||
1243 | /* Unmap DMA from host system and free skb's */ | |
6d8f6eeb EG |
1244 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) |
1245 | iwl_tx_queue_unmap(trans, txq_id); | |
c170b867 EG |
1246 | |
1247 | return 0; | |
1248 | } | |
1249 | ||
43e58856 | 1250 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf EG |
1251 | { |
1252 | unsigned long flags; | |
43e58856 | 1253 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ae2c30bf | 1254 | |
43e58856 | 1255 | /* tell the device to stop sending interrupts */ |
7b11488f | 1256 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1257 | iwl_disable_interrupts(trans); |
7b11488f | 1258 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1259 | |
ab6cf8e8 | 1260 | /* device going down, Stop using ICT table */ |
6d8f6eeb | 1261 | iwl_disable_ict(trans); |
ab6cf8e8 EG |
1262 | |
1263 | /* | |
1264 | * If a HW restart happens during firmware loading, | |
1265 | * then the firmware loading might call this function | |
1266 | * and later it might be called again due to the | |
1267 | * restart. So don't process again if the device is | |
1268 | * already dead. | |
1269 | */ | |
6d8f6eeb EG |
1270 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) { |
1271 | iwl_trans_tx_stop(trans); | |
a5916977 | 1272 | #ifndef CONFIG_IWLWIFI_IDI |
6d8f6eeb | 1273 | iwl_trans_rx_stop(trans); |
a5916977 | 1274 | #endif |
ab6cf8e8 | 1275 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 1276 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1277 | APMG_CLK_VAL_DMA_CLK_RQT); |
1278 | udelay(5); | |
1279 | } | |
1280 | ||
1281 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1282 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
6d8f6eeb | 1283 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1284 | |
1285 | /* Stop the device, and put it in low power state */ | |
cc56feb2 | 1286 | iwl_apm_stop(trans); |
43e58856 EG |
1287 | |
1288 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1289 | * Clean again the interrupt here | |
1290 | */ | |
7b11488f | 1291 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 1292 | iwl_disable_interrupts(trans); |
7b11488f | 1293 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 EG |
1294 | |
1295 | /* wait to make sure we flush pending tasklet*/ | |
a42a1844 | 1296 | synchronize_irq(trans->irq); |
43e58856 EG |
1297 | tasklet_kill(&trans_pcie->irq_tasklet); |
1298 | ||
1ee158d8 JB |
1299 | cancel_work_sync(&trans_pcie->rx_replenish); |
1300 | ||
43e58856 | 1301 | /* stop and reset the on-board processor */ |
1042db2a | 1302 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
ab6cf8e8 EG |
1303 | } |
1304 | ||
2dd4f9f7 JB |
1305 | static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans) |
1306 | { | |
1307 | /* let the ucode operate on its own */ | |
1308 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
1309 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
1310 | ||
1311 | iwl_disable_interrupts(trans); | |
1312 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
1313 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1314 | } | |
1315 | ||
e13c0c59 | 1316 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
14991a9d | 1317 | struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx, |
34b5321e | 1318 | u8 sta_id, u8 tid) |
47c1b496 | 1319 | { |
e13c0c59 EG |
1320 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1321 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
1322 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
132f98c2 | 1323 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
47c1b496 | 1324 | struct iwl_cmd_meta *out_meta; |
e13c0c59 EG |
1325 | struct iwl_tx_queue *txq; |
1326 | struct iwl_queue *q; | |
47c1b496 EG |
1327 | |
1328 | dma_addr_t phys_addr = 0; | |
1329 | dma_addr_t txcmd_phys; | |
1330 | dma_addr_t scratch_phys; | |
1331 | u16 len, firstlen, secondlen; | |
1332 | u8 wait_write_ptr = 0; | |
e13c0c59 | 1333 | u8 txq_id; |
e13c0c59 EG |
1334 | bool is_agg = false; |
1335 | __le16 fc = hdr->frame_control; | |
47c1b496 | 1336 | u8 hdr_len = ieee80211_hdrlen(fc); |
631b84c5 | 1337 | u16 __maybe_unused wifi_seq; |
47c1b496 | 1338 | |
e13c0c59 EG |
1339 | /* |
1340 | * Send this frame after DTIM -- there's a special queue | |
1341 | * reserved for this for contexts that support AP mode. | |
1342 | */ | |
1343 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { | |
1344 | txq_id = trans_pcie->mcast_queue[ctx]; | |
1345 | ||
1346 | /* | |
1347 | * The microcode will clear the more data | |
1348 | * bit in the last frame it transmits. | |
1349 | */ | |
1350 | hdr->frame_control |= | |
1351 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1352 | } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) | |
1353 | txq_id = IWL_AUX_QUEUE; | |
1354 | else | |
1355 | txq_id = | |
1356 | trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)]; | |
1357 | ||
97756fb1 EG |
1358 | /* aggregation is on for this <sta,tid> */ |
1359 | if (info->flags & IEEE80211_TX_CTL_AMPDU) { | |
1360 | WARN_ON(tid >= IWL_MAX_TID_COUNT); | |
1361 | txq_id = trans_pcie->agg_txq[sta_id][tid]; | |
1362 | is_agg = true; | |
e13c0c59 EG |
1363 | } |
1364 | ||
8ad71bef | 1365 | txq = &trans_pcie->txq[txq_id]; |
e13c0c59 EG |
1366 | q = &txq->q; |
1367 | ||
015c15e1 JB |
1368 | spin_lock(&txq->lock); |
1369 | ||
631b84c5 EG |
1370 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1371 | * sequence number. This is a HW requirements to help the SCD to parse | |
1372 | * the BA. | |
1373 | * Check here that the packets are in the right place on the ring. | |
1374 | */ | |
1375 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1376 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1377 | WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr), | |
1378 | "Q: %d WiFi Seq %d tfdNum %d", | |
1379 | txq_id, wifi_seq, q->write_ptr); | |
1380 | #endif | |
1381 | ||
47c1b496 | 1382 | /* Set up driver data for this TFD */ |
2c452297 | 1383 | txq->skbs[q->write_ptr] = skb; |
dfa2bdba EG |
1384 | txq->cmd[q->write_ptr] = dev_cmd; |
1385 | ||
1386 | dev_cmd->hdr.cmd = REPLY_TX; | |
1387 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1388 | INDEX_TO_SEQ(q->write_ptr))); | |
47c1b496 EG |
1389 | |
1390 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1391 | out_meta = &txq->meta[q->write_ptr]; | |
1392 | ||
1393 | /* | |
1394 | * Use the first empty entry in this queue's command buffer array | |
1395 | * to contain the Tx command and MAC header concatenated together | |
1396 | * (payload data will be in another buffer). | |
1397 | * Size of this varies, due to varying MAC header length. | |
1398 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1399 | * of the MAC header (device reads on dword boundaries). | |
1400 | * We'll tell device about this padding later. | |
1401 | */ | |
1402 | len = sizeof(struct iwl_tx_cmd) + | |
1403 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1404 | firstlen = (len + 3) & ~3; | |
1405 | ||
1406 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1407 | if (firstlen != len) | |
1408 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1409 | ||
1410 | /* Physical address of this Tx command's header (not MAC header!), | |
1411 | * within command buffer array. */ | |
1042db2a | 1412 | txcmd_phys = dma_map_single(trans->dev, |
47c1b496 EG |
1413 | &dev_cmd->hdr, firstlen, |
1414 | DMA_BIDIRECTIONAL); | |
1042db2a | 1415 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) |
015c15e1 | 1416 | goto out_err; |
47c1b496 EG |
1417 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
1418 | dma_unmap_len_set(out_meta, len, firstlen); | |
1419 | ||
1420 | if (!ieee80211_has_morefrags(fc)) { | |
1421 | txq->need_update = 1; | |
1422 | } else { | |
1423 | wait_write_ptr = 1; | |
1424 | txq->need_update = 0; | |
1425 | } | |
1426 | ||
1427 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1428 | * if any (802.11 null frames have no payload). */ | |
1429 | secondlen = skb->len - hdr_len; | |
1430 | if (secondlen > 0) { | |
1042db2a | 1431 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, |
47c1b496 | 1432 | secondlen, DMA_TO_DEVICE); |
1042db2a EG |
1433 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
1434 | dma_unmap_single(trans->dev, | |
47c1b496 EG |
1435 | dma_unmap_addr(out_meta, mapping), |
1436 | dma_unmap_len(out_meta, len), | |
1437 | DMA_BIDIRECTIONAL); | |
015c15e1 | 1438 | goto out_err; |
47c1b496 EG |
1439 | } |
1440 | } | |
1441 | ||
1442 | /* Attach buffers to TFD */ | |
e13c0c59 | 1443 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
47c1b496 | 1444 | if (secondlen > 0) |
e13c0c59 | 1445 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
47c1b496 EG |
1446 | secondlen, 0); |
1447 | ||
1448 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1449 | offsetof(struct iwl_tx_cmd, scratch); | |
1450 | ||
1451 | /* take back ownership of DMA buffer to enable update */ | |
1042db2a | 1452 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1453 | DMA_BIDIRECTIONAL); |
1454 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1455 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1456 | ||
e13c0c59 | 1457 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
47c1b496 | 1458 | le16_to_cpu(dev_cmd->hdr.sequence)); |
e13c0c59 EG |
1459 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
1460 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
1461 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
47c1b496 EG |
1462 | |
1463 | /* Set up entry for this TFD in Tx byte-count array */ | |
96f1f05a | 1464 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); |
47c1b496 | 1465 | |
1042db2a | 1466 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1467 | DMA_BIDIRECTIONAL); |
1468 | ||
6c1011e1 | 1469 | trace_iwlwifi_dev_tx(trans->dev, |
47c1b496 EG |
1470 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], |
1471 | sizeof(struct iwl_tfd), | |
1472 | &dev_cmd->hdr, firstlen, | |
1473 | skb->data + hdr_len, secondlen); | |
1474 | ||
1475 | /* Tell device the write index *just past* this latest filled TFD */ | |
1476 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
e13c0c59 EG |
1477 | iwl_txq_update_write_ptr(trans, txq); |
1478 | ||
47c1b496 EG |
1479 | /* |
1480 | * At this point the frame is "transmitted" successfully | |
1481 | * and we will get a TX status notification eventually, | |
1482 | * regardless of the value of ret. "ret" only indicates | |
1483 | * whether or not we should update the write pointer. | |
1484 | */ | |
a0eaad71 | 1485 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1486 | if (wait_write_ptr) { |
1487 | txq->need_update = 1; | |
e13c0c59 | 1488 | iwl_txq_update_write_ptr(trans, txq); |
47c1b496 | 1489 | } else { |
81a3de1c | 1490 | iwl_stop_queue(trans, txq, "Queue is full"); |
47c1b496 EG |
1491 | } |
1492 | } | |
015c15e1 | 1493 | spin_unlock(&txq->lock); |
47c1b496 | 1494 | return 0; |
015c15e1 JB |
1495 | out_err: |
1496 | spin_unlock(&txq->lock); | |
1497 | return -1; | |
47c1b496 EG |
1498 | } |
1499 | ||
57a1dc89 | 1500 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 1501 | { |
5a878bf6 EG |
1502 | struct iwl_trans_pcie *trans_pcie = |
1503 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
e6bb4c9c | 1504 | int err; |
c9eec95c | 1505 | bool hw_rfkill; |
e6bb4c9c | 1506 | |
0c325769 EG |
1507 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1508 | ||
57a1dc89 EG |
1509 | if (!trans_pcie->irq_requested) { |
1510 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1511 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1512 | |
57a1dc89 | 1513 | iwl_alloc_isr_ict(trans); |
e6bb4c9c | 1514 | |
57a1dc89 EG |
1515 | err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED, |
1516 | DRV_NAME, trans); | |
1517 | if (err) { | |
1518 | IWL_ERR(trans, "Error allocating IRQ %d\n", | |
1519 | trans->irq); | |
ebb7678d | 1520 | goto error; |
57a1dc89 EG |
1521 | } |
1522 | ||
1523 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); | |
1524 | trans_pcie->irq_requested = true; | |
e6bb4c9c EG |
1525 | } |
1526 | ||
ebb7678d EG |
1527 | err = iwl_prepare_card_hw(trans); |
1528 | if (err) { | |
1529 | IWL_ERR(trans, "Error while preparing HW: %d", err); | |
f057ac4e | 1530 | goto err_free_irq; |
ebb7678d | 1531 | } |
a6c684ee EG |
1532 | |
1533 | iwl_apm_init(trans); | |
1534 | ||
c9eec95c JB |
1535 | hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) & |
1536 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
1537 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
d48e2074 | 1538 | |
ebb7678d EG |
1539 | return err; |
1540 | ||
f057ac4e JB |
1541 | err_free_irq: |
1542 | free_irq(trans->irq, trans); | |
ebb7678d EG |
1543 | error: |
1544 | iwl_free_isr_ict(trans); | |
1545 | tasklet_kill(&trans_pcie->irq_tasklet); | |
1546 | return err; | |
e6bb4c9c EG |
1547 | } |
1548 | ||
cc56feb2 EG |
1549 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans) |
1550 | { | |
1551 | iwl_apm_stop(trans); | |
1552 | ||
1df06bdc EG |
1553 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
1554 | ||
cc56feb2 EG |
1555 | /* Even if we stop the HW, we still want the RF kill interrupt */ |
1556 | IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); | |
1557 | iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); | |
1558 | } | |
1559 | ||
76bc10fc | 1560 | static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid, |
464021ff EG |
1561 | int txq_id, int ssn, u32 status, |
1562 | struct sk_buff_head *skbs) | |
1563 | { | |
8ad71bef EG |
1564 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1565 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 EG |
1566 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
1567 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
464021ff | 1568 | int freed = 0; |
a0eaad71 | 1569 | |
015c15e1 JB |
1570 | spin_lock(&txq->lock); |
1571 | ||
8ad71bef EG |
1572 | txq->time_stamp = jiffies; |
1573 | ||
76bc10fc | 1574 | if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE && |
3d29dd9b | 1575 | tid != IWL_TID_NON_QOS && |
76bc10fc EG |
1576 | txq_id != trans_pcie->agg_txq[sta_id][tid])) { |
1577 | /* | |
1578 | * FIXME: this is a uCode bug which need to be addressed, | |
1579 | * log the information and return for now. | |
1580 | * Since it is can possibly happen very often and in order | |
1581 | * not to fill the syslog, don't use IWL_ERR or IWL_WARN | |
1582 | */ | |
1583 | IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, " | |
1584 | "agg_txq[sta_id[tid] %d", txq_id, | |
1585 | trans_pcie->agg_txq[sta_id][tid]); | |
015c15e1 | 1586 | spin_unlock(&txq->lock); |
76bc10fc | 1587 | return 1; |
a0eaad71 EG |
1588 | } |
1589 | ||
1590 | if (txq->q.read_ptr != tfd_num) { | |
1daf04b8 EG |
1591 | IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n", |
1592 | txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr, | |
1593 | tfd_num, ssn); | |
464021ff | 1594 | freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
1ba42da4 EG |
1595 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && |
1596 | (!txq->sched_retry || | |
1597 | status != TX_STATUS_FAIL_PASSIVE_NO_RX)) | |
81a3de1c | 1598 | iwl_wake_queue(trans, txq, "Packets reclaimed"); |
a0eaad71 | 1599 | } |
015c15e1 JB |
1600 | |
1601 | spin_unlock(&txq->lock); | |
76bc10fc | 1602 | return 0; |
a0eaad71 EG |
1603 | } |
1604 | ||
03905495 EG |
1605 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1606 | { | |
1607 | iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); | |
1608 | } | |
1609 | ||
1610 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1611 | { | |
1612 | iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); | |
1613 | } | |
1614 | ||
1615 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1616 | { | |
1617 | u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); | |
1618 | return val; | |
1619 | } | |
1620 | ||
6d8f6eeb | 1621 | static void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1622 | { |
a42a1844 EG |
1623 | struct iwl_trans_pcie *trans_pcie = |
1624 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1625 | ||
ae2c30bf | 1626 | iwl_trans_pcie_tx_free(trans); |
a5916977 | 1627 | #ifndef CONFIG_IWLWIFI_IDI |
ae2c30bf | 1628 | iwl_trans_pcie_rx_free(trans); |
a5916977 | 1629 | #endif |
57a1dc89 EG |
1630 | if (trans_pcie->irq_requested == true) { |
1631 | free_irq(trans->irq, trans); | |
1632 | iwl_free_isr_ict(trans); | |
1633 | } | |
a42a1844 EG |
1634 | |
1635 | pci_disable_msi(trans_pcie->pci_dev); | |
1636 | pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base); | |
1637 | pci_release_regions(trans_pcie->pci_dev); | |
1638 | pci_disable_device(trans_pcie->pci_dev); | |
1639 | ||
6d8f6eeb EG |
1640 | trans->shrd->trans = NULL; |
1641 | kfree(trans); | |
34c1b7ba EG |
1642 | } |
1643 | ||
c01a4047 | 1644 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1645 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
1646 | { | |
57210f7c EG |
1647 | return 0; |
1648 | } | |
1649 | ||
1650 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1651 | { | |
c9eec95c | 1652 | bool hw_rfkill; |
57210f7c | 1653 | |
0c325769 | 1654 | iwl_enable_interrupts(trans); |
57210f7c | 1655 | |
c9eec95c JB |
1656 | hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) & |
1657 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
7120d989 | 1658 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
57210f7c EG |
1659 | |
1660 | return 0; | |
1661 | } | |
c01a4047 | 1662 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 1663 | |
e13c0c59 | 1664 | static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans, |
81a3de1c EG |
1665 | enum iwl_rxon_context_id ctx, |
1666 | const char *msg) | |
e13c0c59 EG |
1667 | { |
1668 | u8 ac, txq_id; | |
1669 | struct iwl_trans_pcie *trans_pcie = | |
1670 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1671 | ||
1672 | for (ac = 0; ac < AC_NUM; ac++) { | |
1673 | txq_id = trans_pcie->ac_to_queue[ctx][ac]; | |
81a3de1c | 1674 | IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n", |
e13c0c59 | 1675 | ac, |
8ad71bef | 1676 | (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0) |
e13c0c59 | 1677 | ? "stopped" : "awake"); |
81a3de1c | 1678 | iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg); |
e13c0c59 EG |
1679 | } |
1680 | } | |
1681 | ||
81a3de1c EG |
1682 | static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id, |
1683 | const char *msg) | |
e20d4341 | 1684 | { |
8ad71bef EG |
1685 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1686 | ||
81a3de1c | 1687 | iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg); |
e20d4341 EG |
1688 | } |
1689 | ||
5f178cd2 EG |
1690 | #define IWL_FLUSH_WAIT_MS 2000 |
1691 | ||
1692 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) | |
1693 | { | |
8ad71bef | 1694 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5f178cd2 EG |
1695 | struct iwl_tx_queue *txq; |
1696 | struct iwl_queue *q; | |
1697 | int cnt; | |
1698 | unsigned long now = jiffies; | |
1699 | int ret = 0; | |
1700 | ||
1701 | /* waiting for all the tx frames complete might take a while */ | |
1702 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { | |
1703 | if (cnt == trans->shrd->cmd_queue) | |
1704 | continue; | |
8ad71bef | 1705 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1706 | q = &txq->q; |
1707 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1708 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1709 | msleep(1); | |
1710 | ||
1711 | if (q->read_ptr != q->write_ptr) { | |
1712 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
1713 | ret = -ETIMEDOUT; | |
1714 | break; | |
1715 | } | |
1716 | } | |
1717 | return ret; | |
1718 | } | |
1719 | ||
f22be624 EG |
1720 | /* |
1721 | * On every watchdog tick we check (latest) time stamp. If it does not | |
1722 | * change during timeout period and queue is not empty we reset firmware. | |
1723 | */ | |
1724 | static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt) | |
1725 | { | |
8ad71bef EG |
1726 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1727 | struct iwl_tx_queue *txq = &trans_pcie->txq[cnt]; | |
f22be624 EG |
1728 | struct iwl_queue *q = &txq->q; |
1729 | unsigned long timeout; | |
1730 | ||
1731 | if (q->read_ptr == q->write_ptr) { | |
1732 | txq->time_stamp = jiffies; | |
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | timeout = txq->time_stamp + | |
1737 | msecs_to_jiffies(hw_params(trans).wd_timeout); | |
1738 | ||
1739 | if (time_after(jiffies, timeout)) { | |
1740 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, | |
1741 | hw_params(trans).wd_timeout); | |
08d1700d | 1742 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
05f8a09f | 1743 | q->read_ptr, q->write_ptr); |
08d1700d | 1744 | IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n", |
1042db2a | 1745 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) |
08d1700d | 1746 | & (TFD_QUEUE_SIZE_MAX - 1), |
1042db2a | 1747 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); |
f22be624 EG |
1748 | return 1; |
1749 | } | |
1750 | ||
1751 | return 0; | |
1752 | } | |
1753 | ||
ff620849 EG |
1754 | static const char *get_fh_string(int cmd) |
1755 | { | |
1756 | switch (cmd) { | |
1757 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1758 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1759 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1760 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1761 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1762 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1763 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1764 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1765 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1766 | default: | |
1767 | return "UNKNOWN"; | |
1768 | } | |
1769 | } | |
1770 | ||
1771 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | |
1772 | { | |
1773 | int i; | |
1774 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1775 | int pos = 0; | |
1776 | size_t bufsz = 0; | |
1777 | #endif | |
1778 | static const u32 fh_tbl[] = { | |
1779 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1780 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1781 | FH_RSCSR_CHNL0_WPTR, | |
1782 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1783 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1784 | FH_MEM_RSSR_RX_STATUS_REG, | |
1785 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1786 | FH_TSSR_TX_STATUS_REG, | |
1787 | FH_TSSR_TX_ERROR_REG | |
1788 | }; | |
1789 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1790 | if (display) { | |
1791 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1792 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1793 | if (!*buf) | |
1794 | return -ENOMEM; | |
1795 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1796 | "FH register values:\n"); | |
1797 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1798 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1799 | " %34s: 0X%08x\n", | |
1800 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1801 | iwl_read_direct32(trans, fh_tbl[i])); |
ff620849 EG |
1802 | } |
1803 | return pos; | |
1804 | } | |
1805 | #endif | |
1806 | IWL_ERR(trans, "FH register values:\n"); | |
1807 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1808 | IWL_ERR(trans, " %34s: 0X%08x\n", | |
1809 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1810 | iwl_read_direct32(trans, fh_tbl[i])); |
ff620849 EG |
1811 | } |
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | static const char *get_csr_string(int cmd) | |
1816 | { | |
1817 | switch (cmd) { | |
1818 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1819 | IWL_CMD(CSR_INT_COALESCING); | |
1820 | IWL_CMD(CSR_INT); | |
1821 | IWL_CMD(CSR_INT_MASK); | |
1822 | IWL_CMD(CSR_FH_INT_STATUS); | |
1823 | IWL_CMD(CSR_GPIO_IN); | |
1824 | IWL_CMD(CSR_RESET); | |
1825 | IWL_CMD(CSR_GP_CNTRL); | |
1826 | IWL_CMD(CSR_HW_REV); | |
1827 | IWL_CMD(CSR_EEPROM_REG); | |
1828 | IWL_CMD(CSR_EEPROM_GP); | |
1829 | IWL_CMD(CSR_OTP_GP_REG); | |
1830 | IWL_CMD(CSR_GIO_REG); | |
1831 | IWL_CMD(CSR_GP_UCODE_REG); | |
1832 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1833 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1834 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1835 | IWL_CMD(CSR_LED_REG); | |
1836 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1837 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1838 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1839 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1840 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1841 | default: | |
1842 | return "UNKNOWN"; | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | void iwl_dump_csr(struct iwl_trans *trans) | |
1847 | { | |
1848 | int i; | |
1849 | static const u32 csr_tbl[] = { | |
1850 | CSR_HW_IF_CONFIG_REG, | |
1851 | CSR_INT_COALESCING, | |
1852 | CSR_INT, | |
1853 | CSR_INT_MASK, | |
1854 | CSR_FH_INT_STATUS, | |
1855 | CSR_GPIO_IN, | |
1856 | CSR_RESET, | |
1857 | CSR_GP_CNTRL, | |
1858 | CSR_HW_REV, | |
1859 | CSR_EEPROM_REG, | |
1860 | CSR_EEPROM_GP, | |
1861 | CSR_OTP_GP_REG, | |
1862 | CSR_GIO_REG, | |
1863 | CSR_GP_UCODE_REG, | |
1864 | CSR_GP_DRIVER_REG, | |
1865 | CSR_UCODE_DRV_GP1, | |
1866 | CSR_UCODE_DRV_GP2, | |
1867 | CSR_LED_REG, | |
1868 | CSR_DRAM_INT_TBL_REG, | |
1869 | CSR_GIO_CHICKEN_BITS, | |
1870 | CSR_ANA_PLL_CFG, | |
1871 | CSR_HW_REV_WA_REG, | |
1872 | CSR_DBG_HPET_MEM_REG | |
1873 | }; | |
1874 | IWL_ERR(trans, "CSR values:\n"); | |
1875 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1876 | "CSR_INT_PERIODIC_REG)\n"); | |
1877 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1878 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1879 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1880 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1881 | } |
1882 | } | |
1883 | ||
87e5666c EG |
1884 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1885 | /* create and remove of files */ | |
1886 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1887 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c EG |
1888 | &iwl_dbgfs_##name##_ops)) \ |
1889 | return -ENOMEM; \ | |
1890 | } while (0) | |
1891 | ||
1892 | /* file operation */ | |
1893 | #define DEBUGFS_READ_FUNC(name) \ | |
1894 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1895 | char __user *user_buf, \ | |
1896 | size_t count, loff_t *ppos); | |
1897 | ||
1898 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1899 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1900 | const char __user *user_buf, \ | |
1901 | size_t count, loff_t *ppos); | |
1902 | ||
1903 | ||
1904 | static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file) | |
1905 | { | |
1906 | file->private_data = inode->i_private; | |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | #define DEBUGFS_READ_FILE_OPS(name) \ | |
1911 | DEBUGFS_READ_FUNC(name); \ | |
1912 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1913 | .read = iwl_dbgfs_##name##_read, \ | |
1914 | .open = iwl_dbgfs_open_file_generic, \ | |
1915 | .llseek = generic_file_llseek, \ | |
1916 | }; | |
1917 | ||
16db88ba EG |
1918 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1919 | DEBUGFS_WRITE_FUNC(name); \ | |
1920 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1921 | .write = iwl_dbgfs_##name##_write, \ | |
1922 | .open = iwl_dbgfs_open_file_generic, \ | |
1923 | .llseek = generic_file_llseek, \ | |
1924 | }; | |
1925 | ||
87e5666c EG |
1926 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1927 | DEBUGFS_READ_FUNC(name); \ | |
1928 | DEBUGFS_WRITE_FUNC(name); \ | |
1929 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1930 | .write = iwl_dbgfs_##name##_write, \ | |
1931 | .read = iwl_dbgfs_##name##_read, \ | |
1932 | .open = iwl_dbgfs_open_file_generic, \ | |
1933 | .llseek = generic_file_llseek, \ | |
1934 | }; | |
1935 | ||
87e5666c EG |
1936 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
1937 | char __user *user_buf, | |
8ad71bef EG |
1938 | size_t count, loff_t *ppos) |
1939 | { | |
5a878bf6 | 1940 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1941 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
87e5666c EG |
1942 | struct iwl_tx_queue *txq; |
1943 | struct iwl_queue *q; | |
1944 | char *buf; | |
1945 | int pos = 0; | |
1946 | int cnt; | |
1947 | int ret; | |
fd656935 | 1948 | const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num; |
87e5666c | 1949 | |
8ad71bef | 1950 | if (!trans_pcie->txq) { |
3e10caeb | 1951 | IWL_ERR(trans, "txq not ready\n"); |
87e5666c EG |
1952 | return -EAGAIN; |
1953 | } | |
1954 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1955 | if (!buf) | |
1956 | return -ENOMEM; | |
1957 | ||
5a878bf6 | 1958 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
8ad71bef | 1959 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1960 | q = &txq->q; |
1961 | pos += scnprintf(buf + pos, bufsz - pos, | |
1962 | "hwq %.2d: read=%u write=%u stop=%d" | |
1963 | " swq_id=%#.2x (ac %d/hwq %d)\n", | |
1964 | cnt, q->read_ptr, q->write_ptr, | |
8ad71bef | 1965 | !!test_bit(cnt, trans_pcie->queue_stopped), |
87e5666c EG |
1966 | txq->swq_id, txq->swq_id & 3, |
1967 | (txq->swq_id >> 2) & 0x1f); | |
1968 | if (cnt >= 4) | |
1969 | continue; | |
1970 | /* for the ACs, display the stop count too */ | |
1971 | pos += scnprintf(buf + pos, bufsz - pos, | |
8ad71bef EG |
1972 | " stop-count: %d\n", |
1973 | atomic_read(&trans_pcie->queue_stop_count[cnt])); | |
87e5666c EG |
1974 | } |
1975 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1976 | kfree(buf); | |
1977 | return ret; | |
1978 | } | |
1979 | ||
1980 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
1981 | char __user *user_buf, | |
1982 | size_t count, loff_t *ppos) { | |
5a878bf6 EG |
1983 | struct iwl_trans *trans = file->private_data; |
1984 | struct iwl_trans_pcie *trans_pcie = | |
1985 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1986 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
87e5666c EG |
1987 | char buf[256]; |
1988 | int pos = 0; | |
1989 | const size_t bufsz = sizeof(buf); | |
1990 | ||
1991 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1992 | rxq->read); | |
1993 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1994 | rxq->write); | |
1995 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1996 | rxq->free_count); | |
1997 | if (rxq->rb_stts) { | |
1998 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1999 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
2000 | } else { | |
2001 | pos += scnprintf(buf + pos, bufsz - pos, | |
2002 | "closed_rb_num: Not Allocated\n"); | |
2003 | } | |
2004 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2005 | } | |
2006 | ||
7ff94706 EG |
2007 | static ssize_t iwl_dbgfs_log_event_read(struct file *file, |
2008 | char __user *user_buf, | |
2009 | size_t count, loff_t *ppos) | |
2010 | { | |
2011 | struct iwl_trans *trans = file->private_data; | |
2012 | char *buf; | |
2013 | int pos = 0; | |
2014 | ssize_t ret = -ENOMEM; | |
2015 | ||
6bb78847 | 2016 | ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true); |
7ff94706 EG |
2017 | if (buf) { |
2018 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2019 | kfree(buf); | |
2020 | } | |
2021 | return ret; | |
2022 | } | |
2023 | ||
2024 | static ssize_t iwl_dbgfs_log_event_write(struct file *file, | |
2025 | const char __user *user_buf, | |
2026 | size_t count, loff_t *ppos) | |
2027 | { | |
2028 | struct iwl_trans *trans = file->private_data; | |
2029 | u32 event_log_flag; | |
2030 | char buf[8]; | |
2031 | int buf_size; | |
2032 | ||
2033 | memset(buf, 0, sizeof(buf)); | |
2034 | buf_size = min(count, sizeof(buf) - 1); | |
2035 | if (copy_from_user(buf, user_buf, buf_size)) | |
2036 | return -EFAULT; | |
2037 | if (sscanf(buf, "%d", &event_log_flag) != 1) | |
2038 | return -EFAULT; | |
2039 | if (event_log_flag == 1) | |
6bb78847 | 2040 | iwl_dump_nic_event_log(trans, true, NULL, false); |
7ff94706 EG |
2041 | |
2042 | return count; | |
2043 | } | |
2044 | ||
1f7b6172 EG |
2045 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
2046 | char __user *user_buf, | |
2047 | size_t count, loff_t *ppos) { | |
2048 | ||
2049 | struct iwl_trans *trans = file->private_data; | |
2050 | struct iwl_trans_pcie *trans_pcie = | |
2051 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
2052 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
2053 | ||
2054 | int pos = 0; | |
2055 | char *buf; | |
2056 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
2057 | ssize_t ret; | |
2058 | ||
2059 | buf = kzalloc(bufsz, GFP_KERNEL); | |
2060 | if (!buf) { | |
2061 | IWL_ERR(trans, "Can not allocate Buffer\n"); | |
2062 | return -ENOMEM; | |
2063 | } | |
2064 | ||
2065 | pos += scnprintf(buf + pos, bufsz - pos, | |
2066 | "Interrupt Statistics Report:\n"); | |
2067 | ||
2068 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
2069 | isr_stats->hw); | |
2070 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
2071 | isr_stats->sw); | |
2072 | if (isr_stats->sw || isr_stats->hw) { | |
2073 | pos += scnprintf(buf + pos, bufsz - pos, | |
2074 | "\tLast Restarting Code: 0x%X\n", | |
2075 | isr_stats->err_code); | |
2076 | } | |
2077 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2078 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
2079 | isr_stats->sch); | |
2080 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
2081 | isr_stats->alive); | |
2082 | #endif | |
2083 | pos += scnprintf(buf + pos, bufsz - pos, | |
2084 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
2085 | ||
2086 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
2087 | isr_stats->ctkill); | |
2088 | ||
2089 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
2090 | isr_stats->wakeup); | |
2091 | ||
2092 | pos += scnprintf(buf + pos, bufsz - pos, | |
2093 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
2094 | ||
2095 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
2096 | isr_stats->tx); | |
2097 | ||
2098 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
2099 | isr_stats->unhandled); | |
2100 | ||
2101 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2102 | kfree(buf); | |
2103 | return ret; | |
2104 | } | |
2105 | ||
2106 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
2107 | const char __user *user_buf, | |
2108 | size_t count, loff_t *ppos) | |
2109 | { | |
2110 | struct iwl_trans *trans = file->private_data; | |
2111 | struct iwl_trans_pcie *trans_pcie = | |
2112 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
2113 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
2114 | ||
2115 | char buf[8]; | |
2116 | int buf_size; | |
2117 | u32 reset_flag; | |
2118 | ||
2119 | memset(buf, 0, sizeof(buf)); | |
2120 | buf_size = min(count, sizeof(buf) - 1); | |
2121 | if (copy_from_user(buf, user_buf, buf_size)) | |
2122 | return -EFAULT; | |
2123 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
2124 | return -EFAULT; | |
2125 | if (reset_flag == 0) | |
2126 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
2127 | ||
2128 | return count; | |
2129 | } | |
2130 | ||
16db88ba EG |
2131 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
2132 | const char __user *user_buf, | |
2133 | size_t count, loff_t *ppos) | |
2134 | { | |
2135 | struct iwl_trans *trans = file->private_data; | |
2136 | char buf[8]; | |
2137 | int buf_size; | |
2138 | int csr; | |
2139 | ||
2140 | memset(buf, 0, sizeof(buf)); | |
2141 | buf_size = min(count, sizeof(buf) - 1); | |
2142 | if (copy_from_user(buf, user_buf, buf_size)) | |
2143 | return -EFAULT; | |
2144 | if (sscanf(buf, "%d", &csr) != 1) | |
2145 | return -EFAULT; | |
2146 | ||
2147 | iwl_dump_csr(trans); | |
2148 | ||
2149 | return count; | |
2150 | } | |
2151 | ||
16db88ba EG |
2152 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
2153 | char __user *user_buf, | |
2154 | size_t count, loff_t *ppos) | |
2155 | { | |
2156 | struct iwl_trans *trans = file->private_data; | |
2157 | char *buf; | |
2158 | int pos = 0; | |
2159 | ssize_t ret = -EFAULT; | |
2160 | ||
2161 | ret = pos = iwl_dump_fh(trans, &buf, true); | |
2162 | if (buf) { | |
2163 | ret = simple_read_from_buffer(user_buf, | |
2164 | count, ppos, buf, pos); | |
2165 | kfree(buf); | |
2166 | } | |
2167 | ||
2168 | return ret; | |
2169 | } | |
2170 | ||
7ff94706 | 2171 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
1f7b6172 | 2172 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2173 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2174 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2175 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2176 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
2177 | |
2178 | /* | |
2179 | * Create the debugfs files and directories | |
2180 | * | |
2181 | */ | |
2182 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
2183 | struct dentry *dir) | |
2184 | { | |
87e5666c EG |
2185 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
2186 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
7ff94706 | 2187 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
1f7b6172 | 2188 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
2189 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
2190 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c EG |
2191 | return 0; |
2192 | } | |
2193 | #else | |
2194 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
2195 | struct dentry *dir) | |
2196 | { return 0; } | |
2197 | ||
2198 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
2199 | ||
e6bb4c9c | 2200 | const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2201 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 2202 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 2203 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2204 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2205 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2206 | |
2dd4f9f7 JB |
2207 | .wowlan_suspend = iwl_trans_pcie_wowlan_suspend, |
2208 | ||
e13c0c59 | 2209 | .wake_any_queue = iwl_trans_pcie_wake_any_queue, |
48d42c42 | 2210 | |
e6bb4c9c | 2211 | .send_cmd = iwl_trans_pcie_send_cmd, |
c85eb619 | 2212 | |
e6bb4c9c | 2213 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2214 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2215 | |
7f01d567 | 2216 | .tx_agg_disable = iwl_trans_pcie_tx_agg_disable, |
288712a6 | 2217 | .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc, |
c91bd124 | 2218 | .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, |
34c1b7ba | 2219 | |
e6bb4c9c | 2220 | .free = iwl_trans_pcie_free, |
e20d4341 | 2221 | .stop_queue = iwl_trans_pcie_stop_queue, |
87e5666c EG |
2222 | |
2223 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, | |
5f178cd2 EG |
2224 | |
2225 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, | |
f22be624 | 2226 | .check_stuck_queue = iwl_trans_pcie_check_stuck_queue, |
5f178cd2 | 2227 | |
c01a4047 | 2228 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
2229 | .suspend = iwl_trans_pcie_suspend, |
2230 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 2231 | #endif |
03905495 EG |
2232 | .write8 = iwl_trans_pcie_write8, |
2233 | .write32 = iwl_trans_pcie_write32, | |
2234 | .read32 = iwl_trans_pcie_read32, | |
e6bb4c9c | 2235 | }; |
a42a1844 | 2236 | |
a42a1844 EG |
2237 | struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, |
2238 | struct pci_dev *pdev, | |
2239 | const struct pci_device_id *ent) | |
2240 | { | |
a42a1844 EG |
2241 | struct iwl_trans_pcie *trans_pcie; |
2242 | struct iwl_trans *trans; | |
2243 | u16 pci_cmd; | |
2244 | int err; | |
2245 | ||
2246 | trans = kzalloc(sizeof(struct iwl_trans) + | |
2247 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); | |
2248 | ||
2249 | if (WARN_ON(!trans)) | |
2250 | return NULL; | |
2251 | ||
2252 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2253 | ||
2254 | trans->ops = &trans_ops_pcie; | |
2255 | trans->shrd = shrd; | |
2256 | trans_pcie->trans = trans; | |
7b11488f | 2257 | spin_lock_init(&trans_pcie->irq_lock); |
a42a1844 EG |
2258 | |
2259 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
2260 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
2261 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
2262 | PCIE_LINK_STATE_CLKPM); | |
2263 | ||
2264 | if (pci_enable_device(pdev)) { | |
2265 | err = -ENODEV; | |
2266 | goto out_no_pci; | |
2267 | } | |
2268 | ||
2269 | pci_set_master(pdev); | |
2270 | ||
2271 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2272 | if (!err) | |
2273 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2274 | if (err) { | |
2275 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2276 | if (!err) | |
2277 | err = pci_set_consistent_dma_mask(pdev, | |
2278 | DMA_BIT_MASK(32)); | |
2279 | /* both attempts failed: */ | |
2280 | if (err) { | |
2281 | dev_printk(KERN_ERR, &pdev->dev, | |
2282 | "No suitable DMA available.\n"); | |
2283 | goto out_pci_disable_device; | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | err = pci_request_regions(pdev, DRV_NAME); | |
2288 | if (err) { | |
2289 | dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed"); | |
2290 | goto out_pci_disable_device; | |
2291 | } | |
2292 | ||
2293 | trans_pcie->hw_base = pci_iomap(pdev, 0, 0); | |
2294 | if (!trans_pcie->hw_base) { | |
2295 | dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed"); | |
2296 | err = -ENODEV; | |
2297 | goto out_pci_release_regions; | |
2298 | } | |
2299 | ||
a42a1844 EG |
2300 | dev_printk(KERN_INFO, &pdev->dev, |
2301 | "pci_resource_len = 0x%08llx\n", | |
2302 | (unsigned long long) pci_resource_len(pdev, 0)); | |
2303 | dev_printk(KERN_INFO, &pdev->dev, | |
2304 | "pci_resource_base = %p\n", trans_pcie->hw_base); | |
2305 | ||
2306 | dev_printk(KERN_INFO, &pdev->dev, | |
2307 | "HW Revision ID = 0x%X\n", pdev->revision); | |
2308 | ||
2309 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
2310 | * PCI Tx retries from interfering with C3 CPU state */ | |
2311 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2312 | ||
2313 | err = pci_enable_msi(pdev); | |
2314 | if (err) | |
2315 | dev_printk(KERN_ERR, &pdev->dev, | |
2316 | "pci_enable_msi failed(0X%x)", err); | |
2317 | ||
2318 | trans->dev = &pdev->dev; | |
2319 | trans->irq = pdev->irq; | |
2320 | trans_pcie->pci_dev = pdev; | |
08079a49 | 2321 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 2322 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2323 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2324 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 EG |
2325 | |
2326 | /* TODO: Move this away, not needed if not MSI */ | |
2327 | /* enable rfkill interrupt: hw bug w/a */ | |
2328 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2329 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2330 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2331 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2332 | } | |
2333 | ||
2334 | return trans; | |
2335 | ||
2336 | out_pci_release_regions: | |
2337 | pci_release_regions(pdev); | |
2338 | out_pci_disable_device: | |
2339 | pci_disable_device(pdev); | |
2340 | out_no_pci: | |
2341 | kfree(trans); | |
2342 | return NULL; | |
2343 | } | |
2344 |