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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
4e318262 | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
ed277c93 | 38 | #include "iwl-op-mode.h" |
c17d0681 | 39 | #include "iwl-trans-pcie-int.h" |
1053d35f | 40 | |
522376d2 EG |
41 | #define IWL_TX_CRC_SIZE 4 |
42 | #define IWL_TX_DELIMITER_SIZE 4 | |
43 | ||
70a18c5d JB |
44 | /* |
45 | * mac80211 queues, ACs, hardware queues, FIFOs. | |
46 | * | |
47 | * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues | |
48 | * | |
49 | * Mac80211 uses the following numbers, which we get as from it | |
50 | * by way of skb_get_queue_mapping(skb): | |
51 | * | |
52 | * VO 0 | |
53 | * VI 1 | |
54 | * BE 2 | |
55 | * BK 3 | |
56 | * | |
57 | * | |
58 | * Regular (not A-MPDU) frames are put into hardware queues corresponding | |
59 | * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their | |
60 | * own queue per aggregation session (RA/TID combination), such queues are | |
61 | * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In | |
62 | * order to map frames to the right queue, we also need an AC->hw queue | |
63 | * mapping. This is implemented here. | |
64 | * | |
65 | * Due to the way hw queues are set up (by the hw specific code), the AC->hw | |
66 | * queue mapping is the identity mapping. | |
67 | */ | |
68 | ||
69 | static const u8 tid_to_ac[] = { | |
70 | IEEE80211_AC_BE, | |
71 | IEEE80211_AC_BK, | |
72 | IEEE80211_AC_BK, | |
73 | IEEE80211_AC_BE, | |
74 | IEEE80211_AC_VI, | |
75 | IEEE80211_AC_VI, | |
76 | IEEE80211_AC_VO, | |
77 | IEEE80211_AC_VO | |
78 | }; | |
79 | ||
80 | ||
48d42c42 EG |
81 | /** |
82 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
83 | */ | |
6d8f6eeb | 84 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
85 | struct iwl_tx_queue *txq, |
86 | u16 byte_cnt) | |
87 | { | |
105183b1 | 88 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
89 | struct iwl_trans_pcie *trans_pcie = |
90 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
91 | int write_ptr = txq->q.write_ptr; |
92 | int txq_id = txq->q.id; | |
93 | u8 sec_ctl = 0; | |
94 | u8 sta_id = 0; | |
95 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
96 | __le16 bc_ent; | |
132f98c2 EG |
97 | struct iwl_tx_cmd *tx_cmd = |
98 | (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload; | |
48d42c42 | 99 | |
105183b1 EG |
100 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
101 | ||
48d42c42 EG |
102 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
103 | ||
132f98c2 EG |
104 | sta_id = tx_cmd->sta_id; |
105 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
106 | |
107 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
108 | case TX_CMD_SEC_CCM: | |
109 | len += CCMP_MIC_LEN; | |
110 | break; | |
111 | case TX_CMD_SEC_TKIP: | |
112 | len += TKIP_ICV_LEN; | |
113 | break; | |
114 | case TX_CMD_SEC_WEP: | |
115 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
116 | break; | |
117 | } | |
118 | ||
119 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
120 | ||
121 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
122 | ||
123 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
124 | scd_bc_tbl[txq_id]. | |
125 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
126 | } | |
127 | ||
fd4abac5 TW |
128 | /** |
129 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
130 | */ | |
fd656935 | 131 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
132 | { |
133 | u32 reg = 0; | |
fd4abac5 TW |
134 | int txq_id = txq->q.id; |
135 | ||
136 | if (txq->need_update == 0) | |
7bfedc59 | 137 | return; |
fd4abac5 | 138 | |
0dde86b2 | 139 | if (cfg(trans)->base_params->shadow_reg_enable) { |
f81c1f48 | 140 | /* shadow register enabled */ |
1042db2a | 141 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
142 | txq->q.write_ptr | (txq_id << 8)); |
143 | } else { | |
144 | /* if we're trying to save power */ | |
fd656935 | 145 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
f81c1f48 WYG |
146 | /* wake up nic if it's powered down ... |
147 | * uCode will wake up, and interrupt us again, so next | |
148 | * time we'll skip this part. */ | |
1042db2a | 149 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 150 | |
f81c1f48 | 151 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 152 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
153 | "Tx queue %d requesting wakeup," |
154 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 155 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
156 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
157 | return; | |
158 | } | |
fd4abac5 | 159 | |
1042db2a | 160 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 161 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 162 | |
f81c1f48 WYG |
163 | /* |
164 | * else not in power-save mode, | |
165 | * uCode will never sleep when we're | |
166 | * trying to tx (during RFKILL, we're not trying to tx). | |
167 | */ | |
168 | } else | |
1042db2a | 169 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
170 | txq->q.write_ptr | (txq_id << 8)); |
171 | } | |
fd4abac5 | 172 | txq->need_update = 0; |
fd4abac5 | 173 | } |
fd4abac5 | 174 | |
214d14d4 JB |
175 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
176 | { | |
177 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
178 | ||
179 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
180 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
181 | addr |= | |
182 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
183 | ||
184 | return addr; | |
185 | } | |
186 | ||
187 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
188 | { | |
189 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
190 | ||
191 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
192 | } | |
193 | ||
194 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
195 | dma_addr_t addr, u16 len) | |
196 | { | |
197 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
198 | u16 hi_n_len = len << 4; | |
199 | ||
200 | put_unaligned_le32(addr, &tb->lo); | |
201 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
202 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
203 | ||
204 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
205 | ||
206 | tfd->num_tbs = idx + 1; | |
207 | } | |
208 | ||
209 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
210 | { | |
211 | return tfd->num_tbs & 0x1f; | |
212 | } | |
213 | ||
6d8f6eeb | 214 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 215 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 216 | { |
214d14d4 JB |
217 | int i; |
218 | int num_tbs; | |
219 | ||
214d14d4 JB |
220 | /* Sanity check on number of chunks */ |
221 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
222 | ||
223 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 224 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
225 | /* @todo issue fatal error, it is quite serious situation */ |
226 | return; | |
227 | } | |
228 | ||
229 | /* Unmap tx_cmd */ | |
230 | if (num_tbs) | |
1042db2a | 231 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
232 | dma_unmap_addr(meta, mapping), |
233 | dma_unmap_len(meta, len), | |
795414db | 234 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
235 | |
236 | /* Unmap chunks, if any. */ | |
237 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 238 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 239 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
240 | } |
241 | ||
242 | /** | |
243 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 244 | * @trans - transport private data |
4ce7cc2b | 245 | * @txq - tx queue |
1359ca4f | 246 | * @index - the index of the TFD to be freed |
39644e9a | 247 | *@dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
248 | * |
249 | * Does NOT advance any TFD circular buffer read/write indexes | |
250 | * Does NOT free the TFD itself (which is within circular buffer) | |
251 | */ | |
6d8f6eeb | 252 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
39644e9a | 253 | int index, enum dma_data_direction dma_dir) |
4ce7cc2b JB |
254 | { |
255 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 256 | |
015c15e1 JB |
257 | lockdep_assert_held(&txq->lock); |
258 | ||
39644e9a | 259 | iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir); |
214d14d4 JB |
260 | |
261 | /* free SKB */ | |
2c452297 | 262 | if (txq->skbs) { |
214d14d4 JB |
263 | struct sk_buff *skb; |
264 | ||
2c452297 | 265 | skb = txq->skbs[index]; |
214d14d4 | 266 | |
909e9b23 EG |
267 | /* Can be called from irqs-disabled context |
268 | * If skb is not NULL, it means that the whole queue is being | |
269 | * freed and that the queue is not empty - free the skb | |
270 | */ | |
214d14d4 | 271 | if (skb) { |
ed277c93 | 272 | iwl_op_mode_free_skb(trans->op_mode, skb); |
2c452297 | 273 | txq->skbs[index] = NULL; |
214d14d4 JB |
274 | } |
275 | } | |
276 | } | |
277 | ||
6d8f6eeb | 278 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
279 | struct iwl_tx_queue *txq, |
280 | dma_addr_t addr, u16 len, | |
4c42db0f | 281 | u8 reset) |
214d14d4 JB |
282 | { |
283 | struct iwl_queue *q; | |
284 | struct iwl_tfd *tfd, *tfd_tmp; | |
285 | u32 num_tbs; | |
286 | ||
287 | q = &txq->q; | |
4ce7cc2b | 288 | tfd_tmp = txq->tfds; |
214d14d4 JB |
289 | tfd = &tfd_tmp[q->write_ptr]; |
290 | ||
291 | if (reset) | |
292 | memset(tfd, 0, sizeof(*tfd)); | |
293 | ||
294 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
295 | ||
296 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
297 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 298 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
299 | IWL_NUM_OF_TBS); |
300 | return -EINVAL; | |
301 | } | |
302 | ||
303 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
304 | return -EINVAL; | |
305 | ||
306 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 307 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
308 | (unsigned long long)addr); |
309 | ||
310 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
fd4abac5 TW |
315 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
316 | * DMA services | |
317 | * | |
318 | * Theory of operation | |
319 | * | |
320 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
321 | * of buffer descriptors, each of which points to one or more data buffers for | |
322 | * the device to read from or fill. Driver and device exchange status of each | |
323 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
324 | * entries in each circular buffer, to protect against confusing empty and full | |
325 | * queue states. | |
326 | * | |
327 | * The device reads or writes the data in the queues via the device's several | |
328 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
329 | * | |
330 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
331 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
332 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
333 | * Tx queue resumed. | |
334 | * | |
fd4abac5 TW |
335 | ***************************************************/ |
336 | ||
337 | int iwl_queue_space(const struct iwl_queue *q) | |
338 | { | |
339 | int s = q->read_ptr - q->write_ptr; | |
340 | ||
341 | if (q->read_ptr > q->write_ptr) | |
342 | s -= q->n_bd; | |
343 | ||
344 | if (s <= 0) | |
345 | s += q->n_window; | |
346 | /* keep some reserve to not confuse empty and full situations */ | |
347 | s -= 2; | |
348 | if (s < 0) | |
349 | s = 0; | |
350 | return s; | |
351 | } | |
fd4abac5 | 352 | |
1053d35f RR |
353 | /** |
354 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
355 | */ | |
6d8f6eeb | 356 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
357 | { |
358 | q->n_bd = count; | |
359 | q->n_window = slots_num; | |
360 | q->id = id; | |
361 | ||
362 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
363 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
364 | if (WARN_ON(!is_power_of_2(count))) |
365 | return -EINVAL; | |
1053d35f RR |
366 | |
367 | /* slots_num must be power-of-two size, otherwise | |
368 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
369 | if (WARN_ON(!is_power_of_2(slots_num))) |
370 | return -EINVAL; | |
1053d35f RR |
371 | |
372 | q->low_mark = q->n_window / 4; | |
373 | if (q->low_mark < 4) | |
374 | q->low_mark = 4; | |
375 | ||
376 | q->high_mark = q->n_window / 8; | |
377 | if (q->high_mark < 2) | |
378 | q->high_mark = 2; | |
379 | ||
380 | q->write_ptr = q->read_ptr = 0; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
6d8f6eeb | 385 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
386 | struct iwl_tx_queue *txq) |
387 | { | |
105183b1 EG |
388 | struct iwl_trans_pcie *trans_pcie = |
389 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 390 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
391 | int txq_id = txq->q.id; |
392 | int read_ptr = txq->q.read_ptr; | |
393 | u8 sta_id = 0; | |
394 | __le16 bc_ent; | |
132f98c2 EG |
395 | struct iwl_tx_cmd *tx_cmd = |
396 | (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload; | |
48d42c42 EG |
397 | |
398 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
399 | ||
c6f600fc | 400 | if (txq_id != trans_pcie->cmd_queue) |
132f98c2 | 401 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
402 | |
403 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
404 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
405 | ||
406 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
407 | scd_bc_tbl[txq_id]. | |
408 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
409 | } | |
410 | ||
6d8f6eeb | 411 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
412 | u16 txq_id) |
413 | { | |
414 | u32 tbl_dw_addr; | |
415 | u32 tbl_dw; | |
416 | u16 scd_q2ratid; | |
417 | ||
105183b1 EG |
418 | struct iwl_trans_pcie *trans_pcie = |
419 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
420 | ||
48d42c42 EG |
421 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
422 | ||
105183b1 | 423 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
424 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
425 | ||
1042db2a | 426 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
427 | |
428 | if (txq_id & 0x1) | |
429 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
430 | else | |
431 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
432 | ||
1042db2a | 433 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
434 | |
435 | return 0; | |
436 | } | |
437 | ||
6d8f6eeb | 438 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
439 | { |
440 | /* Simply stop the queue, but don't change any configuration; | |
441 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 442 | iwl_write_prph(trans, |
48d42c42 EG |
443 | SCD_QUEUE_STATUS_BITS(txq_id), |
444 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
445 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
446 | } | |
447 | ||
6d8f6eeb | 448 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
449 | int txq_id, u32 index) |
450 | { | |
631b84c5 | 451 | IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff); |
1042db2a | 452 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
48d42c42 | 453 | (index & 0xff) | (txq_id << 8)); |
1042db2a | 454 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
455 | } |
456 | ||
c91bd124 | 457 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
48d42c42 EG |
458 | struct iwl_tx_queue *txq, |
459 | int tx_fifo_id, int scd_retry) | |
460 | { | |
8ad71bef | 461 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 462 | int txq_id = txq->q.id; |
c91bd124 | 463 | int active = |
8ad71bef | 464 | test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0; |
48d42c42 | 465 | |
1042db2a | 466 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
467 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
468 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
469 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
470 | SCD_QUEUE_STTS_REG_MSK); | |
471 | ||
472 | txq->sched_retry = scd_retry; | |
473 | ||
1dcedc8e EG |
474 | if (active) |
475 | IWL_DEBUG_TX_QUEUES(trans, "Activate %s Queue %d on FIFO %d\n", | |
476 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
477 | else | |
478 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate %s Queue %d\n", | |
479 | scd_retry ? "BA" : "AC/CMD", txq_id); | |
48d42c42 EG |
480 | } |
481 | ||
70a18c5d JB |
482 | static inline int get_ac_from_tid(u16 tid) |
483 | { | |
484 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) | |
485 | return tid_to_ac[tid]; | |
486 | ||
487 | /* no support for TIDs 8-15 yet */ | |
488 | return -EINVAL; | |
489 | } | |
490 | ||
e13c0c59 EG |
491 | static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie, |
492 | u8 ctx, u16 tid) | |
ba562f71 | 493 | { |
e13c0c59 | 494 | const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx]; |
ba562f71 | 495 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) |
e13c0c59 | 496 | return ac_to_fifo[tid_to_ac[tid]]; |
ba562f71 EG |
497 | |
498 | /* no support for TIDs 8-15 yet */ | |
499 | return -EINVAL; | |
500 | } | |
501 | ||
76bc10fc EG |
502 | static inline bool is_agg_txqid_valid(struct iwl_trans *trans, int txq_id) |
503 | { | |
504 | if (txq_id < IWLAGN_FIRST_AMPDU_QUEUE) | |
505 | return false; | |
506 | return txq_id < (IWLAGN_FIRST_AMPDU_QUEUE + | |
507 | hw_params(trans).num_ampdu_queues); | |
508 | } | |
509 | ||
c91bd124 EG |
510 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, |
511 | enum iwl_rxon_context_id ctx, int sta_id, | |
822e8b2a | 512 | int tid, int frame_limit, u16 ssn) |
48d42c42 | 513 | { |
822e8b2a | 514 | int tx_fifo, txq_id; |
48d42c42 EG |
515 | u16 ra_tid; |
516 | unsigned long flags; | |
48d42c42 | 517 | |
105183b1 EG |
518 | struct iwl_trans_pcie *trans_pcie = |
519 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
520 | ||
48d42c42 EG |
521 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) |
522 | return; | |
5f85a789 | 523 | if (WARN_ON(tid >= IWL_MAX_TID_COUNT)) |
48d42c42 EG |
524 | return; |
525 | ||
e13c0c59 | 526 | tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid); |
ba562f71 EG |
527 | if (WARN_ON(tx_fifo < 0)) { |
528 | IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo); | |
529 | return; | |
530 | } | |
531 | ||
76bc10fc EG |
532 | txq_id = trans_pcie->agg_txq[sta_id][tid]; |
533 | if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) { | |
534 | IWL_ERR(trans, | |
535 | "queue number out of range: %d, must be %d to %d\n", | |
536 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
537 | IWLAGN_FIRST_AMPDU_QUEUE + | |
538 | hw_params(trans).num_ampdu_queues - 1); | |
539 | return; | |
540 | } | |
48d42c42 EG |
541 | |
542 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
543 | ||
7b11488f | 544 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
545 | |
546 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 547 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
548 | |
549 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 550 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
551 | |
552 | /* Set this queue as a chain-building queue */ | |
1042db2a | 553 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, (1<<txq_id)); |
48d42c42 EG |
554 | |
555 | /* enable aggregations for the queue */ | |
1042db2a | 556 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, (1<<txq_id)); |
48d42c42 EG |
557 | |
558 | /* Place first TFD at index corresponding to start sequence number. | |
559 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
560 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
561 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
562 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
563 | |
564 | /* Set up Tx window size and frame limit for this queue */ | |
1042db2a | 565 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
48d42c42 EG |
566 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
567 | sizeof(u32), | |
568 | ((frame_limit << | |
569 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
570 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
571 | ((frame_limit << | |
572 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
573 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
574 | ||
1042db2a | 575 | iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
576 | |
577 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 578 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
c91bd124 | 579 | tx_fifo, 1); |
48d42c42 | 580 | |
8ad71bef EG |
581 | trans_pcie->txq[txq_id].sta_id = sta_id; |
582 | trans_pcie->txq[txq_id].tid = tid; | |
a0eaad71 | 583 | |
7b11488f | 584 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
585 | } |
586 | ||
288712a6 EG |
587 | /* |
588 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
589 | * Called only when finding queue for aggregation. | |
590 | * Should never return anything < 7, because they should already | |
591 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
592 | */ | |
593 | static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans) | |
594 | { | |
8ad71bef | 595 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 EG |
596 | int txq_id; |
597 | ||
1745e440 WYG |
598 | for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; |
599 | txq_id++) | |
288712a6 | 600 | if (!test_and_set_bit(txq_id, |
8ad71bef | 601 | &trans_pcie->txq_ctx_active_msk)) |
288712a6 EG |
602 | return txq_id; |
603 | return -1; | |
604 | } | |
605 | ||
606 | int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, | |
3c69b595 | 607 | int sta_id, int tid) |
288712a6 | 608 | { |
8ad71bef | 609 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
143bb15d | 610 | int txq_id; |
288712a6 EG |
611 | |
612 | txq_id = iwlagn_txq_ctx_activate_free(trans); | |
613 | if (txq_id == -1) { | |
614 | IWL_ERR(trans, "No free aggregation queue available\n"); | |
615 | return -ENXIO; | |
616 | } | |
617 | ||
76bc10fc | 618 | trans_pcie->agg_txq[sta_id][tid] = txq_id; |
8ad71bef | 619 | iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id); |
288712a6 | 620 | |
288712a6 EG |
621 | return 0; |
622 | } | |
7f01d567 | 623 | |
bc237730 | 624 | int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid) |
48d42c42 | 625 | { |
8ad71bef | 626 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
76bc10fc | 627 | u8 txq_id = trans_pcie->agg_txq[sta_id][tid]; |
7f01d567 | 628 | |
76bc10fc | 629 | if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) { |
7f01d567 | 630 | IWL_ERR(trans, |
48d42c42 EG |
631 | "queue number out of range: %d, must be %d to %d\n", |
632 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
633 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7f01d567 | 634 | hw_params(trans).num_ampdu_queues - 1); |
48d42c42 EG |
635 | return -EINVAL; |
636 | } | |
637 | ||
bc237730 | 638 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 639 | |
1042db2a | 640 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, (1 << txq_id)); |
48d42c42 | 641 | |
76bc10fc | 642 | trans_pcie->agg_txq[sta_id][tid] = 0; |
bc237730 EG |
643 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
644 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
645 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
646 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); | |
48d42c42 | 647 | |
1042db2a | 648 | iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
bc237730 EG |
649 | iwl_txq_ctx_deactivate(trans_pcie, txq_id); |
650 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0); | |
48d42c42 EG |
651 | return 0; |
652 | } | |
653 | ||
fd4abac5 TW |
654 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
655 | ||
656 | /** | |
657 | * iwl_enqueue_hcmd - enqueue a uCode command | |
658 | * @priv: device private data point | |
659 | * @cmd: a point to the ucode command structure | |
660 | * | |
661 | * The function returns < 0 values to indicate the operation is | |
662 | * failed. On success, it turns the index (> 0) of command in the | |
663 | * command queue. | |
664 | */ | |
6d8f6eeb | 665 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 666 | { |
8ad71bef | 667 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 668 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 669 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
670 | struct iwl_device_cmd *out_cmd; |
671 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 672 | dma_addr_t phys_addr; |
f3674227 | 673 | u32 idx; |
4ce7cc2b | 674 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
675 | bool had_nocopy = false; |
676 | int i; | |
677 | u8 *cmd_dest; | |
678 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
679 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
680 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
681 | int trace_idx; | |
682 | #endif | |
fd4abac5 | 683 | |
6d8f6eeb EG |
684 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { |
685 | IWL_WARN(trans, "fw recovery, no hcmd send\n"); | |
3083d03c WYG |
686 | return -EIO; |
687 | } | |
688 | ||
4ce7cc2b JB |
689 | copy_size = sizeof(out_cmd->hdr); |
690 | cmd_size = sizeof(out_cmd->hdr); | |
691 | ||
692 | /* need one for the header if the first is NOCOPY */ | |
693 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
694 | ||
695 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
696 | if (!cmd->len[i]) | |
697 | continue; | |
698 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
699 | had_nocopy = true; | |
700 | } else { | |
701 | /* NOCOPY must not be followed by normal! */ | |
702 | if (WARN_ON(had_nocopy)) | |
703 | return -EINVAL; | |
704 | copy_size += cmd->len[i]; | |
705 | } | |
706 | cmd_size += cmd->len[i]; | |
707 | } | |
fd4abac5 | 708 | |
3e41ace5 JB |
709 | /* |
710 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
711 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
712 | * allocated into separate TFDs, then we will need to | |
713 | * increase the size of the buffers. | |
3e41ace5 | 714 | */ |
4ce7cc2b | 715 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 716 | return -EINVAL; |
fd4abac5 | 717 | |
015c15e1 | 718 | spin_lock_bh(&txq->lock); |
3598e177 | 719 | |
c2acea8e | 720 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 721 | spin_unlock_bh(&txq->lock); |
3598e177 | 722 | |
6d8f6eeb | 723 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 724 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
fd4abac5 TW |
725 | return -ENOSPC; |
726 | } | |
727 | ||
4ce7cc2b | 728 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 729 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
730 | out_meta = &txq->meta[idx]; |
731 | ||
8ce73f3a | 732 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
733 | if (cmd->flags & CMD_WANT_SKB) |
734 | out_meta->source = cmd; | |
fd4abac5 | 735 | |
4ce7cc2b | 736 | /* set up the header */ |
fd4abac5 | 737 | |
4ce7cc2b | 738 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 739 | out_cmd->hdr.flags = 0; |
cefeaa5f | 740 | out_cmd->hdr.sequence = |
c6f600fc | 741 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 742 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
743 | |
744 | /* and copy the data that needs to be copied */ | |
745 | ||
132f98c2 | 746 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
747 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
748 | if (!cmd->len[i]) | |
749 | continue; | |
750 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
751 | break; | |
752 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
753 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 754 | } |
4ce7cc2b | 755 | |
6d8f6eeb | 756 | IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, " |
4ce7cc2b JB |
757 | "%d bytes at %d[%d]:%d\n", |
758 | get_cmd_string(out_cmd->hdr.cmd), | |
759 | out_cmd->hdr.cmd, | |
760 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
c6f600fc | 761 | q->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 762 | |
1042db2a | 763 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
795414db | 764 | DMA_BIDIRECTIONAL); |
1042db2a | 765 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
766 | idx = -ENOMEM; |
767 | goto out; | |
768 | } | |
769 | ||
2e724443 | 770 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
771 | dma_unmap_len_set(out_meta, len, copy_size); |
772 | ||
6d8f6eeb EG |
773 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
774 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
775 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
776 | trace_bufs[0] = &out_cmd->hdr; | |
777 | trace_lens[0] = copy_size; | |
778 | trace_idx = 1; | |
779 | #endif | |
780 | ||
781 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
782 | if (!cmd->len[i]) | |
783 | continue; | |
784 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
785 | continue; | |
1042db2a | 786 | phys_addr = dma_map_single(trans->dev, |
6d8f6eeb | 787 | (void *)cmd->data[i], |
3be3fdb5 | 788 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 789 | if (dma_mapping_error(trans->dev, phys_addr)) { |
6d8f6eeb | 790 | iwlagn_unmap_tfd(trans, out_meta, |
e815407d | 791 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 792 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
793 | idx = -ENOMEM; |
794 | goto out; | |
795 | } | |
796 | ||
6d8f6eeb | 797 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
798 | cmd->len[i], 0); |
799 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
800 | trace_bufs[trace_idx] = cmd->data[i]; | |
801 | trace_lens[trace_idx] = cmd->len[i]; | |
802 | trace_idx++; | |
803 | #endif | |
804 | } | |
df833b1d | 805 | |
afaf6b57 | 806 | out_meta->flags = cmd->flags; |
2c46f72e JB |
807 | |
808 | txq->need_update = 1; | |
809 | ||
4ce7cc2b JB |
810 | /* check that tracing gets all possible blocks */ |
811 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
812 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
6c1011e1 | 813 | trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags, |
4ce7cc2b JB |
814 | trace_bufs[0], trace_lens[0], |
815 | trace_bufs[1], trace_lens[1], | |
816 | trace_bufs[2], trace_lens[2]); | |
817 | #endif | |
df833b1d | 818 | |
fd4abac5 TW |
819 | /* Increment and update queue's write index */ |
820 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 821 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 822 | |
2c46f72e | 823 | out: |
015c15e1 | 824 | spin_unlock_bh(&txq->lock); |
7bfedc59 | 825 | return idx; |
fd4abac5 TW |
826 | } |
827 | ||
17b88929 TW |
828 | /** |
829 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
830 | * | |
831 | * When FW advances 'R' index, all entries between old and new 'R' index | |
832 | * need to be reclaimed. As result, some free space forms. If there is | |
833 | * enough free space (> low mark), wake the stack that feeds us. | |
834 | */ | |
3e10caeb EG |
835 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
836 | int idx) | |
17b88929 | 837 | { |
3e10caeb | 838 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 839 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
840 | struct iwl_queue *q = &txq->q; |
841 | int nfreed = 0; | |
842 | ||
015c15e1 JB |
843 | lockdep_assert_held(&txq->lock); |
844 | ||
499b1883 | 845 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 846 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
847 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
848 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
849 | return; |
850 | } | |
851 | ||
499b1883 TW |
852 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
853 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 854 | |
499b1883 | 855 | if (nfreed++ > 0) { |
3e10caeb | 856 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 857 | q->write_ptr, q->read_ptr); |
bcb9321c | 858 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 859 | } |
da99c4b6 | 860 | |
17b88929 TW |
861 | } |
862 | } | |
863 | ||
864 | /** | |
865 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
866 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
867 | * @handler_status: return value of the handler of the command |
868 | * (put in setup_rx_handlers) | |
17b88929 TW |
869 | * |
870 | * If an Rx buffer has an async callback associated with it the callback | |
871 | * will be executed. The attached skb (if present) will only be freed | |
872 | * if the callback returns 1 | |
873 | */ | |
48a2d66f | 874 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 875 | int handler_status) |
17b88929 | 876 | { |
2f301227 | 877 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
878 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
879 | int txq_id = SEQ_TO_QUEUE(sequence); | |
880 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 881 | int cmd_index; |
c2acea8e JB |
882 | struct iwl_device_cmd *cmd; |
883 | struct iwl_cmd_meta *meta; | |
8ad71bef | 884 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 885 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
886 | |
887 | /* If a Tx command is being handled and it isn't in the actual | |
888 | * command queue then there a command routing bug has been introduced | |
889 | * in the queue management code. */ | |
c6f600fc | 890 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 891 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
c6f600fc MV |
892 | txq_id, trans_pcie->cmd_queue, sequence, |
893 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
894 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 895 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 896 | return; |
01ef9323 | 897 | } |
17b88929 | 898 | |
015c15e1 JB |
899 | spin_lock(&txq->lock); |
900 | ||
4ce7cc2b | 901 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
902 | cmd = txq->cmd[cmd_index]; |
903 | meta = &txq->meta[cmd_index]; | |
17b88929 | 904 | |
282cdb32 JB |
905 | txq->time_stamp = jiffies; |
906 | ||
6d8f6eeb EG |
907 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
908 | DMA_BIDIRECTIONAL); | |
c33de625 | 909 | |
17b88929 | 910 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 911 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 912 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 913 | |
65b94a4a JB |
914 | meta->source->resp_pkt = pkt; |
915 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
916 | meta->source->_rx_page_order = hw_params(trans).rx_page_order; | |
917 | meta->source->handler_status = handler_status; | |
247c61d6 | 918 | } |
2624e96c | 919 | |
3e10caeb | 920 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 921 | |
c2acea8e | 922 | if (!(meta->flags & CMD_ASYNC)) { |
05c89b91 WYG |
923 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
924 | IWL_WARN(trans, | |
925 | "HCMD_ACTIVE already clear for command %s\n", | |
926 | get_cmd_string(cmd->hdr.cmd)); | |
927 | } | |
6d8f6eeb EG |
928 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
929 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", | |
d2dfe6df | 930 | get_cmd_string(cmd->hdr.cmd)); |
effd4d9a | 931 | wake_up(&trans->shrd->wait_command_queue); |
17b88929 | 932 | } |
3598e177 | 933 | |
dd487449 | 934 | meta->flags = 0; |
3598e177 | 935 | |
015c15e1 | 936 | spin_unlock(&txq->lock); |
17b88929 | 937 | } |
253a634c | 938 | |
253a634c EG |
939 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
940 | ||
6d8f6eeb | 941 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
942 | { |
943 | int ret; | |
944 | ||
945 | /* An asynchronous command can not expect an SKB to be set. */ | |
946 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
947 | return -EINVAL; | |
948 | ||
253a634c | 949 | |
6d8f6eeb | 950 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 951 | if (ret < 0) { |
721c32f7 | 952 | IWL_ERR(trans, |
b36b110c | 953 | "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
954 | get_cmd_string(cmd->id), ret); |
955 | return ret; | |
956 | } | |
957 | return 0; | |
958 | } | |
959 | ||
6d8f6eeb | 960 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 961 | { |
8ad71bef | 962 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
963 | int cmd_idx; |
964 | int ret; | |
965 | ||
6d8f6eeb | 966 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
253a634c EG |
967 | get_cmd_string(cmd->id)); |
968 | ||
94b3c45c WYG |
969 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { |
970 | IWL_ERR(trans, "Command %s failed: FW Error\n", | |
971 | get_cmd_string(cmd->id)); | |
972 | return -EIO; | |
973 | } | |
2cc39c94 JB |
974 | |
975 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, | |
976 | &trans->shrd->status))) { | |
977 | IWL_ERR(trans, "Command %s: a command is already active!\n", | |
978 | get_cmd_string(cmd->id)); | |
979 | return -EIO; | |
980 | } | |
981 | ||
6d8f6eeb | 982 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
253a634c EG |
983 | get_cmd_string(cmd->id)); |
984 | ||
6d8f6eeb | 985 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
986 | if (cmd_idx < 0) { |
987 | ret = cmd_idx; | |
6d8f6eeb | 988 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
721c32f7 | 989 | IWL_ERR(trans, |
b36b110c | 990 | "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
991 | get_cmd_string(cmd->id), ret); |
992 | return ret; | |
993 | } | |
994 | ||
effd4d9a | 995 | ret = wait_event_timeout(trans->shrd->wait_command_queue, |
6d8f6eeb | 996 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), |
253a634c EG |
997 | HOST_COMPLETE_TIMEOUT); |
998 | if (!ret) { | |
6d8f6eeb | 999 | if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
d10630af | 1000 | struct iwl_tx_queue *txq = |
c6f600fc | 1001 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
1002 | struct iwl_queue *q = &txq->q; |
1003 | ||
721c32f7 | 1004 | IWL_ERR(trans, |
253a634c EG |
1005 | "Error sending %s: time out after %dms.\n", |
1006 | get_cmd_string(cmd->id), | |
1007 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
1008 | ||
721c32f7 | 1009 | IWL_ERR(trans, |
d10630af WYG |
1010 | "Current CMD queue read_ptr %d write_ptr %d\n", |
1011 | q->read_ptr, q->write_ptr); | |
1012 | ||
6d8f6eeb EG |
1013 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
1014 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command" | |
253a634c EG |
1015 | "%s\n", get_cmd_string(cmd->id)); |
1016 | ret = -ETIMEDOUT; | |
1017 | goto cancel; | |
1018 | } | |
1019 | } | |
1020 | ||
65b94a4a | 1021 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1022 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
253a634c EG |
1023 | get_cmd_string(cmd->id)); |
1024 | ret = -EIO; | |
1025 | goto cancel; | |
1026 | } | |
1027 | ||
1028 | return 0; | |
1029 | ||
1030 | cancel: | |
1031 | if (cmd->flags & CMD_WANT_SKB) { | |
1032 | /* | |
1033 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1034 | * TX cmd queue. Otherwise in case the cmd comes | |
1035 | * in later, it will possibly set an invalid | |
1036 | * address (cmd->meta.source). | |
1037 | */ | |
c6f600fc | 1038 | trans_pcie->txq[trans_pcie->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
1039 | ~CMD_WANT_SKB; |
1040 | } | |
9cac4943 | 1041 | |
65b94a4a JB |
1042 | if (cmd->resp_pkt) { |
1043 | iwl_free_resp(cmd); | |
1044 | cmd->resp_pkt = NULL; | |
253a634c EG |
1045 | } |
1046 | ||
1047 | return ret; | |
1048 | } | |
1049 | ||
6d8f6eeb | 1050 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
1051 | { |
1052 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 1053 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 1054 | |
6d8f6eeb | 1055 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
1056 | } |
1057 | ||
a0eaad71 | 1058 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
1059 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
1060 | struct sk_buff_head *skbs) | |
a0eaad71 | 1061 | { |
8ad71bef EG |
1062 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1063 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 1064 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 1065 | int last_to_free; |
464021ff | 1066 | int freed = 0; |
a0eaad71 | 1067 | |
39644e9a | 1068 | /* This function is not meant to release cmd queue*/ |
c6f600fc | 1069 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) |
39644e9a EG |
1070 | return 0; |
1071 | ||
015c15e1 JB |
1072 | lockdep_assert_held(&txq->lock); |
1073 | ||
a0eaad71 EG |
1074 | /*Since we free until index _not_ inclusive, the one before index is |
1075 | * the last we will free. This one must be used */ | |
1076 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
1077 | ||
1078 | if ((index >= q->n_bd) || | |
1079 | (iwl_queue_used(q, last_to_free) == 0)) { | |
1080 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
1081 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
1082 | __func__, txq_id, last_to_free, q->n_bd, | |
1083 | q->write_ptr, q->read_ptr); | |
464021ff | 1084 | return 0; |
a0eaad71 EG |
1085 | } |
1086 | ||
a0eaad71 | 1087 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 1088 | return 0; |
a0eaad71 EG |
1089 | |
1090 | for (; | |
1091 | q->read_ptr != index; | |
1092 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1093 | ||
2c452297 | 1094 | if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL)) |
a0eaad71 EG |
1095 | continue; |
1096 | ||
2c452297 | 1097 | __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]); |
a0eaad71 | 1098 | |
2c452297 | 1099 | txq->skbs[txq->q.read_ptr] = NULL; |
a0eaad71 | 1100 | |
6d8f6eeb | 1101 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 1102 | |
39644e9a | 1103 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE); |
464021ff | 1104 | freed++; |
a0eaad71 | 1105 | } |
464021ff | 1106 | return freed; |
a0eaad71 | 1107 | } |