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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
c17d0681 | 38 | #include "iwl-trans-pcie-int.h" |
1053d35f | 39 | |
522376d2 EG |
40 | #define IWL_TX_CRC_SIZE 4 |
41 | #define IWL_TX_DELIMITER_SIZE 4 | |
42 | ||
48d42c42 EG |
43 | /** |
44 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
45 | */ | |
6d8f6eeb | 46 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
47 | struct iwl_tx_queue *txq, |
48 | u16 byte_cnt) | |
49 | { | |
105183b1 | 50 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
51 | struct iwl_trans_pcie *trans_pcie = |
52 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
53 | int write_ptr = txq->q.write_ptr; |
54 | int txq_id = txq->q.id; | |
55 | u8 sec_ctl = 0; | |
56 | u8 sta_id = 0; | |
57 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
58 | __le16 bc_ent; | |
132f98c2 EG |
59 | struct iwl_tx_cmd *tx_cmd = |
60 | (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload; | |
48d42c42 | 61 | |
105183b1 EG |
62 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
63 | ||
48d42c42 EG |
64 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
65 | ||
132f98c2 EG |
66 | sta_id = tx_cmd->sta_id; |
67 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
68 | |
69 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
70 | case TX_CMD_SEC_CCM: | |
71 | len += CCMP_MIC_LEN; | |
72 | break; | |
73 | case TX_CMD_SEC_TKIP: | |
74 | len += TKIP_ICV_LEN; | |
75 | break; | |
76 | case TX_CMD_SEC_WEP: | |
77 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
78 | break; | |
79 | } | |
80 | ||
81 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
82 | ||
83 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
84 | ||
85 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
86 | scd_bc_tbl[txq_id]. | |
87 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
88 | } | |
89 | ||
fd4abac5 TW |
90 | /** |
91 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
92 | */ | |
fd656935 | 93 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
94 | { |
95 | u32 reg = 0; | |
fd4abac5 TW |
96 | int txq_id = txq->q.id; |
97 | ||
98 | if (txq->need_update == 0) | |
7bfedc59 | 99 | return; |
fd4abac5 | 100 | |
fd656935 | 101 | if (hw_params(trans).shadow_reg_enable) { |
f81c1f48 | 102 | /* shadow register enabled */ |
fd656935 | 103 | iwl_write32(bus(trans), HBUS_TARG_WRPTR, |
f81c1f48 WYG |
104 | txq->q.write_ptr | (txq_id << 8)); |
105 | } else { | |
106 | /* if we're trying to save power */ | |
fd656935 | 107 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
f81c1f48 WYG |
108 | /* wake up nic if it's powered down ... |
109 | * uCode will wake up, and interrupt us again, so next | |
110 | * time we'll skip this part. */ | |
fd656935 | 111 | reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1); |
fd4abac5 | 112 | |
f81c1f48 | 113 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 114 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
115 | "Tx queue %d requesting wakeup," |
116 | " GP1 = 0x%x\n", txq_id, reg); | |
fd656935 | 117 | iwl_set_bit(bus(trans), CSR_GP_CNTRL, |
f81c1f48 WYG |
118 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
119 | return; | |
120 | } | |
fd4abac5 | 121 | |
fd656935 | 122 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, |
fd4abac5 | 123 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 124 | |
f81c1f48 WYG |
125 | /* |
126 | * else not in power-save mode, | |
127 | * uCode will never sleep when we're | |
128 | * trying to tx (during RFKILL, we're not trying to tx). | |
129 | */ | |
130 | } else | |
fd656935 | 131 | iwl_write32(bus(trans), HBUS_TARG_WRPTR, |
f81c1f48 WYG |
132 | txq->q.write_ptr | (txq_id << 8)); |
133 | } | |
fd4abac5 | 134 | txq->need_update = 0; |
fd4abac5 | 135 | } |
fd4abac5 | 136 | |
214d14d4 JB |
137 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
138 | { | |
139 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
140 | ||
141 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
142 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
143 | addr |= | |
144 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
145 | ||
146 | return addr; | |
147 | } | |
148 | ||
149 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
150 | { | |
151 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
152 | ||
153 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
154 | } | |
155 | ||
156 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
157 | dma_addr_t addr, u16 len) | |
158 | { | |
159 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
160 | u16 hi_n_len = len << 4; | |
161 | ||
162 | put_unaligned_le32(addr, &tb->lo); | |
163 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
164 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
165 | ||
166 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
167 | ||
168 | tfd->num_tbs = idx + 1; | |
169 | } | |
170 | ||
171 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
172 | { | |
173 | return tfd->num_tbs & 0x1f; | |
174 | } | |
175 | ||
6d8f6eeb | 176 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 177 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 178 | { |
214d14d4 JB |
179 | int i; |
180 | int num_tbs; | |
181 | ||
214d14d4 JB |
182 | /* Sanity check on number of chunks */ |
183 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
184 | ||
185 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 186 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
187 | /* @todo issue fatal error, it is quite serious situation */ |
188 | return; | |
189 | } | |
190 | ||
191 | /* Unmap tx_cmd */ | |
192 | if (num_tbs) | |
6d8f6eeb | 193 | dma_unmap_single(bus(trans)->dev, |
4ce7cc2b JB |
194 | dma_unmap_addr(meta, mapping), |
195 | dma_unmap_len(meta, len), | |
795414db | 196 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
197 | |
198 | /* Unmap chunks, if any. */ | |
199 | for (i = 1; i < num_tbs; i++) | |
6d8f6eeb | 200 | dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 201 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
202 | } |
203 | ||
204 | /** | |
205 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 206 | * @trans - transport private data |
4ce7cc2b | 207 | * @txq - tx queue |
1359ca4f | 208 | * @index - the index of the TFD to be freed |
39644e9a | 209 | *@dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
210 | * |
211 | * Does NOT advance any TFD circular buffer read/write indexes | |
212 | * Does NOT free the TFD itself (which is within circular buffer) | |
213 | */ | |
6d8f6eeb | 214 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
39644e9a | 215 | int index, enum dma_data_direction dma_dir) |
4ce7cc2b JB |
216 | { |
217 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 218 | |
39644e9a | 219 | iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir); |
214d14d4 JB |
220 | |
221 | /* free SKB */ | |
2c452297 | 222 | if (txq->skbs) { |
214d14d4 JB |
223 | struct sk_buff *skb; |
224 | ||
2c452297 | 225 | skb = txq->skbs[index]; |
214d14d4 | 226 | |
909e9b23 EG |
227 | /* Can be called from irqs-disabled context |
228 | * If skb is not NULL, it means that the whole queue is being | |
229 | * freed and that the queue is not empty - free the skb | |
230 | */ | |
214d14d4 | 231 | if (skb) { |
909e9b23 | 232 | iwl_free_skb(priv(trans), skb); |
2c452297 | 233 | txq->skbs[index] = NULL; |
214d14d4 JB |
234 | } |
235 | } | |
236 | } | |
237 | ||
6d8f6eeb | 238 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
239 | struct iwl_tx_queue *txq, |
240 | dma_addr_t addr, u16 len, | |
4c42db0f | 241 | u8 reset) |
214d14d4 JB |
242 | { |
243 | struct iwl_queue *q; | |
244 | struct iwl_tfd *tfd, *tfd_tmp; | |
245 | u32 num_tbs; | |
246 | ||
247 | q = &txq->q; | |
4ce7cc2b | 248 | tfd_tmp = txq->tfds; |
214d14d4 JB |
249 | tfd = &tfd_tmp[q->write_ptr]; |
250 | ||
251 | if (reset) | |
252 | memset(tfd, 0, sizeof(*tfd)); | |
253 | ||
254 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
255 | ||
256 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
257 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 258 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
259 | IWL_NUM_OF_TBS); |
260 | return -EINVAL; | |
261 | } | |
262 | ||
263 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
264 | return -EINVAL; | |
265 | ||
266 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 267 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
268 | (unsigned long long)addr); |
269 | ||
270 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
fd4abac5 TW |
275 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
276 | * DMA services | |
277 | * | |
278 | * Theory of operation | |
279 | * | |
280 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
281 | * of buffer descriptors, each of which points to one or more data buffers for | |
282 | * the device to read from or fill. Driver and device exchange status of each | |
283 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
284 | * entries in each circular buffer, to protect against confusing empty and full | |
285 | * queue states. | |
286 | * | |
287 | * The device reads or writes the data in the queues via the device's several | |
288 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
289 | * | |
290 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
291 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
292 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
293 | * Tx queue resumed. | |
294 | * | |
fd4abac5 TW |
295 | ***************************************************/ |
296 | ||
297 | int iwl_queue_space(const struct iwl_queue *q) | |
298 | { | |
299 | int s = q->read_ptr - q->write_ptr; | |
300 | ||
301 | if (q->read_ptr > q->write_ptr) | |
302 | s -= q->n_bd; | |
303 | ||
304 | if (s <= 0) | |
305 | s += q->n_window; | |
306 | /* keep some reserve to not confuse empty and full situations */ | |
307 | s -= 2; | |
308 | if (s < 0) | |
309 | s = 0; | |
310 | return s; | |
311 | } | |
fd4abac5 | 312 | |
1053d35f RR |
313 | /** |
314 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
315 | */ | |
6d8f6eeb | 316 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
317 | { |
318 | q->n_bd = count; | |
319 | q->n_window = slots_num; | |
320 | q->id = id; | |
321 | ||
322 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
323 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
324 | if (WARN_ON(!is_power_of_2(count))) |
325 | return -EINVAL; | |
1053d35f RR |
326 | |
327 | /* slots_num must be power-of-two size, otherwise | |
328 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
329 | if (WARN_ON(!is_power_of_2(slots_num))) |
330 | return -EINVAL; | |
1053d35f RR |
331 | |
332 | q->low_mark = q->n_window / 4; | |
333 | if (q->low_mark < 4) | |
334 | q->low_mark = 4; | |
335 | ||
336 | q->high_mark = q->n_window / 8; | |
337 | if (q->high_mark < 2) | |
338 | q->high_mark = 2; | |
339 | ||
340 | q->write_ptr = q->read_ptr = 0; | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
6d8f6eeb | 345 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
346 | struct iwl_tx_queue *txq) |
347 | { | |
105183b1 EG |
348 | struct iwl_trans_pcie *trans_pcie = |
349 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 350 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
351 | int txq_id = txq->q.id; |
352 | int read_ptr = txq->q.read_ptr; | |
353 | u8 sta_id = 0; | |
354 | __le16 bc_ent; | |
132f98c2 EG |
355 | struct iwl_tx_cmd *tx_cmd = |
356 | (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload; | |
48d42c42 EG |
357 | |
358 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
359 | ||
6d8f6eeb | 360 | if (txq_id != trans->shrd->cmd_queue) |
132f98c2 | 361 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
362 | |
363 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
364 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
365 | ||
366 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
367 | scd_bc_tbl[txq_id]. | |
368 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
369 | } | |
370 | ||
6d8f6eeb | 371 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
372 | u16 txq_id) |
373 | { | |
374 | u32 tbl_dw_addr; | |
375 | u32 tbl_dw; | |
376 | u16 scd_q2ratid; | |
377 | ||
105183b1 EG |
378 | struct iwl_trans_pcie *trans_pcie = |
379 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
380 | ||
48d42c42 EG |
381 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
382 | ||
105183b1 | 383 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
384 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
385 | ||
83ed9015 | 386 | tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr); |
48d42c42 EG |
387 | |
388 | if (txq_id & 0x1) | |
389 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
390 | else | |
391 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
392 | ||
83ed9015 | 393 | iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw); |
48d42c42 EG |
394 | |
395 | return 0; | |
396 | } | |
397 | ||
6d8f6eeb | 398 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
399 | { |
400 | /* Simply stop the queue, but don't change any configuration; | |
401 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
83ed9015 | 402 | iwl_write_prph(bus(trans), |
48d42c42 EG |
403 | SCD_QUEUE_STATUS_BITS(txq_id), |
404 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
405 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
406 | } | |
407 | ||
6d8f6eeb | 408 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
409 | int txq_id, u32 index) |
410 | { | |
83ed9015 | 411 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, |
48d42c42 | 412 | (index & 0xff) | (txq_id << 8)); |
83ed9015 | 413 | iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
414 | } |
415 | ||
c91bd124 | 416 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
48d42c42 EG |
417 | struct iwl_tx_queue *txq, |
418 | int tx_fifo_id, int scd_retry) | |
419 | { | |
8ad71bef | 420 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 421 | int txq_id = txq->q.id; |
c91bd124 | 422 | int active = |
8ad71bef | 423 | test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0; |
48d42c42 | 424 | |
c91bd124 | 425 | iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
426 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
427 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
428 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
429 | SCD_QUEUE_STTS_REG_MSK); | |
430 | ||
431 | txq->sched_retry = scd_retry; | |
432 | ||
81a3de1c | 433 | IWL_DEBUG_TX_QUEUES(trans, "%s %s Queue %d on FIFO %d\n", |
48d42c42 EG |
434 | active ? "Activate" : "Deactivate", |
435 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
436 | } | |
437 | ||
e13c0c59 EG |
438 | static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie, |
439 | u8 ctx, u16 tid) | |
ba562f71 | 440 | { |
e13c0c59 | 441 | const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx]; |
ba562f71 | 442 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) |
e13c0c59 | 443 | return ac_to_fifo[tid_to_ac[tid]]; |
ba562f71 EG |
444 | |
445 | /* no support for TIDs 8-15 yet */ | |
446 | return -EINVAL; | |
447 | } | |
448 | ||
c91bd124 EG |
449 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, |
450 | enum iwl_rxon_context_id ctx, int sta_id, | |
822e8b2a | 451 | int tid, int frame_limit, u16 ssn) |
48d42c42 | 452 | { |
822e8b2a | 453 | int tx_fifo, txq_id; |
48d42c42 EG |
454 | u16 ra_tid; |
455 | unsigned long flags; | |
48d42c42 | 456 | |
105183b1 EG |
457 | struct iwl_trans_pcie *trans_pcie = |
458 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
459 | ||
48d42c42 EG |
460 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) |
461 | return; | |
5f85a789 | 462 | if (WARN_ON(tid >= IWL_MAX_TID_COUNT)) |
48d42c42 EG |
463 | return; |
464 | ||
e13c0c59 | 465 | tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid); |
ba562f71 EG |
466 | if (WARN_ON(tx_fifo < 0)) { |
467 | IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo); | |
468 | return; | |
469 | } | |
470 | ||
822e8b2a | 471 | txq_id = trans->shrd->tid_data[sta_id][tid].agg.txq_id; |
48d42c42 EG |
472 | |
473 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
474 | ||
c91bd124 | 475 | spin_lock_irqsave(&trans->shrd->lock, flags); |
48d42c42 EG |
476 | |
477 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 478 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
479 | |
480 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 481 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
482 | |
483 | /* Set this queue as a chain-building queue */ | |
c91bd124 | 484 | iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id)); |
48d42c42 EG |
485 | |
486 | /* enable aggregations for the queue */ | |
c91bd124 | 487 | iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id)); |
48d42c42 EG |
488 | |
489 | /* Place first TFD at index corresponding to start sequence number. | |
490 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
491 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
492 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
493 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
494 | |
495 | /* Set up Tx window size and frame limit for this queue */ | |
c91bd124 | 496 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + |
48d42c42 EG |
497 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
498 | sizeof(u32), | |
499 | ((frame_limit << | |
500 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
501 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
502 | ((frame_limit << | |
503 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
504 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
505 | ||
c91bd124 | 506 | iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
507 | |
508 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 509 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
c91bd124 | 510 | tx_fifo, 1); |
48d42c42 | 511 | |
8ad71bef EG |
512 | trans_pcie->txq[txq_id].sta_id = sta_id; |
513 | trans_pcie->txq[txq_id].tid = tid; | |
a0eaad71 | 514 | |
c91bd124 | 515 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
48d42c42 EG |
516 | } |
517 | ||
288712a6 EG |
518 | /* |
519 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
520 | * Called only when finding queue for aggregation. | |
521 | * Should never return anything < 7, because they should already | |
522 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
523 | */ | |
524 | static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans) | |
525 | { | |
8ad71bef | 526 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 EG |
527 | int txq_id; |
528 | ||
529 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) | |
530 | if (!test_and_set_bit(txq_id, | |
8ad71bef | 531 | &trans_pcie->txq_ctx_active_msk)) |
288712a6 EG |
532 | return txq_id; |
533 | return -1; | |
534 | } | |
535 | ||
536 | int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, | |
3c69b595 | 537 | int sta_id, int tid) |
288712a6 | 538 | { |
8ad71bef | 539 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
143bb15d | 540 | int txq_id; |
288712a6 EG |
541 | |
542 | txq_id = iwlagn_txq_ctx_activate_free(trans); | |
543 | if (txq_id == -1) { | |
544 | IWL_ERR(trans, "No free aggregation queue available\n"); | |
545 | return -ENXIO; | |
546 | } | |
547 | ||
3c69b595 | 548 | trans->shrd->tid_data[sta_id][tid].agg.txq_id = txq_id; |
8ad71bef | 549 | iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id); |
288712a6 | 550 | |
288712a6 EG |
551 | return 0; |
552 | } | |
7f01d567 | 553 | |
bc237730 | 554 | int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid) |
48d42c42 | 555 | { |
8ad71bef | 556 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
bc237730 EG |
557 | /* TODO: the transport layer shouldn't access the tid_data */ |
558 | int txq_id = trans->shrd->tid_data[sta_id][tid].agg.txq_id; | |
7f01d567 | 559 | |
48d42c42 EG |
560 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || |
561 | (IWLAGN_FIRST_AMPDU_QUEUE + | |
7f01d567 EG |
562 | hw_params(trans).num_ampdu_queues <= txq_id)) { |
563 | IWL_ERR(trans, | |
48d42c42 EG |
564 | "queue number out of range: %d, must be %d to %d\n", |
565 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
566 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7f01d567 | 567 | hw_params(trans).num_ampdu_queues - 1); |
48d42c42 EG |
568 | return -EINVAL; |
569 | } | |
570 | ||
bc237730 | 571 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 572 | |
bc237730 | 573 | iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id)); |
48d42c42 | 574 | |
bc237730 EG |
575 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
576 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
577 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
578 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); | |
48d42c42 | 579 | |
bc237730 EG |
580 | iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id)); |
581 | iwl_txq_ctx_deactivate(trans_pcie, txq_id); | |
582 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0); | |
48d42c42 EG |
583 | return 0; |
584 | } | |
585 | ||
fd4abac5 TW |
586 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
587 | ||
588 | /** | |
589 | * iwl_enqueue_hcmd - enqueue a uCode command | |
590 | * @priv: device private data point | |
591 | * @cmd: a point to the ucode command structure | |
592 | * | |
593 | * The function returns < 0 values to indicate the operation is | |
594 | * failed. On success, it turns the index (> 0) of command in the | |
595 | * command queue. | |
596 | */ | |
6d8f6eeb | 597 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 598 | { |
8ad71bef EG |
599 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
600 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
fd4abac5 | 601 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
602 | struct iwl_device_cmd *out_cmd; |
603 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 604 | dma_addr_t phys_addr; |
fd4abac5 | 605 | unsigned long flags; |
f3674227 | 606 | u32 idx; |
4ce7cc2b | 607 | u16 copy_size, cmd_size; |
0975cc8f | 608 | bool is_ct_kill = false; |
4ce7cc2b JB |
609 | bool had_nocopy = false; |
610 | int i; | |
611 | u8 *cmd_dest; | |
612 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
613 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
614 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
615 | int trace_idx; | |
616 | #endif | |
fd4abac5 | 617 | |
6d8f6eeb EG |
618 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { |
619 | IWL_WARN(trans, "fw recovery, no hcmd send\n"); | |
3083d03c WYG |
620 | return -EIO; |
621 | } | |
622 | ||
fd656935 | 623 | if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) && |
eedb6e35 | 624 | !(cmd->flags & CMD_ON_DEMAND)) { |
6d8f6eeb | 625 | IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n"); |
eedb6e35 WYG |
626 | return -EIO; |
627 | } | |
628 | ||
4ce7cc2b JB |
629 | copy_size = sizeof(out_cmd->hdr); |
630 | cmd_size = sizeof(out_cmd->hdr); | |
631 | ||
632 | /* need one for the header if the first is NOCOPY */ | |
633 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
634 | ||
635 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
636 | if (!cmd->len[i]) | |
637 | continue; | |
638 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
639 | had_nocopy = true; | |
640 | } else { | |
641 | /* NOCOPY must not be followed by normal! */ | |
642 | if (WARN_ON(had_nocopy)) | |
643 | return -EINVAL; | |
644 | copy_size += cmd->len[i]; | |
645 | } | |
646 | cmd_size += cmd->len[i]; | |
647 | } | |
fd4abac5 | 648 | |
3e41ace5 JB |
649 | /* |
650 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
651 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
652 | * allocated into separate TFDs, then we will need to | |
653 | * increase the size of the buffers. | |
3e41ace5 | 654 | */ |
4ce7cc2b | 655 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 656 | return -EINVAL; |
fd4abac5 | 657 | |
6d8f6eeb EG |
658 | if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) { |
659 | IWL_WARN(trans, "Not sending command - %s KILL\n", | |
660 | iwl_is_rfkill(trans->shrd) ? "RF" : "CT"); | |
fd4abac5 TW |
661 | return -EIO; |
662 | } | |
7b21f00e | 663 | |
72012474 | 664 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
3598e177 | 665 | |
c2acea8e | 666 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
72012474 | 667 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
3598e177 | 668 | |
6d8f6eeb | 669 | IWL_ERR(trans, "No space in command queue\n"); |
fd656935 | 670 | is_ct_kill = iwl_check_for_ct_kill(priv(trans)); |
0975cc8f | 671 | if (!is_ct_kill) { |
6d8f6eeb | 672 | IWL_ERR(trans, "Restarting adapter queue is full\n"); |
fd656935 | 673 | iwlagn_fw_error(priv(trans), false); |
7812b167 | 674 | } |
fd4abac5 TW |
675 | return -ENOSPC; |
676 | } | |
677 | ||
4ce7cc2b | 678 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 679 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
680 | out_meta = &txq->meta[idx]; |
681 | ||
8ce73f3a | 682 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
683 | if (cmd->flags & CMD_WANT_SKB) |
684 | out_meta->source = cmd; | |
fd4abac5 | 685 | |
4ce7cc2b | 686 | /* set up the header */ |
fd4abac5 | 687 | |
4ce7cc2b | 688 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 689 | out_cmd->hdr.flags = 0; |
cefeaa5f | 690 | out_cmd->hdr.sequence = |
6d8f6eeb | 691 | cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) | |
cefeaa5f | 692 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
693 | |
694 | /* and copy the data that needs to be copied */ | |
695 | ||
132f98c2 | 696 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
697 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
698 | if (!cmd->len[i]) | |
699 | continue; | |
700 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
701 | break; | |
702 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
703 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 704 | } |
4ce7cc2b | 705 | |
6d8f6eeb | 706 | IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, " |
4ce7cc2b JB |
707 | "%d bytes at %d[%d]:%d\n", |
708 | get_cmd_string(out_cmd->hdr.cmd), | |
709 | out_cmd->hdr.cmd, | |
710 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
6d8f6eeb | 711 | q->write_ptr, idx, trans->shrd->cmd_queue); |
4ce7cc2b | 712 | |
6d8f6eeb | 713 | phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size, |
795414db | 714 | DMA_BIDIRECTIONAL); |
6d8f6eeb | 715 | if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { |
2c46f72e JB |
716 | idx = -ENOMEM; |
717 | goto out; | |
718 | } | |
719 | ||
2e724443 | 720 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
721 | dma_unmap_len_set(out_meta, len, copy_size); |
722 | ||
6d8f6eeb EG |
723 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
724 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
725 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
726 | trace_bufs[0] = &out_cmd->hdr; | |
727 | trace_lens[0] = copy_size; | |
728 | trace_idx = 1; | |
729 | #endif | |
730 | ||
731 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
732 | if (!cmd->len[i]) | |
733 | continue; | |
734 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
735 | continue; | |
6d8f6eeb EG |
736 | phys_addr = dma_map_single(bus(trans)->dev, |
737 | (void *)cmd->data[i], | |
3be3fdb5 | 738 | cmd->len[i], DMA_BIDIRECTIONAL); |
6d8f6eeb EG |
739 | if (dma_mapping_error(bus(trans)->dev, phys_addr)) { |
740 | iwlagn_unmap_tfd(trans, out_meta, | |
e815407d | 741 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 742 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
743 | idx = -ENOMEM; |
744 | goto out; | |
745 | } | |
746 | ||
6d8f6eeb | 747 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
748 | cmd->len[i], 0); |
749 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
750 | trace_bufs[trace_idx] = cmd->data[i]; | |
751 | trace_lens[trace_idx] = cmd->len[i]; | |
752 | trace_idx++; | |
753 | #endif | |
754 | } | |
df833b1d | 755 | |
afaf6b57 | 756 | out_meta->flags = cmd->flags; |
2c46f72e JB |
757 | |
758 | txq->need_update = 1; | |
759 | ||
4ce7cc2b JB |
760 | /* check that tracing gets all possible blocks */ |
761 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
762 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
fd656935 | 763 | trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags, |
4ce7cc2b JB |
764 | trace_bufs[0], trace_lens[0], |
765 | trace_bufs[1], trace_lens[1], | |
766 | trace_bufs[2], trace_lens[2]); | |
767 | #endif | |
df833b1d | 768 | |
fd4abac5 TW |
769 | /* Increment and update queue's write index */ |
770 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 771 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 772 | |
2c46f72e | 773 | out: |
72012474 | 774 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
7bfedc59 | 775 | return idx; |
fd4abac5 TW |
776 | } |
777 | ||
17b88929 TW |
778 | /** |
779 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
780 | * | |
781 | * When FW advances 'R' index, all entries between old and new 'R' index | |
782 | * need to be reclaimed. As result, some free space forms. If there is | |
783 | * enough free space (> low mark), wake the stack that feeds us. | |
784 | */ | |
3e10caeb EG |
785 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
786 | int idx) | |
17b88929 | 787 | { |
3e10caeb | 788 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 789 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
790 | struct iwl_queue *q = &txq->q; |
791 | int nfreed = 0; | |
792 | ||
499b1883 | 793 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 794 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
795 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
796 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
797 | return; |
798 | } | |
799 | ||
499b1883 TW |
800 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
801 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 802 | |
499b1883 | 803 | if (nfreed++ > 0) { |
3e10caeb | 804 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 805 | q->write_ptr, q->read_ptr); |
3e10caeb | 806 | iwlagn_fw_error(priv(trans), false); |
17b88929 | 807 | } |
da99c4b6 | 808 | |
17b88929 TW |
809 | } |
810 | } | |
811 | ||
812 | /** | |
813 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
814 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
815 | * @handler_status: return value of the handler of the command |
816 | * (put in setup_rx_handlers) | |
17b88929 TW |
817 | * |
818 | * If an Rx buffer has an async callback associated with it the callback | |
819 | * will be executed. The attached skb (if present) will only be freed | |
820 | * if the callback returns 1 | |
821 | */ | |
247c61d6 EG |
822 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb, |
823 | int handler_status) | |
17b88929 | 824 | { |
2f301227 | 825 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
826 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
827 | int txq_id = SEQ_TO_QUEUE(sequence); | |
828 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 829 | int cmd_index; |
c2acea8e JB |
830 | struct iwl_device_cmd *cmd; |
831 | struct iwl_cmd_meta *meta; | |
8ad71bef EG |
832 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
833 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
3598e177 | 834 | unsigned long flags; |
17b88929 TW |
835 | |
836 | /* If a Tx command is being handled and it isn't in the actual | |
837 | * command queue then there a command routing bug has been introduced | |
838 | * in the queue management code. */ | |
6d8f6eeb | 839 | if (WARN(txq_id != trans->shrd->cmd_queue, |
13bb9483 | 840 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
6d8f6eeb | 841 | txq_id, trans->shrd->cmd_queue, sequence, |
8ad71bef EG |
842 | trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr, |
843 | trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) { | |
3e10caeb | 844 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 845 | return; |
01ef9323 | 846 | } |
17b88929 | 847 | |
4ce7cc2b | 848 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
849 | cmd = txq->cmd[cmd_index]; |
850 | meta = &txq->meta[cmd_index]; | |
17b88929 | 851 | |
282cdb32 JB |
852 | txq->time_stamp = jiffies; |
853 | ||
6d8f6eeb EG |
854 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
855 | DMA_BIDIRECTIONAL); | |
c33de625 | 856 | |
17b88929 | 857 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 858 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 | 859 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
247c61d6 | 860 | meta->source->handler_status = handler_status; |
2f301227 | 861 | rxb->page = NULL; |
247c61d6 | 862 | } |
2624e96c | 863 | |
72012474 | 864 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
17b88929 | 865 | |
3e10caeb | 866 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 867 | |
c2acea8e | 868 | if (!(meta->flags & CMD_ASYNC)) { |
05c89b91 WYG |
869 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
870 | IWL_WARN(trans, | |
871 | "HCMD_ACTIVE already clear for command %s\n", | |
872 | get_cmd_string(cmd->hdr.cmd)); | |
873 | } | |
6d8f6eeb EG |
874 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
875 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", | |
d2dfe6df | 876 | get_cmd_string(cmd->hdr.cmd)); |
effd4d9a | 877 | wake_up(&trans->shrd->wait_command_queue); |
17b88929 | 878 | } |
3598e177 | 879 | |
dd487449 | 880 | meta->flags = 0; |
3598e177 | 881 | |
72012474 | 882 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
17b88929 | 883 | } |
253a634c | 884 | |
253a634c EG |
885 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
886 | ||
6d8f6eeb | 887 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
888 | { |
889 | int ret; | |
890 | ||
891 | /* An asynchronous command can not expect an SKB to be set. */ | |
892 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
893 | return -EINVAL; | |
894 | ||
253a634c | 895 | |
6d8f6eeb | 896 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
253a634c EG |
897 | return -EBUSY; |
898 | ||
6d8f6eeb | 899 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 900 | if (ret < 0) { |
b36b110c TP |
901 | IWL_DEBUG_QUIET_RFKILL(trans, |
902 | "Error sending %s: enqueue_hcmd failed: %d\n", | |
253a634c EG |
903 | get_cmd_string(cmd->id), ret); |
904 | return ret; | |
905 | } | |
906 | return 0; | |
907 | } | |
908 | ||
6d8f6eeb | 909 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 910 | { |
8ad71bef | 911 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
912 | int cmd_idx; |
913 | int ret; | |
914 | ||
6d8f6eeb | 915 | lockdep_assert_held(&trans->shrd->mutex); |
253a634c | 916 | |
6d8f6eeb | 917 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
253a634c EG |
918 | get_cmd_string(cmd->id)); |
919 | ||
94b3c45c WYG |
920 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
921 | return -EBUSY; | |
922 | ||
923 | ||
924 | if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) { | |
925 | IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n", | |
926 | get_cmd_string(cmd->id)); | |
927 | return -ECANCELED; | |
928 | } | |
929 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { | |
930 | IWL_ERR(trans, "Command %s failed: FW Error\n", | |
931 | get_cmd_string(cmd->id)); | |
932 | return -EIO; | |
933 | } | |
6d8f6eeb EG |
934 | set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
935 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", | |
253a634c EG |
936 | get_cmd_string(cmd->id)); |
937 | ||
6d8f6eeb | 938 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
939 | if (cmd_idx < 0) { |
940 | ret = cmd_idx; | |
6d8f6eeb | 941 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
b36b110c TP |
942 | IWL_DEBUG_QUIET_RFKILL(trans, |
943 | "Error sending %s: enqueue_hcmd failed: %d\n", | |
253a634c EG |
944 | get_cmd_string(cmd->id), ret); |
945 | return ret; | |
946 | } | |
947 | ||
effd4d9a | 948 | ret = wait_event_timeout(trans->shrd->wait_command_queue, |
6d8f6eeb | 949 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), |
253a634c EG |
950 | HOST_COMPLETE_TIMEOUT); |
951 | if (!ret) { | |
6d8f6eeb | 952 | if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
d10630af | 953 | struct iwl_tx_queue *txq = |
397ede37 | 954 | &trans_pcie->txq[trans->shrd->cmd_queue]; |
d10630af WYG |
955 | struct iwl_queue *q = &txq->q; |
956 | ||
b36b110c | 957 | IWL_DEBUG_QUIET_RFKILL(trans, |
253a634c EG |
958 | "Error sending %s: time out after %dms.\n", |
959 | get_cmd_string(cmd->id), | |
960 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
961 | ||
b36b110c | 962 | IWL_DEBUG_QUIET_RFKILL(trans, |
d10630af WYG |
963 | "Current CMD queue read_ptr %d write_ptr %d\n", |
964 | q->read_ptr, q->write_ptr); | |
965 | ||
6d8f6eeb EG |
966 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
967 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command" | |
253a634c EG |
968 | "%s\n", get_cmd_string(cmd->id)); |
969 | ret = -ETIMEDOUT; | |
970 | goto cancel; | |
971 | } | |
972 | } | |
973 | ||
253a634c | 974 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { |
6d8f6eeb | 975 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
253a634c EG |
976 | get_cmd_string(cmd->id)); |
977 | ret = -EIO; | |
978 | goto cancel; | |
979 | } | |
980 | ||
981 | return 0; | |
982 | ||
983 | cancel: | |
984 | if (cmd->flags & CMD_WANT_SKB) { | |
985 | /* | |
986 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
987 | * TX cmd queue. Otherwise in case the cmd comes | |
988 | * in later, it will possibly set an invalid | |
989 | * address (cmd->meta.source). | |
990 | */ | |
8ad71bef | 991 | trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
992 | ~CMD_WANT_SKB; |
993 | } | |
9cac4943 | 994 | |
253a634c | 995 | if (cmd->reply_page) { |
6d8f6eeb | 996 | iwl_free_pages(trans->shrd, cmd->reply_page); |
253a634c EG |
997 | cmd->reply_page = 0; |
998 | } | |
999 | ||
1000 | return ret; | |
1001 | } | |
1002 | ||
6d8f6eeb | 1003 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
1004 | { |
1005 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 1006 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 1007 | |
6d8f6eeb | 1008 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
1009 | } |
1010 | ||
a0eaad71 | 1011 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
1012 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
1013 | struct sk_buff_head *skbs) | |
a0eaad71 | 1014 | { |
8ad71bef EG |
1015 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1016 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 1017 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 1018 | int last_to_free; |
464021ff | 1019 | int freed = 0; |
a0eaad71 | 1020 | |
39644e9a EG |
1021 | /* This function is not meant to release cmd queue*/ |
1022 | if (WARN_ON(txq_id == trans->shrd->cmd_queue)) | |
1023 | return 0; | |
1024 | ||
a0eaad71 EG |
1025 | /*Since we free until index _not_ inclusive, the one before index is |
1026 | * the last we will free. This one must be used */ | |
1027 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
1028 | ||
1029 | if ((index >= q->n_bd) || | |
1030 | (iwl_queue_used(q, last_to_free) == 0)) { | |
1031 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
1032 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
1033 | __func__, txq_id, last_to_free, q->n_bd, | |
1034 | q->write_ptr, q->read_ptr); | |
464021ff | 1035 | return 0; |
a0eaad71 EG |
1036 | } |
1037 | ||
a0eaad71 | 1038 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 1039 | return 0; |
a0eaad71 EG |
1040 | |
1041 | for (; | |
1042 | q->read_ptr != index; | |
1043 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1044 | ||
2c452297 | 1045 | if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL)) |
a0eaad71 EG |
1046 | continue; |
1047 | ||
2c452297 | 1048 | __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]); |
a0eaad71 | 1049 | |
2c452297 | 1050 | txq->skbs[txq->q.read_ptr] = NULL; |
a0eaad71 | 1051 | |
6d8f6eeb | 1052 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 1053 | |
39644e9a | 1054 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE); |
464021ff | 1055 | freed++; |
a0eaad71 | 1056 | } |
464021ff | 1057 | return freed; |
a0eaad71 | 1058 | } |