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a55360e4 TW |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
a55360e4 TW |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
a55360e4 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
1781a07f | 30 | #include <linux/etherdevice.h> |
a55360e4 | 31 | #include <net/mac80211.h> |
a05ffd39 | 32 | #include <asm/unaligned.h> |
a55360e4 TW |
33 | #include "iwl-eeprom.h" |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
c1354754 | 38 | #include "iwl-calib.h" |
a55360e4 TW |
39 | #include "iwl-helpers.h" |
40 | /************************** RX-FUNCTIONS ****************************/ | |
41 | /* | |
42 | * Rx theory of operation | |
43 | * | |
44 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
45 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
46 | * used not only for Rx frames, but for any command response or notification | |
47 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
48 | * of indexes into the circular buffer. | |
49 | * | |
50 | * Rx Queue Indexes | |
51 | * The host/firmware share two index registers for managing the Rx buffers. | |
52 | * | |
53 | * The READ index maps to the first position that the firmware may be writing | |
54 | * to -- the driver can read up to (but not including) this position and get | |
55 | * good data. | |
56 | * The READ index is managed by the firmware once the card is enabled. | |
57 | * | |
58 | * The WRITE index maps to the last position the driver has read from -- the | |
59 | * position preceding WRITE is the last slot the firmware can place a packet. | |
60 | * | |
61 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
62 | * WRITE = READ. | |
63 | * | |
64 | * During initialization, the host sets up the READ queue position to the first | |
65 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
66 | * | |
67 | * When the firmware places a packet in a buffer, it will advance the READ index | |
68 | * and fire the RX interrupt. The driver can then query the READ index and | |
69 | * process as many packets as possible, moving the WRITE index forward as it | |
70 | * resets the Rx queue buffers with new memory. | |
71 | * | |
72 | * The management in the driver is as follows: | |
73 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
74 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
75 | * to replenish the iwl->rxq->rx_free. | |
76 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
77 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
78 | * 'processed' and 'read' driver indexes as well) | |
79 | * + A received packet is processed and handed to the kernel network stack, | |
80 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
81 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
82 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
83 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
84 | * were enough free buffers and RX_STALLED is set it is cleared. | |
85 | * | |
86 | * | |
87 | * Driver sequence: | |
88 | * | |
89 | * iwl_rx_queue_alloc() Allocates rx_free | |
90 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
91 | * iwl_rx_queue_restock | |
92 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
93 | * queue, updates firmware pointers, and updates | |
94 | * the WRITE index. If insufficient rx_free buffers | |
95 | * are available, schedules iwl_rx_replenish | |
96 | * | |
97 | * -- enable interrupts -- | |
98 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
99 | * READ INDEX, detaching the SKB from the pool. | |
100 | * Moves the packet buffer from queue to rx_used. | |
101 | * Calls iwl_rx_queue_restock to refill any empty | |
102 | * slots. | |
103 | * ... | |
104 | * | |
105 | */ | |
106 | ||
107 | /** | |
108 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
109 | */ | |
110 | int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
111 | { | |
112 | int s = q->read - q->write; | |
113 | if (s <= 0) | |
114 | s += RX_QUEUE_SIZE; | |
115 | /* keep some buffer to not confuse full and empty queue */ | |
116 | s -= 2; | |
117 | if (s < 0) | |
118 | s = 0; | |
119 | return s; | |
120 | } | |
121 | EXPORT_SYMBOL(iwl_rx_queue_space); | |
122 | ||
123 | /** | |
124 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
125 | */ | |
126 | int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q) | |
127 | { | |
a55360e4 | 128 | unsigned long flags; |
141c43a3 WT |
129 | u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg; |
130 | u32 reg; | |
131 | int ret = 0; | |
a55360e4 TW |
132 | |
133 | spin_lock_irqsave(&q->lock, flags); | |
134 | ||
135 | if (q->need_update == 0) | |
136 | goto exit_unlock; | |
137 | ||
138 | /* If power-saving is in use, make sure device is awake */ | |
139 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
140 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
141 | ||
142 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
309e731a BC |
143 | IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n", |
144 | reg); | |
a55360e4 TW |
145 | iwl_set_bit(priv, CSR_GP_CNTRL, |
146 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
147 | goto exit_unlock; | |
148 | } | |
149 | ||
4752c93c MA |
150 | q->write_actual = (q->write & ~0x7); |
151 | iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual); | |
a55360e4 TW |
152 | |
153 | /* Else device is assumed to be awake */ | |
141c43a3 | 154 | } else { |
a55360e4 | 155 | /* Device expects a multiple of 8 */ |
4752c93c MA |
156 | q->write_actual = (q->write & ~0x7); |
157 | iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual); | |
141c43a3 | 158 | } |
a55360e4 TW |
159 | |
160 | q->need_update = 0; | |
161 | ||
162 | exit_unlock: | |
163 | spin_unlock_irqrestore(&q->lock, flags); | |
164 | return ret; | |
165 | } | |
166 | EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr); | |
167 | /** | |
168 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
169 | */ | |
170 | static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv, | |
171 | dma_addr_t dma_addr) | |
172 | { | |
173 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
174 | } | |
175 | ||
176 | /** | |
177 | * iwl_rx_queue_restock - refill RX queue from pre-allocated pool | |
178 | * | |
179 | * If there are slots in the RX queue that need to be restocked, | |
180 | * and we have free pre-allocated buffers, fill the ranks as much | |
181 | * as we can, pulling from rx_free. | |
182 | * | |
183 | * This moves the 'write' index forward to catch up with 'processed', and | |
184 | * also updates the memory address in the firmware to reference the new | |
185 | * target buffer. | |
186 | */ | |
187 | int iwl_rx_queue_restock(struct iwl_priv *priv) | |
188 | { | |
189 | struct iwl_rx_queue *rxq = &priv->rxq; | |
190 | struct list_head *element; | |
191 | struct iwl_rx_mem_buffer *rxb; | |
192 | unsigned long flags; | |
193 | int write; | |
194 | int ret = 0; | |
195 | ||
196 | spin_lock_irqsave(&rxq->lock, flags); | |
197 | write = rxq->write & ~0x7; | |
198 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
199 | /* Get next free Rx buffer, remove from free list */ | |
200 | element = rxq->rx_free.next; | |
201 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
202 | list_del(element); | |
203 | ||
204 | /* Point to Rx buffer via next RBD in circular buffer */ | |
2f301227 | 205 | rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->page_dma); |
a55360e4 TW |
206 | rxq->queue[rxq->write] = rxb; |
207 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
208 | rxq->free_count--; | |
209 | } | |
210 | spin_unlock_irqrestore(&rxq->lock, flags); | |
211 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
212 | * refill it */ | |
213 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
214 | queue_work(priv->workqueue, &priv->rx_replenish); | |
215 | ||
216 | ||
217 | /* If we've added more space for the firmware to place data, tell it. | |
218 | * Increment device's write pointer in multiples of 8. */ | |
4752c93c | 219 | if (rxq->write_actual != (rxq->write & ~0x7)) { |
a55360e4 TW |
220 | spin_lock_irqsave(&rxq->lock, flags); |
221 | rxq->need_update = 1; | |
222 | spin_unlock_irqrestore(&rxq->lock, flags); | |
223 | ret = iwl_rx_queue_update_write_ptr(priv, rxq); | |
224 | } | |
225 | ||
226 | return ret; | |
227 | } | |
228 | EXPORT_SYMBOL(iwl_rx_queue_restock); | |
229 | ||
230 | ||
231 | /** | |
232 | * iwl_rx_replenish - Move all used packet from rx_used to rx_free | |
233 | * | |
234 | * When moving to rx_free an SKB is allocated for the slot. | |
235 | * | |
236 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
237 | * This is called as a scheduled work item (except for during initialization) | |
238 | */ | |
4752c93c | 239 | void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
a55360e4 TW |
240 | { |
241 | struct iwl_rx_queue *rxq = &priv->rxq; | |
242 | struct list_head *element; | |
243 | struct iwl_rx_mem_buffer *rxb; | |
2f301227 | 244 | struct page *page; |
a55360e4 | 245 | unsigned long flags; |
29b1b268 | 246 | gfp_t gfp_mask = priority; |
f1bc4ac6 ZY |
247 | |
248 | while (1) { | |
249 | spin_lock_irqsave(&rxq->lock, flags); | |
f1bc4ac6 ZY |
250 | if (list_empty(&rxq->rx_used)) { |
251 | spin_unlock_irqrestore(&rxq->lock, flags); | |
252 | return; | |
253 | } | |
f1bc4ac6 | 254 | spin_unlock_irqrestore(&rxq->lock, flags); |
a55360e4 | 255 | |
f82a924c | 256 | if (rxq->free_count > RX_LOW_WATERMARK) |
29b1b268 | 257 | gfp_mask |= __GFP_NOWARN; |
4752c93c | 258 | |
2f301227 | 259 | if (priv->hw_params.rx_page_order > 0) |
29b1b268 | 260 | gfp_mask |= __GFP_COMP; |
2f301227 ZY |
261 | |
262 | /* Alloc a new receive buffer */ | |
29b1b268 | 263 | page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); |
2f301227 | 264 | if (!page) { |
f82a924c | 265 | if (net_ratelimit()) |
2f301227 ZY |
266 | IWL_DEBUG_INFO(priv, "alloc_pages failed, " |
267 | "order: %d\n", | |
268 | priv->hw_params.rx_page_order); | |
269 | ||
f82a924c RC |
270 | if ((rxq->free_count <= RX_LOW_WATERMARK) && |
271 | net_ratelimit()) | |
2f301227 | 272 | IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n", |
f82a924c RC |
273 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", |
274 | rxq->free_count); | |
a55360e4 TW |
275 | /* We don't reschedule replenish work here -- we will |
276 | * call the restock method and if it still needs | |
277 | * more buffers it will schedule replenish */ | |
2f301227 | 278 | return; |
a55360e4 | 279 | } |
a55360e4 | 280 | |
de0bd508 RC |
281 | spin_lock_irqsave(&rxq->lock, flags); |
282 | ||
283 | if (list_empty(&rxq->rx_used)) { | |
284 | spin_unlock_irqrestore(&rxq->lock, flags); | |
2f301227 | 285 | __free_pages(page, priv->hw_params.rx_page_order); |
de0bd508 RC |
286 | return; |
287 | } | |
288 | element = rxq->rx_used.next; | |
289 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
290 | list_del(element); | |
291 | ||
292 | spin_unlock_irqrestore(&rxq->lock, flags); | |
293 | ||
2f301227 ZY |
294 | rxb->page = page; |
295 | /* Get physical address of the RB */ | |
296 | rxb->page_dma = pci_map_page(priv->pci_dev, page, 0, | |
297 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
298 | PCI_DMA_FROMDEVICE); | |
4018517a | 299 | /* dma address must be no more than 36 bits */ |
2f301227 | 300 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); |
4018517a | 301 | /* and also 256 byte aligned! */ |
2f301227 | 302 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); |
4018517a | 303 | |
f1bc4ac6 ZY |
304 | spin_lock_irqsave(&rxq->lock, flags); |
305 | ||
a55360e4 TW |
306 | list_add_tail(&rxb->list, &rxq->rx_free); |
307 | rxq->free_count++; | |
2f301227 | 308 | priv->alloc_rxb_page++; |
f1bc4ac6 ZY |
309 | |
310 | spin_unlock_irqrestore(&rxq->lock, flags); | |
a55360e4 | 311 | } |
a55360e4 | 312 | } |
a55360e4 TW |
313 | |
314 | void iwl_rx_replenish(struct iwl_priv *priv) | |
315 | { | |
316 | unsigned long flags; | |
317 | ||
4752c93c | 318 | iwl_rx_allocate(priv, GFP_KERNEL); |
a55360e4 TW |
319 | |
320 | spin_lock_irqsave(&priv->lock, flags); | |
321 | iwl_rx_queue_restock(priv); | |
322 | spin_unlock_irqrestore(&priv->lock, flags); | |
323 | } | |
324 | EXPORT_SYMBOL(iwl_rx_replenish); | |
325 | ||
4752c93c MA |
326 | void iwl_rx_replenish_now(struct iwl_priv *priv) |
327 | { | |
328 | iwl_rx_allocate(priv, GFP_ATOMIC); | |
329 | ||
330 | iwl_rx_queue_restock(priv); | |
331 | } | |
332 | EXPORT_SYMBOL(iwl_rx_replenish_now); | |
333 | ||
a55360e4 TW |
334 | |
335 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
336 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
337 | * This free routine walks the list of POOL entries and if SKB is set to | |
338 | * non NULL it is unmapped and freed | |
339 | */ | |
340 | void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
341 | { | |
342 | int i; | |
343 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
2f301227 ZY |
344 | if (rxq->pool[i].page != NULL) { |
345 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
346 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
347 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 348 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 349 | rxq->pool[i].page = NULL; |
a55360e4 TW |
350 | } |
351 | } | |
352 | ||
353 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
354 | rxq->dma_addr); | |
8d86422a WT |
355 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), |
356 | rxq->rb_stts, rxq->rb_stts_dma); | |
a55360e4 | 357 | rxq->bd = NULL; |
8d86422a | 358 | rxq->rb_stts = NULL; |
a55360e4 TW |
359 | } |
360 | EXPORT_SYMBOL(iwl_rx_queue_free); | |
361 | ||
362 | int iwl_rx_queue_alloc(struct iwl_priv *priv) | |
363 | { | |
364 | struct iwl_rx_queue *rxq = &priv->rxq; | |
365 | struct pci_dev *dev = priv->pci_dev; | |
366 | int i; | |
367 | ||
368 | spin_lock_init(&rxq->lock); | |
369 | INIT_LIST_HEAD(&rxq->rx_free); | |
370 | INIT_LIST_HEAD(&rxq->rx_used); | |
371 | ||
372 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
373 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); | |
374 | if (!rxq->bd) | |
8d86422a WT |
375 | goto err_bd; |
376 | ||
377 | rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status), | |
378 | &rxq->rb_stts_dma); | |
379 | if (!rxq->rb_stts) | |
380 | goto err_rb; | |
a55360e4 TW |
381 | |
382 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
383 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
384 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
385 | ||
386 | /* Set us so that we have processed and used all buffers, but have | |
387 | * not restocked the Rx queue with fresh buffers */ | |
388 | rxq->read = rxq->write = 0; | |
4752c93c | 389 | rxq->write_actual = 0; |
a55360e4 TW |
390 | rxq->free_count = 0; |
391 | rxq->need_update = 0; | |
392 | return 0; | |
8d86422a WT |
393 | |
394 | err_rb: | |
395 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
396 | rxq->dma_addr); | |
397 | err_bd: | |
398 | return -ENOMEM; | |
a55360e4 TW |
399 | } |
400 | EXPORT_SYMBOL(iwl_rx_queue_alloc); | |
401 | ||
402 | void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
403 | { | |
404 | unsigned long flags; | |
405 | int i; | |
406 | spin_lock_irqsave(&rxq->lock, flags); | |
407 | INIT_LIST_HEAD(&rxq->rx_free); | |
408 | INIT_LIST_HEAD(&rxq->rx_used); | |
409 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
410 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
411 | /* In the reset function, these buffers may have been allocated | |
412 | * to an SKB, so we need to unmap and free potential storage */ | |
2f301227 ZY |
413 | if (rxq->pool[i].page != NULL) { |
414 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
415 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
416 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 417 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 418 | rxq->pool[i].page = NULL; |
a55360e4 TW |
419 | } |
420 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
421 | } | |
422 | ||
423 | /* Set us so that we have processed and used all buffers, but have | |
424 | * not restocked the Rx queue with fresh buffers */ | |
425 | rxq->read = rxq->write = 0; | |
4752c93c | 426 | rxq->write_actual = 0; |
a55360e4 TW |
427 | rxq->free_count = 0; |
428 | spin_unlock_irqrestore(&rxq->lock, flags); | |
429 | } | |
a55360e4 | 430 | |
1053d35f RR |
431 | int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
432 | { | |
8cd519e8 WT |
433 | u32 rb_size; |
434 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
0324c14b MA |
435 | u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
436 | ||
437 | if (!priv->cfg->use_isr_legacy) | |
438 | rb_timeout = RX_RB_TIMEOUT; | |
1053d35f | 439 | |
1053d35f RR |
440 | if (priv->cfg->mod_params->amsdu_size_8K) |
441 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
442 | else | |
443 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
444 | ||
445 | /* Stop Rx DMA */ | |
446 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
447 | ||
448 | /* Reset driver's Rx queue write index */ | |
449 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
450 | ||
451 | /* Tell device where to find RBD circular buffer in DRAM */ | |
452 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
8cd519e8 | 453 | (u32)(rxq->dma_addr >> 8)); |
1053d35f RR |
454 | |
455 | /* Tell device where in DRAM to update its Rx status */ | |
456 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
8d86422a | 457 | rxq->rb_stts_dma >> 4); |
1053d35f | 458 | |
8cd519e8 | 459 | /* Enable Rx DMA |
a96a27f9 | 460 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in |
8cd519e8 WT |
461 | * the credit mechanism in 5000 HW RX FIFO |
462 | * Direct rx interrupts to hosts | |
463 | * Rx buffer size 4 or 8k | |
464 | * RB timeout 0x10 | |
465 | * 256 RBDs | |
466 | */ | |
1053d35f RR |
467 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
468 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
8cd519e8 | 469 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | |
1053d35f | 470 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
9f925938 | 471 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | |
8cd519e8 WT |
472 | rb_size| |
473 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
474 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
1053d35f | 475 | |
2be76703 WYG |
476 | /* Set interrupt coalescing timer to default (2048 usecs) */ |
477 | iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); | |
8cd519e8 | 478 | |
1053d35f RR |
479 | return 0; |
480 | } | |
481 | ||
b3bbacb7 TW |
482 | int iwl_rxq_stop(struct iwl_priv *priv) |
483 | { | |
b3bbacb7 TW |
484 | |
485 | /* stop Rx DMA */ | |
486 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
73d7b5ac ZY |
487 | iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, |
488 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
b3bbacb7 | 489 | |
b3bbacb7 TW |
490 | return 0; |
491 | } | |
492 | EXPORT_SYMBOL(iwl_rxq_stop); | |
493 | ||
c1354754 TW |
494 | void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, |
495 | struct iwl_rx_mem_buffer *rxb) | |
496 | ||
497 | { | |
2f301227 | 498 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 | 499 | struct iwl_missed_beacon_notif *missed_beacon; |
c1354754 TW |
500 | |
501 | missed_beacon = &pkt->u.missed_beacon; | |
a13d276f WYG |
502 | if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) > |
503 | priv->missed_beacon_threshold) { | |
e1623446 | 504 | IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n", |
a13d276f | 505 | le32_to_cpu(missed_beacon->consecutive_missed_beacons), |
c1354754 TW |
506 | le32_to_cpu(missed_beacon->total_missed_becons), |
507 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
508 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
509 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
510 | iwl_init_sensitivity(priv); | |
511 | } | |
c1354754 TW |
512 | } |
513 | EXPORT_SYMBOL(iwl_rx_missed_beacon_notif); | |
8f91aecb | 514 | |
81963d68 RC |
515 | void iwl_rx_spectrum_measure_notif(struct iwl_priv *priv, |
516 | struct iwl_rx_mem_buffer *rxb) | |
517 | { | |
518 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
519 | struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
520 | ||
521 | if (!report->state) { | |
522 | IWL_DEBUG_11H(priv, | |
523 | "Spectrum Measure Notification: Start\n"); | |
524 | return; | |
525 | } | |
526 | ||
527 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
528 | priv->measurement_status |= MEASUREMENT_READY; | |
529 | } | |
530 | EXPORT_SYMBOL(iwl_rx_spectrum_measure_notif); | |
531 | ||
532 | ||
8f91aecb EG |
533 | |
534 | /* Calculate noise level, based on measurements during network silence just | |
535 | * before arriving beacon. This measurement can be done only if we know | |
536 | * exactly when to expect beacons, therefore only when we're associated. */ | |
537 | static void iwl_rx_calc_noise(struct iwl_priv *priv) | |
538 | { | |
539 | struct statistics_rx_non_phy *rx_info | |
540 | = &(priv->statistics.rx.general); | |
541 | int num_active_rx = 0; | |
542 | int total_silence = 0; | |
543 | int bcn_silence_a = | |
544 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; | |
545 | int bcn_silence_b = | |
546 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; | |
547 | int bcn_silence_c = | |
548 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; | |
549 | ||
550 | if (bcn_silence_a) { | |
551 | total_silence += bcn_silence_a; | |
552 | num_active_rx++; | |
553 | } | |
554 | if (bcn_silence_b) { | |
555 | total_silence += bcn_silence_b; | |
556 | num_active_rx++; | |
557 | } | |
558 | if (bcn_silence_c) { | |
559 | total_silence += bcn_silence_c; | |
560 | num_active_rx++; | |
561 | } | |
562 | ||
563 | /* Average among active antennas */ | |
564 | if (num_active_rx) | |
565 | priv->last_rx_noise = (total_silence / num_active_rx) - 107; | |
566 | else | |
567 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
568 | ||
e1623446 | 569 | IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n", |
8f91aecb EG |
570 | bcn_silence_a, bcn_silence_b, bcn_silence_c, |
571 | priv->last_rx_noise); | |
572 | } | |
573 | ||
92a35bda WYG |
574 | #ifdef CONFIG_IWLWIFI_DEBUG |
575 | /* | |
576 | * based on the assumption of all statistics counter are in DWORD | |
577 | * FIXME: This function is for debugging, do not deal with | |
578 | * the case of counters roll-over. | |
579 | */ | |
580 | static void iwl_accumulative_statistics(struct iwl_priv *priv, | |
581 | __le32 *stats) | |
582 | { | |
583 | int i; | |
584 | __le32 *prev_stats; | |
585 | u32 *accum_stats; | |
e3ef2164 | 586 | u32 *delta, *max_delta; |
92a35bda WYG |
587 | |
588 | prev_stats = (__le32 *)&priv->statistics; | |
589 | accum_stats = (u32 *)&priv->accum_statistics; | |
e3ef2164 WYG |
590 | delta = (u32 *)&priv->delta_statistics; |
591 | max_delta = (u32 *)&priv->max_delta; | |
92a35bda WYG |
592 | |
593 | for (i = sizeof(__le32); i < sizeof(struct iwl_notif_statistics); | |
e3ef2164 WYG |
594 | i += sizeof(__le32), stats++, prev_stats++, delta++, |
595 | max_delta++, accum_stats++) { | |
596 | if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { | |
597 | *delta = (le32_to_cpu(*stats) - | |
92a35bda | 598 | le32_to_cpu(*prev_stats)); |
e3ef2164 WYG |
599 | *accum_stats += *delta; |
600 | if (*delta > *max_delta) | |
601 | *max_delta = *delta; | |
602 | } | |
603 | } | |
92a35bda WYG |
604 | |
605 | /* reset accumulative statistics for "no-counter" type statistics */ | |
606 | priv->accum_statistics.general.temperature = | |
607 | priv->statistics.general.temperature; | |
608 | priv->accum_statistics.general.temperature_m = | |
609 | priv->statistics.general.temperature_m; | |
610 | priv->accum_statistics.general.ttl_timestamp = | |
611 | priv->statistics.general.ttl_timestamp; | |
612 | priv->accum_statistics.tx.tx_power.ant_a = | |
613 | priv->statistics.tx.tx_power.ant_a; | |
614 | priv->accum_statistics.tx.tx_power.ant_b = | |
615 | priv->statistics.tx.tx_power.ant_b; | |
616 | priv->accum_statistics.tx.tx_power.ant_c = | |
617 | priv->statistics.tx.tx_power.ant_c; | |
618 | } | |
619 | #endif | |
620 | ||
8f91aecb EG |
621 | #define REG_RECALIB_PERIOD (60) |
622 | ||
3e4fb5fa | 623 | #define PLCP_MSG "plcp_err exceeded %u, %u, %u, %u, %u, %d, %u mSecs\n" |
8f91aecb EG |
624 | void iwl_rx_statistics(struct iwl_priv *priv, |
625 | struct iwl_rx_mem_buffer *rxb) | |
626 | { | |
5225640b | 627 | int change; |
2f301227 | 628 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
3e4fb5fa TAN |
629 | int combined_plcp_delta; |
630 | unsigned int plcp_msec; | |
631 | unsigned long plcp_received_jiffies; | |
8f91aecb | 632 | |
e1623446 | 633 | IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n", |
396887a2 DH |
634 | (int)sizeof(priv->statistics), |
635 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
8f91aecb | 636 | |
5225640b ZY |
637 | change = ((priv->statistics.general.temperature != |
638 | pkt->u.stats.general.temperature) || | |
639 | ((priv->statistics.flag & | |
7aafef1c WYG |
640 | STATISTICS_REPLY_FLG_HT40_MODE_MSK) != |
641 | (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK))); | |
5225640b | 642 | |
92a35bda WYG |
643 | #ifdef CONFIG_IWLWIFI_DEBUG |
644 | iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats); | |
645 | #endif | |
3e4fb5fa TAN |
646 | /* |
647 | * check for plcp_err and trigger radio reset if it exceeds | |
648 | * the plcp error threshold plcp_delta. | |
649 | */ | |
650 | plcp_received_jiffies = jiffies; | |
651 | plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies - | |
652 | (long) priv->plcp_jiffies); | |
653 | priv->plcp_jiffies = plcp_received_jiffies; | |
654 | /* | |
655 | * check to make sure plcp_msec is not 0 to prevent division | |
656 | * by zero. | |
657 | */ | |
658 | if (plcp_msec) { | |
659 | combined_plcp_delta = | |
660 | (le32_to_cpu(pkt->u.stats.rx.ofdm.plcp_err) - | |
661 | le32_to_cpu(priv->statistics.rx.ofdm.plcp_err)) + | |
662 | (le32_to_cpu(pkt->u.stats.rx.ofdm_ht.plcp_err) - | |
663 | le32_to_cpu(priv->statistics.rx.ofdm_ht.plcp_err)); | |
664 | ||
665 | if ((combined_plcp_delta > 0) && | |
666 | ((combined_plcp_delta * 100) / plcp_msec) > | |
667 | priv->cfg->plcp_delta_threshold) { | |
668 | /* | |
669 | * if plcp_err exceed the threshold, the following | |
670 | * data is printed in csv format: | |
671 | * Text: plcp_err exceeded %d, | |
672 | * Received ofdm.plcp_err, | |
673 | * Current ofdm.plcp_err, | |
674 | * Received ofdm_ht.plcp_err, | |
675 | * Current ofdm_ht.plcp_err, | |
676 | * combined_plcp_delta, | |
677 | * plcp_msec | |
678 | */ | |
679 | IWL_DEBUG_RADIO(priv, PLCP_MSG, | |
680 | priv->cfg->plcp_delta_threshold, | |
681 | le32_to_cpu(pkt->u.stats.rx.ofdm.plcp_err), | |
682 | le32_to_cpu(priv->statistics.rx.ofdm.plcp_err), | |
683 | le32_to_cpu(pkt->u.stats.rx.ofdm_ht.plcp_err), | |
684 | le32_to_cpu( | |
685 | priv->statistics.rx.ofdm_ht.plcp_err), | |
686 | combined_plcp_delta, plcp_msec); | |
687 | ||
688 | /* | |
689 | * Reset the RF radio due to the high plcp | |
690 | * error rate | |
691 | */ | |
a93e7973 | 692 | iwl_force_reset(priv, IWL_RF_RESET); |
3e4fb5fa TAN |
693 | } |
694 | } | |
695 | ||
8f91aecb EG |
696 | memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics)); |
697 | ||
698 | set_bit(STATUS_STATISTICS, &priv->status); | |
699 | ||
700 | /* Reschedule the statistics timer to occur in | |
701 | * REG_RECALIB_PERIOD seconds to ensure we get a | |
702 | * thermal update even if the uCode doesn't give | |
703 | * us one */ | |
704 | mod_timer(&priv->statistics_periodic, jiffies + | |
705 | msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); | |
706 | ||
707 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
708 | (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) { | |
709 | iwl_rx_calc_noise(priv); | |
710 | queue_work(priv->workqueue, &priv->run_time_calib_work); | |
711 | } | |
62161aef WYG |
712 | if (priv->cfg->ops->lib->temp_ops.temperature && change) |
713 | priv->cfg->ops->lib->temp_ops.temperature(priv); | |
8f91aecb EG |
714 | } |
715 | EXPORT_SYMBOL(iwl_rx_statistics); | |
1781a07f | 716 | |
ef8d5529 WYG |
717 | void iwl_reply_statistics(struct iwl_priv *priv, |
718 | struct iwl_rx_mem_buffer *rxb) | |
719 | { | |
720 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
721 | ||
722 | if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) { | |
ef8d5529 WYG |
723 | #ifdef CONFIG_IWLWIFI_DEBUG |
724 | memset(&priv->accum_statistics, 0, | |
725 | sizeof(struct iwl_notif_statistics)); | |
e3ef2164 WYG |
726 | memset(&priv->delta_statistics, 0, |
727 | sizeof(struct iwl_notif_statistics)); | |
728 | memset(&priv->max_delta, 0, | |
729 | sizeof(struct iwl_notif_statistics)); | |
ef8d5529 WYG |
730 | #endif |
731 | IWL_DEBUG_RX(priv, "Statistics have been cleared\n"); | |
732 | } | |
733 | iwl_rx_statistics(priv, rxb); | |
734 | } | |
735 | EXPORT_SYMBOL(iwl_reply_statistics); | |
736 | ||
00e540b3 HD |
737 | /* Calc max signal level (dBm) among 3 possible receivers */ |
738 | static inline int iwl_calc_rssi(struct iwl_priv *priv, | |
739 | struct iwl_rx_phy_res *rx_resp) | |
740 | { | |
741 | return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); | |
742 | } | |
1781a07f | 743 | |
00e540b3 | 744 | #ifdef CONFIG_IWLWIFI_DEBUG |
1781a07f EG |
745 | /** |
746 | * iwl_dbg_report_frame - dump frame to syslog during debug sessions | |
747 | * | |
748 | * You may hack this function to show different aspects of received frames, | |
749 | * including selective frame dumps. | |
00e540b3 HD |
750 | * group100 parameter selects whether to show 1 out of 100 good data frames. |
751 | * All beacon and probe response frames are printed. | |
1781a07f EG |
752 | */ |
753 | static void iwl_dbg_report_frame(struct iwl_priv *priv, | |
00e540b3 | 754 | struct iwl_rx_phy_res *phy_res, u16 length, |
1781a07f EG |
755 | struct ieee80211_hdr *header, int group100) |
756 | { | |
757 | u32 to_us; | |
758 | u32 print_summary = 0; | |
759 | u32 print_dump = 0; /* set to 1 to dump all frames' contents */ | |
760 | u32 hundred = 0; | |
761 | u32 dataframe = 0; | |
762 | __le16 fc; | |
763 | u16 seq_ctl; | |
764 | u16 channel; | |
765 | u16 phy_flags; | |
00e540b3 | 766 | u32 rate_n_flags; |
1781a07f | 767 | u32 tsf_low; |
00e540b3 | 768 | int rssi; |
1781a07f | 769 | |
3d816c77 | 770 | if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX))) |
1781a07f EG |
771 | return; |
772 | ||
773 | /* MAC header */ | |
774 | fc = header->frame_control; | |
775 | seq_ctl = le16_to_cpu(header->seq_ctrl); | |
776 | ||
777 | /* metadata */ | |
00e540b3 HD |
778 | channel = le16_to_cpu(phy_res->channel); |
779 | phy_flags = le16_to_cpu(phy_res->phy_flags); | |
780 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
1781a07f EG |
781 | |
782 | /* signal statistics */ | |
00e540b3 HD |
783 | rssi = iwl_calc_rssi(priv, phy_res); |
784 | tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff; | |
1781a07f EG |
785 | |
786 | to_us = !compare_ether_addr(header->addr1, priv->mac_addr); | |
787 | ||
788 | /* if data frame is to us and all is good, | |
789 | * (optionally) print summary for only 1 out of every 100 */ | |
790 | if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) == | |
791 | cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { | |
792 | dataframe = 1; | |
793 | if (!group100) | |
794 | print_summary = 1; /* print each frame */ | |
795 | else if (priv->framecnt_to_us < 100) { | |
796 | priv->framecnt_to_us++; | |
797 | print_summary = 0; | |
798 | } else { | |
799 | priv->framecnt_to_us = 0; | |
800 | print_summary = 1; | |
801 | hundred = 1; | |
802 | } | |
803 | } else { | |
804 | /* print summary for all other frames */ | |
805 | print_summary = 1; | |
806 | } | |
807 | ||
808 | if (print_summary) { | |
809 | char *title; | |
810 | int rate_idx; | |
811 | u32 bitrate; | |
812 | ||
813 | if (hundred) | |
814 | title = "100Frames"; | |
815 | else if (ieee80211_has_retry(fc)) | |
816 | title = "Retry"; | |
817 | else if (ieee80211_is_assoc_resp(fc)) | |
818 | title = "AscRsp"; | |
819 | else if (ieee80211_is_reassoc_resp(fc)) | |
820 | title = "RasRsp"; | |
821 | else if (ieee80211_is_probe_resp(fc)) { | |
822 | title = "PrbRsp"; | |
823 | print_dump = 1; /* dump frame contents */ | |
824 | } else if (ieee80211_is_beacon(fc)) { | |
825 | title = "Beacon"; | |
826 | print_dump = 1; /* dump frame contents */ | |
827 | } else if (ieee80211_is_atim(fc)) | |
828 | title = "ATIM"; | |
829 | else if (ieee80211_is_auth(fc)) | |
830 | title = "Auth"; | |
831 | else if (ieee80211_is_deauth(fc)) | |
832 | title = "DeAuth"; | |
833 | else if (ieee80211_is_disassoc(fc)) | |
834 | title = "DisAssoc"; | |
835 | else | |
836 | title = "Frame"; | |
837 | ||
00e540b3 HD |
838 | rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags); |
839 | if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) { | |
1781a07f | 840 | bitrate = 0; |
00e540b3 HD |
841 | WARN_ON_ONCE(1); |
842 | } else { | |
1781a07f | 843 | bitrate = iwl_rates[rate_idx].ieee / 2; |
00e540b3 | 844 | } |
1781a07f EG |
845 | |
846 | /* print frame summary. | |
847 | * MAC addresses show just the last byte (for brevity), | |
848 | * but you can hack it to show more, if you'd like to. */ | |
849 | if (dataframe) | |
e1623446 | 850 | IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, " |
1781a07f EG |
851 | "len=%u, rssi=%d, chnl=%d, rate=%u, \n", |
852 | title, le16_to_cpu(fc), header->addr1[5], | |
853 | length, rssi, channel, bitrate); | |
854 | else { | |
855 | /* src/dst addresses assume managed mode */ | |
e1623446 | 856 | IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, " |
00e540b3 | 857 | "len=%u, rssi=%d, tim=%lu usec, " |
1781a07f EG |
858 | "phy=0x%02x, chnl=%d\n", |
859 | title, le16_to_cpu(fc), header->addr1[5], | |
00e540b3 | 860 | header->addr3[5], length, rssi, |
1781a07f EG |
861 | tsf_low - priv->scan_start_tsf, |
862 | phy_flags, channel); | |
863 | } | |
864 | } | |
865 | if (print_dump) | |
3d816c77 | 866 | iwl_print_hex_dump(priv, IWL_DL_RX, header, length); |
1781a07f | 867 | } |
1781a07f EG |
868 | #endif |
869 | ||
1781a07f EG |
870 | /* |
871 | * returns non-zero if packet should be dropped | |
872 | */ | |
8ccde88a SO |
873 | int iwl_set_decrypted_flag(struct iwl_priv *priv, |
874 | struct ieee80211_hdr *hdr, | |
875 | u32 decrypt_res, | |
876 | struct ieee80211_rx_status *stats) | |
1781a07f EG |
877 | { |
878 | u16 fc = le16_to_cpu(hdr->frame_control); | |
879 | ||
880 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
881 | return 0; | |
882 | ||
883 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
884 | return 0; | |
885 | ||
e1623446 | 886 | IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res); |
1781a07f EG |
887 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { |
888 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
889 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
890 | * Decryption will be done in SW. */ | |
891 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
892 | RX_RES_STATUS_BAD_KEY_TTAK) | |
893 | break; | |
894 | ||
895 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
896 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
897 | RX_RES_STATUS_BAD_ICV_MIC) { | |
898 | /* bad ICV, the packet is destroyed since the | |
899 | * decryption is inplace, drop it */ | |
e1623446 | 900 | IWL_DEBUG_RX(priv, "Packet destroyed\n"); |
1781a07f EG |
901 | return -1; |
902 | } | |
903 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
904 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
905 | RX_RES_STATUS_DECRYPT_OK) { | |
e1623446 | 906 | IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n"); |
1781a07f EG |
907 | stats->flag |= RX_FLAG_DECRYPTED; |
908 | } | |
909 | break; | |
910 | ||
911 | default: | |
912 | break; | |
913 | } | |
914 | return 0; | |
915 | } | |
8ccde88a | 916 | EXPORT_SYMBOL(iwl_set_decrypted_flag); |
1781a07f EG |
917 | |
918 | static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in) | |
919 | { | |
920 | u32 decrypt_out = 0; | |
921 | ||
922 | if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == | |
923 | RX_RES_STATUS_STATION_FOUND) | |
924 | decrypt_out |= (RX_RES_STATUS_STATION_FOUND | | |
925 | RX_RES_STATUS_NO_STATION_INFO_MISMATCH); | |
926 | ||
927 | decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); | |
928 | ||
929 | /* packet was not encrypted */ | |
930 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
931 | RX_RES_STATUS_SEC_TYPE_NONE) | |
932 | return decrypt_out; | |
933 | ||
934 | /* packet was encrypted with unknown alg */ | |
935 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
936 | RX_RES_STATUS_SEC_TYPE_ERR) | |
937 | return decrypt_out; | |
938 | ||
939 | /* decryption was not done in HW */ | |
940 | if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != | |
941 | RX_MPDU_RES_STATUS_DEC_DONE_MSK) | |
942 | return decrypt_out; | |
943 | ||
944 | switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { | |
945 | ||
946 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
947 | /* alg is CCM: check MIC only */ | |
948 | if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) | |
949 | /* Bad MIC */ | |
950 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
951 | else | |
952 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
953 | ||
954 | break; | |
955 | ||
956 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
957 | if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { | |
958 | /* Bad TTAK */ | |
959 | decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; | |
960 | break; | |
961 | } | |
962 | /* fall through if TTAK OK */ | |
963 | default: | |
964 | if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) | |
965 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
966 | else | |
967 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
968 | break; | |
969 | }; | |
970 | ||
e1623446 | 971 | IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n", |
1781a07f EG |
972 | decrypt_in, decrypt_out); |
973 | ||
974 | return decrypt_out; | |
975 | } | |
976 | ||
4b8817b2 | 977 | static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, |
9f30e04e DH |
978 | struct ieee80211_hdr *hdr, |
979 | u16 len, | |
980 | u32 ampdu_status, | |
981 | struct iwl_rx_mem_buffer *rxb, | |
982 | struct ieee80211_rx_status *stats) | |
1781a07f | 983 | { |
2f301227 ZY |
984 | struct sk_buff *skb; |
985 | int ret = 0; | |
29b1b268 | 986 | __le16 fc = hdr->frame_control; |
2f301227 | 987 | |
1781a07f EG |
988 | /* We only process data packets if the interface is open */ |
989 | if (unlikely(!priv->is_open)) { | |
e1623446 TW |
990 | IWL_DEBUG_DROP_LIMIT(priv, |
991 | "Dropping packet while interface is not open.\n"); | |
1781a07f EG |
992 | return; |
993 | } | |
994 | ||
9f30e04e | 995 | /* In case of HW accelerated crypto and bad decryption, drop */ |
90e8e424 | 996 | if (!priv->cfg->mod_params->sw_crypto && |
1781a07f EG |
997 | iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats)) |
998 | return; | |
999 | ||
a3b6bd5b | 1000 | skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC); |
2f301227 ZY |
1001 | if (!skb) { |
1002 | IWL_ERR(priv, "alloc_skb failed\n"); | |
1003 | return; | |
1004 | } | |
1005 | ||
a3b6bd5b | 1006 | skb_reserve(skb, IWL_LINK_HDR_MAX); |
2f301227 ZY |
1007 | skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len); |
1008 | ||
1009 | /* mac80211 currently doesn't support paged SKB. Convert it to | |
1010 | * linear SKB for management frame and data frame requires | |
1011 | * software decryption or software defragementation. */ | |
29b1b268 ZY |
1012 | if (ieee80211_is_mgmt(fc) || |
1013 | ieee80211_has_protected(fc) || | |
1014 | ieee80211_has_morefrags(fc) || | |
2f301227 ZY |
1015 | le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) |
1016 | ret = skb_linearize(skb); | |
1017 | else | |
1018 | ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ? | |
1019 | 0 : -ENOMEM; | |
1020 | ||
1021 | if (ret) { | |
1022 | kfree_skb(skb); | |
1023 | goto out; | |
1024 | } | |
9f30e04e | 1025 | |
29b1b268 ZY |
1026 | /* |
1027 | * XXX: We cannot touch the page and its virtual memory (hdr) after | |
1028 | * here. It might have already been freed by the above skb change. | |
1029 | */ | |
1030 | ||
1031 | iwl_update_stats(priv, false, fc, len); | |
2f301227 ZY |
1032 | memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); |
1033 | ||
1034 | ieee80211_rx(priv->hw, skb); | |
1035 | out: | |
1036 | priv->alloc_rxb_page--; | |
1037 | rxb->page = NULL; | |
1781a07f EG |
1038 | } |
1039 | ||
4b8817b2 | 1040 | /* This is necessary only for a number of statistics, see the caller. */ |
1781a07f EG |
1041 | static int iwl_is_network_packet(struct iwl_priv *priv, |
1042 | struct ieee80211_hdr *header) | |
1043 | { | |
1044 | /* Filter incoming packets to determine if they are targeted toward | |
1045 | * this network, discarding packets coming from ourselves */ | |
1046 | switch (priv->iw_mode) { | |
05c914fe | 1047 | case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ |
4b8817b2 EG |
1048 | /* packets to our IBSS update information */ |
1049 | return !compare_ether_addr(header->addr3, priv->bssid); | |
05c914fe | 1050 | case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ |
4b8817b2 EG |
1051 | /* packets to our IBSS update information */ |
1052 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1781a07f | 1053 | default: |
4b8817b2 | 1054 | return 1; |
1781a07f | 1055 | } |
1781a07f EG |
1056 | } |
1057 | ||
1058 | /* Called for REPLY_RX (legacy ABG frames), or | |
1059 | * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ | |
1060 | void iwl_rx_reply_rx(struct iwl_priv *priv, | |
1061 | struct iwl_rx_mem_buffer *rxb) | |
1062 | { | |
1063 | struct ieee80211_hdr *header; | |
1064 | struct ieee80211_rx_status rx_status; | |
2f301227 | 1065 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
9f30e04e DH |
1066 | struct iwl_rx_phy_res *phy_res; |
1067 | __le32 rx_pkt_status; | |
1068 | struct iwl4965_rx_mpdu_res_start *amsdu; | |
1069 | u32 len; | |
1070 | u32 ampdu_status; | |
c5f8cdb7 | 1071 | u32 rate_n_flags; |
1781a07f | 1072 | |
9f30e04e DH |
1073 | /** |
1074 | * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently. | |
1075 | * REPLY_RX: physical layer info is in this buffer | |
1076 | * REPLY_RX_MPDU_CMD: physical layer info was sent in separate | |
1077 | * command and cached in priv->last_phy_res | |
1078 | * | |
1079 | * Here we set up local variables depending on which command is | |
1080 | * received. | |
1081 | */ | |
1082 | if (pkt->hdr.cmd == REPLY_RX) { | |
1083 | phy_res = (struct iwl_rx_phy_res *)pkt->u.raw; | |
1084 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) | |
1085 | + phy_res->cfg_phy_cnt); | |
1086 | ||
1087 | len = le16_to_cpu(phy_res->byte_count); | |
1088 | rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) + | |
1089 | phy_res->cfg_phy_cnt + len); | |
1090 | ampdu_status = le32_to_cpu(rx_pkt_status); | |
1091 | } else { | |
1092 | if (!priv->last_phy_res[0]) { | |
1093 | IWL_ERR(priv, "MPDU frame without cached PHY data\n"); | |
1094 | return; | |
1095 | } | |
1096 | phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; | |
1097 | amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
1098 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); | |
1099 | len = le16_to_cpu(amsdu->byte_count); | |
1100 | rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len); | |
1101 | ampdu_status = iwl_translate_rx_status(priv, | |
1102 | le32_to_cpu(rx_pkt_status)); | |
1103 | } | |
1104 | ||
1105 | if ((unlikely(phy_res->cfg_phy_cnt > 20))) { | |
1106 | IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n", | |
1107 | phy_res->cfg_phy_cnt); | |
1108 | return; | |
1109 | } | |
1110 | ||
1111 | if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || | |
1112 | !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
1113 | IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", | |
1114 | le32_to_cpu(rx_pkt_status)); | |
1115 | return; | |
1116 | } | |
1117 | ||
31513be8 DH |
1118 | /* This will be used in several places later */ |
1119 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
1120 | ||
9f30e04e DH |
1121 | /* rx_status carries information about the packet to mac80211 */ |
1122 | rx_status.mactime = le64_to_cpu(phy_res->timestamp); | |
1781a07f | 1123 | rx_status.freq = |
9f30e04e DH |
1124 | ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel)); |
1125 | rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? | |
1781a07f EG |
1126 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
1127 | rx_status.rate_idx = | |
31513be8 | 1128 | iwl_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); |
1781a07f | 1129 | rx_status.flag = 0; |
b94d8eea AK |
1130 | |
1131 | /* TSF isn't reliable. In order to allow smooth user experience, | |
1132 | * this W/A doesn't propagate it to the mac80211 */ | |
1133 | /*rx_status.flag |= RX_FLAG_TSFT;*/ | |
1781a07f | 1134 | |
9f30e04e | 1135 | priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); |
1781a07f EG |
1136 | |
1137 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ | |
9f30e04e | 1138 | rx_status.signal = iwl_calc_rssi(priv, phy_res); |
1781a07f EG |
1139 | |
1140 | /* Meaningful noise values are available only from beacon statistics, | |
1141 | * which are gathered only when associated, and indicate noise | |
1142 | * only for the associated network channel ... | |
1143 | * Ignore these noise values while scanning (other channels) */ | |
1144 | if (iwl_is_associated(priv) && | |
1145 | !test_bit(STATUS_SCANNING, &priv->status)) { | |
1146 | rx_status.noise = priv->last_rx_noise; | |
1781a07f EG |
1147 | } else { |
1148 | rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1781a07f EG |
1149 | } |
1150 | ||
1151 | /* Reset beacon noise level if not associated. */ | |
1152 | if (!iwl_is_associated(priv)) | |
1153 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1154 | ||
21a49fc6 | 1155 | #ifdef CONFIG_IWLWIFI_DEBUG |
9f30e04e | 1156 | /* Set "1" to report good data frames in groups of 100 */ |
3d816c77 | 1157 | if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX)) |
9f30e04e | 1158 | iwl_dbg_report_frame(priv, phy_res, len, header, 1); |
21a49fc6 | 1159 | #endif |
20594eb0 | 1160 | iwl_dbg_log_rx_data_frame(priv, len, header); |
671adc93 JB |
1161 | IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, TSF %llu\n", |
1162 | rx_status.signal, rx_status.noise, | |
1781a07f EG |
1163 | (unsigned long long)rx_status.mactime); |
1164 | ||
6f0a2c4d BR |
1165 | /* |
1166 | * "antenna number" | |
1167 | * | |
1168 | * It seems that the antenna field in the phy flags value | |
a96a27f9 | 1169 | * is actually a bit field. This is undefined by radiotap, |
6f0a2c4d BR |
1170 | * it wants an actual antenna number but I always get "7" |
1171 | * for most legacy frames I receive indicating that the | |
1172 | * same frame was received on all three RX chains. | |
1173 | * | |
a96a27f9 | 1174 | * I think this field should be removed in favor of a |
6f0a2c4d BR |
1175 | * new 802.11n radiotap field "RX chains" that is defined |
1176 | * as a bitmask. | |
1177 | */ | |
9f30e04e | 1178 | rx_status.antenna = |
9024adf5 | 1179 | (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) |
9f30e04e | 1180 | >> RX_RES_PHY_FLAGS_ANTENNA_POS; |
6f0a2c4d BR |
1181 | |
1182 | /* set the preamble flag if appropriate */ | |
9f30e04e | 1183 | if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) |
6f0a2c4d BR |
1184 | rx_status.flag |= RX_FLAG_SHORTPRE; |
1185 | ||
c5f8cdb7 | 1186 | /* Set up the HT phy flags */ |
c5f8cdb7 DH |
1187 | if (rate_n_flags & RATE_MCS_HT_MSK) |
1188 | rx_status.flag |= RX_FLAG_HT; | |
1189 | if (rate_n_flags & RATE_MCS_HT40_MSK) | |
1190 | rx_status.flag |= RX_FLAG_40MHZ; | |
1191 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
1192 | rx_status.flag |= RX_FLAG_SHORT_GI; | |
1193 | ||
9f30e04e | 1194 | if (iwl_is_network_packet(priv, header)) { |
1781a07f EG |
1195 | priv->last_rx_rssi = rx_status.signal; |
1196 | priv->last_beacon_time = priv->ucode_beacon_time; | |
9f30e04e | 1197 | priv->last_tsf = le64_to_cpu(phy_res->timestamp); |
1781a07f EG |
1198 | } |
1199 | ||
6ab10ff8 JB |
1200 | iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status, |
1201 | rxb, &rx_status); | |
1781a07f EG |
1202 | } |
1203 | EXPORT_SYMBOL(iwl_rx_reply_rx); | |
1204 | ||
1205 | /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). | |
1206 | * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ | |
1207 | void iwl_rx_reply_rx_phy(struct iwl_priv *priv, | |
1208 | struct iwl_rx_mem_buffer *rxb) | |
1209 | { | |
2f301227 | 1210 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
1781a07f EG |
1211 | priv->last_phy_res[0] = 1; |
1212 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | |
caab8f1a | 1213 | sizeof(struct iwl_rx_phy_res)); |
1781a07f EG |
1214 | } |
1215 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); |