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a55360e4 TW |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
1781a07f | 30 | #include <linux/etherdevice.h> |
a55360e4 | 31 | #include <net/mac80211.h> |
a05ffd39 | 32 | #include <asm/unaligned.h> |
a55360e4 TW |
33 | #include "iwl-eeprom.h" |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
c1354754 | 38 | #include "iwl-calib.h" |
a55360e4 TW |
39 | #include "iwl-helpers.h" |
40 | /************************** RX-FUNCTIONS ****************************/ | |
41 | /* | |
42 | * Rx theory of operation | |
43 | * | |
44 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
45 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
46 | * used not only for Rx frames, but for any command response or notification | |
47 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
48 | * of indexes into the circular buffer. | |
49 | * | |
50 | * Rx Queue Indexes | |
51 | * The host/firmware share two index registers for managing the Rx buffers. | |
52 | * | |
53 | * The READ index maps to the first position that the firmware may be writing | |
54 | * to -- the driver can read up to (but not including) this position and get | |
55 | * good data. | |
56 | * The READ index is managed by the firmware once the card is enabled. | |
57 | * | |
58 | * The WRITE index maps to the last position the driver has read from -- the | |
59 | * position preceding WRITE is the last slot the firmware can place a packet. | |
60 | * | |
61 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
62 | * WRITE = READ. | |
63 | * | |
64 | * During initialization, the host sets up the READ queue position to the first | |
65 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
66 | * | |
67 | * When the firmware places a packet in a buffer, it will advance the READ index | |
68 | * and fire the RX interrupt. The driver can then query the READ index and | |
69 | * process as many packets as possible, moving the WRITE index forward as it | |
70 | * resets the Rx queue buffers with new memory. | |
71 | * | |
72 | * The management in the driver is as follows: | |
73 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
74 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
75 | * to replenish the iwl->rxq->rx_free. | |
76 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
77 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
78 | * 'processed' and 'read' driver indexes as well) | |
79 | * + A received packet is processed and handed to the kernel network stack, | |
80 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
81 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
82 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
83 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
84 | * were enough free buffers and RX_STALLED is set it is cleared. | |
85 | * | |
86 | * | |
87 | * Driver sequence: | |
88 | * | |
89 | * iwl_rx_queue_alloc() Allocates rx_free | |
90 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
91 | * iwl_rx_queue_restock | |
92 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
93 | * queue, updates firmware pointers, and updates | |
94 | * the WRITE index. If insufficient rx_free buffers | |
95 | * are available, schedules iwl_rx_replenish | |
96 | * | |
97 | * -- enable interrupts -- | |
98 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
99 | * READ INDEX, detaching the SKB from the pool. | |
100 | * Moves the packet buffer from queue to rx_used. | |
101 | * Calls iwl_rx_queue_restock to refill any empty | |
102 | * slots. | |
103 | * ... | |
104 | * | |
105 | */ | |
106 | ||
107 | /** | |
108 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
109 | */ | |
110 | int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
111 | { | |
112 | int s = q->read - q->write; | |
113 | if (s <= 0) | |
114 | s += RX_QUEUE_SIZE; | |
115 | /* keep some buffer to not confuse full and empty queue */ | |
116 | s -= 2; | |
117 | if (s < 0) | |
118 | s = 0; | |
119 | return s; | |
120 | } | |
121 | EXPORT_SYMBOL(iwl_rx_queue_space); | |
122 | ||
123 | /** | |
124 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
125 | */ | |
126 | int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q) | |
127 | { | |
128 | u32 reg = 0; | |
129 | int ret = 0; | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&q->lock, flags); | |
133 | ||
134 | if (q->need_update == 0) | |
135 | goto exit_unlock; | |
136 | ||
137 | /* If power-saving is in use, make sure device is awake */ | |
138 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
139 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
140 | ||
141 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
142 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
143 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
144 | goto exit_unlock; | |
145 | } | |
146 | ||
147 | ret = iwl_grab_nic_access(priv); | |
148 | if (ret) | |
149 | goto exit_unlock; | |
150 | ||
151 | /* Device expects a multiple of 8 */ | |
152 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, | |
153 | q->write & ~0x7); | |
154 | iwl_release_nic_access(priv); | |
155 | ||
156 | /* Else device is assumed to be awake */ | |
157 | } else | |
158 | /* Device expects a multiple of 8 */ | |
159 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); | |
160 | ||
161 | ||
162 | q->need_update = 0; | |
163 | ||
164 | exit_unlock: | |
165 | spin_unlock_irqrestore(&q->lock, flags); | |
166 | return ret; | |
167 | } | |
168 | EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr); | |
169 | /** | |
170 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
171 | */ | |
172 | static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv, | |
173 | dma_addr_t dma_addr) | |
174 | { | |
175 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
176 | } | |
177 | ||
178 | /** | |
179 | * iwl_rx_queue_restock - refill RX queue from pre-allocated pool | |
180 | * | |
181 | * If there are slots in the RX queue that need to be restocked, | |
182 | * and we have free pre-allocated buffers, fill the ranks as much | |
183 | * as we can, pulling from rx_free. | |
184 | * | |
185 | * This moves the 'write' index forward to catch up with 'processed', and | |
186 | * also updates the memory address in the firmware to reference the new | |
187 | * target buffer. | |
188 | */ | |
189 | int iwl_rx_queue_restock(struct iwl_priv *priv) | |
190 | { | |
191 | struct iwl_rx_queue *rxq = &priv->rxq; | |
192 | struct list_head *element; | |
193 | struct iwl_rx_mem_buffer *rxb; | |
194 | unsigned long flags; | |
195 | int write; | |
196 | int ret = 0; | |
197 | ||
198 | spin_lock_irqsave(&rxq->lock, flags); | |
199 | write = rxq->write & ~0x7; | |
200 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
201 | /* Get next free Rx buffer, remove from free list */ | |
202 | element = rxq->rx_free.next; | |
203 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
204 | list_del(element); | |
205 | ||
206 | /* Point to Rx buffer via next RBD in circular buffer */ | |
4018517a | 207 | rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr); |
a55360e4 TW |
208 | rxq->queue[rxq->write] = rxb; |
209 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
210 | rxq->free_count--; | |
211 | } | |
212 | spin_unlock_irqrestore(&rxq->lock, flags); | |
213 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
214 | * refill it */ | |
215 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
216 | queue_work(priv->workqueue, &priv->rx_replenish); | |
217 | ||
218 | ||
219 | /* If we've added more space for the firmware to place data, tell it. | |
220 | * Increment device's write pointer in multiples of 8. */ | |
e4e58cf8 | 221 | if (write != (rxq->write & ~0x7)) { |
a55360e4 TW |
222 | spin_lock_irqsave(&rxq->lock, flags); |
223 | rxq->need_update = 1; | |
224 | spin_unlock_irqrestore(&rxq->lock, flags); | |
225 | ret = iwl_rx_queue_update_write_ptr(priv, rxq); | |
226 | } | |
227 | ||
228 | return ret; | |
229 | } | |
230 | EXPORT_SYMBOL(iwl_rx_queue_restock); | |
231 | ||
232 | ||
233 | /** | |
234 | * iwl_rx_replenish - Move all used packet from rx_used to rx_free | |
235 | * | |
236 | * When moving to rx_free an SKB is allocated for the slot. | |
237 | * | |
238 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
239 | * This is called as a scheduled work item (except for during initialization) | |
240 | */ | |
241 | void iwl_rx_allocate(struct iwl_priv *priv) | |
242 | { | |
243 | struct iwl_rx_queue *rxq = &priv->rxq; | |
244 | struct list_head *element; | |
245 | struct iwl_rx_mem_buffer *rxb; | |
246 | unsigned long flags; | |
247 | spin_lock_irqsave(&rxq->lock, flags); | |
248 | while (!list_empty(&rxq->rx_used)) { | |
249 | element = rxq->rx_used.next; | |
250 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
251 | ||
252 | /* Alloc a new receive buffer */ | |
4018517a | 253 | rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256, |
a55360e4 TW |
254 | __GFP_NOWARN | GFP_ATOMIC); |
255 | if (!rxb->skb) { | |
256 | if (net_ratelimit()) | |
257 | printk(KERN_CRIT DRV_NAME | |
258 | ": Can not allocate SKB buffers\n"); | |
259 | /* We don't reschedule replenish work here -- we will | |
260 | * call the restock method and if it still needs | |
261 | * more buffers it will schedule replenish */ | |
262 | break; | |
263 | } | |
264 | priv->alloc_rxb_skb++; | |
265 | list_del(element); | |
266 | ||
267 | /* Get physical address of RB/SKB */ | |
4018517a JB |
268 | rxb->real_dma_addr = pci_map_single( |
269 | priv->pci_dev, | |
270 | rxb->skb->data, | |
271 | priv->hw_params.rx_buf_size + 256, | |
272 | PCI_DMA_FROMDEVICE); | |
273 | /* dma address must be no more than 36 bits */ | |
274 | BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36)); | |
275 | /* and also 256 byte aligned! */ | |
276 | rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256); | |
277 | skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr); | |
278 | ||
a55360e4 TW |
279 | list_add_tail(&rxb->list, &rxq->rx_free); |
280 | rxq->free_count++; | |
281 | } | |
282 | spin_unlock_irqrestore(&rxq->lock, flags); | |
283 | } | |
284 | EXPORT_SYMBOL(iwl_rx_allocate); | |
285 | ||
286 | void iwl_rx_replenish(struct iwl_priv *priv) | |
287 | { | |
288 | unsigned long flags; | |
289 | ||
290 | iwl_rx_allocate(priv); | |
291 | ||
292 | spin_lock_irqsave(&priv->lock, flags); | |
293 | iwl_rx_queue_restock(priv); | |
294 | spin_unlock_irqrestore(&priv->lock, flags); | |
295 | } | |
296 | EXPORT_SYMBOL(iwl_rx_replenish); | |
297 | ||
298 | ||
299 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
300 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
301 | * This free routine walks the list of POOL entries and if SKB is set to | |
302 | * non NULL it is unmapped and freed | |
303 | */ | |
304 | void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
305 | { | |
306 | int i; | |
307 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
308 | if (rxq->pool[i].skb != NULL) { | |
309 | pci_unmap_single(priv->pci_dev, | |
4018517a JB |
310 | rxq->pool[i].real_dma_addr, |
311 | priv->hw_params.rx_buf_size + 256, | |
a55360e4 TW |
312 | PCI_DMA_FROMDEVICE); |
313 | dev_kfree_skb(rxq->pool[i].skb); | |
314 | } | |
315 | } | |
316 | ||
317 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
318 | rxq->dma_addr); | |
8d86422a WT |
319 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), |
320 | rxq->rb_stts, rxq->rb_stts_dma); | |
a55360e4 | 321 | rxq->bd = NULL; |
8d86422a | 322 | rxq->rb_stts = NULL; |
a55360e4 TW |
323 | } |
324 | EXPORT_SYMBOL(iwl_rx_queue_free); | |
325 | ||
326 | int iwl_rx_queue_alloc(struct iwl_priv *priv) | |
327 | { | |
328 | struct iwl_rx_queue *rxq = &priv->rxq; | |
329 | struct pci_dev *dev = priv->pci_dev; | |
330 | int i; | |
331 | ||
332 | spin_lock_init(&rxq->lock); | |
333 | INIT_LIST_HEAD(&rxq->rx_free); | |
334 | INIT_LIST_HEAD(&rxq->rx_used); | |
335 | ||
336 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
337 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); | |
338 | if (!rxq->bd) | |
8d86422a WT |
339 | goto err_bd; |
340 | ||
341 | rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status), | |
342 | &rxq->rb_stts_dma); | |
343 | if (!rxq->rb_stts) | |
344 | goto err_rb; | |
a55360e4 TW |
345 | |
346 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
347 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
348 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
349 | ||
350 | /* Set us so that we have processed and used all buffers, but have | |
351 | * not restocked the Rx queue with fresh buffers */ | |
352 | rxq->read = rxq->write = 0; | |
353 | rxq->free_count = 0; | |
354 | rxq->need_update = 0; | |
355 | return 0; | |
8d86422a WT |
356 | |
357 | err_rb: | |
358 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
359 | rxq->dma_addr); | |
360 | err_bd: | |
361 | return -ENOMEM; | |
a55360e4 TW |
362 | } |
363 | EXPORT_SYMBOL(iwl_rx_queue_alloc); | |
364 | ||
365 | void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
366 | { | |
367 | unsigned long flags; | |
368 | int i; | |
369 | spin_lock_irqsave(&rxq->lock, flags); | |
370 | INIT_LIST_HEAD(&rxq->rx_free); | |
371 | INIT_LIST_HEAD(&rxq->rx_used); | |
372 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
373 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
374 | /* In the reset function, these buffers may have been allocated | |
375 | * to an SKB, so we need to unmap and free potential storage */ | |
376 | if (rxq->pool[i].skb != NULL) { | |
377 | pci_unmap_single(priv->pci_dev, | |
4018517a JB |
378 | rxq->pool[i].real_dma_addr, |
379 | priv->hw_params.rx_buf_size + 256, | |
a55360e4 TW |
380 | PCI_DMA_FROMDEVICE); |
381 | priv->alloc_rxb_skb--; | |
382 | dev_kfree_skb(rxq->pool[i].skb); | |
383 | rxq->pool[i].skb = NULL; | |
384 | } | |
385 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
386 | } | |
387 | ||
388 | /* Set us so that we have processed and used all buffers, but have | |
389 | * not restocked the Rx queue with fresh buffers */ | |
390 | rxq->read = rxq->write = 0; | |
391 | rxq->free_count = 0; | |
392 | spin_unlock_irqrestore(&rxq->lock, flags); | |
393 | } | |
394 | EXPORT_SYMBOL(iwl_rx_queue_reset); | |
395 | ||
1053d35f RR |
396 | int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
397 | { | |
398 | int ret; | |
399 | unsigned long flags; | |
8cd519e8 WT |
400 | u32 rb_size; |
401 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
402 | const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */ | |
1053d35f RR |
403 | |
404 | spin_lock_irqsave(&priv->lock, flags); | |
405 | ret = iwl_grab_nic_access(priv); | |
406 | if (ret) { | |
407 | spin_unlock_irqrestore(&priv->lock, flags); | |
408 | return ret; | |
409 | } | |
410 | ||
411 | if (priv->cfg->mod_params->amsdu_size_8K) | |
412 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
413 | else | |
414 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
415 | ||
416 | /* Stop Rx DMA */ | |
417 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
418 | ||
419 | /* Reset driver's Rx queue write index */ | |
420 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
421 | ||
422 | /* Tell device where to find RBD circular buffer in DRAM */ | |
423 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
8cd519e8 | 424 | (u32)(rxq->dma_addr >> 8)); |
1053d35f RR |
425 | |
426 | /* Tell device where in DRAM to update its Rx status */ | |
427 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
8d86422a | 428 | rxq->rb_stts_dma >> 4); |
1053d35f | 429 | |
8cd519e8 | 430 | /* Enable Rx DMA |
a96a27f9 | 431 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in |
8cd519e8 WT |
432 | * the credit mechanism in 5000 HW RX FIFO |
433 | * Direct rx interrupts to hosts | |
434 | * Rx buffer size 4 or 8k | |
435 | * RB timeout 0x10 | |
436 | * 256 RBDs | |
437 | */ | |
1053d35f RR |
438 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
439 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
8cd519e8 | 440 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | |
1053d35f | 441 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
e4e58cf8 | 442 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME | |
8cd519e8 WT |
443 | rb_size| |
444 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
445 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
1053d35f RR |
446 | |
447 | iwl_release_nic_access(priv); | |
8cd519e8 WT |
448 | |
449 | iwl_write32(priv, CSR_INT_COALESCING, 0x40); | |
450 | ||
1053d35f RR |
451 | spin_unlock_irqrestore(&priv->lock, flags); |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
b3bbacb7 TW |
456 | int iwl_rxq_stop(struct iwl_priv *priv) |
457 | { | |
458 | int ret; | |
459 | unsigned long flags; | |
460 | ||
461 | spin_lock_irqsave(&priv->lock, flags); | |
462 | ret = iwl_grab_nic_access(priv); | |
463 | if (unlikely(ret)) { | |
464 | spin_unlock_irqrestore(&priv->lock, flags); | |
465 | return ret; | |
466 | } | |
467 | ||
468 | /* stop Rx DMA */ | |
469 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
73d7b5ac ZY |
470 | iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, |
471 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
b3bbacb7 TW |
472 | |
473 | iwl_release_nic_access(priv); | |
474 | spin_unlock_irqrestore(&priv->lock, flags); | |
475 | ||
476 | return 0; | |
477 | } | |
478 | EXPORT_SYMBOL(iwl_rxq_stop); | |
479 | ||
c1354754 TW |
480 | void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, |
481 | struct iwl_rx_mem_buffer *rxb) | |
482 | ||
483 | { | |
c1354754 TW |
484 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
485 | struct iwl4965_missed_beacon_notif *missed_beacon; | |
486 | ||
487 | missed_beacon = &pkt->u.missed_beacon; | |
488 | if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) { | |
489 | IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", | |
490 | le32_to_cpu(missed_beacon->consequtive_missed_beacons), | |
491 | le32_to_cpu(missed_beacon->total_missed_becons), | |
492 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
493 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
494 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
495 | iwl_init_sensitivity(priv); | |
496 | } | |
c1354754 TW |
497 | } |
498 | EXPORT_SYMBOL(iwl_rx_missed_beacon_notif); | |
8f91aecb EG |
499 | |
500 | ||
501 | /* Calculate noise level, based on measurements during network silence just | |
502 | * before arriving beacon. This measurement can be done only if we know | |
503 | * exactly when to expect beacons, therefore only when we're associated. */ | |
504 | static void iwl_rx_calc_noise(struct iwl_priv *priv) | |
505 | { | |
506 | struct statistics_rx_non_phy *rx_info | |
507 | = &(priv->statistics.rx.general); | |
508 | int num_active_rx = 0; | |
509 | int total_silence = 0; | |
510 | int bcn_silence_a = | |
511 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; | |
512 | int bcn_silence_b = | |
513 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; | |
514 | int bcn_silence_c = | |
515 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; | |
516 | ||
517 | if (bcn_silence_a) { | |
518 | total_silence += bcn_silence_a; | |
519 | num_active_rx++; | |
520 | } | |
521 | if (bcn_silence_b) { | |
522 | total_silence += bcn_silence_b; | |
523 | num_active_rx++; | |
524 | } | |
525 | if (bcn_silence_c) { | |
526 | total_silence += bcn_silence_c; | |
527 | num_active_rx++; | |
528 | } | |
529 | ||
530 | /* Average among active antennas */ | |
531 | if (num_active_rx) | |
532 | priv->last_rx_noise = (total_silence / num_active_rx) - 107; | |
533 | else | |
534 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
535 | ||
536 | IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", | |
537 | bcn_silence_a, bcn_silence_b, bcn_silence_c, | |
538 | priv->last_rx_noise); | |
539 | } | |
540 | ||
541 | #define REG_RECALIB_PERIOD (60) | |
542 | ||
543 | void iwl_rx_statistics(struct iwl_priv *priv, | |
544 | struct iwl_rx_mem_buffer *rxb) | |
545 | { | |
5225640b | 546 | int change; |
8f91aecb EG |
547 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
548 | ||
549 | IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", | |
550 | (int)sizeof(priv->statistics), pkt->len); | |
551 | ||
5225640b ZY |
552 | change = ((priv->statistics.general.temperature != |
553 | pkt->u.stats.general.temperature) || | |
554 | ((priv->statistics.flag & | |
555 | STATISTICS_REPLY_FLG_FAT_MODE_MSK) != | |
556 | (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK))); | |
557 | ||
8f91aecb EG |
558 | memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics)); |
559 | ||
560 | set_bit(STATUS_STATISTICS, &priv->status); | |
561 | ||
562 | /* Reschedule the statistics timer to occur in | |
563 | * REG_RECALIB_PERIOD seconds to ensure we get a | |
564 | * thermal update even if the uCode doesn't give | |
565 | * us one */ | |
566 | mod_timer(&priv->statistics_periodic, jiffies + | |
567 | msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); | |
568 | ||
569 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
570 | (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) { | |
571 | iwl_rx_calc_noise(priv); | |
572 | queue_work(priv->workqueue, &priv->run_time_calib_work); | |
573 | } | |
574 | ||
575 | iwl_leds_background(priv); | |
576 | ||
5225640b ZY |
577 | if (priv->cfg->ops->lib->temperature && change) |
578 | priv->cfg->ops->lib->temperature(priv); | |
8f91aecb EG |
579 | } |
580 | EXPORT_SYMBOL(iwl_rx_statistics); | |
1781a07f EG |
581 | |
582 | #define PERFECT_RSSI (-20) /* dBm */ | |
583 | #define WORST_RSSI (-95) /* dBm */ | |
584 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
585 | ||
586 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
587 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
588 | * about formulas used below. */ | |
589 | static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm) | |
590 | { | |
591 | int sig_qual; | |
592 | int degradation = PERFECT_RSSI - rssi_dbm; | |
593 | ||
594 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
595 | * as indicator; formula is (signal dbm - noise dbm). | |
596 | * SNR at or above 40 is a great signal (100%). | |
597 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
598 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
599 | if (noise_dbm) { | |
600 | if (rssi_dbm - noise_dbm >= 40) | |
601 | return 100; | |
602 | else if (rssi_dbm < noise_dbm) | |
603 | return 0; | |
604 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
605 | ||
606 | /* Else use just the signal level. | |
607 | * This formula is a least squares fit of data points collected and | |
608 | * compared with a reference system that had a percentage (%) display | |
609 | * for signal quality. */ | |
610 | } else | |
611 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
612 | (15 * RSSI_RANGE + 62 * degradation)) / | |
613 | (RSSI_RANGE * RSSI_RANGE); | |
614 | ||
615 | if (sig_qual > 100) | |
616 | sig_qual = 100; | |
617 | else if (sig_qual < 1) | |
618 | sig_qual = 0; | |
619 | ||
620 | return sig_qual; | |
621 | } | |
622 | ||
00e540b3 HD |
623 | /* Calc max signal level (dBm) among 3 possible receivers */ |
624 | static inline int iwl_calc_rssi(struct iwl_priv *priv, | |
625 | struct iwl_rx_phy_res *rx_resp) | |
626 | { | |
627 | return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); | |
628 | } | |
1781a07f | 629 | |
00e540b3 | 630 | #ifdef CONFIG_IWLWIFI_DEBUG |
1781a07f EG |
631 | /** |
632 | * iwl_dbg_report_frame - dump frame to syslog during debug sessions | |
633 | * | |
634 | * You may hack this function to show different aspects of received frames, | |
635 | * including selective frame dumps. | |
00e540b3 HD |
636 | * group100 parameter selects whether to show 1 out of 100 good data frames. |
637 | * All beacon and probe response frames are printed. | |
1781a07f EG |
638 | */ |
639 | static void iwl_dbg_report_frame(struct iwl_priv *priv, | |
00e540b3 | 640 | struct iwl_rx_phy_res *phy_res, u16 length, |
1781a07f EG |
641 | struct ieee80211_hdr *header, int group100) |
642 | { | |
643 | u32 to_us; | |
644 | u32 print_summary = 0; | |
645 | u32 print_dump = 0; /* set to 1 to dump all frames' contents */ | |
646 | u32 hundred = 0; | |
647 | u32 dataframe = 0; | |
648 | __le16 fc; | |
649 | u16 seq_ctl; | |
650 | u16 channel; | |
651 | u16 phy_flags; | |
00e540b3 | 652 | u32 rate_n_flags; |
1781a07f | 653 | u32 tsf_low; |
00e540b3 | 654 | int rssi; |
1781a07f EG |
655 | |
656 | if (likely(!(priv->debug_level & IWL_DL_RX))) | |
657 | return; | |
658 | ||
659 | /* MAC header */ | |
660 | fc = header->frame_control; | |
661 | seq_ctl = le16_to_cpu(header->seq_ctrl); | |
662 | ||
663 | /* metadata */ | |
00e540b3 HD |
664 | channel = le16_to_cpu(phy_res->channel); |
665 | phy_flags = le16_to_cpu(phy_res->phy_flags); | |
666 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
1781a07f EG |
667 | |
668 | /* signal statistics */ | |
00e540b3 HD |
669 | rssi = iwl_calc_rssi(priv, phy_res); |
670 | tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff; | |
1781a07f EG |
671 | |
672 | to_us = !compare_ether_addr(header->addr1, priv->mac_addr); | |
673 | ||
674 | /* if data frame is to us and all is good, | |
675 | * (optionally) print summary for only 1 out of every 100 */ | |
676 | if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) == | |
677 | cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { | |
678 | dataframe = 1; | |
679 | if (!group100) | |
680 | print_summary = 1; /* print each frame */ | |
681 | else if (priv->framecnt_to_us < 100) { | |
682 | priv->framecnt_to_us++; | |
683 | print_summary = 0; | |
684 | } else { | |
685 | priv->framecnt_to_us = 0; | |
686 | print_summary = 1; | |
687 | hundred = 1; | |
688 | } | |
689 | } else { | |
690 | /* print summary for all other frames */ | |
691 | print_summary = 1; | |
692 | } | |
693 | ||
694 | if (print_summary) { | |
695 | char *title; | |
696 | int rate_idx; | |
697 | u32 bitrate; | |
698 | ||
699 | if (hundred) | |
700 | title = "100Frames"; | |
701 | else if (ieee80211_has_retry(fc)) | |
702 | title = "Retry"; | |
703 | else if (ieee80211_is_assoc_resp(fc)) | |
704 | title = "AscRsp"; | |
705 | else if (ieee80211_is_reassoc_resp(fc)) | |
706 | title = "RasRsp"; | |
707 | else if (ieee80211_is_probe_resp(fc)) { | |
708 | title = "PrbRsp"; | |
709 | print_dump = 1; /* dump frame contents */ | |
710 | } else if (ieee80211_is_beacon(fc)) { | |
711 | title = "Beacon"; | |
712 | print_dump = 1; /* dump frame contents */ | |
713 | } else if (ieee80211_is_atim(fc)) | |
714 | title = "ATIM"; | |
715 | else if (ieee80211_is_auth(fc)) | |
716 | title = "Auth"; | |
717 | else if (ieee80211_is_deauth(fc)) | |
718 | title = "DeAuth"; | |
719 | else if (ieee80211_is_disassoc(fc)) | |
720 | title = "DisAssoc"; | |
721 | else | |
722 | title = "Frame"; | |
723 | ||
00e540b3 HD |
724 | rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags); |
725 | if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) { | |
1781a07f | 726 | bitrate = 0; |
00e540b3 HD |
727 | WARN_ON_ONCE(1); |
728 | } else { | |
1781a07f | 729 | bitrate = iwl_rates[rate_idx].ieee / 2; |
00e540b3 | 730 | } |
1781a07f EG |
731 | |
732 | /* print frame summary. | |
733 | * MAC addresses show just the last byte (for brevity), | |
734 | * but you can hack it to show more, if you'd like to. */ | |
735 | if (dataframe) | |
736 | IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, " | |
737 | "len=%u, rssi=%d, chnl=%d, rate=%u, \n", | |
738 | title, le16_to_cpu(fc), header->addr1[5], | |
739 | length, rssi, channel, bitrate); | |
740 | else { | |
741 | /* src/dst addresses assume managed mode */ | |
00e540b3 HD |
742 | IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, src=0x%02x, " |
743 | "len=%u, rssi=%d, tim=%lu usec, " | |
1781a07f EG |
744 | "phy=0x%02x, chnl=%d\n", |
745 | title, le16_to_cpu(fc), header->addr1[5], | |
00e540b3 | 746 | header->addr3[5], length, rssi, |
1781a07f EG |
747 | tsf_low - priv->scan_start_tsf, |
748 | phy_flags, channel); | |
749 | } | |
750 | } | |
751 | if (print_dump) | |
00e540b3 | 752 | iwl_print_hex_dump(priv, IWL_DL_RX, header, length); |
1781a07f EG |
753 | } |
754 | #else | |
00e540b3 HD |
755 | static void iwl_dbg_report_frame(struct iwl_priv *priv, |
756 | struct iwl_rx_phy_res *phy_res, u16 length, | |
757 | struct ieee80211_hdr *header, int group100) | |
1781a07f EG |
758 | { |
759 | } | |
760 | #endif | |
761 | ||
1781a07f EG |
762 | static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len) |
763 | { | |
764 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
765 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
766 | priv->rx_stats[idx].cnt++; | |
767 | priv->rx_stats[idx].bytes += len; | |
768 | } | |
769 | ||
770 | /* | |
771 | * returns non-zero if packet should be dropped | |
772 | */ | |
773 | static int iwl_set_decrypted_flag(struct iwl_priv *priv, | |
774 | struct ieee80211_hdr *hdr, | |
775 | u32 decrypt_res, | |
776 | struct ieee80211_rx_status *stats) | |
777 | { | |
778 | u16 fc = le16_to_cpu(hdr->frame_control); | |
779 | ||
780 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
781 | return 0; | |
782 | ||
783 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
784 | return 0; | |
785 | ||
786 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
787 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
788 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
789 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
790 | * Decryption will be done in SW. */ | |
791 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
792 | RX_RES_STATUS_BAD_KEY_TTAK) | |
793 | break; | |
794 | ||
795 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
796 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
797 | RX_RES_STATUS_BAD_ICV_MIC) { | |
798 | /* bad ICV, the packet is destroyed since the | |
799 | * decryption is inplace, drop it */ | |
800 | IWL_DEBUG_RX("Packet destroyed\n"); | |
801 | return -1; | |
802 | } | |
803 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
804 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
805 | RX_RES_STATUS_DECRYPT_OK) { | |
806 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
807 | stats->flag |= RX_FLAG_DECRYPTED; | |
808 | } | |
809 | break; | |
810 | ||
811 | default: | |
812 | break; | |
813 | } | |
814 | return 0; | |
815 | } | |
816 | ||
817 | static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in) | |
818 | { | |
819 | u32 decrypt_out = 0; | |
820 | ||
821 | if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == | |
822 | RX_RES_STATUS_STATION_FOUND) | |
823 | decrypt_out |= (RX_RES_STATUS_STATION_FOUND | | |
824 | RX_RES_STATUS_NO_STATION_INFO_MISMATCH); | |
825 | ||
826 | decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); | |
827 | ||
828 | /* packet was not encrypted */ | |
829 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
830 | RX_RES_STATUS_SEC_TYPE_NONE) | |
831 | return decrypt_out; | |
832 | ||
833 | /* packet was encrypted with unknown alg */ | |
834 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
835 | RX_RES_STATUS_SEC_TYPE_ERR) | |
836 | return decrypt_out; | |
837 | ||
838 | /* decryption was not done in HW */ | |
839 | if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != | |
840 | RX_MPDU_RES_STATUS_DEC_DONE_MSK) | |
841 | return decrypt_out; | |
842 | ||
843 | switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { | |
844 | ||
845 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
846 | /* alg is CCM: check MIC only */ | |
847 | if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) | |
848 | /* Bad MIC */ | |
849 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
850 | else | |
851 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
852 | ||
853 | break; | |
854 | ||
855 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
856 | if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { | |
857 | /* Bad TTAK */ | |
858 | decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; | |
859 | break; | |
860 | } | |
861 | /* fall through if TTAK OK */ | |
862 | default: | |
863 | if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) | |
864 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
865 | else | |
866 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
867 | break; | |
868 | }; | |
869 | ||
870 | IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", | |
871 | decrypt_in, decrypt_out); | |
872 | ||
873 | return decrypt_out; | |
874 | } | |
875 | ||
4b8817b2 | 876 | static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, |
1781a07f EG |
877 | int include_phy, |
878 | struct iwl_rx_mem_buffer *rxb, | |
879 | struct ieee80211_rx_status *stats) | |
880 | { | |
881 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
caab8f1a TW |
882 | struct iwl_rx_phy_res *rx_start = (include_phy) ? |
883 | (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL; | |
1781a07f EG |
884 | struct ieee80211_hdr *hdr; |
885 | u16 len; | |
886 | __le32 *rx_end; | |
887 | unsigned int skblen; | |
888 | u32 ampdu_status; | |
889 | u32 ampdu_status_legacy; | |
890 | ||
891 | if (!include_phy && priv->last_phy_res[0]) | |
caab8f1a | 892 | rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; |
1781a07f EG |
893 | |
894 | if (!rx_start) { | |
895 | IWL_ERROR("MPDU frame without a PHY data\n"); | |
896 | return; | |
897 | } | |
898 | if (include_phy) { | |
899 | hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] + | |
900 | rx_start->cfg_phy_cnt); | |
901 | ||
902 | len = le16_to_cpu(rx_start->byte_count); | |
903 | ||
caab8f1a TW |
904 | rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] + |
905 | sizeof(struct iwl_rx_phy_res) + | |
1781a07f EG |
906 | rx_start->cfg_phy_cnt + len); |
907 | ||
908 | } else { | |
909 | struct iwl4965_rx_mpdu_res_start *amsdu = | |
910 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
911 | ||
912 | hdr = (struct ieee80211_hdr *)(pkt->u.raw + | |
913 | sizeof(struct iwl4965_rx_mpdu_res_start)); | |
914 | len = le16_to_cpu(amsdu->byte_count); | |
915 | rx_start->byte_count = amsdu->byte_count; | |
916 | rx_end = (__le32 *) (((u8 *) hdr) + len); | |
917 | } | |
1781a07f EG |
918 | |
919 | ampdu_status = le32_to_cpu(*rx_end); | |
920 | skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32); | |
921 | ||
922 | if (!include_phy) { | |
923 | /* New status scheme, need to translate */ | |
924 | ampdu_status_legacy = ampdu_status; | |
925 | ampdu_status = iwl_translate_rx_status(priv, ampdu_status); | |
926 | } | |
927 | ||
928 | /* start from MAC */ | |
929 | skb_reserve(rxb->skb, (void *)hdr - (void *)pkt); | |
930 | skb_put(rxb->skb, len); /* end where data ends */ | |
931 | ||
932 | /* We only process data packets if the interface is open */ | |
933 | if (unlikely(!priv->is_open)) { | |
934 | IWL_DEBUG_DROP_LIMIT | |
935 | ("Dropping packet while interface is not open.\n"); | |
936 | return; | |
937 | } | |
938 | ||
1781a07f EG |
939 | hdr = (struct ieee80211_hdr *)rxb->skb->data; |
940 | ||
941 | /* in case of HW accelerated crypto and bad decryption, drop */ | |
942 | if (!priv->hw_params.sw_crypto && | |
943 | iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats)) | |
944 | return; | |
945 | ||
1781a07f EG |
946 | iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len); |
947 | ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); | |
948 | priv->alloc_rxb_skb--; | |
949 | rxb->skb = NULL; | |
950 | } | |
951 | ||
4b8817b2 | 952 | /* This is necessary only for a number of statistics, see the caller. */ |
1781a07f EG |
953 | static int iwl_is_network_packet(struct iwl_priv *priv, |
954 | struct ieee80211_hdr *header) | |
955 | { | |
956 | /* Filter incoming packets to determine if they are targeted toward | |
957 | * this network, discarding packets coming from ourselves */ | |
958 | switch (priv->iw_mode) { | |
05c914fe | 959 | case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ |
4b8817b2 EG |
960 | /* packets to our IBSS update information */ |
961 | return !compare_ether_addr(header->addr3, priv->bssid); | |
05c914fe | 962 | case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ |
4b8817b2 EG |
963 | /* packets to our IBSS update information */ |
964 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1781a07f | 965 | default: |
4b8817b2 | 966 | return 1; |
1781a07f | 967 | } |
1781a07f EG |
968 | } |
969 | ||
970 | /* Called for REPLY_RX (legacy ABG frames), or | |
971 | * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ | |
972 | void iwl_rx_reply_rx(struct iwl_priv *priv, | |
973 | struct iwl_rx_mem_buffer *rxb) | |
974 | { | |
975 | struct ieee80211_hdr *header; | |
976 | struct ieee80211_rx_status rx_status; | |
977 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
978 | /* Use phy data (Rx signal strength, etc.) contained within | |
979 | * this rx packet for legacy frames, | |
980 | * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */ | |
981 | int include_phy = (pkt->hdr.cmd == REPLY_RX); | |
caab8f1a TW |
982 | struct iwl_rx_phy_res *rx_start = (include_phy) ? |
983 | (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : | |
984 | (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; | |
1781a07f EG |
985 | __le32 *rx_end; |
986 | unsigned int len = 0; | |
987 | u16 fc; | |
988 | u8 network_packet; | |
989 | ||
990 | rx_status.mactime = le64_to_cpu(rx_start->timestamp); | |
991 | rx_status.freq = | |
992 | ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel)); | |
993 | rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? | |
994 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
995 | rx_status.rate_idx = | |
996 | iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags)); | |
997 | if (rx_status.band == IEEE80211_BAND_5GHZ) | |
998 | rx_status.rate_idx -= IWL_FIRST_OFDM_RATE; | |
999 | ||
1781a07f | 1000 | rx_status.flag = 0; |
b94d8eea AK |
1001 | |
1002 | /* TSF isn't reliable. In order to allow smooth user experience, | |
1003 | * this W/A doesn't propagate it to the mac80211 */ | |
1004 | /*rx_status.flag |= RX_FLAG_TSFT;*/ | |
1781a07f EG |
1005 | |
1006 | if ((unlikely(rx_start->cfg_phy_cnt > 20))) { | |
1007 | IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n", | |
1008 | rx_start->cfg_phy_cnt); | |
1009 | return; | |
1010 | } | |
1011 | ||
1012 | if (!include_phy) { | |
1013 | if (priv->last_phy_res[0]) | |
caab8f1a | 1014 | rx_start = (struct iwl_rx_phy_res *) |
1781a07f EG |
1015 | &priv->last_phy_res[1]; |
1016 | else | |
1017 | rx_start = NULL; | |
1018 | } | |
1019 | ||
1020 | if (!rx_start) { | |
1021 | IWL_ERROR("MPDU frame without a PHY data\n"); | |
1022 | return; | |
1023 | } | |
1024 | ||
1025 | if (include_phy) { | |
1026 | header = (struct ieee80211_hdr *)((u8 *) &rx_start[1] | |
1027 | + rx_start->cfg_phy_cnt); | |
1028 | ||
1029 | len = le16_to_cpu(rx_start->byte_count); | |
1030 | rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt + | |
caab8f1a | 1031 | sizeof(struct iwl_rx_phy_res) + len); |
1781a07f EG |
1032 | } else { |
1033 | struct iwl4965_rx_mpdu_res_start *amsdu = | |
1034 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
1035 | ||
1036 | header = (void *)(pkt->u.raw + | |
1037 | sizeof(struct iwl4965_rx_mpdu_res_start)); | |
1038 | len = le16_to_cpu(amsdu->byte_count); | |
1039 | rx_end = (__le32 *) (pkt->u.raw + | |
1040 | sizeof(struct iwl4965_rx_mpdu_res_start) + len); | |
1041 | } | |
1042 | ||
1043 | if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) || | |
1044 | !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
1045 | IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", | |
1046 | le32_to_cpu(*rx_end)); | |
1047 | return; | |
1048 | } | |
1049 | ||
1050 | priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp); | |
1051 | ||
1052 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ | |
1053 | rx_status.signal = iwl_calc_rssi(priv, rx_start); | |
1054 | ||
1055 | /* Meaningful noise values are available only from beacon statistics, | |
1056 | * which are gathered only when associated, and indicate noise | |
1057 | * only for the associated network channel ... | |
1058 | * Ignore these noise values while scanning (other channels) */ | |
1059 | if (iwl_is_associated(priv) && | |
1060 | !test_bit(STATUS_SCANNING, &priv->status)) { | |
1061 | rx_status.noise = priv->last_rx_noise; | |
1062 | rx_status.qual = iwl_calc_sig_qual(rx_status.signal, | |
1063 | rx_status.noise); | |
1064 | } else { | |
1065 | rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1066 | rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0); | |
1067 | } | |
1068 | ||
1069 | /* Reset beacon noise level if not associated. */ | |
1070 | if (!iwl_is_associated(priv)) | |
1071 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1072 | ||
1073 | /* Set "1" to report good data frames in groups of 100 */ | |
00e540b3 HD |
1074 | if (unlikely(priv->debug_level & IWL_DL_RX)) |
1075 | iwl_dbg_report_frame(priv, rx_start, len, header, 1); | |
1781a07f EG |
1076 | |
1077 | IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n", | |
1078 | rx_status.signal, rx_status.noise, rx_status.signal, | |
1079 | (unsigned long long)rx_status.mactime); | |
1080 | ||
6f0a2c4d BR |
1081 | /* |
1082 | * "antenna number" | |
1083 | * | |
1084 | * It seems that the antenna field in the phy flags value | |
a96a27f9 | 1085 | * is actually a bit field. This is undefined by radiotap, |
6f0a2c4d BR |
1086 | * it wants an actual antenna number but I always get "7" |
1087 | * for most legacy frames I receive indicating that the | |
1088 | * same frame was received on all three RX chains. | |
1089 | * | |
a96a27f9 | 1090 | * I think this field should be removed in favor of a |
6f0a2c4d BR |
1091 | * new 802.11n radiotap field "RX chains" that is defined |
1092 | * as a bitmask. | |
1093 | */ | |
1094 | rx_status.antenna = le16_to_cpu(rx_start->phy_flags & | |
1095 | RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4; | |
1096 | ||
1097 | /* set the preamble flag if appropriate */ | |
1098 | if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) | |
1099 | rx_status.flag |= RX_FLAG_SHORTPRE; | |
1100 | ||
4b8817b2 | 1101 | /* Take shortcut when only in monitor mode */ |
05c914fe | 1102 | if (priv->iw_mode == NL80211_IFTYPE_MONITOR) { |
4b8817b2 | 1103 | iwl_pass_packet_to_mac80211(priv, include_phy, |
1781a07f EG |
1104 | rxb, &rx_status); |
1105 | return; | |
1106 | } | |
1107 | ||
1108 | network_packet = iwl_is_network_packet(priv, header); | |
1109 | if (network_packet) { | |
1110 | priv->last_rx_rssi = rx_status.signal; | |
1111 | priv->last_beacon_time = priv->ucode_beacon_time; | |
1112 | priv->last_tsf = le64_to_cpu(rx_start->timestamp); | |
1113 | } | |
1114 | ||
1115 | fc = le16_to_cpu(header->frame_control); | |
1116 | switch (fc & IEEE80211_FCTL_FTYPE) { | |
1117 | case IEEE80211_FTYPE_MGMT: | |
4b8817b2 | 1118 | case IEEE80211_FTYPE_DATA: |
05c914fe | 1119 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
1781a07f EG |
1120 | iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM, |
1121 | header->addr2); | |
4b8817b2 | 1122 | /* fall through */ |
1781a07f | 1123 | default: |
4b8817b2 EG |
1124 | iwl_pass_packet_to_mac80211(priv, include_phy, rxb, |
1125 | &rx_status); | |
1781a07f EG |
1126 | break; |
1127 | ||
1128 | } | |
1129 | } | |
1130 | EXPORT_SYMBOL(iwl_rx_reply_rx); | |
1131 | ||
1132 | /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). | |
1133 | * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ | |
1134 | void iwl_rx_reply_rx_phy(struct iwl_priv *priv, | |
1135 | struct iwl_rx_mem_buffer *rxb) | |
1136 | { | |
1137 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1138 | priv->last_phy_res[0] = 1; | |
1139 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | |
caab8f1a | 1140 | sizeof(struct iwl_rx_phy_res)); |
1781a07f EG |
1141 | } |
1142 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); |