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02a7fa00 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution in the | |
21 | * file called LICENSE. | |
22 | * | |
23 | * Contact Information: | |
24 | * Intel Linux Wireless <ilw@linux.intel.com> | |
25 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | * | |
27 | *****************************************************************************/ | |
83ed9015 EG |
28 | #include <linux/delay.h> |
29 | #include <linux/device.h> | |
02a7fa00 JB |
30 | |
31 | #include "iwl-io.h" | |
83ed9015 EG |
32 | #include"iwl-csr.h" |
33 | #include "iwl-debug.h" | |
02a7fa00 JB |
34 | |
35 | #define IWL_POLL_INTERVAL 10 /* microseconds */ | |
36 | ||
83ed9015 | 37 | static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) |
02a7fa00 | 38 | { |
83ed9015 | 39 | iwl_write32(bus, reg, iwl_read32(bus, reg) | mask); |
02a7fa00 JB |
40 | } |
41 | ||
83ed9015 | 42 | static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) |
02a7fa00 | 43 | { |
83ed9015 | 44 | iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask); |
02a7fa00 JB |
45 | } |
46 | ||
83ed9015 | 47 | void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) |
02a7fa00 JB |
48 | { |
49 | unsigned long flags; | |
50 | ||
83ed9015 EG |
51 | spin_lock_irqsave(&bus->reg_lock, flags); |
52 | __iwl_set_bit(bus, reg, mask); | |
53 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
54 | } |
55 | ||
83ed9015 | 56 | void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) |
02a7fa00 JB |
57 | { |
58 | unsigned long flags; | |
59 | ||
83ed9015 EG |
60 | spin_lock_irqsave(&bus->reg_lock, flags); |
61 | __iwl_clear_bit(bus, reg, mask); | |
62 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
63 | } |
64 | ||
83ed9015 | 65 | int iwl_poll_bit(struct iwl_bus *bus, u32 addr, |
02a7fa00 JB |
66 | u32 bits, u32 mask, int timeout) |
67 | { | |
68 | int t = 0; | |
69 | ||
70 | do { | |
83ed9015 | 71 | if ((iwl_read32(bus, addr) & mask) == (bits & mask)) |
02a7fa00 JB |
72 | return t; |
73 | udelay(IWL_POLL_INTERVAL); | |
74 | t += IWL_POLL_INTERVAL; | |
75 | } while (t < timeout); | |
76 | ||
77 | return -ETIMEDOUT; | |
78 | } | |
79 | ||
83ed9015 | 80 | int iwl_grab_nic_access_silent(struct iwl_bus *bus) |
02a7fa00 JB |
81 | { |
82 | int ret; | |
02a7fa00 | 83 | |
83ed9015 | 84 | lockdep_assert_held(&bus->reg_lock); |
02a7fa00 JB |
85 | |
86 | /* this bit wakes up the NIC */ | |
83ed9015 | 87 | __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
02a7fa00 JB |
88 | |
89 | /* | |
90 | * These bits say the device is running, and should keep running for | |
91 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
92 | * but they do not indicate that embedded SRAM is restored yet; | |
93 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
94 | * to/from host DRAM when sleeping/waking for power-saving. | |
95 | * Each direction takes approximately 1/4 millisecond; with this | |
96 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
97 | * series of register accesses are expected (e.g. reading Event Log), | |
98 | * to keep device from sleeping. | |
99 | * | |
100 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
101 | * SRAM is okay/restored. We don't check that here because this call | |
102 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
103 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
104 | * | |
105 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
106 | * and do not save/restore SRAM when power cycling. | |
107 | */ | |
83ed9015 | 108 | ret = iwl_poll_bit(bus, CSR_GP_CNTRL, |
02a7fa00 JB |
109 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, |
110 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
111 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
112 | if (ret < 0) { | |
83ed9015 | 113 | iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); |
02a7fa00 JB |
114 | return -EIO; |
115 | } | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
83ed9015 | 120 | int iwl_grab_nic_access(struct iwl_bus *bus) |
4119904f | 121 | { |
83ed9015 | 122 | int ret = iwl_grab_nic_access_silent(bus); |
4119904f | 123 | if (ret) { |
83ed9015 EG |
124 | u32 val = iwl_read32(bus, CSR_GP_CNTRL); |
125 | IWL_ERR(bus, | |
4119904f JB |
126 | "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); |
127 | } | |
128 | ||
129 | return ret; | |
130 | } | |
131 | ||
83ed9015 | 132 | void iwl_release_nic_access(struct iwl_bus *bus) |
02a7fa00 | 133 | { |
83ed9015 EG |
134 | lockdep_assert_held(&bus->reg_lock); |
135 | __iwl_clear_bit(bus, CSR_GP_CNTRL, | |
02a7fa00 JB |
136 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
137 | } | |
138 | ||
83ed9015 | 139 | u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg) |
02a7fa00 JB |
140 | { |
141 | u32 value; | |
142 | unsigned long flags; | |
143 | ||
83ed9015 EG |
144 | spin_lock_irqsave(&bus->reg_lock, flags); |
145 | iwl_grab_nic_access(bus); | |
146 | value = iwl_read32(bus(bus), reg); | |
147 | iwl_release_nic_access(bus); | |
148 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
149 | |
150 | return value; | |
151 | } | |
152 | ||
83ed9015 | 153 | void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value) |
02a7fa00 JB |
154 | { |
155 | unsigned long flags; | |
156 | ||
83ed9015 EG |
157 | spin_lock_irqsave(&bus->reg_lock, flags); |
158 | if (!iwl_grab_nic_access(bus)) { | |
159 | iwl_write32(bus, reg, value); | |
160 | iwl_release_nic_access(bus); | |
02a7fa00 | 161 | } |
83ed9015 | 162 | spin_unlock_irqrestore(&bus->reg_lock, flags); |
02a7fa00 JB |
163 | } |
164 | ||
83ed9015 | 165 | int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask, |
02a7fa00 JB |
166 | int timeout) |
167 | { | |
168 | int t = 0; | |
169 | ||
170 | do { | |
83ed9015 | 171 | if ((iwl_read_direct32(bus, addr) & mask) == mask) |
02a7fa00 JB |
172 | return t; |
173 | udelay(IWL_POLL_INTERVAL); | |
174 | t += IWL_POLL_INTERVAL; | |
175 | } while (t < timeout); | |
176 | ||
177 | return -ETIMEDOUT; | |
178 | } | |
179 | ||
83ed9015 | 180 | static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg) |
02a7fa00 | 181 | { |
83ed9015 | 182 | iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); |
02a7fa00 | 183 | rmb(); |
83ed9015 | 184 | return iwl_read32(bus, HBUS_TARG_PRPH_RDAT); |
02a7fa00 JB |
185 | } |
186 | ||
83ed9015 | 187 | static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) |
02a7fa00 | 188 | { |
83ed9015 | 189 | iwl_write32(bus, HBUS_TARG_PRPH_WADDR, |
02a7fa00 JB |
190 | ((addr & 0x0000FFFF) | (3 << 24))); |
191 | wmb(); | |
83ed9015 | 192 | iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val); |
02a7fa00 JB |
193 | } |
194 | ||
83ed9015 | 195 | u32 iwl_read_prph(struct iwl_bus *bus, u32 reg) |
02a7fa00 JB |
196 | { |
197 | unsigned long flags; | |
198 | u32 val; | |
199 | ||
83ed9015 EG |
200 | spin_lock_irqsave(&bus->reg_lock, flags); |
201 | iwl_grab_nic_access(bus); | |
202 | val = __iwl_read_prph(bus, reg); | |
203 | iwl_release_nic_access(bus); | |
204 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
205 | return val; |
206 | } | |
207 | ||
83ed9015 | 208 | void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) |
02a7fa00 JB |
209 | { |
210 | unsigned long flags; | |
211 | ||
83ed9015 EG |
212 | spin_lock_irqsave(&bus->reg_lock, flags); |
213 | if (!iwl_grab_nic_access(bus)) { | |
214 | __iwl_write_prph(bus, addr, val); | |
215 | iwl_release_nic_access(bus); | |
02a7fa00 | 216 | } |
83ed9015 | 217 | spin_unlock_irqrestore(&bus->reg_lock, flags); |
02a7fa00 JB |
218 | } |
219 | ||
83ed9015 | 220 | void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) |
02a7fa00 JB |
221 | { |
222 | unsigned long flags; | |
223 | ||
83ed9015 EG |
224 | spin_lock_irqsave(&bus->reg_lock, flags); |
225 | iwl_grab_nic_access(bus); | |
226 | __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask); | |
227 | iwl_release_nic_access(bus); | |
228 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
229 | } |
230 | ||
83ed9015 | 231 | void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg, |
02a7fa00 JB |
232 | u32 bits, u32 mask) |
233 | { | |
234 | unsigned long flags; | |
235 | ||
83ed9015 EG |
236 | spin_lock_irqsave(&bus->reg_lock, flags); |
237 | iwl_grab_nic_access(bus); | |
238 | __iwl_write_prph(bus, reg, | |
239 | (__iwl_read_prph(bus, reg) & mask) | bits); | |
240 | iwl_release_nic_access(bus); | |
241 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
242 | } |
243 | ||
83ed9015 | 244 | void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) |
02a7fa00 JB |
245 | { |
246 | unsigned long flags; | |
247 | u32 val; | |
248 | ||
83ed9015 EG |
249 | spin_lock_irqsave(&bus->reg_lock, flags); |
250 | iwl_grab_nic_access(bus); | |
251 | val = __iwl_read_prph(bus, reg); | |
252 | __iwl_write_prph(bus, reg, (val & ~mask)); | |
253 | iwl_release_nic_access(bus); | |
254 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
02a7fa00 JB |
255 | } |
256 | ||
83ed9015 | 257 | void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr, |
e46f6538 | 258 | void *buf, int words) |
02a7fa00 JB |
259 | { |
260 | unsigned long flags; | |
e46f6538 JB |
261 | int offs; |
262 | u32 *vals = buf; | |
02a7fa00 | 263 | |
83ed9015 EG |
264 | spin_lock_irqsave(&bus->reg_lock, flags); |
265 | iwl_grab_nic_access(bus); | |
02a7fa00 | 266 | |
83ed9015 | 267 | iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr); |
02a7fa00 | 268 | rmb(); |
e46f6538 JB |
269 | |
270 | for (offs = 0; offs < words; offs++) | |
83ed9015 | 271 | vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT); |
02a7fa00 | 272 | |
83ed9015 EG |
273 | iwl_release_nic_access(bus); |
274 | spin_unlock_irqrestore(&bus->reg_lock, flags); | |
e46f6538 JB |
275 | } |
276 | ||
83ed9015 | 277 | u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr) |
e46f6538 JB |
278 | { |
279 | u32 value; | |
280 | ||
83ed9015 | 281 | _iwl_read_targ_mem_words(bus, addr, &value, 1); |
e46f6538 | 282 | |
02a7fa00 JB |
283 | return value; |
284 | } | |
285 | ||
83ed9015 | 286 | void iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val) |
02a7fa00 JB |
287 | { |
288 | unsigned long flags; | |
289 | ||
83ed9015 EG |
290 | spin_lock_irqsave(&bus->reg_lock, flags); |
291 | if (!iwl_grab_nic_access(bus)) { | |
292 | iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr); | |
02a7fa00 | 293 | wmb(); |
83ed9015 EG |
294 | iwl_write32(bus, HBUS_TARG_MEM_WDAT, val); |
295 | iwl_release_nic_access(bus); | |
02a7fa00 | 296 | } |
83ed9015 | 297 | spin_unlock_irqrestore(&bus->reg_lock, flags); |
02a7fa00 | 298 | } |