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1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
901069c7 | 8 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
4b52c39d EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
759ef89f | 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
4b52c39d EG |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
901069c7 | 33 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
4b52c39d EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
65a0667b TW |
63 | #ifndef __iwl_fh_h__ |
64 | #define __iwl_fh_h__ | |
4b52c39d | 65 | |
a72b8b08 EG |
66 | #include <linux/types.h> |
67 | ||
4b52c39d EG |
68 | /****************************/ |
69 | /* Flow Handler Definitions */ | |
70 | /****************************/ | |
71 | ||
72 | /** | |
73 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) | |
74 | * Addresses are offsets from device's PCI hardware base address. | |
75 | */ | |
76 | #define FH_MEM_LOWER_BOUND (0x1000) | |
e0737a77 | 77 | #define FH_MEM_UPPER_BOUND (0x2000) |
4b52c39d EG |
78 | |
79 | /** | |
80 | * Keep-Warm (KW) buffer base address. | |
81 | * | |
8ff84a2c | 82 | * Driver must allocate a 4KByte buffer that is for keeping the |
4b52c39d | 83 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency |
8ff84a2c | 84 | * DRAM access when doing Txing or Rxing. The dummy accesses prevent host |
4b52c39d EG |
85 | * from going into a power-savings mode that would cause higher DRAM latency, |
86 | * and possible data over/under-runs, before all Tx/Rx is complete. | |
87 | * | |
88 | * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) | |
8ff84a2c | 89 | * of the buffer, which must be 4K aligned. Once this is set up, the device |
4b52c39d EG |
90 | * automatically invokes keep-warm accesses when normal accesses might not |
91 | * be sufficient to maintain fast DRAM response. | |
92 | * | |
93 | * Bit fields: | |
94 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned | |
95 | */ | |
96 | #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) | |
97 | ||
98 | ||
99 | /** | |
100 | * TFD Circular Buffers Base (CBBC) addresses | |
101 | * | |
8ff84a2c | 102 | * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident |
4b52c39d EG |
103 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) |
104 | * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 | |
105 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte | |
106 | * aligned (address bits 0-7 must be 0). | |
107 | * | |
108 | * Bit fields in each pointer register: | |
109 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned | |
110 | */ | |
111 | #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) | |
112 | #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) | |
113 | ||
114 | /* Find TFD CB base pointer for given queue (range 0-15). */ | |
115 | #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) | |
116 | ||
117 | ||
118 | /** | |
119 | * Rx SRAM Control and Status Registers (RSCSR) | |
120 | * | |
8ff84a2c | 121 | * These registers provide handshake between driver and device for the Rx queue |
4b52c39d | 122 | * (this queue handles *all* command responses, notifications, Rx data, etc. |
8ff84a2c | 123 | * sent from uCode to host driver). Unlike Tx, there is only one Rx |
4b52c39d EG |
124 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can |
125 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer | |
126 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 | |
127 | * mapping between RBDs and RBs. | |
128 | * | |
129 | * Driver must allocate host DRAM memory for the following, and set the | |
8ff84a2c | 130 | * physical address of each into device registers: |
4b52c39d EG |
131 | * |
132 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 | |
133 | * entries (although any power of 2, up to 4096, is selectable by driver). | |
134 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size | |
135 | * (typically 4K, although 8K or 16K are also selectable by driver). | |
136 | * Driver sets up RB size and number of RBDs in the CB via Rx config | |
137 | * register FH_MEM_RCSR_CHNL0_CONFIG_REG. | |
138 | * | |
139 | * Bit fields within one RBD: | |
140 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned | |
141 | * | |
142 | * Driver sets physical address [35:8] of base of RBD circular buffer | |
143 | * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. | |
144 | * | |
8ff84a2c | 145 | * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers |
4b52c39d EG |
146 | * (RBs) have been filled, via a "write pointer", actually the index of |
147 | * the RB's corresponding RBD within the circular buffer. Driver sets | |
148 | * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. | |
149 | * | |
150 | * Bit fields in lower dword of Rx status buffer (upper dword not used | |
8ff84a2c | 151 | * by driver: |
4b52c39d EG |
152 | * 31-12: Not used by driver |
153 | * 11- 0: Index of last filled Rx buffer descriptor | |
8ff84a2c | 154 | * (device writes, driver reads this value) |
4b52c39d | 155 | * |
8ff84a2c | 156 | * As the driver prepares Receive Buffers (RBs) for device to fill, driver must |
4b52c39d | 157 | * enter pointers to these RBs into contiguous RBD circular buffer entries, |
8ff84a2c | 158 | * and update the device's "write" index register, |
4b52c39d EG |
159 | * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. |
160 | * | |
161 | * This "write" index corresponds to the *next* RBD that the driver will make | |
162 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within | |
163 | * the circular buffer. This value should initially be 0 (before preparing any | |
164 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must | |
165 | * wrap back to 0 at the end of the circular buffer (but don't wrap before | |
166 | * "read" index has advanced past 1! See below). | |
8ff84a2c | 167 | * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. |
4b52c39d | 168 | * |
8ff84a2c | 169 | * As the device fills RBs (referenced from contiguous RBDs within the circular |
4b52c39d EG |
170 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, |
171 | * to tell the driver the index of the latest filled RBD. The driver must | |
8ff84a2c | 172 | * read this "read" index from DRAM after receiving an Rx interrupt from device |
4b52c39d EG |
173 | * |
174 | * The driver must also internally keep track of a third index, which is the | |
175 | * next RBD to process. When receiving an Rx interrupt, driver should process | |
176 | * all filled but unprocessed RBs up to, but not including, the RB | |
177 | * corresponding to the "read" index. For example, if "read" index becomes "1", | |
178 | * driver may process the RB pointed to by RBD 0. Depending on volume of | |
179 | * traffic, there may be many RBs to process. | |
180 | * | |
8ff84a2c | 181 | * If read index == write index, device thinks there is no room to put new data. |
4b52c39d EG |
182 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To |
183 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" | |
184 | * and "read" indexes; that is, make sure that there are no more than 254 | |
185 | * buffers waiting to be filled. | |
186 | */ | |
187 | #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) | |
188 | #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
189 | #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) | |
190 | ||
191 | /** | |
192 | * Physical base address of 8-byte Rx Status buffer. | |
193 | * Bit fields: | |
194 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. | |
195 | */ | |
196 | #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) | |
197 | ||
198 | /** | |
199 | * Physical base address of Rx Buffer Descriptor Circular Buffer. | |
200 | * Bit fields: | |
201 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. | |
202 | */ | |
203 | #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) | |
204 | ||
205 | /** | |
206 | * Rx write pointer (index, really!). | |
207 | * Bit fields: | |
208 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. | |
209 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. | |
210 | */ | |
211 | #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) | |
212 | #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) | |
213 | ||
214 | ||
215 | /** | |
216 | * Rx Config/Status Registers (RCSR) | |
217 | * Rx Config Reg for channel 0 (only channel used) | |
218 | * | |
219 | * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for | |
220 | * normal operation (see bit fields). | |
221 | * | |
222 | * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. | |
223 | * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for | |
224 | * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. | |
225 | * | |
226 | * Bit fields: | |
227 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
228 | * '10' operate normally | |
229 | * 29-24: reserved | |
230 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), | |
231 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. | |
232 | * 19-18: reserved | |
233 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, | |
234 | * '10' 12K, '11' 16K. | |
235 | * 15-14: reserved | |
236 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) | |
237 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) | |
238 | * typical value 0x10 (about 1/2 msec) | |
239 | * 3- 0: reserved | |
240 | */ | |
241 | #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
242 | #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) | |
243 | #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) | |
244 | ||
245 | #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) | |
246 | ||
247 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ | |
248 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ | |
249 | #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ | |
250 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ | |
251 | #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ | |
252 | #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ | |
253 | ||
8cd519e8 WT |
254 | #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) |
255 | #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) | |
4b52c39d EG |
256 | #define RX_RB_TIMEOUT (0x10) |
257 | ||
258 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) | |
259 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) | |
260 | #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) | |
261 | ||
262 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) | |
263 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) | |
264 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) | |
265 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) | |
266 | ||
8cd519e8 WT |
267 | #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) |
268 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) | |
269 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) | |
4b52c39d | 270 | |
4b52c39d EG |
271 | /** |
272 | * Rx Shared Status Registers (RSSR) | |
273 | * | |
274 | * After stopping Rx DMA channel (writing 0 to | |
275 | * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll | |
276 | * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. | |
277 | * | |
278 | * Bit fields: | |
279 | * 24: 1 = Channel 0 is idle | |
280 | * | |
281 | * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV | |
282 | * contain default values that should not be altered by the driver. | |
283 | */ | |
284 | #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) | |
285 | #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
286 | ||
287 | #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) | |
288 | #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) | |
289 | #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ | |
290 | (FH_MEM_RSSR_LOWER_BOUND + 0x008) | |
291 | ||
292 | #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) | |
293 | ||
f0b9f5cb | 294 | #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 |
4b52c39d | 295 | |
e0737a77 TW |
296 | /* TFDB Area - TFDs buffer table */ |
297 | #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) | |
298 | #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) | |
299 | #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) | |
300 | #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) | |
301 | #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) | |
302 | ||
4b52c39d EG |
303 | /** |
304 | * Transmit DMA Channel Control/Status Registers (TCSR) | |
305 | * | |
8ff84a2c | 306 | * Device has one configuration register for each of 8 Tx DMA/FIFO channels |
4b52c39d EG |
307 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, |
308 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. | |
309 | * | |
310 | * To use a Tx DMA channel, driver must initialize its | |
311 | * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: | |
312 | * | |
313 | * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
314 | * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
315 | * | |
316 | * All other bits should be 0. | |
317 | * | |
318 | * Bit fields: | |
319 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
320 | * '10' operate normally | |
321 | * 29- 4: Reserved, set to "0" | |
322 | * 3: Enable internal DMA requests (1, normal operation), disable (0) | |
323 | * 2- 0: Reserved, set to "0" | |
324 | */ | |
325 | #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
326 | #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) | |
327 | ||
328 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ | |
02f6f659 | 329 | #define FH_TCSR_CHNL_NUM (8) |
4b52c39d | 330 | |
e0737a77 | 331 | /* TCSR: tx_config register values */ |
9c80c502 WT |
332 | #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
333 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) | |
334 | #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ | |
335 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) | |
336 | #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ | |
337 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) | |
4b52c39d | 338 | |
9c80c502 WT |
339 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) |
340 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) | |
4b52c39d | 341 | |
9c80c502 WT |
342 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) |
343 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) | |
4b52c39d | 344 | |
9c80c502 WT |
345 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) |
346 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) | |
347 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
4b52c39d | 348 | |
9c80c502 WT |
349 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) |
350 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) | |
351 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) | |
4b52c39d | 352 | |
9c80c502 WT |
353 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) |
354 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | |
355 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
356 | ||
357 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) | |
358 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) | |
359 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) | |
360 | ||
361 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) | |
362 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) | |
4b52c39d EG |
363 | |
364 | /** | |
365 | * Tx Shared Status Registers (TSSR) | |
366 | * | |
367 | * After stopping Tx DMA channel (writing 0 to | |
368 | * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll | |
369 | * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle | |
370 | * (channel's buffers empty | no pending requests). | |
371 | * | |
372 | * Bit fields: | |
373 | * 31-24: 1 = Channel buffers empty (channel 7:0) | |
374 | * 23-16: 1 = No pending requests (channel 7:0) | |
375 | */ | |
376 | #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) | |
377 | #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) | |
378 | ||
9c80c502 | 379 | #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) |
4b52c39d | 380 | |
1b3eb823 WYG |
381 | /** |
382 | * Bit fields for TSSR(Tx Shared Status & Control) error status register: | |
383 | * 31: Indicates an address error when accessed to internal memory | |
384 | * uCode/driver must write "1" in order to clear this flag | |
385 | * 30: Indicates that Host did not send the expected number of dwords to FH | |
386 | * uCode/driver must write "1" in order to clear this flag | |
387 | * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA | |
388 | * command was received from the scheduler while the TRB was already full | |
389 | * with previous command | |
390 | * uCode/driver must write "1" in order to clear this flag | |
391 | * 7-0: Each status bit indicates a channel's TxCredit error. When an error | |
392 | * bit is set, it indicates that the FH has received a full indication | |
393 | * from the RTC TxFIFO and the current value of the TxCredit counter was | |
394 | * not equal to zero. This mean that the credit mechanism was not | |
395 | * synchronized to the TxFIFO status | |
396 | * uCode/driver must write "1" in order to clear this flag | |
397 | */ | |
398 | #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) | |
399 | ||
9726f347 | 400 | #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) |
4b52c39d | 401 | |
4b52c39d | 402 | /* Tx service channels */ |
e0737a77 TW |
403 | #define FH_SRVC_CHNL (9) |
404 | #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) | |
405 | #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) | |
4b52c39d EG |
406 | #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ |
407 | (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) | |
408 | ||
40fc95d5 WT |
409 | #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) |
410 | /* Instruct FH to increment the retry count of a packet when | |
411 | * it is brought from the memory to TX-FIFO | |
412 | */ | |
413 | #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) | |
127901ab | 414 | |
1e33dc64 WT |
415 | #define RX_QUEUE_SIZE 256 |
416 | #define RX_QUEUE_MASK 255 | |
417 | #define RX_QUEUE_SIZE_LOG 8 | |
418 | ||
419 | /* | |
420 | * RX related structures and functions | |
421 | */ | |
422 | #define RX_FREE_BUFFERS 64 | |
423 | #define RX_LOW_WATERMARK 8 | |
424 | ||
8d86422a WT |
425 | /** |
426 | * struct iwl_rb_status - reseve buffer status | |
427 | * host memory mapped FH registers | |
428 | * @closed_rb_num [0:11] - Indicates the index of the RB which was closed | |
429 | * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed | |
430 | * @finished_rb_num [0:11] - Indicates the index of the current RB | |
431 | * in which the last frame was written to | |
432 | * @finished_fr_num [0:11] - Indicates the index of the RX Frame | |
25985edc | 433 | * which was transferred |
8d86422a WT |
434 | */ |
435 | struct iwl_rb_status { | |
436 | __le16 closed_rb_num; | |
437 | __le16 closed_fr_num; | |
438 | __le16 finished_rb_num; | |
439 | __le16 finished_fr_nam; | |
ab4bf5ef | 440 | __le32 __unused; |
ba2d3587 | 441 | } __packed; |
127901ab | 442 | |
4ddbb7d0 | 443 | |
e0737a77 TW |
444 | #define TFD_QUEUE_SIZE_MAX (256) |
445 | #define TFD_QUEUE_SIZE_BC_DUP (64) | |
446 | #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) | |
4ddbb7d0 | 447 | #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) |
4ddbb7d0 TW |
448 | #define IWL_NUM_OF_TBS 20 |
449 | ||
450 | static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) | |
451 | { | |
452 | return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; | |
453 | } | |
454 | /** | |
455 | * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor | |
456 | * | |
457 | * This structure contains dma address and length of transmission address | |
458 | * | |
459 | * @lo: low [31:0] portion of the dma address of TX buffer | |
460 | * every even is unaligned on 16 bit boundary | |
461 | * @hi_n_len 0-3 [35:32] portion of dma | |
34faf780 | 462 | * 4-15 length of the tx buffer |
4ddbb7d0 TW |
463 | */ |
464 | struct iwl_tfd_tb { | |
465 | __le32 lo; | |
466 | __le16 hi_n_len; | |
ba2d3587 | 467 | } __packed; |
4ddbb7d0 TW |
468 | |
469 | /** | |
470 | * struct iwl_tfd | |
471 | * | |
472 | * Transmit Frame Descriptor (TFD) | |
473 | * | |
474 | * @ __reserved1[3] reserved | |
34faf780 ZY |
475 | * @ num_tbs 0-4 number of active tbs |
476 | * 5 reserved | |
4ddbb7d0 TW |
477 | * 6-7 padding (not used) |
478 | * @ tbs[20] transmit frame buffer descriptors | |
479 | * @ __pad padding | |
480 | * | |
481 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. | |
482 | * Both driver and device share these circular buffers, each of which must be | |
483 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes | |
484 | * | |
485 | * Driver must indicate the physical address of the base of each | |
486 | * circular buffer via the FH_MEM_CBBC_QUEUE registers. | |
487 | * | |
488 | * Each TFD contains pointer/size information for up to 20 data buffers | |
489 | * in host DRAM. These buffers collectively contain the (one) frame described | |
490 | * by the TFD. Each buffer must be a single contiguous block of memory within | |
491 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size | |
492 | * of (4K - 4). The concatenates all of a TFD's buffers into a single | |
493 | * Tx frame, up to 8 KBytes in size. | |
494 | * | |
495 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. | |
4ddbb7d0 TW |
496 | */ |
497 | struct iwl_tfd { | |
498 | u8 __reserved1[3]; | |
499 | u8 num_tbs; | |
500 | struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; | |
501 | __le32 __pad; | |
ba2d3587 | 502 | } __packed; |
4ddbb7d0 | 503 | |
4ddbb7d0 | 504 | /* Keep Warm Size */ |
34faf780 | 505 | #define IWL_KW_SIZE 0x1000 /* 4k */ |
4ddbb7d0 | 506 | |
dda61a44 EG |
507 | /* Fixed (non-configurable) rx data from phy */ |
508 | ||
509 | /** | |
510 | * struct iwlagn_schedq_bc_tbl scheduler byte count table | |
511 | * base physical address provided by SCD_DRAM_BASE_ADDR | |
512 | * @tfd_offset 0-12 - tx command byte count | |
513 | * 12-16 - station index | |
514 | */ | |
515 | struct iwlagn_scd_bc_tbl { | |
516 | __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; | |
517 | } __packed; | |
518 | ||
65a0667b | 519 | #endif /* !__iwl_fh_h__ */ |