Commit | Line | Data |
---|---|---|
34cf6ff6 AK |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
01f8162a | 8 | * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved. |
34cf6ff6 AK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
759ef89f | 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
34cf6ff6 AK |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
01f8162a | 33 | * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. |
34cf6ff6 AK |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | ||
63 | #ifndef __iwl_eeprom_h__ | |
64 | #define __iwl_eeprom_h__ | |
65 | ||
be1a71a1 JB |
66 | #include <net/mac80211.h> |
67 | ||
c79dd5b5 | 68 | struct iwl_priv; |
34cf6ff6 AK |
69 | |
70 | /* | |
71 | * EEPROM access time values: | |
72 | * | |
3d5717ad | 73 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. |
34cf6ff6 AK |
74 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). |
75 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. | |
76 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. | |
77 | */ | |
78 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ | |
34cf6ff6 | 79 | |
3d5717ad | 80 | #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ |
34cf6ff6 AK |
81 | #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ |
82 | ||
83 | ||
84 | /* | |
85 | * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags. | |
86 | * | |
87 | * IBSS and/or AP operation is allowed *only* on those channels with | |
88 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because | |
89 | * RADAR detection is not supported by the 4965 driver, but is a | |
90 | * requirement for establishing a new network for legal operation on channels | |
91 | * requiring RADAR detection or restricting ACTIVE scanning. | |
92 | * | |
7aafef1c WYG |
93 | * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels. |
94 | * It only indicates that 20 MHz channel use is supported; HT40 channel | |
34cf6ff6 | 95 | * usage is indicated by a separate set of regulatory flags for each |
7aafef1c | 96 | * HT40 channel pair. |
34cf6ff6 AK |
97 | * |
98 | * NOTE: Using a channel inappropriately will result in a uCode error! | |
99 | */ | |
100 | #define IWL_NUM_TX_CALIB_GROUPS 5 | |
101 | enum { | |
102 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ | |
103 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ | |
104 | /* Bit 2 Reserved */ | |
105 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ | |
106 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ | |
107 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ | |
fe7c4040 | 108 | /* Bit 6 Reserved (was Narrow Channel) */ |
34cf6ff6 AK |
109 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ |
110 | }; | |
111 | ||
112 | /* SKU Capabilities */ | |
113 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) | |
114 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) | |
115 | ||
116 | /* *regulatory* channel data format in eeprom, one for each channel. | |
7aafef1c | 117 | * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */ |
073d3f5f | 118 | struct iwl_eeprom_channel { |
34cf6ff6 AK |
119 | u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ |
120 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ | |
121 | } __attribute__ ((packed)); | |
122 | ||
ab9fd1bf WYG |
123 | /** |
124 | * iwl_eeprom_enhanced_txpwr structure | |
125 | * This structure presents the enhanced regulatory tx power limit layout | |
126 | * in eeprom image | |
127 | * Enhanced regulatory tx power portion of eeprom image can be broken down | |
128 | * into individual structures; each one is 8 bytes in size and contain the | |
129 | * following information | |
85f0d9e8 | 130 | * @common: (desc + channel) not used by driver, should _NOT_ be "zero" |
ab9fd1bf WYG |
131 | * @chain_a_max_pwr: chain a max power in 1/2 dBm |
132 | * @chain_b_max_pwr: chain b max power in 1/2 dBm | |
133 | * @chain_c_max_pwr: chain c max power in 1/2 dBm | |
85f0d9e8 | 134 | * @reserved: not used, should be "zero" |
ab9fd1bf WYG |
135 | * @mimo2_max_pwr: mimo2 max power in 1/2 dBm |
136 | * @mimo3_max_pwr: mimo3 max power in 1/2 dBm | |
137 | * | |
138 | */ | |
139 | struct iwl_eeprom_enhanced_txpwr { | |
b7bb1756 | 140 | __le16 common; |
ab9fd1bf WYG |
141 | s8 chain_a_max; |
142 | s8 chain_b_max; | |
143 | s8 chain_c_max; | |
85f0d9e8 | 144 | s8 reserved; |
ab9fd1bf WYG |
145 | s8 mimo2_max; |
146 | s8 mimo3_max; | |
147 | } __attribute__ ((packed)); | |
148 | ||
e6148917 SO |
149 | /* 3945 Specific */ |
150 | #define EEPROM_3945_EEPROM_VERSION (0x2f) | |
151 | ||
34cf6ff6 AK |
152 | /* 4965 has two radio transmitters (and 3 radio receivers) */ |
153 | #define EEPROM_TX_POWER_TX_CHAINS (2) | |
154 | ||
155 | /* 4965 has room for up to 8 sets of txpower calibration data */ | |
156 | #define EEPROM_TX_POWER_BANDS (8) | |
157 | ||
158 | /* 4965 factory calibration measures txpower gain settings for | |
159 | * each of 3 target output levels */ | |
160 | #define EEPROM_TX_POWER_MEASUREMENTS (3) | |
161 | ||
073d3f5f TW |
162 | /* 4965 Specific */ |
163 | /* 4965 driver does not work with txpower calibration version < 5 */ | |
164 | #define EEPROM_4965_TX_POWER_VERSION (5) | |
8614f360 | 165 | #define EEPROM_4965_EEPROM_VERSION (0x2f) |
073d3f5f TW |
166 | #define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */ |
167 | #define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */ | |
168 | #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */ | |
169 | #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */ | |
34cf6ff6 | 170 | |
f1f69415 TW |
171 | /* 5000 Specific */ |
172 | #define EEPROM_5000_TX_POWER_VERSION (4) | |
173 | #define EEPROM_5000_EEPROM_VERSION (0x11A) | |
174 | ||
25ae3986 TW |
175 | /*5000 calibrations */ |
176 | #define EEPROM_5000_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) | |
7c616cba | 177 | #define EEPROM_5000_XTAL ((2*0x128) | EEPROM_5000_CALIB_ALL) |
339afc89 | 178 | #define EEPROM_5000_TEMPERATURE ((2*0x12A) | EEPROM_5000_CALIB_ALL) |
25ae3986 TW |
179 | |
180 | /* 5000 links */ | |
181 | #define EEPROM_5000_LINK_HOST (2*0x64) | |
182 | #define EEPROM_5000_LINK_GENERAL (2*0x65) | |
183 | #define EEPROM_5000_LINK_REGULATORY (2*0x66) | |
184 | #define EEPROM_5000_LINK_CALIBRATION (2*0x67) | |
185 | #define EEPROM_5000_LINK_PROCESS_ADJST (2*0x68) | |
186 | #define EEPROM_5000_LINK_OTHERS (2*0x69) | |
187 | ||
188 | /* 5000 regulatory - indirect access */ | |
189 | #define EEPROM_5000_REG_SKU_ID ((0x02)\ | |
190 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 4 bytes */ | |
191 | #define EEPROM_5000_REG_BAND_1_CHANNELS ((0x08)\ | |
192 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */ | |
193 | #define EEPROM_5000_REG_BAND_2_CHANNELS ((0x26)\ | |
194 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */ | |
195 | #define EEPROM_5000_REG_BAND_3_CHANNELS ((0x42)\ | |
196 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */ | |
197 | #define EEPROM_5000_REG_BAND_4_CHANNELS ((0x5C)\ | |
198 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */ | |
199 | #define EEPROM_5000_REG_BAND_5_CHANNELS ((0x74)\ | |
200 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */ | |
7aafef1c | 201 | #define EEPROM_5000_REG_BAND_24_HT40_CHANNELS ((0x82)\ |
25ae3986 | 202 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */ |
7aafef1c | 203 | #define EEPROM_5000_REG_BAND_52_HT40_CHANNELS ((0x92)\ |
25ae3986 TW |
204 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */ |
205 | ||
ab9fd1bf WYG |
206 | /* 6000 and up regulatory tx power - indirect access */ |
207 | /* max. elements per section */ | |
208 | #define EEPROM_MAX_TXPOWER_SECTION_ELEMENTS (8) | |
209 | #define EEPROM_TXPOWER_COMMON_HT40_INDEX (2) | |
210 | ||
211 | /** | |
212 | * Partition the enhanced tx power portion of eeprom image into | |
213 | * 10 sections based on band, modulation, frequency and channel | |
214 | * | |
215 | * Section 1: all CCK channels | |
216 | * Section 2: all 2.4 GHz OFDM (Legacy, HT and HT40 ) channels | |
217 | * Section 3: all 5.2 GHz OFDM (Legacy, HT and HT40) channels | |
218 | * Section 4: 2.4 GHz 20MHz channels: 1, 2, 10, 11. Both Legacy and HT | |
219 | * Section 5: 2.4 GHz 40MHz channels: 1, 2, 6, 7, 9, (_above_) | |
220 | * Section 6: 5.2 GHz 20MHz channels: 36, 64, 100, both Legacy and HT | |
221 | * Section 7: 5.2 GHz 40MHz channels: 36, 60, 100 (_above_) | |
222 | * Section 8: 2.4 GHz channel 13, Both Legacy and HT | |
223 | * Section 9: 2.4 GHz channel 140, Both Legacy and HT | |
224 | * Section 10: 2.4 GHz 40MHz channels: 132, 44 (_above_) | |
225 | */ | |
226 | /* 2.4 GHz band: CCK */ | |
722d9b1e | 227 | #define EEPROM_LB_CCK_20_COMMON ((0xA8)\ |
ab9fd1bf WYG |
228 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 8 bytes */ |
229 | /* 2.4 GHz band: 20MHz-Legacy, 20MHz-HT, 40MHz-HT */ | |
722d9b1e | 230 | #define EEPROM_LB_OFDM_COMMON ((0xB0)\ |
ab9fd1bf WYG |
231 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */ |
232 | /* 5.2 GHz band: 20MHz-Legacy, 20MHz-HT, 40MHz-HT */ | |
722d9b1e | 233 | #define EEPROM_HB_OFDM_COMMON ((0xC8)\ |
ab9fd1bf WYG |
234 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */ |
235 | /* 2.4GHz band channels: | |
236 | * 1Legacy, 1HT, 2Legacy, 2HT, 10Legacy, 10HT, 11Legacy, 11HT */ | |
722d9b1e | 237 | #define EEPROM_LB_OFDM_20_BAND ((0xE0)\ |
ab9fd1bf WYG |
238 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 64 bytes */ |
239 | /* 2.4 GHz band HT40 channels: (1,+1) (2,+1) (6,+1) (7,+1) (9,+1) */ | |
722d9b1e | 240 | #define EEPROM_LB_OFDM_HT40_BAND ((0x120)\ |
ab9fd1bf WYG |
241 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 40 bytes */ |
242 | /* 5.2GHz band channels: 36Legacy, 36HT, 64Legacy, 64HT, 100Legacy, 100HT */ | |
722d9b1e | 243 | #define EEPROM_HB_OFDM_20_BAND ((0x148)\ |
ab9fd1bf WYG |
244 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 48 bytes */ |
245 | /* 5.2 GHz band HT40 channels: (36,+1) (60,+1) (100,+1) */ | |
722d9b1e | 246 | #define EEPROM_HB_OFDM_HT40_BAND ((0x178)\ |
ab9fd1bf WYG |
247 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */ |
248 | /* 2.4 GHz band, channnel 13: Legacy, HT */ | |
722d9b1e | 249 | #define EEPROM_LB_OFDM_20_CHANNEL_13 ((0x190)\ |
ab9fd1bf WYG |
250 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 16 bytes */ |
251 | /* 5.2 GHz band, channnel 140: Legacy, HT */ | |
722d9b1e | 252 | #define EEPROM_HB_OFDM_20_CHANNEL_140 ((0x1A0)\ |
ab9fd1bf WYG |
253 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 16 bytes */ |
254 | /* 5.2 GHz band, HT40 channnels (132,+1) (44,+1) */ | |
722d9b1e | 255 | #define EEPROM_HB_OFDM_HT40_BAND_1 ((0x1B0)\ |
ab9fd1bf WYG |
256 | | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 16 bytes */ |
257 | ||
258 | ||
0ef2ca67 TW |
259 | /* 5050 Specific */ |
260 | #define EEPROM_5050_TX_POWER_VERSION (4) | |
261 | #define EEPROM_5050_EEPROM_VERSION (0x21E) | |
25ae3986 | 262 | |
1f4b9665 | 263 | /* 1000 Specific */ |
72f0ebd9 | 264 | #define EEPROM_1000_EEPROM_VERSION (0x15C) |
1f4b9665 | 265 | |
32b7e244 | 266 | /* 6x00 Specific */ |
1f4b9665 WYG |
267 | #define EEPROM_6000_EEPROM_VERSION (0x434) |
268 | ||
32b7e244 WYG |
269 | /* 6x50 Specific */ |
270 | #define EEPROM_6050_EEPROM_VERSION (0x532) | |
271 | ||
0848e297 | 272 | /* OTP */ |
415e4993 WYG |
273 | /* lower blocks contain EEPROM image and calibration data */ |
274 | #define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */ | |
275 | /* high blocks contain PAPD data */ | |
276 | #define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */ | |
277 | #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */ | |
278 | #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */ | |
279 | #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */ | |
280 | #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */ | |
0848e297 | 281 | |
bf85ea4f AK |
282 | /* 2.4 GHz */ |
283 | extern const u8 iwl_eeprom_band_1[14]; | |
34cf6ff6 AK |
284 | |
285 | /* | |
073d3f5f | 286 | * factory calibration data for one txpower level, on one channel, |
34cf6ff6 AK |
287 | * measured on one of the 2 tx chains (radio transmitter and associated |
288 | * antenna). EEPROM contains: | |
289 | * | |
290 | * 1) Temperature (degrees Celsius) of device when measurement was made. | |
291 | * | |
292 | * 2) Gain table index used to achieve the target measurement power. | |
293 | * This refers to the "well-known" gain tables (see iwl-4965-hw.h). | |
294 | * | |
295 | * 3) Actual measured output power, in half-dBm ("34" = 17 dBm). | |
296 | * | |
297 | * 4) RF power amplifier detector level measurement (not used). | |
298 | */ | |
073d3f5f | 299 | struct iwl_eeprom_calib_measure { |
34cf6ff6 AK |
300 | u8 temperature; /* Device temperature (Celsius) */ |
301 | u8 gain_idx; /* Index into gain table */ | |
302 | u8 actual_pow; /* Measured RF output power, half-dBm */ | |
303 | s8 pa_det; /* Power amp detector level (not used) */ | |
304 | } __attribute__ ((packed)); | |
305 | ||
306 | ||
307 | /* | |
073d3f5f | 308 | * measurement set for one channel. EEPROM contains: |
34cf6ff6 AK |
309 | * |
310 | * 1) Channel number measured | |
311 | * | |
312 | * 2) Measurements for each of 3 power levels for each of 2 radio transmitters | |
313 | * (a.k.a. "tx chains") (6 measurements altogether) | |
314 | */ | |
073d3f5f | 315 | struct iwl_eeprom_calib_ch_info { |
34cf6ff6 | 316 | u8 ch_num; |
073d3f5f | 317 | struct iwl_eeprom_calib_measure |
34cf6ff6 AK |
318 | measurements[EEPROM_TX_POWER_TX_CHAINS] |
319 | [EEPROM_TX_POWER_MEASUREMENTS]; | |
320 | } __attribute__ ((packed)); | |
321 | ||
322 | /* | |
073d3f5f | 323 | * txpower subband info. |
34cf6ff6 AK |
324 | * |
325 | * For each frequency subband, EEPROM contains the following: | |
326 | * | |
327 | * 1) First and last channels within range of the subband. "0" values | |
328 | * indicate that this sample set is not being used. | |
329 | * | |
330 | * 2) Sample measurement sets for 2 channels close to the range endpoints. | |
331 | */ | |
073d3f5f | 332 | struct iwl_eeprom_calib_subband_info { |
34cf6ff6 AK |
333 | u8 ch_from; /* channel number of lowest channel in subband */ |
334 | u8 ch_to; /* channel number of highest channel in subband */ | |
073d3f5f TW |
335 | struct iwl_eeprom_calib_ch_info ch1; |
336 | struct iwl_eeprom_calib_ch_info ch2; | |
34cf6ff6 AK |
337 | } __attribute__ ((packed)); |
338 | ||
339 | ||
340 | /* | |
073d3f5f | 341 | * txpower calibration info. EEPROM contains: |
34cf6ff6 AK |
342 | * |
343 | * 1) Factory-measured saturation power levels (maximum levels at which | |
344 | * tx power amplifier can output a signal without too much distortion). | |
345 | * There is one level for 2.4 GHz band and one for 5 GHz band. These | |
346 | * values apply to all channels within each of the bands. | |
347 | * | |
348 | * 2) Factory-measured power supply voltage level. This is assumed to be | |
349 | * constant (i.e. same value applies to all channels/bands) while the | |
350 | * factory measurements are being made. | |
351 | * | |
352 | * 3) Up to 8 sets of factory-measured txpower calibration values. | |
353 | * These are for different frequency ranges, since txpower gain | |
354 | * characteristics of the analog radio circuitry vary with frequency. | |
355 | * | |
356 | * Not all sets need to be filled with data; | |
073d3f5f | 357 | * struct iwl_eeprom_calib_subband_info contains range of channels |
34cf6ff6 AK |
358 | * (0 if unused) for each set of data. |
359 | */ | |
073d3f5f | 360 | struct iwl_eeprom_calib_info { |
34cf6ff6 AK |
361 | u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ |
362 | u8 saturation_power52; /* half-dBm */ | |
b7bb1756 | 363 | __le16 voltage; /* signed */ |
073d3f5f | 364 | struct iwl_eeprom_calib_subband_info |
34cf6ff6 AK |
365 | band_info[EEPROM_TX_POWER_BANDS]; |
366 | } __attribute__ ((packed)); | |
367 | ||
368 | ||
073d3f5f TW |
369 | #define ADDRESS_MSK 0x0000FFFF |
370 | #define INDIRECT_TYPE_MSK 0x000F0000 | |
371 | #define INDIRECT_HOST 0x00010000 | |
372 | #define INDIRECT_GENERAL 0x00020000 | |
373 | #define INDIRECT_REGULATORY 0x00030000 | |
374 | #define INDIRECT_CALIBRATION 0x00040000 | |
375 | #define INDIRECT_PROCESS_ADJST 0x00050000 | |
376 | #define INDIRECT_OTHERS 0x00060000 | |
377 | #define INDIRECT_ADDRESS 0x00100000 | |
378 | ||
379 | /* General */ | |
380 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | |
381 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ | |
382 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ | |
383 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ | |
384 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ | |
385 | #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */ | |
073d3f5f TW |
386 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ |
387 | #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ | |
694cc56d | 388 | #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ |
073d3f5f | 389 | #define EEPROM_3945_M_VERSION (2*0x4A) /* 1 bytes */ |
34cf6ff6 | 390 | |
694cc56d TW |
391 | /* The following masks are to be applied on EEPROM_RADIO_CONFIG */ |
392 | #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ | |
393 | #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ | |
394 | #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ | |
395 | #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ | |
396 | #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ | |
397 | #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ | |
398 | ||
399 | #define EEPROM_3945_RF_CFG_TYPE_MAX 0x0 | |
400 | #define EEPROM_4965_RF_CFG_TYPE_MAX 0x1 | |
9371d4ed WYG |
401 | |
402 | /* Radio Config for 5000 and up */ | |
403 | #define EEPROM_RF_CONFIG_TYPE_R3x3 0x0 | |
404 | #define EEPROM_RF_CONFIG_TYPE_R2x2 0x1 | |
405 | #define EEPROM_RF_CONFIG_TYPE_R1x2 0x2 | |
406 | #define EEPROM_RF_CONFIG_TYPE_MAX 0x3 | |
694cc56d | 407 | |
34cf6ff6 AK |
408 | /* |
409 | * Per-channel regulatory data. | |
410 | * | |
073d3f5f | 411 | * Each channel that *might* be supported by iwl has a fixed location |
34cf6ff6 AK |
412 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory |
413 | * txpower (MSB). | |
414 | * | |
7aafef1c | 415 | * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz) |
34cf6ff6 AK |
416 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. |
417 | * | |
418 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
419 | */ | |
073d3f5f TW |
420 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ |
421 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ | |
422 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ | |
34cf6ff6 AK |
423 | |
424 | /* | |
425 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
426 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
427 | * (4915-5080MHz) (none of these is ever supported) | |
428 | */ | |
073d3f5f TW |
429 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ |
430 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ | |
34cf6ff6 AK |
431 | |
432 | /* | |
433 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
434 | * (5170-5320MHz) | |
435 | */ | |
073d3f5f TW |
436 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ |
437 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ | |
34cf6ff6 AK |
438 | |
439 | /* | |
440 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
441 | * (5500-5700MHz) | |
442 | */ | |
073d3f5f TW |
443 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ |
444 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ | |
34cf6ff6 AK |
445 | |
446 | /* | |
447 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
448 | * (5725-5825MHz) | |
449 | */ | |
073d3f5f TW |
450 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ |
451 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ | |
34cf6ff6 AK |
452 | |
453 | /* | |
7aafef1c | 454 | * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) |
34cf6ff6 AK |
455 | * |
456 | * The channel listed is the center of the lower 20 MHz half of the channel. | |
457 | * The overall center frequency is actually 2 channels (10 MHz) above that, | |
7aafef1c WYG |
458 | * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away |
459 | * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5, | |
460 | * and the overall HT40 channel width centers on channel 3. | |
34cf6ff6 AK |
461 | * |
462 | * NOTE: The RXON command uses 20 MHz channel numbers to specify the | |
463 | * control channel to which to tune. RXON also specifies whether the | |
7aafef1c | 464 | * control channel is the upper or lower half of a HT40 channel. |
34cf6ff6 | 465 | * |
7aafef1c | 466 | * NOTE: 4965 does not support HT40 channels on 2.4 GHz. |
34cf6ff6 | 467 | */ |
7aafef1c | 468 | #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */ |
34cf6ff6 AK |
469 | |
470 | /* | |
7aafef1c | 471 | * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64), |
34cf6ff6 AK |
472 | * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) |
473 | */ | |
7aafef1c | 474 | #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */ |
34cf6ff6 | 475 | |
7aafef1c | 476 | #define EEPROM_REGULATORY_BAND_NO_HT40 (0) |
a89d03c4 | 477 | |
34cf6ff6 | 478 | struct iwl_eeprom_ops { |
073d3f5f | 479 | const u32 regulatory_bands[7]; |
c79dd5b5 TW |
480 | int (*verify_signature) (struct iwl_priv *priv); |
481 | int (*acquire_semaphore) (struct iwl_priv *priv); | |
482 | void (*release_semaphore) (struct iwl_priv *priv); | |
0ef2ca67 | 483 | u16 (*calib_version) (struct iwl_priv *priv); |
073d3f5f | 484 | const u8* (*query_addr) (const struct iwl_priv *priv, size_t offset); |
ab9fd1bf | 485 | void (*update_enhanced_txpower) (struct iwl_priv *priv); |
34cf6ff6 AK |
486 | }; |
487 | ||
488 | ||
c79dd5b5 TW |
489 | void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac); |
490 | int iwl_eeprom_init(struct iwl_priv *priv); | |
073d3f5f | 491 | void iwl_eeprom_free(struct iwl_priv *priv); |
8614f360 | 492 | int iwl_eeprom_check_version(struct iwl_priv *priv); |
073d3f5f TW |
493 | const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset); |
494 | u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset); | |
34cf6ff6 | 495 | |
c79dd5b5 TW |
496 | int iwlcore_eeprom_verify_signature(struct iwl_priv *priv); |
497 | int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv); | |
498 | void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv); | |
073d3f5f | 499 | const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset); |
ab9fd1bf | 500 | void iwlcore_eeprom_enhanced_txpower(struct iwl_priv *priv); |
bf85ea4f AK |
501 | int iwl_init_channel_map(struct iwl_priv *priv); |
502 | void iwl_free_channel_map(struct iwl_priv *priv); | |
8622e705 | 503 | const struct iwl_channel_info *iwl_get_channel_info( |
bf85ea4f AK |
504 | const struct iwl_priv *priv, |
505 | enum ieee80211_band band, u16 channel); | |
506 | ||
34cf6ff6 | 507 | #endif /* __iwl_eeprom_h__ */ |