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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/version.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
712b6cf5 34struct iwl_priv; /* FIXME: remove */
0a6857e7 35#include "iwl-debug.h"
6bc913bd 36#include "iwl-eeprom.h"
3e0d4cb1 37#include "iwl-dev.h" /* FIXME: remove */
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
ad97edd2 40#include "iwl-rfkill.h"
5da4b55f 41#include "iwl-power.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
46MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
62/*
63 * Parameter order:
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
1826dcc0 70const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
85};
1826dcc0 86EXPORT_SYMBOL(iwl_rates);
c7de35cd 87
e7d326ac
TW		 88/**
89 * translate ucode response to mac80211 tx status control values
90 */
91void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
92 struct ieee80211_tx_info *control)
93{
94 int rate_index;
95
96 control->antenna_sel_tx =
97 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
98 if (rate_n_flags & RATE_MCS_HT_MSK)
99 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
100 if (rate_n_flags & RATE_MCS_GF_MSK)
101 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
102 if (rate_n_flags & RATE_MCS_FAT_MSK)
103 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
104 if (rate_n_flags & RATE_MCS_DUP_MSK)
105 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
106 if (rate_n_flags & RATE_MCS_SGI_MSK)
107 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
108 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
109 if (control->band == IEEE80211_BAND_5GHZ)
110 rate_index -= IWL_FIRST_OFDM_RATE;
111 control->tx_rate_idx = rate_index;
112}
113EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
114
115int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
116{
117 int idx = 0;
118
119 /* HT rate format */
120 if (rate_n_flags & RATE_MCS_HT_MSK) {
121 idx = (rate_n_flags & 0xff);
122
123 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
124 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
125
126 idx += IWL_FIRST_OFDM_RATE;
127 /* skip 9M not supported in ht*/
128 if (idx >= IWL_RATE_9M_INDEX)
129 idx += 1;
130 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
131 return idx;
132
133 /* legacy rate format, search for match in table */
134 } else {
135 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
136 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
137 return idx;
138 }
139
140 return -1;
141}
142EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
143
144
57bd1bea
TW		 145
146const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
147EXPORT_SYMBOL(iwl_bcast_addr);
148
149
1d0a082d
AK		 150/* This function both allocates and initializes hw and priv. */
151struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
152 struct ieee80211_ops *hw_ops)
153{
154 struct iwl_priv *priv;
155
156 /* mac80211 allocates memory for this device instance, including
157 * space for this driver's private structure */
158 struct ieee80211_hw *hw =
159 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
160 if (hw == NULL) {
161 IWL_ERROR("Can not allocate network device\n");
162 goto out;
163 }
164
165 priv = hw->priv;
166 priv->hw = hw;
167
168out:
169 return hw;
170}
171EXPORT_SYMBOL(iwl_alloc_all);
172
b661c819
TW		 173void iwl_hw_detect(struct iwl_priv *priv)
174{
175 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
176 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
177 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
178}
179EXPORT_SYMBOL(iwl_hw_detect);
180
1053d35f
RR		 181/* Tell nic where to find the "keep warm" buffer */
182int iwl_kw_init(struct iwl_priv *priv)
183{
184 unsigned long flags;
185 int ret;
186
187 spin_lock_irqsave(&priv->lock, flags);
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
193 priv->kw.dma_addr >> 4);
194 iwl_release_nic_access(priv);
195out:
196 spin_unlock_irqrestore(&priv->lock, flags);
197 return ret;
198}
199
200int iwl_kw_alloc(struct iwl_priv *priv)
201{
202 struct pci_dev *dev = priv->pci_dev;
16466903 203 struct iwl_kw *kw = &priv->kw;
1053d35f 204
16466903 205 kw->size = IWL_KW_SIZE;
1053d35f
RR		 206 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
207 if (!kw->v_addr)
208 return -ENOMEM;
209
210 return 0;
211}
212
213/**
214 * iwl_kw_free - Free the "keep warm" buffer
215 */
216void iwl_kw_free(struct iwl_priv *priv)
217{
218 struct pci_dev *dev = priv->pci_dev;
16466903 219 struct iwl_kw *kw = &priv->kw;
1053d35f
RR		 220
221 if (kw->v_addr) {
222 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
223 memset(kw, 0, sizeof(*kw));
224 }
225}
226
227int iwl_hw_nic_init(struct iwl_priv *priv)
228{
229 unsigned long flags;
230 struct iwl_rx_queue *rxq = &priv->rxq;
231 int ret;
232
233 /* nic_init */
1053d35f 234 spin_lock_irqsave(&priv->lock, flags);
1b73af82 235 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 236 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
237 spin_unlock_irqrestore(&priv->lock, flags);
238
239 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
240
241 priv->cfg->ops->lib->apm_ops.config(priv);
242
243 /* Allocate the RX queue, or reset if it is already allocated */
244 if (!rxq->bd) {
245 ret = iwl_rx_queue_alloc(priv);
246 if (ret) {
247 IWL_ERROR("Unable to initialize Rx queue\n");
248 return -ENOMEM;
249 }
250 } else
251 iwl_rx_queue_reset(priv, rxq);
252
253 iwl_rx_replenish(priv);
254
255 iwl_rx_init(priv, rxq);
256
257 spin_lock_irqsave(&priv->lock, flags);
258
259 rxq->need_update = 1;
260 iwl_rx_queue_update_write_ptr(priv, rxq);
261
262 spin_unlock_irqrestore(&priv->lock, flags);
263
264 /* Allocate and init all Tx and Command queues */
265 ret = iwl_txq_ctx_reset(priv);
266 if (ret)
267 return ret;
268
269 set_bit(STATUS_INIT, &priv->status);
270
271 return 0;
272}
273EXPORT_SYMBOL(iwl_hw_nic_init);
274
bf85ea4f 275/**
37deb2a0 276 * iwl_clear_stations_table - Clear the driver's station table
bf85ea4f
AK		 277 *
278 * NOTE: This does not clear or otherwise alter the device's station table.
279 */
37deb2a0 280void iwl_clear_stations_table(struct iwl_priv *priv)
bf85ea4f
AK		 281{
282 unsigned long flags;
283
284 spin_lock_irqsave(&priv->sta_lock, flags);
285
24e5c401 286 if (iwl_is_alive(priv) &&
37deb2a0
EG		 287 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
288 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
24e5c401
EG		 289 IWL_ERROR("Couldn't clear the station table\n");
290
37deb2a0 291 priv->num_stations = 0;
bf85ea4f
AK		 292 memset(priv->stations, 0, sizeof(priv->stations));
293
294 spin_unlock_irqrestore(&priv->sta_lock, flags);
295}
37deb2a0 296EXPORT_SYMBOL(iwl_clear_stations_table);
bf85ea4f 297
c7de35cd 298void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 299{
300 u16 cw_min = 15;
301 u16 cw_max = 1023;
302 u8 aifs = 2;
303 u8 is_legacy = 0;
304 unsigned long flags;
305 int i;
306
307 spin_lock_irqsave(&priv->lock, flags);
308 priv->qos_data.qos_active = 0;
309
310 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
311 if (priv->qos_data.qos_enable)
312 priv->qos_data.qos_active = 1;
313 if (!(priv->active_rate & 0xfff0)) {
314 cw_min = 31;
315 is_legacy = 1;
316 }
317 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
318 if (priv->qos_data.qos_enable)
319 priv->qos_data.qos_active = 1;
320 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
321 cw_min = 31;
322 is_legacy = 1;
323 }
324
325 if (priv->qos_data.qos_active)
326 aifs = 3;
327
328 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
329 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
330 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
331 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
332 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
333
334 if (priv->qos_data.qos_active) {
335 i = 1;
336 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
337 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
338 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
339 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
340 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
341
342 i = 2;
343 priv->qos_data.def_qos_parm.ac[i].cw_min =
344 cpu_to_le16((cw_min + 1) / 2 - 1);
345 priv->qos_data.def_qos_parm.ac[i].cw_max =
346 cpu_to_le16(cw_max);
347 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
348 if (is_legacy)
349 priv->qos_data.def_qos_parm.ac[i].edca_txop =
350 cpu_to_le16(6016);
351 else
352 priv->qos_data.def_qos_parm.ac[i].edca_txop =
353 cpu_to_le16(3008);
354 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
355
356 i = 3;
357 priv->qos_data.def_qos_parm.ac[i].cw_min =
358 cpu_to_le16((cw_min + 1) / 4 - 1);
359 priv->qos_data.def_qos_parm.ac[i].cw_max =
360 cpu_to_le16((cw_max + 1) / 2 - 1);
361 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
362 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
363 if (is_legacy)
364 priv->qos_data.def_qos_parm.ac[i].edca_txop =
365 cpu_to_le16(3264);
366 else
367 priv->qos_data.def_qos_parm.ac[i].edca_txop =
368 cpu_to_le16(1504);
369 } else {
370 for (i = 1; i < 4; i++) {
371 priv->qos_data.def_qos_parm.ac[i].cw_min =
372 cpu_to_le16(cw_min);
373 priv->qos_data.def_qos_parm.ac[i].cw_max =
374 cpu_to_le16(cw_max);
375 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
376 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
377 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
378 }
379 }
380 IWL_DEBUG_QOS("set QoS to default \n");
381
382 spin_unlock_irqrestore(&priv->lock, flags);
383}
c7de35cd
RR		 384EXPORT_SYMBOL(iwl_reset_qos);
385
39130df3
RR		 386#define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
387#define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
c7de35cd
RR		 388static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
389 struct ieee80211_ht_info *ht_info,
390 enum ieee80211_band band)
391{
39130df3
RR		 392 u16 max_bit_rate = 0;
393 u8 rx_chains_num = priv->hw_params.rx_chains_num;
394 u8 tx_chains_num = priv->hw_params.tx_chains_num;
395
c7de35cd
RR		 396 ht_info->cap = 0;
397 memset(ht_info->supp_mcs_set, 0, 16);
398
399 ht_info->ht_supported = 1;
400
39130df3
RR		 401 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
402 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
403 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
404 (IWL_MIMO_PS_NONE << 2));
405
406 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd
RR		 407 if (priv->hw_params.fat_channel & BIT(band)) {
408 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
409 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
410 ht_info->supp_mcs_set[4] = 0x01;
39130df3 411 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 412 }
c7de35cd
RR		 413
414 if (priv->cfg->mod_params->amsdu_size_8K)
415 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
416
417 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
418 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
419
420 ht_info->supp_mcs_set[0] = 0xFF;
39130df3 421 if (rx_chains_num >= 2)
c7de35cd 422 ht_info->supp_mcs_set[1] = 0xFF;
39130df3 423 if (rx_chains_num >= 3)
c7de35cd 424 ht_info->supp_mcs_set[2] = 0xFF;
39130df3
RR		 425
426 /* Highest supported Rx data rate */
427 max_bit_rate *= rx_chains_num;
428 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
429 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
430
431 /* Tx MCS capabilities */
432 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
433 if (tx_chains_num != rx_chains_num) {
434 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
435 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
436 }
c7de35cd 437}
c7de35cd
RR		 438
439static void iwlcore_init_hw_rates(struct iwl_priv *priv,
440 struct ieee80211_rate *rates)
441{
442 int i;
443
444 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 445 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 446 rates[i].hw_value = i; /* Rate scaling will work on indexes */
447 rates[i].hw_value_short = i;
448 rates[i].flags = 0;
449 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
450 /*
451 * If CCK != 1M then set short preamble rate flag.
452 */
453 rates[i].flags |=
1826dcc0 454 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 455 0 : IEEE80211_RATE_SHORT_PREAMBLE;
456 }
457 }
458}
459
460/**
461 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
462 */
463static int iwlcore_init_geos(struct iwl_priv *priv)
464{
465 struct iwl_channel_info *ch;
466 struct ieee80211_supported_band *sband;
467 struct ieee80211_channel *channels;
468 struct ieee80211_channel *geo_ch;
469 struct ieee80211_rate *rates;
470 int i = 0;
471
472 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
473 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
474 IWL_DEBUG_INFO("Geography modes already initialized.\n");
475 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
476 return 0;
477 }
478
479 channels = kzalloc(sizeof(struct ieee80211_channel) *
480 priv->channel_count, GFP_KERNEL);
481 if (!channels)
482 return -ENOMEM;
483
484 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
485 GFP_KERNEL);
486 if (!rates) {
487 kfree(channels);
488 return -ENOMEM;
489 }
490
491 /* 5.2GHz channels start after the 2.4GHz channels */
492 sband = &priv->bands[IEEE80211_BAND_5GHZ];
493 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
494 /* just OFDM */
495 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
496 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
497
49779293
RR		 498 if (priv->cfg->sku & IWL_SKU_N)
499 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
500 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 501
502 sband = &priv->bands[IEEE80211_BAND_2GHZ];
503 sband->channels = channels;
504 /* OFDM & CCK */
505 sband->bitrates = rates;
506 sband->n_bitrates = IWL_RATE_COUNT;
507
49779293
RR		 508 if (priv->cfg->sku & IWL_SKU_N)
509 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
510 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 511
512 priv->ieee_channels = channels;
513 priv->ieee_rates = rates;
514
515 iwlcore_init_hw_rates(priv, rates);
516
517 for (i = 0; i < priv->channel_count; i++) {
518 ch = &priv->channel_info[i];
519
520 /* FIXME: might be removed if scan is OK */
521 if (!is_channel_valid(ch))
522 continue;
523
524 if (is_channel_a_band(ch))
525 sband = &priv->bands[IEEE80211_BAND_5GHZ];
526 else
527 sband = &priv->bands[IEEE80211_BAND_2GHZ];
528
529 geo_ch = &sband->channels[sband->n_channels++];
530
531 geo_ch->center_freq =
532 ieee80211_channel_to_frequency(ch->channel);
533 geo_ch->max_power = ch->max_power_avg;
534 geo_ch->max_antenna_gain = 0xff;
535 geo_ch->hw_value = ch->channel;
536
537 if (is_channel_valid(ch)) {
538 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
539 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
540
541 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
542 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
543
544 if (ch->flags & EEPROM_CHANNEL_RADAR)
545 geo_ch->flags |= IEEE80211_CHAN_RADAR;
546
963f5517 547 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 548
630fe9b6
TW		 549 if (ch->max_power_avg > priv->tx_power_channel_lmt)
550 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 551 } else {
552 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
553 }
554
555 /* Save flags for reg domain usage */
556 geo_ch->orig_flags = geo_ch->flags;
557
963f5517 558 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 559 ch->channel, geo_ch->center_freq,
560 is_channel_a_band(ch) ? "5.2" : "2.4",
561 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
562 "restricted" : "valid",
563 geo_ch->flags);
564 }
565
566 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
567 priv->cfg->sku & IWL_SKU_A) {
568 printk(KERN_INFO DRV_NAME
569 ": Incorrectly detected BG card as ABG. Please send "
570 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
571 priv->pci_dev->device, priv->pci_dev->subsystem_device);
572 priv->cfg->sku &= ~IWL_SKU_A;
573 }
574
575 printk(KERN_INFO DRV_NAME
576 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
577 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
578 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
579
c7de35cd
RR		 580
581 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
582
583 return 0;
584}
585
586/*
587 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
588 */
6ba87956 589static void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 590{
591 kfree(priv->ieee_channels);
592 kfree(priv->ieee_rates);
593 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
594}
c7de35cd 595
c7de35cd
RR		 596static u8 is_single_rx_stream(struct iwl_priv *priv)
597{
598 return !priv->current_ht_config.is_ht ||
599 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
600 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
601 priv->ps_mode == IWL_MIMO_PS_STATIC;
602}
963f5517 603
47c5196e
TW		 604static u8 iwl_is_channel_extension(struct iwl_priv *priv,
605 enum ieee80211_band band,
606 u16 channel, u8 extension_chan_offset)
607{
608 const struct iwl_channel_info *ch_info;
609
610 ch_info = iwl_get_channel_info(priv, band, channel);
611 if (!is_channel_valid(ch_info))
612 return 0;
613
963f5517
EG		 614 if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
615 return !(ch_info->fat_extension_channel &
616 IEEE80211_CHAN_NO_FAT_ABOVE);
617 else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
618 return !(ch_info->fat_extension_channel &
619 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 620
621 return 0;
622}
623
624u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
625 struct ieee80211_ht_info *sta_ht_inf)
626{
627 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
628
629 if ((!iwl_ht_conf->is_ht) ||
630 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
963f5517 631 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
47c5196e
TW		 632 return 0;
633
634 if (sta_ht_inf) {
635 if ((!sta_ht_inf->ht_supported) ||
636 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
637 return 0;
638 }
639
640 return iwl_is_channel_extension(priv, priv->band,
641 iwl_ht_conf->control_channel,
642 iwl_ht_conf->extension_chan_offset);
643}
644EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
645
646void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
647{
c1adf9fb 648 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 649 u32 val;
650
651 if (!ht_info->is_ht)
652 return;
653
654 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
655 if (iwl_is_fat_tx_allowed(priv, NULL))
656 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
657 else
658 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
659 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
660
661 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
662 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
663 le16_to_cpu(rxon->channel),
664 ht_info->control_channel);
47c5196e
TW		 665 return;
666 }
667
668 /* Note: control channel is opposite of extension channel */
669 switch (ht_info->extension_chan_offset) {
963f5517 670 case IEEE80211_HT_IE_CHA_SEC_ABOVE:
47c5196e
TW		 671 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
672 break;
963f5517 673 case IEEE80211_HT_IE_CHA_SEC_BELOW:
47c5196e
TW		 674 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
675 break;
963f5517 676 case IEEE80211_HT_IE_CHA_SEC_NONE:
47c5196e
TW		 677 default:
678 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
679 break;
680 }
681
682 val = ht_info->ht_protection;
683
684 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
685
686 iwl_set_rxon_chain(priv);
687
688 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
689 "rxon flags 0x%X operation mode :0x%X "
690 "extension channel offset 0x%x "
691 "control chan %d\n",
692 ht_info->supp_mcs_set[0],
693 ht_info->supp_mcs_set[1],
694 ht_info->supp_mcs_set[2],
695 le32_to_cpu(rxon->flags), ht_info->ht_protection,
696 ht_info->extension_chan_offset,
697 ht_info->control_channel);
698 return;
699}
700EXPORT_SYMBOL(iwl_set_rxon_ht);
701
c7de35cd
RR		 702/*
703 * Determine how many receiver/antenna chains to use.
704 * More provides better reception via diversity. Fewer saves power.
705 * MIMO (dual stream) requires at least 2, but works better with 3.
706 * This does not determine *which* chains to use, just how many.
707 */
708static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
709 u8 *idle_state, u8 *rx_state)
710{
711 u8 is_single = is_single_rx_stream(priv);
712 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
713
714 /* # of Rx chains to use when expecting MIMO. */
715 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
716 *rx_state = 2;
717 else
718 *rx_state = 3;
719
720 /* # Rx chains when idling and maybe trying to save power */
721 switch (priv->ps_mode) {
722 case IWL_MIMO_PS_STATIC:
723 case IWL_MIMO_PS_DYNAMIC:
724 *idle_state = (is_cam) ? 2 : 1;
725 break;
726 case IWL_MIMO_PS_NONE:
727 *idle_state = (is_cam) ? *rx_state : 1;
728 break;
729 default:
730 *idle_state = 1;
731 break;
732 }
733
734 return 0;
735}
736
737/**
738 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
739 *
740 * Selects how many and which Rx receivers/antennas/chains to use.
741 * This should not be used for scan command ... it puts data in wrong place.
742 */
743void iwl_set_rxon_chain(struct iwl_priv *priv)
744{
745 u8 is_single = is_single_rx_stream(priv);
746 u8 idle_state, rx_state;
747
748 priv->staging_rxon.rx_chain = 0;
749 rx_state = idle_state = 3;
750
751 /* Tell uCode which antennas are actually connected.
752 * Before first association, we assume all antennas are connected.
753 * Just after first association, iwl_chain_noise_calibration()
754 * checks which antennas actually *are* connected. */
755 priv->staging_rxon.rx_chain |=
756 cpu_to_le16(priv->hw_params.valid_rx_ant <<
757 RXON_RX_CHAIN_VALID_POS);
758
759 /* How many receivers should we use? */
760 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
761 priv->staging_rxon.rx_chain |=
762 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
763 priv->staging_rxon.rx_chain |=
764 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
765
766 if (!is_single && (rx_state >= 2) &&
767 !test_bit(STATUS_POWER_PMI, &priv->status))
768 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
769 else
770 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
771
772 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
773}
774EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 775
776/**
777 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
778 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
779 * @channel: Any channel valid for the requested phymode
780
781 * In addition to setting the staging RXON, priv->phymode is also set.
782 *
783 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
784 * in the staging RXON flag structure based on the phymode
785 */
c7de35cd 786int iwl_set_rxon_channel(struct iwl_priv *priv,
bf85ea4f
AK		 787 enum ieee80211_band band,
788 u16 channel)
789{
8622e705 790 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 791 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
792 channel, band);
793 return -EINVAL;
794 }
795
796 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
797 (priv->band == band))
798 return 0;
799
800 priv->staging_rxon.channel = cpu_to_le16(channel);
801 if (band == IEEE80211_BAND_5GHZ)
802 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
803 else
804 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
805
806 priv->band = band;
807
808 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
809
810 return 0;
811}
c7de35cd 812EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 813
6ba87956 814int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 815{
6ba87956 816 int ret;
bf85ea4f
AK		 817 struct ieee80211_hw *hw = priv->hw;
818 hw->rate_control_algorithm = "iwl-4965-rs";
819
566bfe5a
BR		 820 /* Tell mac80211 our characteristics */
821 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
822 IEEE80211_HW_SIGNAL_DBM |
823 IEEE80211_HW_NOISE_DBM;
bf85ea4f
AK		 824 /* Default value; 4 EDCA QOS priorities */
825 hw->queues = 4;
49779293
RR		 826 /* queues to support 11n aggregation */
827 if (priv->cfg->sku & IWL_SKU_N)
828 hw->ampdu_queues = 12;
6ba87956
TW		 829
830 hw->conf.beacon_int = 100;
831
832 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
833 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
834 &priv->bands[IEEE80211_BAND_2GHZ];
835 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
836 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
837 &priv->bands[IEEE80211_BAND_5GHZ];
838
839 ret = ieee80211_register_hw(priv->hw);
840 if (ret) {
841 IWL_ERROR("Failed to register hw (error %d)\n", ret);
842 return ret;
843 }
844 priv->mac80211_registered = 1;
845
846 return 0;
bf85ea4f 847}
6ba87956 848EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 849
da154e30
RR		 850int iwl_set_hw_params(struct iwl_priv *priv)
851{
852 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
853 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
854 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
855 if (priv->cfg->mod_params->amsdu_size_8K)
856 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
857 else
858 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
859 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
860
49779293
RR		 861 if (priv->cfg->mod_params->disable_11n)
862 priv->cfg->sku &= ~IWL_SKU_N;
863
da154e30
RR		 864 /* Device-specific setup */
865 return priv->cfg->ops->lib->set_hw_params(priv);
866}
867EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 868
869int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 870{
871 int ret;
c7de35cd
RR		 872
873 priv->retry_rate = 1;
874 priv->ibss_beacon = NULL;
875
876 spin_lock_init(&priv->lock);
877 spin_lock_init(&priv->power_data.lock);
878 spin_lock_init(&priv->sta_lock);
879 spin_lock_init(&priv->hcmd_lock);
880 spin_lock_init(&priv->lq_mngr.lock);
881
c7de35cd
RR		 882 INIT_LIST_HEAD(&priv->free_frames);
883
884 mutex_init(&priv->mutex);
885
886 /* Clear the driver's (not device's) station table */
37deb2a0 887 iwl_clear_stations_table(priv);
c7de35cd
RR		 888
889 priv->data_retry_limit = -1;
890 priv->ieee_channels = NULL;
891 priv->ieee_rates = NULL;
892 priv->band = IEEE80211_BAND_2GHZ;
893
894 priv->iw_mode = IEEE80211_IF_TYPE_STA;
895
896 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
897 priv->ps_mode = IWL_MIMO_PS_NONE;
898
899 /* Choose which receivers/antennas to use */
900 iwl_set_rxon_chain(priv);
f53696de 901 iwl_init_scan_params(priv);
c7de35cd 902
6ba87956
TW		 903 if (priv->cfg->mod_params->enable_qos)
904 priv->qos_data.qos_enable = 1;
905
c7de35cd
RR		 906 iwl_reset_qos(priv);
907
908 priv->qos_data.qos_active = 0;
909 priv->qos_data.qos_cap.val = 0;
910
911 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
912
913 priv->rates_mask = IWL_RATES_MASK;
914 /* If power management is turned on, default to AC mode */
915 priv->power_mode = IWL_POWER_AC;
630fe9b6 916 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 917
918 ret = iwl_init_channel_map(priv);
919 if (ret) {
920 IWL_ERROR("initializing regulatory failed: %d\n", ret);
921 goto err;
922 }
923
924 ret = iwlcore_init_geos(priv);
925 if (ret) {
926 IWL_ERROR("initializing geos failed: %d\n", ret);
927 goto err_free_channel_map;
928 }
929
c7de35cd
RR		 930 return 0;
931
c7de35cd
RR		 932err_free_channel_map:
933 iwl_free_channel_map(priv);
934err:
935 return ret;
936}
6ba87956 937EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 938
7c616cba
TW		 939void iwl_free_calib_results(struct iwl_priv *priv)
940{
941 kfree(priv->calib_results.lo_res);
942 priv->calib_results.lo_res = NULL;
943 priv->calib_results.lo_res_len = 0;
944
945 kfree(priv->calib_results.tx_iq_res);
946 priv->calib_results.tx_iq_res = NULL;
947 priv->calib_results.tx_iq_res_len = 0;
948
949 kfree(priv->calib_results.tx_iq_perd_res);
950 priv->calib_results.tx_iq_perd_res = NULL;
951 priv->calib_results.tx_iq_perd_res_len = 0;
952}
953EXPORT_SYMBOL(iwl_free_calib_results);
6ba87956 954
630fe9b6
TW		 955int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
956{
957 int ret = 0;
958 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
959 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
960 priv->tx_power_user_lmt);
961 return -EINVAL;
962 }
963
964 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
965 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
966 priv->tx_power_user_lmt);
967 return -EINVAL;
968 }
969
970 if (priv->tx_power_user_lmt != tx_power)
971 force = true;
972
973 priv->tx_power_user_lmt = tx_power;
974
975 if (force && priv->cfg->ops->lib->send_tx_power)
976 ret = priv->cfg->ops->lib->send_tx_power(priv);
977
978 return ret;
979}
980EXPORT_SYMBOL(iwl_set_tx_power);
981
982
6ba87956 983void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 984{
7c616cba 985 iwl_free_calib_results(priv);
6ba87956
TW		 986 iwlcore_free_geos(priv);
987 iwl_free_channel_map(priv);
261415f7 988 kfree(priv->scan);
bf85ea4f 989}
6ba87956 990EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 991
49ea8596
EG		 992int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
993{
994 u32 stat_flags = 0;
995 struct iwl_host_cmd cmd = {
996 .id = REPLY_STATISTICS_CMD,
997 .meta.flags = flags,
998 .len = sizeof(stat_flags),
999 .data = (u8 *) &stat_flags,
1000 };
1001 return iwl_send_cmd(priv, &cmd);
1002}
1003EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1004
b0692f2f
EG		 1005/**
1006 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1007 * using sample data 100 bytes apart. If these sample points are good,
1008 * it's a pretty good bet that everything between them is good, too.
1009 */
1010static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1011{
1012 u32 val;
1013 int ret = 0;
1014 u32 errcnt = 0;
1015 u32 i;
1016
1017 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1018
1019 ret = iwl_grab_nic_access(priv);
1020 if (ret)
1021 return ret;
1022
1023 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1024 /* read data comes through single port, auto-incr addr */
1025 /* NOTE: Use the debugless read so we don't flood kernel log
1026 * if IWL_DL_IO is set */
1027 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1028 i + RTC_INST_LOWER_BOUND);
1029 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1030 if (val != le32_to_cpu(*image)) {
1031 ret = -EIO;
1032 errcnt++;
1033 if (errcnt >= 3)
1034 break;
1035 }
1036 }
1037
1038 iwl_release_nic_access(priv);
1039
1040 return ret;
1041}
1042
1043/**
1044 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1045 * looking at all data.
1046 */
1047static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1048 u32 len)
1049{
1050 u32 val;
1051 u32 save_len = len;
1052 int ret = 0;
1053 u32 errcnt;
1054
1055 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1056
1057 ret = iwl_grab_nic_access(priv);
1058 if (ret)
1059 return ret;
1060
1061 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1062
1063 errcnt = 0;
1064 for (; len > 0; len -= sizeof(u32), image++) {
1065 /* read data comes through single port, auto-incr addr */
1066 /* NOTE: Use the debugless read so we don't flood kernel log
1067 * if IWL_DL_IO is set */
1068 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1069 if (val != le32_to_cpu(*image)) {
1070 IWL_ERROR("uCode INST section is invalid at "
1071 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1072 save_len - len, val, le32_to_cpu(*image));
1073 ret = -EIO;
1074 errcnt++;
1075 if (errcnt >= 20)
1076 break;
1077 }
1078 }
1079
1080 iwl_release_nic_access(priv);
1081
1082 if (!errcnt)
1083 IWL_DEBUG_INFO
1084 ("ucode image in INSTRUCTION memory is good\n");
1085
1086 return ret;
1087}
1088
1089/**
1090 * iwl_verify_ucode - determine which instruction image is in SRAM,
1091 * and verify its contents
1092 */
1093int iwl_verify_ucode(struct iwl_priv *priv)
1094{
1095 __le32 *image;
1096 u32 len;
1097 int ret;
1098
1099 /* Try bootstrap */
1100 image = (__le32 *)priv->ucode_boot.v_addr;
1101 len = priv->ucode_boot.len;
1102 ret = iwlcore_verify_inst_sparse(priv, image, len);
1103 if (!ret) {
1104 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1105 return 0;
1106 }
1107
1108 /* Try initialize */
1109 image = (__le32 *)priv->ucode_init.v_addr;
1110 len = priv->ucode_init.len;
1111 ret = iwlcore_verify_inst_sparse(priv, image, len);
1112 if (!ret) {
1113 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1114 return 0;
1115 }
1116
1117 /* Try runtime/protocol */
1118 image = (__le32 *)priv->ucode_code.v_addr;
1119 len = priv->ucode_code.len;
1120 ret = iwlcore_verify_inst_sparse(priv, image, len);
1121 if (!ret) {
1122 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1123 return 0;
1124 }
1125
1126 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1127
1128 /* Since nothing seems to match, show first several data entries in
1129 * instruction SRAM, so maybe visual inspection will give a clue.
1130 * Selection of bootstrap image (vs. other images) is arbitrary. */
1131 image = (__le32 *)priv->ucode_boot.v_addr;
1132 len = priv->ucode_boot.len;
1133 ret = iwl_verify_inst_full(priv, image, len);
1134
1135 return ret;
1136}
1137EXPORT_SYMBOL(iwl_verify_ucode);
1138
189a2b59 1139
ede0cba4
EK		 1140static const char *desc_lookup(int i)
1141{
1142 switch (i) {
1143 case 1:
1144 return "FAIL";
1145 case 2:
1146 return "BAD_PARAM";
1147 case 3:
1148 return "BAD_CHECKSUM";
1149 case 4:
1150 return "NMI_INTERRUPT";
1151 case 5:
1152 return "SYSASSERT";
1153 case 6:
1154 return "FATAL_ERROR";
1155 }
1156
1157 return "UNKNOWN";
1158}
1159
1160#define ERROR_START_OFFSET (1 * sizeof(u32))
1161#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1162
1163void iwl_dump_nic_error_log(struct iwl_priv *priv)
1164{
1165 u32 data2, line;
1166 u32 desc, time, count, base, data1;
1167 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1168 int ret;
ede0cba4 1169
e1dfc085
GG		 1170 if (priv->ucode_type == UCODE_INIT)
1171 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1172 else
1173 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1174
1175 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1176 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1177 return;
1178 }
1179
e1dfc085
GG		 1180 ret = iwl_grab_nic_access(priv);
1181 if (ret) {
ede0cba4
EK		 1182 IWL_WARNING("Can not read from adapter at this time.\n");
1183 return;
1184 }
1185
1186 count = iwl_read_targ_mem(priv, base);
1187
1188 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1189 IWL_ERROR("Start IWL Error Log Dump:\n");
1190 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1191 }
1192
1193 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1194 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1195 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1196 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1197 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1198 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1199 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1200 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1201 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1202
1203 IWL_ERROR("Desc Time "
1204 "data1 data2 line\n");
1205 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1206 desc_lookup(desc), desc, time, data1, data2, line);
1207 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1208 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1209 ilink1, ilink2);
1210
1211 iwl_release_nic_access(priv);
1212}
1213EXPORT_SYMBOL(iwl_dump_nic_error_log);
1214
189a2b59
EK		 1215#define EVENT_START_OFFSET (4 * sizeof(u32))
1216
1217/**
1218 * iwl_print_event_log - Dump error event log to syslog
1219 *
1220 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1221 */
1222void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1223 u32 num_events, u32 mode)
1224{
1225 u32 i;
1226 u32 base; /* SRAM byte address of event log header */
1227 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1228 u32 ptr; /* SRAM byte address of log data */
1229 u32 ev, time, data; /* event log data */
1230
1231 if (num_events == 0)
1232 return;
e1dfc085
GG		 1233 if (priv->ucode_type == UCODE_INIT)
1234 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1235 else
1236 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1237
1238 if (mode == 0)
1239 event_size = 2 * sizeof(u32);
1240 else
1241 event_size = 3 * sizeof(u32);
1242
1243 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1244
1245 /* "time" is actually "data" for mode 0 (no timestamp).
1246 * place event id # at far right for easier visual parsing. */
1247 for (i = 0; i < num_events; i++) {
1248 ev = iwl_read_targ_mem(priv, ptr);
1249 ptr += sizeof(u32);
1250 time = iwl_read_targ_mem(priv, ptr);
1251 ptr += sizeof(u32);
77c5d08e
TW		 1252 if (mode == 0) {
1253 /* data, ev */
1254 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1255 } else {
189a2b59
EK		 1256 data = iwl_read_targ_mem(priv, ptr);
1257 ptr += sizeof(u32);
77c5d08e
TW		 1258 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1259 time, data, ev);
189a2b59
EK		 1260 }
1261 }
1262}
1263EXPORT_SYMBOL(iwl_print_event_log);
1264
1265
1266void iwl_dump_nic_event_log(struct iwl_priv *priv)
1267{
e1dfc085 1268 int ret;
189a2b59
EK		 1269 u32 base; /* SRAM byte address of event log header */
1270 u32 capacity; /* event log capacity in # entries */
1271 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1272 u32 num_wraps; /* # times uCode wrapped to top of log */
1273 u32 next_entry; /* index of next entry to be written by uCode */
1274 u32 size; /* # entries that we'll print */
1275
e1dfc085
GG		 1276 if (priv->ucode_type == UCODE_INIT)
1277 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1278 else
1279 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1280
189a2b59
EK		 1281 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1282 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1283 return;
1284 }
1285
e1dfc085
GG		 1286 ret = iwl_grab_nic_access(priv);
1287 if (ret) {
189a2b59
EK		 1288 IWL_WARNING("Can not read from adapter at this time.\n");
1289 return;
1290 }
1291
1292 /* event log header */
1293 capacity = iwl_read_targ_mem(priv, base);
1294 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1295 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1296 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1297
1298 size = num_wraps ? capacity : next_entry;
1299
1300 /* bail out if nothing in log */
1301 if (size == 0) {
1302 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1303 iwl_release_nic_access(priv);
1304 return;
1305 }
1306
1307 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1308 size, num_wraps);
1309
1310 /* if uCode has wrapped back to top of log, start at the oldest entry,
1311 * i.e the next one that uCode would fill. */
1312 if (num_wraps)
1313 iwl_print_event_log(priv, next_entry,
1314 capacity - next_entry, mode);
1315 /* (then/else) start at top of log */
1316 iwl_print_event_log(priv, 0, next_entry, mode);
1317
1318 iwl_release_nic_access(priv);
1319}
1320EXPORT_SYMBOL(iwl_dump_nic_event_log);
1321
47f4a587
EG		 1322void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1323{
1324 struct iwl_ct_kill_config cmd;
1325 unsigned long flags;
1326 int ret = 0;
1327
1328 spin_lock_irqsave(&priv->lock, flags);
1329 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1330 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1331 spin_unlock_irqrestore(&priv->lock, flags);
1332
1333 cmd.critical_temperature_R =
1334 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1335
47f4a587
EG		 1336 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1337 sizeof(cmd), &cmd);
1338 if (ret)
1339 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1340 else
1341 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1342 "critical temperature is %d\n",
1343 cmd.critical_temperature_R);
1344}
1345EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f
EG		 1346
1347/*
1348 * CARD_STATE_CMD
1349 *
1350 * Use: Sets the device's internal card state to enable, disable, or halt
1351 *
1352 * When in the 'enable' state the card operates as normal.
1353 * When in the 'disable' state, the card enters into a low power mode.
1354 * When in the 'halt' state, the card is shut down and must be fully
1355 * restarted to come back on.
1356 */
1357static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1358{
1359 struct iwl_host_cmd cmd = {
1360 .id = REPLY_CARD_STATE_CMD,
1361 .len = sizeof(u32),
1362 .data = &flags,
1363 .meta.flags = meta_flag,
1364 };
1365
1366 return iwl_send_cmd(priv, &cmd);
1367}
1368
1369void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1370{
1371 unsigned long flags;
1372
1373 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1374 return;
1375
1376 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1377
1378 iwl_scan_cancel(priv);
1379 /* FIXME: This is a workaround for AP */
1380 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1381 spin_lock_irqsave(&priv->lock, flags);
1382 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1383 CSR_UCODE_SW_BIT_RFKILL);
1384 spin_unlock_irqrestore(&priv->lock, flags);
1385 /* call the host command only if no hw rf-kill set */
1386 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1387 iwl_is_ready(priv))
1388 iwl_send_card_state(priv,
1389 CARD_STATE_CMD_DISABLE, 0);
1390 set_bit(STATUS_RF_KILL_SW, &priv->status);
1391 /* make sure mac80211 stop sending Tx frame */
1392 if (priv->mac80211_registered)
1393 ieee80211_stop_queues(priv->hw);
1394 }
1395}
1396EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1397
1398int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1399{
1400 unsigned long flags;
1401
1402 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1403 return 0;
1404
1405 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1406
1407 spin_lock_irqsave(&priv->lock, flags);
1408 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1409
a9efa652
EG		 1410 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1411 * notification where it will clear SW rfkill status.
1412 * Setting it here would break the handler. Only if the
1413 * interface is down we can set here since we don't
1414 * receive any further notification.
1415 */
1416 if (!priv->is_open)
1417 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1418 spin_unlock_irqrestore(&priv->lock, flags);
1419
1420 /* wake up ucode */
1421 msleep(10);
1422
1423 spin_lock_irqsave(&priv->lock, flags);
1424 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1425 if (!iwl_grab_nic_access(priv))
1426 iwl_release_nic_access(priv);
1427 spin_unlock_irqrestore(&priv->lock, flags);
1428
1429 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1430 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1431 "disabled by HW switch\n");
1432 return 0;
1433 }
1434
a9efa652
EG		 1435 /* If the driver is already loaded, it will receive
1436 * CARD_STATE_NOTIFICATION notifications and the handler will
1437 * call restart to reload the driver.
1438 */
14a08a7f
EG		 1439 return 1;
1440}
1441EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux 6.x block layer and io_uring tree(s)