projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: move beacon handling to iwl4965-base.c
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
3e0d4cb1 42#include "iwl-dev.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
5083e563 47#include "iwl-sta.h"
b481de9c 48
630fe9b6 49static int iwl4965_send_tx_power(struct iwl_priv *priv);
91dbc5bd 50static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
630fe9b6 51
d16dc48a
TW		 52/* Change firmware file name, using "-" and incrementing number,
53 * *only* when uCode interface or architecture changes so that it
54 * is not compatible with earlier drivers.
55 * This number will also appear in << 8 position of 1st dword of uCode file */
56#define IWL4965_UCODE_API "-2"
57
58
1ea87396
AK		 59/* module parameters */
60static struct iwl_mod_params iwl4965_mod_params = {
038669e4 61 .num_of_queues = IWL49_NUM_QUEUES,
9f17b318 62 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
1ea87396
AK		 63 .enable_qos = 1,
64 .amsdu_size_8K = 1,
3a1081e8 65 .restart_fw = 1,
1ea87396
AK		 66 /* the rest are 0 by default */
67};
68
57aab75a
TW		 69/* check contents of special bootstrap uCode SRAM */
70static int iwl4965_verify_bsm(struct iwl_priv *priv)
71{
72 __le32 *image = priv->ucode_boot.v_addr;
73 u32 len = priv->ucode_boot.len;
74 u32 reg;
75 u32 val;
76
77 IWL_DEBUG_INFO("Begin verify bsm\n");
78
79 /* verify BSM SRAM contents */
80 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
81 for (reg = BSM_SRAM_LOWER_BOUND;
82 reg < BSM_SRAM_LOWER_BOUND + len;
83 reg += sizeof(u32), image++) {
84 val = iwl_read_prph(priv, reg);
85 if (val != le32_to_cpu(*image)) {
86 IWL_ERROR("BSM uCode verification failed at "
87 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
88 BSM_SRAM_LOWER_BOUND,
89 reg - BSM_SRAM_LOWER_BOUND, len,
90 val, le32_to_cpu(*image));
91 return -EIO;
92 }
93 }
94
95 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
96
97 return 0;
98}
99
100/**
101 * iwl4965_load_bsm - Load bootstrap instructions
102 *
103 * BSM operation:
104 *
105 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
106 * in special SRAM that does not power down during RFKILL. When powering back
107 * up after power-saving sleeps (or during initial uCode load), the BSM loads
108 * the bootstrap program into the on-board processor, and starts it.
109 *
110 * The bootstrap program loads (via DMA) instructions and data for a new
111 * program from host DRAM locations indicated by the host driver in the
112 * BSM_DRAM_* registers. Once the new program is loaded, it starts
113 * automatically.
114 *
115 * When initializing the NIC, the host driver points the BSM to the
116 * "initialize" uCode image. This uCode sets up some internal data, then
117 * notifies host via "initialize alive" that it is complete.
118 *
119 * The host then replaces the BSM_DRAM_* pointer values to point to the
120 * normal runtime uCode instructions and a backup uCode data cache buffer
121 * (filled initially with starting data values for the on-board processor),
122 * then triggers the "initialize" uCode to load and launch the runtime uCode,
123 * which begins normal operation.
124 *
125 * When doing a power-save shutdown, runtime uCode saves data SRAM into
126 * the backup data cache in DRAM before SRAM is powered down.
127 *
128 * When powering back up, the BSM loads the bootstrap program. This reloads
129 * the runtime uCode instructions and the backup data cache into SRAM,
130 * and re-launches the runtime uCode from where it left off.
131 */
132static int iwl4965_load_bsm(struct iwl_priv *priv)
133{
134 __le32 *image = priv->ucode_boot.v_addr;
135 u32 len = priv->ucode_boot.len;
136 dma_addr_t pinst;
137 dma_addr_t pdata;
138 u32 inst_len;
139 u32 data_len;
140 int i;
141 u32 done;
142 u32 reg_offset;
143 int ret;
144
145 IWL_DEBUG_INFO("Begin load bsm\n");
146
fe9b6b72
RR		 147 priv->ucode_type = UCODE_RT;
148
57aab75a
TW		 149 /* make sure bootstrap program is no larger than BSM's SRAM size */
150 if (len > IWL_MAX_BSM_SIZE)
151 return -EINVAL;
152
153 /* Tell bootstrap uCode where to find the "Initialize" uCode
154 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 155 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 156 * after the "initialize" uCode has run, to point to
2d87889f
TW		 157 * runtime/protocol instructions and backup data cache.
158 */
57aab75a
TW		 159 pinst = priv->ucode_init.p_addr >> 4;
160 pdata = priv->ucode_init_data.p_addr >> 4;
161 inst_len = priv->ucode_init.len;
162 data_len = priv->ucode_init_data.len;
163
164 ret = iwl_grab_nic_access(priv);
165 if (ret)
166 return ret;
167
168 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
169 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
170 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
171 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
172
173 /* Fill BSM memory with bootstrap instructions */
174 for (reg_offset = BSM_SRAM_LOWER_BOUND;
175 reg_offset < BSM_SRAM_LOWER_BOUND + len;
176 reg_offset += sizeof(u32), image++)
177 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
178
179 ret = iwl4965_verify_bsm(priv);
180 if (ret) {
181 iwl_release_nic_access(priv);
182 return ret;
183 }
184
185 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
186 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
187 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
188 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
189
190 /* Load bootstrap code into instruction SRAM now,
191 * to prepare to load "initialize" uCode */
192 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
193
194 /* Wait for load of bootstrap uCode to finish */
195 for (i = 0; i < 100; i++) {
196 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
197 if (!(done & BSM_WR_CTRL_REG_BIT_START))
198 break;
199 udelay(10);
200 }
201 if (i < 100)
202 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
203 else {
204 IWL_ERROR("BSM write did not complete!\n");
205 return -EIO;
206 }
207
208 /* Enable future boot loads whenever power management unit triggers it
209 * (e.g. when powering back up after power-save shutdown) */
210 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
211
212 iwl_release_nic_access(priv);
213
214 return 0;
215}
216
f3ccc08c
EG		 217/**
218 * iwl4965_set_ucode_ptrs - Set uCode address location
219 *
220 * Tell initialization uCode where to find runtime uCode.
221 *
222 * BSM registers initially contain pointers to initialization uCode.
223 * We need to replace them to load runtime uCode inst and data,
224 * and to save runtime data when powering down.
225 */
226static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
227{
228 dma_addr_t pinst;
229 dma_addr_t pdata;
230 unsigned long flags;
231 int ret = 0;
232
233 /* bits 35:4 for 4965 */
234 pinst = priv->ucode_code.p_addr >> 4;
235 pdata = priv->ucode_data_backup.p_addr >> 4;
236
237 spin_lock_irqsave(&priv->lock, flags);
238 ret = iwl_grab_nic_access(priv);
239 if (ret) {
240 spin_unlock_irqrestore(&priv->lock, flags);
241 return ret;
242 }
243
244 /* Tell bootstrap uCode where to find image to load */
245 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
246 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
247 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
248 priv->ucode_data.len);
249
250 /* Inst bytecount must be last to set up, bit 31 signals uCode
251 * that all new ptr/size info is in place */
252 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
253 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
254 iwl_release_nic_access(priv);
255
256 spin_unlock_irqrestore(&priv->lock, flags);
257
258 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
259
260 return ret;
261}
262
263/**
264 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
265 *
266 * Called after REPLY_ALIVE notification received from "initialize" uCode.
267 *
268 * The 4965 "initialize" ALIVE reply contains calibration data for:
269 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
270 * (3945 does not contain this data).
271 *
272 * Tell "initialize" uCode to go ahead and load the runtime uCode.
273*/
274static void iwl4965_init_alive_start(struct iwl_priv *priv)
275{
276 /* Check alive response for "valid" sign from uCode */
277 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
278 /* We had an error bringing up the hardware, so take it
279 * all the way back down so we can try again */
280 IWL_DEBUG_INFO("Initialize Alive failed.\n");
281 goto restart;
282 }
283
284 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
285 * This is a paranoid check, because we would not have gotten the
286 * "initialize" alive if code weren't properly loaded. */
287 if (iwl_verify_ucode(priv)) {
288 /* Runtime instruction load was bad;
289 * take it all the way back down so we can try again */
290 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
291 goto restart;
292 }
293
294 /* Calculate temperature */
91dbc5bd 295 priv->temperature = iwl4965_hw_get_temperature(priv);
f3ccc08c
EG		 296
297 /* Send pointers to protocol/runtime uCode image ... init code will
298 * load and launch runtime uCode, which will send us another "Alive"
299 * notification. */
300 IWL_DEBUG_INFO("Initialization Alive received.\n");
301 if (iwl4965_set_ucode_ptrs(priv)) {
302 /* Runtime instruction load won't happen;
303 * take it all the way back down so we can try again */
304 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
305 goto restart;
306 }
307 return;
308
309restart:
310 queue_work(priv->workqueue, &priv->restart);
311}
312
b481de9c
ZY		 313static int is_fat_channel(__le32 rxon_flags)
314{
315 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
316 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
317}
318
8614f360
TW		 319/*
320 * EEPROM handlers
321 */
322
323static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
324{
325 u16 eeprom_ver;
326 u16 calib_ver;
327
328 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
329
330 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
331
332 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
333 calib_ver < EEPROM_4965_TX_POWER_VERSION)
334 goto err;
335
336 return 0;
337err:
338 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
339 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
340 calib_ver, EEPROM_4965_TX_POWER_VERSION);
341 return -EINVAL;
342
343}
079a2533 344int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 345{
d8609652 346 int ret;
b481de9c
ZY		 347 unsigned long flags;
348
349 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 350 ret = iwl_grab_nic_access(priv);
d8609652 351 if (ret) {
b481de9c 352 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 353 return ret;
b481de9c
ZY		 354 }
355
6f4083aa 356 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 357 u32 val;
d8609652 358 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 359 &val);
b481de9c 360
6f4083aa 361 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 362 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 363 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
364 ~APMG_PS_CTRL_MSK_PWR_SRC);
365 }
366 } else {
3395f6e9 367 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 368 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
369 ~APMG_PS_CTRL_MSK_PWR_SRC);
370 }
b481de9c 371
3395f6e9 372 iwl_release_nic_access(priv);
b481de9c
ZY		 373 spin_unlock_irqrestore(&priv->lock, flags);
374
d8609652 375 return ret;
b481de9c
ZY		 376}
377
da1bc453
TW		 378/*
379 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
380 * must be called under priv->lock and mac access
381 */
382static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 383{
da1bc453 384 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 385}
386
91238714 387static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 388{
91238714 389 int ret = 0;
b481de9c 390
3395f6e9 391 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 392 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 393
8f061891
TW		 394 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
395 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
396 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
397
91238714
TW		 398 /* set "initialization complete" bit to move adapter
399 * D0U* --> D0A* state */
3395f6e9 400 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 401
91238714
TW		 402 /* wait for clock stabilization */
403 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
404 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
405 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
406 if (ret < 0) {
407 IWL_DEBUG_INFO("Failed to init the card\n");
408 goto out;
b481de9c
ZY		 409 }
410
91238714
TW		 411 ret = iwl_grab_nic_access(priv);
412 if (ret)
413 goto out;
b481de9c 414
91238714 415 /* enable DMA */
8f061891
TW		 416 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
417 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 418
419 udelay(20);
420
8f061891 421 /* disable L1-Active */
3395f6e9 422 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 423 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 424
3395f6e9 425 iwl_release_nic_access(priv);
91238714 426out:
91238714
TW		 427 return ret;
428}
429
694cc56d
TW		 430
431static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 432{
433 unsigned long flags;
91238714 434 u32 val;
694cc56d
TW		 435 u16 radio_cfg;
436 u8 val_link;
6f4083aa 437
b481de9c
ZY		 438 spin_lock_irqsave(&priv->lock, flags);
439
b661c819 440 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 441 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
442 /* Enable No Snoop field */
443 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
444 val & ~(1 << 11));
445 }
446
b481de9c
ZY		 447 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
448
8f061891
TW		 449 /* L1 is enabled by BIOS */
450 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
451 /* diable L0S disabled L1A enabled */
452 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
453 else
454 /* L0S enabled L1A disabled */
455 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 456
694cc56d 457 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 458
694cc56d
TW		 459 /* write radio config values to register */
460 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
461 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
462 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
463 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
464 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 465
694cc56d 466 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 467 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 468 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
469 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 470
694cc56d
TW		 471 priv->calib_info = (struct iwl_eeprom_calib_info *)
472 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
473
474 spin_unlock_irqrestore(&priv->lock, flags);
475}
476
46315e01
TW		 477static int iwl4965_apm_stop_master(struct iwl_priv *priv)
478{
479 int ret = 0;
480 unsigned long flags;
481
482 spin_lock_irqsave(&priv->lock, flags);
483
484 /* set stop master bit */
485 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
486
487 ret = iwl_poll_bit(priv, CSR_RESET,
488 CSR_RESET_REG_FLAG_MASTER_DISABLED,
489 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
490 if (ret < 0)
491 goto out;
492
493out:
494 spin_unlock_irqrestore(&priv->lock, flags);
495 IWL_DEBUG_INFO("stop master\n");
496
497 return ret;
498}
499
f118a91d
TW		 500static void iwl4965_apm_stop(struct iwl_priv *priv)
501{
502 unsigned long flags;
503
46315e01 504 iwl4965_apm_stop_master(priv);
f118a91d
TW		 505
506 spin_lock_irqsave(&priv->lock, flags);
507
508 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
509
510 udelay(10);
511
512 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
513 spin_unlock_irqrestore(&priv->lock, flags);
514}
515
7f066108 516static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 517{
7f066108 518 int ret = 0;
b481de9c
ZY		 519 unsigned long flags;
520
46315e01 521 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 522
523 spin_lock_irqsave(&priv->lock, flags);
524
3395f6e9 525 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 526
527 udelay(10);
528
7f066108
TW		 529 /* FIXME: put here L1A -L0S w/a */
530
3395f6e9 531 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 532
7f066108 533 ret = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 534 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
535 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
536
7f066108
TW		 537 if (ret)
538 goto out;
539
b481de9c
ZY		 540 udelay(10);
541
7f066108
TW		 542 ret = iwl_grab_nic_access(priv);
543 if (ret)
544 goto out;
545 /* Enable DMA and BSM Clock */
546 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
547 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 548
7f066108 549 udelay(10);
b481de9c 550
7f066108
TW		 551 /* disable L1A */
552 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
553 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 554
7f066108 555 iwl_release_nic_access(priv);
b481de9c
ZY		 556
557 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
558 wake_up_interruptible(&priv->wait_command_queue);
559
7f066108 560out:
b481de9c
ZY		 561 spin_unlock_irqrestore(&priv->lock, flags);
562
7f066108 563 return ret;
b481de9c
ZY		 564}
565
b481de9c
ZY		 566/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
567 * Called after every association, but this runs only once!
568 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 569static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 570{
f0832f13 571 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 572
3109ece1 573 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 574 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 575
576 memset(&cmd, 0, sizeof(cmd));
577 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
578 cmd.diff_gain_a = 0;
579 cmd.diff_gain_b = 0;
580 cmd.diff_gain_c = 0;
f0832f13
EG		 581 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
582 sizeof(cmd), &cmd))
583 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 584 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
585 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
586 }
b481de9c
ZY		 587}
588
f0832f13
EG		 589static void iwl4965_gain_computation(struct iwl_priv *priv,
590 u32 *average_noise,
591 u16 min_average_noise_antenna_i,
592 u32 min_average_noise)
b481de9c 593{
f0832f13
EG		 594 int i, ret;
595 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 596
f0832f13 597 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 598
f0832f13
EG		 599 for (i = 0; i < NUM_RX_CHAINS; i++) {
600 s32 delta_g = 0;
b481de9c 601
f0832f13
EG		 602 if (!(data->disconn_array[i]) &&
603 (data->delta_gain_code[i] ==
b481de9c 604 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 605 delta_g = average_noise[i] - min_average_noise;
606 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
607 data->delta_gain_code[i] =
608 min(data->delta_gain_code[i],
609 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
610
611 data->delta_gain_code[i] =
612 (data->delta_gain_code[i] | (1 << 2));
613 } else {
614 data->delta_gain_code[i] = 0;
b481de9c 615 }
b481de9c 616 }
f0832f13
EG		 617 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
618 data->delta_gain_code[0],
619 data->delta_gain_code[1],
620 data->delta_gain_code[2]);
b481de9c 621
f0832f13
EG		 622 /* Differential gain gets sent to uCode only once */
623 if (!data->radio_write) {
624 struct iwl4965_calibration_cmd cmd;
625 data->radio_write = 1;
b481de9c 626
f0832f13
EG		 627 memset(&cmd, 0, sizeof(cmd));
628 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
629 cmd.diff_gain_a = data->delta_gain_code[0];
630 cmd.diff_gain_b = data->delta_gain_code[1];
631 cmd.diff_gain_c = data->delta_gain_code[2];
632 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
633 sizeof(cmd), &cmd);
634 if (ret)
635 IWL_DEBUG_CALIB("fail sending cmd "
636 "REPLY_PHY_CALIBRATION_CMD \n");
637
638 /* TODO we might want recalculate
639 * rx_chain in rxon cmd */
640
641 /* Mark so we run this algo only once! */
642 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 643 }
f0832f13
EG		 644 data->chain_noise_a = 0;
645 data->chain_noise_b = 0;
646 data->chain_noise_c = 0;
647 data->chain_signal_a = 0;
648 data->chain_signal_b = 0;
649 data->chain_signal_c = 0;
650 data->beacon_count = 0;
b481de9c
ZY		 651}
652
a326a5d0
EG		 653static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
654 __le32 *tx_flags)
655{
656 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
657 *tx_flags |= TX_CMD_FLG_RTS_MSK;
658 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
659 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
660 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
661 *tx_flags |= TX_CMD_FLG_CTS_MSK;
662 }
663}
664
b481de9c
ZY		 665static void iwl4965_bg_txpower_work(struct work_struct *work)
666{
c79dd5b5 667 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 668 txpower_work);
669
670 /* If a scan happened to start before we got here
671 * then just return; the statistics notification will
672 * kick off another scheduled work to compensate for
673 * any temperature delta we missed here. */
674 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
675 test_bit(STATUS_SCANNING, &priv->status))
676 return;
677
678 mutex_lock(&priv->mutex);
679
680 /* Regardless of if we are assocaited, we must reconfigure the
681 * TX power since frames can be sent on non-radar channels while
682 * not associated */
630fe9b6 683 iwl4965_send_tx_power(priv);
b481de9c
ZY		 684
685 /* Update last_temperature to keep is_calib_needed from running
686 * when it isn't needed... */
687 priv->last_temperature = priv->temperature;
688
689 mutex_unlock(&priv->mutex);
690}
691
692/*
693 * Acquire priv->lock before calling this function !
694 */
c79dd5b5 695static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 696{
3395f6e9 697 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 698 (index & 0xff) | (txq_id << 8));
12a81f60 699 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 700}
701
8b6eaea8
CB		 702/**
703 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
704 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
705 * @scd_retry: (1) Indicates queue will be used in aggregation mode
706 *
707 * NOTE: Acquire priv->lock before calling this function !
b481de9c 708 */
c79dd5b5 709static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 710 struct iwl_tx_queue *txq,
b481de9c
ZY		 711 int tx_fifo_id, int scd_retry)
712{
713 int txq_id = txq->q.id;
8b6eaea8
CB		 714
715 /* Find out whether to activate Tx queue */
b481de9c
ZY		 716 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
717
8b6eaea8 718 /* Set up and activate */
12a81f60 719 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 720 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
721 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
722 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
723 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
724 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 725
726 txq->sched_retry = scd_retry;
727
728 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 729 active ? "Activate" : "Deactivate",
b481de9c
ZY		 730 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
731}
732
733static const u16 default_queue_to_tx_fifo[] = {
734 IWL_TX_FIFO_AC3,
735 IWL_TX_FIFO_AC2,
736 IWL_TX_FIFO_AC1,
737 IWL_TX_FIFO_AC0,
038669e4 738 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 739 IWL_TX_FIFO_HCCA_1,
740 IWL_TX_FIFO_HCCA_2
741};
742
be1f3ab6 743static int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 744{
745 u32 a;
746 int i = 0;
747 unsigned long flags;
857485c0 748 int ret;
b481de9c
ZY		 749
750 spin_lock_irqsave(&priv->lock, flags);
751
3395f6e9 752 ret = iwl_grab_nic_access(priv);
857485c0 753 if (ret) {
b481de9c 754 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 755 return ret;
b481de9c
ZY		 756 }
757
8b6eaea8 758 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 759 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 760 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
761 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 762 iwl_write_targ_mem(priv, a, 0);
038669e4 763 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 764 iwl_write_targ_mem(priv, a, 0);
5425e490 765 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 766 iwl_write_targ_mem(priv, a, 0);
b481de9c 767
8b6eaea8 768 /* Tel 4965 where to find Tx byte count tables */
12a81f60 769 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 770 (priv->shared_phys +
bb8c093b 771 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 772
773 /* Disable chain mode for all queues */
12a81f60 774 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 775
8b6eaea8 776 /* Initialize each Tx queue (including the command queue) */
5425e490 777 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 778
779 /* TFD circular buffer read/write indexes */
12a81f60 780 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 781 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 782
783 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 784 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 785 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
786 (SCD_WIN_SIZE <<
787 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
788 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 789
790 /* Frame limit */
3395f6e9 791 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 792 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
793 sizeof(u32),
794 (SCD_FRAME_LIMIT <<
795 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
796 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 797
798 }
12a81f60 799 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 800 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 801
8b6eaea8 802 /* Activate all Tx DMA/FIFO channels */
da1bc453 803 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
b481de9c
ZY		 804
805 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 806
807 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 808 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
809 int ac = default_queue_to_tx_fifo[i];
36470749 810 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 811 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
812 }
813
3395f6e9 814 iwl_release_nic_access(priv);
b481de9c
ZY		 815 spin_unlock_irqrestore(&priv->lock, flags);
816
857485c0 817 return ret;
b481de9c
ZY		 818}
819
f0832f13
EG		 820static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
821 .min_nrg_cck = 97,
822 .max_nrg_cck = 0,
823
824 .auto_corr_min_ofdm = 85,
825 .auto_corr_min_ofdm_mrc = 170,
826 .auto_corr_min_ofdm_x1 = 105,
827 .auto_corr_min_ofdm_mrc_x1 = 220,
828
829 .auto_corr_max_ofdm = 120,
830 .auto_corr_max_ofdm_mrc = 210,
831 .auto_corr_max_ofdm_x1 = 140,
832 .auto_corr_max_ofdm_mrc_x1 = 270,
833
834 .auto_corr_min_cck = 125,
835 .auto_corr_max_cck = 200,
836 .auto_corr_min_cck_mrc = 200,
837 .auto_corr_max_cck_mrc = 400,
838
839 .nrg_th_cck = 100,
840 .nrg_th_ofdm = 100,
841};
f0832f13 842
8b6eaea8 843/**
5425e490 844 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 845 *
846 * Called when initializing driver
847 */
be1f3ab6 848static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 849{
316c30d9 850
038669e4 851 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 852 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 853 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 854 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 855 return -EINVAL;
316c30d9 856 }
b481de9c 857
5425e490 858 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 859 priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
5425e490
TW		 860 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
861 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
099b40b7
RR		 862 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
863 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
864 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
865 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
866
ec35cf2a
TW		 867 priv->hw_params.tx_chains_num = 2;
868 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 869 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
870 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 871 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
872
f0832f13 873 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 874
059ff826 875 return 0;
b481de9c
ZY		 876}
877
b481de9c
ZY		 878static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
879{
880 s32 sign = 1;
881
882 if (num < 0) {
883 sign = -sign;
884 num = -num;
885 }
886 if (denom < 0) {
887 sign = -sign;
888 denom = -denom;
889 }
890 *res = 1;
891 *res = ((num * 2 + denom) / (denom * 2)) * sign;
892
893 return 1;
894}
895
8b6eaea8
CB		 896/**
897 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
898 *
899 * Determines power supply voltage compensation for txpower calculations.
900 * Returns number of 1/2-dB steps to subtract from gain table index,
901 * to compensate for difference between power supply voltage during
902 * factory measurements, vs. current power supply voltage.
903 *
904 * Voltage indication is higher for lower voltage.
905 * Lower voltage requires more gain (lower gain table index).
906 */
b481de9c
ZY		 907static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
908 s32 current_voltage)
909{
910 s32 comp = 0;
911
912 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
913 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
914 return 0;
915
916 iwl4965_math_div_round(current_voltage - eeprom_voltage,
917 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
918
919 if (current_voltage > eeprom_voltage)
920 comp *= 2;
921 if ((comp < -2) || (comp > 2))
922 comp = 0;
923
924 return comp;
925}
926
b481de9c
ZY		 927static s32 iwl4965_get_tx_atten_grp(u16 channel)
928{
929 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
930 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
931 return CALIB_CH_GROUP_5;
932
933 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
934 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
935 return CALIB_CH_GROUP_1;
936
937 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
938 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
939 return CALIB_CH_GROUP_2;
940
941 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
942 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
943 return CALIB_CH_GROUP_3;
944
945 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
946 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
947 return CALIB_CH_GROUP_4;
948
949 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
950 return -1;
951}
952
c79dd5b5 953static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 954{
955 s32 b = -1;
956
957 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 958 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 959 continue;
960
073d3f5f
TW		 961 if ((channel >= priv->calib_info->band_info[b].ch_from)
962 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 963 break;
964 }
965
966 return b;
967}
968
969static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
970{
971 s32 val;
972
973 if (x2 == x1)
974 return y1;
975 else {
976 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
977 return val + y2;
978 }
979}
980
8b6eaea8
CB		 981/**
982 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
983 *
984 * Interpolates factory measurements from the two sample channels within a
985 * sub-band, to apply to channel of interest. Interpolation is proportional to
986 * differences in channel frequencies, which is proportional to differences
987 * in channel number.
988 */
c79dd5b5 989static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 990 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 991{
992 s32 s = -1;
993 u32 c;
994 u32 m;
073d3f5f
TW		 995 const struct iwl_eeprom_calib_measure *m1;
996 const struct iwl_eeprom_calib_measure *m2;
997 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 998 u32 ch_i1;
999 u32 ch_i2;
1000
1001 s = iwl4965_get_sub_band(priv, channel);
1002 if (s >= EEPROM_TX_POWER_BANDS) {
1003 IWL_ERROR("Tx Power can not find channel %d ", channel);
1004 return -1;
1005 }
1006
073d3f5f
TW		 1007 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1008 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1009 chan_info->ch_num = (u8) channel;
1010
1011 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1012 channel, s, ch_i1, ch_i2);
1013
1014 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1015 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1016 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1017 measurements[c][m]);
073d3f5f 1018 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1019 measurements[c][m]);
1020 omeas = &(chan_info->measurements[c][m]);
1021
1022 omeas->actual_pow =
1023 (u8) iwl4965_interpolate_value(channel, ch_i1,
1024 m1->actual_pow,
1025 ch_i2,
1026 m2->actual_pow);
1027 omeas->gain_idx =
1028 (u8) iwl4965_interpolate_value(channel, ch_i1,
1029 m1->gain_idx, ch_i2,
1030 m2->gain_idx);
1031 omeas->temperature =
1032 (u8) iwl4965_interpolate_value(channel, ch_i1,
1033 m1->temperature,
1034 ch_i2,
1035 m2->temperature);
1036 omeas->pa_det =
1037 (s8) iwl4965_interpolate_value(channel, ch_i1,
1038 m1->pa_det, ch_i2,
1039 m2->pa_det);
1040
1041 IWL_DEBUG_TXPOWER
1042 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1043 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1044 IWL_DEBUG_TXPOWER
1045 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1046 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1047 IWL_DEBUG_TXPOWER
1048 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1049 m1->pa_det, m2->pa_det, omeas->pa_det);
1050 IWL_DEBUG_TXPOWER
1051 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1052 m1->temperature, m2->temperature,
1053 omeas->temperature);
1054 }
1055 }
1056
1057 return 0;
1058}
1059
1060/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1061 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1062static s32 back_off_table[] = {
1063 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1064 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1065 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1066 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1067 10 /* CCK */
1068};
1069
1070/* Thermal compensation values for txpower for various frequency ranges ...
1071 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1072static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1073 s32 degrees_per_05db_a;
1074 s32 degrees_per_05db_a_denom;
1075} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1076 {9, 2}, /* group 0 5.2, ch 34-43 */
1077 {4, 1}, /* group 1 5.2, ch 44-70 */
1078 {4, 1}, /* group 2 5.2, ch 71-124 */
1079 {4, 1}, /* group 3 5.2, ch 125-200 */
1080 {3, 1} /* group 4 2.4, ch all */
1081};
1082
1083static s32 get_min_power_index(s32 rate_power_index, u32 band)
1084{
1085 if (!band) {
1086 if ((rate_power_index & 7) <= 4)
1087 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1088 }
1089 return MIN_TX_GAIN_INDEX;
1090}
1091
1092struct gain_entry {
1093 u8 dsp;
1094 u8 radio;
1095};
1096
1097static const struct gain_entry gain_table[2][108] = {
1098 /* 5.2GHz power gain index table */
1099 {
1100 {123, 0x3F}, /* highest txpower */
1101 {117, 0x3F},
1102 {110, 0x3F},
1103 {104, 0x3F},
1104 {98, 0x3F},
1105 {110, 0x3E},
1106 {104, 0x3E},
1107 {98, 0x3E},
1108 {110, 0x3D},
1109 {104, 0x3D},
1110 {98, 0x3D},
1111 {110, 0x3C},
1112 {104, 0x3C},
1113 {98, 0x3C},
1114 {110, 0x3B},
1115 {104, 0x3B},
1116 {98, 0x3B},
1117 {110, 0x3A},
1118 {104, 0x3A},
1119 {98, 0x3A},
1120 {110, 0x39},
1121 {104, 0x39},
1122 {98, 0x39},
1123 {110, 0x38},
1124 {104, 0x38},
1125 {98, 0x38},
1126 {110, 0x37},
1127 {104, 0x37},
1128 {98, 0x37},
1129 {110, 0x36},
1130 {104, 0x36},
1131 {98, 0x36},
1132 {110, 0x35},
1133 {104, 0x35},
1134 {98, 0x35},
1135 {110, 0x34},
1136 {104, 0x34},
1137 {98, 0x34},
1138 {110, 0x33},
1139 {104, 0x33},
1140 {98, 0x33},
1141 {110, 0x32},
1142 {104, 0x32},
1143 {98, 0x32},
1144 {110, 0x31},
1145 {104, 0x31},
1146 {98, 0x31},
1147 {110, 0x30},
1148 {104, 0x30},
1149 {98, 0x30},
1150 {110, 0x25},
1151 {104, 0x25},
1152 {98, 0x25},
1153 {110, 0x24},
1154 {104, 0x24},
1155 {98, 0x24},
1156 {110, 0x23},
1157 {104, 0x23},
1158 {98, 0x23},
1159 {110, 0x22},
1160 {104, 0x18},
1161 {98, 0x18},
1162 {110, 0x17},
1163 {104, 0x17},
1164 {98, 0x17},
1165 {110, 0x16},
1166 {104, 0x16},
1167 {98, 0x16},
1168 {110, 0x15},
1169 {104, 0x15},
1170 {98, 0x15},
1171 {110, 0x14},
1172 {104, 0x14},
1173 {98, 0x14},
1174 {110, 0x13},
1175 {104, 0x13},
1176 {98, 0x13},
1177 {110, 0x12},
1178 {104, 0x08},
1179 {98, 0x08},
1180 {110, 0x07},
1181 {104, 0x07},
1182 {98, 0x07},
1183 {110, 0x06},
1184 {104, 0x06},
1185 {98, 0x06},
1186 {110, 0x05},
1187 {104, 0x05},
1188 {98, 0x05},
1189 {110, 0x04},
1190 {104, 0x04},
1191 {98, 0x04},
1192 {110, 0x03},
1193 {104, 0x03},
1194 {98, 0x03},
1195 {110, 0x02},
1196 {104, 0x02},
1197 {98, 0x02},
1198 {110, 0x01},
1199 {104, 0x01},
1200 {98, 0x01},
1201 {110, 0x00},
1202 {104, 0x00},
1203 {98, 0x00},
1204 {93, 0x00},
1205 {88, 0x00},
1206 {83, 0x00},
1207 {78, 0x00},
1208 },
1209 /* 2.4GHz power gain index table */
1210 {
1211 {110, 0x3f}, /* highest txpower */
1212 {104, 0x3f},
1213 {98, 0x3f},
1214 {110, 0x3e},
1215 {104, 0x3e},
1216 {98, 0x3e},
1217 {110, 0x3d},
1218 {104, 0x3d},
1219 {98, 0x3d},
1220 {110, 0x3c},
1221 {104, 0x3c},
1222 {98, 0x3c},
1223 {110, 0x3b},
1224 {104, 0x3b},
1225 {98, 0x3b},
1226 {110, 0x3a},
1227 {104, 0x3a},
1228 {98, 0x3a},
1229 {110, 0x39},
1230 {104, 0x39},
1231 {98, 0x39},
1232 {110, 0x38},
1233 {104, 0x38},
1234 {98, 0x38},
1235 {110, 0x37},
1236 {104, 0x37},
1237 {98, 0x37},
1238 {110, 0x36},
1239 {104, 0x36},
1240 {98, 0x36},
1241 {110, 0x35},
1242 {104, 0x35},
1243 {98, 0x35},
1244 {110, 0x34},
1245 {104, 0x34},
1246 {98, 0x34},
1247 {110, 0x33},
1248 {104, 0x33},
1249 {98, 0x33},
1250 {110, 0x32},
1251 {104, 0x32},
1252 {98, 0x32},
1253 {110, 0x31},
1254 {104, 0x31},
1255 {98, 0x31},
1256 {110, 0x30},
1257 {104, 0x30},
1258 {98, 0x30},
1259 {110, 0x6},
1260 {104, 0x6},
1261 {98, 0x6},
1262 {110, 0x5},
1263 {104, 0x5},
1264 {98, 0x5},
1265 {110, 0x4},
1266 {104, 0x4},
1267 {98, 0x4},
1268 {110, 0x3},
1269 {104, 0x3},
1270 {98, 0x3},
1271 {110, 0x2},
1272 {104, 0x2},
1273 {98, 0x2},
1274 {110, 0x1},
1275 {104, 0x1},
1276 {98, 0x1},
1277 {110, 0x0},
1278 {104, 0x0},
1279 {98, 0x0},
1280 {97, 0},
1281 {96, 0},
1282 {95, 0},
1283 {94, 0},
1284 {93, 0},
1285 {92, 0},
1286 {91, 0},
1287 {90, 0},
1288 {89, 0},
1289 {88, 0},
1290 {87, 0},
1291 {86, 0},
1292 {85, 0},
1293 {84, 0},
1294 {83, 0},
1295 {82, 0},
1296 {81, 0},
1297 {80, 0},
1298 {79, 0},
1299 {78, 0},
1300 {77, 0},
1301 {76, 0},
1302 {75, 0},
1303 {74, 0},
1304 {73, 0},
1305 {72, 0},
1306 {71, 0},
1307 {70, 0},
1308 {69, 0},
1309 {68, 0},
1310 {67, 0},
1311 {66, 0},
1312 {65, 0},
1313 {64, 0},
1314 {63, 0},
1315 {62, 0},
1316 {61, 0},
1317 {60, 0},
1318 {59, 0},
1319 }
1320};
1321
c79dd5b5 1322static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1323 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1324 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1325{
1326 u8 saturation_power;
1327 s32 target_power;
1328 s32 user_target_power;
1329 s32 power_limit;
1330 s32 current_temp;
1331 s32 reg_limit;
1332 s32 current_regulatory;
1333 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1334 int i;
1335 int c;
bf85ea4f 1336 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1337 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1338 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1339 s16 voltage;
1340 s32 init_voltage;
1341 s32 voltage_compensation;
1342 s32 degrees_per_05db_num;
1343 s32 degrees_per_05db_denom;
1344 s32 factory_temp;
1345 s32 temperature_comp[2];
1346 s32 factory_gain_index[2];
1347 s32 factory_actual_pwr[2];
1348 s32 power_index;
1349
b481de9c
ZY		 1350 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1351 * are used for indexing into txpower table) */
630fe9b6 1352 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1353
1354 /* Get current (RXON) channel, band, width */
b481de9c
ZY		 1355 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1356 is_fat);
1357
630fe9b6
TW		 1358 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1359
1360 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1361 return -EINVAL;
1362
1363 /* get txatten group, used to select 1) thermal txpower adjustment
1364 * and 2) mimo txpower balance between Tx chains. */
1365 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1366 if (txatten_grp < 0)
1367 return -EINVAL;
1368
1369 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1370 channel, txatten_grp);
1371
1372 if (is_fat) {
1373 if (ctrl_chan_high)
1374 channel -= 2;
1375 else
1376 channel += 2;
1377 }
1378
1379 /* hardware txpower limits ...
1380 * saturation (clipping distortion) txpowers are in half-dBm */
1381 if (band)
073d3f5f 1382 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1383 else
073d3f5f 1384 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1385
1386 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1387 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1388 if (band)
1389 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1390 else
1391 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1392 }
1393
1394 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1395 * max_power_avg values are in dBm, convert * 2 */
1396 if (is_fat)
1397 reg_limit = ch_info->fat_max_power_avg * 2;
1398 else
1399 reg_limit = ch_info->max_power_avg * 2;
1400
1401 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1402 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1403 if (band)
1404 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1405 else
1406 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1407 }
1408
1409 /* Interpolate txpower calibration values for this channel,
1410 * based on factory calibration tests on spaced channels. */
1411 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1412
1413 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1414 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1415 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1416 voltage_compensation =
1417 iwl4965_get_voltage_compensation(voltage, init_voltage);
1418
1419 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1420 init_voltage,
1421 voltage, voltage_compensation);
1422
1423 /* get current temperature (Celsius) */
1424 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1425 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1426 current_temp = KELVIN_TO_CELSIUS(current_temp);
1427
1428 /* select thermal txpower adjustment params, based on channel group
1429 * (same frequency group used for mimo txatten adjustment) */
1430 degrees_per_05db_num =
1431 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1432 degrees_per_05db_denom =
1433 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1434
1435 /* get per-chain txpower values from factory measurements */
1436 for (c = 0; c < 2; c++) {
1437 measurement = &ch_eeprom_info.measurements[c][1];
1438
1439 /* txgain adjustment (in half-dB steps) based on difference
1440 * between factory and current temperature */
1441 factory_temp = measurement->temperature;
1442 iwl4965_math_div_round((current_temp - factory_temp) *
1443 degrees_per_05db_denom,
1444 degrees_per_05db_num,
1445 &temperature_comp[c]);
1446
1447 factory_gain_index[c] = measurement->gain_idx;
1448 factory_actual_pwr[c] = measurement->actual_pow;
1449
1450 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1451 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1452 "curr tmp %d, comp %d steps\n",
1453 factory_temp, current_temp,
1454 temperature_comp[c]);
1455
1456 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1457 factory_gain_index[c],
1458 factory_actual_pwr[c]);
1459 }
1460
1461 /* for each of 33 bit-rates (including 1 for CCK) */
1462 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1463 u8 is_mimo_rate;
bb8c093b 1464 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1465
1466 /* for mimo, reduce each chain's txpower by half
1467 * (3dB, 6 steps), so total output power is regulatory
1468 * compliant. */
1469 if (i & 0x8) {
1470 current_regulatory = reg_limit -
1471 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1472 is_mimo_rate = 1;
1473 } else {
1474 current_regulatory = reg_limit;
1475 is_mimo_rate = 0;
1476 }
1477
1478 /* find txpower limit, either hardware or regulatory */
1479 power_limit = saturation_power - back_off_table[i];
1480 if (power_limit > current_regulatory)
1481 power_limit = current_regulatory;
1482
1483 /* reduce user's txpower request if necessary
1484 * for this rate on this channel */
1485 target_power = user_target_power;
1486 if (target_power > power_limit)
1487 target_power = power_limit;
1488
1489 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1490 i, saturation_power - back_off_table[i],
1491 current_regulatory, user_target_power,
1492 target_power);
1493
1494 /* for each of 2 Tx chains (radio transmitters) */
1495 for (c = 0; c < 2; c++) {
1496 s32 atten_value;
1497
1498 if (is_mimo_rate)
1499 atten_value =
1500 (s32)le32_to_cpu(priv->card_alive_init.
1501 tx_atten[txatten_grp][c]);
1502 else
1503 atten_value = 0;
1504
1505 /* calculate index; higher index means lower txpower */
1506 power_index = (u8) (factory_gain_index[c] -
1507 (target_power -
1508 factory_actual_pwr[c]) -
1509 temperature_comp[c] -
1510 voltage_compensation +
1511 atten_value);
1512
1513/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1514 power_index); */
1515
1516 if (power_index < get_min_power_index(i, band))
1517 power_index = get_min_power_index(i, band);
1518
1519 /* adjust 5 GHz index to support negative indexes */
1520 if (!band)
1521 power_index += 9;
1522
1523 /* CCK, rate 32, reduce txpower for CCK */
1524 if (i == POWER_TABLE_CCK_ENTRY)
1525 power_index +=
1526 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1527
1528 /* stay within the table! */
1529 if (power_index > 107) {
1530 IWL_WARNING("txpower index %d > 107\n",
1531 power_index);
1532 power_index = 107;
1533 }
1534 if (power_index < 0) {
1535 IWL_WARNING("txpower index %d < 0\n",
1536 power_index);
1537 power_index = 0;
1538 }
1539
1540 /* fill txpower command for this rate/chain */
1541 tx_power.s.radio_tx_gain[c] =
1542 gain_table[band][power_index].radio;
1543 tx_power.s.dsp_predis_atten[c] =
1544 gain_table[band][power_index].dsp;
1545
1546 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1547 "gain 0x%02x dsp %d\n",
1548 c, atten_value, power_index,
1549 tx_power.s.radio_tx_gain[c],
1550 tx_power.s.dsp_predis_atten[c]);
1551 }/* for each chain */
1552
1553 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1554
1555 }/* for each rate */
1556
1557 return 0;
1558}
1559
1560/**
630fe9b6 1561 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1562 *
1563 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1564 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1565 */
630fe9b6 1566static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1567{
bb8c093b 1568 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1569 int ret;
b481de9c
ZY		 1570 u8 band = 0;
1571 u8 is_fat = 0;
1572 u8 ctrl_chan_high = 0;
1573
1574 if (test_bit(STATUS_SCANNING, &priv->status)) {
1575 /* If this gets hit a lot, switch it to a BUG() and catch
1576 * the stack trace to find out who is calling this during
1577 * a scan. */
1578 IWL_WARNING("TX Power requested while scanning!\n");
1579 return -EAGAIN;
1580 }
1581
8318d78a 1582 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1583
1584 is_fat = is_fat_channel(priv->active_rxon.flags);
1585
1586 if (is_fat &&
1587 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1588 ctrl_chan_high = 1;
1589
1590 cmd.band = band;
1591 cmd.channel = priv->active_rxon.channel;
1592
857485c0 1593 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1594 le16_to_cpu(priv->active_rxon.channel),
1595 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1596 if (ret)
1597 goto out;
b481de9c 1598
857485c0
TW		 1599 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1600
1601out:
1602 return ret;
b481de9c
ZY		 1603}
1604
7e8c519e
TW		 1605static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1606{
1607 int ret = 0;
1608 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1609 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1610 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1611
1612 if ((rxon1->flags == rxon2->flags) &&
1613 (rxon1->filter_flags == rxon2->filter_flags) &&
1614 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1615 (rxon1->ofdm_ht_single_stream_basic_rates ==
1616 rxon2->ofdm_ht_single_stream_basic_rates) &&
1617 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1618 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1619 (rxon1->rx_chain == rxon2->rx_chain) &&
1620 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1621 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1622 return 0;
1623 }
1624
1625 rxon_assoc.flags = priv->staging_rxon.flags;
1626 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1627 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1628 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1629 rxon_assoc.reserved = 0;
1630 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1631 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1632 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1633 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1634 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1635
1636 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1637 sizeof(rxon_assoc), &rxon_assoc, NULL);
1638 if (ret)
1639 return ret;
1640
1641 return ret;
1642}
1643
1644
c79dd5b5 1645int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1646{
1647 int rc;
1648 u8 band = 0;
1649 u8 is_fat = 0;
1650 u8 ctrl_chan_high = 0;
bb8c093b 1651 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1652 const struct iwl_channel_info *ch_info;
b481de9c 1653
8318d78a 1654 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1655
8622e705 1656 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1657
1658 is_fat = is_fat_channel(priv->staging_rxon.flags);
1659
1660 if (is_fat &&
1661 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1662 ctrl_chan_high = 1;
1663
1664 cmd.band = band;
1665 cmd.expect_beacon = 0;
1666 cmd.channel = cpu_to_le16(channel);
1667 cmd.rxon_flags = priv->active_rxon.flags;
1668 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1669 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1670 if (ch_info)
1671 cmd.expect_beacon = is_channel_radar(ch_info);
1672 else
1673 cmd.expect_beacon = 1;
1674
1675 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1676 ctrl_chan_high, &cmd.tx_power);
1677 if (rc) {
1678 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1679 return rc;
1680 }
1681
857485c0 1682 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1683 return rc;
1684}
1685
d67f5489 1686static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
b481de9c 1687{
059ff826
TW		 1688 struct iwl4965_shared *s = priv->shared_virt;
1689 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 1690}
1691
399f4900
RR		 1692static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
1693{
1694 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
1695 sizeof(struct iwl4965_shared),
1696 &priv->shared_phys);
1697 if (!priv->shared_virt)
1698 return -ENOMEM;
1699
1700 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
1701
d67f5489
RR		 1702 priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
1703
399f4900
RR		 1704 return 0;
1705}
1706
1707static void iwl4965_free_shared_mem(struct iwl_priv *priv)
1708{
1709 if (priv->shared_virt)
1710 pci_free_consistent(priv->pci_dev,
1711 sizeof(struct iwl4965_shared),
1712 priv->shared_virt,
1713 priv->shared_phys);
1714}
1715
8b6eaea8 1716/**
e2a722eb 1717 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1718 */
e2a722eb 1719static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1720 struct iwl_tx_queue *txq,
e2a722eb 1721 u16 byte_cnt)
b481de9c
ZY		 1722{
1723 int len;
1724 int txq_id = txq->q.id;
059ff826 1725 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 1726
b481de9c
ZY		 1727 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1728
8b6eaea8 1729 /* Set up byte count within first 256 entries */
b481de9c 1730 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 1731 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 1732
8b6eaea8 1733 /* If within first 64 entries, duplicate at end */
038669e4 1734 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
b481de9c 1735 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
038669e4 1736 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 1737 byte_cnt, len);
b481de9c
ZY		 1738}
1739
b481de9c
ZY		 1740/**
1741 * sign_extend - Sign extend a value using specified bit as sign-bit
1742 *
1743 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1744 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1745 *
1746 * @param oper value to sign extend
1747 * @param index 0 based bit index (0<=index<32) to sign bit
1748 */
1749static s32 sign_extend(u32 oper, int index)
1750{
1751 u8 shift = 31 - index;
1752
1753 return (s32)(oper << shift) >> shift;
1754}
1755
1756/**
91dbc5bd 1757 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
b481de9c
ZY		 1758 * @statistics: Provides the temperature reading from the uCode
1759 *
1760 * A return of <0 indicates bogus data in the statistics
1761 */
91dbc5bd 1762static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1763{
1764 s32 temperature;
1765 s32 vt;
1766 s32 R1, R2, R3;
1767 u32 R4;
1768
1769 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1770 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1771 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1772 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1773 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1774 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1775 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1776 } else {
1777 IWL_DEBUG_TEMP("Running temperature calibration\n");
1778 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1779 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1780 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1781 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1782 }
1783
1784 /*
8b6eaea8 1785 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1786 *
1787 * NOTE If we haven't received a statistics notification yet
1788 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 1789 * "initialize" ALIVE response.
1790 */
b481de9c
ZY		 1791 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1792 vt = sign_extend(R4, 23);
1793 else
1794 vt = sign_extend(
1795 le32_to_cpu(priv->statistics.general.temperature), 23);
1796
91dbc5bd 1797 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
b481de9c
ZY		 1798
1799 if (R3 == R1) {
1800 IWL_ERROR("Calibration conflict R1 == R3\n");
1801 return -1;
1802 }
1803
1804 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1805 * Add offset to center the adjustment around 0 degrees Centigrade. */
1806 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1807 temperature /= (R3 - R1);
91dbc5bd 1808 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
b481de9c 1809
91dbc5bd
EG		 1810 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n",
1811 temperature, KELVIN_TO_CELSIUS(temperature));
b481de9c
ZY		 1812
1813 return temperature;
1814}
1815
1816/* Adjust Txpower only if temperature variance is greater than threshold. */
1817#define IWL_TEMPERATURE_THRESHOLD 3
1818
1819/**
1820 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1821 *
1822 * If the temperature changed has changed sufficiently, then a recalibration
1823 * is needed.
1824 *
1825 * Assumes caller will replace priv->last_temperature once calibration
1826 * executed.
1827 */
c79dd5b5 1828static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1829{
1830 int temp_diff;
1831
1832 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1833 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
1834 return 0;
1835 }
1836
1837 temp_diff = priv->temperature - priv->last_temperature;
1838
1839 /* get absolute value */
1840 if (temp_diff < 0) {
1841 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
1842 temp_diff = -temp_diff;
1843 } else if (temp_diff == 0)
1844 IWL_DEBUG_POWER("Same temp, \n");
1845 else
1846 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
1847
1848 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1849 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
1850 return 0;
1851 }
1852
1853 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
1854
1855 return 1;
1856}
1857
5225640b 1858static void iwl4965_temperature_calib(struct iwl_priv *priv)
b481de9c 1859{
b481de9c 1860 s32 temp;
b481de9c 1861
91dbc5bd 1862 temp = iwl4965_hw_get_temperature(priv);
b481de9c
ZY		 1863 if (temp < 0)
1864 return;
1865
1866 if (priv->temperature != temp) {
1867 if (priv->temperature)
1868 IWL_DEBUG_TEMP("Temperature changed "
1869 "from %dC to %dC\n",
1870 KELVIN_TO_CELSIUS(priv->temperature),
1871 KELVIN_TO_CELSIUS(temp));
1872 else
1873 IWL_DEBUG_TEMP("Temperature "
1874 "initialized to %dC\n",
1875 KELVIN_TO_CELSIUS(temp));
1876 }
1877
1878 priv->temperature = temp;
1879 set_bit(STATUS_TEMPERATURE, &priv->status);
1880
203566f3
EG		 1881 if (!priv->disable_tx_power_cal &&
1882 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1883 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 1884 queue_work(priv->workqueue, &priv->txpower_work);
1885}
1886
fe01b477
RR		 1887/**
1888 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1889 */
c79dd5b5 1890static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 1891 u16 txq_id)
1892{
1893 /* Simply stop the queue, but don't change any configuration;
1894 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 1895 iwl_write_prph(priv,
12a81f60 1896 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 1897 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1898 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 1899}
b481de9c 1900
fe01b477 1901/**
7f3e4bb6 1902 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 1903 * priv->lock must be held by the caller
fe01b477 1904 */
30e553e3
TW		 1905static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1906 u16 ssn_idx, u8 tx_fifo)
fe01b477 1907{
b095d03a
RR		 1908 int ret = 0;
1909
9f17b318
TW		 1910 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1911 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1912 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1913 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1914 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
fe01b477 1915 return -EINVAL;
b481de9c
ZY		 1916 }
1917
3395f6e9 1918 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 1919 if (ret)
1920 return ret;
1921
fe01b477
RR		 1922 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1923
12a81f60 1924 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 1925
1926 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1927 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1928 /* supposes that ssn_idx is valid (!= 0xFFF) */
1929 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1930
12a81f60 1931 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 1932 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 1933 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1934
3395f6e9 1935 iwl_release_nic_access(priv);
b095d03a 1936
fe01b477
RR		 1937 return 0;
1938}
b481de9c 1939
8b6eaea8
CB		 1940/**
1941 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1942 */
c79dd5b5 1943static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 1944 u16 txq_id)
1945{
1946 u32 tbl_dw_addr;
1947 u32 tbl_dw;
1948 u16 scd_q2ratid;
1949
30e553e3 1950 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 1951
1952 tbl_dw_addr = priv->scd_base_addr +
038669e4 1953 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 1954
3395f6e9 1955 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 1956
1957 if (txq_id & 0x1)
1958 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1959 else
1960 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1961
3395f6e9 1962 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 1963
1964 return 0;
1965}
1966
fe01b477 1967
b481de9c 1968/**
8b6eaea8
CB		 1969 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1970 *
7f3e4bb6 1971 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 1972 * i.e. it must be one of the higher queues used for aggregation
b481de9c 1973 */
30e553e3
TW		 1974static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1975 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 1976{
1977 unsigned long flags;
30e553e3 1978 int ret;
b481de9c
ZY		 1979 u16 ra_tid;
1980
9f17b318
TW		 1981 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1982 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1983 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1984 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1985 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1986 return -EINVAL;
1987 }
b481de9c
ZY		 1988
1989 ra_tid = BUILD_RAxTID(sta_id, tid);
1990
8b6eaea8 1991 /* Modify device's station table to Tx this TID */
5083e563 1992 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 1993
1994 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 1995 ret = iwl_grab_nic_access(priv);
1996 if (ret) {
b481de9c 1997 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 1998 return ret;
b481de9c
ZY		 1999 }
2000
8b6eaea8 2001 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 2002 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
2003
8b6eaea8 2004 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 2005 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
2006
8b6eaea8 2007 /* Set this queue as a chain-building queue */
12a81f60 2008 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 2009
8b6eaea8
CB		 2010 /* Place first TFD at index corresponding to start sequence number.
2011 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 2012 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2013 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 2014 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
2015
8b6eaea8 2016 /* Set up Tx window size and frame limit for this queue */
3395f6e9 2017 iwl_write_targ_mem(priv,
038669e4
EG		 2018 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2019 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
2020 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 2021
3395f6e9 2022 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 2023 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2024 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
2025 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 2026
12a81f60 2027 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 2028
8b6eaea8 2029 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 2030 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
2031
3395f6e9 2032 iwl_release_nic_access(priv);
b481de9c
ZY		 2033 spin_unlock_irqrestore(&priv->lock, flags);
2034
2035 return 0;
2036}
2037
133636de 2038
c1adf9fb
GG		 2039static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
2040{
2041 switch (cmd_id) {
2042 case REPLY_RXON:
2043 return (u16) sizeof(struct iwl4965_rxon_cmd);
2044 default:
2045 return len;
2046 }
2047}
2048
133636de
TW		 2049static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2050{
2051 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
2052 addsta->mode = cmd->mode;
2053 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2054 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2055 addsta->station_flags = cmd->station_flags;
2056 addsta->station_flags_msk = cmd->station_flags_msk;
2057 addsta->tid_disable_tx = cmd->tid_disable_tx;
2058 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2059 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2060 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2061 addsta->reserved1 = __constant_cpu_to_le16(0);
2062 addsta->reserved2 = __constant_cpu_to_le32(0);
2063
2064 return (u16)sizeof(struct iwl4965_addsta_cmd);
2065}
f20217d9 2066
f20217d9
TW		 2067static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
2068{
25a6572c 2069 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 2070}
2071
2072/**
2073 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
2074 */
2075static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
2076 struct iwl_ht_agg *agg,
25a6572c
TW		 2077 struct iwl4965_tx_resp *tx_resp,
2078 int txq_id, u16 start_idx)
f20217d9
TW		 2079{
2080 u16 status;
25a6572c 2081 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 2082 struct ieee80211_tx_info *info = NULL;
2083 struct ieee80211_hdr *hdr = NULL;
e7d326ac 2084 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 2085 int i, sh, idx;
f20217d9 2086 u16 seq;
f20217d9
TW		 2087 if (agg->wait_for_ba)
2088 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
2089
2090 agg->frame_count = tx_resp->frame_count;
2091 agg->start_idx = start_idx;
e7d326ac 2092 agg->rate_n_flags = rate_n_flags;
f20217d9
TW		 2093 agg->bitmap = 0;
2094
2095 /* # frames attempted by Tx command */
2096 if (agg->frame_count == 1) {
2097 /* Only one frame was attempted; no block-ack will arrive */
2098 status = le16_to_cpu(frame_status[0].status);
25a6572c 2099 idx = start_idx;
f20217d9
TW		 2100
2101 /* FIXME: code repetition */
2102 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2103 agg->frame_count, agg->start_idx, idx);
2104
2105 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
2106 info->status.retry_count = tx_resp->failure_frame;
2107 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2108 info->flags |= iwl_is_tx_success(status)?
2109 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2110 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
f20217d9
TW		 2111 /* FIXME: code repetition end */
2112
2113 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
2114 status & 0xff, tx_resp->failure_frame);
e7d326ac 2115 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
f20217d9
TW		 2116
2117 agg->wait_for_ba = 0;
2118 } else {
2119 /* Two or more frames were attempted; expect block-ack */
2120 u64 bitmap = 0;
2121 int start = agg->start_idx;
2122
2123 /* Construct bit-map of pending frames within Tx window */
2124 for (i = 0; i < agg->frame_count; i++) {
2125 u16 sc;
2126 status = le16_to_cpu(frame_status[i].status);
2127 seq = le16_to_cpu(frame_status[i].sequence);
2128 idx = SEQ_TO_INDEX(seq);
2129 txq_id = SEQ_TO_QUEUE(seq);
2130
2131 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2132 AGG_TX_STATE_ABORT_MSK))
2133 continue;
2134
2135 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2136 agg->frame_count, txq_id, idx);
2137
2138 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2139
2140 sc = le16_to_cpu(hdr->seq_ctrl);
2141 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2142 IWL_ERROR("BUG_ON idx doesn't match seq control"
2143 " idx=%d, seq_idx=%d, seq=%d\n",
2144 idx, SEQ_TO_SN(sc),
2145 hdr->seq_ctrl);
2146 return -1;
2147 }
2148
2149 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
2150 i, idx, SEQ_TO_SN(sc));
2151
2152 sh = idx - start;
2153 if (sh > 64) {
2154 sh = (start - idx) + 0xff;
2155 bitmap = bitmap << sh;
2156 sh = 0;
2157 start = idx;
2158 } else if (sh < -64)
2159 sh = 0xff - (start - idx);
2160 else if (sh < 0) {
2161 sh = start - idx;
2162 start = idx;
2163 bitmap = bitmap << sh;
2164 sh = 0;
2165 }
2166 bitmap |= (1 << sh);
2167 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
2168 start, (u32)(bitmap & 0xFFFFFFFF));
2169 }
2170
2171 agg->bitmap = bitmap;
2172 agg->start_idx = start;
f20217d9
TW		 2173 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2174 agg->frame_count, agg->start_idx,
2175 (unsigned long long)agg->bitmap);
2176
2177 if (bitmap)
2178 agg->wait_for_ba = 1;
2179 }
2180 return 0;
2181}
f20217d9
TW		 2182
2183/**
2184 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2185 */
2186static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2187 struct iwl_rx_mem_buffer *rxb)
2188{
2189 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2190 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2191 int txq_id = SEQ_TO_QUEUE(sequence);
2192 int index = SEQ_TO_INDEX(sequence);
2193 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2194 struct ieee80211_tx_info *info;
2195 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 2196 u32 status = le32_to_cpu(tx_resp->u.status);
f20217d9 2197 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
fd7c8a40 2198 __le16 fc;
f20217d9
TW		 2199 struct ieee80211_hdr *hdr;
2200 u8 *qc = NULL;
f20217d9
TW		 2201
2202 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2203 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
2204 "is out of range [0-%d] %d %d\n", txq_id,
2205 index, txq->q.n_bd, txq->q.write_ptr,
2206 txq->q.read_ptr);
2207 return;
2208 }
2209
2210 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2211 memset(&info->status, 0, sizeof(info->status));
2212
f20217d9 2213 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
fd7c8a40
HH		 2214 fc = hdr->frame_control;
2215 if (ieee80211_is_data_qos(fc)) {
2216 qc = ieee80211_get_qos_ctl(hdr);
f20217d9
TW		 2217 tid = qc[0] & 0xf;
2218 }
2219
2220 sta_id = iwl_get_ra_sta_id(priv, hdr);
2221 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2222 IWL_ERROR("Station not known\n");
2223 return;
2224 }
2225
2226 if (txq->sched_retry) {
2227 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2228 struct iwl_ht_agg *agg = NULL;
2229
2230 if (!qc)
2231 return;
2232
2233 agg = &priv->stations[sta_id].tid[tid].agg;
2234
25a6572c 2235 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9 2236
3235427e
RR		 2237 /* check if BAR is needed */
2238 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2239 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
f20217d9
TW		 2240
2241 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2242 int freed, ampdu_q;
2243 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2244 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
2245 "%d index %d\n", scd_ssn , index);
17b88929 2246 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 2247 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2248
2249 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
2250 txq_id >= 0 && priv->mac80211_registered &&
2251 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
2252 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 2253 ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
f20217d9
TW		 2254 priv->hw->queues;
2255 if (agg->state == IWL_AGG_OFF)
2256 ieee80211_wake_queue(priv->hw, txq_id);
2257 else
2258 ieee80211_wake_queue(priv->hw, ampdu_q);
2259 }
30e553e3 2260 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
f20217d9
TW		 2261 }
2262 } else {
4f85f5b3
RR		 2263 info->status.retry_count = tx_resp->failure_frame;
2264 info->flags |=
2265 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2266 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 2267 le32_to_cpu(tx_resp->rate_n_flags),
2268 info);
2269
2270 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
2271 "0x%x retries %d\n", txq_id,
2272 iwl_get_tx_fail_reason(status),
2273 status, le32_to_cpu(tx_resp->rate_n_flags),
2274 tx_resp->failure_frame);
2275
2276 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
e7d326ac 2277
4f85f5b3
RR		 2278 if (index != -1) {
2279 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2280 if (tid != MAX_TID_COUNT)
f20217d9 2281 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 2282 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
f20217d9
TW		 2283 (txq_id >= 0) && priv->mac80211_registered)
2284 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 2285 if (tid != MAX_TID_COUNT)
30e553e3 2286 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 2287 }
f20217d9 2288 }
f20217d9
TW		 2289
2290 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2291 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
2292}
2293
2294
b481de9c 2295/* Set up 4965-specific Rx frame reply handlers */
d4789efe 2296static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 2297{
2298 /* Legacy Rx frames */
1781a07f 2299 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
37a44211 2300 /* Tx response */
f20217d9 2301 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c
ZY		 2302}
2303
4e39317d 2304static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2305{
2306 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 2307}
2308
4e39317d 2309static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2310{
4e39317d 2311 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 2312}
2313
3c424c28
TW		 2314
2315static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 2316 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 2317};
2318
857485c0 2319static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 2320 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 2321 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 2322 .chain_noise_reset = iwl4965_chain_noise_reset,
2323 .gain_computation = iwl4965_gain_computation,
a326a5d0 2324 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
857485c0
TW		 2325};
2326
6bc913bd 2327static struct iwl_lib_ops iwl4965_lib = {
5425e490 2328 .set_hw_params = iwl4965_hw_set_hw_params,
399f4900
RR		 2329 .alloc_shared_mem = iwl4965_alloc_shared_mem,
2330 .free_shared_mem = iwl4965_free_shared_mem,
d67f5489 2331 .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
e2a722eb 2332 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 2333 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 2334 .txq_agg_enable = iwl4965_txq_agg_enable,
2335 .txq_agg_disable = iwl4965_txq_agg_disable,
d4789efe 2336 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 2337 .setup_deferred_work = iwl4965_setup_deferred_work,
2338 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 2339 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2340 .alive_notify = iwl4965_alive_notify,
f3ccc08c 2341 .init_alive_start = iwl4965_init_alive_start,
57aab75a 2342 .load_ucode = iwl4965_load_bsm,
6f4083aa 2343 .apm_ops = {
91238714 2344 .init = iwl4965_apm_init,
7f066108 2345 .reset = iwl4965_apm_reset,
f118a91d 2346 .stop = iwl4965_apm_stop,
694cc56d 2347 .config = iwl4965_nic_config,
6f4083aa
TW		 2348 .set_pwr_src = iwl4965_set_pwr_src,
2349 },
6bc913bd 2350 .eeprom_ops = {
073d3f5f
TW		 2351 .regulatory_bands = {
2352 EEPROM_REGULATORY_BAND_1_CHANNELS,
2353 EEPROM_REGULATORY_BAND_2_CHANNELS,
2354 EEPROM_REGULATORY_BAND_3_CHANNELS,
2355 EEPROM_REGULATORY_BAND_4_CHANNELS,
2356 EEPROM_REGULATORY_BAND_5_CHANNELS,
2357 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
2358 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
2359 },
6bc913bd
AK		 2360 .verify_signature = iwlcore_eeprom_verify_signature,
2361 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2362 .release_semaphore = iwlcore_eeprom_release_semaphore,
8614f360 2363 .check_version = iwl4965_eeprom_check_version,
073d3f5f 2364 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 2365 },
630fe9b6 2366 .send_tx_power = iwl4965_send_tx_power,
5da4b55f 2367 .update_chain_flags = iwl4965_update_chain_flags,
8f91aecb 2368 .temperature = iwl4965_temperature_calib,
6bc913bd
AK		 2369};
2370
2371static struct iwl_ops iwl4965_ops = {
2372 .lib = &iwl4965_lib,
3c424c28 2373 .hcmd = &iwl4965_hcmd,
857485c0 2374 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 2375};
2376
fed9017e 2377struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 2378 .name = "4965AGN",
4bf775cd 2379 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 2380 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 2381 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 2382 .ops = &iwl4965_ops,
1ea87396 2383 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 2384};
2385
d16dc48a
TW		 2386/* Module firmware */
2387MODULE_FIRMWARE("iwlwifi-4965" IWL4965_UCODE_API ".ucode");
2388
1ea87396
AK		 2389module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
2390MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2391module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
2392MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b 2393module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
61a2d07d 2394MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
1ea87396
AK		 2395module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
2396MODULE_PARM_DESC(debug, "debug output mask");
2397module_param_named(
2398 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
2399MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2400
2401module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
2402MODULE_PARM_DESC(queues_num, "number of hw queues.");
1ea87396
AK		 2403/* QoS */
2404module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
2405MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
49779293
RR		 2406/* 11n */
2407module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2408MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
1ea87396
AK		 2409module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
2410MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
49779293 2411
3a1081e8
EK		 2412module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2413MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux 6.x block layer and io_uring tree(s)