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iwlegacy: merge iwl-debug.h into common.h
[linux-2.6-block.git] / drivers / net / wireless / iwlegacy / 4965.h
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4bc85c13 1/******************************************************************************
4bc85c13
WYG		 2 *
3 * GPL LICENSE SUMMARY
4 *
af038f40 5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
4bc85c13
WYG		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
4bc85c13 28 *****************************************************************************/
af038f40
SG		 29
30#ifndef __il_4965_h__
31#define __il_4965_h__
32
af038f40
SG		 33struct il_rx_queue;
34struct il_rx_buf;
35struct il_rx_pkt;
36struct il_tx_queue;
37struct il_rxon_context;
38
39/* configuration for the _4965 devices */
40extern struct il_cfg il4965_cfg;
41
42extern struct il_mod_params il4965_mod_params;
43
44extern struct ieee80211_ops il4965_hw_ops;
45
46/* tx queue */
47void il4965_free_tfds_in_queue(struct il_priv *il,
48 int sta_id, int tid, int freed);
49
50/* RXON */
51void il4965_set_rxon_chain(struct il_priv *il,
52 struct il_rxon_context *ctx);
53
54/* uCode */
55int il4965_verify_ucode(struct il_priv *il);
56
57/* lib */
58void il4965_check_abort_status(struct il_priv *il,
59 u8 frame_count, u32 status);
60
61void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
62int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
63int il4965_hw_nic_init(struct il_priv *il);
64int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
65
66/* rx */
67void il4965_rx_queue_restock(struct il_priv *il);
68void il4965_rx_replenish(struct il_priv *il);
69void il4965_rx_replenish_now(struct il_priv *il);
70void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
71int il4965_rxq_stop(struct il_priv *il);
72int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
6e9848b4 73void il4965_hdl_rx(struct il_priv *il,
af038f40 74 struct il_rx_buf *rxb);
6e9848b4 75void il4965_hdl_rx_phy(struct il_priv *il,
af038f40
SG		 76 struct il_rx_buf *rxb);
77void il4965_rx_handle(struct il_priv *il);
78
79/* tx */
80void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
81int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il,
82 struct il_tx_queue *txq,
83 dma_addr_t addr, u16 len, u8 reset, u8 pad);
84int il4965_hw_tx_queue_init(struct il_priv *il,
85 struct il_tx_queue *txq);
86void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
87 struct ieee80211_tx_info *info);
88int il4965_tx_skb(struct il_priv *il, struct sk_buff *skb);
89int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
90 struct ieee80211_sta *sta, u16 tid, u16 *ssn);
91int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
92 struct ieee80211_sta *sta, u16 tid);
93int il4965_txq_check_empty(struct il_priv *il,
94 int sta_id, u8 tid, int txq_id);
6e9848b4 95void il4965_hdl_compressed_ba(struct il_priv *il,
af038f40
SG		 96 struct il_rx_buf *rxb);
97int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
98void il4965_hw_txq_ctx_free(struct il_priv *il);
99int il4965_txq_ctx_alloc(struct il_priv *il);
100void il4965_txq_ctx_reset(struct il_priv *il);
101void il4965_txq_ctx_stop(struct il_priv *il);
102void il4965_txq_set_sched(struct il_priv *il, u32 mask);
103
4bc85c13 104/*
af038f40 105 * Acquire il->lock before calling this function !
4bc85c13 106 */
af038f40
SG		 107void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
108/**
109 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
110 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
111 * @scd_retry: (1) Indicates queue will be used in aggregation mode
112 *
113 * NOTE: Acquire il->lock before calling this function !
114 */
115void il4965_tx_queue_set_status(struct il_priv *il,
116 struct il_tx_queue *txq,
117 int tx_fifo_id, int scd_retry);
118
119u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant_idx, u8 valid);
120
121/* rx */
d2dfb33e 122void il4965_hdl_missed_beacon(struct il_priv *il,
af038f40
SG		 123 struct il_rx_buf *rxb);
124bool il4965_good_plcp_health(struct il_priv *il,
125 struct il_rx_pkt *pkt);
d2dfb33e 126void il4965_hdl_stats(struct il_priv *il,
af038f40 127 struct il_rx_buf *rxb);
d2dfb33e 128void il4965_hdl_c_stats(struct il_priv *il,
af038f40
SG		 129 struct il_rx_buf *rxb);
130
131/* scan */
132int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
133
134/* station mgmt */
135int il4965_manage_ibss_station(struct il_priv *il,
136 struct ieee80211_vif *vif, bool add);
137
138/* hcmd */
139int il4965_send_beacon_cmd(struct il_priv *il);
140
141#ifdef CONFIG_IWLEGACY_DEBUG
142const char *il4965_get_tx_fail_reason(u32 status);
143#else
144static inline const char *
145il4965_get_tx_fail_reason(u32 status) { return ""; }
146#endif
147
148/* station management */
149int il4965_alloc_bcast_station(struct il_priv *il,
150 struct il_rxon_context *ctx);
151int il4965_add_bssid_station(struct il_priv *il,
152 struct il_rxon_context *ctx,
153 const u8 *addr, u8 *sta_id_r);
154int il4965_remove_default_wep_key(struct il_priv *il,
155 struct il_rxon_context *ctx,
156 struct ieee80211_key_conf *key);
157int il4965_set_default_wep_key(struct il_priv *il,
158 struct il_rxon_context *ctx,
159 struct ieee80211_key_conf *key);
160int il4965_restore_default_wep_keys(struct il_priv *il,
161 struct il_rxon_context *ctx);
162int il4965_set_dynamic_key(struct il_priv *il,
163 struct il_rxon_context *ctx,
164 struct ieee80211_key_conf *key, u8 sta_id);
165int il4965_remove_dynamic_key(struct il_priv *il,
166 struct il_rxon_context *ctx,
167 struct ieee80211_key_conf *key, u8 sta_id);
168void il4965_update_tkip_key(struct il_priv *il,
169 struct il_rxon_context *ctx,
170 struct ieee80211_key_conf *keyconf,
171 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key);
172int il4965_sta_tx_modify_enable_tid(struct il_priv *il,
173 int sta_id, int tid);
174int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
175 int tid, u16 ssn);
176int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
177 int tid);
178void il4965_sta_modify_sleep_tx_count(struct il_priv *il,
179 int sta_id, int cnt);
180int il4965_update_bcast_stations(struct il_priv *il);
181
182/* rate */
183static inline u8 il4965_hw_get_rate(__le32 rate_n_flags)
184{
185 return le32_to_cpu(rate_n_flags) & 0xFF;
186}
4bc85c13 187
af038f40
SG		 188static inline __le32 il4965_hw_set_rate_n_flags(u8 rate, u32 flags)
189{
190 return cpu_to_le32(flags|(u32)rate);
191}
192
193/* eeprom */
194void il4965_eeprom_get_mac(const struct il_priv *il, u8 *mac);
195int il4965_eeprom_acquire_semaphore(struct il_priv *il);
196void il4965_eeprom_release_semaphore(struct il_priv *il);
197int il4965_eeprom_check_version(struct il_priv *il);
198
199/* mac80211 handlers (for 4965) */
200void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
201int il4965_mac_start(struct ieee80211_hw *hw);
202void il4965_mac_stop(struct ieee80211_hw *hw);
203void il4965_configure_filter(struct ieee80211_hw *hw,
204 unsigned int changed_flags,
205 unsigned int *total_flags,
206 u64 multicast);
207int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
208 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
209 struct ieee80211_key_conf *key);
210void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
211 struct ieee80211_vif *vif,
212 struct ieee80211_key_conf *keyconf,
213 struct ieee80211_sta *sta,
214 u32 iv32, u16 *phase1key);
215int il4965_mac_ampdu_action(struct ieee80211_hw *hw,
216 struct ieee80211_vif *vif,
217 enum ieee80211_ampdu_mlme_action action,
218 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
219 u8 buf_size);
220int il4965_mac_sta_add(struct ieee80211_hw *hw,
221 struct ieee80211_vif *vif,
222 struct ieee80211_sta *sta);
223void il4965_mac_channel_switch(struct ieee80211_hw *hw,
224 struct ieee80211_channel_switch *ch_switch);
225
226void il4965_led_enable(struct il_priv *il);
4bc85c13 227
4bc85c13
WYG		 228
229/* EEPROM */
d3175167 230#define IL4965_EEPROM_IMG_SIZE 1024
4bc85c13
WYG		 231
232/*
233 * uCode queue management definitions ...
234 * The first queue used for block-ack aggregation is #7 (4965 only).
235 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
236 */
d3175167 237#define IL49_FIRST_AMPDU_QUEUE 7
4bc85c13
WYG		 238
239/* Sizes and addresses for instruction and data memory (SRAM) in
240 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
d3175167
SG		 241#define IL49_RTC_INST_LOWER_BOUND (0x000000)
242#define IL49_RTC_INST_UPPER_BOUND (0x018000)
4bc85c13 243
d3175167
SG		 244#define IL49_RTC_DATA_LOWER_BOUND (0x800000)
245#define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
4bc85c13 246
d3175167
SG		 247#define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
248 IL49_RTC_INST_LOWER_BOUND)
249#define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
250 IL49_RTC_DATA_LOWER_BOUND)
4bc85c13 251
d3175167
SG		 252#define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
253#define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
4bc85c13
WYG		 254
255/* Size of uCode instruction memory in bootstrap state machine */
d3175167 256#define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
4bc85c13 257
e2ebc833 258static inline int il4965_hw_valid_rtc_data_addr(u32 addr)
4bc85c13 259{
d3175167
SG		 260 return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
261 addr < IL49_RTC_DATA_UPPER_BOUND);
4bc85c13
WYG		 262}
263
264/********************* START TEMPERATURE *************************************/
265
266/**
267 * 4965 temperature calculation.
268 *
269 * The driver must calculate the device temperature before calculating
270 * a txpower setting (amplifier gain is temperature dependent). The
271 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
272 * values used for the life of the driver, and one of which (R4) is the
273 * real-time temperature indicator.
274 *
275 * uCode provides all 4 values to the driver via the "initialize alive"
e2ebc833 276 * notification (see struct il4965_init_alive_resp). After the runtime uCode
ebf0d90d 277 * image loads, uCode updates the R4 value via stats notifications
4d69c752
SG		 278 * (see N_STATS), which occur after each received beacon
279 * when associated, or can be requested via C_STATS.
4bc85c13
WYG		 280 *
281 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
282 * must sign-extend to 32 bits before applying formula below.
283 *
284 * Formula:
285 *
286 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
287 *
288 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
289 * an additional correction, which should be centered around 0 degrees
290 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
291 * centering the 97/100 correction around 0 degrees K.
292 *
293 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
294 * temperature with factory-measured temperatures when calculating txpower
295 * settings.
296 */
297#define TEMPERATURE_CALIB_KELVIN_OFFSET 8
298#define TEMPERATURE_CALIB_A_VAL 259
299
300/* Limit range of calculated temperature to be between these Kelvin values */
e2ebc833
SG		 301#define IL_TX_POWER_TEMPERATURE_MIN (263)
302#define IL_TX_POWER_TEMPERATURE_MAX (410)
4bc85c13 303
e2ebc833 304#define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
232913b5
SG		 305 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
306 (t) > IL_TX_POWER_TEMPERATURE_MAX)
4bc85c13
WYG		 307
308/********************* END TEMPERATURE ***************************************/
309
310/********************* START TXPOWER *****************************************/
311
312/**
313 * 4965 txpower calculations rely on information from three sources:
314 *
315 * 1) EEPROM
316 * 2) "initialize" alive notification
ebf0d90d 317 * 3) stats notifications
4bc85c13
WYG		 318 *
319 * EEPROM data consists of:
320 *
321 * 1) Regulatory information (max txpower and channel usage flags) is provided
322 * separately for each channel that can possibly supported by 4965.
323 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
324 * (legacy) channels.
325 *
e2ebc833 326 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom
4bc85c13
WYG		 327 * for locations in EEPROM.
328 *
329 * 2) Factory txpower calibration information is provided separately for
330 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
331 * but 5 GHz has several sub-bands.
332 *
333 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
334 *
e2ebc833
SG		 335 * See struct il4965_eeprom_calib_info (and the tree of structures
336 * contained within it) for format, and struct il4965_eeprom for
4bc85c13
WYG		 337 * locations in EEPROM.
338 *
e2ebc833 339 * "Initialization alive" notification (see struct il4965_init_alive_resp)
4bc85c13
WYG		 340 * consists of:
341 *
342 * 1) Temperature calculation parameters.
343 *
344 * 2) Power supply voltage measurement.
345 *
346 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
347 *
348 * Statistics notifications deliver:
349 *
350 * 1) Current values for temperature param R4.
351 */
352
353/**
354 * To calculate a txpower setting for a given desired target txpower, channel,
355 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
356 * support MIMO and transmit diversity), driver must do the following:
357 *
358 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
359 * Do not exceed regulatory limit; reduce target txpower if necessary.
360 *
0c2c8852 361 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
4bc85c13
WYG		 362 * 2 transmitters will be used simultaneously; driver must reduce the
363 * regulatory limit by 3 dB (half-power) for each transmitter, so the
364 * combined total output of the 2 transmitters is within regulatory limits.
365 *
366 *
367 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
368 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
369 * reduce target txpower if necessary.
370 *
371 * Backoff values below are in 1/2 dB units (equivalent to steps in
372 * txpower gain tables):
373 *
374 * OFDM 6 - 36 MBit: 10 steps (5 dB)
375 * OFDM 48 MBit: 15 steps (7.5 dB)
376 * OFDM 54 MBit: 17 steps (8.5 dB)
377 * OFDM 60 MBit: 20 steps (10 dB)
378 * CCK all rates: 10 steps (5 dB)
379 *
380 * Backoff values apply to saturation txpower on a per-transmitter basis;
381 * when using MIMO (2 transmitters), each transmitter uses the same
382 * saturation level provided in EEPROM, and the same backoff values;
383 * no reduction (such as with regulatory txpower limits) is required.
384 *
385 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
386 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate
387 * factory measurement for ht40 channels.
388 *
389 * The result of this step is the final target txpower. The rest of
390 * the steps figure out the proper settings for the device to achieve
391 * that target txpower.
392 *
393 *
394 * 3) Determine (EEPROM) calibration sub band for the target channel, by
395 * comparing against first and last channels in each sub band
e2ebc833 396 * (see struct il4965_eeprom_calib_subband_info).
4bc85c13
WYG		 397 *
398 *
399 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
400 * referencing the 2 factory-measured (sample) channels within the sub band.
401 *
402 * Interpolation is based on difference between target channel's frequency
403 * and the sample channels' frequencies. Since channel numbers are based
404 * on frequency (5 MHz between each channel number), this is equivalent
405 * to interpolating based on channel number differences.
406 *
407 * Note that the sample channels may or may not be the channels at the
408 * edges of the sub band. The target channel may be "outside" of the
409 * span of the sampled channels.
410 *
411 * Driver may choose the pair (for 2 Tx chains) of measurements (see
e2ebc833 412 * struct il4965_eeprom_calib_ch_info) for which the actual measured
4bc85c13
WYG		 413 * txpower comes closest to the desired txpower. Usually, though,
414 * the middle set of measurements is closest to the regulatory limits,
415 * and is therefore a good choice for all txpower calculations (this
416 * assumes that high accuracy is needed for maximizing legal txpower,
417 * while lower txpower configurations do not need as much accuracy).
418 *
419 * Driver should interpolate both members of the chosen measurement pair,
420 * i.e. for both Tx chains (radio transmitters), unless the driver knows
421 * that only one of the chains will be used (e.g. only one tx antenna
422 * connected, but this should be unusual). The rate scaling algorithm
423 * switches antennas to find best performance, so both Tx chains will
424 * be used (although only one at a time) even for non-MIMO transmissions.
425 *
426 * Driver should interpolate factory values for temperature, gain table
0c2c8852 427 * idx, and actual power. The power amplifier detector values are
4bc85c13
WYG		 428 * not used by the driver.
429 *
430 * Sanity check: If the target channel happens to be one of the sample
431 * channels, the results should agree with the sample channel's
432 * measurements!
433 *
434 *
435 * 5) Find difference between desired txpower and (interpolated)
0c2c8852
SG		 436 * factory-measured txpower. Using (interpolated) factory gain table idx
437 * (shown elsewhere) as a starting point, adjust this idx lower to
4bc85c13
WYG		 438 * increase txpower, or higher to decrease txpower, until the target
439 * txpower is reached. Each step in the gain table is 1/2 dB.
440 *
441 * For example, if factory measured txpower is 16 dBm, and target txpower
0c2c8852 442 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
4bc85c13
WYG		 443 * by 3 dB.
444 *
445 *
446 * 6) Find difference between current device temperature and (interpolated)
447 * factory-measured temperature for sub-band. Factory values are in
448 * degrees Celsius. To calculate current temperature, see comments for
449 * "4965 temperature calculation".
450 *
451 * If current temperature is higher than factory temperature, driver must
0c2c8852 452 * increase gain (lower gain table idx), and vice verse.
4bc85c13
WYG		 453 *
454 * Temperature affects gain differently for different channels:
455 *
456 * 2.4 GHz all channels: 3.5 degrees per half-dB step
457 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
458 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
459 *
460 * NOTE: Temperature can increase rapidly when transmitting, especially
461 * with heavy traffic at high txpowers. Driver should update
462 * temperature calculations often under these conditions to
463 * maintain strong txpower in the face of rising temperature.
464 *
465 *
466 * 7) Find difference between current power supply voltage indicator
467 * (from "initialize alive") and factory-measured power supply voltage
468 * indicator (EEPROM).
469 *
470 * If the current voltage is higher (indicator is lower) than factory
0c2c8852 471 * voltage, gain should be reduced (gain table idx increased) by:
4bc85c13
WYG		 472 *
473 * (eeprom - current) / 7
474 *
475 * If the current voltage is lower (indicator is higher) than factory
0c2c8852 476 * voltage, gain should be increased (gain table idx decreased) by:
4bc85c13
WYG		 477 *
478 * 2 * (current - eeprom) / 7
479 *
0c2c8852 480 * If number of idx steps in either direction turns out to be > 2,
4bc85c13
WYG		 481 * something is wrong ... just use 0.
482 *
483 * NOTE: Voltage compensation is independent of band/channel.
484 *
485 * NOTE: "Initialize" uCode measures current voltage, which is assumed
486 * to be constant after this initial measurement. Voltage
487 * compensation for txpower (number of steps in gain table)
488 * may be calculated once and used until the next uCode bootload.
489 *
490 *
0c2c8852 491 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
4bc85c13
WYG		 492 * adjust txpower for each transmitter chain, so txpower is balanced
493 * between the two chains. There are 5 pairs of tx_atten[group][chain]
494 * values in "initialize alive", one pair for each of 5 channel ranges:
495 *
496 * Group 0: 5 GHz channel 34-43
497 * Group 1: 5 GHz channel 44-70
498 * Group 2: 5 GHz channel 71-124
499 * Group 3: 5 GHz channel 125-200
500 * Group 4: 2.4 GHz all channels
501 *
0c2c8852 502 * Add the tx_atten[group][chain] value to the idx for the target chain.
4bc85c13
WYG		 503 * The values are signed, but are in pairs of 0 and a non-negative number,
504 * so as to reduce gain (if necessary) of the "hotter" channel. This
505 * avoids any need to double-check for regulatory compliance after
506 * this step.
507 *
508 *
509 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
0c2c8852 510 * value to the idx:
4bc85c13
WYG		 511 *
512 * Hardware rev B: 9 steps (4.5 dB)
513 * Hardware rev C: 5 steps (2.5 dB)
514 *
515 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
516 * bits [3:2], 1 = B, 2 = C.
517 *
518 * NOTE: This compensation is in addition to any saturation backoff that
519 * might have been applied in an earlier step.
520 *
521 *
522 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
523 *
0c2c8852 524 * Limit the adjusted idx to stay within the table!
4bc85c13
WYG		 525 *
526 *
527 * 11) Read gain table entries for DSP and radio gain, place into appropriate
e2ebc833 528 * location(s) in command (struct il4965_txpowertable_cmd).
4bc85c13
WYG		 529 */
530
531/**
532 * When MIMO is used (2 transmitters operating simultaneously), driver should
533 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
534 * for the device. That is, use half power for each transmitter, so total
535 * txpower is within regulatory limits.
536 *
537 * The value "6" represents number of steps in gain table to reduce power 3 dB.
538 * Each step is 1/2 dB.
539 */
e2ebc833 540#define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
4bc85c13
WYG		 541
542/**
543 * CCK gain compensation.
544 *
545 * When calculating txpowers for CCK, after making sure that the target power
546 * is within regulatory and saturation limits, driver must additionally
0c2c8852 547 * back off gain by adding these values to the gain table idx.
4bc85c13
WYG		 548 *
549 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
550 * bits [3:2], 1 = B, 2 = C.
551 */
e2ebc833
SG		 552#define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
553#define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
4bc85c13
WYG		 554
555/*
556 * 4965 power supply voltage compensation for txpower
557 */
e2ebc833 558#define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
4bc85c13
WYG		 559
560/**
561 * Gain tables.
562 *
563 * The following tables contain pair of values for setting txpower, i.e.
564 * gain settings for the output of the device's digital signal processor (DSP),
565 * and for the analog gain structure of the transmitter.
566 *
567 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
568 * are *relative* steps, not indications of absolute output power. Output
569 * power varies with temperature, voltage, and channel frequency, and also
570 * requires consideration of average power (to satisfy regulatory constraints),
571 * and peak power (to avoid distortion of the output signal).
572 *
573 * Each entry contains two values:
574 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
575 * linear value that multiplies the output of the digital signal processor,
576 * before being sent to the analog radio.
577 * 2) Radio gain. This sets the analog gain of the radio Tx path.
578 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
579 *
580 * EEPROM contains factory calibration data for txpower. This maps actual
581 * measured txpower levels to gain settings in the "well known" tables
582 * below ("well-known" means here that both factory calibration *and* the
583 * driver work with the same table).
584 *
585 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
0c2c8852 586 * has an extension (into negative idxes), in case the driver needs to
4bc85c13 587 * boost power setting for high device temperatures (higher than would be
0c2c8852 588 * present during factory calibration). A 5 Ghz EEPROM idx of "40"
4bc85c13
WYG		 589 * corresponds to the 49th entry in the table used by the driver.
590 */
2d09b062
SG		 591#define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */
592#define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
4bc85c13
WYG		 593
594/**
595 * 2.4 GHz gain table
596 *
597 * Index Dsp gain Radio gain
598 * 0 110 0x3f (highest gain)
599 * 1 104 0x3f
600 * 2 98 0x3f
601 * 3 110 0x3e
602 * 4 104 0x3e
603 * 5 98 0x3e
604 * 6 110 0x3d
605 * 7 104 0x3d
606 * 8 98 0x3d
607 * 9 110 0x3c
608 * 10 104 0x3c
609 * 11 98 0x3c
610 * 12 110 0x3b
611 * 13 104 0x3b
612 * 14 98 0x3b
613 * 15 110 0x3a
614 * 16 104 0x3a
615 * 17 98 0x3a
616 * 18 110 0x39
617 * 19 104 0x39
618 * 20 98 0x39
619 * 21 110 0x38
620 * 22 104 0x38
621 * 23 98 0x38
622 * 24 110 0x37
623 * 25 104 0x37
624 * 26 98 0x37
625 * 27 110 0x36
626 * 28 104 0x36
627 * 29 98 0x36
628 * 30 110 0x35
629 * 31 104 0x35
630 * 32 98 0x35
631 * 33 110 0x34
632 * 34 104 0x34
633 * 35 98 0x34
634 * 36 110 0x33
635 * 37 104 0x33
636 * 38 98 0x33
637 * 39 110 0x32
638 * 40 104 0x32
639 * 41 98 0x32
640 * 42 110 0x31
641 * 43 104 0x31
642 * 44 98 0x31
643 * 45 110 0x30
644 * 46 104 0x30
645 * 47 98 0x30
646 * 48 110 0x6
647 * 49 104 0x6
648 * 50 98 0x6
649 * 51 110 0x5
650 * 52 104 0x5
651 * 53 98 0x5
652 * 54 110 0x4
653 * 55 104 0x4
654 * 56 98 0x4
655 * 57 110 0x3
656 * 58 104 0x3
657 * 59 98 0x3
658 * 60 110 0x2
659 * 61 104 0x2
660 * 62 98 0x2
661 * 63 110 0x1
662 * 64 104 0x1
663 * 65 98 0x1
664 * 66 110 0x0
665 * 67 104 0x0
666 * 68 98 0x0
667 * 69 97 0
668 * 70 96 0
669 * 71 95 0
670 * 72 94 0
671 * 73 93 0
672 * 74 92 0
673 * 75 91 0
674 * 76 90 0
675 * 77 89 0
676 * 78 88 0
677 * 79 87 0
678 * 80 86 0
679 * 81 85 0
680 * 82 84 0
681 * 83 83 0
682 * 84 82 0
683 * 85 81 0
684 * 86 80 0
685 * 87 79 0
686 * 88 78 0
687 * 89 77 0
688 * 90 76 0
689 * 91 75 0
690 * 92 74 0
691 * 93 73 0
692 * 94 72 0
693 * 95 71 0
694 * 96 70 0
695 * 97 69 0
696 * 98 68 0
697 */
698
699/**
700 * 5 GHz gain table
701 *
702 * Index Dsp gain Radio gain
703 * -9 123 0x3F (highest gain)
704 * -8 117 0x3F
705 * -7 110 0x3F
706 * -6 104 0x3F
707 * -5 98 0x3F
708 * -4 110 0x3E
709 * -3 104 0x3E
710 * -2 98 0x3E
711 * -1 110 0x3D
712 * 0 104 0x3D
713 * 1 98 0x3D
714 * 2 110 0x3C
715 * 3 104 0x3C
716 * 4 98 0x3C
717 * 5 110 0x3B
718 * 6 104 0x3B
719 * 7 98 0x3B
720 * 8 110 0x3A
721 * 9 104 0x3A
722 * 10 98 0x3A
723 * 11 110 0x39
724 * 12 104 0x39
725 * 13 98 0x39
726 * 14 110 0x38
727 * 15 104 0x38
728 * 16 98 0x38
729 * 17 110 0x37
730 * 18 104 0x37
731 * 19 98 0x37
732 * 20 110 0x36
733 * 21 104 0x36
734 * 22 98 0x36
735 * 23 110 0x35
736 * 24 104 0x35
737 * 25 98 0x35
738 * 26 110 0x34
739 * 27 104 0x34
740 * 28 98 0x34
741 * 29 110 0x33
742 * 30 104 0x33
743 * 31 98 0x33
744 * 32 110 0x32
745 * 33 104 0x32
746 * 34 98 0x32
747 * 35 110 0x31
748 * 36 104 0x31
749 * 37 98 0x31
750 * 38 110 0x30
751 * 39 104 0x30
752 * 40 98 0x30
753 * 41 110 0x25
754 * 42 104 0x25
755 * 43 98 0x25
756 * 44 110 0x24
757 * 45 104 0x24
758 * 46 98 0x24
759 * 47 110 0x23
760 * 48 104 0x23
761 * 49 98 0x23
762 * 50 110 0x22
763 * 51 104 0x18
764 * 52 98 0x18
765 * 53 110 0x17
766 * 54 104 0x17
767 * 55 98 0x17
768 * 56 110 0x16
769 * 57 104 0x16
770 * 58 98 0x16
771 * 59 110 0x15
772 * 60 104 0x15
773 * 61 98 0x15
774 * 62 110 0x14
775 * 63 104 0x14
776 * 64 98 0x14
777 * 65 110 0x13
778 * 66 104 0x13
779 * 67 98 0x13
780 * 68 110 0x12
781 * 69 104 0x08
782 * 70 98 0x08
783 * 71 110 0x07
784 * 72 104 0x07
785 * 73 98 0x07
786 * 74 110 0x06
787 * 75 104 0x06
788 * 76 98 0x06
789 * 77 110 0x05
790 * 78 104 0x05
791 * 79 98 0x05
792 * 80 110 0x04
793 * 81 104 0x04
794 * 82 98 0x04
795 * 83 110 0x03
796 * 84 104 0x03
797 * 85 98 0x03
798 * 86 110 0x02
799 * 87 104 0x02
800 * 88 98 0x02
801 * 89 110 0x01
802 * 90 104 0x01
803 * 91 98 0x01
804 * 92 110 0x00
805 * 93 104 0x00
806 * 94 98 0x00
807 * 95 93 0x00
808 * 96 88 0x00
809 * 97 83 0x00
810 * 98 78 0x00
811 */
812
813
814/**
815 * Sanity checks and default values for EEPROM regulatory levels.
816 * If EEPROM values fall outside MIN/MAX range, use default values.
817 *
818 * Regulatory limits refer to the maximum average txpower allowed by
819 * regulatory agencies in the geographies in which the device is meant
820 * to be operated. These limits are SKU-specific (i.e. geography-specific),
821 * and channel-specific; each channel has an individual regulatory limit
822 * listed in the EEPROM.
823 *
824 * Units are in half-dBm (i.e. "34" means 17 dBm).
825 */
e2ebc833
SG		 826#define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
827#define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
828#define IL_TX_POWER_REGULATORY_MIN (0)
829#define IL_TX_POWER_REGULATORY_MAX (34)
4bc85c13
WYG		 830
831/**
832 * Sanity checks and default values for EEPROM saturation levels.
833 * If EEPROM values fall outside MIN/MAX range, use default values.
834 *
835 * Saturation is the highest level that the output power amplifier can produce
836 * without significant clipping distortion. This is a "peak" power level.
837 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
838 * require differing amounts of backoff, relative to their average power output,
839 * in order to avoid clipping distortion.
840 *
841 * Driver must make sure that it is violating neither the saturation limit,
842 * nor the regulatory limit, when calculating Tx power settings for various
843 * rates.
844 *
845 * Units are in half-dBm (i.e. "38" means 19 dBm).
846 */
e2ebc833
SG		 847#define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
848#define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
849#define IL_TX_POWER_SATURATION_MIN (20)
850#define IL_TX_POWER_SATURATION_MAX (50)
4bc85c13
WYG		 851
852/**
853 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
854 * and thermal Txpower calibration.
855 *
856 * When calculating txpower, driver must compensate for current device
857 * temperature; higher temperature requires higher gain. Driver must calculate
858 * current temperature (see "4965 temperature calculation"), then compare vs.
859 * factory calibration temperature in EEPROM; if current temperature is higher
860 * than factory temperature, driver must *increase* gain by proportions shown
861 * in table below. If current temperature is lower than factory, driver must
862 * *decrease* gain.
863 *
864 * Different frequency ranges require different compensation, as shown below.
865 */
866/* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
e2ebc833
SG		 867#define CALIB_IL_TX_ATTEN_GR1_FCH 34
868#define CALIB_IL_TX_ATTEN_GR1_LCH 43
4bc85c13
WYG		 869
870/* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
e2ebc833
SG		 871#define CALIB_IL_TX_ATTEN_GR2_FCH 44
872#define CALIB_IL_TX_ATTEN_GR2_LCH 70
4bc85c13
WYG		 873
874/* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
e2ebc833
SG		 875#define CALIB_IL_TX_ATTEN_GR3_FCH 71
876#define CALIB_IL_TX_ATTEN_GR3_LCH 124
4bc85c13
WYG		 877
878/* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
e2ebc833
SG		 879#define CALIB_IL_TX_ATTEN_GR4_FCH 125
880#define CALIB_IL_TX_ATTEN_GR4_LCH 200
4bc85c13
WYG		 881
882/* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
e2ebc833
SG		 883#define CALIB_IL_TX_ATTEN_GR5_FCH 1
884#define CALIB_IL_TX_ATTEN_GR5_LCH 20
4bc85c13
WYG		 885
886enum {
887 CALIB_CH_GROUP_1 = 0,
888 CALIB_CH_GROUP_2 = 1,
889 CALIB_CH_GROUP_3 = 2,
890 CALIB_CH_GROUP_4 = 3,
891 CALIB_CH_GROUP_5 = 4,
892 CALIB_CH_GROUP_MAX
893};
894
895/********************* END TXPOWER *****************************************/
896
897
898/**
899 * Tx/Rx Queues
900 *
901 * Most communication between driver and 4965 is via queues of data buffers.
902 * For example, all commands that the driver issues to device's embedded
903 * controller (uCode) are via the command queue (one of the Tx queues). All
904 * uCode command responses/replies/notifications, including Rx frames, are
905 * conveyed from uCode to driver via the Rx queue.
906 *
907 * Most support for these queues, including handshake support, resides in
908 * structures in host DRAM, shared between the driver and the device. When
909 * allocating this memory, the driver must make sure that data written by
910 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
911 * cache memory), so DRAM and cache are consistent, and the device can
912 * immediately see changes made by the driver.
913 *
914 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
915 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
916 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
917 */
d3175167
SG		 918#define IL49_NUM_FIFOS 7
919#define IL49_CMD_FIFO_NUM 4
920#define IL49_NUM_QUEUES 16
921#define IL49_NUM_AMPDU_QUEUES 8
4bc85c13
WYG		 922
923
924/**
e2ebc833 925 * struct il4965_schedq_bc_tbl
4bc85c13
WYG		 926 *
927 * Byte Count table
928 *
929 * Each Tx queue uses a byte-count table containing 320 entries:
930 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
6ce1dc45
SG		 931 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
932 * max Tx win is 64 TFDs).
4bc85c13
WYG		 933 *
934 * When driver sets up a new TFD, it must also enter the total byte count
935 * of the frame to be transmitted into the corresponding entry in the byte
0c2c8852
SG		 936 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
937 * must duplicate the byte count entry in corresponding idx 256-319.
4bc85c13
WYG		 938 *
939 * padding puts each byte count table on a 1024-byte boundary;
940 * 4965 assumes tables are separated by 1024 bytes.
941 */
e2ebc833 942struct il4965_scd_bc_tbl {
4bc85c13
WYG		 943 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
944 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
945} __packed;
946
be663ab6 947
d3175167 948#define IL4965_RTC_INST_LOWER_BOUND (0x000000)
be663ab6
WYG		 949
950/* RSSI to dBm */
d3175167 951#define IL4965_RSSI_OFFSET 44
be663ab6
WYG		 952
953/* PCI registers */
954#define PCI_CFG_RETRY_TIMEOUT 0x041
955
956/* PCI register values */
957#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
958#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
959
d3175167 960#define IL4965_DEFAULT_TX_RETRY 15
be663ab6 961
be663ab6 962/* EEPROM */
d3175167 963#define IL4965_FIRST_AMPDU_QUEUE 10
be663ab6 964
af038f40
SG		 965/* Calibration */
966void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
967void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
968void il4965_init_sensitivity(struct il_priv *il);
969void il4965_reset_run_time_calib(struct il_priv *il);
970void il4965_calib_free_results(struct il_priv *il);
971
972/* Debug */
973#ifdef CONFIG_IWLEGACY_DEBUGFS
974ssize_t il4965_ucode_rx_stats_read(struct file *file, char __user *user_buf,
975 size_t count, loff_t *ppos);
976ssize_t il4965_ucode_tx_stats_read(struct file *file, char __user *user_buf,
977 size_t count, loff_t *ppos);
978ssize_t il4965_ucode_general_stats_read(struct file *file,
979 char __user *user_buf, size_t count, loff_t *ppos);
980#else
981static ssize_t
982il4965_ucode_rx_stats_read(struct file *file, char __user *user_buf,
983 size_t count, loff_t *ppos)
984{
985 return 0;
986}
987static ssize_t
988il4965_ucode_tx_stats_read(struct file *file, char __user *user_buf,
989 size_t count, loff_t *ppos)
990{
991 return 0;
992}
993static ssize_t
994il4965_ucode_general_stats_read(struct file *file, char __user *user_buf,
995 size_t count, loff_t *ppos)
996{
997 return 0;
998}
999#endif
be663ab6 1000
eac3b212
SG		 1001/****************************/
1002/* Flow Handler Definitions */
1003/****************************/
1004
1005/**
1006 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1007 * Addresses are offsets from device's PCI hardware base address.
1008 */
1009#define FH49_MEM_LOWER_BOUND (0x1000)
1010#define FH49_MEM_UPPER_BOUND (0x2000)
1011
1012/**
1013 * Keep-Warm (KW) buffer base address.
1014 *
1015 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
1016 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1017 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
1018 * from going into a power-savings mode that would cause higher DRAM latency,
1019 * and possible data over/under-runs, before all Tx/Rx is complete.
1020 *
1021 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1022 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
1023 * automatically invokes keep-warm accesses when normal accesses might not
1024 * be sufficient to maintain fast DRAM response.
1025 *
1026 * Bit fields:
1027 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1028 */
1029#define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
1030
1031
1032/**
1033 * TFD Circular Buffers Base (CBBC) addresses
1034 *
1035 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
1036 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1037 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
1038 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1039 * aligned (address bits 0-7 must be 0).
1040 *
1041 * Bit fields in each pointer register:
1042 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1043 */
1044#define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1045#define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
1046
1047/* Find TFD CB base pointer for given queue (range 0-15). */
1048#define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
1049
1050
1051/**
1052 * Rx SRAM Control and Status Registers (RSCSR)
1053 *
1054 * These registers provide handshake between driver and 4965 for the Rx queue
1055 * (this queue handles *all* command responses, notifications, Rx data, etc.
1056 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
1057 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1058 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1059 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1060 * mapping between RBDs and RBs.
1061 *
1062 * Driver must allocate host DRAM memory for the following, and set the
1063 * physical address of each into 4965 registers:
1064 *
1065 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1066 * entries (although any power of 2, up to 4096, is selectable by driver).
1067 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1068 * (typically 4K, although 8K or 16K are also selectable by driver).
1069 * Driver sets up RB size and number of RBDs in the CB via Rx config
1070 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
1071 *
1072 * Bit fields within one RBD:
1073 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1074 *
1075 * Driver sets physical address [35:8] of base of RBD circular buffer
1076 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1077 *
1078 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1079 * (RBs) have been filled, via a "write pointer", actually the idx of
1080 * the RB's corresponding RBD within the circular buffer. Driver sets
1081 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1082 *
1083 * Bit fields in lower dword of Rx status buffer (upper dword not used
1084 * by driver; see struct il4965_shared, val0):
1085 * 31-12: Not used by driver
1086 * 11- 0: Index of last filled Rx buffer descriptor
1087 * (4965 writes, driver reads this value)
1088 *
1089 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1090 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1091 * and update the 4965's "write" idx register,
1092 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1093 *
1094 * This "write" idx corresponds to the *next* RBD that the driver will make
1095 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1096 * the circular buffer. This value should initially be 0 (before preparing any
1097 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1098 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1099 * "read" idx has advanced past 1! See below).
1100 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1101 *
1102 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1103 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1104 * to tell the driver the idx of the latest filled RBD. The driver must
1105 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1106 *
1107 * The driver must also internally keep track of a third idx, which is the
1108 * next RBD to process. When receiving an Rx interrupt, driver should process
1109 * all filled but unprocessed RBs up to, but not including, the RB
1110 * corresponding to the "read" idx. For example, if "read" idx becomes "1",
1111 * driver may process the RB pointed to by RBD 0. Depending on volume of
1112 * traffic, there may be many RBs to process.
1113 *
1114 * If read idx == write idx, 4965 thinks there is no room to put new data.
1115 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1116 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1117 * and "read" idxes; that is, make sure that there are no more than 254
1118 * buffers waiting to be filled.
1119 */
1120#define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1121#define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1122#define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1123
1124/**
1125 * Physical base address of 8-byte Rx Status buffer.
1126 * Bit fields:
1127 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1128 */
1129#define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1130
1131/**
1132 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1133 * Bit fields:
1134 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1135 */
1136#define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1137
1138/**
1139 * Rx write pointer (idx, really!).
1140 * Bit fields:
1141 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1142 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1143 */
1144#define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1145#define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1146
1147
1148/**
1149 * Rx Config/Status Registers (RCSR)
1150 * Rx Config Reg for channel 0 (only channel used)
1151 *
1152 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1153 * normal operation (see bit fields).
1154 *
1155 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1156 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
1157 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1158 *
1159 * Bit fields:
1160 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1161 * '10' operate normally
1162 * 29-24: reserved
1163 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1164 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1165 * 19-18: reserved
1166 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1167 * '10' 12K, '11' 16K.
1168 * 15-14: reserved
1169 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1170 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1171 * typical value 0x10 (about 1/2 msec)
1172 * 3- 0: reserved
1173 */
1174#define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1175#define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1176#define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1177
1178#define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1179
1180#define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1181#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1182#define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1183#define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1184#define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1185#define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1186
1187#define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1188#define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1189#define RX_RB_TIMEOUT (0x10)
1190
1191#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1192#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1193#define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1194
1195#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1196#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1197#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1198#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1199
1200#define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1201#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1202#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1203
1204/**
1205 * Rx Shared Status Registers (RSSR)
1206 *
1207 * After stopping Rx DMA channel (writing 0 to
1208 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1209 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1210 *
1211 * Bit fields:
1212 * 24: 1 = Channel 0 is idle
1213 *
1214 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1215 * contain default values that should not be altered by the driver.
1216 */
1217#define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1218#define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1219
1220#define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1221#define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1222#define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1223 (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1224
1225#define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1226
1227#define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1228
1229/* TFDB Area - TFDs buffer table */
1230#define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1231#define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1232#define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1233#define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1234#define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1235
1236/**
1237 * Transmit DMA Channel Control/Status Registers (TCSR)
1238 *
1239 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1240 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1241 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1242 *
1243 * To use a Tx DMA channel, driver must initialize its
1244 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1245 *
1246 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1247 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1248 *
1249 * All other bits should be 0.
1250 *
1251 * Bit fields:
1252 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1253 * '10' operate normally
1254 * 29- 4: Reserved, set to "0"
1255 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1256 * 2- 0: Reserved, set to "0"
1257 */
1258#define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1259#define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1260
1261/* Find Control/Status reg for given Tx DMA/FIFO channel */
1262#define FH49_TCSR_CHNL_NUM (7)
1263#define FH50_TCSR_CHNL_NUM (8)
1264
1265/* TCSR: tx_config register values */
1266#define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1267 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1268#define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1269 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1270#define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1271 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1272
1273#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1274#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1275
1276#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1277#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1278
1279#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1280#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1281#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1282
1283#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1284#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1285#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1286
1287#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1288#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1289#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1290
1291#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1292#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1293#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1294
1295#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1296#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1297
1298/**
1299 * Tx Shared Status Registers (TSSR)
1300 *
1301 * After stopping Tx DMA channel (writing 0 to
1302 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1303 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1304 * (channel's buffers empty | no pending requests).
1305 *
1306 * Bit fields:
1307 * 31-24: 1 = Channel buffers empty (channel 7:0)
1308 * 23-16: 1 = No pending requests (channel 7:0)
1309 */
1310#define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1311#define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1312
1313#define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1314
1315/**
1316 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1317 * 31: Indicates an address error when accessed to internal memory
1318 * uCode/driver must write "1" in order to clear this flag
1319 * 30: Indicates that Host did not send the expected number of dwords to FH
1320 * uCode/driver must write "1" in order to clear this flag
1321 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1322 * command was received from the scheduler while the TRB was already full
1323 * with previous command
1324 * uCode/driver must write "1" in order to clear this flag
1325 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1326 * bit is set, it indicates that the FH has received a full indication
1327 * from the RTC TxFIFO and the current value of the TxCredit counter was
1328 * not equal to zero. This mean that the credit mechanism was not
1329 * synchronized to the TxFIFO status
1330 * uCode/driver must write "1" in order to clear this flag
1331 */
1332#define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1333
1334#define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1335
1336/* Tx service channels */
1337#define FH49_SRVC_CHNL (9)
1338#define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1339#define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1340#define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1341 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1342
1343#define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1344/* Instruct FH to increment the retry count of a packet when
1345 * it is brought from the memory to TX-FIFO
1346 */
1347#define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1348
1349/* Keep Warm Size */
1350#define IL_KW_SIZE 0x1000 /* 4k */
1351
af038f40 1352#endif /* __il_4965_h__ */
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