iwlegacy: move iwl-3945-{,hw,fh,debugfs}.h to 3945.h
[linux-2.6-block.git] / drivers / net / wireless / iwlegacy / 3945-mac.c
CommitLineData
4bc85c13
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1/******************************************************************************
2 *
be663ab6 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
4bc85c13
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43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/ieee80211_radiotap.h>
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
52#define DRV_NAME "iwl3945"
53
54#include "iwl-fh.h"
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55#include "iwl-commands.h"
56#include "iwl-sta.h"
6bbb1370 57#include "3945.h"
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58#include "iwl-core.h"
59#include "iwl-helpers.h"
60#include "iwl-dev.h"
61#include "iwl-spectrum.h"
4bc85c13
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62
63/*
64 * module name, copyright, version, etc.
65 */
66
67#define DRV_DESCRIPTION \
68"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
69
d3175167 70#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
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71#define VD "d"
72#else
73#define VD
74#endif
75
76/*
77 * add "s" to indicate spectrum measurement included.
78 * we add it here to be consistent with previous releases in which
79 * this was configurable.
80 */
81#define DRV_VERSION IWLWIFI_VERSION VD "s"
be663ab6 82#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
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83#define DRV_AUTHOR "<ilw@linux.intel.com>"
84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88MODULE_LICENSE("GPL");
89
90 /* module parameters */
e2ebc833 91struct il_mod_params il3945_mod_params = {
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92 .sw_crypto = 1,
93 .restart_fw = 1,
0263aa45 94 .disable_hw_scan = 1,
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95 /* the rest are 0 by default */
96};
97
98/**
e2ebc833 99 * il3945_get_antenna_flags - Get antenna flags for RXON command
46bc8d4b 100 * @il: eeprom and antenna fields are used to determine antenna flags
4bc85c13 101 *
46bc8d4b 102 * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
e2ebc833 103 * il3945_mod_params.antenna specifies the antenna diversity mode:
4bc85c13 104 *
e2ebc833
SG
105 * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
106 * IL_ANTENNA_MAIN - Force MAIN antenna
107 * IL_ANTENNA_AUX - Force AUX antenna
4bc85c13 108 */
46bc8d4b 109__le32 il3945_get_antenna_flags(const struct il_priv *il)
4bc85c13 110{
46bc8d4b 111 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 112
e2ebc833
SG
113 switch (il3945_mod_params.antenna) {
114 case IL_ANTENNA_DIVERSITY:
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115 return 0;
116
e2ebc833 117 case IL_ANTENNA_MAIN:
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118 if (eeprom->antenna_switch_type)
119 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
121
e2ebc833 122 case IL_ANTENNA_AUX:
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123 if (eeprom->antenna_switch_type)
124 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
126 }
127
128 /* bad antenna selector value */
9406f797 129 IL_ERR("Bad antenna selector value (0x%x)\n",
e2ebc833 130 il3945_mod_params.antenna);
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131
132 return 0; /* "diversity" is default if error */
133}
134
46bc8d4b 135static int il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
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136 struct ieee80211_key_conf *keyconf,
137 u8 sta_id)
138{
139 unsigned long flags;
140 __le16 key_flags = 0;
141 int ret;
142
143 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
144 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
145
7c2cde2e 146 if (sta_id == il->ctx.bcast_sta_id)
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147 key_flags |= STA_KEY_MULTICAST_MSK;
148
149 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
150 keyconf->hw_key_idx = keyconf->keyidx;
151 key_flags &= ~STA_KEY_FLG_INVALID;
152
46bc8d4b
SG
153 spin_lock_irqsave(&il->sta_lock, flags);
154 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
155 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
156 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key,
4bc85c13
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157 keyconf->keylen);
158
46bc8d4b 159 memcpy(il->stations[sta_id].sta.key.key, keyconf->key,
4bc85c13
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160 keyconf->keylen);
161
46bc8d4b 162 if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
4bc85c13 163 == STA_KEY_FLG_NO_ENC)
46bc8d4b 164 il->stations[sta_id].sta.key.key_offset =
0c2c8852 165 il_get_free_ucode_key_idx(il);
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166 /* else, we are overriding an existing key => no need to allocated room
167 * in uCode. */
168
46bc8d4b 169 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
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170 "no space for a new key");
171
46bc8d4b
SG
172 il->stations[sta_id].sta.key.key_flags = key_flags;
173 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
174 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4bc85c13 175
58de00a4 176 D_INFO("hwcrypto: modify ucode station key info\n");
4bc85c13 177
46bc8d4b
SG
178 ret = il_send_add_sta(il,
179 &il->stations[sta_id].sta, CMD_ASYNC);
4bc85c13 180
46bc8d4b 181 spin_unlock_irqrestore(&il->sta_lock, flags);
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182
183 return ret;
184}
185
46bc8d4b 186static int il3945_set_tkip_dynamic_key_info(struct il_priv *il,
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187 struct ieee80211_key_conf *keyconf,
188 u8 sta_id)
189{
190 return -EOPNOTSUPP;
191}
192
46bc8d4b 193static int il3945_set_wep_dynamic_key_info(struct il_priv *il,
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194 struct ieee80211_key_conf *keyconf,
195 u8 sta_id)
196{
197 return -EOPNOTSUPP;
198}
199
46bc8d4b 200static int il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
4bc85c13
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201{
202 unsigned long flags;
e2ebc833 203 struct il_addsta_cmd sta_cmd;
4bc85c13 204
46bc8d4b
SG
205 spin_lock_irqsave(&il->sta_lock, flags);
206 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
207 memset(&il->stations[sta_id].sta.key, 0,
e2ebc833 208 sizeof(struct il4965_keyinfo));
46bc8d4b
SG
209 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
210 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
211 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
212 memcpy(&sta_cmd, &il->stations[sta_id].sta, sizeof(struct il_addsta_cmd));
213 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13 214
58de00a4 215 D_INFO("hwcrypto: clear ucode station key info\n");
46bc8d4b 216 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
4bc85c13
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217}
218
46bc8d4b 219static int il3945_set_dynamic_key(struct il_priv *il,
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220 struct ieee80211_key_conf *keyconf, u8 sta_id)
221{
222 int ret = 0;
223
224 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
225
226 switch (keyconf->cipher) {
227 case WLAN_CIPHER_SUITE_CCMP:
46bc8d4b 228 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
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229 break;
230 case WLAN_CIPHER_SUITE_TKIP:
46bc8d4b 231 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
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232 break;
233 case WLAN_CIPHER_SUITE_WEP40:
234 case WLAN_CIPHER_SUITE_WEP104:
46bc8d4b 235 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
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236 break;
237 default:
9406f797 238 IL_ERR("Unknown alg: %s alg=%x\n", __func__,
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239 keyconf->cipher);
240 ret = -EINVAL;
241 }
242
58de00a4 243 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
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244 keyconf->cipher, keyconf->keylen, keyconf->keyidx,
245 sta_id, ret);
246
247 return ret;
248}
249
46bc8d4b 250static int il3945_remove_static_key(struct il_priv *il)
4bc85c13
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251{
252 int ret = -EOPNOTSUPP;
253
254 return ret;
255}
256
46bc8d4b 257static int il3945_set_static_key(struct il_priv *il,
4bc85c13
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258 struct ieee80211_key_conf *key)
259{
260 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
261 key->cipher == WLAN_CIPHER_SUITE_WEP104)
262 return -EOPNOTSUPP;
263
9406f797 264 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
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265 return -EINVAL;
266}
267
46bc8d4b 268static void il3945_clear_free_frames(struct il_priv *il)
4bc85c13
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269{
270 struct list_head *element;
271
58de00a4 272 D_INFO("%d frames on pre-allocated heap on clear.\n",
46bc8d4b 273 il->frames_count);
4bc85c13 274
46bc8d4b
SG
275 while (!list_empty(&il->free_frames)) {
276 element = il->free_frames.next;
4bc85c13 277 list_del(element);
e2ebc833 278 kfree(list_entry(element, struct il3945_frame, list));
46bc8d4b 279 il->frames_count--;
4bc85c13
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280 }
281
46bc8d4b 282 if (il->frames_count) {
9406f797 283 IL_WARN("%d frames still in use. Did we lose one?\n",
46bc8d4b
SG
284 il->frames_count);
285 il->frames_count = 0;
4bc85c13
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286 }
287}
288
46bc8d4b 289static struct il3945_frame *il3945_get_free_frame(struct il_priv *il)
4bc85c13 290{
e2ebc833 291 struct il3945_frame *frame;
4bc85c13 292 struct list_head *element;
46bc8d4b 293 if (list_empty(&il->free_frames)) {
4bc85c13
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294 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
295 if (!frame) {
9406f797 296 IL_ERR("Could not allocate frame!\n");
4bc85c13
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297 return NULL;
298 }
299
46bc8d4b 300 il->frames_count++;
4bc85c13
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301 return frame;
302 }
303
46bc8d4b 304 element = il->free_frames.next;
4bc85c13 305 list_del(element);
e2ebc833 306 return list_entry(element, struct il3945_frame, list);
4bc85c13
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307}
308
46bc8d4b 309static void il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
4bc85c13
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310{
311 memset(frame, 0, sizeof(*frame));
46bc8d4b 312 list_add(&frame->list, &il->free_frames);
4bc85c13
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313}
314
46bc8d4b 315unsigned int il3945_fill_beacon_frame(struct il_priv *il,
4bc85c13
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316 struct ieee80211_hdr *hdr,
317 int left)
318{
319
7c2cde2e 320 if (!il_is_associated(il) || !il->beacon_skb)
4bc85c13
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321 return 0;
322
46bc8d4b 323 if (il->beacon_skb->len > left)
4bc85c13
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324 return 0;
325
46bc8d4b 326 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
4bc85c13 327
46bc8d4b 328 return il->beacon_skb->len;
4bc85c13
WYG
329}
330
46bc8d4b 331static int il3945_send_beacon_cmd(struct il_priv *il)
4bc85c13 332{
e2ebc833 333 struct il3945_frame *frame;
4bc85c13
WYG
334 unsigned int frame_size;
335 int rc;
336 u8 rate;
337
46bc8d4b 338 frame = il3945_get_free_frame(il);
4bc85c13
WYG
339
340 if (!frame) {
9406f797 341 IL_ERR("Could not obtain free frame buffer for beacon "
4bc85c13
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342 "command.\n");
343 return -ENOMEM;
344 }
345
46bc8d4b 346 rate = il_get_lowest_plcp(il,
7c2cde2e 347 &il->ctx);
4bc85c13 348
46bc8d4b 349 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
4bc85c13 350
46bc8d4b 351 rc = il_send_cmd_pdu(il, REPLY_TX_BEACON, frame_size,
4bc85c13
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352 &frame->u.cmd[0]);
353
46bc8d4b 354 il3945_free_frame(il, frame);
4bc85c13
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355
356 return rc;
357}
358
46bc8d4b 359static void il3945_unset_hw_params(struct il_priv *il)
4bc85c13 360{
46bc8d4b
SG
361 if (il->_3945.shared_virt)
362 dma_free_coherent(&il->pci_dev->dev,
e2ebc833 363 sizeof(struct il3945_shared),
46bc8d4b
SG
364 il->_3945.shared_virt,
365 il->_3945.shared_phys);
4bc85c13
WYG
366}
367
46bc8d4b 368static void il3945_build_tx_cmd_hwcrypto(struct il_priv *il,
4bc85c13 369 struct ieee80211_tx_info *info,
e2ebc833 370 struct il_device_cmd *cmd,
4bc85c13
WYG
371 struct sk_buff *skb_frag,
372 int sta_id)
373{
e2ebc833 374 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
46bc8d4b 375 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
4bc85c13
WYG
376
377 tx_cmd->sec_ctl = 0;
378
379 switch (keyinfo->cipher) {
380 case WLAN_CIPHER_SUITE_CCMP:
381 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
382 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
58de00a4 383 D_TX("tx_cmd with AES hwcrypto\n");
4bc85c13
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384 break;
385
386 case WLAN_CIPHER_SUITE_TKIP:
387 break;
388
389 case WLAN_CIPHER_SUITE_WEP104:
390 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
391 /* fall through */
392 case WLAN_CIPHER_SUITE_WEP40:
393 tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
394 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
395
396 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
397
58de00a4 398 D_TX("Configuring packet for WEP encryption "
4bc85c13
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399 "with key %d\n", info->control.hw_key->hw_key_idx);
400 break;
401
402 default:
9406f797 403 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
4bc85c13
WYG
404 break;
405 }
406}
407
408/*
409 * handle build REPLY_TX command notification.
410 */
46bc8d4b 411static void il3945_build_tx_cmd_basic(struct il_priv *il,
e2ebc833 412 struct il_device_cmd *cmd,
4bc85c13
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413 struct ieee80211_tx_info *info,
414 struct ieee80211_hdr *hdr, u8 std_id)
415{
e2ebc833 416 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
4bc85c13
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417 __le32 tx_flags = tx_cmd->tx_flags;
418 __le16 fc = hdr->frame_control;
419
420 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
421 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
422 tx_flags |= TX_CMD_FLG_ACK_MSK;
423 if (ieee80211_is_mgmt(fc))
424 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
425 if (ieee80211_is_probe_resp(fc) &&
426 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
427 tx_flags |= TX_CMD_FLG_TSF_MSK;
428 } else {
429 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
430 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
431 }
432
433 tx_cmd->sta_id = std_id;
434 if (ieee80211_has_morefrags(fc))
435 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
436
437 if (ieee80211_is_data_qos(fc)) {
438 u8 *qc = ieee80211_get_qos_ctl(hdr);
439 tx_cmd->tid_tspec = qc[0] & 0xf;
440 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
441 } else {
442 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
443 }
444
46bc8d4b 445 il_tx_cmd_protection(il, info, fc, &tx_flags);
4bc85c13
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446
447 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
448 if (ieee80211_is_mgmt(fc)) {
449 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
450 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
451 else
452 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
453 } else {
454 tx_cmd->timeout.pm_frame_timeout = 0;
455 }
456
457 tx_cmd->driver_txop = 0;
458 tx_cmd->tx_flags = tx_flags;
459 tx_cmd->next_frame_len = 0;
460}
461
462/*
463 * start REPLY_TX command process
464 */
46bc8d4b 465static int il3945_tx_skb(struct il_priv *il, struct sk_buff *skb)
4bc85c13
WYG
466{
467 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e2ebc833
SG
469 struct il3945_tx_cmd *tx_cmd;
470 struct il_tx_queue *txq = NULL;
471 struct il_queue *q = NULL;
472 struct il_device_cmd *out_cmd;
473 struct il_cmd_meta *out_meta;
4bc85c13
WYG
474 dma_addr_t phys_addr;
475 dma_addr_t txcmd_phys;
476 int txq_id = skb_get_queue_mapping(skb);
477 u16 len, idx, hdr_len;
478 u8 id;
479 u8 unicast;
480 u8 sta_id;
481 u8 tid = 0;
482 __le16 fc;
483 u8 wait_write_ptr = 0;
484 unsigned long flags;
485
46bc8d4b
SG
486 spin_lock_irqsave(&il->lock, flags);
487 if (il_is_rfkill(il)) {
58de00a4 488 D_DROP("Dropping - RF KILL\n");
4bc85c13
WYG
489 goto drop_unlock;
490 }
491
46bc8d4b 492 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) == IL_INVALID_RATE) {
9406f797 493 IL_ERR("ERROR: No TX rate available.\n");
4bc85c13
WYG
494 goto drop_unlock;
495 }
496
497 unicast = !is_multicast_ether_addr(hdr->addr1);
498 id = 0;
499
500 fc = hdr->frame_control;
501
d3175167 502#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13 503 if (ieee80211_is_auth(fc))
58de00a4 504 D_TX("Sending AUTH frame\n");
4bc85c13 505 else if (ieee80211_is_assoc_req(fc))
58de00a4 506 D_TX("Sending ASSOC frame\n");
4bc85c13 507 else if (ieee80211_is_reassoc_req(fc))
58de00a4 508 D_TX("Sending REASSOC frame\n");
4bc85c13
WYG
509#endif
510
46bc8d4b 511 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
512
513 hdr_len = ieee80211_hdrlen(fc);
514
0c2c8852 515 /* Find idx into station table for destination station */
e2ebc833 516 sta_id = il_sta_id_or_broadcast(
7c2cde2e 517 il, &il->ctx,
4bc85c13 518 info->control.sta);
e2ebc833 519 if (sta_id == IL_INVALID_STATION) {
58de00a4 520 D_DROP("Dropping - INVALID STATION: %pM\n",
4bc85c13
WYG
521 hdr->addr1);
522 goto drop;
523 }
524
58de00a4 525 D_RATE("station Id %d\n", sta_id);
4bc85c13
WYG
526
527 if (ieee80211_is_data_qos(fc)) {
528 u8 *qc = ieee80211_get_qos_ctl(hdr);
529 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
530 if (unlikely(tid >= MAX_TID_COUNT))
531 goto drop;
532 }
533
534 /* Descriptor for chosen Tx queue */
46bc8d4b 535 txq = &il->txq[txq_id];
4bc85c13
WYG
536 q = &txq->q;
537
e2ebc833 538 if ((il_queue_space(q) < q->high_mark))
4bc85c13
WYG
539 goto drop;
540
46bc8d4b 541 spin_lock_irqsave(&il->lock, flags);
4bc85c13 542
0c2c8852 543 idx = il_get_cmd_idx(q, q->write_ptr, 0);
4bc85c13
WYG
544
545 /* Set up driver data for this TFD */
e2ebc833 546 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info));
4bc85c13 547 txq->txb[q->write_ptr].skb = skb;
7c2cde2e 548 txq->txb[q->write_ptr].ctx = &il->ctx;
4bc85c13
WYG
549
550 /* Init first empty entry in queue's array of Tx/cmd buffers */
551 out_cmd = txq->cmd[idx];
552 out_meta = &txq->meta[idx];
e2ebc833 553 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
4bc85c13
WYG
554 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
555 memset(tx_cmd, 0, sizeof(*tx_cmd));
556
557 /*
558 * Set up the Tx-command (not MAC!) header.
0c2c8852 559 * Store the chosen Tx queue and TFD idx within the sequence field;
4bc85c13
WYG
560 * after Tx, uCode's Tx response will return this value so driver can
561 * locate the frame within the tx queue and do post-tx processing.
562 */
563 out_cmd->hdr.cmd = REPLY_TX;
564 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2d09b062 565 IDX_TO_SEQ(q->write_ptr)));
4bc85c13
WYG
566
567 /* Copy MAC header from skb into command buffer */
568 memcpy(tx_cmd->hdr, hdr, hdr_len);
569
570
571 if (info->control.hw_key)
46bc8d4b 572 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
4bc85c13
WYG
573
574 /* TODO need this for burst mode later on */
46bc8d4b 575 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
4bc85c13
WYG
576
577 /* set is_hcca to 0; it probably will never be implemented */
46bc8d4b 578 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id, 0);
4bc85c13
WYG
579
580 /* Total # bytes to be transmitted */
581 len = (u16)skb->len;
582 tx_cmd->len = cpu_to_le16(len);
583
46bc8d4b
SG
584 il_dbg_log_tx_data_frame(il, len, hdr);
585 il_update_stats(il, true, fc, len);
4bc85c13
WYG
586 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
587 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
588
589 if (!ieee80211_has_morefrags(hdr->frame_control)) {
590 txq->need_update = 1;
591 } else {
592 wait_write_ptr = 1;
593 txq->need_update = 0;
594 }
595
58de00a4 596 D_TX("sequence nr = 0X%x\n",
4bc85c13 597 le16_to_cpu(out_cmd->hdr.sequence));
58de00a4 598 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
46bc8d4b
SG
599 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
600 il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd->hdr,
4bc85c13
WYG
601 ieee80211_hdrlen(fc));
602
603 /*
604 * Use the first empty entry in this queue's command buffer array
605 * to contain the Tx command and MAC header concatenated together
606 * (payload data will be in another buffer).
607 * Size of this varies, due to varying MAC header length.
608 * If end is not dword aligned, we'll have 2 extra bytes at the end
609 * of the MAC header (device reads on dword boundaries).
610 * We'll tell device about this padding later.
611 */
e2ebc833
SG
612 len = sizeof(struct il3945_tx_cmd) +
613 sizeof(struct il_cmd_header) + hdr_len;
4bc85c13
WYG
614 len = (len + 3) & ~3;
615
616 /* Physical address of this Tx command's header (not MAC header!),
617 * within command buffer array. */
46bc8d4b 618 txcmd_phys = pci_map_single(il->pci_dev, &out_cmd->hdr,
4bc85c13
WYG
619 len, PCI_DMA_TODEVICE);
620 /* we do not map meta data ... so we can safely access address to
621 * provide to unmap command*/
622 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
623 dma_unmap_len_set(out_meta, len, len);
624
625 /* Add buffer containing Tx command and MAC(!) header to TFD's
626 * first entry */
46bc8d4b 627 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
4bc85c13
WYG
628 txcmd_phys, len, 1, 0);
629
630
631 /* Set up TFD's 2nd entry to point directly to remainder of skb,
632 * if any (802.11 null frames have no payload). */
633 len = skb->len - hdr_len;
634 if (len) {
46bc8d4b 635 phys_addr = pci_map_single(il->pci_dev, skb->data + hdr_len,
4bc85c13 636 len, PCI_DMA_TODEVICE);
46bc8d4b 637 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
4bc85c13
WYG
638 phys_addr, len,
639 0, U32_PAD(len));
640 }
641
642
0c2c8852 643 /* Tell device the write idx *just past* this latest filled TFD */
e2ebc833 644 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
46bc8d4b
SG
645 il_txq_update_write_ptr(il, txq);
646 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 647
232913b5 648 if (il_queue_space(q) < q->high_mark
46bc8d4b 649 && il->mac80211_registered) {
4bc85c13 650 if (wait_write_ptr) {
46bc8d4b 651 spin_lock_irqsave(&il->lock, flags);
4bc85c13 652 txq->need_update = 1;
46bc8d4b
SG
653 il_txq_update_write_ptr(il, txq);
654 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
655 }
656
46bc8d4b 657 il_stop_queue(il, txq);
4bc85c13
WYG
658 }
659
660 return 0;
661
662drop_unlock:
46bc8d4b 663 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
664drop:
665 return -1;
666}
667
46bc8d4b 668static int il3945_get_measurement(struct il_priv *il,
4bc85c13
WYG
669 struct ieee80211_measurement_params *params,
670 u8 type)
671{
e2ebc833 672 struct il_spectrum_cmd spectrum;
dcae1c64 673 struct il_rx_pkt *pkt;
e2ebc833 674 struct il_host_cmd cmd = {
4bc85c13
WYG
675 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
676 .data = (void *)&spectrum,
677 .flags = CMD_WANT_SKB,
678 };
679 u32 add_time = le64_to_cpu(params->start_time);
680 int rc;
681 int spectrum_resp_status;
682 int duration = le16_to_cpu(params->duration);
7c2cde2e 683 struct il_rxon_context *ctx = &il->ctx;
4bc85c13 684
7c2cde2e 685 if (il_is_associated(il))
46bc8d4b
SG
686 add_time = il_usecs_to_beacons(il,
687 le64_to_cpu(params->start_time) - il->_3945.last_tsf,
4bc85c13
WYG
688 le16_to_cpu(ctx->timing.beacon_interval));
689
690 memset(&spectrum, 0, sizeof(spectrum));
691
692 spectrum.channel_count = cpu_to_le16(1);
693 spectrum.flags =
694 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
695 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
696 cmd.len = sizeof(spectrum);
697 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
698
7c2cde2e 699 if (il_is_associated(il))
4bc85c13 700 spectrum.start_time =
46bc8d4b
SG
701 il_add_beacon_time(il,
702 il->_3945.last_beacon_time, add_time,
4bc85c13
WYG
703 le16_to_cpu(ctx->timing.beacon_interval));
704 else
705 spectrum.start_time = 0;
706
707 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
708 spectrum.channels[0].channel = params->channel;
709 spectrum.channels[0].type = type;
710 if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
711 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
712 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
713
46bc8d4b 714 rc = il_send_cmd_sync(il, &cmd);
4bc85c13
WYG
715 if (rc)
716 return rc;
717
dcae1c64 718 pkt = (struct il_rx_pkt *)cmd.reply_page;
e2ebc833 719 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
9406f797 720 IL_ERR("Bad return from REPLY_RX_ON_ASSOC command\n");
4bc85c13
WYG
721 rc = -EIO;
722 }
723
724 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
725 switch (spectrum_resp_status) {
726 case 0: /* Command will be handled */
727 if (pkt->u.spectrum.id != 0xff) {
58de00a4 728 D_INFO("Replaced existing measurement: %d\n",
4bc85c13 729 pkt->u.spectrum.id);
46bc8d4b 730 il->measurement_status &= ~MEASUREMENT_READY;
4bc85c13 731 }
46bc8d4b 732 il->measurement_status |= MEASUREMENT_ACTIVE;
4bc85c13
WYG
733 rc = 0;
734 break;
735
736 case 1: /* Command will not be handled */
737 rc = -EAGAIN;
738 break;
739 }
740
46bc8d4b 741 il_free_pages(il, cmd.reply_page);
4bc85c13
WYG
742
743 return rc;
744}
745
46bc8d4b 746static void il3945_rx_reply_alive(struct il_priv *il,
b73bb5f1 747 struct il_rx_buf *rxb)
4bc85c13 748{
dcae1c64 749 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 750 struct il_alive_resp *palive;
4bc85c13
WYG
751 struct delayed_work *pwork;
752
753 palive = &pkt->u.alive_frame;
754
58de00a4 755 D_INFO("Alive ucode status 0x%08X revision "
4bc85c13
WYG
756 "0x%01X 0x%01X\n",
757 palive->is_valid, palive->ver_type,
758 palive->ver_subtype);
759
760 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 761 D_INFO("Initialization Alive received.\n");
46bc8d4b 762 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 763 sizeof(struct il_alive_resp));
46bc8d4b 764 pwork = &il->init_alive_start;
4bc85c13 765 } else {
58de00a4 766 D_INFO("Runtime Alive received.\n");
46bc8d4b 767 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 768 sizeof(struct il_alive_resp));
46bc8d4b
SG
769 pwork = &il->alive_start;
770 il3945_disable_events(il);
4bc85c13
WYG
771 }
772
773 /* We delay the ALIVE response by 5ms to
774 * give the HW RF Kill time to activate... */
775 if (palive->is_valid == UCODE_VALID_OK)
46bc8d4b 776 queue_delayed_work(il->workqueue, pwork,
4bc85c13
WYG
777 msecs_to_jiffies(5));
778 else
9406f797 779 IL_WARN("uCode did not respond OK.\n");
4bc85c13
WYG
780}
781
46bc8d4b 782static void il3945_rx_reply_add_sta(struct il_priv *il,
b73bb5f1 783 struct il_rx_buf *rxb)
4bc85c13 784{
d3175167 785#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 786 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13
WYG
787#endif
788
58de00a4 789 D_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
4bc85c13
WYG
790}
791
46bc8d4b 792static void il3945_rx_beacon_notif(struct il_priv *il,
b73bb5f1 793 struct il_rx_buf *rxb)
4bc85c13 794{
dcae1c64 795 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 796 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
d3175167 797#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
798 u8 rate = beacon->beacon_notify_hdr.rate;
799
58de00a4 800 D_RX("beacon status %x retries %d iss %d "
4bc85c13
WYG
801 "tsf %d %d rate %d\n",
802 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
803 beacon->beacon_notify_hdr.failure_frame,
804 le32_to_cpu(beacon->ibss_mgr_status),
805 le32_to_cpu(beacon->high_tsf),
806 le32_to_cpu(beacon->low_tsf), rate);
807#endif
808
46bc8d4b 809 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4bc85c13 810
4bc85c13
WYG
811}
812
813/* Handle notification from uCode that card's power state is changing
814 * due to software, hardware, or critical temperature RFKILL */
46bc8d4b 815static void il3945_rx_card_state_notif(struct il_priv *il,
b73bb5f1 816 struct il_rx_buf *rxb)
4bc85c13 817{
dcae1c64 818 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13 819 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 820 unsigned long status = il->status;
4bc85c13 821
9406f797 822 IL_WARN("Card state received: HW:%s SW:%s\n",
4bc85c13
WYG
823 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
824 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
825
841b2cca 826 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4bc85c13
WYG
827 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
828
829 if (flags & HW_CARD_DISABLED)
46bc8d4b 830 set_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13 831 else
46bc8d4b 832 clear_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13
WYG
833
834
46bc8d4b 835 il_scan_cancel(il);
4bc85c13
WYG
836
837 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
46bc8d4b
SG
838 test_bit(STATUS_RF_KILL_HW, &il->status)))
839 wiphy_rfkill_set_hw_state(il->hw->wiphy,
840 test_bit(STATUS_RF_KILL_HW, &il->status));
4bc85c13 841 else
46bc8d4b 842 wake_up(&il->wait_command_queue);
4bc85c13
WYG
843}
844
845/**
e2ebc833 846 * il3945_setup_rx_handlers - Initialize Rx handler callbacks
4bc85c13
WYG
847 *
848 * Setup the RX handlers for each of the reply types sent from the uCode
849 * to the host.
850 *
851 * This function chains into the hardware specific files for them to setup
852 * any hardware specific handlers as well.
853 */
46bc8d4b 854static void il3945_setup_rx_handlers(struct il_priv *il)
4bc85c13 855{
46bc8d4b
SG
856 il->rx_handlers[REPLY_ALIVE] = il3945_rx_reply_alive;
857 il->rx_handlers[REPLY_ADD_STA] = il3945_rx_reply_add_sta;
858 il->rx_handlers[REPLY_ERROR] = il_rx_reply_error;
859 il->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = il_rx_csa;
860 il->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
e2ebc833 861 il_rx_spectrum_measure_notif;
46bc8d4b
SG
862 il->rx_handlers[PM_SLEEP_NOTIFICATION] = il_rx_pm_sleep_notif;
863 il->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
ebf0d90d 864 il_rx_pm_debug_stats_notif;
46bc8d4b 865 il->rx_handlers[BEACON_NOTIFICATION] = il3945_rx_beacon_notif;
4bc85c13
WYG
866
867 /*
868 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG
869 * stats request from the host as well as for the periodic
870 * stats notifications (after received beacons) from the uCode.
4bc85c13 871 */
ebf0d90d
SG
872 il->rx_handlers[REPLY_STATISTICS_CMD] = il3945_reply_stats;
873 il->rx_handlers[STATISTICS_NOTIFICATION] = il3945_hw_rx_stats;
4bc85c13 874
46bc8d4b
SG
875 il_setup_rx_scan_handlers(il);
876 il->rx_handlers[CARD_STATE_NOTIFICATION] = il3945_rx_card_state_notif;
4bc85c13
WYG
877
878 /* Set up hardware specific Rx handlers */
46bc8d4b 879 il3945_hw_rx_handler_setup(il);
4bc85c13
WYG
880}
881
882/************************** RX-FUNCTIONS ****************************/
883/*
884 * Rx theory of operation
885 *
886 * The host allocates 32 DMA target addresses and passes the host address
3b98c7f4 887 * to the firmware at register IL_RFDS_TBL_LOWER + N * RFD_SIZE where N is
4bc85c13
WYG
888 * 0 to 31
889 *
890 * Rx Queue Indexes
0c2c8852 891 * The host/firmware share two idx registers for managing the Rx buffers.
4bc85c13 892 *
0c2c8852 893 * The READ idx maps to the first position that the firmware may be writing
4bc85c13
WYG
894 * to -- the driver can read up to (but not including) this position and get
895 * good data.
0c2c8852 896 * The READ idx is managed by the firmware once the card is enabled.
4bc85c13 897 *
0c2c8852 898 * The WRITE idx maps to the last position the driver has read from -- the
4bc85c13
WYG
899 * position preceding WRITE is the last slot the firmware can place a packet.
900 *
901 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
902 * WRITE = READ.
903 *
904 * During initialization, the host sets up the READ queue position to the first
2d09b062 905 * IDX position, and WRITE to the last (READ - 1 wrapped)
4bc85c13 906 *
0c2c8852
SG
907 * When the firmware places a packet in a buffer, it will advance the READ idx
908 * and fire the RX interrupt. The driver can then query the READ idx and
909 * process as many packets as possible, moving the WRITE idx forward as it
4bc85c13
WYG
910 * resets the Rx queue buffers with new memory.
911 *
912 * The management in the driver is as follows:
913 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
914 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
915 * to replenish the iwl->rxq->rx_free.
e2ebc833 916 * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the
2d09b062 917 * iwl->rxq is replenished and the READ IDX is updated (updating the
0c2c8852 918 * 'processed' and 'read' driver idxes as well)
4bc85c13 919 * + A received packet is processed and handed to the kernel network stack,
0c2c8852 920 * detached from the iwl->rxq. The driver 'processed' idx is updated.
4bc85c13
WYG
921 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
922 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2d09b062 923 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
4bc85c13
WYG
924 * were enough free buffers and RX_STALLED is set it is cleared.
925 *
926 *
927 * Driver sequence:
928 *
e2ebc833
SG
929 * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
930 * il3945_rx_queue_restock
931 * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx
4bc85c13 932 * queue, updates firmware pointers, and updates
0c2c8852 933 * the WRITE idx. If insufficient rx_free buffers
e2ebc833 934 * are available, schedules il3945_rx_replenish
4bc85c13
WYG
935 *
936 * -- enable interrupts --
b73bb5f1 937 * ISR - il3945_rx() Detach il_rx_bufs from pool up to the
2d09b062 938 * READ IDX, detaching the SKB from the pool.
4bc85c13 939 * Moves the packet buffer from queue to rx_used.
e2ebc833 940 * Calls il3945_rx_queue_restock to refill any empty
4bc85c13
WYG
941 * slots.
942 * ...
943 *
944 */
945
946/**
e2ebc833 947 * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
4bc85c13 948 */
46bc8d4b 949static inline __le32 il3945_dma_addr2rbd_ptr(struct il_priv *il,
4bc85c13
WYG
950 dma_addr_t dma_addr)
951{
952 return cpu_to_le32((u32)dma_addr);
953}
954
955/**
e2ebc833 956 * il3945_rx_queue_restock - refill RX queue from pre-allocated pool
4bc85c13
WYG
957 *
958 * If there are slots in the RX queue that need to be restocked,
959 * and we have free pre-allocated buffers, fill the ranks as much
960 * as we can, pulling from rx_free.
961 *
0c2c8852 962 * This moves the 'write' idx forward to catch up with 'processed', and
4bc85c13
WYG
963 * also updates the memory address in the firmware to reference the new
964 * target buffer.
965 */
46bc8d4b 966static void il3945_rx_queue_restock(struct il_priv *il)
4bc85c13 967{
46bc8d4b 968 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 969 struct list_head *element;
b73bb5f1 970 struct il_rx_buf *rxb;
4bc85c13
WYG
971 unsigned long flags;
972 int write;
973
974 spin_lock_irqsave(&rxq->lock, flags);
975 write = rxq->write & ~0x7;
232913b5 976 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
4bc85c13
WYG
977 /* Get next free Rx buffer, remove from free list */
978 element = rxq->rx_free.next;
b73bb5f1 979 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
980 list_del(element);
981
982 /* Point to Rx buffer via next RBD in circular buffer */
46bc8d4b 983 rxq->bd[rxq->write] = il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
4bc85c13
WYG
984 rxq->queue[rxq->write] = rxb;
985 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
986 rxq->free_count--;
987 }
988 spin_unlock_irqrestore(&rxq->lock, flags);
989 /* If the pre-allocated buffer pool is dropping low, schedule to
990 * refill it */
991 if (rxq->free_count <= RX_LOW_WATERMARK)
46bc8d4b 992 queue_work(il->workqueue, &il->rx_replenish);
4bc85c13
WYG
993
994
995 /* If we've added more space for the firmware to place data, tell it.
996 * Increment device's write pointer in multiples of 8. */
232913b5
SG
997 if (rxq->write_actual != (rxq->write & ~0x7) ||
998 abs(rxq->write - rxq->read) > 7) {
4bc85c13
WYG
999 spin_lock_irqsave(&rxq->lock, flags);
1000 rxq->need_update = 1;
1001 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 1002 il_rx_queue_update_write_ptr(il, rxq);
4bc85c13
WYG
1003 }
1004}
1005
1006/**
e2ebc833 1007 * il3945_rx_replenish - Move all used packet from rx_used to rx_free
4bc85c13
WYG
1008 *
1009 * When moving to rx_free an SKB is allocated for the slot.
1010 *
e2ebc833 1011 * Also restock the Rx queue via il3945_rx_queue_restock.
4bc85c13
WYG
1012 * This is called as a scheduled work item (except for during initialization)
1013 */
46bc8d4b 1014static void il3945_rx_allocate(struct il_priv *il, gfp_t priority)
4bc85c13 1015{
46bc8d4b 1016 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 1017 struct list_head *element;
b73bb5f1 1018 struct il_rx_buf *rxb;
4bc85c13
WYG
1019 struct page *page;
1020 unsigned long flags;
1021 gfp_t gfp_mask = priority;
1022
1023 while (1) {
1024 spin_lock_irqsave(&rxq->lock, flags);
1025
1026 if (list_empty(&rxq->rx_used)) {
1027 spin_unlock_irqrestore(&rxq->lock, flags);
1028 return;
1029 }
1030 spin_unlock_irqrestore(&rxq->lock, flags);
1031
1032 if (rxq->free_count > RX_LOW_WATERMARK)
1033 gfp_mask |= __GFP_NOWARN;
1034
46bc8d4b 1035 if (il->hw_params.rx_page_order > 0)
4bc85c13
WYG
1036 gfp_mask |= __GFP_COMP;
1037
1038 /* Alloc a new receive buffer */
46bc8d4b 1039 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
4bc85c13
WYG
1040 if (!page) {
1041 if (net_ratelimit())
58de00a4 1042 D_INFO("Failed to allocate SKB buffer.\n");
232913b5 1043 if (rxq->free_count <= RX_LOW_WATERMARK &&
4bc85c13 1044 net_ratelimit())
b6297cd2 1045 IL_ERR("Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
4bc85c13
WYG
1046 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1047 rxq->free_count);
1048 /* We don't reschedule replenish work here -- we will
1049 * call the restock method and if it still needs
1050 * more buffers it will schedule replenish */
1051 break;
1052 }
1053
1054 spin_lock_irqsave(&rxq->lock, flags);
1055 if (list_empty(&rxq->rx_used)) {
1056 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 1057 __free_pages(page, il->hw_params.rx_page_order);
4bc85c13
WYG
1058 return;
1059 }
1060 element = rxq->rx_used.next;
b73bb5f1 1061 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
1062 list_del(element);
1063 spin_unlock_irqrestore(&rxq->lock, flags);
1064
1065 rxb->page = page;
1066 /* Get physical address of RB/SKB */
46bc8d4b
SG
1067 rxb->page_dma = pci_map_page(il->pci_dev, page, 0,
1068 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13
WYG
1069 PCI_DMA_FROMDEVICE);
1070
1071 spin_lock_irqsave(&rxq->lock, flags);
1072
1073 list_add_tail(&rxb->list, &rxq->rx_free);
1074 rxq->free_count++;
46bc8d4b 1075 il->alloc_rxb_page++;
4bc85c13
WYG
1076
1077 spin_unlock_irqrestore(&rxq->lock, flags);
1078 }
1079}
1080
46bc8d4b 1081void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1082{
1083 unsigned long flags;
1084 int i;
1085 spin_lock_irqsave(&rxq->lock, flags);
1086 INIT_LIST_HEAD(&rxq->rx_free);
1087 INIT_LIST_HEAD(&rxq->rx_used);
1088 /* Fill the rx_used queue with _all_ of the Rx buffers */
1089 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1090 /* In the reset function, these buffers may have been allocated
1091 * to an SKB, so we need to unmap and free potential storage */
1092 if (rxq->pool[i].page != NULL) {
46bc8d4b
SG
1093 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1094 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13 1095 PCI_DMA_FROMDEVICE);
46bc8d4b 1096 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1097 rxq->pool[i].page = NULL;
1098 }
1099 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1100 }
1101
1102 /* Set us so that we have processed and used all buffers, but have
1103 * not restocked the Rx queue with fresh buffers */
1104 rxq->read = rxq->write = 0;
1105 rxq->write_actual = 0;
1106 rxq->free_count = 0;
1107 spin_unlock_irqrestore(&rxq->lock, flags);
1108}
1109
e2ebc833 1110void il3945_rx_replenish(void *data)
4bc85c13 1111{
46bc8d4b 1112 struct il_priv *il = data;
4bc85c13
WYG
1113 unsigned long flags;
1114
46bc8d4b 1115 il3945_rx_allocate(il, GFP_KERNEL);
4bc85c13 1116
46bc8d4b
SG
1117 spin_lock_irqsave(&il->lock, flags);
1118 il3945_rx_queue_restock(il);
1119 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1120}
1121
46bc8d4b 1122static void il3945_rx_replenish_now(struct il_priv *il)
4bc85c13 1123{
46bc8d4b 1124 il3945_rx_allocate(il, GFP_ATOMIC);
4bc85c13 1125
46bc8d4b 1126 il3945_rx_queue_restock(il);
4bc85c13
WYG
1127}
1128
1129
1130/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1131 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1132 * This free routine walks the list of POOL entries and if SKB is set to
1133 * non NULL it is unmapped and freed
1134 */
46bc8d4b 1135static void il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1136{
1137 int i;
1138 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1139 if (rxq->pool[i].page != NULL) {
46bc8d4b
SG
1140 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1141 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13 1142 PCI_DMA_FROMDEVICE);
46bc8d4b 1143 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1144 rxq->pool[i].page = NULL;
1145 }
1146 }
1147
46bc8d4b 1148 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4bc85c13 1149 rxq->bd_dma);
46bc8d4b 1150 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
4bc85c13
WYG
1151 rxq->rb_stts, rxq->rb_stts_dma);
1152 rxq->bd = NULL;
1153 rxq->rb_stts = NULL;
1154}
1155
1156
1157/* Convert linear signal-to-noise ratio into dB */
1158static u8 ratio2dB[100] = {
1159/* 0 1 2 3 4 5 6 7 8 9 */
1160 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1161 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1162 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1163 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1164 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1165 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1166 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1167 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1168 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1169 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1170};
1171
1172/* Calculates a relative dB value from a ratio of linear
1173 * (i.e. not dB) signal levels.
1174 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
e2ebc833 1175int il3945_calc_db_from_ratio(int sig_ratio)
4bc85c13
WYG
1176{
1177 /* 1000:1 or higher just report as 60 dB */
1178 if (sig_ratio >= 1000)
1179 return 60;
1180
1181 /* 100:1 or higher, divide by 10 and use table,
1182 * add 20 dB to make up for divide by 10 */
1183 if (sig_ratio >= 100)
1184 return 20 + (int)ratio2dB[sig_ratio/10];
1185
1186 /* We shouldn't see this */
1187 if (sig_ratio < 1)
1188 return 0;
1189
1190 /* Use table for ratios 1:1 - 99:1 */
1191 return (int)ratio2dB[sig_ratio];
1192}
1193
1194/**
e2ebc833 1195 * il3945_rx_handle - Main entry function for receiving responses from uCode
4bc85c13 1196 *
46bc8d4b 1197 * Uses the il->rx_handlers callback function array to invoke
4bc85c13
WYG
1198 * the appropriate handlers, including command responses,
1199 * frame-received notifications, and other notifications.
1200 */
46bc8d4b 1201static void il3945_rx_handle(struct il_priv *il)
4bc85c13 1202{
b73bb5f1 1203 struct il_rx_buf *rxb;
dcae1c64 1204 struct il_rx_pkt *pkt;
46bc8d4b 1205 struct il_rx_queue *rxq = &il->rxq;
4bc85c13
WYG
1206 u32 r, i;
1207 int reclaim;
1208 unsigned long flags;
1209 u8 fill_rx = 0;
1210 u32 count = 8;
1211 int total_empty = 0;
1212
0c2c8852 1213 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
4bc85c13
WYG
1214 * buffer that the driver may process (last buffer filled by ucode). */
1215 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1216 i = rxq->read;
1217
1218 /* calculate total frames need to be restock after handling RX */
1219 total_empty = r - rxq->write_actual;
1220 if (total_empty < 0)
1221 total_empty += RX_QUEUE_SIZE;
1222
1223 if (total_empty > (RX_QUEUE_SIZE / 2))
1224 fill_rx = 1;
1225 /* Rx interrupt, but nothing sent from uCode */
1226 if (i == r)
58de00a4 1227 D_RX("r = %d, i = %d\n", r, i);
4bc85c13
WYG
1228
1229 while (i != r) {
1230 int len;
1231
1232 rxb = rxq->queue[i];
1233
1234 /* If an RXB doesn't have a Rx queue slot associated with it,
1235 * then a bug has been introduced in the queue refilling
1236 * routines -- catch it here */
1237 BUG_ON(rxb == NULL);
1238
1239 rxq->queue[i] = NULL;
1240
46bc8d4b
SG
1241 pci_unmap_page(il->pci_dev, rxb->page_dma,
1242 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13
WYG
1243 PCI_DMA_FROMDEVICE);
1244 pkt = rxb_addr(rxb);
1245
1246 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1247 len += sizeof(u32); /* account for status word */
4bc85c13
WYG
1248
1249 /* Reclaim a command buffer only if this packet is a response
1250 * to a (driver-originated) command.
1251 * If the packet (e.g. Rx frame) originated from uCode,
1252 * there is no command buffer to reclaim.
1253 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1254 * but apparently a few don't get set; catch them here. */
1255 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
232913b5
SG
1256 pkt->hdr.cmd != STATISTICS_NOTIFICATION &&
1257 pkt->hdr.cmd != REPLY_TX;
4bc85c13
WYG
1258
1259 /* Based on type of command response or notification,
1260 * handle those that need handling via function in
e2ebc833 1261 * rx_handlers table. See il3945_setup_rx_handlers() */
46bc8d4b 1262 if (il->rx_handlers[pkt->hdr.cmd]) {
58de00a4 1263 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
e2ebc833 1264 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
46bc8d4b
SG
1265 il->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1266 il->rx_handlers[pkt->hdr.cmd] (il, rxb);
4bc85c13
WYG
1267 } else {
1268 /* No handling needed */
58de00a4 1269 D_RX(
4bc85c13 1270 "r %d i %d No handler needed for %s, 0x%02x\n",
e2ebc833 1271 r, i, il_get_cmd_string(pkt->hdr.cmd),
4bc85c13
WYG
1272 pkt->hdr.cmd);
1273 }
1274
1275 /*
1276 * XXX: After here, we should always check rxb->page
1277 * against NULL before touching it or its virtual
1278 * memory (pkt). Because some rx_handler might have
1279 * already taken or freed the pages.
1280 */
1281
1282 if (reclaim) {
1283 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 1284 * and fire off the (possibly) blocking il_send_cmd()
4bc85c13
WYG
1285 * as we reclaim the driver command queue */
1286 if (rxb->page)
46bc8d4b 1287 il_tx_cmd_complete(il, rxb);
4bc85c13 1288 else
9406f797 1289 IL_WARN("Claim null rxb?\n");
4bc85c13
WYG
1290 }
1291
1292 /* Reuse the page if possible. For notification packets and
1293 * SKBs that fail to Rx correctly, add them back into the
1294 * rx_free list for reuse later. */
1295 spin_lock_irqsave(&rxq->lock, flags);
1296 if (rxb->page != NULL) {
46bc8d4b
SG
1297 rxb->page_dma = pci_map_page(il->pci_dev, rxb->page,
1298 0, PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13
WYG
1299 PCI_DMA_FROMDEVICE);
1300 list_add_tail(&rxb->list, &rxq->rx_free);
1301 rxq->free_count++;
1302 } else
1303 list_add_tail(&rxb->list, &rxq->rx_used);
1304
1305 spin_unlock_irqrestore(&rxq->lock, flags);
1306
1307 i = (i + 1) & RX_QUEUE_MASK;
1308 /* If there are a lot of unused frames,
1309 * restock the Rx queue so ucode won't assert. */
1310 if (fill_rx) {
1311 count++;
1312 if (count >= 8) {
1313 rxq->read = i;
46bc8d4b 1314 il3945_rx_replenish_now(il);
4bc85c13
WYG
1315 count = 0;
1316 }
1317 }
1318 }
1319
1320 /* Backtrack one entry */
1321 rxq->read = i;
1322 if (fill_rx)
46bc8d4b 1323 il3945_rx_replenish_now(il);
4bc85c13 1324 else
46bc8d4b 1325 il3945_rx_queue_restock(il);
4bc85c13
WYG
1326}
1327
1328/* call this function to flush any scheduled tasklet */
46bc8d4b 1329static inline void il3945_synchronize_irq(struct il_priv *il)
4bc85c13
WYG
1330{
1331 /* wait to make sure we flush pending tasklet*/
46bc8d4b
SG
1332 synchronize_irq(il->pci_dev->irq);
1333 tasklet_kill(&il->irq_tasklet);
4bc85c13
WYG
1334}
1335
e2ebc833 1336static const char *il3945_desc_lookup(int i)
4bc85c13
WYG
1337{
1338 switch (i) {
1339 case 1:
1340 return "FAIL";
1341 case 2:
1342 return "BAD_PARAM";
1343 case 3:
1344 return "BAD_CHECKSUM";
1345 case 4:
1346 return "NMI_INTERRUPT";
1347 case 5:
1348 return "SYSASSERT";
1349 case 6:
1350 return "FATAL_ERROR";
1351 }
1352
1353 return "UNKNOWN";
1354}
1355
1356#define ERROR_START_OFFSET (1 * sizeof(u32))
1357#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1358
46bc8d4b 1359void il3945_dump_nic_error_log(struct il_priv *il)
4bc85c13
WYG
1360{
1361 u32 i;
1362 u32 desc, time, count, base, data1;
1363 u32 blink1, blink2, ilink1, ilink2;
1364
46bc8d4b 1365 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
4bc85c13 1366
e2ebc833 1367 if (!il3945_hw_valid_rtc_data_addr(base)) {
9406f797 1368 IL_ERR("Not valid error log pointer 0x%08X\n", base);
4bc85c13
WYG
1369 return;
1370 }
1371
1372
46bc8d4b 1373 count = il_read_targ_mem(il, base);
4bc85c13
WYG
1374
1375 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797
SG
1376 IL_ERR("Start IWL Error Log Dump:\n");
1377 IL_ERR("Status: 0x%08lX, count: %d\n",
46bc8d4b 1378 il->status, count);
4bc85c13
WYG
1379 }
1380
9406f797 1381 IL_ERR("Desc Time asrtPC blink2 "
4bc85c13
WYG
1382 "ilink1 nmiPC Line\n");
1383 for (i = ERROR_START_OFFSET;
1384 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1385 i += ERROR_ELEM_SIZE) {
46bc8d4b 1386 desc = il_read_targ_mem(il, base + i);
4bc85c13 1387 time =
46bc8d4b 1388 il_read_targ_mem(il, base + i + 1 * sizeof(u32));
4bc85c13 1389 blink1 =
46bc8d4b 1390 il_read_targ_mem(il, base + i + 2 * sizeof(u32));
4bc85c13 1391 blink2 =
46bc8d4b 1392 il_read_targ_mem(il, base + i + 3 * sizeof(u32));
4bc85c13 1393 ilink1 =
46bc8d4b 1394 il_read_targ_mem(il, base + i + 4 * sizeof(u32));
4bc85c13 1395 ilink2 =
46bc8d4b 1396 il_read_targ_mem(il, base + i + 5 * sizeof(u32));
4bc85c13 1397 data1 =
46bc8d4b 1398 il_read_targ_mem(il, base + i + 6 * sizeof(u32));
4bc85c13 1399
9406f797 1400 IL_ERR(
4bc85c13 1401 "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
e2ebc833 1402 il3945_desc_lookup(desc), desc, time, blink1, blink2,
4bc85c13 1403 ilink1, ilink2, data1);
4bc85c13
WYG
1404 }
1405}
1406
46bc8d4b 1407static void il3945_irq_tasklet(struct il_priv *il)
4bc85c13
WYG
1408{
1409 u32 inta, handled = 0;
1410 u32 inta_fh;
1411 unsigned long flags;
d3175167 1412#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
1413 u32 inta_mask;
1414#endif
1415
46bc8d4b 1416 spin_lock_irqsave(&il->lock, flags);
4bc85c13
WYG
1417
1418 /* Ack/clear/reset pending uCode interrupts.
1419 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1420 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG
1421 inta = _il_rd(il, CSR_INT);
1422 _il_wr(il, CSR_INT, inta);
4bc85c13
WYG
1423
1424 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1425 * Any new interrupts that happen after this, either while we're
1426 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG
1427 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1428 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4bc85c13 1429
d3175167 1430#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1431 if (il_get_debug_level(il) & IL_DL_ISR) {
4bc85c13 1432 /* just for debug */
841b2cca 1433 inta_mask = _il_rd(il, CSR_INT_MASK);
58de00a4 1434 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4bc85c13
WYG
1435 inta, inta_mask, inta_fh);
1436 }
1437#endif
1438
46bc8d4b 1439 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1440
1441 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1442 * atomic, make sure that inta covers all the interrupts that
1443 * we've discovered, even if FH interrupt came in just after
1444 * reading CSR_INT. */
1445 if (inta_fh & CSR39_FH_INT_RX_MASK)
1446 inta |= CSR_INT_BIT_FH_RX;
1447 if (inta_fh & CSR39_FH_INT_TX_MASK)
1448 inta |= CSR_INT_BIT_FH_TX;
1449
1450 /* Now service all interrupt bits discovered above. */
1451 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 1452 IL_ERR("Hardware error detected. Restarting.\n");
4bc85c13
WYG
1453
1454 /* Tell the device to stop sending interrupts */
46bc8d4b 1455 il_disable_interrupts(il);
4bc85c13 1456
46bc8d4b
SG
1457 il->isr_stats.hw++;
1458 il_irq_handle_error(il);
4bc85c13
WYG
1459
1460 handled |= CSR_INT_BIT_HW_ERR;
1461
1462 return;
1463 }
1464
d3175167 1465#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1466 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4bc85c13
WYG
1467 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1468 if (inta & CSR_INT_BIT_SCD) {
58de00a4 1469 D_ISR("Scheduler finished to transmit "
4bc85c13 1470 "the frame/frames.\n");
46bc8d4b 1471 il->isr_stats.sch++;
4bc85c13
WYG
1472 }
1473
1474 /* Alive notification via Rx interrupt will do the real work */
1475 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 1476 D_ISR("Alive interrupt\n");
46bc8d4b 1477 il->isr_stats.alive++;
4bc85c13
WYG
1478 }
1479 }
1480#endif
1481 /* Safely ignore these bits for debug checks below */
1482 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1483
1484 /* Error detected by uCode */
1485 if (inta & CSR_INT_BIT_SW_ERR) {
9406f797 1486 IL_ERR("Microcode SW error detected. "
4bc85c13 1487 "Restarting 0x%X.\n", inta);
46bc8d4b
SG
1488 il->isr_stats.sw++;
1489 il_irq_handle_error(il);
4bc85c13
WYG
1490 handled |= CSR_INT_BIT_SW_ERR;
1491 }
1492
1493 /* uCode wakes up after power-down sleep */
1494 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 1495 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG
1496 il_rx_queue_update_write_ptr(il, &il->rxq);
1497 il_txq_update_write_ptr(il, &il->txq[0]);
1498 il_txq_update_write_ptr(il, &il->txq[1]);
1499 il_txq_update_write_ptr(il, &il->txq[2]);
1500 il_txq_update_write_ptr(il, &il->txq[3]);
1501 il_txq_update_write_ptr(il, &il->txq[4]);
1502 il_txq_update_write_ptr(il, &il->txq[5]);
1503
1504 il->isr_stats.wakeup++;
4bc85c13
WYG
1505 handled |= CSR_INT_BIT_WAKEUP;
1506 }
1507
1508 /* All uCode command responses, including Tx command responses,
1509 * Rx "responses" (frame-received notification), and other
1510 * notifications from uCode come through here*/
1511 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG
1512 il3945_rx_handle(il);
1513 il->isr_stats.rx++;
4bc85c13
WYG
1514 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1515 }
1516
1517 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 1518 D_ISR("Tx interrupt\n");
46bc8d4b 1519 il->isr_stats.tx++;
4bc85c13 1520
841b2cca 1521 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
0c1a94e2 1522 il_wr(il, FH39_TCSR_CREDIT
4bc85c13
WYG
1523 (FH39_SRVC_CHNL), 0x0);
1524 handled |= CSR_INT_BIT_FH_TX;
1525 }
1526
1527 if (inta & ~handled) {
9406f797 1528 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 1529 il->isr_stats.unhandled++;
4bc85c13
WYG
1530 }
1531
46bc8d4b 1532 if (inta & ~il->inta_mask) {
9406f797 1533 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
46bc8d4b 1534 inta & ~il->inta_mask);
9406f797 1535 IL_WARN(" with FH_INT = 0x%08x\n", inta_fh);
4bc85c13
WYG
1536 }
1537
1538 /* Re-enable all interrupts */
1539 /* only Re-enable if disabled by irq */
46bc8d4b
SG
1540 if (test_bit(STATUS_INT_ENABLED, &il->status))
1541 il_enable_interrupts(il);
4bc85c13 1542
d3175167 1543#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1544 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG
1545 inta = _il_rd(il, CSR_INT);
1546 inta_mask = _il_rd(il, CSR_INT_MASK);
1547 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
58de00a4 1548 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4bc85c13
WYG
1549 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1550 }
1551#endif
1552}
1553
46bc8d4b 1554static int il3945_get_channels_for_scan(struct il_priv *il,
4bc85c13
WYG
1555 enum ieee80211_band band,
1556 u8 is_active, u8 n_probes,
e2ebc833 1557 struct il3945_scan_channel *scan_ch,
4bc85c13
WYG
1558 struct ieee80211_vif *vif)
1559{
1560 struct ieee80211_channel *chan;
1561 const struct ieee80211_supported_band *sband;
e2ebc833 1562 const struct il_channel_info *ch_info;
4bc85c13
WYG
1563 u16 passive_dwell = 0;
1564 u16 active_dwell = 0;
1565 int added, i;
1566
46bc8d4b 1567 sband = il_get_hw_mode(il, band);
4bc85c13
WYG
1568 if (!sband)
1569 return 0;
1570
46bc8d4b
SG
1571 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1572 passive_dwell = il_get_passive_dwell_time(il, band, vif);
4bc85c13
WYG
1573
1574 if (passive_dwell <= active_dwell)
1575 passive_dwell = active_dwell + 1;
1576
46bc8d4b
SG
1577 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1578 chan = il->scan_request->channels[i];
4bc85c13
WYG
1579
1580 if (chan->band != band)
1581 continue;
1582
1583 scan_ch->channel = chan->hw_value;
1584
46bc8d4b 1585 ch_info = il_get_channel_info(il, band,
be663ab6 1586 scan_ch->channel);
e2ebc833 1587 if (!il_is_channel_valid(ch_info)) {
58de00a4 1588 D_SCAN(
be663ab6
WYG
1589 "Channel %d is INVALID for this band.\n",
1590 scan_ch->channel);
4bc85c13
WYG
1591 continue;
1592 }
1593
1594 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1595 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1596 /* If passive , set up for auto-switch
1597 * and use long active_dwell time.
1598 */
e2ebc833 1599 if (!is_active || il_is_channel_passive(ch_info) ||
4bc85c13
WYG
1600 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
1601 scan_ch->type = 0; /* passive */
46bc8d4b 1602 if (IL_UCODE_API(il->ucode_ver) == 1)
4bc85c13
WYG
1603 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1604 } else {
1605 scan_ch->type = 1; /* active */
1606 }
1607
1608 /* Set direct probe bits. These may be used both for active
1609 * scan channels (probes gets sent right away),
1610 * or for passive channels (probes get se sent only after
1611 * hearing clear Rx packet).*/
46bc8d4b 1612 if (IL_UCODE_API(il->ucode_ver) >= 2) {
4bc85c13 1613 if (n_probes)
d3175167 1614 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1615 } else {
1616 /* uCode v1 does not allow setting direct probe bits on
1617 * passive channel. */
1618 if ((scan_ch->type & 1) && n_probes)
d3175167 1619 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1620 }
1621
1622 /* Set txpower levels to defaults */
1623 scan_ch->tpc.dsp_atten = 110;
1624 /* scan_pwr_info->tpc.dsp_atten; */
1625
1626 /*scan_pwr_info->tpc.tx_gain; */
1627 if (band == IEEE80211_BAND_5GHZ)
1628 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1629 else {
1630 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1631 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1632 * power level:
1633 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
1634 */
1635 }
1636
58de00a4 1637 D_SCAN("Scanning %d [%s %d]\n",
4bc85c13
WYG
1638 scan_ch->channel,
1639 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1640 (scan_ch->type & 1) ?
1641 active_dwell : passive_dwell);
1642
1643 scan_ch++;
1644 added++;
1645 }
1646
58de00a4 1647 D_SCAN("total channels to scan %d\n", added);
4bc85c13
WYG
1648 return added;
1649}
1650
46bc8d4b 1651static void il3945_init_hw_rates(struct il_priv *il,
4bc85c13
WYG
1652 struct ieee80211_rate *rates)
1653{
1654 int i;
1655
2eb05816 1656 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
e2ebc833 1657 rates[i].bitrate = il3945_rates[i].ieee * 5;
0c2c8852 1658 rates[i].hw_value = i; /* Rate scaling will work on idxes */
4bc85c13
WYG
1659 rates[i].hw_value_short = i;
1660 rates[i].flags = 0;
d3175167 1661 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
4bc85c13
WYG
1662 /*
1663 * If CCK != 1M then set short preamble rate flag.
1664 */
e2ebc833 1665 rates[i].flags |= (il3945_rates[i].plcp == 10) ?
4bc85c13
WYG
1666 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1667 }
1668 }
1669}
1670
1671/******************************************************************************
1672 *
1673 * uCode download functions
1674 *
1675 ******************************************************************************/
1676
46bc8d4b 1677static void il3945_dealloc_ucode_pci(struct il_priv *il)
4bc85c13 1678{
46bc8d4b
SG
1679 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1680 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1681 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1682 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1683 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1684 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13
WYG
1685}
1686
1687/**
e2ebc833 1688 * il3945_verify_inst_full - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1689 * looking at all data.
1690 */
46bc8d4b 1691static int il3945_verify_inst_full(struct il_priv *il, __le32 *image, u32 len)
4bc85c13
WYG
1692{
1693 u32 val;
1694 u32 save_len = len;
1695 int rc = 0;
1696 u32 errcnt;
1697
58de00a4 1698 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1699
0c1a94e2 1700 il_wr(il, HBUS_TARG_MEM_RADDR,
d3175167 1701 IL39_RTC_INST_LOWER_BOUND);
4bc85c13
WYG
1702
1703 errcnt = 0;
1704 for (; len > 0; len -= sizeof(u32), image++) {
1705 /* read data comes through single port, auto-incr addr */
1706 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1707 * if IL_DL_IO is set */
1c8cae57 1708 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1709 if (val != le32_to_cpu(*image)) {
9406f797 1710 IL_ERR("uCode INST section is invalid at "
4bc85c13
WYG
1711 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1712 save_len - len, val, le32_to_cpu(*image));
1713 rc = -EIO;
1714 errcnt++;
1715 if (errcnt >= 20)
1716 break;
1717 }
1718 }
1719
1720
1721 if (!errcnt)
58de00a4 1722 D_INFO(
4bc85c13
WYG
1723 "ucode image in INSTRUCTION memory is good\n");
1724
1725 return rc;
1726}
1727
1728
1729/**
e2ebc833 1730 * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1731 * using sample data 100 bytes apart. If these sample points are good,
1732 * it's a pretty good bet that everything between them is good, too.
1733 */
46bc8d4b 1734static int il3945_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len)
4bc85c13
WYG
1735{
1736 u32 val;
1737 int rc = 0;
1738 u32 errcnt = 0;
1739 u32 i;
1740
58de00a4 1741 D_INFO("ucode inst image size is %u\n", len);
4bc85c13
WYG
1742
1743 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1744 /* read data comes through single port, auto-incr addr */
1745 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1746 * if IL_DL_IO is set */
0c1a94e2 1747 il_wr(il, HBUS_TARG_MEM_RADDR,
d3175167 1748 i + IL39_RTC_INST_LOWER_BOUND);
1c8cae57 1749 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13
WYG
1750 if (val != le32_to_cpu(*image)) {
1751#if 0 /* Enable this if you want to see details */
9406f797 1752 IL_ERR("uCode INST section is invalid at "
4bc85c13
WYG
1753 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1754 i, val, *image);
1755#endif
1756 rc = -EIO;
1757 errcnt++;
1758 if (errcnt >= 3)
1759 break;
1760 }
1761 }
1762
1763 return rc;
1764}
1765
1766
1767/**
e2ebc833 1768 * il3945_verify_ucode - determine which instruction image is in SRAM,
4bc85c13
WYG
1769 * and verify its contents
1770 */
46bc8d4b 1771static int il3945_verify_ucode(struct il_priv *il)
4bc85c13
WYG
1772{
1773 __le32 *image;
1774 u32 len;
1775 int rc = 0;
1776
1777 /* Try bootstrap */
46bc8d4b
SG
1778 image = (__le32 *)il->ucode_boot.v_addr;
1779 len = il->ucode_boot.len;
1780 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1781 if (rc == 0) {
58de00a4 1782 D_INFO("Bootstrap uCode is good in inst SRAM\n");
4bc85c13
WYG
1783 return 0;
1784 }
1785
1786 /* Try initialize */
46bc8d4b
SG
1787 image = (__le32 *)il->ucode_init.v_addr;
1788 len = il->ucode_init.len;
1789 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1790 if (rc == 0) {
58de00a4 1791 D_INFO("Initialize uCode is good in inst SRAM\n");
4bc85c13
WYG
1792 return 0;
1793 }
1794
1795 /* Try runtime/protocol */
46bc8d4b
SG
1796 image = (__le32 *)il->ucode_code.v_addr;
1797 len = il->ucode_code.len;
1798 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1799 if (rc == 0) {
58de00a4 1800 D_INFO("Runtime uCode is good in inst SRAM\n");
4bc85c13
WYG
1801 return 0;
1802 }
1803
9406f797 1804 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
4bc85c13
WYG
1805
1806 /* Since nothing seems to match, show first several data entries in
1807 * instruction SRAM, so maybe visual inspection will give a clue.
1808 * Selection of bootstrap image (vs. other images) is arbitrary. */
46bc8d4b
SG
1809 image = (__le32 *)il->ucode_boot.v_addr;
1810 len = il->ucode_boot.len;
1811 rc = il3945_verify_inst_full(il, image, len);
4bc85c13
WYG
1812
1813 return rc;
1814}
1815
46bc8d4b 1816static void il3945_nic_start(struct il_priv *il)
4bc85c13
WYG
1817{
1818 /* Remove all resets to allow NIC to operate */
841b2cca 1819 _il_wr(il, CSR_RESET, 0);
4bc85c13
WYG
1820}
1821
d3175167 1822#define IL3945_UCODE_GET(item) \
e2ebc833 1823static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
4bc85c13 1824{ \
be663ab6 1825 return le32_to_cpu(ucode->v1.item); \
4bc85c13
WYG
1826}
1827
e2ebc833 1828static u32 il3945_ucode_get_header_size(u32 api_ver)
4bc85c13
WYG
1829{
1830 return 24;
1831}
1832
e2ebc833 1833static u8 *il3945_ucode_get_data(const struct il_ucode_header *ucode)
4bc85c13 1834{
be663ab6 1835 return (u8 *) ucode->v1.data;
4bc85c13
WYG
1836}
1837
d3175167
SG
1838IL3945_UCODE_GET(inst_size);
1839IL3945_UCODE_GET(data_size);
1840IL3945_UCODE_GET(init_size);
1841IL3945_UCODE_GET(init_data_size);
1842IL3945_UCODE_GET(boot_size);
4bc85c13
WYG
1843
1844/**
e2ebc833 1845 * il3945_read_ucode - Read uCode images from disk file.
4bc85c13
WYG
1846 *
1847 * Copy into buffers for card to fetch via bus-mastering
1848 */
46bc8d4b 1849static int il3945_read_ucode(struct il_priv *il)
4bc85c13 1850{
e2ebc833 1851 const struct il_ucode_header *ucode;
0c2c8852 1852 int ret = -EINVAL, idx;
4bc85c13
WYG
1853 const struct firmware *ucode_raw;
1854 /* firmware file name contains uCode/driver compatibility version */
46bc8d4b
SG
1855 const char *name_pre = il->cfg->fw_name_pre;
1856 const unsigned int api_max = il->cfg->ucode_api_max;
1857 const unsigned int api_min = il->cfg->ucode_api_min;
4bc85c13
WYG
1858 char buf[25];
1859 u8 *src;
1860 size_t len;
1861 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1862
1863 /* Ask kernel firmware_class module to get the boot firmware off disk.
1864 * request_firmware() is synchronous, file is in memory on return. */
0c2c8852
SG
1865 for (idx = api_max; idx >= api_min; idx--) {
1866 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
46bc8d4b 1867 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
4bc85c13 1868 if (ret < 0) {
9406f797 1869 IL_ERR("%s firmware file req failed: %d\n",
4bc85c13
WYG
1870 buf, ret);
1871 if (ret == -ENOENT)
1872 continue;
1873 else
1874 goto error;
1875 } else {
0c2c8852 1876 if (idx < api_max)
9406f797 1877 IL_ERR("Loaded firmware %s, "
4bc85c13
WYG
1878 "which is deprecated. "
1879 " Please use API v%u instead.\n",
1880 buf, api_max);
58de00a4 1881 D_INFO("Got firmware '%s' file "
4bc85c13
WYG
1882 "(%zd bytes) from disk\n",
1883 buf, ucode_raw->size);
1884 break;
1885 }
1886 }
1887
1888 if (ret < 0)
1889 goto error;
1890
1891 /* Make sure that we got at least our header! */
e2ebc833 1892 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
9406f797 1893 IL_ERR("File size way too small!\n");
4bc85c13
WYG
1894 ret = -EINVAL;
1895 goto err_release;
1896 }
1897
1898 /* Data from ucode file: header followed by uCode images */
e2ebc833 1899 ucode = (struct il_ucode_header *)ucode_raw->data;
4bc85c13 1900
46bc8d4b
SG
1901 il->ucode_ver = le32_to_cpu(ucode->ver);
1902 api_ver = IL_UCODE_API(il->ucode_ver);
e2ebc833
SG
1903 inst_size = il3945_ucode_get_inst_size(ucode);
1904 data_size = il3945_ucode_get_data_size(ucode);
1905 init_size = il3945_ucode_get_init_size(ucode);
1906 init_data_size = il3945_ucode_get_init_data_size(ucode);
1907 boot_size = il3945_ucode_get_boot_size(ucode);
1908 src = il3945_ucode_get_data(ucode);
4bc85c13
WYG
1909
1910 /* api_ver should match the api version forming part of the
1911 * firmware filename ... but we don't check for that and only rely
1912 * on the API version read from firmware header from here on forward */
1913
1914 if (api_ver < api_min || api_ver > api_max) {
9406f797 1915 IL_ERR("Driver unable to support your firmware API. "
4bc85c13
WYG
1916 "Driver supports v%u, firmware is v%u.\n",
1917 api_max, api_ver);
46bc8d4b 1918 il->ucode_ver = 0;
4bc85c13
WYG
1919 ret = -EINVAL;
1920 goto err_release;
1921 }
1922 if (api_ver != api_max)
9406f797 1923 IL_ERR("Firmware has old API version. Expected %u, "
4bc85c13
WYG
1924 "got %u. New firmware can be obtained "
1925 "from http://www.intellinuxwireless.org.\n",
1926 api_max, api_ver);
1927
9406f797 1928 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
46bc8d4b
SG
1929 IL_UCODE_MAJOR(il->ucode_ver),
1930 IL_UCODE_MINOR(il->ucode_ver),
1931 IL_UCODE_API(il->ucode_ver),
1932 IL_UCODE_SERIAL(il->ucode_ver));
4bc85c13 1933
46bc8d4b
SG
1934 snprintf(il->hw->wiphy->fw_version,
1935 sizeof(il->hw->wiphy->fw_version),
4bc85c13 1936 "%u.%u.%u.%u",
46bc8d4b
SG
1937 IL_UCODE_MAJOR(il->ucode_ver),
1938 IL_UCODE_MINOR(il->ucode_ver),
1939 IL_UCODE_API(il->ucode_ver),
1940 IL_UCODE_SERIAL(il->ucode_ver));
1941
58de00a4 1942 D_INFO("f/w package hdr ucode version raw = 0x%x\n",
46bc8d4b 1943 il->ucode_ver);
58de00a4 1944 D_INFO("f/w package hdr runtime inst size = %u\n",
4bc85c13 1945 inst_size);
58de00a4 1946 D_INFO("f/w package hdr runtime data size = %u\n",
4bc85c13 1947 data_size);
58de00a4 1948 D_INFO("f/w package hdr init inst size = %u\n",
4bc85c13 1949 init_size);
58de00a4 1950 D_INFO("f/w package hdr init data size = %u\n",
4bc85c13 1951 init_data_size);
58de00a4 1952 D_INFO("f/w package hdr boot inst size = %u\n",
4bc85c13
WYG
1953 boot_size);
1954
1955
1956 /* Verify size of file vs. image size info in file's header */
e2ebc833 1957 if (ucode_raw->size != il3945_ucode_get_header_size(api_ver) +
4bc85c13
WYG
1958 inst_size + data_size + init_size +
1959 init_data_size + boot_size) {
1960
58de00a4 1961 D_INFO(
4bc85c13
WYG
1962 "uCode file size %zd does not match expected size\n",
1963 ucode_raw->size);
1964 ret = -EINVAL;
1965 goto err_release;
1966 }
1967
1968 /* Verify that uCode images will fit in card's SRAM */
d3175167 1969 if (inst_size > IL39_MAX_INST_SIZE) {
58de00a4 1970 D_INFO("uCode instr len %d too large to fit in\n",
4bc85c13
WYG
1971 inst_size);
1972 ret = -EINVAL;
1973 goto err_release;
1974 }
1975
d3175167 1976 if (data_size > IL39_MAX_DATA_SIZE) {
58de00a4 1977 D_INFO("uCode data len %d too large to fit in\n",
4bc85c13
WYG
1978 data_size);
1979 ret = -EINVAL;
1980 goto err_release;
1981 }
d3175167 1982 if (init_size > IL39_MAX_INST_SIZE) {
58de00a4 1983 D_INFO(
4bc85c13
WYG
1984 "uCode init instr len %d too large to fit in\n",
1985 init_size);
1986 ret = -EINVAL;
1987 goto err_release;
1988 }
d3175167 1989 if (init_data_size > IL39_MAX_DATA_SIZE) {
58de00a4 1990 D_INFO(
4bc85c13
WYG
1991 "uCode init data len %d too large to fit in\n",
1992 init_data_size);
1993 ret = -EINVAL;
1994 goto err_release;
1995 }
d3175167 1996 if (boot_size > IL39_MAX_BSM_SIZE) {
58de00a4 1997 D_INFO(
4bc85c13
WYG
1998 "uCode boot instr len %d too large to fit in\n",
1999 boot_size);
2000 ret = -EINVAL;
2001 goto err_release;
2002 }
2003
2004 /* Allocate ucode buffers for card's bus-master loading ... */
2005
2006 /* Runtime instructions and 2 copies of data:
2007 * 1) unmodified from disk
2008 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG
2009 il->ucode_code.len = inst_size;
2010 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4bc85c13 2011
46bc8d4b
SG
2012 il->ucode_data.len = data_size;
2013 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4bc85c13 2014
46bc8d4b
SG
2015 il->ucode_data_backup.len = data_size;
2016 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4bc85c13 2017
46bc8d4b
SG
2018 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
2019 !il->ucode_data_backup.v_addr)
4bc85c13
WYG
2020 goto err_pci_alloc;
2021
2022 /* Initialization instructions and data */
2023 if (init_size && init_data_size) {
46bc8d4b
SG
2024 il->ucode_init.len = init_size;
2025 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4bc85c13 2026
46bc8d4b
SG
2027 il->ucode_init_data.len = init_data_size;
2028 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4bc85c13 2029
46bc8d4b 2030 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4bc85c13
WYG
2031 goto err_pci_alloc;
2032 }
2033
2034 /* Bootstrap (instructions only, no data) */
2035 if (boot_size) {
46bc8d4b
SG
2036 il->ucode_boot.len = boot_size;
2037 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13 2038
46bc8d4b 2039 if (!il->ucode_boot.v_addr)
4bc85c13
WYG
2040 goto err_pci_alloc;
2041 }
2042
2043 /* Copy images into buffers for card's bus-master reads ... */
2044
2045 /* Runtime instructions (first block of data in file) */
2046 len = inst_size;
58de00a4 2047 D_INFO(
4bc85c13 2048 "Copying (but not loading) uCode instr len %zd\n", len);
46bc8d4b 2049 memcpy(il->ucode_code.v_addr, src, len);
4bc85c13
WYG
2050 src += len;
2051
58de00a4 2052 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
46bc8d4b 2053 il->ucode_code.v_addr, (u32)il->ucode_code.p_addr);
4bc85c13
WYG
2054
2055 /* Runtime data (2nd block)
e2ebc833 2056 * NOTE: Copy into backup buffer will be done in il3945_up() */
4bc85c13 2057 len = data_size;
58de00a4 2058 D_INFO(
4bc85c13 2059 "Copying (but not loading) uCode data len %zd\n", len);
46bc8d4b
SG
2060 memcpy(il->ucode_data.v_addr, src, len);
2061 memcpy(il->ucode_data_backup.v_addr, src, len);
4bc85c13
WYG
2062 src += len;
2063
2064 /* Initialization instructions (3rd block) */
2065 if (init_size) {
2066 len = init_size;
58de00a4 2067 D_INFO(
4bc85c13 2068 "Copying (but not loading) init instr len %zd\n", len);
46bc8d4b 2069 memcpy(il->ucode_init.v_addr, src, len);
4bc85c13
WYG
2070 src += len;
2071 }
2072
2073 /* Initialization data (4th block) */
2074 if (init_data_size) {
2075 len = init_data_size;
58de00a4 2076 D_INFO(
4bc85c13 2077 "Copying (but not loading) init data len %zd\n", len);
46bc8d4b 2078 memcpy(il->ucode_init_data.v_addr, src, len);
4bc85c13
WYG
2079 src += len;
2080 }
2081
2082 /* Bootstrap instructions (5th block) */
2083 len = boot_size;
58de00a4 2084 D_INFO(
4bc85c13 2085 "Copying (but not loading) boot instr len %zd\n", len);
46bc8d4b 2086 memcpy(il->ucode_boot.v_addr, src, len);
4bc85c13
WYG
2087
2088 /* We have our copies now, allow OS release its copies */
2089 release_firmware(ucode_raw);
2090 return 0;
2091
2092 err_pci_alloc:
9406f797 2093 IL_ERR("failed to allocate pci memory\n");
4bc85c13 2094 ret = -ENOMEM;
46bc8d4b 2095 il3945_dealloc_ucode_pci(il);
4bc85c13
WYG
2096
2097 err_release:
2098 release_firmware(ucode_raw);
2099
2100 error:
2101 return ret;
2102}
2103
2104
2105/**
e2ebc833 2106 * il3945_set_ucode_ptrs - Set uCode address location
4bc85c13
WYG
2107 *
2108 * Tell initialization uCode where to find runtime uCode.
2109 *
2110 * BSM registers initially contain pointers to initialization uCode.
2111 * We need to replace them to load runtime uCode inst and data,
2112 * and to save runtime data when powering down.
2113 */
46bc8d4b 2114static int il3945_set_ucode_ptrs(struct il_priv *il)
4bc85c13
WYG
2115{
2116 dma_addr_t pinst;
2117 dma_addr_t pdata;
2118
2119 /* bits 31:0 for 3945 */
46bc8d4b
SG
2120 pinst = il->ucode_code.p_addr;
2121 pdata = il->ucode_data_backup.p_addr;
4bc85c13
WYG
2122
2123 /* Tell bootstrap uCode where to find image to load */
db54eb57
SG
2124 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2125 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2126 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
46bc8d4b 2127 il->ucode_data.len);
4bc85c13
WYG
2128
2129 /* Inst byte count must be last to set up, bit 31 signals uCode
2130 * that all new ptr/size info is in place */
db54eb57 2131 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
46bc8d4b 2132 il->ucode_code.len | BSM_DRAM_INST_LOAD);
4bc85c13 2133
58de00a4 2134 D_INFO("Runtime uCode pointers are set.\n");
4bc85c13
WYG
2135
2136 return 0;
2137}
2138
2139/**
e2ebc833 2140 * il3945_init_alive_start - Called after REPLY_ALIVE notification received
4bc85c13
WYG
2141 *
2142 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2143 *
2144 * Tell "initialize" uCode to go ahead and load the runtime uCode.
2145 */
46bc8d4b 2146static void il3945_init_alive_start(struct il_priv *il)
4bc85c13
WYG
2147{
2148 /* Check alive response for "valid" sign from uCode */
46bc8d4b 2149 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2150 /* We had an error bringing up the hardware, so take it
2151 * all the way back down so we can try again */
58de00a4 2152 D_INFO("Initialize Alive failed.\n");
4bc85c13
WYG
2153 goto restart;
2154 }
2155
2156 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2157 * This is a paranoid check, because we would not have gotten the
2158 * "initialize" alive if code weren't properly loaded. */
46bc8d4b 2159 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2160 /* Runtime instruction load was bad;
2161 * take it all the way back down so we can try again */
58de00a4 2162 D_INFO("Bad \"initialize\" uCode load.\n");
4bc85c13
WYG
2163 goto restart;
2164 }
2165
2166 /* Send pointers to protocol/runtime uCode image ... init code will
2167 * load and launch runtime uCode, which will send us another "Alive"
2168 * notification. */
58de00a4 2169 D_INFO("Initialization Alive received.\n");
46bc8d4b 2170 if (il3945_set_ucode_ptrs(il)) {
4bc85c13
WYG
2171 /* Runtime instruction load won't happen;
2172 * take it all the way back down so we can try again */
58de00a4 2173 D_INFO("Couldn't set up uCode pointers.\n");
4bc85c13
WYG
2174 goto restart;
2175 }
2176 return;
2177
2178 restart:
46bc8d4b 2179 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2180}
2181
2182/**
e2ebc833 2183 * il3945_alive_start - called after REPLY_ALIVE notification received
4bc85c13 2184 * from protocol/runtime uCode (initialization uCode's
e2ebc833 2185 * Alive gets handled by il3945_init_alive_start()).
4bc85c13 2186 */
46bc8d4b 2187static void il3945_alive_start(struct il_priv *il)
4bc85c13
WYG
2188{
2189 int thermal_spin = 0;
2190 u32 rfkill;
7c2cde2e 2191 struct il_rxon_context *ctx = &il->ctx;
4bc85c13 2192
58de00a4 2193 D_INFO("Runtime Alive received.\n");
4bc85c13 2194
46bc8d4b 2195 if (il->card_alive.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2196 /* We had an error bringing up the hardware, so take it
2197 * all the way back down so we can try again */
58de00a4 2198 D_INFO("Alive failed.\n");
4bc85c13
WYG
2199 goto restart;
2200 }
2201
2202 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2203 * This is a paranoid check, because we would not have gotten the
2204 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 2205 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2206 /* Runtime instruction load was bad;
2207 * take it all the way back down so we can try again */
58de00a4 2208 D_INFO("Bad runtime uCode load.\n");
4bc85c13
WYG
2209 goto restart;
2210 }
2211
db54eb57 2212 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
58de00a4 2213 D_INFO("RFKILL status: 0x%x\n", rfkill);
4bc85c13
WYG
2214
2215 if (rfkill & 0x1) {
46bc8d4b 2216 clear_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13
WYG
2217 /* if RFKILL is not on, then wait for thermal
2218 * sensor in adapter to kick in */
46bc8d4b 2219 while (il3945_hw_get_temperature(il) == 0) {
4bc85c13
WYG
2220 thermal_spin++;
2221 udelay(10);
2222 }
2223
2224 if (thermal_spin)
58de00a4 2225 D_INFO("Thermal calibration took %dus\n",
4bc85c13
WYG
2226 thermal_spin * 10);
2227 } else
46bc8d4b 2228 set_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13
WYG
2229
2230 /* After the ALIVE response, we can send commands to 3945 uCode */
46bc8d4b 2231 set_bit(STATUS_ALIVE, &il->status);
4bc85c13
WYG
2232
2233 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 2234 il_setup_watchdog(il);
4bc85c13 2235
46bc8d4b 2236 if (il_is_rfkill(il))
4bc85c13
WYG
2237 return;
2238
46bc8d4b 2239 ieee80211_wake_queues(il->hw);
4bc85c13 2240
2eb05816 2241 il->active_rate = RATES_MASK_3945;
4bc85c13 2242
46bc8d4b 2243 il_power_update_mode(il, true);
4bc85c13 2244
7c2cde2e 2245 if (il_is_associated(il)) {
e2ebc833
SG
2246 struct il3945_rxon_cmd *active_rxon =
2247 (struct il3945_rxon_cmd *)(&ctx->active);
4bc85c13
WYG
2248
2249 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2250 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2251 } else {
2252 /* Initialize our rx_config data */
46bc8d4b 2253 il_connection_init_rx_config(il, ctx);
4bc85c13
WYG
2254 }
2255
2256 /* Configure Bluetooth device coexistence support */
46bc8d4b 2257 il_send_bt_config(il);
4bc85c13 2258
46bc8d4b 2259 set_bit(STATUS_READY, &il->status);
4bc85c13
WYG
2260
2261 /* Configure the adapter for unassociated operation */
46bc8d4b 2262 il3945_commit_rxon(il, ctx);
4bc85c13 2263
46bc8d4b 2264 il3945_reg_txpower_periodic(il);
4bc85c13 2265
58de00a4 2266 D_INFO("ALIVE processing complete.\n");
46bc8d4b 2267 wake_up(&il->wait_command_queue);
4bc85c13
WYG
2268
2269 return;
2270
2271 restart:
46bc8d4b 2272 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2273}
2274
46bc8d4b 2275static void il3945_cancel_deferred_work(struct il_priv *il);
4bc85c13 2276
46bc8d4b 2277static void __il3945_down(struct il_priv *il)
4bc85c13
WYG
2278{
2279 unsigned long flags;
2280 int exit_pending;
2281
58de00a4 2282 D_INFO(DRV_NAME " is going down\n");
4bc85c13 2283
46bc8d4b 2284 il_scan_cancel_timeout(il, 200);
4bc85c13 2285
46bc8d4b 2286 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &il->status);
4bc85c13
WYG
2287
2288 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2289 * to prevent rearm timer */
46bc8d4b 2290 del_timer_sync(&il->watchdog);
4bc85c13
WYG
2291
2292 /* Station information will now be cleared in device */
46bc8d4b
SG
2293 il_clear_ucode_stations(il, NULL);
2294 il_dealloc_bcast_stations(il);
2295 il_clear_driver_stations(il);
4bc85c13
WYG
2296
2297 /* Unblock any waiting calls */
46bc8d4b 2298 wake_up_all(&il->wait_command_queue);
4bc85c13
WYG
2299
2300 /* Wipe out the EXIT_PENDING status bit if we are not actually
2301 * exiting the module */
2302 if (!exit_pending)
46bc8d4b 2303 clear_bit(STATUS_EXIT_PENDING, &il->status);
4bc85c13
WYG
2304
2305 /* stop and reset the on-board processor */
841b2cca 2306 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
2307
2308 /* tell the device to stop sending interrupts */
46bc8d4b
SG
2309 spin_lock_irqsave(&il->lock, flags);
2310 il_disable_interrupts(il);
2311 spin_unlock_irqrestore(&il->lock, flags);
2312 il3945_synchronize_irq(il);
4bc85c13 2313
46bc8d4b
SG
2314 if (il->mac80211_registered)
2315 ieee80211_stop_queues(il->hw);
4bc85c13 2316
e2ebc833 2317 /* If we have not previously called il3945_init() then
4bc85c13 2318 * clear all bits but the RF Kill bits and return */
46bc8d4b
SG
2319 if (!il_is_init(il)) {
2320 il->status = test_bit(STATUS_RF_KILL_HW, &il->status) <<
4bc85c13 2321 STATUS_RF_KILL_HW |
46bc8d4b 2322 test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
4bc85c13 2323 STATUS_GEO_CONFIGURED |
46bc8d4b 2324 test_bit(STATUS_EXIT_PENDING, &il->status) <<
4bc85c13
WYG
2325 STATUS_EXIT_PENDING;
2326 goto exit;
2327 }
2328
2329 /* ...otherwise clear out all the status bits but the RF Kill
2330 * bit and continue taking the NIC down. */
46bc8d4b 2331 il->status &= test_bit(STATUS_RF_KILL_HW, &il->status) <<
4bc85c13 2332 STATUS_RF_KILL_HW |
46bc8d4b 2333 test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
4bc85c13 2334 STATUS_GEO_CONFIGURED |
46bc8d4b 2335 test_bit(STATUS_FW_ERROR, &il->status) <<
4bc85c13 2336 STATUS_FW_ERROR |
46bc8d4b 2337 test_bit(STATUS_EXIT_PENDING, &il->status) <<
4bc85c13
WYG
2338 STATUS_EXIT_PENDING;
2339
46bc8d4b
SG
2340 il3945_hw_txq_ctx_stop(il);
2341 il3945_hw_rxq_stop(il);
4bc85c13
WYG
2342
2343 /* Power-down device's busmaster DMA clocks */
db54eb57 2344 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
4bc85c13
WYG
2345 udelay(5);
2346
2347 /* Stop the device, and put it in low power state */
46bc8d4b 2348 il_apm_stop(il);
4bc85c13
WYG
2349
2350 exit:
46bc8d4b 2351 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
4bc85c13 2352
46bc8d4b
SG
2353 if (il->beacon_skb)
2354 dev_kfree_skb(il->beacon_skb);
2355 il->beacon_skb = NULL;
4bc85c13
WYG
2356
2357 /* clear out any free frames */
46bc8d4b 2358 il3945_clear_free_frames(il);
4bc85c13
WYG
2359}
2360
46bc8d4b 2361static void il3945_down(struct il_priv *il)
4bc85c13 2362{
46bc8d4b
SG
2363 mutex_lock(&il->mutex);
2364 __il3945_down(il);
2365 mutex_unlock(&il->mutex);
4bc85c13 2366
46bc8d4b 2367 il3945_cancel_deferred_work(il);
4bc85c13
WYG
2368}
2369
2370#define MAX_HW_RESTARTS 5
2371
46bc8d4b 2372static int il3945_alloc_bcast_station(struct il_priv *il)
4bc85c13 2373{
7c2cde2e 2374 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
2375 unsigned long flags;
2376 u8 sta_id;
2377
46bc8d4b
SG
2378 spin_lock_irqsave(&il->sta_lock, flags);
2379 sta_id = il_prep_station(il, ctx,
d2ddf621 2380 il_bcast_addr, false, NULL);
e2ebc833 2381 if (sta_id == IL_INVALID_STATION) {
9406f797 2382 IL_ERR("Unable to prepare broadcast station\n");
46bc8d4b 2383 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2384
2385 return -EINVAL;
2386 }
2387
46bc8d4b
SG
2388 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2389 il->stations[sta_id].used |= IL_STA_BCAST;
2390 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2391
2392 return 0;
2393}
2394
46bc8d4b 2395static int __il3945_up(struct il_priv *il)
4bc85c13
WYG
2396{
2397 int rc, i;
2398
46bc8d4b 2399 rc = il3945_alloc_bcast_station(il);
4bc85c13
WYG
2400 if (rc)
2401 return rc;
2402
46bc8d4b 2403 if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
9406f797 2404 IL_WARN("Exit pending; will not bring the NIC up\n");
4bc85c13
WYG
2405 return -EIO;
2406 }
2407
46bc8d4b 2408 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 2409 IL_ERR("ucode not available for device bring up\n");
4bc85c13
WYG
2410 return -EIO;
2411 }
2412
2413 /* If platform's RF_KILL switch is NOT set to KILL */
841b2cca 2414 if (_il_rd(il, CSR_GP_CNTRL) &
4bc85c13 2415 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
46bc8d4b 2416 clear_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13 2417 else {
46bc8d4b 2418 set_bit(STATUS_RF_KILL_HW, &il->status);
9406f797 2419 IL_WARN("Radio disabled by HW RF Kill switch\n");
4bc85c13
WYG
2420 return -ENODEV;
2421 }
2422
841b2cca 2423 _il_wr(il, CSR_INT, 0xFFFFFFFF);
4bc85c13 2424
46bc8d4b 2425 rc = il3945_hw_nic_init(il);
4bc85c13 2426 if (rc) {
9406f797 2427 IL_ERR("Unable to int nic\n");
4bc85c13
WYG
2428 return rc;
2429 }
2430
2431 /* make sure rfkill handshake bits are cleared */
841b2cca
SG
2432 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2433 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4bc85c13
WYG
2434 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2435
2436 /* clear (again), then enable host interrupts */
841b2cca 2437 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 2438 il_enable_interrupts(il);
4bc85c13
WYG
2439
2440 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG
2441 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2442 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4bc85c13
WYG
2443
2444 /* Copy original ucode data image from disk into backup cache.
2445 * This will be used to initialize the on-board processor's
2446 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG
2447 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2448 il->ucode_data.len);
4bc85c13
WYG
2449
2450 /* We return success when we resume from suspend and rf_kill is on. */
46bc8d4b 2451 if (test_bit(STATUS_RF_KILL_HW, &il->status))
4bc85c13
WYG
2452 return 0;
2453
2454 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2455
2456 /* load bootstrap state machine,
2457 * load bootstrap program into processor's memory,
2458 * prepare to load the "initialize" uCode */
46bc8d4b 2459 rc = il->cfg->ops->lib->load_ucode(il);
4bc85c13
WYG
2460
2461 if (rc) {
9406f797 2462 IL_ERR(
4bc85c13
WYG
2463 "Unable to set up bootstrap uCode: %d\n", rc);
2464 continue;
2465 }
2466
2467 /* start card; "initialize" will load runtime ucode */
46bc8d4b 2468 il3945_nic_start(il);
4bc85c13 2469
58de00a4 2470 D_INFO(DRV_NAME " is coming up\n");
4bc85c13
WYG
2471
2472 return 0;
2473 }
2474
46bc8d4b
SG
2475 set_bit(STATUS_EXIT_PENDING, &il->status);
2476 __il3945_down(il);
2477 clear_bit(STATUS_EXIT_PENDING, &il->status);
4bc85c13
WYG
2478
2479 /* tried to restart and config the device for as long as our
2480 * patience could withstand */
9406f797 2481 IL_ERR("Unable to initialize device after %d attempts.\n", i);
4bc85c13
WYG
2482 return -EIO;
2483}
2484
2485
2486/*****************************************************************************
2487 *
2488 * Workqueue callbacks
2489 *
2490 *****************************************************************************/
2491
e2ebc833 2492static void il3945_bg_init_alive_start(struct work_struct *data)
4bc85c13 2493{
46bc8d4b 2494 struct il_priv *il =
e2ebc833 2495 container_of(data, struct il_priv, init_alive_start.work);
4bc85c13 2496
46bc8d4b
SG
2497 mutex_lock(&il->mutex);
2498 if (test_bit(STATUS_EXIT_PENDING, &il->status))
28a6e577 2499 goto out;
4bc85c13 2500
46bc8d4b 2501 il3945_init_alive_start(il);
28a6e577 2502out:
46bc8d4b 2503 mutex_unlock(&il->mutex);
4bc85c13
WYG
2504}
2505
e2ebc833 2506static void il3945_bg_alive_start(struct work_struct *data)
4bc85c13 2507{
46bc8d4b 2508 struct il_priv *il =
e2ebc833 2509 container_of(data, struct il_priv, alive_start.work);
4bc85c13 2510
46bc8d4b
SG
2511 mutex_lock(&il->mutex);
2512 if (test_bit(STATUS_EXIT_PENDING, &il->status))
28a6e577 2513 goto out;
4bc85c13 2514
46bc8d4b 2515 il3945_alive_start(il);
28a6e577 2516out:
46bc8d4b 2517 mutex_unlock(&il->mutex);
4bc85c13
WYG
2518}
2519
2520/*
2521 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2522 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2523 * *is* readable even when device has been SW_RESET into low power mode
2524 * (e.g. during RF KILL).
2525 */
e2ebc833 2526static void il3945_rfkill_poll(struct work_struct *data)
4bc85c13 2527{
46bc8d4b 2528 struct il_priv *il =
e2ebc833 2529 container_of(data, struct il_priv, _3945.rfkill_poll.work);
46bc8d4b 2530 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &il->status);
841b2cca 2531 bool new_rfkill = !(_il_rd(il, CSR_GP_CNTRL)
4bc85c13
WYG
2532 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2533
2534 if (new_rfkill != old_rfkill) {
2535 if (new_rfkill)
46bc8d4b 2536 set_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13 2537 else
46bc8d4b 2538 clear_bit(STATUS_RF_KILL_HW, &il->status);
4bc85c13 2539
46bc8d4b 2540 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
4bc85c13 2541
58de00a4 2542 D_RF_KILL("RF_KILL bit toggled to %s.\n",
4bc85c13
WYG
2543 new_rfkill ? "disable radio" : "enable radio");
2544 }
2545
2546 /* Keep this running, even if radio now enabled. This will be
2547 * cancelled in mac_start() if system decides to start again */
46bc8d4b 2548 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2549 round_jiffies_relative(2 * HZ));
2550
2551}
2552
46bc8d4b 2553int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
4bc85c13 2554{
e2ebc833 2555 struct il_host_cmd cmd = {
4bc85c13 2556 .id = REPLY_SCAN_CMD,
e2ebc833 2557 .len = sizeof(struct il3945_scan_cmd),
4bc85c13
WYG
2558 .flags = CMD_SIZE_HUGE,
2559 };
e2ebc833 2560 struct il3945_scan_cmd *scan;
4bc85c13
WYG
2561 u8 n_probes = 0;
2562 enum ieee80211_band band;
2563 bool is_active = false;
2564 int ret;
dd6d2a8a 2565 u16 len;
4bc85c13 2566
46bc8d4b 2567 lockdep_assert_held(&il->mutex);
4bc85c13 2568
46bc8d4b
SG
2569 if (!il->scan_cmd) {
2570 il->scan_cmd = kmalloc(sizeof(struct il3945_scan_cmd) +
e2ebc833 2571 IL_MAX_SCAN_SIZE, GFP_KERNEL);
46bc8d4b 2572 if (!il->scan_cmd) {
58de00a4 2573 D_SCAN("Fail to allocate scan memory\n");
4bc85c13
WYG
2574 return -ENOMEM;
2575 }
2576 }
46bc8d4b 2577 scan = il->scan_cmd;
e2ebc833 2578 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
4bc85c13 2579
e2ebc833
SG
2580 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2581 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
4bc85c13 2582
7c2cde2e 2583 if (il_is_associated(il)) {
dd6d2a8a 2584 u16 interval;
4bc85c13
WYG
2585 u32 extra;
2586 u32 suspend_time = 100;
2587 u32 scan_suspend_time = 100;
2588
58de00a4 2589 D_INFO("Scanning while associated...\n");
4bc85c13 2590
dd6d2a8a 2591 interval = vif->bss_conf.beacon_int;
4bc85c13
WYG
2592
2593 scan->suspend_time = 0;
2594 scan->max_out_time = cpu_to_le32(200 * 1024);
2595 if (!interval)
2596 interval = suspend_time;
2597 /*
2598 * suspend time format:
2599 * 0-19: beacon interval in usec (time before exec.)
2600 * 20-23: 0
2601 * 24-31: number of beacons (suspend between channels)
2602 */
2603
2604 extra = (suspend_time / interval) << 24;
2605 scan_suspend_time = 0xFF0FFFFF &
2606 (extra | ((suspend_time % interval) * 1024));
2607
2608 scan->suspend_time = cpu_to_le32(scan_suspend_time);
58de00a4 2609 D_SCAN("suspend_time 0x%X beacon interval %d\n",
4bc85c13
WYG
2610 scan_suspend_time, interval);
2611 }
2612
46bc8d4b 2613 if (il->scan_request->n_ssids) {
4bc85c13 2614 int i, p = 0;
58de00a4 2615 D_SCAN("Kicking off active scan\n");
46bc8d4b 2616 for (i = 0; i < il->scan_request->n_ssids; i++) {
4bc85c13 2617 /* always does wildcard anyway */
46bc8d4b 2618 if (!il->scan_request->ssids[i].ssid_len)
4bc85c13
WYG
2619 continue;
2620 scan->direct_scan[p].id = WLAN_EID_SSID;
2621 scan->direct_scan[p].len =
46bc8d4b 2622 il->scan_request->ssids[i].ssid_len;
4bc85c13 2623 memcpy(scan->direct_scan[p].ssid,
46bc8d4b
SG
2624 il->scan_request->ssids[i].ssid,
2625 il->scan_request->ssids[i].ssid_len);
4bc85c13
WYG
2626 n_probes++;
2627 p++;
2628 }
2629 is_active = true;
2630 } else
58de00a4 2631 D_SCAN("Kicking off passive scan.\n");
4bc85c13
WYG
2632
2633 /* We don't build a direct scan probe request; the uCode will do
2634 * that based on the direct_mask added to each channel entry */
2635 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
7c2cde2e 2636 scan->tx_cmd.sta_id = il->ctx.bcast_sta_id;
4bc85c13
WYG
2637 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2638
2639 /* flags + rate selection */
2640
46bc8d4b 2641 switch (il->scan_band) {
4bc85c13
WYG
2642 case IEEE80211_BAND_2GHZ:
2643 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2eb05816 2644 scan->tx_cmd.rate = RATE_1M_PLCP;
4bc85c13
WYG
2645 band = IEEE80211_BAND_2GHZ;
2646 break;
2647 case IEEE80211_BAND_5GHZ:
2eb05816 2648 scan->tx_cmd.rate = RATE_6M_PLCP;
4bc85c13
WYG
2649 band = IEEE80211_BAND_5GHZ;
2650 break;
2651 default:
9406f797 2652 IL_WARN("Invalid scan band\n");
4bc85c13
WYG
2653 return -EIO;
2654 }
2655
2656 /*
2657 * If active scaning is requested but a certain channel
2658 * is marked passive, we can do active scanning if we
2659 * detect transmissions.
2660 */
e2ebc833
SG
2661 scan->good_CRC_th = is_active ? IL_GOOD_CRC_TH_DEFAULT :
2662 IL_GOOD_CRC_TH_DISABLED;
4bc85c13 2663
46bc8d4b
SG
2664 len = il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2665 vif->addr, il->scan_request->ie,
2666 il->scan_request->ie_len,
e2ebc833 2667 IL_MAX_SCAN_SIZE - sizeof(*scan));
dd6d2a8a
SG
2668 scan->tx_cmd.len = cpu_to_le16(len);
2669
4bc85c13 2670 /* select Rx antennas */
46bc8d4b 2671 scan->flags |= il3945_get_antenna_flags(il);
4bc85c13 2672
46bc8d4b 2673 scan->channel_count = il3945_get_channels_for_scan(il, band, is_active, n_probes,
dd6d2a8a 2674 (void *)&scan->data[len], vif);
4bc85c13 2675 if (scan->channel_count == 0) {
58de00a4 2676 D_SCAN("channel count %d\n", scan->channel_count);
4bc85c13
WYG
2677 return -EIO;
2678 }
2679
2680 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
e2ebc833 2681 scan->channel_count * sizeof(struct il3945_scan_channel);
4bc85c13
WYG
2682 cmd.data = scan;
2683 scan->len = cpu_to_le16(cmd.len);
2684
46bc8d4b
SG
2685 set_bit(STATUS_SCAN_HW, &il->status);
2686 ret = il_send_cmd_sync(il, &cmd);
4bc85c13 2687 if (ret)
46bc8d4b 2688 clear_bit(STATUS_SCAN_HW, &il->status);
4bc85c13
WYG
2689 return ret;
2690}
2691
46bc8d4b 2692void il3945_post_scan(struct il_priv *il)
4bc85c13 2693{
7c2cde2e 2694 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
2695
2696 /*
2697 * Since setting the RXON may have been deferred while
2698 * performing the scan, fire one off if needed
2699 */
2700 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
46bc8d4b 2701 il3945_commit_rxon(il, ctx);
4bc85c13
WYG
2702}
2703
e2ebc833 2704static void il3945_bg_restart(struct work_struct *data)
4bc85c13 2705{
46bc8d4b 2706 struct il_priv *il = container_of(data, struct il_priv, restart);
4bc85c13 2707
46bc8d4b 2708 if (test_bit(STATUS_EXIT_PENDING, &il->status))
4bc85c13
WYG
2709 return;
2710
46bc8d4b 2711 if (test_and_clear_bit(STATUS_FW_ERROR, &il->status)) {
46bc8d4b 2712 mutex_lock(&il->mutex);
17d6e557 2713 il->ctx.vif = NULL;
46bc8d4b
SG
2714 il->is_open = 0;
2715 mutex_unlock(&il->mutex);
2716 il3945_down(il);
2717 ieee80211_restart_hw(il->hw);
4bc85c13 2718 } else {
46bc8d4b 2719 il3945_down(il);
4bc85c13 2720
46bc8d4b
SG
2721 mutex_lock(&il->mutex);
2722 if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
2723 mutex_unlock(&il->mutex);
4bc85c13 2724 return;
28a6e577 2725 }
4bc85c13 2726
46bc8d4b
SG
2727 __il3945_up(il);
2728 mutex_unlock(&il->mutex);
4bc85c13
WYG
2729 }
2730}
2731
e2ebc833 2732static void il3945_bg_rx_replenish(struct work_struct *data)
4bc85c13 2733{
46bc8d4b 2734 struct il_priv *il =
e2ebc833 2735 container_of(data, struct il_priv, rx_replenish);
4bc85c13 2736
46bc8d4b
SG
2737 mutex_lock(&il->mutex);
2738 if (test_bit(STATUS_EXIT_PENDING, &il->status))
28a6e577 2739 goto out;
4bc85c13 2740
46bc8d4b 2741 il3945_rx_replenish(il);
28a6e577 2742out:
46bc8d4b 2743 mutex_unlock(&il->mutex);
4bc85c13
WYG
2744}
2745
46bc8d4b 2746void il3945_post_associate(struct il_priv *il)
4bc85c13
WYG
2747{
2748 int rc = 0;
2749 struct ieee80211_conf *conf = NULL;
7c2cde2e 2750 struct il_rxon_context *ctx = &il->ctx;
4bc85c13 2751
46bc8d4b 2752 if (!ctx->vif || !il->is_open)
4bc85c13
WYG
2753 return;
2754
58de00a4 2755 D_ASSOC("Associated as %d to: %pM\n",
4bc85c13
WYG
2756 ctx->vif->bss_conf.aid, ctx->active.bssid_addr);
2757
46bc8d4b 2758 if (test_bit(STATUS_EXIT_PENDING, &il->status))
4bc85c13
WYG
2759 return;
2760
46bc8d4b 2761 il_scan_cancel_timeout(il, 200);
4bc85c13 2762
46bc8d4b 2763 conf = il_ieee80211_get_hw_conf(il->hw);
4bc85c13
WYG
2764
2765 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
46bc8d4b 2766 il3945_commit_rxon(il, ctx);
4bc85c13 2767
46bc8d4b 2768 rc = il_send_rxon_timing(il, ctx);
4bc85c13 2769 if (rc)
9406f797 2770 IL_WARN("REPLY_RXON_TIMING failed - "
4bc85c13
WYG
2771 "Attempting to continue.\n");
2772
2773 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2774
2775 ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid);
2776
58de00a4 2777 D_ASSOC("assoc id %d beacon interval %d\n",
4bc85c13
WYG
2778 ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int);
2779
2780 if (ctx->vif->bss_conf.use_short_preamble)
2781 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2782 else
2783 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2784
2785 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
2786 if (ctx->vif->bss_conf.use_short_slot)
2787 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2788 else
2789 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2790 }
2791
46bc8d4b 2792 il3945_commit_rxon(il, ctx);
4bc85c13
WYG
2793
2794 switch (ctx->vif->type) {
2795 case NL80211_IFTYPE_STATION:
46bc8d4b 2796 il3945_rate_scale_init(il->hw, IL_AP_ID);
4bc85c13
WYG
2797 break;
2798 case NL80211_IFTYPE_ADHOC:
46bc8d4b 2799 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2800 break;
2801 default:
9406f797 2802 IL_ERR("%s Should not be called in %d mode\n",
4bc85c13
WYG
2803 __func__, ctx->vif->type);
2804 break;
2805 }
2806}
2807
2808/*****************************************************************************
2809 *
2810 * mac80211 entry point functions
2811 *
2812 *****************************************************************************/
2813
2814#define UCODE_READY_TIMEOUT (2 * HZ)
2815
e2ebc833 2816static int il3945_mac_start(struct ieee80211_hw *hw)
4bc85c13 2817{
46bc8d4b 2818 struct il_priv *il = hw->priv;
4bc85c13
WYG
2819 int ret;
2820
58de00a4 2821 D_MAC80211("enter\n");
4bc85c13
WYG
2822
2823 /* we should be verifying the device is ready to be opened */
46bc8d4b 2824 mutex_lock(&il->mutex);
4bc85c13
WYG
2825
2826 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2827 * ucode filename and max sizes are card-specific. */
2828
46bc8d4b
SG
2829 if (!il->ucode_code.len) {
2830 ret = il3945_read_ucode(il);
4bc85c13 2831 if (ret) {
9406f797 2832 IL_ERR("Could not read microcode: %d\n", ret);
46bc8d4b 2833 mutex_unlock(&il->mutex);
4bc85c13
WYG
2834 goto out_release_irq;
2835 }
2836 }
2837
46bc8d4b 2838 ret = __il3945_up(il);
4bc85c13 2839
46bc8d4b 2840 mutex_unlock(&il->mutex);
4bc85c13
WYG
2841
2842 if (ret)
2843 goto out_release_irq;
2844
58de00a4 2845 D_INFO("Start UP work.\n");
4bc85c13
WYG
2846
2847 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
2848 * mac80211 will not be run successfully. */
46bc8d4b
SG
2849 ret = wait_event_timeout(il->wait_command_queue,
2850 test_bit(STATUS_READY, &il->status),
4bc85c13
WYG
2851 UCODE_READY_TIMEOUT);
2852 if (!ret) {
46bc8d4b 2853 if (!test_bit(STATUS_READY, &il->status)) {
9406f797 2854 IL_ERR(
4bc85c13
WYG
2855 "Wait for START_ALIVE timeout after %dms.\n",
2856 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2857 ret = -ETIMEDOUT;
2858 goto out_release_irq;
2859 }
2860 }
2861
2862 /* ucode is running and will send rfkill notifications,
2863 * no need to poll the killswitch state anymore */
46bc8d4b 2864 cancel_delayed_work(&il->_3945.rfkill_poll);
4bc85c13 2865
46bc8d4b 2866 il->is_open = 1;
58de00a4 2867 D_MAC80211("leave\n");
4bc85c13
WYG
2868 return 0;
2869
2870out_release_irq:
46bc8d4b 2871 il->is_open = 0;
58de00a4 2872 D_MAC80211("leave - failed\n");
4bc85c13
WYG
2873 return ret;
2874}
2875
e2ebc833 2876static void il3945_mac_stop(struct ieee80211_hw *hw)
4bc85c13 2877{
46bc8d4b 2878 struct il_priv *il = hw->priv;
4bc85c13 2879
58de00a4 2880 D_MAC80211("enter\n");
4bc85c13 2881
46bc8d4b 2882 if (!il->is_open) {
58de00a4 2883 D_MAC80211("leave - skip\n");
4bc85c13
WYG
2884 return;
2885 }
2886
46bc8d4b 2887 il->is_open = 0;
4bc85c13 2888
46bc8d4b 2889 il3945_down(il);
4bc85c13 2890
46bc8d4b 2891 flush_workqueue(il->workqueue);
4bc85c13
WYG
2892
2893 /* start polling the killswitch state again */
46bc8d4b 2894 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2895 round_jiffies_relative(2 * HZ));
2896
58de00a4 2897 D_MAC80211("leave\n");
4bc85c13
WYG
2898}
2899
e2ebc833 2900static void il3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
4bc85c13 2901{
46bc8d4b 2902 struct il_priv *il = hw->priv;
4bc85c13 2903
58de00a4 2904 D_MAC80211("enter\n");
4bc85c13 2905
58de00a4 2906 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
4bc85c13
WYG
2907 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2908
46bc8d4b 2909 if (il3945_tx_skb(il, skb))
4bc85c13
WYG
2910 dev_kfree_skb_any(skb);
2911
58de00a4 2912 D_MAC80211("leave\n");
4bc85c13
WYG
2913}
2914
46bc8d4b 2915void il3945_config_ap(struct il_priv *il)
4bc85c13 2916{
7c2cde2e 2917 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
2918 struct ieee80211_vif *vif = ctx->vif;
2919 int rc = 0;
2920
46bc8d4b 2921 if (test_bit(STATUS_EXIT_PENDING, &il->status))
4bc85c13
WYG
2922 return;
2923
2924 /* The following should be done only at AP bring up */
7c2cde2e 2925 if (!(il_is_associated(il))) {
4bc85c13
WYG
2926
2927 /* RXON - unassoc (to set timing command) */
2928 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
46bc8d4b 2929 il3945_commit_rxon(il, ctx);
4bc85c13
WYG
2930
2931 /* RXON Timing */
46bc8d4b 2932 rc = il_send_rxon_timing(il, ctx);
4bc85c13 2933 if (rc)
9406f797 2934 IL_WARN("REPLY_RXON_TIMING failed - "
4bc85c13
WYG
2935 "Attempting to continue.\n");
2936
2937 ctx->staging.assoc_id = 0;
2938
2939 if (vif->bss_conf.use_short_preamble)
2940 ctx->staging.flags |=
2941 RXON_FLG_SHORT_PREAMBLE_MSK;
2942 else
2943 ctx->staging.flags &=
2944 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2945
2946 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
2947 if (vif->bss_conf.use_short_slot)
2948 ctx->staging.flags |=
2949 RXON_FLG_SHORT_SLOT_MSK;
2950 else
2951 ctx->staging.flags &=
2952 ~RXON_FLG_SHORT_SLOT_MSK;
2953 }
2954 /* restore RXON assoc */
2955 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
46bc8d4b 2956 il3945_commit_rxon(il, ctx);
4bc85c13 2957 }
46bc8d4b 2958 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2959}
2960
e2ebc833 2961static int il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4bc85c13
WYG
2962 struct ieee80211_vif *vif,
2963 struct ieee80211_sta *sta,
2964 struct ieee80211_key_conf *key)
2965{
46bc8d4b 2966 struct il_priv *il = hw->priv;
4bc85c13 2967 int ret = 0;
e2ebc833 2968 u8 sta_id = IL_INVALID_STATION;
4bc85c13
WYG
2969 u8 static_key;
2970
58de00a4 2971 D_MAC80211("enter\n");
4bc85c13 2972
e2ebc833 2973 if (il3945_mod_params.sw_crypto) {
58de00a4 2974 D_MAC80211("leave - hwcrypto disabled\n");
4bc85c13
WYG
2975 return -EOPNOTSUPP;
2976 }
2977
2978 /*
2979 * To support IBSS RSN, don't program group keys in IBSS, the
2980 * hardware will then not attempt to decrypt the frames.
2981 */
2982 if (vif->type == NL80211_IFTYPE_ADHOC &&
2983 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2984 return -EOPNOTSUPP;
2985
7c2cde2e 2986 static_key = !il_is_associated(il);
4bc85c13
WYG
2987
2988 if (!static_key) {
e2ebc833 2989 sta_id = il_sta_id_or_broadcast(
7c2cde2e 2990 il, &il->ctx, sta);
e2ebc833 2991 if (sta_id == IL_INVALID_STATION)
4bc85c13
WYG
2992 return -EINVAL;
2993 }
2994
46bc8d4b
SG
2995 mutex_lock(&il->mutex);
2996 il_scan_cancel_timeout(il, 100);
4bc85c13
WYG
2997
2998 switch (cmd) {
2999 case SET_KEY:
3000 if (static_key)
46bc8d4b 3001 ret = il3945_set_static_key(il, key);
4bc85c13 3002 else
46bc8d4b 3003 ret = il3945_set_dynamic_key(il, key, sta_id);
58de00a4 3004 D_MAC80211("enable hwcrypto key\n");
4bc85c13
WYG
3005 break;
3006 case DISABLE_KEY:
3007 if (static_key)
46bc8d4b 3008 ret = il3945_remove_static_key(il);
4bc85c13 3009 else
46bc8d4b 3010 ret = il3945_clear_sta_key_info(il, sta_id);
58de00a4 3011 D_MAC80211("disable hwcrypto key\n");
4bc85c13
WYG
3012 break;
3013 default:
3014 ret = -EINVAL;
3015 }
3016
46bc8d4b 3017 mutex_unlock(&il->mutex);
58de00a4 3018 D_MAC80211("leave\n");
4bc85c13
WYG
3019
3020 return ret;
3021}
3022
e2ebc833 3023static int il3945_mac_sta_add(struct ieee80211_hw *hw,
4bc85c13
WYG
3024 struct ieee80211_vif *vif,
3025 struct ieee80211_sta *sta)
3026{
46bc8d4b 3027 struct il_priv *il = hw->priv;
e2ebc833 3028 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
4bc85c13
WYG
3029 int ret;
3030 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3031 u8 sta_id;
3032
58de00a4 3033 D_INFO("received request to add station %pM\n",
4bc85c13 3034 sta->addr);
46bc8d4b 3035 mutex_lock(&il->mutex);
58de00a4 3036 D_INFO("proceeding to add station %pM\n",
4bc85c13 3037 sta->addr);
e2ebc833 3038 sta_priv->common.sta_id = IL_INVALID_STATION;
4bc85c13
WYG
3039
3040
46bc8d4b 3041 ret = il_add_station_common(il,
7c2cde2e 3042 &il->ctx,
4bc85c13
WYG
3043 sta->addr, is_ap, sta, &sta_id);
3044 if (ret) {
9406f797 3045 IL_ERR("Unable to add station %pM (%d)\n",
4bc85c13
WYG
3046 sta->addr, ret);
3047 /* Should we return success if return code is EEXIST ? */
46bc8d4b 3048 mutex_unlock(&il->mutex);
4bc85c13
WYG
3049 return ret;
3050 }
3051
3052 sta_priv->common.sta_id = sta_id;
3053
3054 /* Initialize rate scaling */
58de00a4 3055 D_INFO("Initializing rate scaling for station %pM\n",
4bc85c13 3056 sta->addr);
46bc8d4b
SG
3057 il3945_rs_rate_init(il, sta, sta_id);
3058 mutex_unlock(&il->mutex);
4bc85c13
WYG
3059
3060 return 0;
3061}
3062
e2ebc833 3063static void il3945_configure_filter(struct ieee80211_hw *hw,
4bc85c13
WYG
3064 unsigned int changed_flags,
3065 unsigned int *total_flags,
3066 u64 multicast)
3067{
46bc8d4b 3068 struct il_priv *il = hw->priv;
4bc85c13 3069 __le32 filter_or = 0, filter_nand = 0;
7c2cde2e 3070 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
3071
3072#define CHK(test, flag) do { \
3073 if (*total_flags & (test)) \
3074 filter_or |= (flag); \
3075 else \
3076 filter_nand |= (flag); \
3077 } while (0)
3078
58de00a4 3079 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
4bc85c13
WYG
3080 changed_flags, *total_flags);
3081
3082 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3083 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3084 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3085
3086#undef CHK
3087
46bc8d4b 3088 mutex_lock(&il->mutex);
4bc85c13
WYG
3089
3090 ctx->staging.filter_flags &= ~filter_nand;
3091 ctx->staging.filter_flags |= filter_or;
3092
3093 /*
3094 * Not committing directly because hardware can perform a scan,
3095 * but even if hw is ready, committing here breaks for some reason,
3096 * we'll eventually commit the filter flags change anyway.
3097 */
3098
46bc8d4b 3099 mutex_unlock(&il->mutex);
4bc85c13
WYG
3100
3101 /*
3102 * Receiving all multicast frames is always enabled by the
e2ebc833 3103 * default flags setup in il_connection_init_rx_config()
4bc85c13
WYG
3104 * since we currently do not support programming multicast
3105 * filters into the device.
3106 */
3107 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3108 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3109}
3110
3111
3112/*****************************************************************************
3113 *
3114 * sysfs attributes
3115 *
3116 *****************************************************************************/
3117
d3175167 3118#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3119
3120/*
3121 * The following adds a new attribute to the sysfs representation
3122 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3123 * used for controlling the debug level.
3124 *
3125 * See the level definitions in iwl for details.
3126 *
3127 * The debug_level being managed using sysfs below is a per device debug
3128 * level that is used instead of the global debug level if it (the per
3129 * device debug level) is set.
3130 */
e2ebc833 3131static ssize_t il3945_show_debug_level(struct device *d,
4bc85c13
WYG
3132 struct device_attribute *attr, char *buf)
3133{
46bc8d4b
SG
3134 struct il_priv *il = dev_get_drvdata(d);
3135 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4bc85c13 3136}
e2ebc833 3137static ssize_t il3945_store_debug_level(struct device *d,
4bc85c13
WYG
3138 struct device_attribute *attr,
3139 const char *buf, size_t count)
3140{
46bc8d4b 3141 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3142 unsigned long val;
3143 int ret;
3144
3145 ret = strict_strtoul(buf, 0, &val);
3146 if (ret)
9406f797 3147 IL_INFO("%s is not in hex or decimal form.\n", buf);
4bc85c13 3148 else {
46bc8d4b
SG
3149 il->debug_level = val;
3150 if (il_alloc_traffic_mem(il))
9406f797 3151 IL_ERR(
4bc85c13
WYG
3152 "Not enough memory to generate traffic log\n");
3153 }
3154 return strnlen(buf, count);
3155}
3156
3157static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
e2ebc833 3158 il3945_show_debug_level, il3945_store_debug_level);
4bc85c13 3159
d3175167 3160#endif /* CONFIG_IWLEGACY_DEBUG */
4bc85c13 3161
e2ebc833 3162static ssize_t il3945_show_temperature(struct device *d,
4bc85c13
WYG
3163 struct device_attribute *attr, char *buf)
3164{
46bc8d4b 3165 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3166
46bc8d4b 3167 if (!il_is_alive(il))
4bc85c13
WYG
3168 return -EAGAIN;
3169
46bc8d4b 3170 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
4bc85c13
WYG
3171}
3172
e2ebc833 3173static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL);
4bc85c13 3174
e2ebc833 3175static ssize_t il3945_show_tx_power(struct device *d,
4bc85c13
WYG
3176 struct device_attribute *attr, char *buf)
3177{
46bc8d4b
SG
3178 struct il_priv *il = dev_get_drvdata(d);
3179 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4bc85c13
WYG
3180}
3181
e2ebc833 3182static ssize_t il3945_store_tx_power(struct device *d,
4bc85c13
WYG
3183 struct device_attribute *attr,
3184 const char *buf, size_t count)
3185{
46bc8d4b 3186 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3187 char *p = (char *)buf;
3188 u32 val;
3189
3190 val = simple_strtoul(p, &p, 10);
3191 if (p == buf)
9406f797 3192 IL_INFO(": %s is not in decimal form.\n", buf);
4bc85c13 3193 else
46bc8d4b 3194 il3945_hw_reg_set_txpower(il, val);
4bc85c13
WYG
3195
3196 return count;
3197}
3198
e2ebc833 3199static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power, il3945_store_tx_power);
4bc85c13 3200
e2ebc833 3201static ssize_t il3945_show_flags(struct device *d,
4bc85c13
WYG
3202 struct device_attribute *attr, char *buf)
3203{
46bc8d4b 3204 struct il_priv *il = dev_get_drvdata(d);
7c2cde2e 3205 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
3206
3207 return sprintf(buf, "0x%04X\n", ctx->active.flags);
3208}
3209
e2ebc833 3210static ssize_t il3945_store_flags(struct device *d,
4bc85c13
WYG
3211 struct device_attribute *attr,
3212 const char *buf, size_t count)
3213{
46bc8d4b 3214 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3215 u32 flags = simple_strtoul(buf, NULL, 0);
7c2cde2e 3216 struct il_rxon_context *ctx = &il->ctx;
4bc85c13 3217
46bc8d4b 3218 mutex_lock(&il->mutex);
4bc85c13
WYG
3219 if (le32_to_cpu(ctx->staging.flags) != flags) {
3220 /* Cancel any currently running scans... */
46bc8d4b 3221 if (il_scan_cancel_timeout(il, 100))
9406f797 3222 IL_WARN("Could not cancel scan.\n");
4bc85c13 3223 else {
58de00a4 3224 D_INFO("Committing rxon.flags = 0x%04X\n",
4bc85c13
WYG
3225 flags);
3226 ctx->staging.flags = cpu_to_le32(flags);
46bc8d4b 3227 il3945_commit_rxon(il, ctx);
4bc85c13
WYG
3228 }
3229 }
46bc8d4b 3230 mutex_unlock(&il->mutex);
4bc85c13
WYG
3231
3232 return count;
3233}
3234
e2ebc833 3235static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags, il3945_store_flags);
4bc85c13 3236
e2ebc833 3237static ssize_t il3945_show_filter_flags(struct device *d,
4bc85c13
WYG
3238 struct device_attribute *attr, char *buf)
3239{
46bc8d4b 3240 struct il_priv *il = dev_get_drvdata(d);
7c2cde2e 3241 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
3242
3243 return sprintf(buf, "0x%04X\n",
3244 le32_to_cpu(ctx->active.filter_flags));
3245}
3246
e2ebc833 3247static ssize_t il3945_store_filter_flags(struct device *d,
4bc85c13
WYG
3248 struct device_attribute *attr,
3249 const char *buf, size_t count)
3250{
46bc8d4b 3251 struct il_priv *il = dev_get_drvdata(d);
7c2cde2e 3252 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
3253 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3254
46bc8d4b 3255 mutex_lock(&il->mutex);
4bc85c13
WYG
3256 if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
3257 /* Cancel any currently running scans... */
46bc8d4b 3258 if (il_scan_cancel_timeout(il, 100))
9406f797 3259 IL_WARN("Could not cancel scan.\n");
4bc85c13 3260 else {
58de00a4 3261 D_INFO("Committing rxon.filter_flags = "
4bc85c13
WYG
3262 "0x%04X\n", filter_flags);
3263 ctx->staging.filter_flags =
3264 cpu_to_le32(filter_flags);
46bc8d4b 3265 il3945_commit_rxon(il, ctx);
4bc85c13
WYG
3266 }
3267 }
46bc8d4b 3268 mutex_unlock(&il->mutex);
4bc85c13
WYG
3269
3270 return count;
3271}
3272
e2ebc833
SG
3273static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags,
3274 il3945_store_filter_flags);
4bc85c13 3275
e2ebc833 3276static ssize_t il3945_show_measurement(struct device *d,
4bc85c13
WYG
3277 struct device_attribute *attr, char *buf)
3278{
46bc8d4b 3279 struct il_priv *il = dev_get_drvdata(d);
e2ebc833 3280 struct il_spectrum_notification measure_report;
4bc85c13
WYG
3281 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3282 u8 *data = (u8 *)&measure_report;
3283 unsigned long flags;
3284
46bc8d4b
SG
3285 spin_lock_irqsave(&il->lock, flags);
3286 if (!(il->measurement_status & MEASUREMENT_READY)) {
3287 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
3288 return 0;
3289 }
46bc8d4b
SG
3290 memcpy(&measure_report, &il->measure_report, size);
3291 il->measurement_status = 0;
3292 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3293
232913b5 3294 while (size && PAGE_SIZE - len) {
4bc85c13
WYG
3295 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3296 PAGE_SIZE - len, 1);
3297 len = strlen(buf);
3298 if (PAGE_SIZE - len)
3299 buf[len++] = '\n';
3300
3301 ofs += 16;
3302 size -= min(size, 16U);
3303 }
3304
3305 return len;
3306}
3307
e2ebc833 3308static ssize_t il3945_store_measurement(struct device *d,
4bc85c13
WYG
3309 struct device_attribute *attr,
3310 const char *buf, size_t count)
3311{
46bc8d4b 3312 struct il_priv *il = dev_get_drvdata(d);
7c2cde2e 3313 struct il_rxon_context *ctx = &il->ctx;
4bc85c13
WYG
3314 struct ieee80211_measurement_params params = {
3315 .channel = le16_to_cpu(ctx->active.channel),
46bc8d4b 3316 .start_time = cpu_to_le64(il->_3945.last_tsf),
4bc85c13
WYG
3317 .duration = cpu_to_le16(1),
3318 };
e2ebc833 3319 u8 type = IL_MEASURE_BASIC;
4bc85c13
WYG
3320 u8 buffer[32];
3321 u8 channel;
3322
3323 if (count) {
3324 char *p = buffer;
3325 strncpy(buffer, buf, min(sizeof(buffer), count));
3326 channel = simple_strtoul(p, NULL, 0);
3327 if (channel)
3328 params.channel = channel;
3329
3330 p = buffer;
3331 while (*p && *p != ' ')
3332 p++;
3333 if (*p)
3334 type = simple_strtoul(p + 1, NULL, 0);
3335 }
3336
58de00a4 3337 D_INFO("Invoking measurement of type %d on "
4bc85c13 3338 "channel %d (for '%s')\n", type, params.channel, buf);
46bc8d4b 3339 il3945_get_measurement(il, &params, type);
4bc85c13
WYG
3340
3341 return count;
3342}
3343
3344static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
e2ebc833 3345 il3945_show_measurement, il3945_store_measurement);
4bc85c13 3346
e2ebc833 3347static ssize_t il3945_store_retry_rate(struct device *d,
4bc85c13
WYG
3348 struct device_attribute *attr,
3349 const char *buf, size_t count)
3350{
46bc8d4b 3351 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3352
46bc8d4b
SG
3353 il->retry_rate = simple_strtoul(buf, NULL, 0);
3354 if (il->retry_rate <= 0)
3355 il->retry_rate = 1;
4bc85c13
WYG
3356
3357 return count;
3358}
3359
e2ebc833 3360static ssize_t il3945_show_retry_rate(struct device *d,
4bc85c13
WYG
3361 struct device_attribute *attr, char *buf)
3362{
46bc8d4b
SG
3363 struct il_priv *il = dev_get_drvdata(d);
3364 return sprintf(buf, "%d", il->retry_rate);
4bc85c13
WYG
3365}
3366
e2ebc833
SG
3367static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate,
3368 il3945_store_retry_rate);
4bc85c13
WYG
3369
3370
e2ebc833 3371static ssize_t il3945_show_channels(struct device *d,
4bc85c13
WYG
3372 struct device_attribute *attr, char *buf)
3373{
3374 /* all this shit doesn't belong into sysfs anyway */
3375 return 0;
3376}
3377
e2ebc833 3378static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL);
4bc85c13 3379
e2ebc833 3380static ssize_t il3945_show_antenna(struct device *d,
4bc85c13
WYG
3381 struct device_attribute *attr, char *buf)
3382{
46bc8d4b 3383 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3384
46bc8d4b 3385 if (!il_is_alive(il))
4bc85c13
WYG
3386 return -EAGAIN;
3387
e2ebc833 3388 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
4bc85c13
WYG
3389}
3390
e2ebc833 3391static ssize_t il3945_store_antenna(struct device *d,
4bc85c13
WYG
3392 struct device_attribute *attr,
3393 const char *buf, size_t count)
3394{
46bc8d4b 3395 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
4bc85c13
WYG
3396 int ant;
3397
3398 if (count == 0)
3399 return 0;
3400
3401 if (sscanf(buf, "%1i", &ant) != 1) {
58de00a4 3402 D_INFO("not in hex or decimal form.\n");
4bc85c13
WYG
3403 return count;
3404 }
3405
232913b5 3406 if (ant >= 0 && ant <= 2) {
58de00a4 3407 D_INFO("Setting antenna select to %d.\n", ant);
e2ebc833 3408 il3945_mod_params.antenna = (enum il3945_antenna)ant;
4bc85c13 3409 } else
58de00a4 3410 D_INFO("Bad antenna select value %d.\n", ant);
4bc85c13
WYG
3411
3412
3413 return count;
3414}
3415
e2ebc833 3416static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna, il3945_store_antenna);
4bc85c13 3417
e2ebc833 3418static ssize_t il3945_show_status(struct device *d,
4bc85c13
WYG
3419 struct device_attribute *attr, char *buf)
3420{
46bc8d4b
SG
3421 struct il_priv *il = dev_get_drvdata(d);
3422 if (!il_is_alive(il))
4bc85c13 3423 return -EAGAIN;
46bc8d4b 3424 return sprintf(buf, "0x%08x\n", (int)il->status);
4bc85c13
WYG
3425}
3426
e2ebc833 3427static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL);
4bc85c13 3428
e2ebc833 3429static ssize_t il3945_dump_error_log(struct device *d,
4bc85c13
WYG
3430 struct device_attribute *attr,
3431 const char *buf, size_t count)
3432{
46bc8d4b 3433 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3434 char *p = (char *)buf;
3435
3436 if (p[0] == '1')
46bc8d4b 3437 il3945_dump_nic_error_log(il);
4bc85c13
WYG
3438
3439 return strnlen(buf, count);
3440}
3441
e2ebc833 3442static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log);
4bc85c13
WYG
3443
3444/*****************************************************************************
3445 *
3446 * driver setup and tear down
3447 *
3448 *****************************************************************************/
3449
46bc8d4b 3450static void il3945_setup_deferred_work(struct il_priv *il)
4bc85c13 3451{
46bc8d4b 3452 il->workqueue = create_singlethread_workqueue(DRV_NAME);
4bc85c13 3453
46bc8d4b 3454 init_waitqueue_head(&il->wait_command_queue);
4bc85c13 3455
46bc8d4b
SG
3456 INIT_WORK(&il->restart, il3945_bg_restart);
3457 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3458 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3459 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3460 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
4bc85c13 3461
46bc8d4b 3462 il_setup_scan_deferred_work(il);
4bc85c13 3463
46bc8d4b 3464 il3945_hw_setup_deferred_work(il);
4bc85c13 3465
46bc8d4b
SG
3466 init_timer(&il->watchdog);
3467 il->watchdog.data = (unsigned long)il;
3468 il->watchdog.function = il_bg_watchdog;
4bc85c13 3469
46bc8d4b
SG
3470 tasklet_init(&il->irq_tasklet, (void (*)(unsigned long))
3471 il3945_irq_tasklet, (unsigned long)il);
4bc85c13
WYG
3472}
3473
46bc8d4b 3474static void il3945_cancel_deferred_work(struct il_priv *il)
4bc85c13 3475{
46bc8d4b 3476 il3945_hw_cancel_deferred_work(il);
4bc85c13 3477
46bc8d4b
SG
3478 cancel_delayed_work_sync(&il->init_alive_start);
3479 cancel_delayed_work(&il->alive_start);
4bc85c13 3480
46bc8d4b 3481 il_cancel_scan_deferred_work(il);
4bc85c13
WYG
3482}
3483
e2ebc833 3484static struct attribute *il3945_sysfs_entries[] = {
4bc85c13
WYG
3485 &dev_attr_antenna.attr,
3486 &dev_attr_channels.attr,
3487 &dev_attr_dump_errors.attr,
3488 &dev_attr_flags.attr,
3489 &dev_attr_filter_flags.attr,
3490 &dev_attr_measurement.attr,
3491 &dev_attr_retry_rate.attr,
3492 &dev_attr_status.attr,
3493 &dev_attr_temperature.attr,
3494 &dev_attr_tx_power.attr,
d3175167 3495#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3496 &dev_attr_debug_level.attr,
3497#endif
3498 NULL
3499};
3500
e2ebc833 3501static struct attribute_group il3945_attribute_group = {
4bc85c13 3502 .name = NULL, /* put in device directory */
e2ebc833 3503 .attrs = il3945_sysfs_entries,
4bc85c13
WYG
3504};
3505
e2ebc833
SG
3506struct ieee80211_ops il3945_hw_ops = {
3507 .tx = il3945_mac_tx,
3508 .start = il3945_mac_start,
3509 .stop = il3945_mac_stop,
3510 .add_interface = il_mac_add_interface,
3511 .remove_interface = il_mac_remove_interface,
3512 .change_interface = il_mac_change_interface,
3513 .config = il_mac_config,
3514 .configure_filter = il3945_configure_filter,
3515 .set_key = il3945_mac_set_key,
3516 .conf_tx = il_mac_conf_tx,
3517 .reset_tsf = il_mac_reset_tsf,
3518 .bss_info_changed = il_mac_bss_info_changed,
3519 .hw_scan = il_mac_hw_scan,
3520 .sta_add = il3945_mac_sta_add,
3521 .sta_remove = il_mac_sta_remove,
3522 .tx_last_beacon = il_mac_tx_last_beacon,
4bc85c13
WYG
3523};
3524
46bc8d4b 3525static int il3945_init_drv(struct il_priv *il)
4bc85c13
WYG
3526{
3527 int ret;
46bc8d4b 3528 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 3529
46bc8d4b
SG
3530 il->retry_rate = 1;
3531 il->beacon_skb = NULL;
4bc85c13 3532
46bc8d4b
SG
3533 spin_lock_init(&il->sta_lock);
3534 spin_lock_init(&il->hcmd_lock);
4bc85c13 3535
46bc8d4b 3536 INIT_LIST_HEAD(&il->free_frames);
4bc85c13 3537
46bc8d4b 3538 mutex_init(&il->mutex);
4bc85c13 3539
46bc8d4b
SG
3540 il->ieee_channels = NULL;
3541 il->ieee_rates = NULL;
3542 il->band = IEEE80211_BAND_2GHZ;
4bc85c13 3543
46bc8d4b
SG
3544 il->iw_mode = NL80211_IFTYPE_STATION;
3545 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
4bc85c13
WYG
3546
3547 /* initialize force reset */
46bc8d4b 3548 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
4bc85c13 3549
4bc85c13 3550 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
9406f797 3551 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
4bc85c13
WYG
3552 eeprom->version);
3553 ret = -EINVAL;
3554 goto err;
3555 }
46bc8d4b 3556 ret = il_init_channel_map(il);
4bc85c13 3557 if (ret) {
9406f797 3558 IL_ERR("initializing regulatory failed: %d\n", ret);
4bc85c13
WYG
3559 goto err;
3560 }
3561
3562 /* Set up txpower settings in driver for all channels */
46bc8d4b 3563 if (il3945_txpower_set_from_eeprom(il)) {
4bc85c13
WYG
3564 ret = -EIO;
3565 goto err_free_channel_map;
3566 }
3567
46bc8d4b 3568 ret = il_init_geos(il);
4bc85c13 3569 if (ret) {
9406f797 3570 IL_ERR("initializing geos failed: %d\n", ret);
4bc85c13
WYG
3571 goto err_free_channel_map;
3572 }
46bc8d4b 3573 il3945_init_hw_rates(il, il->ieee_rates);
4bc85c13
WYG
3574
3575 return 0;
3576
3577err_free_channel_map:
46bc8d4b 3578 il_free_channel_map(il);
4bc85c13
WYG
3579err:
3580 return ret;
3581}
3582
d3175167 3583#define IL3945_MAX_PROBE_REQUEST 200
4bc85c13 3584
46bc8d4b 3585static int il3945_setup_mac(struct il_priv *il)
4bc85c13
WYG
3586{
3587 int ret;
46bc8d4b 3588 struct ieee80211_hw *hw = il->hw;
4bc85c13
WYG
3589
3590 hw->rate_control_algorithm = "iwl-3945-rs";
e2ebc833
SG
3591 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3592 hw->vif_data_size = sizeof(struct il_vif_priv);
4bc85c13
WYG
3593
3594 /* Tell mac80211 our characteristics */
3595 hw->flags = IEEE80211_HW_SIGNAL_DBM |
3596 IEEE80211_HW_SPECTRUM_MGMT;
3597
4bc85c13 3598 hw->wiphy->interface_modes =
7c2cde2e 3599 il->ctx.interface_modes;
4bc85c13
WYG
3600
3601 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3602 WIPHY_FLAG_DISABLE_BEACON_HINTS |
3603 WIPHY_FLAG_IBSS_RSN;
3604
3605 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3606 /* we create the 802.11 header and a zero-length SSID element */
d3175167 3607 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
4bc85c13
WYG
3608
3609 /* Default value; 4 EDCA QOS priorities */
3610 hw->queues = 4;
3611
46bc8d4b
SG
3612 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
3613 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3614 &il->bands[IEEE80211_BAND_2GHZ];
4bc85c13 3615
46bc8d4b
SG
3616 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
3617 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3618 &il->bands[IEEE80211_BAND_5GHZ];
4bc85c13 3619
46bc8d4b 3620 il_leds_init(il);
4bc85c13 3621
46bc8d4b 3622 ret = ieee80211_register_hw(il->hw);
4bc85c13 3623 if (ret) {
9406f797 3624 IL_ERR("Failed to register hw (error %d)\n", ret);
4bc85c13
WYG
3625 return ret;
3626 }
46bc8d4b 3627 il->mac80211_registered = 1;
4bc85c13
WYG
3628
3629 return 0;
3630}
3631
e2ebc833 3632static int il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4bc85c13 3633{
7c2cde2e 3634 int err = 0;
46bc8d4b 3635 struct il_priv *il;
4bc85c13 3636 struct ieee80211_hw *hw;
e2ebc833
SG
3637 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3638 struct il3945_eeprom *eeprom;
4bc85c13
WYG
3639 unsigned long flags;
3640
3641 /***********************
3642 * 1. Allocating HW data
3643 * ********************/
3644
3645 /* mac80211 allocates memory for this device instance, including
46bc8d4b 3646 * space for this driver's ilate structure */
e2ebc833 3647 hw = il_alloc_all(cfg);
4bc85c13
WYG
3648 if (hw == NULL) {
3649 pr_err("Can not allocate network device\n");
3650 err = -ENOMEM;
3651 goto out;
3652 }
46bc8d4b 3653 il = hw->priv;
4bc85c13
WYG
3654 SET_IEEE80211_DEV(hw, &pdev->dev);
3655
d3175167 3656 il->cmd_queue = IL39_CMD_QUEUE_NUM;
4bc85c13 3657
7c2cde2e 3658 il->ctx.ctxid = 0;
4bc85c13 3659
7c2cde2e
SG
3660 il->ctx.rxon_cmd = REPLY_RXON;
3661 il->ctx.rxon_timing_cmd = REPLY_RXON_TIMING;
3662 il->ctx.rxon_assoc_cmd = REPLY_RXON_ASSOC;
3663 il->ctx.qos_cmd = REPLY_QOS_PARAM;
3664 il->ctx.ap_sta_id = IL_AP_ID;
3665 il->ctx.wep_key_cmd = REPLY_WEPKEY;
3666 il->ctx.interface_modes =
4bc85c13
WYG
3667 BIT(NL80211_IFTYPE_STATION) |
3668 BIT(NL80211_IFTYPE_ADHOC);
7c2cde2e
SG
3669 il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS;
3670 il->ctx.station_devtype = RXON_DEV_TYPE_ESS;
3671 il->ctx.unused_devtype = RXON_DEV_TYPE_ESS;
4bc85c13
WYG
3672
3673 /*
3674 * Disabling hardware scan means that mac80211 will perform scans
3675 * "the hard way", rather than using device's scan.
3676 */
e2ebc833 3677 if (il3945_mod_params.disable_hw_scan) {
58de00a4 3678 D_INFO("Disabling hw_scan\n");
e2ebc833 3679 il3945_hw_ops.hw_scan = NULL;
4bc85c13
WYG
3680 }
3681
58de00a4 3682 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b
SG
3683 il->cfg = cfg;
3684 il->pci_dev = pdev;
3685 il->inta_mask = CSR_INI_SET_MASK;
4bc85c13 3686
46bc8d4b 3687 if (il_alloc_traffic_mem(il))
9406f797 3688 IL_ERR("Not enough memory to generate traffic log\n");
4bc85c13
WYG
3689
3690 /***************************
3691 * 2. Initializing PCI bus
3692 * *************************/
3693 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3694 PCIE_LINK_STATE_CLKPM);
3695
3696 if (pci_enable_device(pdev)) {
3697 err = -ENODEV;
3698 goto out_ieee80211_free_hw;
3699 }
3700
3701 pci_set_master(pdev);
3702
3703 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3704 if (!err)
3705 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3706 if (err) {
9406f797 3707 IL_WARN("No suitable DMA available.\n");
4bc85c13
WYG
3708 goto out_pci_disable_device;
3709 }
3710
46bc8d4b 3711 pci_set_drvdata(pdev, il);
4bc85c13
WYG
3712 err = pci_request_regions(pdev, DRV_NAME);
3713 if (err)
3714 goto out_pci_disable_device;
3715
3716 /***********************
3717 * 3. Read REV Register
3718 * ********************/
46bc8d4b
SG
3719 il->hw_base = pci_iomap(pdev, 0, 0);
3720 if (!il->hw_base) {
4bc85c13
WYG
3721 err = -ENODEV;
3722 goto out_pci_release_regions;
3723 }
3724
58de00a4 3725 D_INFO("pci_resource_len = 0x%08llx\n",
4bc85c13 3726 (unsigned long long) pci_resource_len(pdev, 0));
58de00a4 3727 D_INFO("pci_resource_base = %p\n", il->hw_base);
4bc85c13
WYG
3728
3729 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3730 * PCI Tx retries from interfering with C3 CPU state */
3731 pci_write_config_byte(pdev, 0x41, 0x00);
3732
3733 /* these spin locks will be used in apm_ops.init and EEPROM access
3734 * we should init now
3735 */
46bc8d4b
SG
3736 spin_lock_init(&il->reg_lock);
3737 spin_lock_init(&il->lock);
4bc85c13
WYG
3738
3739 /*
3740 * stop and reset the on-board processor just in case it is in a
3741 * strange state ... like being left stranded by a primary kernel
3742 * and this is now the kdump kernel trying to start up
3743 */
841b2cca 3744 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
3745
3746 /***********************
3747 * 4. Read EEPROM
3748 * ********************/
3749
3750 /* Read the EEPROM */
46bc8d4b 3751 err = il_eeprom_init(il);
4bc85c13 3752 if (err) {
9406f797 3753 IL_ERR("Unable to init EEPROM\n");
4bc85c13
WYG
3754 goto out_iounmap;
3755 }
3756 /* MAC Address location in EEPROM same for 3945/4965 */
46bc8d4b 3757 eeprom = (struct il3945_eeprom *)il->eeprom;
58de00a4 3758 D_INFO("MAC address: %pM\n", eeprom->mac_address);
46bc8d4b 3759 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
4bc85c13
WYG
3760
3761 /***********************
3762 * 5. Setup HW Constants
3763 * ********************/
3764 /* Device-specific setup */
46bc8d4b 3765 if (il3945_hw_set_hw_params(il)) {
9406f797 3766 IL_ERR("failed to set hw settings\n");
4bc85c13
WYG
3767 goto out_eeprom_free;
3768 }
3769
3770 /***********************
46bc8d4b 3771 * 6. Setup il
4bc85c13
WYG
3772 * ********************/
3773
46bc8d4b 3774 err = il3945_init_drv(il);
4bc85c13 3775 if (err) {
9406f797 3776 IL_ERR("initializing driver failed\n");
4bc85c13
WYG
3777 goto out_unset_hw_params;
3778 }
3779
9406f797 3780 IL_INFO("Detected Intel Wireless WiFi Link %s\n",
46bc8d4b 3781 il->cfg->name);
4bc85c13
WYG
3782
3783 /***********************
3784 * 7. Setup Services
3785 * ********************/
3786
46bc8d4b
SG
3787 spin_lock_irqsave(&il->lock, flags);
3788 il_disable_interrupts(il);
3789 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3790
46bc8d4b 3791 pci_enable_msi(il->pci_dev);
4bc85c13 3792
46bc8d4b
SG
3793 err = request_irq(il->pci_dev->irq, il_isr,
3794 IRQF_SHARED, DRV_NAME, il);
4bc85c13 3795 if (err) {
9406f797 3796 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
4bc85c13
WYG
3797 goto out_disable_msi;
3798 }
3799
e2ebc833 3800 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3801 if (err) {
9406f797 3802 IL_ERR("failed to create sysfs device attributes\n");
4bc85c13
WYG
3803 goto out_release_irq;
3804 }
3805
46bc8d4b
SG
3806 il_set_rxon_channel(il,
3807 &il->bands[IEEE80211_BAND_2GHZ].channels[5],
7c2cde2e 3808 &il->ctx);
46bc8d4b
SG
3809 il3945_setup_deferred_work(il);
3810 il3945_setup_rx_handlers(il);
3811 il_power_initialize(il);
4bc85c13
WYG
3812
3813 /*********************************
3814 * 8. Setup and Register mac80211
3815 * *******************************/
3816
46bc8d4b 3817 il_enable_interrupts(il);
4bc85c13 3818
46bc8d4b 3819 err = il3945_setup_mac(il);
4bc85c13
WYG
3820 if (err)
3821 goto out_remove_sysfs;
3822
46bc8d4b 3823 err = il_dbgfs_register(il, DRV_NAME);
4bc85c13 3824 if (err)
9406f797 3825 IL_ERR("failed to create debugfs files. Ignoring error: %d\n", err);
4bc85c13
WYG
3826
3827 /* Start monitoring the killswitch */
46bc8d4b 3828 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
3829 2 * HZ);
3830
3831 return 0;
3832
3833 out_remove_sysfs:
46bc8d4b
SG
3834 destroy_workqueue(il->workqueue);
3835 il->workqueue = NULL;
e2ebc833 3836 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3837 out_release_irq:
46bc8d4b 3838 free_irq(il->pci_dev->irq, il);
4bc85c13 3839 out_disable_msi:
46bc8d4b
SG
3840 pci_disable_msi(il->pci_dev);
3841 il_free_geos(il);
3842 il_free_channel_map(il);
4bc85c13 3843 out_unset_hw_params:
46bc8d4b 3844 il3945_unset_hw_params(il);
4bc85c13 3845 out_eeprom_free:
46bc8d4b 3846 il_eeprom_free(il);
4bc85c13 3847 out_iounmap:
46bc8d4b 3848 pci_iounmap(pdev, il->hw_base);
4bc85c13
WYG
3849 out_pci_release_regions:
3850 pci_release_regions(pdev);
3851 out_pci_disable_device:
3852 pci_set_drvdata(pdev, NULL);
3853 pci_disable_device(pdev);
3854 out_ieee80211_free_hw:
46bc8d4b
SG
3855 il_free_traffic_mem(il);
3856 ieee80211_free_hw(il->hw);
4bc85c13
WYG
3857 out:
3858 return err;
3859}
3860
e2ebc833 3861static void __devexit il3945_pci_remove(struct pci_dev *pdev)
4bc85c13 3862{
46bc8d4b 3863 struct il_priv *il = pci_get_drvdata(pdev);
4bc85c13
WYG
3864 unsigned long flags;
3865
46bc8d4b 3866 if (!il)
4bc85c13
WYG
3867 return;
3868
58de00a4 3869 D_INFO("*** UNLOAD DRIVER ***\n");
4bc85c13 3870
46bc8d4b 3871 il_dbgfs_unregister(il);
4bc85c13 3872
46bc8d4b 3873 set_bit(STATUS_EXIT_PENDING, &il->status);
4bc85c13 3874
46bc8d4b 3875 il_leds_exit(il);
4bc85c13 3876
46bc8d4b
SG
3877 if (il->mac80211_registered) {
3878 ieee80211_unregister_hw(il->hw);
3879 il->mac80211_registered = 0;
4bc85c13 3880 } else {
46bc8d4b 3881 il3945_down(il);
4bc85c13
WYG
3882 }
3883
3884 /*
3885 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG
3886 * This may be redundant with il_down(), but there are paths to
3887 * run il_down() without calling apm_ops.stop(), and there are
3888 * paths to avoid running il_down() at all before leaving driver.
4bc85c13
WYG
3889 * This (inexpensive) call *makes sure* device is reset.
3890 */
46bc8d4b 3891 il_apm_stop(il);
4bc85c13
WYG
3892
3893 /* make sure we flush any pending irq or
3894 * tasklet for the driver
3895 */
46bc8d4b
SG
3896 spin_lock_irqsave(&il->lock, flags);
3897 il_disable_interrupts(il);
3898 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3899
46bc8d4b 3900 il3945_synchronize_irq(il);
4bc85c13 3901
e2ebc833 3902 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3903
46bc8d4b 3904 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
4bc85c13 3905
46bc8d4b 3906 il3945_dealloc_ucode_pci(il);
4bc85c13 3907
46bc8d4b
SG
3908 if (il->rxq.bd)
3909 il3945_rx_queue_free(il, &il->rxq);
3910 il3945_hw_txq_ctx_free(il);
4bc85c13 3911
46bc8d4b 3912 il3945_unset_hw_params(il);
4bc85c13
WYG
3913
3914 /*netif_stop_queue(dev); */
46bc8d4b 3915 flush_workqueue(il->workqueue);
4bc85c13 3916
e2ebc833 3917 /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes
46bc8d4b 3918 * il->workqueue... so we can't take down the workqueue
4bc85c13 3919 * until now... */
46bc8d4b
SG
3920 destroy_workqueue(il->workqueue);
3921 il->workqueue = NULL;
3922 il_free_traffic_mem(il);
4bc85c13 3923
46bc8d4b 3924 free_irq(pdev->irq, il);
4bc85c13
WYG
3925 pci_disable_msi(pdev);
3926
46bc8d4b 3927 pci_iounmap(pdev, il->hw_base);
4bc85c13
WYG
3928 pci_release_regions(pdev);
3929 pci_disable_device(pdev);
3930 pci_set_drvdata(pdev, NULL);
3931
46bc8d4b
SG
3932 il_free_channel_map(il);
3933 il_free_geos(il);
3934 kfree(il->scan_cmd);
3935 if (il->beacon_skb)
3936 dev_kfree_skb(il->beacon_skb);
4bc85c13 3937
46bc8d4b 3938 ieee80211_free_hw(il->hw);
4bc85c13
WYG
3939}
3940
3941
3942/*****************************************************************************
3943 *
3944 * driver and module entry point
3945 *
3946 *****************************************************************************/
3947
e2ebc833 3948static struct pci_driver il3945_driver = {
4bc85c13 3949 .name = DRV_NAME,
e2ebc833
SG
3950 .id_table = il3945_hw_card_ids,
3951 .probe = il3945_pci_probe,
3952 .remove = __devexit_p(il3945_pci_remove),
3953 .driver.pm = IL_LEGACY_PM_OPS,
4bc85c13
WYG
3954};
3955
e2ebc833 3956static int __init il3945_init(void)
4bc85c13
WYG
3957{
3958
3959 int ret;
3960 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3961 pr_info(DRV_COPYRIGHT "\n");
3962
e2ebc833 3963 ret = il3945_rate_control_register();
4bc85c13
WYG
3964 if (ret) {
3965 pr_err("Unable to register rate control algorithm: %d\n", ret);
3966 return ret;
3967 }
3968
e2ebc833 3969 ret = pci_register_driver(&il3945_driver);
4bc85c13
WYG
3970 if (ret) {
3971 pr_err("Unable to initialize PCI module\n");
3972 goto error_register;
3973 }
3974
3975 return ret;
3976
3977error_register:
e2ebc833 3978 il3945_rate_control_unregister();
4bc85c13
WYG
3979 return ret;
3980}
3981
e2ebc833 3982static void __exit il3945_exit(void)
4bc85c13 3983{
e2ebc833
SG
3984 pci_unregister_driver(&il3945_driver);
3985 il3945_rate_control_unregister();
4bc85c13
WYG
3986}
3987
d3175167 3988MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
4bc85c13 3989
e2ebc833 3990module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO);
4bc85c13 3991MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
e2ebc833 3992module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO);
4bc85c13 3993MODULE_PARM_DESC(swcrypto,
be663ab6 3994 "using software crypto (default 1 [software])");
e2ebc833 3995module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan,
be663ab6 3996 int, S_IRUGO);
0263aa45 3997MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
d3175167 3998#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 3999module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
4bc85c13
WYG
4000MODULE_PARM_DESC(debug, "debug output mask");
4001#endif
e2ebc833 4002module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO);
be663ab6 4003MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4bc85c13 4004
e2ebc833
SG
4005module_exit(il3945_exit);
4006module_init(il3945_init);