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[PATCH] changing CONFIG_LOCALVERSION rebuilds too much, for no good reason
[linux-2.6-block.git] / drivers / net / wireless / ipw2200.h
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43f66a6c 1/******************************************************************************
bf79451e 2
43f66a6c 3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
bf79451e
JG		 4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
43f66a6c 7 published by the Free Software Foundation.
bf79451e
JG		 8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
43f66a6c 12 more details.
bf79451e 13
43f66a6c 14 You should have received a copy of the GNU General Public License along with
bf79451e 15 this program; if not, write to the Free Software Foundation, Inc., 59
43f66a6c 16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
bf79451e 17
43f66a6c
JK		 18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
bf79451e 20
43f66a6c
JK		 21 Contact Information:
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25******************************************************************************/
26
27#ifndef __ipw2200_h__
28#define __ipw2200_h__
29
30#define WEXT_USECHANNELS 1
31
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/config.h>
35#include <linux/init.h>
36
43f66a6c
JK		 37#include <linux/pci.h>
38#include <linux/netdevice.h>
39#include <linux/ethtool.h>
40#include <linux/skbuff.h>
41#include <linux/etherdevice.h>
42#include <linux/delay.h>
43#include <linux/random.h>
843684a2 44#include <linux/dma-mapping.h>
43f66a6c
JK		 45
46#include <linux/firmware.h>
47#include <linux/wireless.h>
3da54c5b 48#include <linux/dma-mapping.h>
43f66a6c
JK		 49#include <asm/io.h>
50
51#include <net/ieee80211.h>
52
53#define DRV_NAME "ipw2200"
54
55#include <linux/workqueue.h>
56
43f66a6c 57/* Authentication and Association States */
0edd5b44 58enum connection_manager_assoc_states {
43f66a6c
JK		 59 CMAS_INIT = 0,
60 CMAS_TX_AUTH_SEQ_1,
61 CMAS_RX_AUTH_SEQ_2,
62 CMAS_AUTH_SEQ_1_PASS,
63 CMAS_AUTH_SEQ_1_FAIL,
64 CMAS_TX_AUTH_SEQ_3,
65 CMAS_RX_AUTH_SEQ_4,
66 CMAS_AUTH_SEQ_2_PASS,
67 CMAS_AUTH_SEQ_2_FAIL,
68 CMAS_AUTHENTICATED,
69 CMAS_TX_ASSOC,
70 CMAS_RX_ASSOC_RESP,
71 CMAS_ASSOCIATED,
72 CMAS_LAST
73};
74
43f66a6c
JK		 75#define IPW_WAIT (1<<0)
76#define IPW_QUIET (1<<1)
77#define IPW_ROAMING (1<<2)
78
79#define IPW_POWER_MODE_CAM 0x00 //(always on)
80#define IPW_POWER_INDEX_1 0x01
81#define IPW_POWER_INDEX_2 0x02
82#define IPW_POWER_INDEX_3 0x03
83#define IPW_POWER_INDEX_4 0x04
84#define IPW_POWER_INDEX_5 0x05
85#define IPW_POWER_AC 0x06
86#define IPW_POWER_BATTERY 0x07
87#define IPW_POWER_LIMIT 0x07
88#define IPW_POWER_MASK 0x0F
89#define IPW_POWER_ENABLED 0x10
90#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
91
92#define IPW_CMD_HOST_COMPLETE 2
93#define IPW_CMD_POWER_DOWN 4
94#define IPW_CMD_SYSTEM_CONFIG 6
95#define IPW_CMD_MULTICAST_ADDRESS 7
96#define IPW_CMD_SSID 8
97#define IPW_CMD_ADAPTER_ADDRESS 11
98#define IPW_CMD_PORT_TYPE 12
99#define IPW_CMD_RTS_THRESHOLD 15
100#define IPW_CMD_FRAG_THRESHOLD 16
101#define IPW_CMD_POWER_MODE 17
102#define IPW_CMD_WEP_KEY 18
103#define IPW_CMD_TGI_TX_KEY 19
104#define IPW_CMD_SCAN_REQUEST 20
105#define IPW_CMD_ASSOCIATE 21
106#define IPW_CMD_SUPPORTED_RATES 22
107#define IPW_CMD_SCAN_ABORT 23
108#define IPW_CMD_TX_FLUSH 24
109#define IPW_CMD_QOS_PARAMETERS 25
110#define IPW_CMD_SCAN_REQUEST_EXT 26
111#define IPW_CMD_DINO_CONFIG 30
112#define IPW_CMD_RSN_CAPABILITIES 31
113#define IPW_CMD_RX_KEY 32
114#define IPW_CMD_CARD_DISABLE 33
115#define IPW_CMD_SEED_NUMBER 34
116#define IPW_CMD_TX_POWER 35
117#define IPW_CMD_COUNTRY_INFO 36
118#define IPW_CMD_AIRONET_INFO 37
119#define IPW_CMD_AP_TX_POWER 38
120#define IPW_CMD_CCKM_INFO 39
121#define IPW_CMD_CCX_VER_INFO 40
122#define IPW_CMD_SET_CALIBRATION 41
123#define IPW_CMD_SENSITIVITY_CALIB 42
124#define IPW_CMD_RETRY_LIMIT 51
125#define IPW_CMD_IPW_PRE_POWER_DOWN 58
126#define IPW_CMD_VAP_BEACON_TEMPLATE 60
127#define IPW_CMD_VAP_DTIM_PERIOD 61
128#define IPW_CMD_EXT_SUPPORTED_RATES 62
129#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
130#define IPW_CMD_VAP_QUIET_INTERVALS 64
131#define IPW_CMD_VAP_CHANNEL_SWITCH 65
132#define IPW_CMD_VAP_MANDATORY_CHANNELS 66
133#define IPW_CMD_VAP_CELL_PWR_LIMIT 67
134#define IPW_CMD_VAP_CF_PARAM_SET 68
135#define IPW_CMD_VAP_SET_BEACONING_STATE 69
136#define IPW_CMD_MEASUREMENT 80
137#define IPW_CMD_POWER_CAPABILITY 81
138#define IPW_CMD_SUPPORTED_CHANNELS 82
139#define IPW_CMD_TPC_REPORT 83
140#define IPW_CMD_WME_INFO 84
141#define IPW_CMD_PRODUCTION_COMMAND 85
142#define IPW_CMD_LINKSYS_EOU_INFO 90
143
144#define RFD_SIZE 4
145#define NUM_TFD_CHUNKS 6
146
147#define TX_QUEUE_SIZE 32
148#define RX_QUEUE_SIZE 32
149
150#define DINO_CMD_WEP_KEY 0x08
151#define DINO_CMD_TX 0x0B
152#define DCT_ANTENNA_A 0x01
153#define DCT_ANTENNA_B 0x02
154
155#define IPW_A_MODE 0
156#define IPW_B_MODE 1
157#define IPW_G_MODE 2
158
bf79451e
JG		 159/*
160 * TX Queue Flag Definitions
43f66a6c
JK		 161 */
162
163/* abort attempt if mgmt frame is rx'd */
bf79451e
JG		 164#define DCT_FLAG_ABORT_MGMT 0x01
165
43f66a6c
JK		 166/* require CTS */
167#define DCT_FLAG_CTS_REQUIRED 0x02
168
169/* use short preamble */
bf79451e 170#define DCT_FLAG_SHORT_PREMBL 0x04
43f66a6c
JK		 171
172/* RTS/CTS first */
173#define DCT_FLAG_RTS_REQD 0x08
174
175/* dont calculate duration field */
176#define DCT_FLAG_DUR_SET 0x10
177
178/* even if MAC WEP set (allows pre-encrypt) */
179#define DCT_FLAG_NO_WEP 0x20
8d45ff7d 180
43f66a6c
JK		 181/* overwrite TSF field */
182#define DCT_FLAG_TSF_REQD 0x40
183
184/* ACK rx is expected to follow */
bf79451e 185#define DCT_FLAG_ACK_REQD 0x80
43f66a6c
JK		 186
187#define DCT_FLAG_EXT_MODE_CCK 0x01
188#define DCT_FLAG_EXT_MODE_OFDM 0x00
189
43f66a6c
JK		 190#define TX_RX_TYPE_MASK 0xFF
191#define TX_FRAME_TYPE 0x00
192#define TX_HOST_COMMAND_TYPE 0x01
193#define RX_FRAME_TYPE 0x09
194#define RX_HOST_NOTIFICATION_TYPE 0x03
195#define RX_HOST_CMD_RESPONSE_TYPE 0x04
196#define RX_TX_FRAME_RESPONSE_TYPE 0x05
197#define TFD_NEED_IRQ_MASK 0x04
198
199#define HOST_CMD_DINO_CONFIG 30
200
201#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
202#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
203#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
204#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
205#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
206#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
207#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
208#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
209#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
210#define HOST_NOTIFICATION_TX_STATUS 19
211#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
212#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
213#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
214#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
215#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
216#define HOST_NOTIFICATION_NOISE_STATS 25
bf79451e 217#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
43f66a6c
JK		 218#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
219
220#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
221#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
222#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
bf79451e 223#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
43f66a6c
JK		 224
225#define MACADRR_BYTE_LEN 6
226
227#define DCR_TYPE_AP 0x01
228#define DCR_TYPE_WLAP 0x02
229#define DCR_TYPE_MU_ESS 0x03
230#define DCR_TYPE_MU_IBSS 0x04
231#define DCR_TYPE_MU_PIBSS 0x05
232#define DCR_TYPE_SNIFFER 0x06
233#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
234
235/**
236 * Generic queue structure
bf79451e 237 *
43f66a6c
JK		 238 * Contains common data for Rx and Tx queues
239 */
240struct clx2_queue {
0edd5b44
JG		 241 int n_bd; /**< number of BDs in this queue */
242 int first_empty; /**< 1-st empty entry (index) */
243 int last_used; /**< last used entry (index) */
244 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
245 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
246 dma_addr_t dma_addr; /**< physical addr for BD's */
247 int low_mark; /**< low watermark, resume queue if free space more than this */
248 int high_mark; /**< high watermark, stop queue if free space less than this */
43f66a6c
JK		 249} __attribute__ ((packed));
250
0edd5b44 251struct machdr32 {
43f66a6c 252 u16 frame_ctl;
0edd5b44
JG		 253 u16 duration; // watch out for endians!
254 u8 addr1[MACADRR_BYTE_LEN];
255 u8 addr2[MACADRR_BYTE_LEN];
256 u8 addr3[MACADRR_BYTE_LEN];
257 u16 seq_ctrl; // more endians!
258 u8 addr4[MACADRR_BYTE_LEN];
43f66a6c 259 u16 qos_ctrl;
0edd5b44 260} __attribute__ ((packed));
43f66a6c 261
0edd5b44 262struct machdr30 {
43f66a6c 263 u16 frame_ctl;
0edd5b44
JG		 264 u16 duration; // watch out for endians!
265 u8 addr1[MACADRR_BYTE_LEN];
266 u8 addr2[MACADRR_BYTE_LEN];
267 u8 addr3[MACADRR_BYTE_LEN];
268 u16 seq_ctrl; // more endians!
269 u8 addr4[MACADRR_BYTE_LEN];
270} __attribute__ ((packed));
271
272struct machdr26 {
43f66a6c 273 u16 frame_ctl;
0edd5b44
JG		 274 u16 duration; // watch out for endians!
275 u8 addr1[MACADRR_BYTE_LEN];
276 u8 addr2[MACADRR_BYTE_LEN];
277 u8 addr3[MACADRR_BYTE_LEN];
278 u16 seq_ctrl; // more endians!
43f66a6c 279 u16 qos_ctrl;
0edd5b44 280} __attribute__ ((packed));
43f66a6c 281
0edd5b44 282struct machdr24 {
43f66a6c 283 u16 frame_ctl;
0edd5b44
JG		 284 u16 duration; // watch out for endians!
285 u8 addr1[MACADRR_BYTE_LEN];
286 u8 addr2[MACADRR_BYTE_LEN];
287 u8 addr3[MACADRR_BYTE_LEN];
288 u16 seq_ctrl; // more endians!
289} __attribute__ ((packed));
43f66a6c
JK		 290
291// TX TFD with 32 byte MAC Header
0edd5b44
JG		 292struct tx_tfd_32 {
293 struct machdr32 mchdr; // 32
294 u32 uivplaceholder[2]; // 8
295} __attribute__ ((packed));
43f66a6c
JK		 296
297// TX TFD with 30 byte MAC Header
0edd5b44
JG		 298struct tx_tfd_30 {
299 struct machdr30 mchdr; // 30
300 u8 reserved[2]; // 2
301 u32 uivplaceholder[2]; // 8
302} __attribute__ ((packed));
43f66a6c
JK		 303
304// tx tfd with 26 byte mac header
0edd5b44
JG		 305struct tx_tfd_26 {
306 struct machdr26 mchdr; // 26
307 u8 reserved1[2]; // 2
308 u32 uivplaceholder[2]; // 8
309 u8 reserved2[4]; // 4
310} __attribute__ ((packed));
43f66a6c
JK		 311
312// tx tfd with 24 byte mac header
0edd5b44
JG		 313struct tx_tfd_24 {
314 struct machdr24 mchdr; // 24
315 u32 uivplaceholder[2]; // 8
316 u8 reserved[8]; // 8
317} __attribute__ ((packed));
43f66a6c
JK		 318
319#define DCT_WEP_KEY_FIELD_LENGTH 16
320
0edd5b44 321struct tfd_command {
43f66a6c
JK		 322 u8 index;
323 u8 length;
324 u16 reserved;
325 u8 payload[0];
0edd5b44 326} __attribute__ ((packed));
43f66a6c
JK		 327
328struct tfd_data {
329 /* Header */
330 u32 work_area_ptr;
0edd5b44 331 u8 station_number; /* 0 for BSS */
43f66a6c
JK		 332 u8 reserved1;
333 u16 reserved2;
334
335 /* Tx Parameters */
336 u8 cmd_id;
bf79451e
JG		 337 u8 seq_num;
338 u16 len;
43f66a6c
JK		 339 u8 priority;
340 u8 tx_flags;
341 u8 tx_flags_ext;
342 u8 key_index;
343 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
344 u8 rate;
345 u8 antenna;
346 u16 next_packet_duration;
bf79451e 347 u16 next_frag_len;
0edd5b44 348 u16 back_off_counter; //////txop;
43f66a6c 349 u8 retrylimit;
bf79451e 350 u16 cwcurrent;
43f66a6c
JK		 351 u8 reserved3;
352
353 /* 802.11 MAC Header */
0edd5b44 354 union {
43f66a6c
JK		 355 struct tx_tfd_24 tfd_24;
356 struct tx_tfd_26 tfd_26;
357 struct tx_tfd_30 tfd_30;
358 struct tx_tfd_32 tfd_32;
359 } tfd;
360
361 /* Payload DMA info */
362 u32 num_chunks;
363 u32 chunk_ptr[NUM_TFD_CHUNKS];
364 u16 chunk_len[NUM_TFD_CHUNKS];
365} __attribute__ ((packed));
366
0edd5b44 367struct txrx_control_flags {
43f66a6c
JK		 368 u8 message_type;
369 u8 rx_seq_num;
370 u8 control_bits;
371 u8 reserved;
372} __attribute__ ((packed));
373
374#define TFD_SIZE 128
375#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
376
0edd5b44 377struct tfd_frame {
43f66a6c
JK		 378 struct txrx_control_flags control_flags;
379 union {
380 struct tfd_data data;
381 struct tfd_command cmd;
382 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
383 } u;
0edd5b44 384} __attribute__ ((packed));
43f66a6c 385
0edd5b44 386typedef void destructor_func(const void *);
43f66a6c
JK		 387
388/**
389 * Tx Queue for DMA. Queue consists of circular buffer of
390 * BD's and required locking structures.
391 */
392struct clx2_tx_queue {
393 struct clx2_queue q;
0edd5b44 394 struct tfd_frame *bd;
43f66a6c
JK		 395 struct ieee80211_txb **txb;
396};
397
398/*
399 * RX related structures and functions
400 */
401#define RX_FREE_BUFFERS 32
402#define RX_LOW_WATERMARK 8
403
404#define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
405#define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
406#define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
407
408// Used for passing to driver number of successes and failures per rate
0edd5b44 409struct rate_histogram {
43f66a6c
JK		 410 union {
411 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
412 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
413 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
414 } success;
415 union {
416 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
417 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
418 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
419 } failed;
420} __attribute__ ((packed));
421
bf79451e 422/* statistics command response */
43f66a6c
JK		 423struct ipw_cmd_stats {
424 u8 cmd_id;
425 u8 seq_num;
bf79451e
JG		 426 u16 good_sfd;
427 u16 bad_plcp;
428 u16 wrong_bssid;
429 u16 valid_mpdu;
430 u16 bad_mac_header;
431 u16 reserved_frame_types;
432 u16 rx_ina;
433 u16 bad_crc32;
434 u16 invalid_cts;
435 u16 invalid_acks;
436 u16 long_distance_ina_fina;
43f66a6c 437 u16 dsp_silence_unreachable;
bf79451e
JG		 438 u16 accumulated_rssi;
439 u16 rx_ovfl_frame_tossed;
43f66a6c
JK		 440 u16 rssi_silence_threshold;
441 u16 rx_ovfl_frame_supplied;
bf79451e
JG		 442 u16 last_rx_frame_signal;
443 u16 last_rx_frame_noise;
444 u16 rx_autodetec_no_ofdm;
43f66a6c
JK		 445 u16 rx_autodetec_no_barker;
446 u16 reserved;
447} __attribute__ ((packed));
448
449struct notif_channel_result {
450 u8 channel_num;
451 struct ipw_cmd_stats stats;
452 u8 uReserved;
453} __attribute__ ((packed));
454
455struct notif_scan_complete {
456 u8 scan_type;
457 u8 num_channels;
458 u8 status;
459 u8 reserved;
0edd5b44 460} __attribute__ ((packed));
43f66a6c
JK		 461
462struct notif_frag_length {
463 u16 frag_length;
464 u16 reserved;
0edd5b44 465} __attribute__ ((packed));
43f66a6c
JK		 466
467struct notif_beacon_state {
468 u32 state;
469 u32 number;
470} __attribute__ ((packed));
471
472struct notif_tgi_tx_key {
473 u8 key_state;
474 u8 security_type;
475 u8 station_index;
476 u8 reserved;
477} __attribute__ ((packed));
478
479struct notif_link_deterioration {
480 struct ipw_cmd_stats stats;
481 u8 rate;
482 u8 modulation;
483 struct rate_histogram histogram;
484 u8 reserved1;
485 u16 reserved2;
486} __attribute__ ((packed));
487
488struct notif_association {
489 u8 state;
490} __attribute__ ((packed));
491
492struct notif_authenticate {
493 u8 state;
494 struct machdr24 addr;
495 u16 status;
496} __attribute__ ((packed));
497
43f66a6c
JK		 498struct notif_calibration {
499 u8 data[104];
500} __attribute__ ((packed));
501
502struct notif_noise {
503 u32 value;
504} __attribute__ ((packed));
505
506struct ipw_rx_notification {
507 u8 reserved[8];
508 u8 subtype;
509 u8 flags;
510 u16 size;
511 union {
512 struct notif_association assoc;
513 struct notif_authenticate auth;
514 struct notif_channel_result channel_result;
515 struct notif_scan_complete scan_complete;
516 struct notif_frag_length frag_len;
517 struct notif_beacon_state beacon_state;
518 struct notif_tgi_tx_key tgi_tx_key;
519 struct notif_link_deterioration link_deterioration;
520 struct notif_calibration calibration;
521 struct notif_noise noise;
522 u8 raw[0];
523 } u;
524} __attribute__ ((packed));
525
526struct ipw_rx_frame {
bf79451e 527 u32 reserved1;
0edd5b44
JG		 528 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
529 u8 received_channel; // The channel that this frame was received on.
530 // Note that for .11b this does not have to be
531 // the same as the channel that it was sent.
532 // Filled by LMAC
43f66a6c
JK		 533 u8 frameStatus;
534 u8 rate;
535 u8 rssi;
536 u8 agc;
537 u8 rssi_dbm;
538 u16 signal;
539 u16 noise;
540 u8 antennaAndPhy;
0edd5b44
JG		 541 u8 control; // control bit should be on in bg
542 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
543 // is identical)
544 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
43f66a6c
JK		 545 u16 length;
546 u8 data[0];
547} __attribute__ ((packed));
bf79451e 548
43f66a6c
JK		 549struct ipw_rx_header {
550 u8 message_type;
551 u8 rx_seq_num;
552 u8 control_bits;
553 u8 reserved;
554} __attribute__ ((packed));
555
0edd5b44 556struct ipw_rx_packet {
43f66a6c
JK		 557 struct ipw_rx_header header;
558 union {
559 struct ipw_rx_frame frame;
560 struct ipw_rx_notification notification;
561 } u;
562} __attribute__ ((packed));
563
564#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
565#define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
566 sizeof(struct ipw_rx_frame)
567
568struct ipw_rx_mem_buffer {
569 dma_addr_t dma_addr;
570 struct ipw_rx_buffer *rxb;
571 struct sk_buff *skb;
572 struct list_head list;
0edd5b44 573}; /* Not transferred over network, so not __attribute__ ((packed)) */
43f66a6c
JK		 574
575struct ipw_rx_queue {
576 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
577 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
0edd5b44
JG		 578 u32 processed; /* Internal index to last handled Rx packet */
579 u32 read; /* Shared index to newest available Rx buffer */
580 u32 write; /* Shared index to oldest written Rx packet */
581 u32 free_count; /* Number of pre-allocated buffers in rx_free */
43f66a6c 582 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
0edd5b44
JG		 583 struct list_head rx_free; /* Own an SKBs */
584 struct list_head rx_used; /* No SKB allocated */
43f66a6c 585 spinlock_t lock;
0edd5b44 586}; /* Not transferred over network, so not __attribute__ ((packed)) */
43f66a6c
JK		 587
588struct alive_command_responce {
589 u8 alive_command;
590 u8 sequence_number;
591 u16 software_revision;
592 u8 device_identifier;
593 u8 reserved1[5];
594 u16 reserved2;
595 u16 reserved3;
596 u16 clock_settle_time;
597 u16 powerup_settle_time;
598 u16 reserved4;
599 u8 time_stamp[5]; /* month, day, year, hours, minutes */
600 u8 ucode_valid;
601} __attribute__ ((packed));
602
603#define IPW_MAX_RATES 12
604
605struct ipw_rates {
606 u8 num_rates;
607 u8 rates[IPW_MAX_RATES];
608} __attribute__ ((packed));
609
0edd5b44 610struct command_block {
43f66a6c
JK		 611 unsigned int control;
612 u32 source_addr;
613 u32 dest_addr;
614 unsigned int status;
615} __attribute__ ((packed));
616
617#define CB_NUMBER_OF_ELEMENTS_SMALL 64
0edd5b44 618struct fw_image_desc {
43f66a6c
JK		 619 unsigned long last_cb_index;
620 unsigned long current_cb_index;
621 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
0edd5b44 622 void *v_addr;
43f66a6c
JK		 623 unsigned long p_addr;
624 unsigned long len;
625};
626
0edd5b44 627struct ipw_sys_config {
43f66a6c
JK		 628 u8 bt_coexistence;
629 u8 reserved1;
630 u8 answer_broadcast_ssid_probe;
631 u8 accept_all_data_frames;
632 u8 accept_non_directed_frames;
633 u8 exclude_unicast_unencrypted;
634 u8 disable_unicast_decryption;
635 u8 exclude_multicast_unencrypted;
636 u8 disable_multicast_decryption;
637 u8 antenna_diversity;
638 u8 pass_crc_to_host;
639 u8 dot11g_auto_detection;
640 u8 enable_cts_to_self;
641 u8 enable_multicast_filtering;
642 u8 bt_coexist_collision_thr;
643 u8 reserved2;
644 u8 accept_all_mgmt_bcpr;
645 u8 accept_all_mgtm_frames;
646 u8 pass_noise_stats_to_host;
647 u8 reserved3;
648} __attribute__ ((packed));
649
0edd5b44 650struct ipw_multicast_addr {
43f66a6c
JK		 651 u8 num_of_multicast_addresses;
652 u8 reserved[3];
653 u8 mac1[6];
654 u8 mac2[6];
655 u8 mac3[6];
656 u8 mac4[6];
657} __attribute__ ((packed));
658
0edd5b44 659struct ipw_wep_key {
43f66a6c
JK		 660 u8 cmd_id;
661 u8 seq_num;
662 u8 key_index;
663 u8 key_size;
664 u8 key[16];
665} __attribute__ ((packed));
666
0edd5b44 667struct ipw_tgi_tx_key {
bf79451e 668 u8 key_id;
43f66a6c
JK		 669 u8 security_type;
670 u8 station_index;
671 u8 flags;
672 u8 key[16];
673 u32 tx_counter[2];
674} __attribute__ ((packed));
675
676#define IPW_SCAN_CHANNELS 54
677
0edd5b44 678struct ipw_scan_request {
43f66a6c
JK		 679 u8 scan_type;
680 u16 dwell_time;
681 u8 channels_list[IPW_SCAN_CHANNELS];
682 u8 channels_reserved[3];
683} __attribute__ ((packed));
684
685enum {
686 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
687 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
688 IPW_SCAN_ACTIVE_DIRECT_SCAN,
689 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
690 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
691 IPW_SCAN_TYPES
692};
693
0edd5b44 694struct ipw_scan_request_ext {
43f66a6c
JK		 695 u32 full_scan_index;
696 u8 channels_list[IPW_SCAN_CHANNELS];
697 u8 scan_type[IPW_SCAN_CHANNELS / 2];
698 u8 reserved;
699 u16 dwell_time[IPW_SCAN_TYPES];
700} __attribute__ ((packed));
701
bf79451e 702extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
43f66a6c
JK		 703{
704 if (index % 2)
705 return scan->scan_type[index / 2] & 0x0F;
706 else
707 return (scan->scan_type[index / 2] & 0xF0) >> 4;
708}
709
bf79451e 710extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
43f66a6c
JK		 711 u8 index, u8 scan_type)
712{
bf79451e
JG		 713 if (index % 2)
714 scan->scan_type[index / 2] =
0edd5b44 715 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
43f66a6c 716 else
bf79451e 717 scan->scan_type[index / 2] =
0edd5b44
JG		 718 (scan->scan_type[index / 2] & 0x0F) |
719 ((scan_type & 0x0F) << 4);
43f66a6c
JK		 720}
721
0edd5b44 722struct ipw_associate {
43f66a6c 723 u8 channel;
0edd5b44 724 u8 auth_type:4, auth_key:4;
43f66a6c
JK		 725 u8 assoc_type;
726 u8 reserved;
727 u16 policy_support;
728 u8 preamble_length;
729 u8 ieee_mode;
730 u8 bssid[ETH_ALEN];
731 u32 assoc_tsf_msw;
732 u32 assoc_tsf_lsw;
733 u16 capability;
734 u16 listen_interval;
735 u16 beacon_interval;
736 u8 dest[ETH_ALEN];
737 u16 atim_window;
738 u8 smr;
739 u8 reserved1;
740 u16 reserved2;
741} __attribute__ ((packed));
742
0edd5b44 743struct ipw_supported_rates {
43f66a6c
JK		 744 u8 ieee_mode;
745 u8 num_rates;
746 u8 purpose;
747 u8 reserved;
748 u8 supported_rates[IPW_MAX_RATES];
749} __attribute__ ((packed));
750
0edd5b44 751struct ipw_rts_threshold {
43f66a6c
JK		 752 u16 rts_threshold;
753 u16 reserved;
754} __attribute__ ((packed));
755
0edd5b44 756struct ipw_frag_threshold {
43f66a6c
JK		 757 u16 frag_threshold;
758 u16 reserved;
759} __attribute__ ((packed));
760
0edd5b44 761struct ipw_retry_limit {
43f66a6c
JK		 762 u8 short_retry_limit;
763 u8 long_retry_limit;
764 u16 reserved;
765} __attribute__ ((packed));
766
0edd5b44 767struct ipw_dino_config {
43f66a6c
JK		 768 u32 dino_config_addr;
769 u16 dino_config_size;
770 u8 dino_response;
771 u8 reserved;
772} __attribute__ ((packed));
773
0edd5b44 774struct ipw_aironet_info {
43f66a6c
JK		 775 u8 id;
776 u8 length;
777 u16 reserved;
778} __attribute__ ((packed));
779
0edd5b44 780struct ipw_rx_key {
43f66a6c
JK		 781 u8 station_index;
782 u8 key_type;
783 u8 key_id;
784 u8 key_flag;
785 u8 key[16];
786 u8 station_address[6];
787 u8 key_index;
788 u8 reserved;
789} __attribute__ ((packed));
790
0edd5b44 791struct ipw_country_channel_info {
43f66a6c
JK		 792 u8 first_channel;
793 u8 no_channels;
794 s8 max_tx_power;
795} __attribute__ ((packed));
796
0edd5b44 797struct ipw_country_info {
43f66a6c
JK		 798 u8 id;
799 u8 length;
800 u8 country_str[3];
801 struct ipw_country_channel_info groups[7];
802} __attribute__ ((packed));
803
0edd5b44 804struct ipw_channel_tx_power {
43f66a6c
JK		 805 u8 channel_number;
806 s8 tx_power;
807} __attribute__ ((packed));
808
809#define SCAN_ASSOCIATED_INTERVAL (HZ)
810#define SCAN_INTERVAL (HZ / 10)
811#define MAX_A_CHANNELS 37
812#define MAX_B_CHANNELS 14
813
0edd5b44 814struct ipw_tx_power {
43f66a6c
JK		 815 u8 num_channels;
816 u8 ieee_mode;
817 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
818} __attribute__ ((packed));
819
0edd5b44 820struct ipw_qos_parameters {
43f66a6c
JK		 821 u16 cw_min[4];
822 u16 cw_max[4];
823 u8 aifs[4];
824 u8 flag[4];
825 u16 tx_op_limit[4];
826} __attribute__ ((packed));
827
0edd5b44 828struct ipw_rsn_capabilities {
43f66a6c
JK		 829 u8 id;
830 u8 length;
831 u16 version;
832} __attribute__ ((packed));
833
0edd5b44 834struct ipw_sensitivity_calib {
43f66a6c
JK		 835 u16 beacon_rssi_raw;
836 u16 reserved;
837} __attribute__ ((packed));
838
839/**
840 * Host command structure.
bf79451e 841 *
43f66a6c
JK		 842 * On input, the following fields should be filled:
843 * - cmd
844 * - len
845 * - status_len
846 * - param (if needed)
bf79451e
JG		 847 *
848 * On output,
43f66a6c
JK		 849 * - \a status contains status;
850 * - \a param filled with status parameters.
851 */
852struct ipw_cmd {
0edd5b44
JG		 853 u32 cmd; /**< Host command */
854 u32 status;/**< Status */
855 u32 status_len;
856 /**< How many 32 bit parameters in the status */
857 u32 len; /**< incoming parameters length, bytes */
43f66a6c 858 /**
bf79451e
JG		 859 * command parameters.
860 * There should be enough space for incoming and
43f66a6c
JK		 861 * outcoming parameters.
862 * Incoming parameters listed 1-st, followed by outcoming params.
863 * nParams=(len+3)/4+status_len
864 */
0edd5b44 865 u32 param[0];
43f66a6c
JK		 866} __attribute__ ((packed));
867
0edd5b44 868#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
43f66a6c
JK		 869
870#define STATUS_INT_ENABLED (1<<1)
871#define STATUS_RF_KILL_HW (1<<2)
872#define STATUS_RF_KILL_SW (1<<3)
873#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
874
875#define STATUS_INIT (1<<5)
876#define STATUS_AUTH (1<<6)
877#define STATUS_ASSOCIATED (1<<7)
878#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
879
880#define STATUS_ASSOCIATING (1<<8)
881#define STATUS_DISASSOCIATING (1<<9)
882#define STATUS_ROAMING (1<<10)
883#define STATUS_EXIT_PENDING (1<<11)
884#define STATUS_DISASSOC_PENDING (1<<12)
885#define STATUS_STATE_PENDING (1<<13)
886
887#define STATUS_SCAN_PENDING (1<<20)
bf79451e
JG		 888#define STATUS_SCANNING (1<<21)
889#define STATUS_SCAN_ABORTING (1<<22)
43f66a6c 890
0edd5b44
JG		 891#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
892#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
893#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
43f66a6c 894
0edd5b44 895#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
43f66a6c 896
0edd5b44
JG		 897#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
898#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
899#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
43f66a6c
JK		 900#define CFG_CUSTOM_MAC (1<<3)
901#define CFG_PREAMBLE (1<<4)
902#define CFG_ADHOC_PERSIST (1<<5)
903#define CFG_ASSOCIATE (1<<6)
904#define CFG_FIXED_RATE (1<<7)
905#define CFG_ADHOC_CREATE (1<<8)
906
0edd5b44
JG		 907#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
908#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
43f66a6c
JK		 909
910#define MAX_STATIONS 32
911#define IPW_INVALID_STATION (0xff)
912
913struct ipw_station_entry {
914 u8 mac_addr[ETH_ALEN];
915 u8 reserved;
916 u8 support_mode;
917};
918
919#define AVG_ENTRIES 8
920struct average {
921 s16 entries[AVG_ENTRIES];
922 u8 pos;
923 u8 init;
924 s32 sum;
925};
926
927struct ipw_priv {
928 /* ieee device used by generic ieee processing code */
929 struct ieee80211_device *ieee;
930 struct ieee80211_security sec;
931
932 /* spinlock */
933 spinlock_t lock;
934
935 /* basic pci-network driver stuff */
936 struct pci_dev *pci_dev;
937 struct net_device *net_dev;
938
939 /* pci hardware address support */
940 void __iomem *hw_base;
941 unsigned long hw_len;
bf79451e 942
43f66a6c
JK		 943 struct fw_image_desc sram_desc;
944
945 /* result of ucode download */
946 struct alive_command_responce dino_alive;
947
0edd5b44
JG		 948 wait_queue_head_t wait_command_queue;
949 wait_queue_head_t wait_state;
43f66a6c
JK		 950
951 /* Rx and Tx DMA processing queues */
952 struct ipw_rx_queue *rxq;
953 struct clx2_tx_queue txq_cmd;
954 struct clx2_tx_queue txq[4];
955 u32 status;
956 u32 config;
957 u32 capability;
958
959 u8 last_rx_rssi;
960 u8 last_noise;
961 struct average average_missed_beacons;
962 struct average average_rssi;
963 struct average average_noise;
964 u32 port_type;
0edd5b44
JG		 965 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
966 int rx_pend_max; /**< maximum pending buffers for one IRQ */
967 u32 hcmd_seq; /**< sequence number for hcmd */
43f66a6c 968 u32 missed_beacon_threshold;
bf79451e 969 u32 roaming_threshold;
43f66a6c
JK		 970
971 struct ipw_associate assoc_request;
972 struct ieee80211_network *assoc_network;
973
974 unsigned long ts_scan_abort;
975 struct ipw_supported_rates rates;
0edd5b44
JG		 976 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
977 struct ipw_rates supp; /**< software defined */
978 struct ipw_rates extended; /**< use for corresp. IE, AP only */
43f66a6c
JK		 979
980 struct notif_link_deterioration last_link_deterioration; /** for statistics */
0edd5b44 981 struct ipw_cmd *hcmd; /**< host command currently executed */
43f66a6c
JK		 982
983 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
0edd5b44 984 u32 tsf_bcn[2]; /**< TSF from latest beacon */
43f66a6c 985
0edd5b44 986 struct notif_calibration calib; /**< last calibration */
43f66a6c
JK		 987
988 /* ordinal interface with firmware */
989 u32 table0_addr;
990 u32 table0_len;
991 u32 table1_addr;
992 u32 table1_len;
993 u32 table2_addr;
994 u32 table2_len;
995
996 /* context information */
997 u8 essid[IW_ESSID_MAX_SIZE];
998 u8 essid_len;
999 u8 nick[IW_ESSID_MAX_SIZE];
1000 u16 rates_mask;
1001 u8 channel;
1002 struct ipw_sys_config sys_config;
1003 u32 power_mode;
bf79451e 1004 u8 bssid[ETH_ALEN];
43f66a6c
JK		 1005 u16 rts_threshold;
1006 u8 mac_addr[ETH_ALEN];
1007 u8 num_stations;
bf79451e 1008 u8 stations[MAX_STATIONS][ETH_ALEN];
43f66a6c
JK		 1009
1010 u32 notif_missed_beacons;
1011
1012 /* Statistics and counters normalized with each association */
1013 u32 last_missed_beacons;
1014 u32 last_tx_packets;
1015 u32 last_rx_packets;
1016 u32 last_tx_failures;
1017 u32 last_rx_err;
1018 u32 last_rate;
1019
1020 u32 missed_adhoc_beacons;
1021 u32 missed_beacons;
1022 u32 rx_packets;
1023 u32 tx_packets;
1024 u32 quality;
1025
0edd5b44
JG		 1026 /* eeprom */
1027 u8 eeprom[0x100]; /* 256 bytes of eeprom */
43f66a6c
JK		 1028 int eeprom_delay;
1029
bf79451e 1030 struct iw_statistics wstats;
43f66a6c
JK		 1031
1032 struct workqueue_struct *workqueue;
bf79451e 1033
43f66a6c
JK		 1034 struct work_struct adhoc_check;
1035 struct work_struct associate;
1036 struct work_struct disassociate;
1037 struct work_struct rx_replenish;
1038 struct work_struct request_scan;
1039 struct work_struct adapter_restart;
1040 struct work_struct rf_kill;
1041 struct work_struct up;
1042 struct work_struct down;
1043 struct work_struct gather_stats;
1044 struct work_struct abort_scan;
1045 struct work_struct roam;
1046 struct work_struct scan_check;
1047
1048 struct tasklet_struct irq_tasklet;
1049
43f66a6c
JK		 1050#define IPW_2200BG 1
1051#define IPW_2915ABG 2
1052 u8 adapter;
1053
1054#define IPW_DEFAULT_TX_POWER 0x14
1055 u8 tx_power;
1056
bf79451e 1057#ifdef CONFIG_PM
43f66a6c
JK		 1058 u32 pm_state[16];
1059#endif
1060
1061 /* network state */
1062
1063 /* Used to pass the current INTA value from ISR to Tasklet */
1064 u32 isr_inta;
1065
1066 /* debugging info */
1067 u32 indirect_dword;
1068 u32 direct_dword;
1069 u32 indirect_byte;
1070}; /*ipw_priv */
1071
43f66a6c
JK		 1072/* debug macros */
1073
1074#ifdef CONFIG_IPW_DEBUG
1075#define IPW_DEBUG(level, fmt, args...) \
1076do { if (ipw_debug_level & (level)) \
1077 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1078 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1079#else
1080#define IPW_DEBUG(level, fmt, args...) do {} while (0)
1081#endif /* CONFIG_IPW_DEBUG */
1082
1083/*
1084 * To use the debug system;
1085 *
1086 * If you are defining a new debug classification, simply add it to the #define
1087 * list here in the form of:
1088 *
1089 * #define IPW_DL_xxxx VALUE
bf79451e 1090 *
43f66a6c
JK		 1091 * shifting value to the left one bit from the previous entry. xxxx should be
1092 * the name of the classification (for example, WEP)
1093 *
1094 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1095 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1096 * to send output to that classification.
1097 *
1098 * To add your debug level to the list of levels seen when you perform
1099 *
1100 * % cat /proc/net/ipw/debug_level
1101 *
1102 * you simply need to add your entry to the ipw_debug_levels array.
1103 *
bf79451e 1104 * If you do not see debug_level in /proc/net/ipw then you do not have
43f66a6c
JK		 1105 * CONFIG_IPW_DEBUG defined in your kernel configuration
1106 *
1107 */
1108
1109#define IPW_DL_ERROR (1<<0)
1110#define IPW_DL_WARNING (1<<1)
1111#define IPW_DL_INFO (1<<2)
1112#define IPW_DL_WX (1<<3)
1113#define IPW_DL_HOST_COMMAND (1<<5)
1114#define IPW_DL_STATE (1<<6)
1115
1116#define IPW_DL_NOTIF (1<<10)
1117#define IPW_DL_SCAN (1<<11)
1118#define IPW_DL_ASSOC (1<<12)
1119#define IPW_DL_DROP (1<<13)
1120#define IPW_DL_IOCTL (1<<14)
1121
1122#define IPW_DL_MANAGE (1<<15)
1123#define IPW_DL_FW (1<<16)
1124#define IPW_DL_RF_KILL (1<<17)
1125#define IPW_DL_FW_ERRORS (1<<18)
1126
43f66a6c
JK		 1127#define IPW_DL_ORD (1<<20)
1128
1129#define IPW_DL_FRAG (1<<21)
1130#define IPW_DL_WEP (1<<22)
1131#define IPW_DL_TX (1<<23)
1132#define IPW_DL_RX (1<<24)
1133#define IPW_DL_ISR (1<<25)
1134#define IPW_DL_FW_INFO (1<<26)
1135#define IPW_DL_IO (1<<27)
1136#define IPW_DL_TRACE (1<<28)
1137
1138#define IPW_DL_STATS (1<<29)
1139
43f66a6c
JK		 1140#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1141#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1142#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1143
1144#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1145#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1146#define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1147#define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1148#define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1149#define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1150#define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1151#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1152#define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1153#define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1154#define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1155#define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1156#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1157#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1158#define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1159#define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1160#define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1161#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1162#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1163#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1164#define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1165
1166#include <linux/ctype.h>
1167
1168/*
1169* Register bit definitions
1170*/
1171
1172/* Dino control registers bits */
1173
1174#define DINO_ENABLE_SYSTEM 0x80
1175#define DINO_ENABLE_CS 0x40
bf79451e 1176#define DINO_RXFIFO_DATA 0x01
43f66a6c
JK		 1177#define DINO_CONTROL_REG 0x00200000
1178
1179#define CX2_INTA_RW 0x00000008
1180#define CX2_INTA_MASK_R 0x0000000C
1181#define CX2_INDIRECT_ADDR 0x00000010
1182#define CX2_INDIRECT_DATA 0x00000014
1183#define CX2_AUTOINC_ADDR 0x00000018
1184#define CX2_AUTOINC_DATA 0x0000001C
1185#define CX2_RESET_REG 0x00000020
1186#define CX2_GP_CNTRL_RW 0x00000024
1187
1188#define CX2_READ_INT_REGISTER 0xFF4
1189
1190#define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1191
1192#define CX2_REGISTER_DOMAIN1_END 0x00001000
1193#define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1194
1195#define CX2_SHARED_LOWER_BOUND 0x00000200
1196#define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1197
1198#define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1199#define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1200
1201#define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1202#define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1203#define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1204
1205/*
1206 * RESET Register Bit Indexes
1207 */
0edd5b44
JG		 1208#define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */
1209#define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */
1210#define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */
1211#define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */
1212#define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */
1213#define CX2_START_STANDBY 0x00000004 /* Bit 2 */
43f66a6c
JK		 1214
1215#define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1216#define CX2_DOMAIN_0_END 0x1000
1217#define CLX_MEM_BAR_SIZE 0x1000
1218
1219#define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1220#define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1221#define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1222#define CX2_BASEBAND_CONTROL_STORE 0X00200010
1223
1224#define CX2_INTERNAL_CMD_EVENT 0X00300004
1225#define CX2_BASEBAND_POWER_DOWN 0x00000001
1226
1227#define CX2_MEM_HALT_AND_RESET 0x003000e0
1228
1229/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1230#define CX2_BIT_HALT_RESET_ON 0x80000000
1231#define CX2_BIT_HALT_RESET_OFF 0x00000000
1232
1233#define CB_LAST_VALID 0x20000000
1234#define CB_INT_ENABLED 0x40000000
1235#define CB_VALID 0x80000000
1236#define CB_SRC_LE 0x08000000
1237#define CB_DEST_LE 0x04000000
1238#define CB_SRC_AUTOINC 0x00800000
1239#define CB_SRC_IO_GATED 0x00400000
1240#define CB_DEST_AUTOINC 0x00080000
1241#define CB_SRC_SIZE_LONG 0x00200000
1242#define CB_DEST_SIZE_LONG 0x00020000
1243
43f66a6c
JK		 1244/* DMA DEFINES */
1245
1246#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1247#define DMA_CB_STOP_AND_ABORT 0x00000C00
bf79451e 1248#define DMA_CB_START 0x00000100
43f66a6c 1249
43f66a6c
JK		 1250#define CX2_SHARED_SRAM_SIZE 0x00030000
1251#define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1252#define CB_MAX_LENGTH 0x1FFF
1253
1254#define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1255#define CX2_EEPROM_IMAGE_SIZE 0x100
1256
43f66a6c
JK		 1257/* DMA defs */
1258#define CX2_DMA_I_CURRENT_CB 0x003000D0
1259#define CX2_DMA_O_CURRENT_CB 0x003000D4
1260#define CX2_DMA_I_DMA_CONTROL 0x003000A4
1261#define CX2_DMA_I_CB_BASE 0x003000A0
1262
1263#define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
1264#define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
1265#define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
1266#define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
1267#define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
1268#define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
1269#define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
1270#define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
1271#define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
1272#define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
1273#define CX2_RX_BD_BASE (0x00000240)
1274#define CX2_RX_BD_SIZE (0x00000244)
1275#define CX2_RFDS_TABLE_LOWER (0x00000500)
1276
1277#define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
1278#define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
1279#define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
1280#define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
1281#define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
1282#define CX2_RX_READ_INDEX (0x000002A0)
1283
1284#define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1285#define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1286#define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1287#define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1288#define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1289#define CX2_RX_WRITE_INDEX (0x00000FA0)
1290
1291/*
1292 * EEPROM Related Definitions
1293 */
1294
1295#define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1296#define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1297#define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1298#define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1299#define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1300
1301#define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1302#define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1303#define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1304#define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1305#define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1306#define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1307
43f66a6c
JK		 1308#define MSB 1
1309#define LSB 0
1310#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1311
1312#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1313 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1314
1315/* EEPROM access by BYTE */
0edd5b44
JG		 1316#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1317#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1318#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1319#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1320#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1321#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1322#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1323#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1324#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1325#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
43f66a6c
JK		 1326
1327/* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1328#define EEPROM_NIC_TYPE_STANDARD 0
1329#define EEPROM_NIC_TYPE_DELL 1
1330#define EEPROM_NIC_TYPE_FUJITSU 2
1331#define EEPROM_NIC_TYPE_IBM 3
1332#define EEPROM_NIC_TYPE_HP 4
1333
1334#define FW_MEM_REG_LOWER_BOUND 0x00300000
bf79451e 1335#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
43f66a6c
JK		 1336
1337#define EEPROM_BIT_SK (1<<0)
1338#define EEPROM_BIT_CS (1<<1)
1339#define EEPROM_BIT_DI (1<<2)
1340#define EEPROM_BIT_DO (1<<4)
1341
1342#define EEPROM_CMD_READ 0x2
1343
1344/* Interrupts masks */
1345#define CX2_INTA_NONE 0x00000000
1346
1347#define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1348#define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1349#define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1350
1351//Inta Bits for CF
1352#define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1353#define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1354#define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1355#define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1356#define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1357
1358#define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1359
1360#define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1361#define CX2_INTA_BIT_POWER_DOWN 0x00200000
1362
1363#define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1364#define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1365#define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1366#define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1367#define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1368
1369/* Interrupts enabled at init time. */
1370#define CX2_INTA_MASK_ALL \
1371 (CX2_INTA_BIT_TX_QUEUE_1 | \
1372 CX2_INTA_BIT_TX_QUEUE_2 | \
1373 CX2_INTA_BIT_TX_QUEUE_3 | \
1374 CX2_INTA_BIT_TX_QUEUE_4 | \
1375 CX2_INTA_BIT_TX_CMD_QUEUE | \
1376 CX2_INTA_BIT_RX_TRANSFER | \
1377 CX2_INTA_BIT_FATAL_ERROR | \
1378 CX2_INTA_BIT_PARITY_ERROR | \
1379 CX2_INTA_BIT_STATUS_CHANGE | \
1380 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1381 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1382 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1383 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1384 CX2_INTA_BIT_POWER_DOWN | \
1385 CX2_INTA_BIT_RF_KILL_DONE )
1386
1387#define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1388#define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1389
1390/* FW event log definitions */
1391#define EVENT_ELEM_SIZE (3 * sizeof(u32))
1392#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1393
1394/* FW error log definitions */
1395#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1396#define ERROR_START_OFFSET (1 * sizeof(u32))
1397
1398enum {
1399 IPW_FW_ERROR_OK = 0,
1400 IPW_FW_ERROR_FAIL,
1401 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1402 IPW_FW_ERROR_MEMORY_OVERFLOW,
1403 IPW_FW_ERROR_BAD_PARAM,
1404 IPW_FW_ERROR_BAD_CHECKSUM,
1405 IPW_FW_ERROR_NMI_INTERRUPT,
1406 IPW_FW_ERROR_BAD_DATABASE,
1407 IPW_FW_ERROR_ALLOC_FAIL,
1408 IPW_FW_ERROR_DMA_UNDERRUN,
1409 IPW_FW_ERROR_DMA_STATUS,
1410 IPW_FW_ERROR_DINOSTATUS_ERROR,
1411 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1412 IPW_FW_ERROR_SYSASSERT,
1413 IPW_FW_ERROR_FATAL_ERROR
1414};
1415
1416#define AUTH_OPEN 0
1417#define AUTH_SHARED_KEY 1
1418#define AUTH_IGNORE 3
1419
1420#define HC_ASSOCIATE 0
1421#define HC_REASSOCIATE 1
1422#define HC_DISASSOCIATE 2
1423#define HC_IBSS_START 3
1424#define HC_IBSS_RECONF 4
1425#define HC_DISASSOC_QUIET 5
1426
1427#define IPW_RATE_CAPABILITIES 1
1428#define IPW_RATE_CONNECT 0
1429
bf79451e
JG		 1430/*
1431 * Rate values and masks
43f66a6c
JK		 1432 */
1433#define IPW_TX_RATE_1MB 0x0A
1434#define IPW_TX_RATE_2MB 0x14
1435#define IPW_TX_RATE_5MB 0x37
1436#define IPW_TX_RATE_6MB 0x0D
1437#define IPW_TX_RATE_9MB 0x0F
bf79451e 1438#define IPW_TX_RATE_11MB 0x6E
43f66a6c
JK		 1439#define IPW_TX_RATE_12MB 0x05
1440#define IPW_TX_RATE_18MB 0x07
1441#define IPW_TX_RATE_24MB 0x09
1442#define IPW_TX_RATE_36MB 0x0B
1443#define IPW_TX_RATE_48MB 0x01
1444#define IPW_TX_RATE_54MB 0x03
1445
1446#define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1447#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1448
bf79451e
JG		 1449#define IPW_ORD_TABLE_0_MASK 0x0000F000
1450#define IPW_ORD_TABLE_1_MASK 0x0000F100
1451#define IPW_ORD_TABLE_2_MASK 0x0000F200
1452#define IPW_ORD_TABLE_3_MASK 0x0000F300
1453#define IPW_ORD_TABLE_4_MASK 0x0000F400
1454#define IPW_ORD_TABLE_5_MASK 0x0000F500
1455#define IPW_ORD_TABLE_6_MASK 0x0000F600
1456#define IPW_ORD_TABLE_7_MASK 0x0000F700
43f66a6c
JK		 1457
1458/*
1459 * Table 0 Entries (all entries are 32 bits)
1460 */
bf79451e 1461enum {
43f66a6c
JK		 1462 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1463 IPW_ORD_STAT_FRAG_TRESHOLD,
1464 IPW_ORD_STAT_RTS_THRESHOLD,
bf79451e
JG		 1465 IPW_ORD_STAT_TX_HOST_REQUESTS,
1466 IPW_ORD_STAT_TX_HOST_COMPLETE,
1467 IPW_ORD_STAT_TX_DIR_DATA,
43f66a6c
JK		 1468 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1469 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1470 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1471 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1472 /* Hole */
1473
43f66a6c
JK		 1474 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1475 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1476 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1477 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1478 IPW_ORD_STAT_TX_DIR_DATA_G_9,
bf79451e 1479 IPW_ORD_STAT_TX_DIR_DATA_G_11,
43f66a6c
JK		 1480 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1481 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1482 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1483 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1484 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1485 IPW_ORD_STAT_TX_DIR_DATA_G_54,
bf79451e 1486 IPW_ORD_STAT_TX_NON_DIR_DATA,
43f66a6c
JK		 1487 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1488 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1489 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
bf79451e 1490 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
43f66a6c
JK		 1491 /* Hole */
1492
43f66a6c
JK		 1493 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1494 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1495 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1496 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1497 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
bf79451e 1498 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
43f66a6c
JK		 1499 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1500 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1501 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1502 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1503 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1504 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1505 IPW_ORD_STAT_TX_RETRY,
1506 IPW_ORD_STAT_TX_FAILURE,
1507 IPW_ORD_STAT_RX_ERR_CRC,
1508 IPW_ORD_STAT_RX_ERR_ICV,
1509 IPW_ORD_STAT_RX_NO_BUFFER,
1510 IPW_ORD_STAT_FULL_SCANS,
1511 IPW_ORD_STAT_PARTIAL_SCANS,
1512 IPW_ORD_STAT_TGH_ABORTED_SCANS,
bf79451e 1513 IPW_ORD_STAT_TX_TOTAL_BYTES,
43f66a6c
JK		 1514 IPW_ORD_STAT_CURR_RSSI_RAW,
1515 IPW_ORD_STAT_RX_BEACON,
1516 IPW_ORD_STAT_MISSED_BEACONS,
bf79451e
JG		 1517 IPW_ORD_TABLE_0_LAST
1518};
43f66a6c
JK		 1519
1520#define IPW_RSSI_TO_DBM 112
1521
1522/* Table 1 Entries
1523 */
1524enum {
1525 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1526};
1527
1528/*
1529 * Table 2 Entries
1530 *
1531 * FW_VERSION: 16 byte string
1532 * FW_DATE: 16 byte string (only 14 bytes used)
1533 * UCODE_VERSION: 4 byte version code
1534 * UCODE_DATE: 5 bytes code code
1535 * ADDAPTER_MAC: 6 byte MAC address
1536 * RTC: 4 byte clock
1537 */
bf79451e 1538enum {
43f66a6c 1539 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
bf79451e 1540 IPW_ORD_STAT_FW_DATE,
43f66a6c 1541 IPW_ORD_STAT_UCODE_VERSION,
bf79451e
JG		 1542 IPW_ORD_STAT_UCODE_DATE,
1543 IPW_ORD_STAT_ADAPTER_MAC,
1544 IPW_ORD_STAT_RTC,
1545 IPW_ORD_TABLE_2_LAST
1546};
43f66a6c
JK		 1547
1548/* Table 3 */
1549enum {
1550 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1551 IPW_ORD_STAT_TX_PACKET_FAILURE,
1552 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1553 IPW_ORD_STAT_TX_PACKET_ABORTED,
1554 IPW_ORD_TABLE_3_LAST
1555};
1556
1557/* Table 4 */
1558enum {
1559 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1560};
1561
1562/* Table 5 */
1563enum {
1564 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1565 IPW_ORD_STAT_AP_ASSNS,
1566 IPW_ORD_STAT_ROAM,
1567 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1568 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1569 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1570 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1571 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1572 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1573 IPW_ORD_STAT_LINK_UP,
1574 IPW_ORD_STAT_LINK_DOWN,
1575 IPW_ORD_ANTENNA_DIVERSITY,
1576 IPW_ORD_CURR_FREQ,
1577 IPW_ORD_TABLE_5_LAST
1578};
1579
1580/* Table 6 */
1581enum {
1582 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1583 IPW_ORD_CURR_BSSID,
1584 IPW_ORD_CURR_SSID,
1585 IPW_ORD_TABLE_6_LAST
1586};
1587
1588/* Table 7 */
1589enum {
1590 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1591 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1592 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1593 IPW_ORD_STAT_CURR_RSSI_DBM,
1594 IPW_ORD_TABLE_7_LAST
1595};
1596
1597#define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1598#define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1599#define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1600#define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1601#define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1602
1603struct ipw_fixed_rate {
1604 u16 tx_rates;
1605 u16 reserved;
1606} __attribute__ ((packed));
1607
1608#define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1609
1610struct host_cmd {
1611 u8 cmd;
1612 u8 len;
1613 u16 reserved;
1614 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1615} __attribute__ ((packed));
1616
1617#define CFG_BT_COEXISTENCE_MIN 0x00
1618#define CFG_BT_COEXISTENCE_DEFER 0x02
1619#define CFG_BT_COEXISTENCE_KILL 0x04
1620#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1621#define CFG_BT_COEXISTENCE_OOB 0x10
1622#define CFG_BT_COEXISTENCE_MAX 0xFF
0edd5b44 1623#define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM */
43f66a6c
JK		 1624
1625#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1626#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1627#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1628
1629#define CFG_SYS_ANTENNA_BOTH 0x000
1630#define CFG_SYS_ANTENNA_A 0x001
1631#define CFG_SYS_ANTENNA_B 0x003
1632
1633/*
bf79451e 1634 * The definitions below were lifted off the ipw2100 driver, which only
43f66a6c 1635 * supports 'b' mode, so I'm sure these are not exactly correct.
bf79451e 1636 *
43f66a6c
JK		 1637 * Somebody fix these!!
1638 */
1639#define REG_MIN_CHANNEL 0
1640#define REG_MAX_CHANNEL 14
1641
1642#define REG_CHANNEL_MASK 0x00003FFF
1643#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1644
bf79451e
JG		 1645static const long ipw_frequencies[] = {
1646 2412, 2417, 2422, 2427,
1647 2432, 2437, 2442, 2447,
1648 2452, 2457, 2462, 2467,
1649 2472, 2484
43f66a6c
JK		 1650};
1651
1652#define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1653
1654#define IPW_MAX_CONFIG_RETRIES 10
1655
0dacca1f 1656static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr)
43f66a6c
JK		 1657{
1658 u32 retval;
1659 u16 fc;
1660
0dacca1f 1661 retval = sizeof(struct ieee80211_hdr_3addr);
43f66a6c
JK		 1662 fc = le16_to_cpu(hdr->frame_ctl);
1663
1664 /*
0edd5b44
JG		 1665 * Function ToDS FromDS
1666 * IBSS 0 0
1667 * To AP 1 0
1668 * From AP 0 1
1669 * WDS (bridge) 1 1
43f66a6c
JK		 1670 *
1671 * Only WDS frames use Address4 among them. --YZ
1672 */
1673 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1674 retval -= ETH_ALEN;
1675
1676 return retval;
1677}
1678
0edd5b44 1679#endif /* __ipw2200_h__ */
Linux 6.x block layer and io_uring tree(s)