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[PATCH] Introduce sg_set_buf
[linux-2.6-block.git] / drivers / net / wireless / ipw2200.h
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43f66a6c 1/******************************************************************************
bf79451e 2
43f66a6c 3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
bf79451e
JG		 4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
43f66a6c 7 published by the Free Software Foundation.
bf79451e
JG		 8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
43f66a6c 12 more details.
bf79451e 13
43f66a6c 14 You should have received a copy of the GNU General Public License along with
bf79451e 15 this program; if not, write to the Free Software Foundation, Inc., 59
43f66a6c 16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
bf79451e 17
43f66a6c
JK		 18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
bf79451e 20
43f66a6c
JK		 21 Contact Information:
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25******************************************************************************/
26
27#ifndef __ipw2200_h__
28#define __ipw2200_h__
29
30#define WEXT_USECHANNELS 1
31
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/config.h>
35#include <linux/init.h>
36
37#include <linux/version.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/ethtool.h>
41#include <linux/skbuff.h>
42#include <linux/etherdevice.h>
43#include <linux/delay.h>
44#include <linux/random.h>
843684a2 45#include <linux/dma-mapping.h>
43f66a6c
JK		 46
47#include <linux/firmware.h>
48#include <linux/wireless.h>
3da54c5b 49#include <linux/dma-mapping.h>
43f66a6c
JK		 50#include <asm/io.h>
51
52#include <net/ieee80211.h>
53
54#define DRV_NAME "ipw2200"
55
56#include <linux/workqueue.h>
57
43f66a6c 58/* Authentication and Association States */
0edd5b44 59enum connection_manager_assoc_states {
43f66a6c
JK		 60 CMAS_INIT = 0,
61 CMAS_TX_AUTH_SEQ_1,
62 CMAS_RX_AUTH_SEQ_2,
63 CMAS_AUTH_SEQ_1_PASS,
64 CMAS_AUTH_SEQ_1_FAIL,
65 CMAS_TX_AUTH_SEQ_3,
66 CMAS_RX_AUTH_SEQ_4,
67 CMAS_AUTH_SEQ_2_PASS,
68 CMAS_AUTH_SEQ_2_FAIL,
69 CMAS_AUTHENTICATED,
70 CMAS_TX_ASSOC,
71 CMAS_RX_ASSOC_RESP,
72 CMAS_ASSOCIATED,
73 CMAS_LAST
74};
75
43f66a6c
JK		 76#define IPW_WAIT (1<<0)
77#define IPW_QUIET (1<<1)
78#define IPW_ROAMING (1<<2)
79
80#define IPW_POWER_MODE_CAM 0x00 //(always on)
81#define IPW_POWER_INDEX_1 0x01
82#define IPW_POWER_INDEX_2 0x02
83#define IPW_POWER_INDEX_3 0x03
84#define IPW_POWER_INDEX_4 0x04
85#define IPW_POWER_INDEX_5 0x05
86#define IPW_POWER_AC 0x06
87#define IPW_POWER_BATTERY 0x07
88#define IPW_POWER_LIMIT 0x07
89#define IPW_POWER_MASK 0x0F
90#define IPW_POWER_ENABLED 0x10
91#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
92
93#define IPW_CMD_HOST_COMPLETE 2
94#define IPW_CMD_POWER_DOWN 4
95#define IPW_CMD_SYSTEM_CONFIG 6
96#define IPW_CMD_MULTICAST_ADDRESS 7
97#define IPW_CMD_SSID 8
98#define IPW_CMD_ADAPTER_ADDRESS 11
99#define IPW_CMD_PORT_TYPE 12
100#define IPW_CMD_RTS_THRESHOLD 15
101#define IPW_CMD_FRAG_THRESHOLD 16
102#define IPW_CMD_POWER_MODE 17
103#define IPW_CMD_WEP_KEY 18
104#define IPW_CMD_TGI_TX_KEY 19
105#define IPW_CMD_SCAN_REQUEST 20
106#define IPW_CMD_ASSOCIATE 21
107#define IPW_CMD_SUPPORTED_RATES 22
108#define IPW_CMD_SCAN_ABORT 23
109#define IPW_CMD_TX_FLUSH 24
110#define IPW_CMD_QOS_PARAMETERS 25
111#define IPW_CMD_SCAN_REQUEST_EXT 26
112#define IPW_CMD_DINO_CONFIG 30
113#define IPW_CMD_RSN_CAPABILITIES 31
114#define IPW_CMD_RX_KEY 32
115#define IPW_CMD_CARD_DISABLE 33
116#define IPW_CMD_SEED_NUMBER 34
117#define IPW_CMD_TX_POWER 35
118#define IPW_CMD_COUNTRY_INFO 36
119#define IPW_CMD_AIRONET_INFO 37
120#define IPW_CMD_AP_TX_POWER 38
121#define IPW_CMD_CCKM_INFO 39
122#define IPW_CMD_CCX_VER_INFO 40
123#define IPW_CMD_SET_CALIBRATION 41
124#define IPW_CMD_SENSITIVITY_CALIB 42
125#define IPW_CMD_RETRY_LIMIT 51
126#define IPW_CMD_IPW_PRE_POWER_DOWN 58
127#define IPW_CMD_VAP_BEACON_TEMPLATE 60
128#define IPW_CMD_VAP_DTIM_PERIOD 61
129#define IPW_CMD_EXT_SUPPORTED_RATES 62
130#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
131#define IPW_CMD_VAP_QUIET_INTERVALS 64
132#define IPW_CMD_VAP_CHANNEL_SWITCH 65
133#define IPW_CMD_VAP_MANDATORY_CHANNELS 66
134#define IPW_CMD_VAP_CELL_PWR_LIMIT 67
135#define IPW_CMD_VAP_CF_PARAM_SET 68
136#define IPW_CMD_VAP_SET_BEACONING_STATE 69
137#define IPW_CMD_MEASUREMENT 80
138#define IPW_CMD_POWER_CAPABILITY 81
139#define IPW_CMD_SUPPORTED_CHANNELS 82
140#define IPW_CMD_TPC_REPORT 83
141#define IPW_CMD_WME_INFO 84
142#define IPW_CMD_PRODUCTION_COMMAND 85
143#define IPW_CMD_LINKSYS_EOU_INFO 90
144
145#define RFD_SIZE 4
146#define NUM_TFD_CHUNKS 6
147
148#define TX_QUEUE_SIZE 32
149#define RX_QUEUE_SIZE 32
150
151#define DINO_CMD_WEP_KEY 0x08
152#define DINO_CMD_TX 0x0B
153#define DCT_ANTENNA_A 0x01
154#define DCT_ANTENNA_B 0x02
155
156#define IPW_A_MODE 0
157#define IPW_B_MODE 1
158#define IPW_G_MODE 2
159
bf79451e
JG		 160/*
161 * TX Queue Flag Definitions
43f66a6c
JK		 162 */
163
164/* abort attempt if mgmt frame is rx'd */
bf79451e
JG		 165#define DCT_FLAG_ABORT_MGMT 0x01
166
43f66a6c
JK		 167/* require CTS */
168#define DCT_FLAG_CTS_REQUIRED 0x02
169
170/* use short preamble */
bf79451e 171#define DCT_FLAG_SHORT_PREMBL 0x04
43f66a6c
JK		 172
173/* RTS/CTS first */
174#define DCT_FLAG_RTS_REQD 0x08
175
176/* dont calculate duration field */
177#define DCT_FLAG_DUR_SET 0x10
178
179/* even if MAC WEP set (allows pre-encrypt) */
180#define DCT_FLAG_NO_WEP 0x20
8d45ff7d 181
43f66a6c
JK		 182/* overwrite TSF field */
183#define DCT_FLAG_TSF_REQD 0x40
184
185/* ACK rx is expected to follow */
bf79451e 186#define DCT_FLAG_ACK_REQD 0x80
43f66a6c
JK		 187
188#define DCT_FLAG_EXT_MODE_CCK 0x01
189#define DCT_FLAG_EXT_MODE_OFDM 0x00
190
43f66a6c
JK		 191#define TX_RX_TYPE_MASK 0xFF
192#define TX_FRAME_TYPE 0x00
193#define TX_HOST_COMMAND_TYPE 0x01
194#define RX_FRAME_TYPE 0x09
195#define RX_HOST_NOTIFICATION_TYPE 0x03
196#define RX_HOST_CMD_RESPONSE_TYPE 0x04
197#define RX_TX_FRAME_RESPONSE_TYPE 0x05
198#define TFD_NEED_IRQ_MASK 0x04
199
200#define HOST_CMD_DINO_CONFIG 30
201
202#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
203#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
204#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
205#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
206#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
207#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
208#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
209#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
210#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
211#define HOST_NOTIFICATION_TX_STATUS 19
212#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
213#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
214#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
215#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
216#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
217#define HOST_NOTIFICATION_NOISE_STATS 25
bf79451e 218#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
43f66a6c
JK		 219#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
220
221#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
222#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
223#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
bf79451e 224#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
43f66a6c
JK		 225
226#define MACADRR_BYTE_LEN 6
227
228#define DCR_TYPE_AP 0x01
229#define DCR_TYPE_WLAP 0x02
230#define DCR_TYPE_MU_ESS 0x03
231#define DCR_TYPE_MU_IBSS 0x04
232#define DCR_TYPE_MU_PIBSS 0x05
233#define DCR_TYPE_SNIFFER 0x06
234#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
235
236/**
237 * Generic queue structure
bf79451e 238 *
43f66a6c
JK		 239 * Contains common data for Rx and Tx queues
240 */
241struct clx2_queue {
0edd5b44
JG		 242 int n_bd; /**< number of BDs in this queue */
243 int first_empty; /**< 1-st empty entry (index) */
244 int last_used; /**< last used entry (index) */
245 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
246 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
247 dma_addr_t dma_addr; /**< physical addr for BD's */
248 int low_mark; /**< low watermark, resume queue if free space more than this */
249 int high_mark; /**< high watermark, stop queue if free space less than this */
43f66a6c
JK		 250} __attribute__ ((packed));
251
0edd5b44 252struct machdr32 {
43f66a6c 253 u16 frame_ctl;
0edd5b44
JG		 254 u16 duration; // watch out for endians!
255 u8 addr1[MACADRR_BYTE_LEN];
256 u8 addr2[MACADRR_BYTE_LEN];
257 u8 addr3[MACADRR_BYTE_LEN];
258 u16 seq_ctrl; // more endians!
259 u8 addr4[MACADRR_BYTE_LEN];
43f66a6c 260 u16 qos_ctrl;
0edd5b44 261} __attribute__ ((packed));
43f66a6c 262
0edd5b44 263struct machdr30 {
43f66a6c 264 u16 frame_ctl;
0edd5b44
JG		 265 u16 duration; // watch out for endians!
266 u8 addr1[MACADRR_BYTE_LEN];
267 u8 addr2[MACADRR_BYTE_LEN];
268 u8 addr3[MACADRR_BYTE_LEN];
269 u16 seq_ctrl; // more endians!
270 u8 addr4[MACADRR_BYTE_LEN];
271} __attribute__ ((packed));
272
273struct machdr26 {
43f66a6c 274 u16 frame_ctl;
0edd5b44
JG		 275 u16 duration; // watch out for endians!
276 u8 addr1[MACADRR_BYTE_LEN];
277 u8 addr2[MACADRR_BYTE_LEN];
278 u8 addr3[MACADRR_BYTE_LEN];
279 u16 seq_ctrl; // more endians!
43f66a6c 280 u16 qos_ctrl;
0edd5b44 281} __attribute__ ((packed));
43f66a6c 282
0edd5b44 283struct machdr24 {
43f66a6c 284 u16 frame_ctl;
0edd5b44
JG		 285 u16 duration; // watch out for endians!
286 u8 addr1[MACADRR_BYTE_LEN];
287 u8 addr2[MACADRR_BYTE_LEN];
288 u8 addr3[MACADRR_BYTE_LEN];
289 u16 seq_ctrl; // more endians!
290} __attribute__ ((packed));
43f66a6c
JK		 291
292// TX TFD with 32 byte MAC Header
0edd5b44
JG		 293struct tx_tfd_32 {
294 struct machdr32 mchdr; // 32
295 u32 uivplaceholder[2]; // 8
296} __attribute__ ((packed));
43f66a6c
JK		 297
298// TX TFD with 30 byte MAC Header
0edd5b44
JG		 299struct tx_tfd_30 {
300 struct machdr30 mchdr; // 30
301 u8 reserved[2]; // 2
302 u32 uivplaceholder[2]; // 8
303} __attribute__ ((packed));
43f66a6c
JK		 304
305// tx tfd with 26 byte mac header
0edd5b44
JG		 306struct tx_tfd_26 {
307 struct machdr26 mchdr; // 26
308 u8 reserved1[2]; // 2
309 u32 uivplaceholder[2]; // 8
310 u8 reserved2[4]; // 4
311} __attribute__ ((packed));
43f66a6c
JK		 312
313// tx tfd with 24 byte mac header
0edd5b44
JG		 314struct tx_tfd_24 {
315 struct machdr24 mchdr; // 24
316 u32 uivplaceholder[2]; // 8
317 u8 reserved[8]; // 8
318} __attribute__ ((packed));
43f66a6c
JK		 319
320#define DCT_WEP_KEY_FIELD_LENGTH 16
321
0edd5b44 322struct tfd_command {
43f66a6c
JK		 323 u8 index;
324 u8 length;
325 u16 reserved;
326 u8 payload[0];
0edd5b44 327} __attribute__ ((packed));
43f66a6c
JK		 328
329struct tfd_data {
330 /* Header */
331 u32 work_area_ptr;
0edd5b44 332 u8 station_number; /* 0 for BSS */
43f66a6c
JK		 333 u8 reserved1;
334 u16 reserved2;
335
336 /* Tx Parameters */
337 u8 cmd_id;
bf79451e
JG		 338 u8 seq_num;
339 u16 len;
43f66a6c
JK		 340 u8 priority;
341 u8 tx_flags;
342 u8 tx_flags_ext;
343 u8 key_index;
344 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
345 u8 rate;
346 u8 antenna;
347 u16 next_packet_duration;
bf79451e 348 u16 next_frag_len;
0edd5b44 349 u16 back_off_counter; //////txop;
43f66a6c 350 u8 retrylimit;
bf79451e 351 u16 cwcurrent;
43f66a6c
JK		 352 u8 reserved3;
353
354 /* 802.11 MAC Header */
0edd5b44 355 union {
43f66a6c
JK		 356 struct tx_tfd_24 tfd_24;
357 struct tx_tfd_26 tfd_26;
358 struct tx_tfd_30 tfd_30;
359 struct tx_tfd_32 tfd_32;
360 } tfd;
361
362 /* Payload DMA info */
363 u32 num_chunks;
364 u32 chunk_ptr[NUM_TFD_CHUNKS];
365 u16 chunk_len[NUM_TFD_CHUNKS];
366} __attribute__ ((packed));
367
0edd5b44 368struct txrx_control_flags {
43f66a6c
JK		 369 u8 message_type;
370 u8 rx_seq_num;
371 u8 control_bits;
372 u8 reserved;
373} __attribute__ ((packed));
374
375#define TFD_SIZE 128
376#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
377
0edd5b44 378struct tfd_frame {
43f66a6c
JK		 379 struct txrx_control_flags control_flags;
380 union {
381 struct tfd_data data;
382 struct tfd_command cmd;
383 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
384 } u;
0edd5b44 385} __attribute__ ((packed));
43f66a6c 386
0edd5b44 387typedef void destructor_func(const void *);
43f66a6c
JK		 388
389/**
390 * Tx Queue for DMA. Queue consists of circular buffer of
391 * BD's and required locking structures.
392 */
393struct clx2_tx_queue {
394 struct clx2_queue q;
0edd5b44 395 struct tfd_frame *bd;
43f66a6c
JK		 396 struct ieee80211_txb **txb;
397};
398
399/*
400 * RX related structures and functions
401 */
402#define RX_FREE_BUFFERS 32
403#define RX_LOW_WATERMARK 8
404
405#define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
406#define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
407#define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
408
409// Used for passing to driver number of successes and failures per rate
0edd5b44 410struct rate_histogram {
43f66a6c
JK		 411 union {
412 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
413 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
414 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
415 } success;
416 union {
417 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
418 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
419 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
420 } failed;
421} __attribute__ ((packed));
422
bf79451e 423/* statistics command response */
43f66a6c
JK		 424struct ipw_cmd_stats {
425 u8 cmd_id;
426 u8 seq_num;
bf79451e
JG		 427 u16 good_sfd;
428 u16 bad_plcp;
429 u16 wrong_bssid;
430 u16 valid_mpdu;
431 u16 bad_mac_header;
432 u16 reserved_frame_types;
433 u16 rx_ina;
434 u16 bad_crc32;
435 u16 invalid_cts;
436 u16 invalid_acks;
437 u16 long_distance_ina_fina;
43f66a6c 438 u16 dsp_silence_unreachable;
bf79451e
JG		 439 u16 accumulated_rssi;
440 u16 rx_ovfl_frame_tossed;
43f66a6c
JK		 441 u16 rssi_silence_threshold;
442 u16 rx_ovfl_frame_supplied;
bf79451e
JG		 443 u16 last_rx_frame_signal;
444 u16 last_rx_frame_noise;
445 u16 rx_autodetec_no_ofdm;
43f66a6c
JK		 446 u16 rx_autodetec_no_barker;
447 u16 reserved;
448} __attribute__ ((packed));
449
450struct notif_channel_result {
451 u8 channel_num;
452 struct ipw_cmd_stats stats;
453 u8 uReserved;
454} __attribute__ ((packed));
455
456struct notif_scan_complete {
457 u8 scan_type;
458 u8 num_channels;
459 u8 status;
460 u8 reserved;
0edd5b44 461} __attribute__ ((packed));
43f66a6c
JK		 462
463struct notif_frag_length {
464 u16 frag_length;
465 u16 reserved;
0edd5b44 466} __attribute__ ((packed));
43f66a6c
JK		 467
468struct notif_beacon_state {
469 u32 state;
470 u32 number;
471} __attribute__ ((packed));
472
473struct notif_tgi_tx_key {
474 u8 key_state;
475 u8 security_type;
476 u8 station_index;
477 u8 reserved;
478} __attribute__ ((packed));
479
480struct notif_link_deterioration {
481 struct ipw_cmd_stats stats;
482 u8 rate;
483 u8 modulation;
484 struct rate_histogram histogram;
485 u8 reserved1;
486 u16 reserved2;
487} __attribute__ ((packed));
488
489struct notif_association {
490 u8 state;
491} __attribute__ ((packed));
492
493struct notif_authenticate {
494 u8 state;
495 struct machdr24 addr;
496 u16 status;
497} __attribute__ ((packed));
498
43f66a6c
JK		 499struct notif_calibration {
500 u8 data[104];
501} __attribute__ ((packed));
502
503struct notif_noise {
504 u32 value;
505} __attribute__ ((packed));
506
507struct ipw_rx_notification {
508 u8 reserved[8];
509 u8 subtype;
510 u8 flags;
511 u16 size;
512 union {
513 struct notif_association assoc;
514 struct notif_authenticate auth;
515 struct notif_channel_result channel_result;
516 struct notif_scan_complete scan_complete;
517 struct notif_frag_length frag_len;
518 struct notif_beacon_state beacon_state;
519 struct notif_tgi_tx_key tgi_tx_key;
520 struct notif_link_deterioration link_deterioration;
521 struct notif_calibration calibration;
522 struct notif_noise noise;
523 u8 raw[0];
524 } u;
525} __attribute__ ((packed));
526
527struct ipw_rx_frame {
bf79451e 528 u32 reserved1;
0edd5b44
JG		 529 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
530 u8 received_channel; // The channel that this frame was received on.
531 // Note that for .11b this does not have to be
532 // the same as the channel that it was sent.
533 // Filled by LMAC
43f66a6c
JK		 534 u8 frameStatus;
535 u8 rate;
536 u8 rssi;
537 u8 agc;
538 u8 rssi_dbm;
539 u16 signal;
540 u16 noise;
541 u8 antennaAndPhy;
0edd5b44
JG		 542 u8 control; // control bit should be on in bg
543 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
544 // is identical)
545 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
43f66a6c
JK		 546 u16 length;
547 u8 data[0];
548} __attribute__ ((packed));
bf79451e 549
43f66a6c
JK		 550struct ipw_rx_header {
551 u8 message_type;
552 u8 rx_seq_num;
553 u8 control_bits;
554 u8 reserved;
555} __attribute__ ((packed));
556
0edd5b44 557struct ipw_rx_packet {
43f66a6c
JK		 558 struct ipw_rx_header header;
559 union {
560 struct ipw_rx_frame frame;
561 struct ipw_rx_notification notification;
562 } u;
563} __attribute__ ((packed));
564
565#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
566#define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
567 sizeof(struct ipw_rx_frame)
568
569struct ipw_rx_mem_buffer {
570 dma_addr_t dma_addr;
571 struct ipw_rx_buffer *rxb;
572 struct sk_buff *skb;
573 struct list_head list;
0edd5b44 574}; /* Not transferred over network, so not __attribute__ ((packed)) */
43f66a6c
JK		 575
576struct ipw_rx_queue {
577 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
578 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
0edd5b44
JG		 579 u32 processed; /* Internal index to last handled Rx packet */
580 u32 read; /* Shared index to newest available Rx buffer */
581 u32 write; /* Shared index to oldest written Rx packet */
582 u32 free_count; /* Number of pre-allocated buffers in rx_free */
43f66a6c 583 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
0edd5b44
JG		 584 struct list_head rx_free; /* Own an SKBs */
585 struct list_head rx_used; /* No SKB allocated */
43f66a6c 586 spinlock_t lock;
0edd5b44 587}; /* Not transferred over network, so not __attribute__ ((packed)) */
43f66a6c
JK		 588
589struct alive_command_responce {
590 u8 alive_command;
591 u8 sequence_number;
592 u16 software_revision;
593 u8 device_identifier;
594 u8 reserved1[5];
595 u16 reserved2;
596 u16 reserved3;
597 u16 clock_settle_time;
598 u16 powerup_settle_time;
599 u16 reserved4;
600 u8 time_stamp[5]; /* month, day, year, hours, minutes */
601 u8 ucode_valid;
602} __attribute__ ((packed));
603
604#define IPW_MAX_RATES 12
605
606struct ipw_rates {
607 u8 num_rates;
608 u8 rates[IPW_MAX_RATES];
609} __attribute__ ((packed));
610
0edd5b44 611struct command_block {
43f66a6c
JK		 612 unsigned int control;
613 u32 source_addr;
614 u32 dest_addr;
615 unsigned int status;
616} __attribute__ ((packed));
617
618#define CB_NUMBER_OF_ELEMENTS_SMALL 64
0edd5b44 619struct fw_image_desc {
43f66a6c
JK		 620 unsigned long last_cb_index;
621 unsigned long current_cb_index;
622 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
0edd5b44 623 void *v_addr;
43f66a6c
JK		 624 unsigned long p_addr;
625 unsigned long len;
626};
627
0edd5b44 628struct ipw_sys_config {
43f66a6c
JK		 629 u8 bt_coexistence;
630 u8 reserved1;
631 u8 answer_broadcast_ssid_probe;
632 u8 accept_all_data_frames;
633 u8 accept_non_directed_frames;
634 u8 exclude_unicast_unencrypted;
635 u8 disable_unicast_decryption;
636 u8 exclude_multicast_unencrypted;
637 u8 disable_multicast_decryption;
638 u8 antenna_diversity;
639 u8 pass_crc_to_host;
640 u8 dot11g_auto_detection;
641 u8 enable_cts_to_self;
642 u8 enable_multicast_filtering;
643 u8 bt_coexist_collision_thr;
644 u8 reserved2;
645 u8 accept_all_mgmt_bcpr;
646 u8 accept_all_mgtm_frames;
647 u8 pass_noise_stats_to_host;
648 u8 reserved3;
649} __attribute__ ((packed));
650
0edd5b44 651struct ipw_multicast_addr {
43f66a6c
JK		 652 u8 num_of_multicast_addresses;
653 u8 reserved[3];
654 u8 mac1[6];
655 u8 mac2[6];
656 u8 mac3[6];
657 u8 mac4[6];
658} __attribute__ ((packed));
659
0edd5b44 660struct ipw_wep_key {
43f66a6c
JK		 661 u8 cmd_id;
662 u8 seq_num;
663 u8 key_index;
664 u8 key_size;
665 u8 key[16];
666} __attribute__ ((packed));
667
0edd5b44 668struct ipw_tgi_tx_key {
bf79451e 669 u8 key_id;
43f66a6c
JK		 670 u8 security_type;
671 u8 station_index;
672 u8 flags;
673 u8 key[16];
674 u32 tx_counter[2];
675} __attribute__ ((packed));
676
677#define IPW_SCAN_CHANNELS 54
678
0edd5b44 679struct ipw_scan_request {
43f66a6c
JK		 680 u8 scan_type;
681 u16 dwell_time;
682 u8 channels_list[IPW_SCAN_CHANNELS];
683 u8 channels_reserved[3];
684} __attribute__ ((packed));
685
686enum {
687 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
688 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
689 IPW_SCAN_ACTIVE_DIRECT_SCAN,
690 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
691 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
692 IPW_SCAN_TYPES
693};
694
0edd5b44 695struct ipw_scan_request_ext {
43f66a6c
JK		 696 u32 full_scan_index;
697 u8 channels_list[IPW_SCAN_CHANNELS];
698 u8 scan_type[IPW_SCAN_CHANNELS / 2];
699 u8 reserved;
700 u16 dwell_time[IPW_SCAN_TYPES];
701} __attribute__ ((packed));
702
bf79451e 703extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
43f66a6c
JK		 704{
705 if (index % 2)
706 return scan->scan_type[index / 2] & 0x0F;
707 else
708 return (scan->scan_type[index / 2] & 0xF0) >> 4;
709}
710
bf79451e 711extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
43f66a6c
JK		 712 u8 index, u8 scan_type)
713{
bf79451e
JG		 714 if (index % 2)
715 scan->scan_type[index / 2] =
0edd5b44 716 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
43f66a6c 717 else
bf79451e 718 scan->scan_type[index / 2] =
0edd5b44
JG		 719 (scan->scan_type[index / 2] & 0x0F) |
720 ((scan_type & 0x0F) << 4);
43f66a6c
JK		 721}
722
0edd5b44 723struct ipw_associate {
43f66a6c 724 u8 channel;
0edd5b44 725 u8 auth_type:4, auth_key:4;
43f66a6c
JK		 726 u8 assoc_type;
727 u8 reserved;
728 u16 policy_support;
729 u8 preamble_length;
730 u8 ieee_mode;
731 u8 bssid[ETH_ALEN];
732 u32 assoc_tsf_msw;
733 u32 assoc_tsf_lsw;
734 u16 capability;
735 u16 listen_interval;
736 u16 beacon_interval;
737 u8 dest[ETH_ALEN];
738 u16 atim_window;
739 u8 smr;
740 u8 reserved1;
741 u16 reserved2;
742} __attribute__ ((packed));
743
0edd5b44 744struct ipw_supported_rates {
43f66a6c
JK		 745 u8 ieee_mode;
746 u8 num_rates;
747 u8 purpose;
748 u8 reserved;
749 u8 supported_rates[IPW_MAX_RATES];
750} __attribute__ ((packed));
751
0edd5b44 752struct ipw_rts_threshold {
43f66a6c
JK		 753 u16 rts_threshold;
754 u16 reserved;
755} __attribute__ ((packed));
756
0edd5b44 757struct ipw_frag_threshold {
43f66a6c
JK		 758 u16 frag_threshold;
759 u16 reserved;
760} __attribute__ ((packed));
761
0edd5b44 762struct ipw_retry_limit {
43f66a6c
JK		 763 u8 short_retry_limit;
764 u8 long_retry_limit;
765 u16 reserved;
766} __attribute__ ((packed));
767
0edd5b44 768struct ipw_dino_config {
43f66a6c
JK		 769 u32 dino_config_addr;
770 u16 dino_config_size;
771 u8 dino_response;
772 u8 reserved;
773} __attribute__ ((packed));
774
0edd5b44 775struct ipw_aironet_info {
43f66a6c
JK		 776 u8 id;
777 u8 length;
778 u16 reserved;
779} __attribute__ ((packed));
780
0edd5b44 781struct ipw_rx_key {
43f66a6c
JK		 782 u8 station_index;
783 u8 key_type;
784 u8 key_id;
785 u8 key_flag;
786 u8 key[16];
787 u8 station_address[6];
788 u8 key_index;
789 u8 reserved;
790} __attribute__ ((packed));
791
0edd5b44 792struct ipw_country_channel_info {
43f66a6c
JK		 793 u8 first_channel;
794 u8 no_channels;
795 s8 max_tx_power;
796} __attribute__ ((packed));
797
0edd5b44 798struct ipw_country_info {
43f66a6c
JK		 799 u8 id;
800 u8 length;
801 u8 country_str[3];
802 struct ipw_country_channel_info groups[7];
803} __attribute__ ((packed));
804
0edd5b44 805struct ipw_channel_tx_power {
43f66a6c
JK		 806 u8 channel_number;
807 s8 tx_power;
808} __attribute__ ((packed));
809
810#define SCAN_ASSOCIATED_INTERVAL (HZ)
811#define SCAN_INTERVAL (HZ / 10)
812#define MAX_A_CHANNELS 37
813#define MAX_B_CHANNELS 14
814
0edd5b44 815struct ipw_tx_power {
43f66a6c
JK		 816 u8 num_channels;
817 u8 ieee_mode;
818 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
819} __attribute__ ((packed));
820
0edd5b44 821struct ipw_qos_parameters {
43f66a6c
JK		 822 u16 cw_min[4];
823 u16 cw_max[4];
824 u8 aifs[4];
825 u8 flag[4];
826 u16 tx_op_limit[4];
827} __attribute__ ((packed));
828
0edd5b44 829struct ipw_rsn_capabilities {
43f66a6c
JK		 830 u8 id;
831 u8 length;
832 u16 version;
833} __attribute__ ((packed));
834
0edd5b44 835struct ipw_sensitivity_calib {
43f66a6c
JK		 836 u16 beacon_rssi_raw;
837 u16 reserved;
838} __attribute__ ((packed));
839
840/**
841 * Host command structure.
bf79451e 842 *
43f66a6c
JK		 843 * On input, the following fields should be filled:
844 * - cmd
845 * - len
846 * - status_len
847 * - param (if needed)
bf79451e
JG		 848 *
849 * On output,
43f66a6c
JK		 850 * - \a status contains status;
851 * - \a param filled with status parameters.
852 */
853struct ipw_cmd {
0edd5b44
JG		 854 u32 cmd; /**< Host command */
855 u32 status;/**< Status */
856 u32 status_len;
857 /**< How many 32 bit parameters in the status */
858 u32 len; /**< incoming parameters length, bytes */
43f66a6c 859 /**
bf79451e
JG		 860 * command parameters.
861 * There should be enough space for incoming and
43f66a6c
JK		 862 * outcoming parameters.
863 * Incoming parameters listed 1-st, followed by outcoming params.
864 * nParams=(len+3)/4+status_len
865 */
0edd5b44 866 u32 param[0];
43f66a6c
JK		 867} __attribute__ ((packed));
868
0edd5b44 869#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
43f66a6c
JK		 870
871#define STATUS_INT_ENABLED (1<<1)
872#define STATUS_RF_KILL_HW (1<<2)
873#define STATUS_RF_KILL_SW (1<<3)
874#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
875
876#define STATUS_INIT (1<<5)
877#define STATUS_AUTH (1<<6)
878#define STATUS_ASSOCIATED (1<<7)
879#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
880
881#define STATUS_ASSOCIATING (1<<8)
882#define STATUS_DISASSOCIATING (1<<9)
883#define STATUS_ROAMING (1<<10)
884#define STATUS_EXIT_PENDING (1<<11)
885#define STATUS_DISASSOC_PENDING (1<<12)
886#define STATUS_STATE_PENDING (1<<13)
887
888#define STATUS_SCAN_PENDING (1<<20)
bf79451e
JG		 889#define STATUS_SCANNING (1<<21)
890#define STATUS_SCAN_ABORTING (1<<22)
43f66a6c 891
0edd5b44
JG		 892#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
893#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
894#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
43f66a6c 895
0edd5b44 896#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
43f66a6c 897
0edd5b44
JG		 898#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
899#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
900#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
43f66a6c
JK		 901#define CFG_CUSTOM_MAC (1<<3)
902#define CFG_PREAMBLE (1<<4)
903#define CFG_ADHOC_PERSIST (1<<5)
904#define CFG_ASSOCIATE (1<<6)
905#define CFG_FIXED_RATE (1<<7)
906#define CFG_ADHOC_CREATE (1<<8)
907
0edd5b44
JG		 908#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
909#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
43f66a6c
JK		 910
911#define MAX_STATIONS 32
912#define IPW_INVALID_STATION (0xff)
913
914struct ipw_station_entry {
915 u8 mac_addr[ETH_ALEN];
916 u8 reserved;
917 u8 support_mode;
918};
919
920#define AVG_ENTRIES 8
921struct average {
922 s16 entries[AVG_ENTRIES];
923 u8 pos;
924 u8 init;
925 s32 sum;
926};
927
928struct ipw_priv {
929 /* ieee device used by generic ieee processing code */
930 struct ieee80211_device *ieee;
931 struct ieee80211_security sec;
932
933 /* spinlock */
934 spinlock_t lock;
935
936 /* basic pci-network driver stuff */
937 struct pci_dev *pci_dev;
938 struct net_device *net_dev;
939
940 /* pci hardware address support */
941 void __iomem *hw_base;
942 unsigned long hw_len;
bf79451e 943
43f66a6c
JK		 944 struct fw_image_desc sram_desc;
945
946 /* result of ucode download */
947 struct alive_command_responce dino_alive;
948
0edd5b44
JG		 949 wait_queue_head_t wait_command_queue;
950 wait_queue_head_t wait_state;
43f66a6c
JK		 951
952 /* Rx and Tx DMA processing queues */
953 struct ipw_rx_queue *rxq;
954 struct clx2_tx_queue txq_cmd;
955 struct clx2_tx_queue txq[4];
956 u32 status;
957 u32 config;
958 u32 capability;
959
960 u8 last_rx_rssi;
961 u8 last_noise;
962 struct average average_missed_beacons;
963 struct average average_rssi;
964 struct average average_noise;
965 u32 port_type;
0edd5b44
JG		 966 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
967 int rx_pend_max; /**< maximum pending buffers for one IRQ */
968 u32 hcmd_seq; /**< sequence number for hcmd */
43f66a6c 969 u32 missed_beacon_threshold;
bf79451e 970 u32 roaming_threshold;
43f66a6c
JK		 971
972 struct ipw_associate assoc_request;
973 struct ieee80211_network *assoc_network;
974
975 unsigned long ts_scan_abort;
976 struct ipw_supported_rates rates;
0edd5b44
JG		 977 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
978 struct ipw_rates supp; /**< software defined */
979 struct ipw_rates extended; /**< use for corresp. IE, AP only */
43f66a6c
JK		 980
981 struct notif_link_deterioration last_link_deterioration; /** for statistics */
0edd5b44 982 struct ipw_cmd *hcmd; /**< host command currently executed */
43f66a6c
JK		 983
984 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
0edd5b44 985 u32 tsf_bcn[2]; /**< TSF from latest beacon */
43f66a6c 986
0edd5b44 987 struct notif_calibration calib; /**< last calibration */
43f66a6c
JK		 988
989 /* ordinal interface with firmware */
990 u32 table0_addr;
991 u32 table0_len;
992 u32 table1_addr;
993 u32 table1_len;
994 u32 table2_addr;
995 u32 table2_len;
996
997 /* context information */
998 u8 essid[IW_ESSID_MAX_SIZE];
999 u8 essid_len;
1000 u8 nick[IW_ESSID_MAX_SIZE];
1001 u16 rates_mask;
1002 u8 channel;
1003 struct ipw_sys_config sys_config;
1004 u32 power_mode;
bf79451e 1005 u8 bssid[ETH_ALEN];
43f66a6c
JK		 1006 u16 rts_threshold;
1007 u8 mac_addr[ETH_ALEN];
1008 u8 num_stations;
bf79451e 1009 u8 stations[MAX_STATIONS][ETH_ALEN];
43f66a6c
JK		 1010
1011 u32 notif_missed_beacons;
1012
1013 /* Statistics and counters normalized with each association */
1014 u32 last_missed_beacons;
1015 u32 last_tx_packets;
1016 u32 last_rx_packets;
1017 u32 last_tx_failures;
1018 u32 last_rx_err;
1019 u32 last_rate;
1020
1021 u32 missed_adhoc_beacons;
1022 u32 missed_beacons;
1023 u32 rx_packets;
1024 u32 tx_packets;
1025 u32 quality;
1026
0edd5b44
JG		 1027 /* eeprom */
1028 u8 eeprom[0x100]; /* 256 bytes of eeprom */
43f66a6c
JK		 1029 int eeprom_delay;
1030
bf79451e 1031 struct iw_statistics wstats;
43f66a6c
JK		 1032
1033 struct workqueue_struct *workqueue;
bf79451e 1034
43f66a6c
JK		 1035 struct work_struct adhoc_check;
1036 struct work_struct associate;
1037 struct work_struct disassociate;
1038 struct work_struct rx_replenish;
1039 struct work_struct request_scan;
1040 struct work_struct adapter_restart;
1041 struct work_struct rf_kill;
1042 struct work_struct up;
1043 struct work_struct down;
1044 struct work_struct gather_stats;
1045 struct work_struct abort_scan;
1046 struct work_struct roam;
1047 struct work_struct scan_check;
1048
1049 struct tasklet_struct irq_tasklet;
1050
43f66a6c
JK		 1051#define IPW_2200BG 1
1052#define IPW_2915ABG 2
1053 u8 adapter;
1054
1055#define IPW_DEFAULT_TX_POWER 0x14
1056 u8 tx_power;
1057
bf79451e 1058#ifdef CONFIG_PM
43f66a6c
JK		 1059 u32 pm_state[16];
1060#endif
1061
1062 /* network state */
1063
1064 /* Used to pass the current INTA value from ISR to Tasklet */
1065 u32 isr_inta;
1066
1067 /* debugging info */
1068 u32 indirect_dword;
1069 u32 direct_dword;
1070 u32 indirect_byte;
1071}; /*ipw_priv */
1072
43f66a6c
JK		 1073/* debug macros */
1074
1075#ifdef CONFIG_IPW_DEBUG
1076#define IPW_DEBUG(level, fmt, args...) \
1077do { if (ipw_debug_level & (level)) \
1078 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1079 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1080#else
1081#define IPW_DEBUG(level, fmt, args...) do {} while (0)
1082#endif /* CONFIG_IPW_DEBUG */
1083
1084/*
1085 * To use the debug system;
1086 *
1087 * If you are defining a new debug classification, simply add it to the #define
1088 * list here in the form of:
1089 *
1090 * #define IPW_DL_xxxx VALUE
bf79451e 1091 *
43f66a6c
JK		 1092 * shifting value to the left one bit from the previous entry. xxxx should be
1093 * the name of the classification (for example, WEP)
1094 *
1095 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1096 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1097 * to send output to that classification.
1098 *
1099 * To add your debug level to the list of levels seen when you perform
1100 *
1101 * % cat /proc/net/ipw/debug_level
1102 *
1103 * you simply need to add your entry to the ipw_debug_levels array.
1104 *
bf79451e 1105 * If you do not see debug_level in /proc/net/ipw then you do not have
43f66a6c
JK		 1106 * CONFIG_IPW_DEBUG defined in your kernel configuration
1107 *
1108 */
1109
1110#define IPW_DL_ERROR (1<<0)
1111#define IPW_DL_WARNING (1<<1)
1112#define IPW_DL_INFO (1<<2)
1113#define IPW_DL_WX (1<<3)
1114#define IPW_DL_HOST_COMMAND (1<<5)
1115#define IPW_DL_STATE (1<<6)
1116
1117#define IPW_DL_NOTIF (1<<10)
1118#define IPW_DL_SCAN (1<<11)
1119#define IPW_DL_ASSOC (1<<12)
1120#define IPW_DL_DROP (1<<13)
1121#define IPW_DL_IOCTL (1<<14)
1122
1123#define IPW_DL_MANAGE (1<<15)
1124#define IPW_DL_FW (1<<16)
1125#define IPW_DL_RF_KILL (1<<17)
1126#define IPW_DL_FW_ERRORS (1<<18)
1127
43f66a6c
JK		 1128#define IPW_DL_ORD (1<<20)
1129
1130#define IPW_DL_FRAG (1<<21)
1131#define IPW_DL_WEP (1<<22)
1132#define IPW_DL_TX (1<<23)
1133#define IPW_DL_RX (1<<24)
1134#define IPW_DL_ISR (1<<25)
1135#define IPW_DL_FW_INFO (1<<26)
1136#define IPW_DL_IO (1<<27)
1137#define IPW_DL_TRACE (1<<28)
1138
1139#define IPW_DL_STATS (1<<29)
1140
43f66a6c
JK		 1141#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1142#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1143#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1144
1145#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1146#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1147#define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1148#define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1149#define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1150#define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1151#define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1152#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1153#define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1154#define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1155#define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1156#define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1157#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1158#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1159#define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1160#define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1161#define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1162#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1163#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1164#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1165#define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1166
1167#include <linux/ctype.h>
1168
1169/*
1170* Register bit definitions
1171*/
1172
1173/* Dino control registers bits */
1174
1175#define DINO_ENABLE_SYSTEM 0x80
1176#define DINO_ENABLE_CS 0x40
bf79451e 1177#define DINO_RXFIFO_DATA 0x01
43f66a6c
JK		 1178#define DINO_CONTROL_REG 0x00200000
1179
1180#define CX2_INTA_RW 0x00000008
1181#define CX2_INTA_MASK_R 0x0000000C
1182#define CX2_INDIRECT_ADDR 0x00000010
1183#define CX2_INDIRECT_DATA 0x00000014
1184#define CX2_AUTOINC_ADDR 0x00000018
1185#define CX2_AUTOINC_DATA 0x0000001C
1186#define CX2_RESET_REG 0x00000020
1187#define CX2_GP_CNTRL_RW 0x00000024
1188
1189#define CX2_READ_INT_REGISTER 0xFF4
1190
1191#define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1192
1193#define CX2_REGISTER_DOMAIN1_END 0x00001000
1194#define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1195
1196#define CX2_SHARED_LOWER_BOUND 0x00000200
1197#define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1198
1199#define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1200#define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1201
1202#define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1203#define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1204#define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1205
1206/*
1207 * RESET Register Bit Indexes
1208 */
0edd5b44
JG		 1209#define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */
1210#define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */
1211#define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */
1212#define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */
1213#define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */
1214#define CX2_START_STANDBY 0x00000004 /* Bit 2 */
43f66a6c
JK		 1215
1216#define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1217#define CX2_DOMAIN_0_END 0x1000
1218#define CLX_MEM_BAR_SIZE 0x1000
1219
1220#define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1221#define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1222#define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1223#define CX2_BASEBAND_CONTROL_STORE 0X00200010
1224
1225#define CX2_INTERNAL_CMD_EVENT 0X00300004
1226#define CX2_BASEBAND_POWER_DOWN 0x00000001
1227
1228#define CX2_MEM_HALT_AND_RESET 0x003000e0
1229
1230/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1231#define CX2_BIT_HALT_RESET_ON 0x80000000
1232#define CX2_BIT_HALT_RESET_OFF 0x00000000
1233
1234#define CB_LAST_VALID 0x20000000
1235#define CB_INT_ENABLED 0x40000000
1236#define CB_VALID 0x80000000
1237#define CB_SRC_LE 0x08000000
1238#define CB_DEST_LE 0x04000000
1239#define CB_SRC_AUTOINC 0x00800000
1240#define CB_SRC_IO_GATED 0x00400000
1241#define CB_DEST_AUTOINC 0x00080000
1242#define CB_SRC_SIZE_LONG 0x00200000
1243#define CB_DEST_SIZE_LONG 0x00020000
1244
43f66a6c
JK		 1245/* DMA DEFINES */
1246
1247#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1248#define DMA_CB_STOP_AND_ABORT 0x00000C00
bf79451e 1249#define DMA_CB_START 0x00000100
43f66a6c 1250
43f66a6c
JK		 1251#define CX2_SHARED_SRAM_SIZE 0x00030000
1252#define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1253#define CB_MAX_LENGTH 0x1FFF
1254
1255#define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1256#define CX2_EEPROM_IMAGE_SIZE 0x100
1257
43f66a6c
JK		 1258/* DMA defs */
1259#define CX2_DMA_I_CURRENT_CB 0x003000D0
1260#define CX2_DMA_O_CURRENT_CB 0x003000D4
1261#define CX2_DMA_I_DMA_CONTROL 0x003000A4
1262#define CX2_DMA_I_CB_BASE 0x003000A0
1263
1264#define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
1265#define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
1266#define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
1267#define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
1268#define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
1269#define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
1270#define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
1271#define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
1272#define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
1273#define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
1274#define CX2_RX_BD_BASE (0x00000240)
1275#define CX2_RX_BD_SIZE (0x00000244)
1276#define CX2_RFDS_TABLE_LOWER (0x00000500)
1277
1278#define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
1279#define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
1280#define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
1281#define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
1282#define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
1283#define CX2_RX_READ_INDEX (0x000002A0)
1284
1285#define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1286#define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1287#define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1288#define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1289#define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1290#define CX2_RX_WRITE_INDEX (0x00000FA0)
1291
1292/*
1293 * EEPROM Related Definitions
1294 */
1295
1296#define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1297#define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1298#define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1299#define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1300#define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1301
1302#define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1303#define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1304#define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1305#define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1306#define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1307#define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1308
43f66a6c
JK		 1309#define MSB 1
1310#define LSB 0
1311#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1312
1313#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1314 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1315
1316/* EEPROM access by BYTE */
0edd5b44
JG		 1317#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1318#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1319#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1320#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1321#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1322#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1323#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1324#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1325#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1326#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
43f66a6c
JK		 1327
1328/* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1329#define EEPROM_NIC_TYPE_STANDARD 0
1330#define EEPROM_NIC_TYPE_DELL 1
1331#define EEPROM_NIC_TYPE_FUJITSU 2
1332#define EEPROM_NIC_TYPE_IBM 3
1333#define EEPROM_NIC_TYPE_HP 4
1334
1335#define FW_MEM_REG_LOWER_BOUND 0x00300000
bf79451e 1336#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
43f66a6c
JK		 1337
1338#define EEPROM_BIT_SK (1<<0)
1339#define EEPROM_BIT_CS (1<<1)
1340#define EEPROM_BIT_DI (1<<2)
1341#define EEPROM_BIT_DO (1<<4)
1342
1343#define EEPROM_CMD_READ 0x2
1344
1345/* Interrupts masks */
1346#define CX2_INTA_NONE 0x00000000
1347
1348#define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1349#define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1350#define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1351
1352//Inta Bits for CF
1353#define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1354#define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1355#define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1356#define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1357#define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1358
1359#define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1360
1361#define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1362#define CX2_INTA_BIT_POWER_DOWN 0x00200000
1363
1364#define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1365#define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1366#define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1367#define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1368#define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1369
1370/* Interrupts enabled at init time. */
1371#define CX2_INTA_MASK_ALL \
1372 (CX2_INTA_BIT_TX_QUEUE_1 | \
1373 CX2_INTA_BIT_TX_QUEUE_2 | \
1374 CX2_INTA_BIT_TX_QUEUE_3 | \
1375 CX2_INTA_BIT_TX_QUEUE_4 | \
1376 CX2_INTA_BIT_TX_CMD_QUEUE | \
1377 CX2_INTA_BIT_RX_TRANSFER | \
1378 CX2_INTA_BIT_FATAL_ERROR | \
1379 CX2_INTA_BIT_PARITY_ERROR | \
1380 CX2_INTA_BIT_STATUS_CHANGE | \
1381 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1382 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1383 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1384 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1385 CX2_INTA_BIT_POWER_DOWN | \
1386 CX2_INTA_BIT_RF_KILL_DONE )
1387
1388#define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1389#define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1390
1391/* FW event log definitions */
1392#define EVENT_ELEM_SIZE (3 * sizeof(u32))
1393#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1394
1395/* FW error log definitions */
1396#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1397#define ERROR_START_OFFSET (1 * sizeof(u32))
1398
1399enum {
1400 IPW_FW_ERROR_OK = 0,
1401 IPW_FW_ERROR_FAIL,
1402 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1403 IPW_FW_ERROR_MEMORY_OVERFLOW,
1404 IPW_FW_ERROR_BAD_PARAM,
1405 IPW_FW_ERROR_BAD_CHECKSUM,
1406 IPW_FW_ERROR_NMI_INTERRUPT,
1407 IPW_FW_ERROR_BAD_DATABASE,
1408 IPW_FW_ERROR_ALLOC_FAIL,
1409 IPW_FW_ERROR_DMA_UNDERRUN,
1410 IPW_FW_ERROR_DMA_STATUS,
1411 IPW_FW_ERROR_DINOSTATUS_ERROR,
1412 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1413 IPW_FW_ERROR_SYSASSERT,
1414 IPW_FW_ERROR_FATAL_ERROR
1415};
1416
1417#define AUTH_OPEN 0
1418#define AUTH_SHARED_KEY 1
1419#define AUTH_IGNORE 3
1420
1421#define HC_ASSOCIATE 0
1422#define HC_REASSOCIATE 1
1423#define HC_DISASSOCIATE 2
1424#define HC_IBSS_START 3
1425#define HC_IBSS_RECONF 4
1426#define HC_DISASSOC_QUIET 5
1427
1428#define IPW_RATE_CAPABILITIES 1
1429#define IPW_RATE_CONNECT 0
1430
bf79451e
JG		 1431/*
1432 * Rate values and masks
43f66a6c
JK		 1433 */
1434#define IPW_TX_RATE_1MB 0x0A
1435#define IPW_TX_RATE_2MB 0x14
1436#define IPW_TX_RATE_5MB 0x37
1437#define IPW_TX_RATE_6MB 0x0D
1438#define IPW_TX_RATE_9MB 0x0F
bf79451e 1439#define IPW_TX_RATE_11MB 0x6E
43f66a6c
JK		 1440#define IPW_TX_RATE_12MB 0x05
1441#define IPW_TX_RATE_18MB 0x07
1442#define IPW_TX_RATE_24MB 0x09
1443#define IPW_TX_RATE_36MB 0x0B
1444#define IPW_TX_RATE_48MB 0x01
1445#define IPW_TX_RATE_54MB 0x03
1446
1447#define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1448#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1449
bf79451e
JG		 1450#define IPW_ORD_TABLE_0_MASK 0x0000F000
1451#define IPW_ORD_TABLE_1_MASK 0x0000F100
1452#define IPW_ORD_TABLE_2_MASK 0x0000F200
1453#define IPW_ORD_TABLE_3_MASK 0x0000F300
1454#define IPW_ORD_TABLE_4_MASK 0x0000F400
1455#define IPW_ORD_TABLE_5_MASK 0x0000F500
1456#define IPW_ORD_TABLE_6_MASK 0x0000F600
1457#define IPW_ORD_TABLE_7_MASK 0x0000F700
43f66a6c
JK		 1458
1459/*
1460 * Table 0 Entries (all entries are 32 bits)
1461 */
bf79451e 1462enum {
43f66a6c
JK		 1463 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1464 IPW_ORD_STAT_FRAG_TRESHOLD,
1465 IPW_ORD_STAT_RTS_THRESHOLD,
bf79451e
JG		 1466 IPW_ORD_STAT_TX_HOST_REQUESTS,
1467 IPW_ORD_STAT_TX_HOST_COMPLETE,
1468 IPW_ORD_STAT_TX_DIR_DATA,
43f66a6c
JK		 1469 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1470 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1471 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1472 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1473 /* Hole */
1474
43f66a6c
JK		 1475 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1476 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1477 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1478 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1479 IPW_ORD_STAT_TX_DIR_DATA_G_9,
bf79451e 1480 IPW_ORD_STAT_TX_DIR_DATA_G_11,
43f66a6c
JK		 1481 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1482 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1483 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1484 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1485 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1486 IPW_ORD_STAT_TX_DIR_DATA_G_54,
bf79451e 1487 IPW_ORD_STAT_TX_NON_DIR_DATA,
43f66a6c
JK		 1488 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1489 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1490 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
bf79451e 1491 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
43f66a6c
JK		 1492 /* Hole */
1493
43f66a6c
JK		 1494 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1495 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1496 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1497 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1498 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
bf79451e 1499 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
43f66a6c
JK		 1500 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1501 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1502 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1503 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1504 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1505 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1506 IPW_ORD_STAT_TX_RETRY,
1507 IPW_ORD_STAT_TX_FAILURE,
1508 IPW_ORD_STAT_RX_ERR_CRC,
1509 IPW_ORD_STAT_RX_ERR_ICV,
1510 IPW_ORD_STAT_RX_NO_BUFFER,
1511 IPW_ORD_STAT_FULL_SCANS,
1512 IPW_ORD_STAT_PARTIAL_SCANS,
1513 IPW_ORD_STAT_TGH_ABORTED_SCANS,
bf79451e 1514 IPW_ORD_STAT_TX_TOTAL_BYTES,
43f66a6c
JK		 1515 IPW_ORD_STAT_CURR_RSSI_RAW,
1516 IPW_ORD_STAT_RX_BEACON,
1517 IPW_ORD_STAT_MISSED_BEACONS,
bf79451e
JG		 1518 IPW_ORD_TABLE_0_LAST
1519};
43f66a6c
JK		 1520
1521#define IPW_RSSI_TO_DBM 112
1522
1523/* Table 1 Entries
1524 */
1525enum {
1526 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1527};
1528
1529/*
1530 * Table 2 Entries
1531 *
1532 * FW_VERSION: 16 byte string
1533 * FW_DATE: 16 byte string (only 14 bytes used)
1534 * UCODE_VERSION: 4 byte version code
1535 * UCODE_DATE: 5 bytes code code
1536 * ADDAPTER_MAC: 6 byte MAC address
1537 * RTC: 4 byte clock
1538 */
bf79451e 1539enum {
43f66a6c 1540 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
bf79451e 1541 IPW_ORD_STAT_FW_DATE,
43f66a6c 1542 IPW_ORD_STAT_UCODE_VERSION,
bf79451e
JG		 1543 IPW_ORD_STAT_UCODE_DATE,
1544 IPW_ORD_STAT_ADAPTER_MAC,
1545 IPW_ORD_STAT_RTC,
1546 IPW_ORD_TABLE_2_LAST
1547};
43f66a6c
JK		 1548
1549/* Table 3 */
1550enum {
1551 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1552 IPW_ORD_STAT_TX_PACKET_FAILURE,
1553 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1554 IPW_ORD_STAT_TX_PACKET_ABORTED,
1555 IPW_ORD_TABLE_3_LAST
1556};
1557
1558/* Table 4 */
1559enum {
1560 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1561};
1562
1563/* Table 5 */
1564enum {
1565 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1566 IPW_ORD_STAT_AP_ASSNS,
1567 IPW_ORD_STAT_ROAM,
1568 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1569 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1570 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1571 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1572 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1573 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1574 IPW_ORD_STAT_LINK_UP,
1575 IPW_ORD_STAT_LINK_DOWN,
1576 IPW_ORD_ANTENNA_DIVERSITY,
1577 IPW_ORD_CURR_FREQ,
1578 IPW_ORD_TABLE_5_LAST
1579};
1580
1581/* Table 6 */
1582enum {
1583 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1584 IPW_ORD_CURR_BSSID,
1585 IPW_ORD_CURR_SSID,
1586 IPW_ORD_TABLE_6_LAST
1587};
1588
1589/* Table 7 */
1590enum {
1591 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1592 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1593 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1594 IPW_ORD_STAT_CURR_RSSI_DBM,
1595 IPW_ORD_TABLE_7_LAST
1596};
1597
1598#define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1599#define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1600#define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1601#define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1602#define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1603
1604struct ipw_fixed_rate {
1605 u16 tx_rates;
1606 u16 reserved;
1607} __attribute__ ((packed));
1608
1609#define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1610
1611struct host_cmd {
1612 u8 cmd;
1613 u8 len;
1614 u16 reserved;
1615 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1616} __attribute__ ((packed));
1617
1618#define CFG_BT_COEXISTENCE_MIN 0x00
1619#define CFG_BT_COEXISTENCE_DEFER 0x02
1620#define CFG_BT_COEXISTENCE_KILL 0x04
1621#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1622#define CFG_BT_COEXISTENCE_OOB 0x10
1623#define CFG_BT_COEXISTENCE_MAX 0xFF
0edd5b44 1624#define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM */
43f66a6c
JK		 1625
1626#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1627#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1628#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1629
1630#define CFG_SYS_ANTENNA_BOTH 0x000
1631#define CFG_SYS_ANTENNA_A 0x001
1632#define CFG_SYS_ANTENNA_B 0x003
1633
1634/*
bf79451e 1635 * The definitions below were lifted off the ipw2100 driver, which only
43f66a6c 1636 * supports 'b' mode, so I'm sure these are not exactly correct.
bf79451e 1637 *
43f66a6c
JK		 1638 * Somebody fix these!!
1639 */
1640#define REG_MIN_CHANNEL 0
1641#define REG_MAX_CHANNEL 14
1642
1643#define REG_CHANNEL_MASK 0x00003FFF
1644#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1645
bf79451e
JG		 1646static const long ipw_frequencies[] = {
1647 2412, 2417, 2422, 2427,
1648 2432, 2437, 2442, 2447,
1649 2452, 2457, 2462, 2467,
1650 2472, 2484
43f66a6c
JK		 1651};
1652
1653#define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1654
1655#define IPW_MAX_CONFIG_RETRIES 10
1656
0dacca1f 1657static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr)
43f66a6c
JK		 1658{
1659 u32 retval;
1660 u16 fc;
1661
0dacca1f 1662 retval = sizeof(struct ieee80211_hdr_3addr);
43f66a6c
JK		 1663 fc = le16_to_cpu(hdr->frame_ctl);
1664
1665 /*
0edd5b44
JG		 1666 * Function ToDS FromDS
1667 * IBSS 0 0
1668 * To AP 1 0
1669 * From AP 0 1
1670 * WDS (bridge) 1 1
43f66a6c
JK		 1671 *
1672 * Only WDS frames use Address4 among them. --YZ
1673 */
1674 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1675 retval -= ETH_ALEN;
1676
1677 return retval;
1678}
1679
0edd5b44 1680#endif /* __ipw2200_h__ */
Linux 6.x block layer and io_uring tree(s)