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iwlwifi: support internal debug data collection for new devices
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
d962f9b1 83#include "fw/error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
fb12777a 91static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad
RJ		 92{
93#define PCI_DUMP_SIZE 64
94#define PREFIX_LEN 32
95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
96 struct pci_dev *pdev = trans_pcie->pci_dev;
97 u32 i, pos, alloc_size, *ptr, *buf;
98 char *prefix;
99
100 if (trans_pcie->pcie_dbg_dumped_once)
101 return;
102
103 /* Should be a multiple of 4 */
104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
105 /* Alloc a max size buffer */
106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
108 else
109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
110 buf = kmalloc(alloc_size, GFP_ATOMIC);
111 if (!buf)
112 return;
113 prefix = (char *)buf + alloc_size - PREFIX_LEN;
114
115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
116
117 /* Print wifi device registers */
118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
119 IWL_ERR(trans, "iwlwifi device config registers:\n");
120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
121 if (pci_read_config_dword(pdev, i, ptr))
122 goto err_read;
123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
124
125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
127 *ptr = iwl_read32(trans, i);
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
129
130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
131 if (pos) {
132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
134 if (pci_read_config_dword(pdev, pos + i, ptr))
135 goto err_read;
136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
137 32, 4, buf, i, 0);
138 }
139
140 /* Print parent device registers next */
141 if (!pdev->bus->self)
142 goto out;
143
144 pdev = pdev->bus->self;
145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
146
147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
148 pci_name(pdev));
149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
150 if (pci_read_config_dword(pdev, i, ptr))
151 goto err_read;
152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
153
154 /* Print root port AER registers */
155 pos = 0;
156 pdev = pcie_find_root_port(pdev);
157 if (pdev)
158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
159 if (pos) {
160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
161 pci_name(pdev));
162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
164 if (pci_read_config_dword(pdev, pos + i, ptr))
165 goto err_read;
166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
167 4, buf, i, 0);
168 }
f3402d6d 169 goto out;
a6d24fad
RJ		 170
171err_read:
172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
173 IWL_ERR(trans, "Read failed at 0x%X\n", i);
174out:
175 trans_pcie->pcie_dbg_dumped_once = 1;
176 kfree(buf);
177}
178
c2d20201
EG		 179static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
180{
181 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
182
183 if (!trans_pcie->fw_mon_page)
184 return;
185
186 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
187 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
188 __free_pages(trans_pcie->fw_mon_page,
189 get_order(trans_pcie->fw_mon_size));
190 trans_pcie->fw_mon_page = NULL;
191 trans_pcie->fw_mon_phys = 0;
192 trans_pcie->fw_mon_size = 0;
193}
194
96c285da 195static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 196{
197 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 198 struct page *page = NULL;
c2d20201 199 dma_addr_t phys;
96c285da 200 u32 size = 0;
c2d20201
EG		 201 u8 power;
202
96c285da
EG		 203 if (!max_power) {
204 /* default max_power is maximum */
205 max_power = 26;
206 } else {
207 max_power += 11;
208 }
209
210 if (WARN(max_power > 26,
211 "External buffer size for monitor is too big %d, check the FW TLV\n",
212 max_power))
213 return;
214
c2d20201
EG		 215 if (trans_pcie->fw_mon_page) {
216 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
217 trans_pcie->fw_mon_size,
218 DMA_FROM_DEVICE);
219 return;
220 }
221
222 phys = 0;
96c285da 223 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 224 int order;
225
226 size = BIT(power);
227 order = get_order(size);
228 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
229 order);
230 if (!page)
231 continue;
232
233 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
234 DMA_FROM_DEVICE);
235 if (dma_mapping_error(trans->dev, phys)) {
236 __free_pages(page, order);
553452e5 237 page = NULL;
c2d20201
EG		 238 continue;
239 }
240 IWL_INFO(trans,
241 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
242 size, order);
243 break;
244 }
245
40a76905 246 if (WARN_ON_ONCE(!page))
c2d20201
EG		 247 return;
248
96c285da
EG		 249 if (power != max_power)
250 IWL_ERR(trans,
251 "Sorry - debug buffer is only %luK while you requested %luK\n",
252 (unsigned long)BIT(power - 10),
253 (unsigned long)BIT(max_power - 10));
254
c2d20201
EG		 255 trans_pcie->fw_mon_page = page;
256 trans_pcie->fw_mon_phys = phys;
257 trans_pcie->fw_mon_size = size;
258}
259
a812cba9
AB		 260static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
261{
262 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
263 ((reg & 0x0000ffff) | (2 << 28)));
264 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
265}
266
267static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
268{
269 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
270 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
271 ((reg & 0x0000ffff) | (3 << 28)));
272}
273
ddaf5a5b 274static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 275{
66337b7c 276 if (trans->cfg->apmg_not_supported)
95411d04
AA		 277 return;
278
ddaf5a5b
JB		 279 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
280 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
281 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
282 ~APMG_PS_CTRL_MSK_PWR_SRC);
283 else
284 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
285 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
286 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 287}
288
af634bee
EG		 289/* PCI registers */
290#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 291
eda50cde 292void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 293{
20d3b647 294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 295 u16 lctl;
9180ac50 296 u16 cap;
af634bee 297
af634bee
EG		 298 /*
299 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
300 * Check if BIOS (or OS) enabled L1-ASPM on this device.
301 * If so (likely), disable L0S, so device moves directly L0->L1;
302 * costs negligible amount of power savings.
303 * If not (unlikely), enable L0S, so there is at least some
304 * power savings, even without L1.
305 */
7afe3705 306 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 307 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 308 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 309 else
af634bee 310 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 311 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 312
313 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
314 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 315 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
316 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
317 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 318}
319
a6c684ee
EG		 320/*
321 * Start up NIC's basic functionality after it has been reset
7afe3705 322 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 323 * NOTE: This does not load uCode nor start the embedded processor
324 */
7afe3705 325static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 326{
52b6e168
EG		 327 int ret;
328
a6c684ee
EG		 329 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
330
331 /*
332 * Use "set_bit" below rather than "write", to preserve any hardware
333 * bits already set by default after reset.
334 */
335
336 /* Disable L0S exit timer (platform NMI Work/Around) */
6e584873 337 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 338 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
339 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 340
341 /*
342 * Disable L0s without affecting L1;
343 * don't wait for ICH L0s (ICH bug W/A)
344 */
345 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 346 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 347
348 /* Set FH wait threshold to maximum (HW error during stress W/A) */
349 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
350
351 /*
352 * Enable HAP INTA (interrupt from management bus) to
353 * wake device's PCI Express link L1a -> L0s
354 */
355 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 356 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 357
7afe3705 358 iwl_pcie_apm_config(trans);
a6c684ee
EG		 359
360 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 361 if (trans->cfg->base_params->pll_cfg)
362 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is supported, e.g. iwl_write_prph()
373 * and accesses to uCode SRAM.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee 378 if (ret < 0) {
52b6e168
EG		 379 IWL_ERR(trans, "Failed to init the card\n");
380 return ret;
a6c684ee
EG		 381 }
382
2d93aee1
EG		 383 if (trans->cfg->host_interrupt_operation_mode) {
384 /*
385 * This is a bit of an abuse - This is needed for 7260 / 3160
386 * only check host_interrupt_operation_mode even if this is
387 * not related to host_interrupt_operation_mode.
388 *
389 * Enable the oscillator to count wake up time for L1 exit. This
390 * consumes slightly more power (100uA) - but allows to be sure
391 * that we wake up from L1 on time.
392 *
393 * This looks weird: read twice the same register, discard the
394 * value, set a bit, and yet again, read that same register
395 * just to discard the value. But that's the way the hardware
396 * seems to like it.
397 */
398 iwl_read_prph(trans, OSC_CLK);
399 iwl_read_prph(trans, OSC_CLK);
400 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
401 iwl_read_prph(trans, OSC_CLK);
402 iwl_read_prph(trans, OSC_CLK);
403 }
404
a6c684ee
EG		 405 /*
406 * Enable DMA clock and wait for it to stabilize.
407 *
3073d8c0
EH		 408 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
409 * bits do not disable clocks. This preserves any hardware
410 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 411 */
95411d04 412 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 413 iwl_write_prph(trans, APMG_CLK_EN_REG,
414 APMG_CLK_VAL_DMA_CLK_RQT);
415 udelay(20);
416
417 /* Disable L1-Active */
418 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
419 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
420
421 /* Clear the interrupt in APMG if the NIC is in RFKILL */
422 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
423 APMG_RTC_INT_STT_RFKILL);
424 }
889b1696 425
eb7ff77e 426 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 427
52b6e168 428 return 0;
a6c684ee
EG		 429}
430
a812cba9
AB		 431/*
432 * Enable LP XTAL to avoid HW bug where device may consume much power if
433 * FW is not loaded after device reset. LP XTAL is disabled by default
434 * after device HW reset. Do it only if XTAL is fed by internal source.
435 * Configure device's "persistence" mode to avoid resetting XTAL again when
436 * SHRD_HW_RST occurs in S3.
437 */
438static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
439{
440 int ret;
441 u32 apmg_gp1_reg;
442 u32 apmg_xtal_cfg_reg;
443 u32 dl_cfg_reg;
444
445 /* Force XTAL ON */
446 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
447 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
448
099a628b 449 iwl_pcie_sw_reset(trans);
a812cba9
AB		 450
451 /*
452 * Set "initialization complete" bit to move adapter from
453 * D0U* --> D0A* (powered-up active) state.
454 */
455 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
456
457 /*
458 * Wait for clock stabilization; once stabilized, access to
459 * device-internal resources is possible.
460 */
461 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
462 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
463 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
464 25000);
465 if (WARN_ON(ret < 0)) {
466 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
467 /* Release XTAL ON request */
468 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
469 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
470 return;
471 }
472
473 /*
474 * Clear "disable persistence" to avoid LP XTAL resetting when
475 * SHRD_HW_RST is applied in S3.
476 */
477 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
478 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
479
480 /*
481 * Force APMG XTAL to be active to prevent its disabling by HW
482 * caused by APMG idle state.
483 */
484 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
485 SHR_APMG_XTAL_CFG_REG);
486 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
487 apmg_xtal_cfg_reg |
488 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
489
099a628b 490 iwl_pcie_sw_reset(trans);
a812cba9
AB		 491
492 /* Enable LP XTAL by indirect access through CSR */
493 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
494 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
495 SHR_APMG_GP1_WF_XTAL_LP_EN |
496 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
497
498 /* Clear delay line clock power up */
499 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
500 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
501 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
502
503 /*
504 * Enable persistence mode to avoid LP XTAL resetting when
505 * SHRD_HW_RST is applied in S3.
506 */
507 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
508 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
509
510 /*
511 * Clear "initialization complete" bit to move adapter from
512 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
513 */
514 iwl_clear_bit(trans, CSR_GP_CNTRL,
515 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
516
517 /* Activates XTAL resources monitor */
518 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
519 CSR_MONITOR_XTAL_RESOURCES);
520
521 /* Release XTAL ON request */
522 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
523 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
524 udelay(10);
525
526 /* Release APMG XTAL */
527 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
528 apmg_xtal_cfg_reg &
529 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
530}
531
e8c8935e 532void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 533{
e8c8935e 534 int ret;
cc56feb2
EG		 535
536 /* stop device's busmaster DMA activity */
537 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
538
539 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 540 CSR_RESET_REG_FLAG_MASTER_DISABLED,
541 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 542 if (ret < 0)
cc56feb2
EG		 543 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
544
545 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 546}
547
b7aaeae4 548static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 549{
550 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
551
b7aaeae4
EG		 552 if (op_mode_leave) {
553 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
554 iwl_pcie_apm_init(trans);
555
556 /* inform ME that we are leaving */
557 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
558 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
559 APMG_PCIDEV_STT_VAL_WAKE_ME);
6e584873 560 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 561 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
562 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 563 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
564 CSR_HW_IF_CONFIG_REG_PREPARE |
565 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 566 mdelay(1);
567 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
568 CSR_RESET_LINK_PWR_MGMT_DISABLED);
569 }
b7aaeae4
EG		 570 mdelay(5);
571 }
572
eb7ff77e 573 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 574
575 /* Stop device's DMA activity */
7afe3705 576 iwl_pcie_apm_stop_master(trans);
cc56feb2 577
a812cba9
AB		 578 if (trans->cfg->lp_xtal_workaround) {
579 iwl_pcie_apm_lp_xtal_enable(trans);
580 return;
581 }
582
099a628b 583 iwl_pcie_sw_reset(trans);
cc56feb2
EG		 584
585 /*
586 * Clear "initialization complete" bit to move adapter from
587 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
588 */
589 iwl_clear_bit(trans, CSR_GP_CNTRL,
590 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
591}
592
7afe3705 593static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 594{
7b11488f 595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 596 int ret;
392f8b78
EG		 597
598 /* nic_init */
7b70bd63 599 spin_lock(&trans_pcie->irq_lock);
52b6e168 600 ret = iwl_pcie_apm_init(trans);
7b70bd63 601 spin_unlock(&trans_pcie->irq_lock);
392f8b78 602
52b6e168
EG		 603 if (ret)
604 return ret;
605
95411d04 606 iwl_pcie_set_pwr(trans, false);
392f8b78 607
ecdb975c 608 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 609
610 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 611 iwl_pcie_rx_init(trans);
392f8b78
EG		 612
613 /* Allocate or reset and init all Tx and Command queues */
f02831be 614 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 615 return -ENOMEM;
616
035f7ff2 617 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 618 /* enable shadow regs in HW */
20d3b647 619 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 620 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 621 }
622
392f8b78
EG		 623 return 0;
624}
625
626#define HW_READY_TIMEOUT (50)
627
628/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 629static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 630{
631 int ret;
632
1042db2a 633 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 634 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 635
636 /* See if we got it */
1042db2a 637 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 638 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
639 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
640 HW_READY_TIMEOUT);
392f8b78 641
6a08f514
EG		 642 if (ret >= 0)
643 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
644
6d8f6eeb 645 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 646 return ret;
647}
648
649/* Note: returns standard 0/-ERROR code */
eda50cde 650int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 651{
652 int ret;
289e5501 653 int t = 0;
501fd989 654 int iter;
392f8b78 655
6d8f6eeb 656 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 657
7afe3705 658 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 659 /* If the card is ready, exit 0 */
392f8b78
EG		 660 if (ret >= 0)
661 return 0;
662
c9fdec9f
EG		 663 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
664 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 665 usleep_range(1000, 2000);
c9fdec9f 666
501fd989
EG		 667 for (iter = 0; iter < 10; iter++) {
668 /* If HW is not ready, prepare the conditions to check again */
669 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
670 CSR_HW_IF_CONFIG_REG_PREPARE);
671
672 do {
673 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 674 if (ret >= 0)
675 return 0;
392f8b78 676
501fd989
EG		 677 usleep_range(200, 1000);
678 t += 200;
679 } while (t < 150000);
680 msleep(25);
681 }
392f8b78 682
7f2ac8fb 683 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 684
392f8b78
EG		 685 return ret;
686}
687
cf614297
EG		 688/*
689 * ucode
690 */
564cdce7
SS		 691static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
692 u32 dst_addr, dma_addr_t phy_addr,
693 u32 byte_cnt)
cf614297 694{
bac842da
EG		 695 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
696 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
697
698 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
699 dst_addr);
700
701 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
702 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
703
704 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
705 (iwl_get_dma_hi_addr(phy_addr)
706 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
707
708 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
709 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
710 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
711 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
712
713 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
714 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
715 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
716 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 717}
718
564cdce7
SS		 719static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
720 u32 dst_addr, dma_addr_t phy_addr,
721 u32 byte_cnt)
722{
723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
724 unsigned long flags;
725 int ret;
726
727 trans_pcie->ucode_write_complete = false;
728
729 if (!iwl_trans_grab_nic_access(trans, &flags))
730 return -EIO;
731
eda50cde
SS		 732 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
733 byte_cnt);
bac842da 734 iwl_trans_release_nic_access(trans, &flags);
cf614297 735
13df1aab
JB		 736 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
737 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 738 if (!ret) {
83f84d7b 739 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 740 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 741 return -ETIMEDOUT;
742 }
743
744 return 0;
745}
746
7afe3705 747static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 748 const struct fw_desc *section)
cf614297 749{
83f84d7b
JB		 750 u8 *v_addr;
751 dma_addr_t p_addr;
baa21e83 752 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 753 int ret = 0;
754
83f84d7b
JB		 755 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
756 section_num);
757
c571573a
EG		 758 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
759 GFP_KERNEL | __GFP_NOWARN);
760 if (!v_addr) {
761 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
762 chunk_sz = PAGE_SIZE;
763 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
764 &p_addr, GFP_KERNEL);
765 if (!v_addr)
766 return -ENOMEM;
767 }
83f84d7b 768
c571573a 769 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 770 u32 copy_size, dst_addr;
771 bool extended_addr = false;
83f84d7b 772
c571573a 773 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 774 dst_addr = section->offset + offset;
775
776 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
777 dst_addr <= IWL_FW_MEM_EXTENDED_END)
778 extended_addr = true;
779
780 if (extended_addr)
781 iwl_set_bits_prph(trans, LMPM_CHICK,
782 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 783
83f84d7b 784 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 785 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
786 copy_size);
787
788 if (extended_addr)
789 iwl_clear_bits_prph(trans, LMPM_CHICK,
790 LMPM_CHICK_EXTENDED_ADDR_SPACE);
791
83f84d7b
JB		 792 if (ret) {
793 IWL_ERR(trans,
794 "Could not load the [%d] uCode section\n",
795 section_num);
796 break;
6dfa8d01 797 }
83f84d7b
JB		 798 }
799
c571573a 800 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 801 return ret;
802}
803
5dd9c68a
EG		 804static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
805 const struct fw_img *image,
806 int cpu,
807 int *first_ucode_section)
e2d6f4e7
EH		 808{
809 int shift_param;
dcab8ecd
EH		 810 int i, ret = 0, sec_num = 0x1;
811 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 812
813 if (cpu == 1) {
814 shift_param = 0;
034846cf 815 *first_ucode_section = 0;
e2d6f4e7
EH		 816 } else {
817 shift_param = 16;
034846cf 818 (*first_ucode_section)++;
e2d6f4e7
EH		 819 }
820
eef187a7 821 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 822 last_read_idx = i;
823
a6c4fb44
MG		 824 /*
825 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
826 * CPU1 to CPU2.
827 * PAGING_SEPARATOR_SECTION delimiter - separate between
828 * CPU2 non paged to CPU2 paging sec.
829 */
034846cf 830 if (!image->sec[i].data ||
a6c4fb44
MG		 831 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
832 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 833 IWL_DEBUG_FW(trans,
834 "Break since Data not valid or Empty section, sec = %d\n",
835 i);
189fa2fa 836 break;
034846cf
EH		 837 }
838
189fa2fa
EH		 839 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
840 if (ret)
841 return ret;
dcab8ecd 842
d6a2c5c7 843 /* Notify ucode of loaded section number and status */
eda50cde
SS		 844 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
845 val = val | (sec_num << shift_param);
846 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
847
dcab8ecd 848 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 849 }
850
034846cf
EH		 851 *first_ucode_section = last_read_idx;
852
2aabdbdc
EG		 853 iwl_enable_interrupts(trans);
854
d6a2c5c7
SS		 855 if (trans->cfg->use_tfh) {
856 if (cpu == 1)
857 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
858 0xFFFF);
859 else
860 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
861 0xFFFFFFFF);
862 } else {
863 if (cpu == 1)
864 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
865 0xFFFF);
866 else
867 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
868 0xFFFFFFFF);
869 }
afb88917 870
189fa2fa
EH		 871 return 0;
872}
e2d6f4e7 873
189fa2fa
EH		 874static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
875 const struct fw_img *image,
034846cf
EH		 876 int cpu,
877 int *first_ucode_section)
189fa2fa 878{
189fa2fa 879 int i, ret = 0;
034846cf 880 u32 last_read_idx = 0;
189fa2fa 881
3ce4a038 882 if (cpu == 1)
034846cf 883 *first_ucode_section = 0;
3ce4a038 884 else
034846cf 885 (*first_ucode_section)++;
189fa2fa 886
eef187a7 887 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 888 last_read_idx = i;
889
a6c4fb44
MG		 890 /*
891 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
892 * CPU1 to CPU2.
893 * PAGING_SEPARATOR_SECTION delimiter - separate between
894 * CPU2 non paged to CPU2 paging sec.
895 */
034846cf 896 if (!image->sec[i].data ||
a6c4fb44
MG		 897 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
898 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 899 IWL_DEBUG_FW(trans,
900 "Break since Data not valid or Empty section, sec = %d\n",
901 i);
189fa2fa 902 break;
034846cf
EH		 903 }
904
189fa2fa
EH		 905 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
906 if (ret)
907 return ret;
e2d6f4e7
EH		 908 }
909
034846cf
EH		 910 *first_ucode_section = last_read_idx;
911
e2d6f4e7
EH		 912 return 0;
913}
914
c9be849d 915void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7
LK		 916{
917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
fd527eb5 918 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
09e350f7
LK		 919 int i;
920
09e350f7
LK		 921 IWL_INFO(trans, "Applying debug destination %s\n",
922 get_fw_dbg_mode_string(dest->monitor_mode));
923
924 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 925 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 926 else
927 IWL_WARN(trans, "PCI should have external buffer debug\n");
928
929 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
930 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
931 u32 val = le32_to_cpu(dest->reg_ops[i].val);
932
933 switch (dest->reg_ops[i].op) {
934 case CSR_ASSIGN:
935 iwl_write32(trans, addr, val);
936 break;
937 case CSR_SETBIT:
938 iwl_set_bit(trans, addr, BIT(val));
939 break;
940 case CSR_CLEARBIT:
941 iwl_clear_bit(trans, addr, BIT(val));
942 break;
943 case PRPH_ASSIGN:
944 iwl_write_prph(trans, addr, val);
945 break;
946 case PRPH_SETBIT:
947 iwl_set_bits_prph(trans, addr, BIT(val));
948 break;
949 case PRPH_CLEARBIT:
950 iwl_clear_bits_prph(trans, addr, BIT(val));
951 break;
869f3b15
HD		 952 case PRPH_BLOCKBIT:
953 if (iwl_read_prph(trans, addr) & BIT(val)) {
954 IWL_ERR(trans,
955 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
956 val, addr);
957 goto monitor;
958 }
959 break;
09e350f7
LK		 960 default:
961 IWL_ERR(trans, "FW debug - unknown OP %d\n",
962 dest->reg_ops[i].op);
963 break;
964 }
965 }
966
869f3b15 967monitor:
09e350f7
LK		 968 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
969 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
970 trans_pcie->fw_mon_phys >> dest->base_shift);
6e584873 971 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d
EG		 972 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
973 (trans_pcie->fw_mon_phys +
974 trans_pcie->fw_mon_size - 256) >>
975 dest->end_shift);
976 else
977 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
978 (trans_pcie->fw_mon_phys +
979 trans_pcie->fw_mon_size) >>
980 dest->end_shift);
09e350f7
LK		 981 }
982}
983
7afe3705 984static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 985 const struct fw_img *image)
cf614297 986{
c2d20201 987 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 988 int ret = 0;
034846cf 989 int first_ucode_section;
cf614297 990
dcab8ecd 991 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 992 image->is_dual_cpus ? "Dual" : "Single");
993
dcab8ecd
EH		 994 /* load to FW the binary non secured sections of CPU1 */
995 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
996 if (ret)
997 return ret;
e2d6f4e7
EH		 998
999 if (image->is_dual_cpus) {
189fa2fa
EH		 1000 /* set CPU2 header address */
1001 iwl_write_prph(trans,
1002 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1003 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1004
189fa2fa 1005 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1006 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1007 &first_ucode_section);
189fa2fa
EH		 1008 if (ret)
1009 return ret;
e2d6f4e7 1010 }
cf614297 1011
c2d20201
EG		 1012 /* supported for 7000 only for the moment */
1013 if (iwlwifi_mod_params.fw_monitor &&
1014 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1015 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1016
1017 if (trans_pcie->fw_mon_size) {
1018 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1019 trans_pcie->fw_mon_phys >> 4);
1020 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1021 (trans_pcie->fw_mon_phys +
1022 trans_pcie->fw_mon_size) >> 4);
1023 }
09e350f7
LK		 1024 } else if (trans->dbg_dest_tlv) {
1025 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1026 }
1027
2aabdbdc
EG		 1028 iwl_enable_interrupts(trans);
1029
e12ba844 1030 /* release CPU reset */
5dd9c68a 1031 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1032
dcab8ecd
EH		 1033 return 0;
1034}
189fa2fa 1035
5dd9c68a
EG		 1036static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1037 const struct fw_img *image)
dcab8ecd
EH		 1038{
1039 int ret = 0;
1040 int first_ucode_section;
dcab8ecd
EH		 1041
1042 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1043 image->is_dual_cpus ? "Dual" : "Single");
1044
a2227ce2
EG		 1045 if (trans->dbg_dest_tlv)
1046 iwl_pcie_apply_destination(trans);
1047
82ea7966
SS		 1048 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1049 iwl_read_prph(trans, WFPM_GP2));
1050
1051 /*
1052 * Set default value. On resume reading the values that were
1053 * zeored can provide debug data on the resume flow.
1054 * This is for debugging only and has no functional impact.
1055 */
1056 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1057
dcab8ecd
EH		 1058 /* configure the ucode to be ready to get the secured image */
1059 /* release CPU reset */
1060 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1061
1062 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1063 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1064 &first_ucode_section);
dcab8ecd
EH		 1065 if (ret)
1066 return ret;
1067
1068 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1069 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1070 &first_ucode_section);
cf614297
EG		 1071}
1072
9ad8fd0b 1073bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1074{
326477e4 1075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1076 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1077 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1078 bool report;
727c02df 1079
326477e4
JB		 1080 if (hw_rfkill) {
1081 set_bit(STATUS_RFKILL_HW, &trans->status);
1082 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083 } else {
1084 clear_bit(STATUS_RFKILL_HW, &trans->status);
1085 if (trans_pcie->opmode_down)
1086 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1087 }
1088
1089 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1090
326477e4
JB		 1091 if (prev != report)
1092 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1093
1094 return hw_rfkill;
1095}
1096
7ca00409
HD		 1097struct iwl_causes_list {
1098 u32 cause_num;
1099 u32 mask_reg;
1100 u8 addr;
1101};
1102
1103static struct iwl_causes_list causes_list[] = {
1104 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1105 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1106 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1107 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1108 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1109 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1110 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1111 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1112 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1113 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1114 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1115 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1116 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1117 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1118};
1119
1120static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1121{
1122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1123 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1124 int i;
1125
1126 /*
1127 * Access all non RX causes and map them to the default irq.
1128 * In case we are missing at least one interrupt vector,
1129 * the first interrupt vector will serve non-RX and FBQ causes.
1130 */
1131 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1132 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1133 iwl_clear_bit(trans, causes_list[i].mask_reg,
1134 causes_list[i].cause_num);
1135 }
1136}
1137
1138static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1139{
1140 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1141 u32 offset =
1142 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1143 u32 val, idx;
1144
1145 /*
1146 * The first RX queue - fallback queue, which is designated for
1147 * management frame, command responses etc, is always mapped to the
1148 * first interrupt vector. The other RX queues are mapped to
1149 * the other (N - 2) interrupt vectors.
1150 */
1151 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1152 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1153 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1154 MSIX_FH_INT_CAUSES_Q(idx - offset));
1155 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1156 }
1157 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1158
1159 val = MSIX_FH_INT_CAUSES_Q(0);
1160 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1161 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1162 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1163
1164 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1165 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1166}
1167
77c09bc8 1168void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1169{
1170 struct iwl_trans *trans = trans_pcie->trans;
1171
1172 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1173 if (trans->cfg->mq_rx_supported &&
1174 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1175 iwl_write_prph(trans, UREG_CHICK,
1176 UREG_CHICK_MSI_ENABLE);
1177 return;
1178 }
d7270d61
HD		 1179 /*
1180 * The IVAR table needs to be configured again after reset,
1181 * but if the device is disabled, we can't write to
1182 * prph.
1183 */
1184 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1185 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1186
1187 /*
1188 * Each cause from the causes list above and the RX causes is
1189 * represented as a byte in the IVAR table. The first nibble
1190 * represents the bound interrupt vector of the cause, the second
1191 * represents no auto clear for this cause. This will be set if its
1192 * interrupt vector is bound to serve other causes.
1193 */
1194 iwl_pcie_map_rx_causes(trans);
1195
1196 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1197}
1198
1199static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1200{
1201 struct iwl_trans *trans = trans_pcie->trans;
1202
1203 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1204
83730058
HD		 1205 if (!trans_pcie->msix_enabled)
1206 return;
1207
1208 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1209 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1210 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1211 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1212}
1213
fa9f3281 1214static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1215{
43e58856 1216 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1217
fa9f3281
EG		 1218 lockdep_assert_held(&trans_pcie->mutex);
1219
1220 if (trans_pcie->is_down)
1221 return;
1222
1223 trans_pcie->is_down = true;
1224
0232d2cd
SS		 1225 /* Stop dbgc before stopping device */
1226 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1227 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1228 } else {
1229 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1230 udelay(100);
1231 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1232 }
1233
43e58856 1234 /* tell the device to stop sending interrupts */
ae2c30bf 1235 iwl_disable_interrupts(trans);
ae2c30bf 1236
ab6cf8e8 1237 /* device going down, Stop using ICT table */
990aa6d7 1238 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1239
1240 /*
1241 * If a HW restart happens during firmware loading,
1242 * then the firmware loading might call this function
1243 * and later it might be called again due to the
1244 * restart. So don't process again if the device is
1245 * already dead.
1246 */
31b8b343 1247 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1248 IWL_DEBUG_INFO(trans,
1249 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1250 iwl_pcie_tx_stop(trans);
9805c446 1251 iwl_pcie_rx_stop(trans);
6379103e 1252
ab6cf8e8 1253 /* Power-down device's busmaster DMA clocks */
95411d04 1254 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1255 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1256 APMG_CLK_VAL_DMA_CLK_RQT);
1257 udelay(5);
1258 }
ab6cf8e8
EG		 1259 }
1260
1261 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1262 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1263 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1264
1265 /* Stop the device, and put it in low power state */
b7aaeae4 1266 iwl_pcie_apm_stop(trans, false);
43e58856 1267
099a628b 1268 iwl_pcie_sw_reset(trans);
03d6c3b0 1269
f4a1f04a
GBA		 1270 /*
1271 * Upon stop, the IVAR table gets erased, so msi-x won't
1272 * work. This causes a bug in RF-KILL flows, since the interrupt
1273 * that enables radio won't fire on the correct irq, and the
1274 * driver won't be able to handle the interrupt.
1275 * Configure the IVAR table again after reset.
1276 */
1277 iwl_pcie_conf_msix_hw(trans_pcie);
1278
03d6c3b0
EG		 1279 /*
1280 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1281 * This is a bug in certain verions of the hardware.
1282 * Certain devices also keep sending HW RF kill interrupt all
1283 * the time, unless the interrupt is ACKed even if the interrupt
1284 * should be masked. Re-ACK all the interrupts here.
43e58856 1285 */
43e58856 1286 iwl_disable_interrupts(trans);
43e58856 1287
74fda971 1288 /* clear all status bits */
eb7ff77e
AN		 1289 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1290 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1291 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1292
1293 /*
1294 * Even if we stop the HW, we still want the RF kill
1295 * interrupt
1296 */
1297 iwl_enable_rfkill_int(trans);
1298
a6bd005f 1299 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1300 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1301}
1302
eda50cde 1303void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1304{
1305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1306
1307 if (trans_pcie->msix_enabled) {
1308 int i;
1309
496d83ca 1310 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1311 synchronize_irq(trans_pcie->msix_entries[i].vector);
1312 } else {
1313 synchronize_irq(trans_pcie->pci_dev->irq);
1314 }
1315}
1316
a6bd005f
EG		 1317static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1318 const struct fw_img *fw, bool run_in_rfkill)
1319{
1320 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1321 bool hw_rfkill;
1322 int ret;
1323
1324 /* This may fail if AMT took ownership of the device */
1325 if (iwl_pcie_prepare_card_hw(trans)) {
1326 IWL_WARN(trans, "Exit HW not ready\n");
1327 ret = -EIO;
1328 goto out;
1329 }
1330
1331 iwl_enable_rfkill_int(trans);
1332
1333 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1334
1335 /*
1336 * We enabled the RF-Kill interrupt and the handler may very
1337 * well be running. Disable the interrupts to make sure no other
1338 * interrupt can be fired.
1339 */
1340 iwl_disable_interrupts(trans);
1341
1342 /* Make sure it finished running */
2e5d4a8f 1343 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1344
1345 mutex_lock(&trans_pcie->mutex);
1346
1347 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1348 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1349 if (hw_rfkill && !run_in_rfkill) {
1350 ret = -ERFKILL;
1351 goto out;
1352 }
1353
1354 /* Someone called stop_device, don't try to start_fw */
1355 if (trans_pcie->is_down) {
1356 IWL_WARN(trans,
1357 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1358 ret = -EIO;
a6bd005f
EG		 1359 goto out;
1360 }
1361
1362 /* make sure rfkill handshake bits are cleared */
1363 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1364 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1365 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1366
1367 /* clear (again), then enable host interrupts */
1368 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1369
1370 ret = iwl_pcie_nic_init(trans);
1371 if (ret) {
1372 IWL_ERR(trans, "Unable to init nic\n");
1373 goto out;
1374 }
1375
1376 /*
1377 * Now, we load the firmware and don't want to be interrupted, even
1378 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1379 * FH_TX interrupt which is needed to load the firmware). If the
1380 * RF-Kill switch is toggled, we will find out after having loaded
1381 * the firmware and return the proper value to the caller.
1382 */
1383 iwl_enable_fw_load_int(trans);
1384
1385 /* really make sure rfkill handshake bits are cleared */
1386 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1387 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1388
1389 /* Load the given image to the HW */
6e584873 1390 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1391 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1392 else
1393 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1394
1395 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1396 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1397 if (hw_rfkill && !run_in_rfkill)
1398 ret = -ERFKILL;
1399
1400out:
1401 mutex_unlock(&trans_pcie->mutex);
1402 return ret;
1403}
1404
1405static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1406{
1407 iwl_pcie_reset_ict(trans);
1408 iwl_pcie_tx_start(trans, scd_addr);
1409}
1410
326477e4
JB		 1411void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1412 bool was_in_rfkill)
1413{
1414 bool hw_rfkill;
1415
1416 /*
1417 * Check again since the RF kill state may have changed while
1418 * all the interrupts were disabled, in this case we couldn't
1419 * receive the RF kill interrupt and update the state in the
1420 * op_mode.
1421 * Don't call the op_mode if the rkfill state hasn't changed.
1422 * This allows the op_mode to call stop_device from the rfkill
1423 * notification without endless recursion. Under very rare
1424 * circumstances, we might have a small recursion if the rfkill
1425 * state changed exactly now while we were called from stop_device.
1426 * This is very unlikely but can happen and is supported.
1427 */
1428 hw_rfkill = iwl_is_rfkill_set(trans);
1429 if (hw_rfkill) {
1430 set_bit(STATUS_RFKILL_HW, &trans->status);
1431 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1432 } else {
1433 clear_bit(STATUS_RFKILL_HW, &trans->status);
1434 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1435 }
1436 if (hw_rfkill != was_in_rfkill)
1437 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1438}
1439
fa9f3281
EG		 1440static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1441{
1442 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1443 bool was_in_rfkill;
fa9f3281
EG		 1444
1445 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1446 trans_pcie->opmode_down = true;
1447 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
fa9f3281 1448 _iwl_trans_pcie_stop_device(trans, low_power);
326477e4 1449 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1450 mutex_unlock(&trans_pcie->mutex);
1451}
1452
14cfca71
JB		 1453void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1454{
fa9f3281
EG		 1455 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1456 IWL_TRANS_GET_PCIE_TRANS(trans);
1457
1458 lockdep_assert_held(&trans_pcie->mutex);
1459
326477e4
JB		 1460 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1461 state ? "disabled" : "enabled");
77c09bc8
SS		 1462 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1463 if (trans->cfg->gen2)
1464 _iwl_trans_pcie_gen2_stop_device(trans, true);
1465 else
1466 _iwl_trans_pcie_stop_device(trans, true);
1467 }
ab6cf8e8
EG		 1468}
1469
23ae6128
MG		 1470static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1471 bool reset)
2dd4f9f7 1472{
23ae6128 1473 if (!reset) {
6dfb36c8
EP		 1474 /* Enable persistence mode to avoid reset */
1475 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1476 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1477 }
1478
2dd4f9f7 1479 iwl_disable_interrupts(trans);
debff618
JB		 1480
1481 /*
1482 * in testing mode, the host stays awake and the
1483 * hardware won't be reset (not even partially)
1484 */
1485 if (test)
1486 return;
1487
ddaf5a5b
JB		 1488 iwl_pcie_disable_ict(trans);
1489
2e5d4a8f 1490 iwl_pcie_synchronize_irqs(trans);
33b56af1 1491
2dd4f9f7
JB		 1492 iwl_clear_bit(trans, CSR_GP_CNTRL,
1493 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1494 iwl_clear_bit(trans, CSR_GP_CNTRL,
1495 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1496
1316d595
SS		 1497 iwl_pcie_enable_rx_wake(trans, false);
1498
23ae6128 1499 if (reset) {
6dfb36c8
EP		 1500 /*
1501 * reset TX queues -- some of their registers reset during S3
1502 * so if we don't reset everything here the D3 image would try
1503 * to execute some invalid memory upon resume
1504 */
1505 iwl_trans_pcie_tx_reset(trans);
1506 }
ddaf5a5b
JB		 1507
1508 iwl_pcie_set_pwr(trans, true);
1509}
1510
1511static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1512 enum iwl_d3_status *status,
23ae6128 1513 bool test, bool reset)
ddaf5a5b 1514{
d7270d61 1515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1516 u32 val;
1517 int ret;
1518
debff618
JB		 1519 if (test) {
1520 iwl_enable_interrupts(trans);
1521 *status = IWL_D3_STATUS_ALIVE;
1522 return 0;
1523 }
1524
1316d595
SS		 1525 iwl_pcie_enable_rx_wake(trans, true);
1526
ddaf5a5b 1527 /*
d7270d61
HD		 1528 * Reconfigure IVAR table in case of MSIX or reset ict table in
1529 * MSI mode since HW reset erased it.
1530 * Also enables interrupts - none will happen as
1531 * the device doesn't know we're waking it up, only when
1532 * the opmode actually tells it after this call.
ddaf5a5b 1533 */
d7270d61
HD		 1534 iwl_pcie_conf_msix_hw(trans_pcie);
1535 if (!trans_pcie->msix_enabled)
1536 iwl_pcie_reset_ict(trans);
18dcb9a9 1537 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1538
1539 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1540 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1541
6e584873 1542 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28
EG		 1543 udelay(2);
1544
ddaf5a5b
JB		 1545 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1546 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1547 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1548 25000);
7f2ac8fb 1549 if (ret < 0) {
ddaf5a5b
JB		 1550 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1551 return ret;
1552 }
1553
a3ead656
EG		 1554 iwl_pcie_set_pwr(trans, false);
1555
23ae6128 1556 if (!reset) {
6dfb36c8
EP		 1557 iwl_clear_bit(trans, CSR_GP_CNTRL,
1558 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1559 } else {
1560 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1561
6dfb36c8
EP		 1562 ret = iwl_pcie_rx_init(trans);
1563 if (ret) {
1564 IWL_ERR(trans,
1565 "Failed to resume the device (RX reset)\n");
1566 return ret;
1567 }
ddaf5a5b
JB		 1568 }
1569
82ea7966
SS		 1570 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1571 iwl_read_prph(trans, WFPM_GP2));
1572
a3ead656
EG		 1573 val = iwl_read32(trans, CSR_RESET);
1574 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1575 *status = IWL_D3_STATUS_RESET;
1576 else
1577 *status = IWL_D3_STATUS_ALIVE;
1578
ddaf5a5b 1579 return 0;
2dd4f9f7
JB		 1580}
1581
2e5d4a8f
HD		 1582static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1583 struct iwl_trans *trans)
1584{
1585 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9fb064df 1586 int max_irqs, num_irqs, i, ret, nr_online_cpus;
2e5d4a8f 1587 u16 pci_cmd;
2e5d4a8f 1588
06f4b081
SS		 1589 if (!trans->cfg->mq_rx_supported)
1590 goto enable_msi;
1591
9fb064df
HD		 1592 nr_online_cpus = num_online_cpus();
1593 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1594 for (i = 0; i < max_irqs; i++)
1595 trans_pcie->msix_entries[i].entry = i;
496d83ca 1596
06f4b081
SS		 1597 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1598 MSIX_MIN_INTERRUPT_VECTORS,
1599 max_irqs);
1600 if (num_irqs < 0) {
2e5d4a8f 1601 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1602 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1603 num_irqs);
1604 goto enable_msi;
1605 }
1606 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1607
06f4b081
SS		 1608 IWL_DEBUG_INFO(trans,
1609 "MSI-X enabled. %d interrupt vectors were allocated\n",
1610 num_irqs);
1611
1612 /*
1613 * In case the OS provides fewer interrupts than requested, different
1614 * causes will share the same interrupt vector as follows:
1615 * One interrupt less: non rx causes shared with FBQ.
1616 * Two interrupts less: non rx causes shared with FBQ and RSS.
1617 * More than two interrupts: we will use fewer RSS queues.
1618 */
9fb064df 1619 if (num_irqs <= nr_online_cpus) {
06f4b081
SS		 1620 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1621 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1622 IWL_SHARED_IRQ_FIRST_RSS;
9fb064df 1623 } else if (num_irqs == nr_online_cpus + 1) {
06f4b081
SS		 1624 trans_pcie->trans->num_rx_queues = num_irqs;
1625 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1626 } else {
1627 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f
HD		 1628 }
1629
06f4b081
SS		 1630 trans_pcie->alloc_vecs = num_irqs;
1631 trans_pcie->msix_enabled = true;
1632 return;
1633
1634enable_msi:
1635 ret = pci_enable_msi(pdev);
1636 if (ret) {
1637 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1638 /* enable rfkill interrupt: hw bug w/a */
1639 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1640 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1641 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1642 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1643 }
1644 }
1645}
1646
7c8d91eb
HD		 1647static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1648{
1649 int iter_rx_q, i, ret, cpu, offset;
1650 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1651
1652 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1653 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1654 offset = 1 + i;
1655 for (; i < iter_rx_q ; i++) {
1656 /*
1657 * Get the cpu prior to the place to search
1658 * (i.e. return will be > i - 1).
1659 */
1660 cpu = cpumask_next(i - offset, cpu_online_mask);
1661 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1662 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1663 &trans_pcie->affinity_mask[i]);
1664 if (ret)
1665 IWL_ERR(trans_pcie->trans,
1666 "Failed to set affinity mask for IRQ %d\n",
1667 i);
1668 }
1669}
1670
64fa3aff
SD		 1671static const char *queue_name(struct device *dev,
1672 struct iwl_trans_pcie *trans_p, int i)
1673{
1674 if (trans_p->shared_vec_mask) {
1675 int vec = trans_p->shared_vec_mask &
1676 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1677
1678 if (i == 0)
1679 return DRV_NAME ": shared IRQ";
1680
1681 return devm_kasprintf(dev, GFP_KERNEL,
1682 DRV_NAME ": queue %d", i + vec);
1683 }
1684 if (i == 0)
1685 return DRV_NAME ": default queue";
1686
1687 if (i == trans_p->alloc_vecs - 1)
1688 return DRV_NAME ": exception";
1689
1690 return devm_kasprintf(dev, GFP_KERNEL,
1691 DRV_NAME ": queue %d", i);
1692}
1693
2e5d4a8f
HD		 1694static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1695 struct iwl_trans_pcie *trans_pcie)
1696{
496d83ca 1697 int i;
2e5d4a8f 1698
496d83ca 1699 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1700 int ret;
5a41a86c 1701 struct msix_entry *msix_entry;
64fa3aff
SD		 1702 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1703
1704 if (!qname)
1705 return -ENOMEM;
5a41a86c
SD		 1706
1707 msix_entry = &trans_pcie->msix_entries[i];
1708 ret = devm_request_threaded_irq(&pdev->dev,
1709 msix_entry->vector,
1710 iwl_pcie_msix_isr,
1711 (i == trans_pcie->def_irq) ?
1712 iwl_pcie_irq_msix_handler :
1713 iwl_pcie_irq_rx_msix_handler,
1714 IRQF_SHARED,
64fa3aff 1715 qname,
5a41a86c 1716 msix_entry);
2e5d4a8f 1717 if (ret) {
2e5d4a8f
HD		 1718 IWL_ERR(trans_pcie->trans,
1719 "Error allocating IRQ %d\n", i);
5a41a86c 1720
2e5d4a8f
HD		 1721 return ret;
1722 }
1723 }
7c8d91eb 1724 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1725
1726 return 0;
1727}
1728
fa9f3281 1729static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1730{
fa9f3281 1731 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1732 int err;
e6bb4c9c 1733
fa9f3281
EG		 1734 lockdep_assert_held(&trans_pcie->mutex);
1735
7afe3705 1736 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1737 if (err) {
d6f1c316 1738 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1739 return err;
ebb7678d 1740 }
a6c684ee 1741
099a628b 1742 iwl_pcie_sw_reset(trans);
2997494f 1743
52b6e168
EG		 1744 err = iwl_pcie_apm_init(trans);
1745 if (err)
1746 return err;
a6c684ee 1747
2e5d4a8f 1748 iwl_pcie_init_msix(trans_pcie);
83730058 1749
226c02ca
EG		 1750 /* From now on, the op_mode will be kept updated about RF kill state */
1751 iwl_enable_rfkill_int(trans);
1752
326477e4
JB		 1753 trans_pcie->opmode_down = false;
1754
fa9f3281
EG		 1755 /* Set is_down to false here so that...*/
1756 trans_pcie->is_down = false;
1757
727c02df 1758 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1759 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1760
4cbb8e50
LC		 1761 /* Make sure we sync here, because we'll need full access later */
1762 if (low_power)
1763 pm_runtime_resume(trans->dev);
1764
a8b691e6 1765 return 0;
e6bb4c9c
EG		 1766}
1767
fa9f3281
EG		 1768static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1769{
1770 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1771 int ret;
1772
1773 mutex_lock(&trans_pcie->mutex);
1774 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1775 mutex_unlock(&trans_pcie->mutex);
1776
1777 return ret;
1778}
1779
a4082843 1780static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1781{
20d3b647 1782 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1783
fa9f3281
EG		 1784 mutex_lock(&trans_pcie->mutex);
1785
a4082843 1786 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1787 iwl_disable_interrupts(trans);
ee7d737c 1788
b7aaeae4 1789 iwl_pcie_apm_stop(trans, true);
cc56feb2 1790
218733cf 1791 iwl_disable_interrupts(trans);
1df06bdc 1792
8d96bb61 1793 iwl_pcie_disable_ict(trans);
33b56af1 1794
fa9f3281 1795 mutex_unlock(&trans_pcie->mutex);
33b56af1 1796
2e5d4a8f 1797 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1798}
1799
03905495
EG		 1800static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1801{
05f5b97e 1802 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1803}
1804
1805static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1806{
05f5b97e 1807 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1808}
1809
1810static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1811{
05f5b97e 1812 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1813}
1814
6a06b6c1
EG		 1815static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1816{
f9477c17
AP		 1817 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1818 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1819 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1820}
1821
1822static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1823 u32 val)
1824{
1825 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1826 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1827 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1828}
1829
c6f600fc 1830static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1831 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1832{
1833 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1834
1835 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1836 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1837 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1838 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1839 trans_pcie->n_no_reclaim_cmds = 0;
1840 else
1841 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1842 if (trans_pcie->n_no_reclaim_cmds)
1843 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1844 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1845
6c4fbcbc
EG		 1846 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1847 trans_pcie->rx_page_order =
1848 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1849
046db346 1850 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1851 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1852 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1853
21cb3222
JB		 1854 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1855 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1856
39bdb17e
SD		 1857 trans->command_groups = trans_cfg->command_groups;
1858 trans->command_groups_size = trans_cfg->command_groups_size;
1859
f14d6b39
JB		 1860 /* Initialize NAPI here - it should be before registering to mac80211
1861 * in the opmode but after the HW struct is allocated.
1862 * As this function may be called again in some corner cases don't
1863 * do anything if NAPI was already initialized.
1864 */
bce97731 1865 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1866 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1867}
1868
d1ff5253 1869void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1870{
20d3b647 1871 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1872 int i;
a42a1844 1873
2e5d4a8f 1874 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1875
13a3a390
SS		 1876 if (trans->cfg->gen2)
1877 iwl_pcie_gen2_tx_free(trans);
1878 else
1879 iwl_pcie_tx_free(trans);
9805c446 1880 iwl_pcie_rx_free(trans);
6379103e 1881
10a54d81
LC		 1882 if (trans_pcie->rba.alloc_wq) {
1883 destroy_workqueue(trans_pcie->rba.alloc_wq);
1884 trans_pcie->rba.alloc_wq = NULL;
1885 }
1886
2e5d4a8f 1887 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1888 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1889 irq_set_affinity_hint(
1890 trans_pcie->msix_entries[i].vector,
1891 NULL);
7c8d91eb 1892 }
2e5d4a8f 1893
2e5d4a8f
HD		 1894 trans_pcie->msix_enabled = false;
1895 } else {
2e5d4a8f 1896 iwl_pcie_free_ict(trans);
2e5d4a8f 1897 }
a42a1844 1898
c2d20201
EG		 1899 iwl_pcie_free_fw_monitor(trans);
1900
6eb5e529
EG		 1901 for_each_possible_cpu(i) {
1902 struct iwl_tso_hdr_page *p =
1903 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1904
1905 if (p->page)
1906 __free_page(p->page);
1907 }
1908
1909 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1910 mutex_destroy(&trans_pcie->mutex);
7b501d10 1911 iwl_trans_free(trans);
34c1b7ba
EG		 1912}
1913
47107e84
DF		 1914static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1915{
47107e84 1916 if (state)
eb7ff77e 1917 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1918 else
eb7ff77e 1919 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1920}
1921
23ba9340
EG		 1922static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1923 unsigned long *flags)
7a65d170
EG		 1924{
1925 int ret;
cfb4e624
JB		 1926 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1927
1928 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1929
fc8a350d 1930 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1931 goto out;
1932
7a65d170 1933 /* this bit wakes up the NIC */
e139dc4a
LE		 1934 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1935 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6e584873 1936 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 1937 udelay(2);
7a65d170
EG		 1938
1939 /*
1940 * These bits say the device is running, and should keep running for
1941 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1942 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 1943 * HW with volatile SRAM must save/restore contents to/from
1944 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 1945 * Each direction takes approximately 1/4 millisecond; with this
1946 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1947 * series of register accesses are expected (e.g. reading Event Log),
1948 * to keep device from sleeping.
1949 *
1950 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1951 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 1952 * is just for hardware register access; but GP1 MAC_SLEEP
1953 * check is a good idea before accessing the SRAM of HW with
1954 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 1955 *
1956 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1957 * and do not save/restore SRAM when power cycling.
1958 */
1959 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1960 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1961 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1962 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1963 if (unlikely(ret < 0)) {
fb12777a 1964 iwl_trans_pcie_dump_regs(trans);
7a65d170 1965 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1966 WARN_ONCE(1,
1967 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1968 iwl_read32(trans, CSR_GP_CNTRL));
1969 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1970 return false;
7a65d170
EG		 1971 }
1972
b9439491 1973out:
e56b04ef
LE		 1974 /*
1975 * Fool sparse by faking we release the lock - sparse will
1976 * track nic_access anyway.
1977 */
cfb4e624 1978 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1979 return true;
1980}
1981
e56b04ef
LE		 1982static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1983 unsigned long *flags)
7a65d170 1984{
cfb4e624 1985 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1986
cfb4e624 1987 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1988
1989 /*
1990 * Fool sparse by faking we acquiring the lock - sparse will
1991 * track nic_access anyway.
1992 */
cfb4e624 1993 __acquire(&trans_pcie->reg_lock);
e56b04ef 1994
fc8a350d 1995 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1996 goto out;
1997
e139dc4a
LE		 1998 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1999 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2000 /*
2001 * Above we read the CSR_GP_CNTRL register, which will flush
2002 * any previous writes, but we need the write that clears the
2003 * MAC_ACCESS_REQ bit to be performed before any other writes
2004 * scheduled on different CPUs (after we drop reg_lock).
2005 */
2006 mmiowb();
b9439491 2007out:
cfb4e624 2008 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2009}
2010
4fd442db
EG		 2011static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2012 void *buf, int dwords)
2013{
2014 unsigned long flags;
2015 int offs, ret = 0;
2016 u32 *vals = buf;
2017
23ba9340 2018 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2019 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2020 for (offs = 0; offs < dwords; offs++)
2021 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2022 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2023 } else {
2024 ret = -EBUSY;
2025 }
4fd442db
EG		 2026 return ret;
2027}
2028
2029static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2030 const void *buf, int dwords)
4fd442db
EG		 2031{
2032 unsigned long flags;
2033 int offs, ret = 0;
bf0fd5da 2034 const u32 *vals = buf;
4fd442db 2035
23ba9340 2036 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2037 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2038 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2039 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2040 vals ? vals[offs] : 0);
e56b04ef 2041 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2042 } else {
2043 ret = -EBUSY;
2044 }
4fd442db
EG		 2045 return ret;
2046}
7a65d170 2047
e0b8d405
EG		 2048static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2049 unsigned long txqs,
2050 bool freeze)
2051{
2052 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2053 int queue;
2054
2055 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2056 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2057 unsigned long now;
2058
2059 spin_lock_bh(&txq->lock);
2060
2061 now = jiffies;
2062
2063 if (txq->frozen == freeze)
2064 goto next_queue;
2065
2066 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2067 freeze ? "Freezing" : "Waking", queue);
2068
2069 txq->frozen = freeze;
2070
bb98ecd4 2071 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2072 goto next_queue;
2073
2074 if (freeze) {
2075 if (unlikely(time_after(now,
2076 txq->stuck_timer.expires))) {
2077 /*
2078 * The timer should have fired, maybe it is
2079 * spinning right now on the lock.
2080 */
2081 goto next_queue;
2082 }
2083 /* remember how long until the timer fires */
2084 txq->frozen_expiry_remainder =
2085 txq->stuck_timer.expires - now;
2086 del_timer(&txq->stuck_timer);
2087 goto next_queue;
2088 }
2089
2090 /*
2091 * Wake a non-empty queue -> arm timer with the
2092 * remainder before it froze
2093 */
2094 mod_timer(&txq->stuck_timer,
2095 now + txq->frozen_expiry_remainder);
2096
2097next_queue:
2098 spin_unlock_bh(&txq->lock);
2099 }
2100}
2101
0cd58eaa
EG		 2102static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2103{
2104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2105 int i;
2106
2107 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2108 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2109
2110 if (i == trans_pcie->cmd_queue)
2111 continue;
2112
2113 spin_lock_bh(&txq->lock);
2114
2115 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2116 txq->block--;
2117 if (!txq->block) {
2118 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2119 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2120 }
2121 } else if (block) {
2122 txq->block++;
2123 }
2124
2125 spin_unlock_bh(&txq->lock);
2126 }
2127}
2128
5f178cd2
EG		 2129#define IWL_FLUSH_WAIT_MS 2000
2130
38398efb
SS		 2131void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2132{
afb84431
EG		 2133 u32 txq_id = txq->id;
2134 u32 status;
2135 bool active;
2136 u8 fifo;
38398efb 2137
afb84431
EG		 2138 if (trans->cfg->use_tfh) {
2139 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2140 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2141 /* TODO: access new SCD registers and dump them */
2142 return;
38398efb 2143 }
afb84431
EG		 2144
2145 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2146 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2147 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2148
2149 IWL_ERR(trans,
2150 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2151 txq_id, active ? "" : "in", fifo,
2152 jiffies_to_msecs(txq->wd_timeout),
2153 txq->read_ptr, txq->write_ptr,
2154 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2155 (TFD_QUEUE_SIZE_MAX - 1),
2156 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2157 (TFD_QUEUE_SIZE_MAX - 1),
2158 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2159}
2160
d6d517b7 2161static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2162{
8ad71bef 2163 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2164 struct iwl_txq *txq;
5f178cd2 2165 unsigned long now = jiffies;
d6d517b7
SS		 2166 u8 wr_ptr;
2167
2168 if (!test_bit(txq_idx, trans_pcie->queue_used))
2169 return -EINVAL;
2170
2171 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2172 txq = trans_pcie->txq[txq_idx];
6aa7de05 2173 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2174
6aa7de05 2175 while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
d6d517b7
SS		 2176 !time_after(jiffies,
2177 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2178 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7
SS		 2179
2180 if (WARN_ONCE(wr_ptr != write_ptr,
2181 "WR pointer moved while flushing %d -> %d\n",
2182 wr_ptr, write_ptr))
2183 return -ETIMEDOUT;
2184 usleep_range(1000, 2000);
2185 }
2186
2187 if (txq->read_ptr != txq->write_ptr) {
2188 IWL_ERR(trans,
2189 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2190 iwl_trans_pcie_log_scd_error(trans, txq);
2191 return -ETIMEDOUT;
2192 }
2193
2194 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2195
2196 return 0;
2197}
2198
2199static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2200{
2201 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2202 int cnt;
5f178cd2
EG		 2203 int ret = 0;
2204
2205 /* waiting for all the tx frames complete might take a while */
035f7ff2 2206 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd 2207
9ba1947a 2208 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2209 continue;
3cafdbe6
EG		 2210 if (!test_bit(cnt, trans_pcie->queue_used))
2211 continue;
2212 if (!(BIT(cnt) & txq_bm))
2213 continue;
748fa67c 2214
d6d517b7
SS		 2215 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2216 if (ret)
5f178cd2 2217 break;
5f178cd2 2218 }
1c3fea82 2219
5f178cd2
EG		 2220 return ret;
2221}
2222
e139dc4a
LE		 2223static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2224 u32 mask, u32 value)
2225{
e56b04ef 2226 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2227 unsigned long flags;
2228
e56b04ef 2229 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2230 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2231 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2232}
2233
c24c7f58 2234static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2235{
2236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2237
2238 if (iwlwifi_mod_params.d0i3_disable)
2239 return;
2240
b3ff1270 2241 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2242
2243#ifdef CONFIG_PM
2244 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2245 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2246#endif /* CONFIG_PM */
7616f334
EP		 2247}
2248
c24c7f58 2249static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2250{
2251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2252
2253 if (iwlwifi_mod_params.d0i3_disable)
2254 return;
2255
b3ff1270
LC		 2256 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2257 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2258
5d93f3a2
LC		 2259#ifdef CONFIG_PM
2260 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2261 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2262#endif /* CONFIG_PM */
7616f334
EP		 2263}
2264
ff620849
EG		 2265static const char *get_csr_string(int cmd)
2266{
d9fb6465 2267#define IWL_CMD(x) case x: return #x
ff620849
EG		 2268 switch (cmd) {
2269 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2270 IWL_CMD(CSR_INT_COALESCING);
2271 IWL_CMD(CSR_INT);
2272 IWL_CMD(CSR_INT_MASK);
2273 IWL_CMD(CSR_FH_INT_STATUS);
2274 IWL_CMD(CSR_GPIO_IN);
2275 IWL_CMD(CSR_RESET);
2276 IWL_CMD(CSR_GP_CNTRL);
2277 IWL_CMD(CSR_HW_REV);
2278 IWL_CMD(CSR_EEPROM_REG);
2279 IWL_CMD(CSR_EEPROM_GP);
2280 IWL_CMD(CSR_OTP_GP_REG);
2281 IWL_CMD(CSR_GIO_REG);
2282 IWL_CMD(CSR_GP_UCODE_REG);
2283 IWL_CMD(CSR_GP_DRIVER_REG);
2284 IWL_CMD(CSR_UCODE_DRV_GP1);
2285 IWL_CMD(CSR_UCODE_DRV_GP2);
2286 IWL_CMD(CSR_LED_REG);
2287 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2288 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2289 IWL_CMD(CSR_ANA_PLL_CFG);
2290 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2291 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2292 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2293 default:
2294 return "UNKNOWN";
2295 }
d9fb6465 2296#undef IWL_CMD
ff620849
EG		 2297}
2298
990aa6d7 2299void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2300{
2301 int i;
2302 static const u32 csr_tbl[] = {
2303 CSR_HW_IF_CONFIG_REG,
2304 CSR_INT_COALESCING,
2305 CSR_INT,
2306 CSR_INT_MASK,
2307 CSR_FH_INT_STATUS,
2308 CSR_GPIO_IN,
2309 CSR_RESET,
2310 CSR_GP_CNTRL,
2311 CSR_HW_REV,
2312 CSR_EEPROM_REG,
2313 CSR_EEPROM_GP,
2314 CSR_OTP_GP_REG,
2315 CSR_GIO_REG,
2316 CSR_GP_UCODE_REG,
2317 CSR_GP_DRIVER_REG,
2318 CSR_UCODE_DRV_GP1,
2319 CSR_UCODE_DRV_GP2,
2320 CSR_LED_REG,
2321 CSR_DRAM_INT_TBL_REG,
2322 CSR_GIO_CHICKEN_BITS,
2323 CSR_ANA_PLL_CFG,
a812cba9 2324 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2325 CSR_HW_REV_WA_REG,
2326 CSR_DBG_HPET_MEM_REG
2327 };
2328 IWL_ERR(trans, "CSR values:\n");
2329 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2330 "CSR_INT_PERIODIC_REG)\n");
2331 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2332 IWL_ERR(trans, " %25s: 0X%08x\n",
2333 get_csr_string(csr_tbl[i]),
1042db2a 2334 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2335 }
2336}
2337
87e5666c
EG		 2338#ifdef CONFIG_IWLWIFI_DEBUGFS
2339/* create and remove of files */
2340#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2341 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2342 &iwl_dbgfs_##name##_ops)) \
9da987ac 2343 goto err; \
87e5666c
EG		 2344} while (0)
2345
2346/* file operation */
87e5666c 2347#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2348static const struct file_operations iwl_dbgfs_##name##_ops = { \
2349 .read = iwl_dbgfs_##name##_read, \
234e3405 2350 .open = simple_open, \
87e5666c
EG		 2351 .llseek = generic_file_llseek, \
2352};
2353
16db88ba 2354#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2355static const struct file_operations iwl_dbgfs_##name##_ops = { \
2356 .write = iwl_dbgfs_##name##_write, \
234e3405 2357 .open = simple_open, \
16db88ba
EG		 2358 .llseek = generic_file_llseek, \
2359};
2360
87e5666c 2361#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2362static const struct file_operations iwl_dbgfs_##name##_ops = { \
2363 .write = iwl_dbgfs_##name##_write, \
2364 .read = iwl_dbgfs_##name##_read, \
234e3405 2365 .open = simple_open, \
87e5666c
EG		 2366 .llseek = generic_file_llseek, \
2367};
2368
87e5666c 2369static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2370 char __user *user_buf,
2371 size_t count, loff_t *ppos)
8ad71bef 2372{
5a878bf6 2373 struct iwl_trans *trans = file->private_data;
8ad71bef 2374 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2375 struct iwl_txq *txq;
87e5666c
EG		 2376 char *buf;
2377 int pos = 0;
2378 int cnt;
2379 int ret;
1745e440
WYG		 2380 size_t bufsz;
2381
e0b8d405 2382 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2383
b2a3b1c1 2384 if (!trans_pcie->txq_memory)
87e5666c 2385 return -EAGAIN;
f9e75447 2386
87e5666c
EG		 2387 buf = kzalloc(bufsz, GFP_KERNEL);
2388 if (!buf)
2389 return -ENOMEM;
2390
035f7ff2 2391 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2392 txq = trans_pcie->txq[cnt];
87e5666c 2393 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2394 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2395 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2396 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2397 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2398 txq->need_update, txq->frozen,
f40faf62 2399 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2400 }
2401 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2402 kfree(buf);
2403 return ret;
2404}
2405
2406static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2407 char __user *user_buf,
2408 size_t count, loff_t *ppos)
2409{
5a878bf6 2410 struct iwl_trans *trans = file->private_data;
20d3b647 2411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2412 char *buf;
2413 int pos = 0, i, ret;
2414 size_t bufsz = sizeof(buf);
2415
2416 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2417
2418 if (!trans_pcie->rxq)
2419 return -EAGAIN;
2420
2421 buf = kzalloc(bufsz, GFP_KERNEL);
2422 if (!buf)
2423 return -ENOMEM;
2424
2425 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2426 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2427
2428 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2429 i);
2430 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2431 rxq->read);
2432 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2433 rxq->write);
2434 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2435 rxq->write_actual);
2436 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2437 rxq->need_update);
2438 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2439 rxq->free_count);
2440 if (rxq->rb_stts) {
2441 pos += scnprintf(buf + pos, bufsz - pos,
2442 "\tclosed_rb_num: %u\n",
2443 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2444 0x0FFF);
2445 } else {
2446 pos += scnprintf(buf + pos, bufsz - pos,
2447 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2448 }
87e5666c 2449 }
78485054
SS		 2450 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2451 kfree(buf);
2452
2453 return ret;
87e5666c
EG		 2454}
2455
1f7b6172
EG		 2456static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2457 char __user *user_buf,
20d3b647
JB		 2458 size_t count, loff_t *ppos)
2459{
1f7b6172 2460 struct iwl_trans *trans = file->private_data;
20d3b647 2461 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2462 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2463
2464 int pos = 0;
2465 char *buf;
2466 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2467 ssize_t ret;
2468
2469 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2470 if (!buf)
1f7b6172 2471 return -ENOMEM;
1f7b6172
EG		 2472
2473 pos += scnprintf(buf + pos, bufsz - pos,
2474 "Interrupt Statistics Report:\n");
2475
2476 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2477 isr_stats->hw);
2478 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2479 isr_stats->sw);
2480 if (isr_stats->sw || isr_stats->hw) {
2481 pos += scnprintf(buf + pos, bufsz - pos,
2482 "\tLast Restarting Code: 0x%X\n",
2483 isr_stats->err_code);
2484 }
2485#ifdef CONFIG_IWLWIFI_DEBUG
2486 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2487 isr_stats->sch);
2488 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2489 isr_stats->alive);
2490#endif
2491 pos += scnprintf(buf + pos, bufsz - pos,
2492 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2493
2494 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2495 isr_stats->ctkill);
2496
2497 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2498 isr_stats->wakeup);
2499
2500 pos += scnprintf(buf + pos, bufsz - pos,
2501 "Rx command responses:\t\t %u\n", isr_stats->rx);
2502
2503 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2504 isr_stats->tx);
2505
2506 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2507 isr_stats->unhandled);
2508
2509 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2510 kfree(buf);
2511 return ret;
2512}
2513
2514static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2515 const char __user *user_buf,
2516 size_t count, loff_t *ppos)
2517{
2518 struct iwl_trans *trans = file->private_data;
20d3b647 2519 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2520 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2521 u32 reset_flag;
078f1131 2522 int ret;
1f7b6172 2523
078f1131
JB		 2524 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2525 if (ret)
2526 return ret;
1f7b6172
EG		 2527 if (reset_flag == 0)
2528 memset(isr_stats, 0, sizeof(*isr_stats));
2529
2530 return count;
2531}
2532
16db88ba 2533static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2534 const char __user *user_buf,
2535 size_t count, loff_t *ppos)
16db88ba
EG		 2536{
2537 struct iwl_trans *trans = file->private_data;
16db88ba 2538
990aa6d7 2539 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2540
2541 return count;
2542}
2543
16db88ba 2544static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2545 char __user *user_buf,
2546 size_t count, loff_t *ppos)
16db88ba
EG		 2547{
2548 struct iwl_trans *trans = file->private_data;
94543a8d 2549 char *buf = NULL;
56c2477f 2550 ssize_t ret;
16db88ba 2551
56c2477f
JB		 2552 ret = iwl_dump_fh(trans, &buf);
2553 if (ret < 0)
2554 return ret;
2555 if (!buf)
2556 return -EINVAL;
2557 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2558 kfree(buf);
16db88ba
EG		 2559 return ret;
2560}
2561
fa4de7f7
JB		 2562static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2563 char __user *user_buf,
2564 size_t count, loff_t *ppos)
2565{
2566 struct iwl_trans *trans = file->private_data;
2567 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2568 char buf[100];
2569 int pos;
2570
2571 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2572 trans_pcie->debug_rfkill,
2573 !(iwl_read32(trans, CSR_GP_CNTRL) &
2574 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2575
2576 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2577}
2578
2579static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2580 const char __user *user_buf,
2581 size_t count, loff_t *ppos)
2582{
2583 struct iwl_trans *trans = file->private_data;
2584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2585 bool old = trans_pcie->debug_rfkill;
2586 int ret;
2587
2588 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2589 if (ret)
2590 return ret;
2591 if (old == trans_pcie->debug_rfkill)
2592 return count;
2593 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2594 old, trans_pcie->debug_rfkill);
2595 iwl_pcie_handle_rfkill_irq(trans);
2596
2597 return count;
2598}
2599
1f7b6172 2600DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2601DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2602DEBUGFS_READ_FILE_OPS(rx_queue);
2603DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2604DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2605DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2606
f8a1edb7
JB		 2607/* Create the debugfs files and directories */
2608int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2609{
f8a1edb7
JB		 2610 struct dentry *dir = trans->dbgfs_dir;
2611
87e5666c
EG		 2612 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2613 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2614 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2615 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2616 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
fa4de7f7 2617 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
87e5666c 2618 return 0;
9da987ac
MV		 2619
2620err:
2621 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2622 return -ENOMEM;
87e5666c 2623}
aadede6e 2624#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2625
6983ba69 2626static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2627{
3cd1980b 2628 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2629 u32 cmdlen = 0;
2630 int i;
2631
3cd1980b 2632 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2633 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2634
2635 return cmdlen;
2636}
2637
bd7fc617
EG		 2638static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2639 struct iwl_fw_error_dump_data **data,
2640 int allocated_rb_nums)
2641{
2642 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2643 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2644 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2645 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2646 u32 i, r, j, rb_len = 0;
2647
2648 spin_lock(&rxq->lock);
2649
6aa7de05 2650 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
bd7fc617
EG		 2651
2652 for (i = rxq->read, j = 0;
2653 i != r && j < allocated_rb_nums;
2654 i = (i + 1) & RX_QUEUE_MASK, j++) {
2655 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2656 struct iwl_fw_error_dump_rb *rb;
2657
2658 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2659 DMA_FROM_DEVICE);
2660
2661 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2662
2663 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2664 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2665 rb = (void *)(*data)->data;
2666 rb->index = cpu_to_le32(i);
2667 memcpy(rb->data, page_address(rxb->page), max_len);
2668 /* remap the page for the free benefit */
2669 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2670 max_len,
2671 DMA_FROM_DEVICE);
2672
2673 *data = iwl_fw_error_next_data(*data);
2674 }
2675
2676 spin_unlock(&rxq->lock);
2677
2678 return rb_len;
2679}
473ad712
EG		 2680#define IWL_CSR_TO_DUMP (0x250)
2681
2682static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2683 struct iwl_fw_error_dump_data **data)
2684{
2685 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2686 __le32 *val;
2687 int i;
2688
2689 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2690 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2691 val = (void *)(*data)->data;
2692
2693 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2694 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2695
2696 *data = iwl_fw_error_next_data(*data);
2697
2698 return csr_len;
2699}
2700
06d51e0d
LK		 2701static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2702 struct iwl_fw_error_dump_data **data)
2703{
2704 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2705 unsigned long flags;
2706 __le32 *val;
2707 int i;
2708
23ba9340 2709 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2710 return 0;
2711
2712 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2713 (*data)->len = cpu_to_le32(fh_regs_len);
2714 val = (void *)(*data)->data;
2715
723b45e2
LK		 2716 if (!trans->cfg->gen2)
2717 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2718 i += sizeof(u32))
2719 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2720 else
2721 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2722 i += sizeof(u32))
2723 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2724 i));
06d51e0d
LK		 2725
2726 iwl_trans_release_nic_access(trans, &flags);
2727
2728 *data = iwl_fw_error_next_data(*data);
2729
2730 return sizeof(**data) + fh_regs_len;
2731}
2732
cc79ef66
LK		 2733static u32
2734iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2735 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2736 u32 monitor_len)
2737{
2738 u32 buf_size_in_dwords = (monitor_len >> 2);
2739 u32 *buffer = (u32 *)fw_mon_data->data;
2740 unsigned long flags;
2741 u32 i;
2742
23ba9340 2743 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2744 return 0;
2745
14ef1b43 2746 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2747 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2748 buffer[i] = iwl_read_prph_no_grab(trans,
2749 MON_DMARB_RD_DATA_ADDR);
2750 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2751
2752 iwl_trans_release_nic_access(trans, &flags);
2753
2754 return monitor_len;
2755}
2756
36fb9017
OG		 2757static u32
2758iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2759 struct iwl_fw_error_dump_data **data,
2760 u32 monitor_len)
2761{
2762 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2763 u32 len = 0;
2764
2765 if ((trans_pcie->fw_mon_page &&
2766 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2767 trans->dbg_dest_tlv) {
2768 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2769 u32 base, write_ptr, wrap_cnt;
2770
2771 /* If there was a dest TLV - use the values from there */
2772 if (trans->dbg_dest_tlv) {
2773 write_ptr =
2774 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2775 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2776 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2777 } else {
2778 base = MON_BUFF_BASE_ADDR;
2779 write_ptr = MON_BUFF_WRPTR;
2780 wrap_cnt = MON_BUFF_CYCLE_CNT;
2781 }
2782
2783 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2784 fw_mon_data = (void *)(*data)->data;
2785 fw_mon_data->fw_mon_wr_ptr =
2786 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2787 fw_mon_data->fw_mon_cycle_cnt =
2788 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2789 fw_mon_data->fw_mon_base_ptr =
2790 cpu_to_le32(iwl_read_prph(trans, base));
2791
2792 len += sizeof(**data) + sizeof(*fw_mon_data);
2793 if (trans_pcie->fw_mon_page) {
2794 /*
2795 * The firmware is now asserted, it won't write anything
2796 * to the buffer. CPU can take ownership to fetch the
2797 * data. The buffer will be handed back to the device
2798 * before the firmware will be restarted.
2799 */
2800 dma_sync_single_for_cpu(trans->dev,
2801 trans_pcie->fw_mon_phys,
2802 trans_pcie->fw_mon_size,
2803 DMA_FROM_DEVICE);
2804 memcpy(fw_mon_data->data,
2805 page_address(trans_pcie->fw_mon_page),
2806 trans_pcie->fw_mon_size);
2807
2808 monitor_len = trans_pcie->fw_mon_size;
2809 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2810 /*
2811 * Update pointers to reflect actual values after
2812 * shifting
2813 */
fd527eb5
GBA		 2814 if (trans->dbg_dest_tlv->version) {
2815 base = (iwl_read_prph(trans, base) &
2816 IWL_LDBG_M2S_BUF_BA_MSK) <<
2817 trans->dbg_dest_tlv->base_shift;
2818 base *= IWL_M2S_UNIT_SIZE;
2819 base += trans->cfg->smem_offset;
2820 } else {
2821 base = iwl_read_prph(trans, base) <<
2822 trans->dbg_dest_tlv->base_shift;
2823 }
2824
36fb9017
OG		 2825 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2826 monitor_len / sizeof(u32));
2827 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2828 monitor_len =
2829 iwl_trans_pci_dump_marbh_monitor(trans,
2830 fw_mon_data,
2831 monitor_len);
2832 } else {
2833 /* Didn't match anything - output no monitor data */
2834 monitor_len = 0;
2835 }
2836
2837 len += monitor_len;
2838 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2839 }
2840
2841 return len;
2842}
2843
2844static struct iwl_trans_dump_data
2845*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2846 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2847{
2848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2849 struct iwl_fw_error_dump_data *data;
b2a3b1c1 2850 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
4d075007 2851 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2852 struct iwl_trans_dump_data *dump_data;
bd7fc617 2853 u32 len, num_rbs;
99684ae3 2854 u32 monitor_len;
4d075007 2855 int i, ptr;
96a6497b
SS		 2856 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2857 !trans->cfg->mq_rx_supported;
4d075007 2858
473ad712
EG		 2859 /* transport dump header */
2860 len = sizeof(*dump_data);
2861
2862 /* host commands */
2863 len += sizeof(*data) +
bb98ecd4 2864 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2865
473ad712 2866 /* FW monitor */
99684ae3 2867 if (trans_pcie->fw_mon_page) {
c544e9c4 2868 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2869 trans_pcie->fw_mon_size;
2870 monitor_len = trans_pcie->fw_mon_size;
2871 } else if (trans->dbg_dest_tlv) {
fd527eb5 2872 u32 base, end, cfg_reg;
99684ae3 2873
fd527eb5
GBA		 2874 if (trans->dbg_dest_tlv->version == 1) {
2875 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2876 cfg_reg = iwl_read_prph(trans, cfg_reg);
2877 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
2878 trans->dbg_dest_tlv->base_shift;
2879 base *= IWL_M2S_UNIT_SIZE;
2880 base += trans->cfg->smem_offset;
99684ae3 2881
fd527eb5
GBA		 2882 monitor_len =
2883 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
2884 trans->dbg_dest_tlv->end_shift;
2885 monitor_len *= IWL_M2S_UNIT_SIZE;
2886 } else {
2887 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2888 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
99684ae3 2889
fd527eb5
GBA		 2890 base = iwl_read_prph(trans, base) <<
2891 trans->dbg_dest_tlv->base_shift;
2892 end = iwl_read_prph(trans, end) <<
2893 trans->dbg_dest_tlv->end_shift;
2894
2895 /* Make "end" point to the actual end */
2896 if (trans->cfg->device_family >=
2897 IWL_DEVICE_FAMILY_8000 ||
2898 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2899 end += (1 << trans->dbg_dest_tlv->end_shift);
2900 monitor_len = end - base;
2901 }
99684ae3
LK		 2902 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2903 monitor_len;
2904 } else {
2905 monitor_len = 0;
2906 }
c2d20201 2907
36fb9017
OG		 2908 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2909 dump_data = vzalloc(len);
2910 if (!dump_data)
2911 return NULL;
2912
2913 data = (void *)dump_data->data;
2914 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2915 dump_data->len = len;
2916
2917 return dump_data;
2918 }
2919
2920 /* CSR registers */
2921 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2922
36fb9017 2923 /* FH registers */
723b45e2
LK		 2924 if (trans->cfg->gen2)
2925 len += sizeof(*data) +
2926 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2927 else
2928 len += sizeof(*data) +
2929 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
36fb9017
OG		 2930
2931 if (dump_rbs) {
78485054
SS		 2932 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2933 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2934 /* RBs */
6aa7de05 2935 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2936 & 0x0FFF;
78485054 2937 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2938 len += num_rbs * (sizeof(*data) +
2939 sizeof(struct iwl_fw_error_dump_rb) +
2940 (PAGE_SIZE << trans_pcie->rx_page_order));
2941 }
2942
5538409b
LK		 2943 /* Paged memory for gen2 HW */
2944 if (trans->cfg->gen2)
2945 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2946 len += sizeof(*data) +
2947 sizeof(struct iwl_fw_error_dump_paging) +
2948 trans_pcie->init_dram.paging[i].size;
2949
48eb7b34
EG		 2950 dump_data = vzalloc(len);
2951 if (!dump_data)
2952 return NULL;
4d075007
JB		 2953
2954 len = 0;
48eb7b34 2955 data = (void *)dump_data->data;
4d075007
JB		 2956 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2957 txcmd = (void *)data->data;
2958 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 2959 ptr = cmdq->write_ptr;
2960 for (i = 0; i < cmdq->n_window; i++) {
4ecab561 2961 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
4d075007
JB		 2962 u32 caplen, cmdlen;
2963
6983ba69
SS		 2964 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2965 trans_pcie->tfd_size * ptr);
4d075007
JB		 2966 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2967
2968 if (cmdlen) {
2969 len += sizeof(*txcmd) + caplen;
2970 txcmd->cmdlen = cpu_to_le32(cmdlen);
2971 txcmd->caplen = cpu_to_le32(caplen);
2972 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2973 txcmd = (void *)((u8 *)txcmd->data + caplen);
2974 }
2975
2976 ptr = iwl_queue_dec_wrap(ptr);
2977 }
2978 spin_unlock_bh(&cmdq->lock);
2979
2980 data->len = cpu_to_le32(len);
c2d20201 2981 len += sizeof(*data);
67c65f2c
EG		 2982 data = iwl_fw_error_next_data(data);
2983
473ad712 2984 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2985 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2986 if (dump_rbs)
2987 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2988
5538409b
LK		 2989 /* Paged memory for gen2 HW */
2990 if (trans->cfg->gen2) {
2991 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2992 struct iwl_fw_error_dump_paging *paging;
2993 dma_addr_t addr =
2994 trans_pcie->init_dram.paging[i].physical;
2995 u32 page_len = trans_pcie->init_dram.paging[i].size;
2996
2997 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2998 data->len = cpu_to_le32(sizeof(*paging) + page_len);
2999 paging = (void *)data->data;
3000 paging->index = cpu_to_le32(i);
3001 dma_sync_single_for_cpu(trans->dev, addr, page_len,
3002 DMA_BIDIRECTIONAL);
3003 memcpy(paging->data,
3004 trans_pcie->init_dram.paging[i].block, page_len);
3005 data = iwl_fw_error_next_data(data);
3006
3007 len += sizeof(*data) + sizeof(*paging) + page_len;
3008 }
3009 }
3010
36fb9017 3011 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3012
48eb7b34
EG		 3013 dump_data->len = len;
3014
3015 return dump_data;
4d075007 3016}
87e5666c 3017
4cbb8e50
LC		 3018#ifdef CONFIG_PM_SLEEP
3019static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3020{
e4c49c49
LC		 3021 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3022 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3023 return iwl_pci_fw_enter_d0i3(trans);
3024
3025 return 0;
3026}
3027
3028static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3029{
e4c49c49
LC		 3030 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3031 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3032 iwl_pci_fw_exit_d0i3(trans);
3033}
3034#endif /* CONFIG_PM_SLEEP */
3035
623e7766
SS		 3036#define IWL_TRANS_COMMON_OPS \
3037 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3038 .write8 = iwl_trans_pcie_write8, \
3039 .write32 = iwl_trans_pcie_write32, \
3040 .read32 = iwl_trans_pcie_read32, \
3041 .read_prph = iwl_trans_pcie_read_prph, \
3042 .write_prph = iwl_trans_pcie_write_prph, \
3043 .read_mem = iwl_trans_pcie_read_mem, \
3044 .write_mem = iwl_trans_pcie_write_mem, \
3045 .configure = iwl_trans_pcie_configure, \
3046 .set_pmi = iwl_trans_pcie_set_pmi, \
3047 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3048 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3049 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3050 .ref = iwl_trans_pcie_ref, \
3051 .unref = iwl_trans_pcie_unref, \
3052 .dump_data = iwl_trans_pcie_dump_data, \
fb12777a 3053 .dump_regs = iwl_trans_pcie_dump_regs, \
623e7766
SS		 3054 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3055 .d3_resume = iwl_trans_pcie_d3_resume
3056
3057#ifdef CONFIG_PM_SLEEP
3058#define IWL_TRANS_PM_OPS \
3059 .suspend = iwl_trans_pcie_suspend, \
3060 .resume = iwl_trans_pcie_resume,
3061#else
3062#define IWL_TRANS_PM_OPS
3063#endif /* CONFIG_PM_SLEEP */
3064
d1ff5253 3065static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3066 IWL_TRANS_COMMON_OPS,
3067 IWL_TRANS_PM_OPS
57a1dc89 3068 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3069 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3070 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3071 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3072
623e7766 3073 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3074
623e7766
SS		 3075 .tx = iwl_trans_pcie_tx,
3076 .reclaim = iwl_trans_pcie_reclaim,
3077
3078 .txq_disable = iwl_trans_pcie_txq_disable,
3079 .txq_enable = iwl_trans_pcie_txq_enable,
3080
3081 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3082
d6d517b7
SS		 3083 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3084
623e7766
SS		 3085 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3086 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3087};
3088
3089static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3090 IWL_TRANS_COMMON_OPS,
3091 IWL_TRANS_PM_OPS
3092 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3093 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3094 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3095 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3096
ca60da2e 3097 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3098
ab6c6445 3099 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3100 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3101
6b35ff91
SS		 3102 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3103 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3104 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
e6bb4c9c 3105};
a42a1844 3106
87ce05a2 3107struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 3108 const struct pci_device_id *ent,
3109 const struct iwl_cfg *cfg)
a42a1844 3110{
a42a1844
EG		 3111 struct iwl_trans_pcie *trans_pcie;
3112 struct iwl_trans *trans;
96a6497b 3113 int ret, addr_size;
a42a1844 3114
5a41a86c
SD		 3115 ret = pcim_enable_device(pdev);
3116 if (ret)
3117 return ERR_PTR(ret);
3118
623e7766
SS		 3119 if (cfg->gen2)
3120 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3121 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3122 else
3123 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3124 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 3125 if (!trans)
3126 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3127
3128 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3129
a42a1844 3130 trans_pcie->trans = trans;
326477e4 3131 trans_pcie->opmode_down = true;
7b11488f 3132 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3133 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3134 mutex_init(&trans_pcie->mutex);
13df1aab 3135 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 3136 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3137 if (!trans_pcie->tso_hdr_page) {
3138 ret = -ENOMEM;
3139 goto out_no_pci;
3140 }
a42a1844 3141
d819c6cf 3142
f2532b04
EG		 3143 if (!cfg->base_params->pcie_l1_allowed) {
3144 /*
3145 * W/A - seems to solve weird behavior. We need to remove this
3146 * if we don't want to stay in L1 all the time. This wastes a
3147 * lot of power.
3148 */
3149 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3150 PCIE_LINK_STATE_L1 |
3151 PCIE_LINK_STATE_CLKPM);
3152 }
a42a1844 3153
6983ba69 3154 if (cfg->use_tfh) {
2c6262b7 3155 addr_size = 64;
3cd1980b 3156 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3157 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3158 } else {
2c6262b7 3159 addr_size = 36;
3cd1980b 3160 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3161 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3162 }
3cd1980b
SS		 3163 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3164
a42a1844
EG		 3165 pci_set_master(pdev);
3166
96a6497b 3167 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3168 if (!ret)
96a6497b
SS		 3169 ret = pci_set_consistent_dma_mask(pdev,
3170 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3171 if (ret) {
3172 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3173 if (!ret)
3174 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3175 DMA_BIT_MASK(32));
a42a1844 3176 /* both attempts failed: */
af3f2f74 3177 if (ret) {
6a4b09f8 3178 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3179 goto out_no_pci;
a42a1844
EG		 3180 }
3181 }
3182
5a41a86c 3183 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3184 if (ret) {
5a41a86c
SD		 3185 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3186 goto out_no_pci;
a42a1844
EG		 3187 }
3188
5a41a86c 3189 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3190 if (!trans_pcie->hw_base) {
5a41a86c 3191 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3192 ret = -ENODEV;
5a41a86c 3193 goto out_no_pci;
a42a1844
EG		 3194 }
3195
a42a1844
EG		 3196 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3197 * PCI Tx retries from interfering with C3 CPU state */
3198 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3199
83f7a85f
EG		 3200 trans_pcie->pci_dev = pdev;
3201 iwl_disable_interrupts(trans);
3202
08079a49 3203 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3204 /*
3205 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3206 * changed, and now the revision step also includes bit 0-1 (no more
3207 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3208 * in the old format.
3209 */
6e584873 3210 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
7a42baa6 3211 unsigned long flags;
7a42baa6 3212
b513ee7f 3213 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3214 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3215
f9e5554c
EG		 3216 ret = iwl_pcie_prepare_card_hw(trans);
3217 if (ret) {
3218 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3219 goto out_no_pci;
f9e5554c
EG		 3220 }
3221
7a42baa6
EH		 3222 /*
3223 * in-order to recognize C step driver should read chip version
3224 * id located at the AUX bus MISC address space.
3225 */
3226 iwl_set_bit(trans, CSR_GP_CNTRL,
3227 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3228 udelay(2);
3229
3230 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3231 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3232 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3233 25000);
3234 if (ret < 0) {
3235 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3236 goto out_no_pci;
7a42baa6
EH		 3237 }
3238
23ba9340 3239 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3240 u32 hw_step;
3241
14ef1b43 3242 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3243 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3244 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3245 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3246 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3247 if (hw_step == 0x3)
3248 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3249 (SILICON_C_STEP << 2);
3250 iwl_trans_release_nic_access(trans, &flags);
3251 }
3252 }
3253
c00ee467
JB		 3254 /*
3255 * 9000-series integrated A-step has a problem with suspend/resume
3256 * and sometimes even causes the whole platform to get stuck. This
3257 * workaround makes the hardware not go into the problematic state.
3258 */
3259 if (trans->cfg->integrated &&
3260 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3261 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3262 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3263 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3264
f6586b69 3265#if IS_ENABLED(CONFIG_IWLMVM)
1afb0ae4 3266 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
f6586b69
TP		 3267 if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3268 u32 hw_status;
3269
3270 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3271 if (hw_status & UMAG_GEN_HW_IS_FPGA)
2f7a3863 3272 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_f0;
f6586b69 3273 else
2f7a3863 3274 trans->cfg = &iwl22000_2ac_cfg_hr;
f6586b69
TP		 3275 }
3276#endif
1afb0ae4 3277
2e5d4a8f 3278 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3279 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3280 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3281 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3282
69a10b29 3283 /* Initialize the wait queue for commands */
f946b529 3284 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3285
4cbb8e50
LC		 3286 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3287
2e5d4a8f 3288 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3289 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3290 if (ret)
5a41a86c 3291 goto out_no_pci;
2e5d4a8f
HD		 3292 } else {
3293 ret = iwl_pcie_alloc_ict(trans);
3294 if (ret)
5a41a86c 3295 goto out_no_pci;
a8b691e6 3296
5a41a86c
SD		 3297 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3298 iwl_pcie_isr,
3299 iwl_pcie_irq_handler,
3300 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3301 if (ret) {
3302 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3303 goto out_free_ict;
3304 }
3305 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3306 }
83f7a85f 3307
10a54d81
LC		 3308 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3309 WQ_HIGHPRI | WQ_UNBOUND, 1);
3310 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3311
b3ff1270
LC		 3312#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3313 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3314#else
3315 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3316#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3317
a42a1844
EG		 3318 return trans;
3319
a8b691e6
JB		 3320out_free_ict:
3321 iwl_pcie_free_ict(trans);
a42a1844 3322out_no_pci:
6eb5e529 3323 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3324 iwl_trans_free(trans);
af3f2f74 3325 return ERR_PTR(ret);
a42a1844 3326}
Linux 6.x block layer and io_uring tree(s)