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Merge branch 'nfp-flower-add-Geneve-tunnel-support'
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
d962f9b1 83#include "fw/error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
fb12777a 91static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad
RJ		 92{
93#define PCI_DUMP_SIZE 64
94#define PREFIX_LEN 32
95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
96 struct pci_dev *pdev = trans_pcie->pci_dev;
97 u32 i, pos, alloc_size, *ptr, *buf;
98 char *prefix;
99
100 if (trans_pcie->pcie_dbg_dumped_once)
101 return;
102
103 /* Should be a multiple of 4 */
104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
105 /* Alloc a max size buffer */
106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
108 else
109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
110 buf = kmalloc(alloc_size, GFP_ATOMIC);
111 if (!buf)
112 return;
113 prefix = (char *)buf + alloc_size - PREFIX_LEN;
114
115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
116
117 /* Print wifi device registers */
118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
119 IWL_ERR(trans, "iwlwifi device config registers:\n");
120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
121 if (pci_read_config_dword(pdev, i, ptr))
122 goto err_read;
123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
124
125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
127 *ptr = iwl_read32(trans, i);
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
129
130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
131 if (pos) {
132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
134 if (pci_read_config_dword(pdev, pos + i, ptr))
135 goto err_read;
136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
137 32, 4, buf, i, 0);
138 }
139
140 /* Print parent device registers next */
141 if (!pdev->bus->self)
142 goto out;
143
144 pdev = pdev->bus->self;
145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
146
147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
148 pci_name(pdev));
149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
150 if (pci_read_config_dword(pdev, i, ptr))
151 goto err_read;
152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
153
154 /* Print root port AER registers */
155 pos = 0;
156 pdev = pcie_find_root_port(pdev);
157 if (pdev)
158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
159 if (pos) {
160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
161 pci_name(pdev));
162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
164 if (pci_read_config_dword(pdev, pos + i, ptr))
165 goto err_read;
166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
167 4, buf, i, 0);
168 }
f3402d6d 169 goto out;
a6d24fad
RJ		 170
171err_read:
172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
173 IWL_ERR(trans, "Read failed at 0x%X\n", i);
174out:
175 trans_pcie->pcie_dbg_dumped_once = 1;
176 kfree(buf);
177}
178
c2d20201
EG		 179static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
180{
181 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
182
183 if (!trans_pcie->fw_mon_page)
184 return;
185
186 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
187 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
188 __free_pages(trans_pcie->fw_mon_page,
189 get_order(trans_pcie->fw_mon_size));
190 trans_pcie->fw_mon_page = NULL;
191 trans_pcie->fw_mon_phys = 0;
192 trans_pcie->fw_mon_size = 0;
193}
194
96c285da 195static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 196{
197 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 198 struct page *page = NULL;
c2d20201 199 dma_addr_t phys;
96c285da 200 u32 size = 0;
c2d20201
EG		 201 u8 power;
202
96c285da
EG		 203 if (!max_power) {
204 /* default max_power is maximum */
205 max_power = 26;
206 } else {
207 max_power += 11;
208 }
209
210 if (WARN(max_power > 26,
211 "External buffer size for monitor is too big %d, check the FW TLV\n",
212 max_power))
213 return;
214
c2d20201
EG		 215 if (trans_pcie->fw_mon_page) {
216 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
217 trans_pcie->fw_mon_size,
218 DMA_FROM_DEVICE);
219 return;
220 }
221
222 phys = 0;
96c285da 223 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 224 int order;
225
226 size = BIT(power);
227 order = get_order(size);
228 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
229 order);
230 if (!page)
231 continue;
232
233 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
234 DMA_FROM_DEVICE);
235 if (dma_mapping_error(trans->dev, phys)) {
236 __free_pages(page, order);
553452e5 237 page = NULL;
c2d20201
EG		 238 continue;
239 }
240 IWL_INFO(trans,
241 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
242 size, order);
243 break;
244 }
245
40a76905 246 if (WARN_ON_ONCE(!page))
c2d20201
EG		 247 return;
248
96c285da
EG		 249 if (power != max_power)
250 IWL_ERR(trans,
251 "Sorry - debug buffer is only %luK while you requested %luK\n",
252 (unsigned long)BIT(power - 10),
253 (unsigned long)BIT(max_power - 10));
254
c2d20201
EG		 255 trans_pcie->fw_mon_page = page;
256 trans_pcie->fw_mon_phys = phys;
257 trans_pcie->fw_mon_size = size;
258}
259
a812cba9
AB		 260static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
261{
262 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
263 ((reg & 0x0000ffff) | (2 << 28)));
264 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
265}
266
267static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
268{
269 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
270 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
271 ((reg & 0x0000ffff) | (3 << 28)));
272}
273
ddaf5a5b 274static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 275{
66337b7c 276 if (trans->cfg->apmg_not_supported)
95411d04
AA		 277 return;
278
ddaf5a5b
JB		 279 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
280 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
281 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
282 ~APMG_PS_CTRL_MSK_PWR_SRC);
283 else
284 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
285 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
286 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 287}
288
af634bee
EG		 289/* PCI registers */
290#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 291
eda50cde 292void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 293{
20d3b647 294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 295 u16 lctl;
9180ac50 296 u16 cap;
af634bee 297
af634bee
EG		 298 /*
299 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
300 * Check if BIOS (or OS) enabled L1-ASPM on this device.
301 * If so (likely), disable L0S, so device moves directly L0->L1;
302 * costs negligible amount of power savings.
303 * If not (unlikely), enable L0S, so there is at least some
304 * power savings, even without L1.
305 */
7afe3705 306 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 307 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 308 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 309 else
af634bee 310 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 311 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 312
313 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
314 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 315 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
316 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
317 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 318}
319
a6c684ee
EG		 320/*
321 * Start up NIC's basic functionality after it has been reset
7afe3705 322 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 323 * NOTE: This does not load uCode nor start the embedded processor
324 */
7afe3705 325static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 326{
52b6e168
EG		 327 int ret;
328
a6c684ee
EG		 329 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
330
331 /*
332 * Use "set_bit" below rather than "write", to preserve any hardware
333 * bits already set by default after reset.
334 */
335
336 /* Disable L0S exit timer (platform NMI Work/Around) */
6e584873 337 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 338 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
339 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 340
341 /*
342 * Disable L0s without affecting L1;
343 * don't wait for ICH L0s (ICH bug W/A)
344 */
345 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 346 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 347
348 /* Set FH wait threshold to maximum (HW error during stress W/A) */
349 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
350
351 /*
352 * Enable HAP INTA (interrupt from management bus) to
353 * wake device's PCI Express link L1a -> L0s
354 */
355 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 356 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 357
7afe3705 358 iwl_pcie_apm_config(trans);
a6c684ee
EG		 359
360 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 361 if (trans->cfg->base_params->pll_cfg)
362 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is supported, e.g. iwl_write_prph()
373 * and accesses to uCode SRAM.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee 378 if (ret < 0) {
52b6e168
EG		 379 IWL_ERR(trans, "Failed to init the card\n");
380 return ret;
a6c684ee
EG		 381 }
382
2d93aee1
EG		 383 if (trans->cfg->host_interrupt_operation_mode) {
384 /*
385 * This is a bit of an abuse - This is needed for 7260 / 3160
386 * only check host_interrupt_operation_mode even if this is
387 * not related to host_interrupt_operation_mode.
388 *
389 * Enable the oscillator to count wake up time for L1 exit. This
390 * consumes slightly more power (100uA) - but allows to be sure
391 * that we wake up from L1 on time.
392 *
393 * This looks weird: read twice the same register, discard the
394 * value, set a bit, and yet again, read that same register
395 * just to discard the value. But that's the way the hardware
396 * seems to like it.
397 */
398 iwl_read_prph(trans, OSC_CLK);
399 iwl_read_prph(trans, OSC_CLK);
400 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
401 iwl_read_prph(trans, OSC_CLK);
402 iwl_read_prph(trans, OSC_CLK);
403 }
404
a6c684ee
EG		 405 /*
406 * Enable DMA clock and wait for it to stabilize.
407 *
3073d8c0
EH		 408 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
409 * bits do not disable clocks. This preserves any hardware
410 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 411 */
95411d04 412 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 413 iwl_write_prph(trans, APMG_CLK_EN_REG,
414 APMG_CLK_VAL_DMA_CLK_RQT);
415 udelay(20);
416
417 /* Disable L1-Active */
418 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
419 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
420
421 /* Clear the interrupt in APMG if the NIC is in RFKILL */
422 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
423 APMG_RTC_INT_STT_RFKILL);
424 }
889b1696 425
eb7ff77e 426 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 427
52b6e168 428 return 0;
a6c684ee
EG		 429}
430
a812cba9
AB		 431/*
432 * Enable LP XTAL to avoid HW bug where device may consume much power if
433 * FW is not loaded after device reset. LP XTAL is disabled by default
434 * after device HW reset. Do it only if XTAL is fed by internal source.
435 * Configure device's "persistence" mode to avoid resetting XTAL again when
436 * SHRD_HW_RST occurs in S3.
437 */
438static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
439{
440 int ret;
441 u32 apmg_gp1_reg;
442 u32 apmg_xtal_cfg_reg;
443 u32 dl_cfg_reg;
444
445 /* Force XTAL ON */
446 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
447 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
448
099a628b 449 iwl_pcie_sw_reset(trans);
a812cba9
AB		 450
451 /*
452 * Set "initialization complete" bit to move adapter from
453 * D0U* --> D0A* (powered-up active) state.
454 */
455 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
456
457 /*
458 * Wait for clock stabilization; once stabilized, access to
459 * device-internal resources is possible.
460 */
461 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
462 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
463 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
464 25000);
465 if (WARN_ON(ret < 0)) {
466 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
467 /* Release XTAL ON request */
468 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
469 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
470 return;
471 }
472
473 /*
474 * Clear "disable persistence" to avoid LP XTAL resetting when
475 * SHRD_HW_RST is applied in S3.
476 */
477 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
478 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
479
480 /*
481 * Force APMG XTAL to be active to prevent its disabling by HW
482 * caused by APMG idle state.
483 */
484 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
485 SHR_APMG_XTAL_CFG_REG);
486 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
487 apmg_xtal_cfg_reg |
488 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
489
099a628b 490 iwl_pcie_sw_reset(trans);
a812cba9
AB		 491
492 /* Enable LP XTAL by indirect access through CSR */
493 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
494 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
495 SHR_APMG_GP1_WF_XTAL_LP_EN |
496 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
497
498 /* Clear delay line clock power up */
499 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
500 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
501 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
502
503 /*
504 * Enable persistence mode to avoid LP XTAL resetting when
505 * SHRD_HW_RST is applied in S3.
506 */
507 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
508 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
509
510 /*
511 * Clear "initialization complete" bit to move adapter from
512 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
513 */
514 iwl_clear_bit(trans, CSR_GP_CNTRL,
515 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
516
517 /* Activates XTAL resources monitor */
518 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
519 CSR_MONITOR_XTAL_RESOURCES);
520
521 /* Release XTAL ON request */
522 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
523 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
524 udelay(10);
525
526 /* Release APMG XTAL */
527 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
528 apmg_xtal_cfg_reg &
529 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
530}
531
e8c8935e 532void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 533{
e8c8935e 534 int ret;
cc56feb2
EG		 535
536 /* stop device's busmaster DMA activity */
537 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
538
539 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 540 CSR_RESET_REG_FLAG_MASTER_DISABLED,
541 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 542 if (ret < 0)
cc56feb2
EG		 543 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
544
545 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 546}
547
b7aaeae4 548static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 549{
550 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
551
b7aaeae4
EG		 552 if (op_mode_leave) {
553 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
554 iwl_pcie_apm_init(trans);
555
556 /* inform ME that we are leaving */
557 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
558 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
559 APMG_PCIDEV_STT_VAL_WAKE_ME);
6e584873 560 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 561 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
562 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 563 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
564 CSR_HW_IF_CONFIG_REG_PREPARE |
565 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 566 mdelay(1);
567 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
568 CSR_RESET_LINK_PWR_MGMT_DISABLED);
569 }
b7aaeae4
EG		 570 mdelay(5);
571 }
572
eb7ff77e 573 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 574
575 /* Stop device's DMA activity */
7afe3705 576 iwl_pcie_apm_stop_master(trans);
cc56feb2 577
a812cba9
AB		 578 if (trans->cfg->lp_xtal_workaround) {
579 iwl_pcie_apm_lp_xtal_enable(trans);
580 return;
581 }
582
099a628b 583 iwl_pcie_sw_reset(trans);
cc56feb2
EG		 584
585 /*
586 * Clear "initialization complete" bit to move adapter from
587 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
588 */
589 iwl_clear_bit(trans, CSR_GP_CNTRL,
590 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
591}
592
7afe3705 593static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 594{
7b11488f 595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 596 int ret;
392f8b78
EG		 597
598 /* nic_init */
7b70bd63 599 spin_lock(&trans_pcie->irq_lock);
52b6e168 600 ret = iwl_pcie_apm_init(trans);
7b70bd63 601 spin_unlock(&trans_pcie->irq_lock);
392f8b78 602
52b6e168
EG		 603 if (ret)
604 return ret;
605
95411d04 606 iwl_pcie_set_pwr(trans, false);
392f8b78 607
ecdb975c 608 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 609
610 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 611 iwl_pcie_rx_init(trans);
392f8b78
EG		 612
613 /* Allocate or reset and init all Tx and Command queues */
f02831be 614 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 615 return -ENOMEM;
616
035f7ff2 617 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 618 /* enable shadow regs in HW */
20d3b647 619 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 620 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 621 }
622
392f8b78
EG		 623 return 0;
624}
625
626#define HW_READY_TIMEOUT (50)
627
628/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 629static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 630{
631 int ret;
632
1042db2a 633 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 634 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 635
636 /* See if we got it */
1042db2a 637 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 638 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
639 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
640 HW_READY_TIMEOUT);
392f8b78 641
6a08f514
EG		 642 if (ret >= 0)
643 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
644
6d8f6eeb 645 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 646 return ret;
647}
648
649/* Note: returns standard 0/-ERROR code */
eda50cde 650int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 651{
652 int ret;
289e5501 653 int t = 0;
501fd989 654 int iter;
392f8b78 655
6d8f6eeb 656 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 657
7afe3705 658 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 659 /* If the card is ready, exit 0 */
392f8b78
EG		 660 if (ret >= 0)
661 return 0;
662
c9fdec9f
EG		 663 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
664 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 665 usleep_range(1000, 2000);
c9fdec9f 666
501fd989
EG		 667 for (iter = 0; iter < 10; iter++) {
668 /* If HW is not ready, prepare the conditions to check again */
669 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
670 CSR_HW_IF_CONFIG_REG_PREPARE);
671
672 do {
673 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 674 if (ret >= 0)
675 return 0;
392f8b78 676
501fd989
EG		 677 usleep_range(200, 1000);
678 t += 200;
679 } while (t < 150000);
680 msleep(25);
681 }
392f8b78 682
7f2ac8fb 683 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 684
392f8b78
EG		 685 return ret;
686}
687
cf614297
EG		 688/*
689 * ucode
690 */
564cdce7
SS		 691static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
692 u32 dst_addr, dma_addr_t phy_addr,
693 u32 byte_cnt)
cf614297 694{
bac842da
EG		 695 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
696 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
697
698 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
699 dst_addr);
700
701 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
702 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
703
704 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
705 (iwl_get_dma_hi_addr(phy_addr)
706 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
707
708 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
709 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
710 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
711 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
712
713 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
714 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
715 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
716 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 717}
718
564cdce7
SS		 719static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
720 u32 dst_addr, dma_addr_t phy_addr,
721 u32 byte_cnt)
722{
723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
724 unsigned long flags;
725 int ret;
726
727 trans_pcie->ucode_write_complete = false;
728
729 if (!iwl_trans_grab_nic_access(trans, &flags))
730 return -EIO;
731
eda50cde
SS		 732 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
733 byte_cnt);
bac842da 734 iwl_trans_release_nic_access(trans, &flags);
cf614297 735
13df1aab
JB		 736 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
737 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 738 if (!ret) {
83f84d7b 739 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 740 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 741 return -ETIMEDOUT;
742 }
743
744 return 0;
745}
746
7afe3705 747static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 748 const struct fw_desc *section)
cf614297 749{
83f84d7b
JB		 750 u8 *v_addr;
751 dma_addr_t p_addr;
baa21e83 752 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 753 int ret = 0;
754
83f84d7b
JB		 755 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
756 section_num);
757
c571573a
EG		 758 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
759 GFP_KERNEL | __GFP_NOWARN);
760 if (!v_addr) {
761 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
762 chunk_sz = PAGE_SIZE;
763 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
764 &p_addr, GFP_KERNEL);
765 if (!v_addr)
766 return -ENOMEM;
767 }
83f84d7b 768
c571573a 769 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 770 u32 copy_size, dst_addr;
771 bool extended_addr = false;
83f84d7b 772
c571573a 773 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 774 dst_addr = section->offset + offset;
775
776 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
777 dst_addr <= IWL_FW_MEM_EXTENDED_END)
778 extended_addr = true;
779
780 if (extended_addr)
781 iwl_set_bits_prph(trans, LMPM_CHICK,
782 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 783
83f84d7b 784 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 785 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
786 copy_size);
787
788 if (extended_addr)
789 iwl_clear_bits_prph(trans, LMPM_CHICK,
790 LMPM_CHICK_EXTENDED_ADDR_SPACE);
791
83f84d7b
JB		 792 if (ret) {
793 IWL_ERR(trans,
794 "Could not load the [%d] uCode section\n",
795 section_num);
796 break;
6dfa8d01 797 }
83f84d7b
JB		 798 }
799
c571573a 800 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 801 return ret;
802}
803
5dd9c68a
EG		 804static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
805 const struct fw_img *image,
806 int cpu,
807 int *first_ucode_section)
e2d6f4e7
EH		 808{
809 int shift_param;
dcab8ecd
EH		 810 int i, ret = 0, sec_num = 0x1;
811 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 812
813 if (cpu == 1) {
814 shift_param = 0;
034846cf 815 *first_ucode_section = 0;
e2d6f4e7
EH		 816 } else {
817 shift_param = 16;
034846cf 818 (*first_ucode_section)++;
e2d6f4e7
EH		 819 }
820
eef187a7 821 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 822 last_read_idx = i;
823
a6c4fb44
MG		 824 /*
825 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
826 * CPU1 to CPU2.
827 * PAGING_SEPARATOR_SECTION delimiter - separate between
828 * CPU2 non paged to CPU2 paging sec.
829 */
034846cf 830 if (!image->sec[i].data ||
a6c4fb44
MG		 831 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
832 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 833 IWL_DEBUG_FW(trans,
834 "Break since Data not valid or Empty section, sec = %d\n",
835 i);
189fa2fa 836 break;
034846cf
EH		 837 }
838
189fa2fa
EH		 839 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
840 if (ret)
841 return ret;
dcab8ecd 842
d6a2c5c7 843 /* Notify ucode of loaded section number and status */
eda50cde
SS		 844 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
845 val = val | (sec_num << shift_param);
846 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
847
dcab8ecd 848 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 849 }
850
034846cf
EH		 851 *first_ucode_section = last_read_idx;
852
2aabdbdc
EG		 853 iwl_enable_interrupts(trans);
854
d6a2c5c7
SS		 855 if (trans->cfg->use_tfh) {
856 if (cpu == 1)
857 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
858 0xFFFF);
859 else
860 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
861 0xFFFFFFFF);
862 } else {
863 if (cpu == 1)
864 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
865 0xFFFF);
866 else
867 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
868 0xFFFFFFFF);
869 }
afb88917 870
189fa2fa
EH		 871 return 0;
872}
e2d6f4e7 873
189fa2fa
EH		 874static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
875 const struct fw_img *image,
034846cf
EH		 876 int cpu,
877 int *first_ucode_section)
189fa2fa 878{
189fa2fa 879 int i, ret = 0;
034846cf 880 u32 last_read_idx = 0;
189fa2fa 881
3ce4a038 882 if (cpu == 1)
034846cf 883 *first_ucode_section = 0;
3ce4a038 884 else
034846cf 885 (*first_ucode_section)++;
189fa2fa 886
eef187a7 887 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 888 last_read_idx = i;
889
a6c4fb44
MG		 890 /*
891 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
892 * CPU1 to CPU2.
893 * PAGING_SEPARATOR_SECTION delimiter - separate between
894 * CPU2 non paged to CPU2 paging sec.
895 */
034846cf 896 if (!image->sec[i].data ||
a6c4fb44
MG		 897 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
898 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 899 IWL_DEBUG_FW(trans,
900 "Break since Data not valid or Empty section, sec = %d\n",
901 i);
189fa2fa 902 break;
034846cf
EH		 903 }
904
189fa2fa
EH		 905 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
906 if (ret)
907 return ret;
e2d6f4e7
EH		 908 }
909
034846cf
EH		 910 *first_ucode_section = last_read_idx;
911
e2d6f4e7
EH		 912 return 0;
913}
914
c9be849d 915void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7
LK		 916{
917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
918 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
919 int i;
920
921 if (dest->version)
922 IWL_ERR(trans,
923 "DBG DEST version is %d - expect issues\n",
924 dest->version);
925
926 IWL_INFO(trans, "Applying debug destination %s\n",
927 get_fw_dbg_mode_string(dest->monitor_mode));
928
929 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 930 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 931 else
932 IWL_WARN(trans, "PCI should have external buffer debug\n");
933
934 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
935 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
936 u32 val = le32_to_cpu(dest->reg_ops[i].val);
937
938 switch (dest->reg_ops[i].op) {
939 case CSR_ASSIGN:
940 iwl_write32(trans, addr, val);
941 break;
942 case CSR_SETBIT:
943 iwl_set_bit(trans, addr, BIT(val));
944 break;
945 case CSR_CLEARBIT:
946 iwl_clear_bit(trans, addr, BIT(val));
947 break;
948 case PRPH_ASSIGN:
949 iwl_write_prph(trans, addr, val);
950 break;
951 case PRPH_SETBIT:
952 iwl_set_bits_prph(trans, addr, BIT(val));
953 break;
954 case PRPH_CLEARBIT:
955 iwl_clear_bits_prph(trans, addr, BIT(val));
956 break;
869f3b15
HD		 957 case PRPH_BLOCKBIT:
958 if (iwl_read_prph(trans, addr) & BIT(val)) {
959 IWL_ERR(trans,
960 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
961 val, addr);
962 goto monitor;
963 }
964 break;
09e350f7
LK		 965 default:
966 IWL_ERR(trans, "FW debug - unknown OP %d\n",
967 dest->reg_ops[i].op);
968 break;
969 }
970 }
971
869f3b15 972monitor:
09e350f7
LK		 973 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
974 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
975 trans_pcie->fw_mon_phys >> dest->base_shift);
6e584873 976 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d
EG		 977 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
978 (trans_pcie->fw_mon_phys +
979 trans_pcie->fw_mon_size - 256) >>
980 dest->end_shift);
981 else
982 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
983 (trans_pcie->fw_mon_phys +
984 trans_pcie->fw_mon_size) >>
985 dest->end_shift);
09e350f7
LK		 986 }
987}
988
7afe3705 989static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 990 const struct fw_img *image)
cf614297 991{
c2d20201 992 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 993 int ret = 0;
034846cf 994 int first_ucode_section;
cf614297 995
dcab8ecd 996 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 997 image->is_dual_cpus ? "Dual" : "Single");
998
dcab8ecd
EH		 999 /* load to FW the binary non secured sections of CPU1 */
1000 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1001 if (ret)
1002 return ret;
e2d6f4e7
EH		 1003
1004 if (image->is_dual_cpus) {
189fa2fa
EH		 1005 /* set CPU2 header address */
1006 iwl_write_prph(trans,
1007 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1008 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1009
189fa2fa 1010 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1011 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1012 &first_ucode_section);
189fa2fa
EH		 1013 if (ret)
1014 return ret;
e2d6f4e7 1015 }
cf614297 1016
c2d20201
EG		 1017 /* supported for 7000 only for the moment */
1018 if (iwlwifi_mod_params.fw_monitor &&
1019 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1020 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1021
1022 if (trans_pcie->fw_mon_size) {
1023 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1024 trans_pcie->fw_mon_phys >> 4);
1025 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1026 (trans_pcie->fw_mon_phys +
1027 trans_pcie->fw_mon_size) >> 4);
1028 }
09e350f7
LK		 1029 } else if (trans->dbg_dest_tlv) {
1030 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1031 }
1032
2aabdbdc
EG		 1033 iwl_enable_interrupts(trans);
1034
e12ba844 1035 /* release CPU reset */
5dd9c68a 1036 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1037
dcab8ecd
EH		 1038 return 0;
1039}
189fa2fa 1040
5dd9c68a
EG		 1041static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1042 const struct fw_img *image)
dcab8ecd
EH		 1043{
1044 int ret = 0;
1045 int first_ucode_section;
dcab8ecd
EH		 1046
1047 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1048 image->is_dual_cpus ? "Dual" : "Single");
1049
a2227ce2
EG		 1050 if (trans->dbg_dest_tlv)
1051 iwl_pcie_apply_destination(trans);
1052
82ea7966
SS		 1053 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1054 iwl_read_prph(trans, WFPM_GP2));
1055
1056 /*
1057 * Set default value. On resume reading the values that were
1058 * zeored can provide debug data on the resume flow.
1059 * This is for debugging only and has no functional impact.
1060 */
1061 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1062
dcab8ecd
EH		 1063 /* configure the ucode to be ready to get the secured image */
1064 /* release CPU reset */
1065 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1066
1067 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1068 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1069 &first_ucode_section);
dcab8ecd
EH		 1070 if (ret)
1071 return ret;
1072
1073 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1074 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1075 &first_ucode_section);
cf614297
EG		 1076}
1077
9ad8fd0b 1078bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1079{
326477e4 1080 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1081 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1082 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083 bool report;
727c02df 1084
326477e4
JB		 1085 if (hw_rfkill) {
1086 set_bit(STATUS_RFKILL_HW, &trans->status);
1087 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1088 } else {
1089 clear_bit(STATUS_RFKILL_HW, &trans->status);
1090 if (trans_pcie->opmode_down)
1091 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1092 }
1093
1094 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1095
326477e4
JB		 1096 if (prev != report)
1097 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1098
1099 return hw_rfkill;
1100}
1101
7ca00409
HD		 1102struct iwl_causes_list {
1103 u32 cause_num;
1104 u32 mask_reg;
1105 u8 addr;
1106};
1107
1108static struct iwl_causes_list causes_list[] = {
1109 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1110 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1111 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1112 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1113 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1114 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1115 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1116 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1117 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1118 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1119 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1120 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1121 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1122 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1123};
1124
1125static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1126{
1127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1128 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1129 int i;
1130
1131 /*
1132 * Access all non RX causes and map them to the default irq.
1133 * In case we are missing at least one interrupt vector,
1134 * the first interrupt vector will serve non-RX and FBQ causes.
1135 */
1136 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1137 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1138 iwl_clear_bit(trans, causes_list[i].mask_reg,
1139 causes_list[i].cause_num);
1140 }
1141}
1142
1143static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1144{
1145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1146 u32 offset =
1147 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1148 u32 val, idx;
1149
1150 /*
1151 * The first RX queue - fallback queue, which is designated for
1152 * management frame, command responses etc, is always mapped to the
1153 * first interrupt vector. The other RX queues are mapped to
1154 * the other (N - 2) interrupt vectors.
1155 */
1156 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1157 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1158 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1159 MSIX_FH_INT_CAUSES_Q(idx - offset));
1160 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1161 }
1162 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1163
1164 val = MSIX_FH_INT_CAUSES_Q(0);
1165 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1166 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1167 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1168
1169 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1170 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1171}
1172
77c09bc8 1173void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1174{
1175 struct iwl_trans *trans = trans_pcie->trans;
1176
1177 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1178 if (trans->cfg->mq_rx_supported &&
1179 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1180 iwl_write_prph(trans, UREG_CHICK,
1181 UREG_CHICK_MSI_ENABLE);
1182 return;
1183 }
d7270d61
HD		 1184 /*
1185 * The IVAR table needs to be configured again after reset,
1186 * but if the device is disabled, we can't write to
1187 * prph.
1188 */
1189 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1190 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1191
1192 /*
1193 * Each cause from the causes list above and the RX causes is
1194 * represented as a byte in the IVAR table. The first nibble
1195 * represents the bound interrupt vector of the cause, the second
1196 * represents no auto clear for this cause. This will be set if its
1197 * interrupt vector is bound to serve other causes.
1198 */
1199 iwl_pcie_map_rx_causes(trans);
1200
1201 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1202}
1203
1204static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1205{
1206 struct iwl_trans *trans = trans_pcie->trans;
1207
1208 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1209
83730058
HD		 1210 if (!trans_pcie->msix_enabled)
1211 return;
1212
1213 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1214 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1215 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1216 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1217}
1218
fa9f3281 1219static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1220{
43e58856 1221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1222
fa9f3281
EG		 1223 lockdep_assert_held(&trans_pcie->mutex);
1224
1225 if (trans_pcie->is_down)
1226 return;
1227
1228 trans_pcie->is_down = true;
1229
0232d2cd
SS		 1230 /* Stop dbgc before stopping device */
1231 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1232 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1233 } else {
1234 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1235 udelay(100);
1236 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1237 }
1238
43e58856 1239 /* tell the device to stop sending interrupts */
ae2c30bf 1240 iwl_disable_interrupts(trans);
ae2c30bf 1241
ab6cf8e8 1242 /* device going down, Stop using ICT table */
990aa6d7 1243 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1244
1245 /*
1246 * If a HW restart happens during firmware loading,
1247 * then the firmware loading might call this function
1248 * and later it might be called again due to the
1249 * restart. So don't process again if the device is
1250 * already dead.
1251 */
31b8b343 1252 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1253 IWL_DEBUG_INFO(trans,
1254 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1255 iwl_pcie_tx_stop(trans);
9805c446 1256 iwl_pcie_rx_stop(trans);
6379103e 1257
ab6cf8e8 1258 /* Power-down device's busmaster DMA clocks */
95411d04 1259 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1260 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1261 APMG_CLK_VAL_DMA_CLK_RQT);
1262 udelay(5);
1263 }
ab6cf8e8
EG		 1264 }
1265
1266 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1267 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1268 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1269
1270 /* Stop the device, and put it in low power state */
b7aaeae4 1271 iwl_pcie_apm_stop(trans, false);
43e58856 1272
099a628b 1273 iwl_pcie_sw_reset(trans);
03d6c3b0 1274
f4a1f04a
GBA		 1275 /*
1276 * Upon stop, the IVAR table gets erased, so msi-x won't
1277 * work. This causes a bug in RF-KILL flows, since the interrupt
1278 * that enables radio won't fire on the correct irq, and the
1279 * driver won't be able to handle the interrupt.
1280 * Configure the IVAR table again after reset.
1281 */
1282 iwl_pcie_conf_msix_hw(trans_pcie);
1283
03d6c3b0
EG		 1284 /*
1285 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1286 * This is a bug in certain verions of the hardware.
1287 * Certain devices also keep sending HW RF kill interrupt all
1288 * the time, unless the interrupt is ACKed even if the interrupt
1289 * should be masked. Re-ACK all the interrupts here.
43e58856 1290 */
43e58856 1291 iwl_disable_interrupts(trans);
43e58856 1292
74fda971 1293 /* clear all status bits */
eb7ff77e
AN		 1294 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1295 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1296 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1297
1298 /*
1299 * Even if we stop the HW, we still want the RF kill
1300 * interrupt
1301 */
1302 iwl_enable_rfkill_int(trans);
1303
a6bd005f 1304 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1305 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1306}
1307
eda50cde 1308void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1309{
1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1311
1312 if (trans_pcie->msix_enabled) {
1313 int i;
1314
496d83ca 1315 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1316 synchronize_irq(trans_pcie->msix_entries[i].vector);
1317 } else {
1318 synchronize_irq(trans_pcie->pci_dev->irq);
1319 }
1320}
1321
a6bd005f
EG		 1322static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1323 const struct fw_img *fw, bool run_in_rfkill)
1324{
1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1326 bool hw_rfkill;
1327 int ret;
1328
1329 /* This may fail if AMT took ownership of the device */
1330 if (iwl_pcie_prepare_card_hw(trans)) {
1331 IWL_WARN(trans, "Exit HW not ready\n");
1332 ret = -EIO;
1333 goto out;
1334 }
1335
1336 iwl_enable_rfkill_int(trans);
1337
1338 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1339
1340 /*
1341 * We enabled the RF-Kill interrupt and the handler may very
1342 * well be running. Disable the interrupts to make sure no other
1343 * interrupt can be fired.
1344 */
1345 iwl_disable_interrupts(trans);
1346
1347 /* Make sure it finished running */
2e5d4a8f 1348 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1349
1350 mutex_lock(&trans_pcie->mutex);
1351
1352 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1353 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1354 if (hw_rfkill && !run_in_rfkill) {
1355 ret = -ERFKILL;
1356 goto out;
1357 }
1358
1359 /* Someone called stop_device, don't try to start_fw */
1360 if (trans_pcie->is_down) {
1361 IWL_WARN(trans,
1362 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1363 ret = -EIO;
a6bd005f
EG		 1364 goto out;
1365 }
1366
1367 /* make sure rfkill handshake bits are cleared */
1368 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1369 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1370 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1371
1372 /* clear (again), then enable host interrupts */
1373 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1374
1375 ret = iwl_pcie_nic_init(trans);
1376 if (ret) {
1377 IWL_ERR(trans, "Unable to init nic\n");
1378 goto out;
1379 }
1380
1381 /*
1382 * Now, we load the firmware and don't want to be interrupted, even
1383 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1384 * FH_TX interrupt which is needed to load the firmware). If the
1385 * RF-Kill switch is toggled, we will find out after having loaded
1386 * the firmware and return the proper value to the caller.
1387 */
1388 iwl_enable_fw_load_int(trans);
1389
1390 /* really make sure rfkill handshake bits are cleared */
1391 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1392 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1393
1394 /* Load the given image to the HW */
6e584873 1395 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1396 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1397 else
1398 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1399
1400 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1401 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1402 if (hw_rfkill && !run_in_rfkill)
1403 ret = -ERFKILL;
1404
1405out:
1406 mutex_unlock(&trans_pcie->mutex);
1407 return ret;
1408}
1409
1410static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1411{
1412 iwl_pcie_reset_ict(trans);
1413 iwl_pcie_tx_start(trans, scd_addr);
1414}
1415
326477e4
JB		 1416void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1417 bool was_in_rfkill)
1418{
1419 bool hw_rfkill;
1420
1421 /*
1422 * Check again since the RF kill state may have changed while
1423 * all the interrupts were disabled, in this case we couldn't
1424 * receive the RF kill interrupt and update the state in the
1425 * op_mode.
1426 * Don't call the op_mode if the rkfill state hasn't changed.
1427 * This allows the op_mode to call stop_device from the rfkill
1428 * notification without endless recursion. Under very rare
1429 * circumstances, we might have a small recursion if the rfkill
1430 * state changed exactly now while we were called from stop_device.
1431 * This is very unlikely but can happen and is supported.
1432 */
1433 hw_rfkill = iwl_is_rfkill_set(trans);
1434 if (hw_rfkill) {
1435 set_bit(STATUS_RFKILL_HW, &trans->status);
1436 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1437 } else {
1438 clear_bit(STATUS_RFKILL_HW, &trans->status);
1439 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1440 }
1441 if (hw_rfkill != was_in_rfkill)
1442 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1443}
1444
fa9f3281
EG		 1445static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1446{
1447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1448 bool was_in_rfkill;
fa9f3281
EG		 1449
1450 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1451 trans_pcie->opmode_down = true;
1452 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
fa9f3281 1453 _iwl_trans_pcie_stop_device(trans, low_power);
326477e4 1454 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1455 mutex_unlock(&trans_pcie->mutex);
1456}
1457
14cfca71
JB		 1458void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1459{
fa9f3281
EG		 1460 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1461 IWL_TRANS_GET_PCIE_TRANS(trans);
1462
1463 lockdep_assert_held(&trans_pcie->mutex);
1464
326477e4
JB		 1465 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1466 state ? "disabled" : "enabled");
77c09bc8
SS		 1467 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1468 if (trans->cfg->gen2)
1469 _iwl_trans_pcie_gen2_stop_device(trans, true);
1470 else
1471 _iwl_trans_pcie_stop_device(trans, true);
1472 }
ab6cf8e8
EG		 1473}
1474
23ae6128
MG		 1475static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1476 bool reset)
2dd4f9f7 1477{
23ae6128 1478 if (!reset) {
6dfb36c8
EP		 1479 /* Enable persistence mode to avoid reset */
1480 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1481 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1482 }
1483
2dd4f9f7 1484 iwl_disable_interrupts(trans);
debff618
JB		 1485
1486 /*
1487 * in testing mode, the host stays awake and the
1488 * hardware won't be reset (not even partially)
1489 */
1490 if (test)
1491 return;
1492
ddaf5a5b
JB		 1493 iwl_pcie_disable_ict(trans);
1494
2e5d4a8f 1495 iwl_pcie_synchronize_irqs(trans);
33b56af1 1496
2dd4f9f7
JB		 1497 iwl_clear_bit(trans, CSR_GP_CNTRL,
1498 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1499 iwl_clear_bit(trans, CSR_GP_CNTRL,
1500 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1501
1316d595
SS		 1502 iwl_pcie_enable_rx_wake(trans, false);
1503
23ae6128 1504 if (reset) {
6dfb36c8
EP		 1505 /*
1506 * reset TX queues -- some of their registers reset during S3
1507 * so if we don't reset everything here the D3 image would try
1508 * to execute some invalid memory upon resume
1509 */
1510 iwl_trans_pcie_tx_reset(trans);
1511 }
ddaf5a5b
JB		 1512
1513 iwl_pcie_set_pwr(trans, true);
1514}
1515
1516static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1517 enum iwl_d3_status *status,
23ae6128 1518 bool test, bool reset)
ddaf5a5b 1519{
d7270d61 1520 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1521 u32 val;
1522 int ret;
1523
debff618
JB		 1524 if (test) {
1525 iwl_enable_interrupts(trans);
1526 *status = IWL_D3_STATUS_ALIVE;
1527 return 0;
1528 }
1529
1316d595
SS		 1530 iwl_pcie_enable_rx_wake(trans, true);
1531
ddaf5a5b 1532 /*
d7270d61
HD		 1533 * Reconfigure IVAR table in case of MSIX or reset ict table in
1534 * MSI mode since HW reset erased it.
1535 * Also enables interrupts - none will happen as
1536 * the device doesn't know we're waking it up, only when
1537 * the opmode actually tells it after this call.
ddaf5a5b 1538 */
d7270d61
HD		 1539 iwl_pcie_conf_msix_hw(trans_pcie);
1540 if (!trans_pcie->msix_enabled)
1541 iwl_pcie_reset_ict(trans);
18dcb9a9 1542 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1543
1544 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1545 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1546
6e584873 1547 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28
EG		 1548 udelay(2);
1549
ddaf5a5b
JB		 1550 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1551 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1552 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1553 25000);
7f2ac8fb 1554 if (ret < 0) {
ddaf5a5b
JB		 1555 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1556 return ret;
1557 }
1558
a3ead656
EG		 1559 iwl_pcie_set_pwr(trans, false);
1560
23ae6128 1561 if (!reset) {
6dfb36c8
EP		 1562 iwl_clear_bit(trans, CSR_GP_CNTRL,
1563 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1564 } else {
1565 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1566
6dfb36c8
EP		 1567 ret = iwl_pcie_rx_init(trans);
1568 if (ret) {
1569 IWL_ERR(trans,
1570 "Failed to resume the device (RX reset)\n");
1571 return ret;
1572 }
ddaf5a5b
JB		 1573 }
1574
82ea7966
SS		 1575 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1576 iwl_read_prph(trans, WFPM_GP2));
1577
a3ead656
EG		 1578 val = iwl_read32(trans, CSR_RESET);
1579 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1580 *status = IWL_D3_STATUS_RESET;
1581 else
1582 *status = IWL_D3_STATUS_ALIVE;
1583
ddaf5a5b 1584 return 0;
2dd4f9f7
JB		 1585}
1586
2e5d4a8f
HD		 1587static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1588 struct iwl_trans *trans)
1589{
1590 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9fb064df 1591 int max_irqs, num_irqs, i, ret, nr_online_cpus;
2e5d4a8f 1592 u16 pci_cmd;
2e5d4a8f 1593
06f4b081
SS		 1594 if (!trans->cfg->mq_rx_supported)
1595 goto enable_msi;
1596
9fb064df
HD		 1597 nr_online_cpus = num_online_cpus();
1598 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1599 for (i = 0; i < max_irqs; i++)
1600 trans_pcie->msix_entries[i].entry = i;
496d83ca 1601
06f4b081
SS		 1602 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1603 MSIX_MIN_INTERRUPT_VECTORS,
1604 max_irqs);
1605 if (num_irqs < 0) {
2e5d4a8f 1606 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1607 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1608 num_irqs);
1609 goto enable_msi;
1610 }
1611 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1612
06f4b081
SS		 1613 IWL_DEBUG_INFO(trans,
1614 "MSI-X enabled. %d interrupt vectors were allocated\n",
1615 num_irqs);
1616
1617 /*
1618 * In case the OS provides fewer interrupts than requested, different
1619 * causes will share the same interrupt vector as follows:
1620 * One interrupt less: non rx causes shared with FBQ.
1621 * Two interrupts less: non rx causes shared with FBQ and RSS.
1622 * More than two interrupts: we will use fewer RSS queues.
1623 */
9fb064df 1624 if (num_irqs <= nr_online_cpus) {
06f4b081
SS		 1625 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1626 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1627 IWL_SHARED_IRQ_FIRST_RSS;
9fb064df 1628 } else if (num_irqs == nr_online_cpus + 1) {
06f4b081
SS		 1629 trans_pcie->trans->num_rx_queues = num_irqs;
1630 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1631 } else {
1632 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f
HD		 1633 }
1634
06f4b081
SS		 1635 trans_pcie->alloc_vecs = num_irqs;
1636 trans_pcie->msix_enabled = true;
1637 return;
1638
1639enable_msi:
1640 ret = pci_enable_msi(pdev);
1641 if (ret) {
1642 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1643 /* enable rfkill interrupt: hw bug w/a */
1644 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1645 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1646 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1647 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1648 }
1649 }
1650}
1651
7c8d91eb
HD		 1652static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1653{
1654 int iter_rx_q, i, ret, cpu, offset;
1655 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1656
1657 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1658 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1659 offset = 1 + i;
1660 for (; i < iter_rx_q ; i++) {
1661 /*
1662 * Get the cpu prior to the place to search
1663 * (i.e. return will be > i - 1).
1664 */
1665 cpu = cpumask_next(i - offset, cpu_online_mask);
1666 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1667 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1668 &trans_pcie->affinity_mask[i]);
1669 if (ret)
1670 IWL_ERR(trans_pcie->trans,
1671 "Failed to set affinity mask for IRQ %d\n",
1672 i);
1673 }
1674}
1675
64fa3aff
SD		 1676static const char *queue_name(struct device *dev,
1677 struct iwl_trans_pcie *trans_p, int i)
1678{
1679 if (trans_p->shared_vec_mask) {
1680 int vec = trans_p->shared_vec_mask &
1681 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1682
1683 if (i == 0)
1684 return DRV_NAME ": shared IRQ";
1685
1686 return devm_kasprintf(dev, GFP_KERNEL,
1687 DRV_NAME ": queue %d", i + vec);
1688 }
1689 if (i == 0)
1690 return DRV_NAME ": default queue";
1691
1692 if (i == trans_p->alloc_vecs - 1)
1693 return DRV_NAME ": exception";
1694
1695 return devm_kasprintf(dev, GFP_KERNEL,
1696 DRV_NAME ": queue %d", i);
1697}
1698
2e5d4a8f
HD		 1699static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1700 struct iwl_trans_pcie *trans_pcie)
1701{
496d83ca 1702 int i;
2e5d4a8f 1703
496d83ca 1704 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1705 int ret;
5a41a86c 1706 struct msix_entry *msix_entry;
64fa3aff
SD		 1707 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1708
1709 if (!qname)
1710 return -ENOMEM;
5a41a86c
SD		 1711
1712 msix_entry = &trans_pcie->msix_entries[i];
1713 ret = devm_request_threaded_irq(&pdev->dev,
1714 msix_entry->vector,
1715 iwl_pcie_msix_isr,
1716 (i == trans_pcie->def_irq) ?
1717 iwl_pcie_irq_msix_handler :
1718 iwl_pcie_irq_rx_msix_handler,
1719 IRQF_SHARED,
64fa3aff 1720 qname,
5a41a86c 1721 msix_entry);
2e5d4a8f 1722 if (ret) {
2e5d4a8f
HD		 1723 IWL_ERR(trans_pcie->trans,
1724 "Error allocating IRQ %d\n", i);
5a41a86c 1725
2e5d4a8f
HD		 1726 return ret;
1727 }
1728 }
7c8d91eb 1729 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1730
1731 return 0;
1732}
1733
fa9f3281 1734static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1735{
fa9f3281 1736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1737 int err;
e6bb4c9c 1738
fa9f3281
EG		 1739 lockdep_assert_held(&trans_pcie->mutex);
1740
7afe3705 1741 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1742 if (err) {
d6f1c316 1743 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1744 return err;
ebb7678d 1745 }
a6c684ee 1746
099a628b 1747 iwl_pcie_sw_reset(trans);
2997494f 1748
52b6e168
EG		 1749 err = iwl_pcie_apm_init(trans);
1750 if (err)
1751 return err;
a6c684ee 1752
2e5d4a8f 1753 iwl_pcie_init_msix(trans_pcie);
83730058 1754
226c02ca
EG		 1755 /* From now on, the op_mode will be kept updated about RF kill state */
1756 iwl_enable_rfkill_int(trans);
1757
326477e4
JB		 1758 trans_pcie->opmode_down = false;
1759
fa9f3281
EG		 1760 /* Set is_down to false here so that...*/
1761 trans_pcie->is_down = false;
1762
727c02df 1763 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1764 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1765
4cbb8e50
LC		 1766 /* Make sure we sync here, because we'll need full access later */
1767 if (low_power)
1768 pm_runtime_resume(trans->dev);
1769
a8b691e6 1770 return 0;
e6bb4c9c
EG		 1771}
1772
fa9f3281
EG		 1773static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1774{
1775 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1776 int ret;
1777
1778 mutex_lock(&trans_pcie->mutex);
1779 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1780 mutex_unlock(&trans_pcie->mutex);
1781
1782 return ret;
1783}
1784
a4082843 1785static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1786{
20d3b647 1787 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1788
fa9f3281
EG		 1789 mutex_lock(&trans_pcie->mutex);
1790
a4082843 1791 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1792 iwl_disable_interrupts(trans);
ee7d737c 1793
b7aaeae4 1794 iwl_pcie_apm_stop(trans, true);
cc56feb2 1795
218733cf 1796 iwl_disable_interrupts(trans);
1df06bdc 1797
8d96bb61 1798 iwl_pcie_disable_ict(trans);
33b56af1 1799
fa9f3281 1800 mutex_unlock(&trans_pcie->mutex);
33b56af1 1801
2e5d4a8f 1802 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1803}
1804
03905495
EG		 1805static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1806{
05f5b97e 1807 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1808}
1809
1810static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1811{
05f5b97e 1812 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1813}
1814
1815static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1816{
05f5b97e 1817 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1818}
1819
6a06b6c1
EG		 1820static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1821{
f9477c17
AP		 1822 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1823 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1824 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1825}
1826
1827static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1828 u32 val)
1829{
1830 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1831 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1832 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1833}
1834
c6f600fc 1835static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1836 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1837{
1838 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1839
1840 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1841 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1842 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1843 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1844 trans_pcie->n_no_reclaim_cmds = 0;
1845 else
1846 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1847 if (trans_pcie->n_no_reclaim_cmds)
1848 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1849 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1850
6c4fbcbc
EG		 1851 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1852 trans_pcie->rx_page_order =
1853 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1854
046db346 1855 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1856 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1857 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1858
21cb3222
JB		 1859 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1860 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1861
39bdb17e
SD		 1862 trans->command_groups = trans_cfg->command_groups;
1863 trans->command_groups_size = trans_cfg->command_groups_size;
1864
f14d6b39
JB		 1865 /* Initialize NAPI here - it should be before registering to mac80211
1866 * in the opmode but after the HW struct is allocated.
1867 * As this function may be called again in some corner cases don't
1868 * do anything if NAPI was already initialized.
1869 */
bce97731 1870 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1871 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1872}
1873
d1ff5253 1874void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1875{
20d3b647 1876 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1877 int i;
a42a1844 1878
2e5d4a8f 1879 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1880
13a3a390
SS		 1881 if (trans->cfg->gen2)
1882 iwl_pcie_gen2_tx_free(trans);
1883 else
1884 iwl_pcie_tx_free(trans);
9805c446 1885 iwl_pcie_rx_free(trans);
6379103e 1886
10a54d81
LC		 1887 if (trans_pcie->rba.alloc_wq) {
1888 destroy_workqueue(trans_pcie->rba.alloc_wq);
1889 trans_pcie->rba.alloc_wq = NULL;
1890 }
1891
2e5d4a8f 1892 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1893 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1894 irq_set_affinity_hint(
1895 trans_pcie->msix_entries[i].vector,
1896 NULL);
7c8d91eb 1897 }
2e5d4a8f 1898
2e5d4a8f
HD		 1899 trans_pcie->msix_enabled = false;
1900 } else {
2e5d4a8f 1901 iwl_pcie_free_ict(trans);
2e5d4a8f 1902 }
a42a1844 1903
c2d20201
EG		 1904 iwl_pcie_free_fw_monitor(trans);
1905
6eb5e529
EG		 1906 for_each_possible_cpu(i) {
1907 struct iwl_tso_hdr_page *p =
1908 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1909
1910 if (p->page)
1911 __free_page(p->page);
1912 }
1913
1914 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1915 mutex_destroy(&trans_pcie->mutex);
7b501d10 1916 iwl_trans_free(trans);
34c1b7ba
EG		 1917}
1918
47107e84
DF		 1919static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1920{
47107e84 1921 if (state)
eb7ff77e 1922 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1923 else
eb7ff77e 1924 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1925}
1926
23ba9340
EG		 1927static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1928 unsigned long *flags)
7a65d170
EG		 1929{
1930 int ret;
cfb4e624
JB		 1931 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1932
1933 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1934
fc8a350d 1935 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1936 goto out;
1937
7a65d170 1938 /* this bit wakes up the NIC */
e139dc4a
LE		 1939 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1940 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6e584873 1941 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 1942 udelay(2);
7a65d170
EG		 1943
1944 /*
1945 * These bits say the device is running, and should keep running for
1946 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1947 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 1948 * HW with volatile SRAM must save/restore contents to/from
1949 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 1950 * Each direction takes approximately 1/4 millisecond; with this
1951 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1952 * series of register accesses are expected (e.g. reading Event Log),
1953 * to keep device from sleeping.
1954 *
1955 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1956 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 1957 * is just for hardware register access; but GP1 MAC_SLEEP
1958 * check is a good idea before accessing the SRAM of HW with
1959 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 1960 *
1961 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1962 * and do not save/restore SRAM when power cycling.
1963 */
1964 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1965 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1966 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1967 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1968 if (unlikely(ret < 0)) {
fb12777a 1969 iwl_trans_pcie_dump_regs(trans);
7a65d170 1970 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1971 WARN_ONCE(1,
1972 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1973 iwl_read32(trans, CSR_GP_CNTRL));
1974 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1975 return false;
7a65d170
EG		 1976 }
1977
b9439491 1978out:
e56b04ef
LE		 1979 /*
1980 * Fool sparse by faking we release the lock - sparse will
1981 * track nic_access anyway.
1982 */
cfb4e624 1983 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1984 return true;
1985}
1986
e56b04ef
LE		 1987static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1988 unsigned long *flags)
7a65d170 1989{
cfb4e624 1990 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1991
cfb4e624 1992 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1993
1994 /*
1995 * Fool sparse by faking we acquiring the lock - sparse will
1996 * track nic_access anyway.
1997 */
cfb4e624 1998 __acquire(&trans_pcie->reg_lock);
e56b04ef 1999
fc8a350d 2000 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2001 goto out;
2002
e139dc4a
LE		 2003 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2004 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2005 /*
2006 * Above we read the CSR_GP_CNTRL register, which will flush
2007 * any previous writes, but we need the write that clears the
2008 * MAC_ACCESS_REQ bit to be performed before any other writes
2009 * scheduled on different CPUs (after we drop reg_lock).
2010 */
2011 mmiowb();
b9439491 2012out:
cfb4e624 2013 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2014}
2015
4fd442db
EG		 2016static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2017 void *buf, int dwords)
2018{
2019 unsigned long flags;
2020 int offs, ret = 0;
2021 u32 *vals = buf;
2022
23ba9340 2023 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2024 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2025 for (offs = 0; offs < dwords; offs++)
2026 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2027 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2028 } else {
2029 ret = -EBUSY;
2030 }
4fd442db
EG		 2031 return ret;
2032}
2033
2034static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2035 const void *buf, int dwords)
4fd442db
EG		 2036{
2037 unsigned long flags;
2038 int offs, ret = 0;
bf0fd5da 2039 const u32 *vals = buf;
4fd442db 2040
23ba9340 2041 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2042 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2043 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2044 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2045 vals ? vals[offs] : 0);
e56b04ef 2046 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2047 } else {
2048 ret = -EBUSY;
2049 }
4fd442db
EG		 2050 return ret;
2051}
7a65d170 2052
e0b8d405
EG		 2053static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2054 unsigned long txqs,
2055 bool freeze)
2056{
2057 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2058 int queue;
2059
2060 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2061 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2062 unsigned long now;
2063
2064 spin_lock_bh(&txq->lock);
2065
2066 now = jiffies;
2067
2068 if (txq->frozen == freeze)
2069 goto next_queue;
2070
2071 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2072 freeze ? "Freezing" : "Waking", queue);
2073
2074 txq->frozen = freeze;
2075
bb98ecd4 2076 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2077 goto next_queue;
2078
2079 if (freeze) {
2080 if (unlikely(time_after(now,
2081 txq->stuck_timer.expires))) {
2082 /*
2083 * The timer should have fired, maybe it is
2084 * spinning right now on the lock.
2085 */
2086 goto next_queue;
2087 }
2088 /* remember how long until the timer fires */
2089 txq->frozen_expiry_remainder =
2090 txq->stuck_timer.expires - now;
2091 del_timer(&txq->stuck_timer);
2092 goto next_queue;
2093 }
2094
2095 /*
2096 * Wake a non-empty queue -> arm timer with the
2097 * remainder before it froze
2098 */
2099 mod_timer(&txq->stuck_timer,
2100 now + txq->frozen_expiry_remainder);
2101
2102next_queue:
2103 spin_unlock_bh(&txq->lock);
2104 }
2105}
2106
0cd58eaa
EG		 2107static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2108{
2109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2110 int i;
2111
2112 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2113 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2114
2115 if (i == trans_pcie->cmd_queue)
2116 continue;
2117
2118 spin_lock_bh(&txq->lock);
2119
2120 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2121 txq->block--;
2122 if (!txq->block) {
2123 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2124 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2125 }
2126 } else if (block) {
2127 txq->block++;
2128 }
2129
2130 spin_unlock_bh(&txq->lock);
2131 }
2132}
2133
5f178cd2
EG		 2134#define IWL_FLUSH_WAIT_MS 2000
2135
38398efb
SS		 2136void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2137{
afb84431
EG		 2138 u32 txq_id = txq->id;
2139 u32 status;
2140 bool active;
2141 u8 fifo;
38398efb 2142
afb84431
EG		 2143 if (trans->cfg->use_tfh) {
2144 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2145 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2146 /* TODO: access new SCD registers and dump them */
2147 return;
38398efb 2148 }
afb84431
EG		 2149
2150 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2151 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2152 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2153
2154 IWL_ERR(trans,
2155 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2156 txq_id, active ? "" : "in", fifo,
2157 jiffies_to_msecs(txq->wd_timeout),
2158 txq->read_ptr, txq->write_ptr,
2159 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2160 (TFD_QUEUE_SIZE_MAX - 1),
2161 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2162 (TFD_QUEUE_SIZE_MAX - 1),
2163 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2164}
2165
d6d517b7 2166static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2167{
8ad71bef 2168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2169 struct iwl_txq *txq;
5f178cd2 2170 unsigned long now = jiffies;
d6d517b7
SS		 2171 u8 wr_ptr;
2172
2173 if (!test_bit(txq_idx, trans_pcie->queue_used))
2174 return -EINVAL;
2175
2176 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2177 txq = trans_pcie->txq[txq_idx];
6aa7de05 2178 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2179
6aa7de05 2180 while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
d6d517b7
SS		 2181 !time_after(jiffies,
2182 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2183 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7
SS		 2184
2185 if (WARN_ONCE(wr_ptr != write_ptr,
2186 "WR pointer moved while flushing %d -> %d\n",
2187 wr_ptr, write_ptr))
2188 return -ETIMEDOUT;
2189 usleep_range(1000, 2000);
2190 }
2191
2192 if (txq->read_ptr != txq->write_ptr) {
2193 IWL_ERR(trans,
2194 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2195 iwl_trans_pcie_log_scd_error(trans, txq);
2196 return -ETIMEDOUT;
2197 }
2198
2199 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2200
2201 return 0;
2202}
2203
2204static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2205{
2206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2207 int cnt;
5f178cd2
EG		 2208 int ret = 0;
2209
2210 /* waiting for all the tx frames complete might take a while */
035f7ff2 2211 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd 2212
9ba1947a 2213 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2214 continue;
3cafdbe6
EG		 2215 if (!test_bit(cnt, trans_pcie->queue_used))
2216 continue;
2217 if (!(BIT(cnt) & txq_bm))
2218 continue;
748fa67c 2219
d6d517b7
SS		 2220 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2221 if (ret)
5f178cd2 2222 break;
5f178cd2 2223 }
1c3fea82 2224
5f178cd2
EG		 2225 return ret;
2226}
2227
e139dc4a
LE		 2228static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2229 u32 mask, u32 value)
2230{
e56b04ef 2231 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2232 unsigned long flags;
2233
e56b04ef 2234 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2235 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2236 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2237}
2238
c24c7f58 2239static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2240{
2241 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2242
2243 if (iwlwifi_mod_params.d0i3_disable)
2244 return;
2245
b3ff1270 2246 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2247
2248#ifdef CONFIG_PM
2249 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2250 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2251#endif /* CONFIG_PM */
7616f334
EP		 2252}
2253
c24c7f58 2254static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2255{
2256 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2257
2258 if (iwlwifi_mod_params.d0i3_disable)
2259 return;
2260
b3ff1270
LC		 2261 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2262 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2263
5d93f3a2
LC		 2264#ifdef CONFIG_PM
2265 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2266 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2267#endif /* CONFIG_PM */
7616f334
EP		 2268}
2269
ff620849
EG		 2270static const char *get_csr_string(int cmd)
2271{
d9fb6465 2272#define IWL_CMD(x) case x: return #x
ff620849
EG		 2273 switch (cmd) {
2274 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2275 IWL_CMD(CSR_INT_COALESCING);
2276 IWL_CMD(CSR_INT);
2277 IWL_CMD(CSR_INT_MASK);
2278 IWL_CMD(CSR_FH_INT_STATUS);
2279 IWL_CMD(CSR_GPIO_IN);
2280 IWL_CMD(CSR_RESET);
2281 IWL_CMD(CSR_GP_CNTRL);
2282 IWL_CMD(CSR_HW_REV);
2283 IWL_CMD(CSR_EEPROM_REG);
2284 IWL_CMD(CSR_EEPROM_GP);
2285 IWL_CMD(CSR_OTP_GP_REG);
2286 IWL_CMD(CSR_GIO_REG);
2287 IWL_CMD(CSR_GP_UCODE_REG);
2288 IWL_CMD(CSR_GP_DRIVER_REG);
2289 IWL_CMD(CSR_UCODE_DRV_GP1);
2290 IWL_CMD(CSR_UCODE_DRV_GP2);
2291 IWL_CMD(CSR_LED_REG);
2292 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2293 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2294 IWL_CMD(CSR_ANA_PLL_CFG);
2295 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2296 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2297 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2298 default:
2299 return "UNKNOWN";
2300 }
d9fb6465 2301#undef IWL_CMD
ff620849
EG		 2302}
2303
990aa6d7 2304void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2305{
2306 int i;
2307 static const u32 csr_tbl[] = {
2308 CSR_HW_IF_CONFIG_REG,
2309 CSR_INT_COALESCING,
2310 CSR_INT,
2311 CSR_INT_MASK,
2312 CSR_FH_INT_STATUS,
2313 CSR_GPIO_IN,
2314 CSR_RESET,
2315 CSR_GP_CNTRL,
2316 CSR_HW_REV,
2317 CSR_EEPROM_REG,
2318 CSR_EEPROM_GP,
2319 CSR_OTP_GP_REG,
2320 CSR_GIO_REG,
2321 CSR_GP_UCODE_REG,
2322 CSR_GP_DRIVER_REG,
2323 CSR_UCODE_DRV_GP1,
2324 CSR_UCODE_DRV_GP2,
2325 CSR_LED_REG,
2326 CSR_DRAM_INT_TBL_REG,
2327 CSR_GIO_CHICKEN_BITS,
2328 CSR_ANA_PLL_CFG,
a812cba9 2329 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2330 CSR_HW_REV_WA_REG,
2331 CSR_DBG_HPET_MEM_REG
2332 };
2333 IWL_ERR(trans, "CSR values:\n");
2334 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2335 "CSR_INT_PERIODIC_REG)\n");
2336 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2337 IWL_ERR(trans, " %25s: 0X%08x\n",
2338 get_csr_string(csr_tbl[i]),
1042db2a 2339 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2340 }
2341}
2342
87e5666c
EG		 2343#ifdef CONFIG_IWLWIFI_DEBUGFS
2344/* create and remove of files */
2345#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2346 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2347 &iwl_dbgfs_##name##_ops)) \
9da987ac 2348 goto err; \
87e5666c
EG		 2349} while (0)
2350
2351/* file operation */
87e5666c 2352#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2353static const struct file_operations iwl_dbgfs_##name##_ops = { \
2354 .read = iwl_dbgfs_##name##_read, \
234e3405 2355 .open = simple_open, \
87e5666c
EG		 2356 .llseek = generic_file_llseek, \
2357};
2358
16db88ba 2359#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2360static const struct file_operations iwl_dbgfs_##name##_ops = { \
2361 .write = iwl_dbgfs_##name##_write, \
234e3405 2362 .open = simple_open, \
16db88ba
EG		 2363 .llseek = generic_file_llseek, \
2364};
2365
87e5666c 2366#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2367static const struct file_operations iwl_dbgfs_##name##_ops = { \
2368 .write = iwl_dbgfs_##name##_write, \
2369 .read = iwl_dbgfs_##name##_read, \
234e3405 2370 .open = simple_open, \
87e5666c
EG		 2371 .llseek = generic_file_llseek, \
2372};
2373
87e5666c 2374static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2375 char __user *user_buf,
2376 size_t count, loff_t *ppos)
8ad71bef 2377{
5a878bf6 2378 struct iwl_trans *trans = file->private_data;
8ad71bef 2379 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2380 struct iwl_txq *txq;
87e5666c
EG		 2381 char *buf;
2382 int pos = 0;
2383 int cnt;
2384 int ret;
1745e440
WYG		 2385 size_t bufsz;
2386
e0b8d405 2387 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2388
b2a3b1c1 2389 if (!trans_pcie->txq_memory)
87e5666c 2390 return -EAGAIN;
f9e75447 2391
87e5666c
EG		 2392 buf = kzalloc(bufsz, GFP_KERNEL);
2393 if (!buf)
2394 return -ENOMEM;
2395
035f7ff2 2396 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2397 txq = trans_pcie->txq[cnt];
87e5666c 2398 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2399 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2400 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2401 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2402 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2403 txq->need_update, txq->frozen,
f40faf62 2404 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2405 }
2406 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2407 kfree(buf);
2408 return ret;
2409}
2410
2411static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2412 char __user *user_buf,
2413 size_t count, loff_t *ppos)
2414{
5a878bf6 2415 struct iwl_trans *trans = file->private_data;
20d3b647 2416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2417 char *buf;
2418 int pos = 0, i, ret;
2419 size_t bufsz = sizeof(buf);
2420
2421 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2422
2423 if (!trans_pcie->rxq)
2424 return -EAGAIN;
2425
2426 buf = kzalloc(bufsz, GFP_KERNEL);
2427 if (!buf)
2428 return -ENOMEM;
2429
2430 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2431 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2432
2433 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2434 i);
2435 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2436 rxq->read);
2437 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2438 rxq->write);
2439 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2440 rxq->write_actual);
2441 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2442 rxq->need_update);
2443 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2444 rxq->free_count);
2445 if (rxq->rb_stts) {
2446 pos += scnprintf(buf + pos, bufsz - pos,
2447 "\tclosed_rb_num: %u\n",
2448 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2449 0x0FFF);
2450 } else {
2451 pos += scnprintf(buf + pos, bufsz - pos,
2452 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2453 }
87e5666c 2454 }
78485054
SS		 2455 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2456 kfree(buf);
2457
2458 return ret;
87e5666c
EG		 2459}
2460
1f7b6172
EG		 2461static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2462 char __user *user_buf,
20d3b647
JB		 2463 size_t count, loff_t *ppos)
2464{
1f7b6172 2465 struct iwl_trans *trans = file->private_data;
20d3b647 2466 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2467 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2468
2469 int pos = 0;
2470 char *buf;
2471 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2472 ssize_t ret;
2473
2474 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2475 if (!buf)
1f7b6172 2476 return -ENOMEM;
1f7b6172
EG		 2477
2478 pos += scnprintf(buf + pos, bufsz - pos,
2479 "Interrupt Statistics Report:\n");
2480
2481 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2482 isr_stats->hw);
2483 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2484 isr_stats->sw);
2485 if (isr_stats->sw || isr_stats->hw) {
2486 pos += scnprintf(buf + pos, bufsz - pos,
2487 "\tLast Restarting Code: 0x%X\n",
2488 isr_stats->err_code);
2489 }
2490#ifdef CONFIG_IWLWIFI_DEBUG
2491 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2492 isr_stats->sch);
2493 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2494 isr_stats->alive);
2495#endif
2496 pos += scnprintf(buf + pos, bufsz - pos,
2497 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2498
2499 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2500 isr_stats->ctkill);
2501
2502 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2503 isr_stats->wakeup);
2504
2505 pos += scnprintf(buf + pos, bufsz - pos,
2506 "Rx command responses:\t\t %u\n", isr_stats->rx);
2507
2508 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2509 isr_stats->tx);
2510
2511 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2512 isr_stats->unhandled);
2513
2514 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2515 kfree(buf);
2516 return ret;
2517}
2518
2519static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2520 const char __user *user_buf,
2521 size_t count, loff_t *ppos)
2522{
2523 struct iwl_trans *trans = file->private_data;
20d3b647 2524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2525 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2526 u32 reset_flag;
078f1131 2527 int ret;
1f7b6172 2528
078f1131
JB		 2529 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2530 if (ret)
2531 return ret;
1f7b6172
EG		 2532 if (reset_flag == 0)
2533 memset(isr_stats, 0, sizeof(*isr_stats));
2534
2535 return count;
2536}
2537
16db88ba 2538static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2539 const char __user *user_buf,
2540 size_t count, loff_t *ppos)
16db88ba
EG		 2541{
2542 struct iwl_trans *trans = file->private_data;
16db88ba 2543
990aa6d7 2544 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2545
2546 return count;
2547}
2548
16db88ba 2549static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2550 char __user *user_buf,
2551 size_t count, loff_t *ppos)
16db88ba
EG		 2552{
2553 struct iwl_trans *trans = file->private_data;
94543a8d 2554 char *buf = NULL;
56c2477f 2555 ssize_t ret;
16db88ba 2556
56c2477f
JB		 2557 ret = iwl_dump_fh(trans, &buf);
2558 if (ret < 0)
2559 return ret;
2560 if (!buf)
2561 return -EINVAL;
2562 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2563 kfree(buf);
16db88ba
EG		 2564 return ret;
2565}
2566
fa4de7f7
JB		 2567static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2568 char __user *user_buf,
2569 size_t count, loff_t *ppos)
2570{
2571 struct iwl_trans *trans = file->private_data;
2572 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2573 char buf[100];
2574 int pos;
2575
2576 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2577 trans_pcie->debug_rfkill,
2578 !(iwl_read32(trans, CSR_GP_CNTRL) &
2579 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2580
2581 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2582}
2583
2584static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2585 const char __user *user_buf,
2586 size_t count, loff_t *ppos)
2587{
2588 struct iwl_trans *trans = file->private_data;
2589 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2590 bool old = trans_pcie->debug_rfkill;
2591 int ret;
2592
2593 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2594 if (ret)
2595 return ret;
2596 if (old == trans_pcie->debug_rfkill)
2597 return count;
2598 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2599 old, trans_pcie->debug_rfkill);
2600 iwl_pcie_handle_rfkill_irq(trans);
2601
2602 return count;
2603}
2604
1f7b6172 2605DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2606DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2607DEBUGFS_READ_FILE_OPS(rx_queue);
2608DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2609DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2610DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2611
f8a1edb7
JB		 2612/* Create the debugfs files and directories */
2613int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2614{
f8a1edb7
JB		 2615 struct dentry *dir = trans->dbgfs_dir;
2616
87e5666c
EG		 2617 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2618 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2619 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2620 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2621 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
fa4de7f7 2622 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
87e5666c 2623 return 0;
9da987ac
MV		 2624
2625err:
2626 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2627 return -ENOMEM;
87e5666c 2628}
aadede6e 2629#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2630
6983ba69 2631static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2632{
3cd1980b 2633 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2634 u32 cmdlen = 0;
2635 int i;
2636
3cd1980b 2637 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2638 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2639
2640 return cmdlen;
2641}
2642
bd7fc617
EG		 2643static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2644 struct iwl_fw_error_dump_data **data,
2645 int allocated_rb_nums)
2646{
2647 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2648 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2649 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2650 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2651 u32 i, r, j, rb_len = 0;
2652
2653 spin_lock(&rxq->lock);
2654
6aa7de05 2655 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
bd7fc617
EG		 2656
2657 for (i = rxq->read, j = 0;
2658 i != r && j < allocated_rb_nums;
2659 i = (i + 1) & RX_QUEUE_MASK, j++) {
2660 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2661 struct iwl_fw_error_dump_rb *rb;
2662
2663 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2664 DMA_FROM_DEVICE);
2665
2666 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2667
2668 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2669 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2670 rb = (void *)(*data)->data;
2671 rb->index = cpu_to_le32(i);
2672 memcpy(rb->data, page_address(rxb->page), max_len);
2673 /* remap the page for the free benefit */
2674 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2675 max_len,
2676 DMA_FROM_DEVICE);
2677
2678 *data = iwl_fw_error_next_data(*data);
2679 }
2680
2681 spin_unlock(&rxq->lock);
2682
2683 return rb_len;
2684}
473ad712
EG		 2685#define IWL_CSR_TO_DUMP (0x250)
2686
2687static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2688 struct iwl_fw_error_dump_data **data)
2689{
2690 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2691 __le32 *val;
2692 int i;
2693
2694 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2695 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2696 val = (void *)(*data)->data;
2697
2698 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2699 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2700
2701 *data = iwl_fw_error_next_data(*data);
2702
2703 return csr_len;
2704}
2705
06d51e0d
LK		 2706static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2707 struct iwl_fw_error_dump_data **data)
2708{
2709 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2710 unsigned long flags;
2711 __le32 *val;
2712 int i;
2713
23ba9340 2714 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2715 return 0;
2716
2717 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2718 (*data)->len = cpu_to_le32(fh_regs_len);
2719 val = (void *)(*data)->data;
2720
723b45e2
LK		 2721 if (!trans->cfg->gen2)
2722 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2723 i += sizeof(u32))
2724 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2725 else
2726 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2727 i += sizeof(u32))
2728 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2729 i));
06d51e0d
LK		 2730
2731 iwl_trans_release_nic_access(trans, &flags);
2732
2733 *data = iwl_fw_error_next_data(*data);
2734
2735 return sizeof(**data) + fh_regs_len;
2736}
2737
cc79ef66
LK		 2738static u32
2739iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2740 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2741 u32 monitor_len)
2742{
2743 u32 buf_size_in_dwords = (monitor_len >> 2);
2744 u32 *buffer = (u32 *)fw_mon_data->data;
2745 unsigned long flags;
2746 u32 i;
2747
23ba9340 2748 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2749 return 0;
2750
14ef1b43 2751 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2752 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2753 buffer[i] = iwl_read_prph_no_grab(trans,
2754 MON_DMARB_RD_DATA_ADDR);
2755 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2756
2757 iwl_trans_release_nic_access(trans, &flags);
2758
2759 return monitor_len;
2760}
2761
36fb9017
OG		 2762static u32
2763iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2764 struct iwl_fw_error_dump_data **data,
2765 u32 monitor_len)
2766{
2767 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2768 u32 len = 0;
2769
2770 if ((trans_pcie->fw_mon_page &&
2771 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2772 trans->dbg_dest_tlv) {
2773 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2774 u32 base, write_ptr, wrap_cnt;
2775
2776 /* If there was a dest TLV - use the values from there */
2777 if (trans->dbg_dest_tlv) {
2778 write_ptr =
2779 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2780 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2781 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2782 } else {
2783 base = MON_BUFF_BASE_ADDR;
2784 write_ptr = MON_BUFF_WRPTR;
2785 wrap_cnt = MON_BUFF_CYCLE_CNT;
2786 }
2787
2788 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2789 fw_mon_data = (void *)(*data)->data;
2790 fw_mon_data->fw_mon_wr_ptr =
2791 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2792 fw_mon_data->fw_mon_cycle_cnt =
2793 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2794 fw_mon_data->fw_mon_base_ptr =
2795 cpu_to_le32(iwl_read_prph(trans, base));
2796
2797 len += sizeof(**data) + sizeof(*fw_mon_data);
2798 if (trans_pcie->fw_mon_page) {
2799 /*
2800 * The firmware is now asserted, it won't write anything
2801 * to the buffer. CPU can take ownership to fetch the
2802 * data. The buffer will be handed back to the device
2803 * before the firmware will be restarted.
2804 */
2805 dma_sync_single_for_cpu(trans->dev,
2806 trans_pcie->fw_mon_phys,
2807 trans_pcie->fw_mon_size,
2808 DMA_FROM_DEVICE);
2809 memcpy(fw_mon_data->data,
2810 page_address(trans_pcie->fw_mon_page),
2811 trans_pcie->fw_mon_size);
2812
2813 monitor_len = trans_pcie->fw_mon_size;
2814 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2815 /*
2816 * Update pointers to reflect actual values after
2817 * shifting
2818 */
2819 base = iwl_read_prph(trans, base) <<
2820 trans->dbg_dest_tlv->base_shift;
2821 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2822 monitor_len / sizeof(u32));
2823 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2824 monitor_len =
2825 iwl_trans_pci_dump_marbh_monitor(trans,
2826 fw_mon_data,
2827 monitor_len);
2828 } else {
2829 /* Didn't match anything - output no monitor data */
2830 monitor_len = 0;
2831 }
2832
2833 len += monitor_len;
2834 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2835 }
2836
2837 return len;
2838}
2839
2840static struct iwl_trans_dump_data
2841*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2842 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2843{
2844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2845 struct iwl_fw_error_dump_data *data;
b2a3b1c1 2846 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
4d075007 2847 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2848 struct iwl_trans_dump_data *dump_data;
bd7fc617 2849 u32 len, num_rbs;
99684ae3 2850 u32 monitor_len;
4d075007 2851 int i, ptr;
96a6497b
SS		 2852 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2853 !trans->cfg->mq_rx_supported;
4d075007 2854
473ad712
EG		 2855 /* transport dump header */
2856 len = sizeof(*dump_data);
2857
2858 /* host commands */
2859 len += sizeof(*data) +
bb98ecd4 2860 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2861
473ad712 2862 /* FW monitor */
99684ae3 2863 if (trans_pcie->fw_mon_page) {
c544e9c4 2864 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2865 trans_pcie->fw_mon_size;
2866 monitor_len = trans_pcie->fw_mon_size;
2867 } else if (trans->dbg_dest_tlv) {
2868 u32 base, end;
2869
2870 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2871 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2872
2873 base = iwl_read_prph(trans, base) <<
2874 trans->dbg_dest_tlv->base_shift;
2875 end = iwl_read_prph(trans, end) <<
2876 trans->dbg_dest_tlv->end_shift;
2877
2878 /* Make "end" point to the actual end */
6e584873 2879 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 ||
cc79ef66 2880 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2881 end += (1 << trans->dbg_dest_tlv->end_shift);
2882 monitor_len = end - base;
2883 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2884 monitor_len;
2885 } else {
2886 monitor_len = 0;
2887 }
c2d20201 2888
36fb9017
OG		 2889 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2890 dump_data = vzalloc(len);
2891 if (!dump_data)
2892 return NULL;
2893
2894 data = (void *)dump_data->data;
2895 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2896 dump_data->len = len;
2897
2898 return dump_data;
2899 }
2900
2901 /* CSR registers */
2902 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2903
36fb9017 2904 /* FH registers */
723b45e2
LK		 2905 if (trans->cfg->gen2)
2906 len += sizeof(*data) +
2907 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2908 else
2909 len += sizeof(*data) +
2910 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
36fb9017
OG		 2911
2912 if (dump_rbs) {
78485054
SS		 2913 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2914 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2915 /* RBs */
6aa7de05 2916 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2917 & 0x0FFF;
78485054 2918 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2919 len += num_rbs * (sizeof(*data) +
2920 sizeof(struct iwl_fw_error_dump_rb) +
2921 (PAGE_SIZE << trans_pcie->rx_page_order));
2922 }
2923
5538409b
LK		 2924 /* Paged memory for gen2 HW */
2925 if (trans->cfg->gen2)
2926 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2927 len += sizeof(*data) +
2928 sizeof(struct iwl_fw_error_dump_paging) +
2929 trans_pcie->init_dram.paging[i].size;
2930
48eb7b34
EG		 2931 dump_data = vzalloc(len);
2932 if (!dump_data)
2933 return NULL;
4d075007
JB		 2934
2935 len = 0;
48eb7b34 2936 data = (void *)dump_data->data;
4d075007
JB		 2937 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2938 txcmd = (void *)data->data;
2939 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 2940 ptr = cmdq->write_ptr;
2941 for (i = 0; i < cmdq->n_window; i++) {
4ecab561 2942 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
4d075007
JB		 2943 u32 caplen, cmdlen;
2944
6983ba69
SS		 2945 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2946 trans_pcie->tfd_size * ptr);
4d075007
JB		 2947 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2948
2949 if (cmdlen) {
2950 len += sizeof(*txcmd) + caplen;
2951 txcmd->cmdlen = cpu_to_le32(cmdlen);
2952 txcmd->caplen = cpu_to_le32(caplen);
2953 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2954 txcmd = (void *)((u8 *)txcmd->data + caplen);
2955 }
2956
2957 ptr = iwl_queue_dec_wrap(ptr);
2958 }
2959 spin_unlock_bh(&cmdq->lock);
2960
2961 data->len = cpu_to_le32(len);
c2d20201 2962 len += sizeof(*data);
67c65f2c
EG		 2963 data = iwl_fw_error_next_data(data);
2964
473ad712 2965 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2966 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2967 if (dump_rbs)
2968 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2969
5538409b
LK		 2970 /* Paged memory for gen2 HW */
2971 if (trans->cfg->gen2) {
2972 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2973 struct iwl_fw_error_dump_paging *paging;
2974 dma_addr_t addr =
2975 trans_pcie->init_dram.paging[i].physical;
2976 u32 page_len = trans_pcie->init_dram.paging[i].size;
2977
2978 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2979 data->len = cpu_to_le32(sizeof(*paging) + page_len);
2980 paging = (void *)data->data;
2981 paging->index = cpu_to_le32(i);
2982 dma_sync_single_for_cpu(trans->dev, addr, page_len,
2983 DMA_BIDIRECTIONAL);
2984 memcpy(paging->data,
2985 trans_pcie->init_dram.paging[i].block, page_len);
2986 data = iwl_fw_error_next_data(data);
2987
2988 len += sizeof(*data) + sizeof(*paging) + page_len;
2989 }
2990 }
2991
36fb9017 2992 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2993
48eb7b34
EG		 2994 dump_data->len = len;
2995
2996 return dump_data;
4d075007 2997}
87e5666c 2998
4cbb8e50
LC		 2999#ifdef CONFIG_PM_SLEEP
3000static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3001{
e4c49c49
LC		 3002 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3003 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3004 return iwl_pci_fw_enter_d0i3(trans);
3005
3006 return 0;
3007}
3008
3009static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3010{
e4c49c49
LC		 3011 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3012 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3013 iwl_pci_fw_exit_d0i3(trans);
3014}
3015#endif /* CONFIG_PM_SLEEP */
3016
623e7766
SS		 3017#define IWL_TRANS_COMMON_OPS \
3018 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3019 .write8 = iwl_trans_pcie_write8, \
3020 .write32 = iwl_trans_pcie_write32, \
3021 .read32 = iwl_trans_pcie_read32, \
3022 .read_prph = iwl_trans_pcie_read_prph, \
3023 .write_prph = iwl_trans_pcie_write_prph, \
3024 .read_mem = iwl_trans_pcie_read_mem, \
3025 .write_mem = iwl_trans_pcie_write_mem, \
3026 .configure = iwl_trans_pcie_configure, \
3027 .set_pmi = iwl_trans_pcie_set_pmi, \
3028 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3029 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3030 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3031 .ref = iwl_trans_pcie_ref, \
3032 .unref = iwl_trans_pcie_unref, \
3033 .dump_data = iwl_trans_pcie_dump_data, \
fb12777a 3034 .dump_regs = iwl_trans_pcie_dump_regs, \
623e7766
SS		 3035 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3036 .d3_resume = iwl_trans_pcie_d3_resume
3037
3038#ifdef CONFIG_PM_SLEEP
3039#define IWL_TRANS_PM_OPS \
3040 .suspend = iwl_trans_pcie_suspend, \
3041 .resume = iwl_trans_pcie_resume,
3042#else
3043#define IWL_TRANS_PM_OPS
3044#endif /* CONFIG_PM_SLEEP */
3045
d1ff5253 3046static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3047 IWL_TRANS_COMMON_OPS,
3048 IWL_TRANS_PM_OPS
57a1dc89 3049 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3050 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3051 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3052 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3053
623e7766 3054 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3055
623e7766
SS		 3056 .tx = iwl_trans_pcie_tx,
3057 .reclaim = iwl_trans_pcie_reclaim,
3058
3059 .txq_disable = iwl_trans_pcie_txq_disable,
3060 .txq_enable = iwl_trans_pcie_txq_enable,
3061
3062 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3063
d6d517b7
SS		 3064 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3065
623e7766
SS		 3066 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3067 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3068};
3069
3070static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3071 IWL_TRANS_COMMON_OPS,
3072 IWL_TRANS_PM_OPS
3073 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3074 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3075 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3076 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3077
ca60da2e 3078 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3079
ab6c6445 3080 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3081 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3082
6b35ff91
SS		 3083 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3084 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3085 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
e6bb4c9c 3086};
a42a1844 3087
87ce05a2 3088struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 3089 const struct pci_device_id *ent,
3090 const struct iwl_cfg *cfg)
a42a1844 3091{
a42a1844
EG		 3092 struct iwl_trans_pcie *trans_pcie;
3093 struct iwl_trans *trans;
96a6497b 3094 int ret, addr_size;
a42a1844 3095
5a41a86c
SD		 3096 ret = pcim_enable_device(pdev);
3097 if (ret)
3098 return ERR_PTR(ret);
3099
623e7766
SS		 3100 if (cfg->gen2)
3101 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3102 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3103 else
3104 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3105 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 3106 if (!trans)
3107 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3108
3109 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3110
a42a1844 3111 trans_pcie->trans = trans;
326477e4 3112 trans_pcie->opmode_down = true;
7b11488f 3113 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3114 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3115 mutex_init(&trans_pcie->mutex);
13df1aab 3116 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 3117 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3118 if (!trans_pcie->tso_hdr_page) {
3119 ret = -ENOMEM;
3120 goto out_no_pci;
3121 }
a42a1844 3122
d819c6cf 3123
f2532b04
EG		 3124 if (!cfg->base_params->pcie_l1_allowed) {
3125 /*
3126 * W/A - seems to solve weird behavior. We need to remove this
3127 * if we don't want to stay in L1 all the time. This wastes a
3128 * lot of power.
3129 */
3130 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3131 PCIE_LINK_STATE_L1 |
3132 PCIE_LINK_STATE_CLKPM);
3133 }
a42a1844 3134
6983ba69 3135 if (cfg->use_tfh) {
2c6262b7 3136 addr_size = 64;
3cd1980b 3137 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3138 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3139 } else {
2c6262b7 3140 addr_size = 36;
3cd1980b 3141 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3142 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3143 }
3cd1980b
SS		 3144 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3145
a42a1844
EG		 3146 pci_set_master(pdev);
3147
96a6497b 3148 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3149 if (!ret)
96a6497b
SS		 3150 ret = pci_set_consistent_dma_mask(pdev,
3151 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3152 if (ret) {
3153 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3154 if (!ret)
3155 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3156 DMA_BIT_MASK(32));
a42a1844 3157 /* both attempts failed: */
af3f2f74 3158 if (ret) {
6a4b09f8 3159 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3160 goto out_no_pci;
a42a1844
EG		 3161 }
3162 }
3163
5a41a86c 3164 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3165 if (ret) {
5a41a86c
SD		 3166 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3167 goto out_no_pci;
a42a1844
EG		 3168 }
3169
5a41a86c 3170 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3171 if (!trans_pcie->hw_base) {
5a41a86c 3172 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3173 ret = -ENODEV;
5a41a86c 3174 goto out_no_pci;
a42a1844
EG		 3175 }
3176
a42a1844
EG		 3177 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3178 * PCI Tx retries from interfering with C3 CPU state */
3179 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3180
83f7a85f
EG		 3181 trans_pcie->pci_dev = pdev;
3182 iwl_disable_interrupts(trans);
3183
08079a49 3184 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3185 /*
3186 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3187 * changed, and now the revision step also includes bit 0-1 (no more
3188 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3189 * in the old format.
3190 */
6e584873 3191 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
7a42baa6 3192 unsigned long flags;
7a42baa6 3193
b513ee7f 3194 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3195 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3196
f9e5554c
EG		 3197 ret = iwl_pcie_prepare_card_hw(trans);
3198 if (ret) {
3199 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3200 goto out_no_pci;
f9e5554c
EG		 3201 }
3202
7a42baa6
EH		 3203 /*
3204 * in-order to recognize C step driver should read chip version
3205 * id located at the AUX bus MISC address space.
3206 */
3207 iwl_set_bit(trans, CSR_GP_CNTRL,
3208 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3209 udelay(2);
3210
3211 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3212 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3213 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3214 25000);
3215 if (ret < 0) {
3216 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3217 goto out_no_pci;
7a42baa6
EH		 3218 }
3219
23ba9340 3220 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3221 u32 hw_step;
3222
14ef1b43 3223 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3224 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3225 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3226 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3227 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3228 if (hw_step == 0x3)
3229 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3230 (SILICON_C_STEP << 2);
3231 iwl_trans_release_nic_access(trans, &flags);
3232 }
3233 }
3234
c00ee467
JB		 3235 /*
3236 * 9000-series integrated A-step has a problem with suspend/resume
3237 * and sometimes even causes the whole platform to get stuck. This
3238 * workaround makes the hardware not go into the problematic state.
3239 */
3240 if (trans->cfg->integrated &&
3241 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3242 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3243 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3244 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3245
f6586b69 3246#if IS_ENABLED(CONFIG_IWLMVM)
1afb0ae4 3247 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
f6586b69
TP		 3248 if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3249 u32 hw_status;
3250
3251 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3252 if (hw_status & UMAG_GEN_HW_IS_FPGA)
2f7a3863 3253 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_f0;
f6586b69 3254 else
2f7a3863 3255 trans->cfg = &iwl22000_2ac_cfg_hr;
f6586b69
TP		 3256 }
3257#endif
1afb0ae4 3258
2e5d4a8f 3259 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3260 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3261 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3262 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3263
69a10b29 3264 /* Initialize the wait queue for commands */
f946b529 3265 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3266
4cbb8e50
LC		 3267 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3268
2e5d4a8f 3269 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3270 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3271 if (ret)
5a41a86c 3272 goto out_no_pci;
2e5d4a8f
HD		 3273 } else {
3274 ret = iwl_pcie_alloc_ict(trans);
3275 if (ret)
5a41a86c 3276 goto out_no_pci;
a8b691e6 3277
5a41a86c
SD		 3278 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3279 iwl_pcie_isr,
3280 iwl_pcie_irq_handler,
3281 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3282 if (ret) {
3283 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3284 goto out_free_ict;
3285 }
3286 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3287 }
83f7a85f 3288
10a54d81
LC		 3289 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3290 WQ_HIGHPRI | WQ_UNBOUND, 1);
3291 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3292
b3ff1270
LC		 3293#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3294 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3295#else
3296 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3297#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3298
a42a1844
EG		 3299 return trans;
3300
a8b691e6
JB		 3301out_free_ict:
3302 iwl_pcie_free_ict(trans);
a42a1844 3303out_no_pci:
6eb5e529 3304 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3305 iwl_trans_free(trans);
af3f2f74 3306 return ERR_PTR(ret);
a42a1844 3307}
Linux 6.x block layer and io_uring tree(s)