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iwlwifi: mvm: no need to check return value of debugfs_create functions
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 11 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
c85eb619 22 * The full GNU General Public License is included in this distribution
410dc5aa 23 * in the file called COPYING.
c85eb619
EG		 24 *
25 * Contact Information:
cb2f8277 26 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
553452e5
LK		 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 34 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
a42a1844
EG		 64#include <linux/pci.h>
65#include <linux/pci-aspm.h>
e6bb4c9c 66#include <linux/interrupt.h>
87e5666c 67#include <linux/debugfs.h>
cf614297 68#include <linux/sched.h>
6d8f6eeb
EG		 69#include <linux/bitops.h>
70#include <linux/gfp.h>
48eb7b34 71#include <linux/vmalloc.h>
b3ff1270 72#include <linux/pm_runtime.h>
49564a80 73#include <linux/module.h>
f7805b33 74#include <linux/wait.h>
e6bb4c9c 75
82575102 76#include "iwl-drv.h"
c85eb619 77#include "iwl-trans.h"
522376d2
EG		 78#include "iwl-csr.h"
79#include "iwl-prph.h"
cb6bb128 80#include "iwl-scd.h"
7a10e3e4 81#include "iwl-agn-hw.h"
d962f9b1 82#include "fw/error-dump.h"
520f03ea 83#include "fw/dbg.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
4290eaad 91void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad
RJ		 92{
93#define PCI_DUMP_SIZE 64
94#define PREFIX_LEN 32
95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
96 struct pci_dev *pdev = trans_pcie->pci_dev;
97 u32 i, pos, alloc_size, *ptr, *buf;
98 char *prefix;
99
100 if (trans_pcie->pcie_dbg_dumped_once)
101 return;
102
103 /* Should be a multiple of 4 */
104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
105 /* Alloc a max size buffer */
106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
108 else
109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
110 buf = kmalloc(alloc_size, GFP_ATOMIC);
111 if (!buf)
112 return;
113 prefix = (char *)buf + alloc_size - PREFIX_LEN;
114
115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
116
117 /* Print wifi device registers */
118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
119 IWL_ERR(trans, "iwlwifi device config registers:\n");
120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
121 if (pci_read_config_dword(pdev, i, ptr))
122 goto err_read;
123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
124
125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
127 *ptr = iwl_read32(trans, i);
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
129
130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
131 if (pos) {
132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
134 if (pci_read_config_dword(pdev, pos + i, ptr))
135 goto err_read;
136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
137 32, 4, buf, i, 0);
138 }
139
140 /* Print parent device registers next */
141 if (!pdev->bus->self)
142 goto out;
143
144 pdev = pdev->bus->self;
145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
146
147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
148 pci_name(pdev));
149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
150 if (pci_read_config_dword(pdev, i, ptr))
151 goto err_read;
152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
153
154 /* Print root port AER registers */
155 pos = 0;
156 pdev = pcie_find_root_port(pdev);
157 if (pdev)
158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
159 if (pos) {
160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
161 pci_name(pdev));
162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
164 if (pci_read_config_dword(pdev, pos + i, ptr))
165 goto err_read;
166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
167 4, buf, i, 0);
168 }
f3402d6d 169 goto out;
a6d24fad
RJ		 170
171err_read:
172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
173 IWL_ERR(trans, "Read failed at 0x%X\n", i);
174out:
175 trans_pcie->pcie_dbg_dumped_once = 1;
176 kfree(buf);
177}
178
870c2a11
GBA		 179static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
180{
181 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
a8cbb46f
GBA		 182 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
183 BIT(trans->cfg->csr->flag_sw_reset));
870c2a11
GBA		 184 usleep_range(5000, 6000);
185}
186
c2d20201
EG		 187static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
188{
88964b2e 189 int i;
c2d20201 190
88964b2e
SS		 191 for (i = 0; i < trans->num_blocks; i++) {
192 dma_free_coherent(trans->dev, trans->fw_mon[i].size,
193 trans->fw_mon[i].block,
194 trans->fw_mon[i].physical);
195 trans->fw_mon[i].block = NULL;
196 trans->fw_mon[i].physical = 0;
197 trans->fw_mon[i].size = 0;
198 trans->num_blocks--;
199 }
c2d20201
EG		 200}
201
88964b2e
SS		 202static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
203 u8 max_power, u8 min_power)
c2d20201 204{
c5f97542 205 void *cpu_addr = NULL;
88964b2e 206 dma_addr_t phys = 0;
96c285da 207 u32 size = 0;
c2d20201
EG		 208 u8 power;
209
88964b2e 210 for (power = max_power; power >= min_power; power--) {
c2d20201 211 size = BIT(power);
c5f97542
SM		 212 cpu_addr = dma_alloc_coherent(trans->dev, size, &phys,
213 GFP_KERNEL | __GFP_NOWARN |
214 __GFP_ZERO | __GFP_COMP);
215 if (!cpu_addr)
c2d20201
EG		 216 continue;
217
c2d20201 218 IWL_INFO(trans,
c5f97542
SM		 219 "Allocated 0x%08x bytes for firmware monitor.\n",
220 size);
c2d20201
EG		 221 break;
222 }
223
c5f97542 224 if (WARN_ON_ONCE(!cpu_addr))
c2d20201
EG		 225 return;
226
96c285da
EG		 227 if (power != max_power)
228 IWL_ERR(trans,
229 "Sorry - debug buffer is only %luK while you requested %luK\n",
230 (unsigned long)BIT(power - 10),
231 (unsigned long)BIT(max_power - 10));
232
88964b2e
SS		 233 trans->fw_mon[trans->num_blocks].block = cpu_addr;
234 trans->fw_mon[trans->num_blocks].physical = phys;
235 trans->fw_mon[trans->num_blocks].size = size;
236 trans->num_blocks++;
237}
238
239void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
240{
241 if (!max_power) {
242 /* default max_power is maximum */
243 max_power = 26;
244 } else {
245 max_power += 11;
246 }
247
248 if (WARN(max_power > 26,
249 "External buffer size for monitor is too big %d, check the FW TLV\n",
250 max_power))
251 return;
252
253 /*
254 * This function allocats the default fw monitor.
255 * The optional additional ones will be allocated in runtime
256 */
257 if (trans->num_blocks)
258 return;
259
260 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
c2d20201
EG		 261}
262
a812cba9
AB		 263static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
264{
265 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
266 ((reg & 0x0000ffff) | (2 << 28)));
267 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
268}
269
270static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
271{
272 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
273 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
274 ((reg & 0x0000ffff) | (3 << 28)));
275}
276
ddaf5a5b 277static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 278{
66337b7c 279 if (trans->cfg->apmg_not_supported)
95411d04
AA		 280 return;
281
ddaf5a5b
JB		 282 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
283 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
284 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
285 ~APMG_PS_CTRL_MSK_PWR_SRC);
286 else
287 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
288 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
289 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 290}
291
af634bee
EG		 292/* PCI registers */
293#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 294
eda50cde 295void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 296{
20d3b647 297 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 298 u16 lctl;
9180ac50 299 u16 cap;
af634bee 300
af634bee
EG		 301 /*
302 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
303 * Check if BIOS (or OS) enabled L1-ASPM on this device.
304 * If so (likely), disable L0S, so device moves directly L0->L1;
305 * costs negligible amount of power savings.
306 * If not (unlikely), enable L0S, so there is at least some
307 * power savings, even without L1.
308 */
7afe3705 309 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 310 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 311 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 312 else
af634bee 313 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 314 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 315
316 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
317 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 318 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
319 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
320 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 321}
322
a6c684ee
EG		 323/*
324 * Start up NIC's basic functionality after it has been reset
7afe3705 325 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 326 * NOTE: This does not load uCode nor start the embedded processor
327 */
7afe3705 328static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 329{
52b6e168
EG		 330 int ret;
331
a6c684ee
EG		 332 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
333
334 /*
335 * Use "set_bit" below rather than "write", to preserve any hardware
336 * bits already set by default after reset.
337 */
338
339 /* Disable L0S exit timer (platform NMI Work/Around) */
6e584873 340 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 341 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
342 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 343
344 /*
345 * Disable L0s without affecting L1;
346 * don't wait for ICH L0s (ICH bug W/A)
347 */
348 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 349 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 350
351 /* Set FH wait threshold to maximum (HW error during stress W/A) */
352 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
353
354 /*
355 * Enable HAP INTA (interrupt from management bus) to
356 * wake device's PCI Express link L1a -> L0s
357 */
358 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 359 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 360
7afe3705 361 iwl_pcie_apm_config(trans);
a6c684ee
EG		 362
363 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 364 if (trans->cfg->base_params->pll_cfg)
365 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 366
c96b5eec
JB		 367 ret = iwl_finish_nic_init(trans);
368 if (ret)
52b6e168 369 return ret;
a6c684ee 370
2d93aee1
EG		 371 if (trans->cfg->host_interrupt_operation_mode) {
372 /*
373 * This is a bit of an abuse - This is needed for 7260 / 3160
374 * only check host_interrupt_operation_mode even if this is
375 * not related to host_interrupt_operation_mode.
376 *
377 * Enable the oscillator to count wake up time for L1 exit. This
378 * consumes slightly more power (100uA) - but allows to be sure
379 * that we wake up from L1 on time.
380 *
381 * This looks weird: read twice the same register, discard the
382 * value, set a bit, and yet again, read that same register
383 * just to discard the value. But that's the way the hardware
384 * seems to like it.
385 */
386 iwl_read_prph(trans, OSC_CLK);
387 iwl_read_prph(trans, OSC_CLK);
388 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
389 iwl_read_prph(trans, OSC_CLK);
390 iwl_read_prph(trans, OSC_CLK);
391 }
392
a6c684ee
EG		 393 /*
394 * Enable DMA clock and wait for it to stabilize.
395 *
3073d8c0
EH		 396 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
397 * bits do not disable clocks. This preserves any hardware
398 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 399 */
95411d04 400 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 401 iwl_write_prph(trans, APMG_CLK_EN_REG,
402 APMG_CLK_VAL_DMA_CLK_RQT);
403 udelay(20);
404
405 /* Disable L1-Active */
406 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
407 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
408
409 /* Clear the interrupt in APMG if the NIC is in RFKILL */
410 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
411 APMG_RTC_INT_STT_RFKILL);
412 }
889b1696 413
eb7ff77e 414 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 415
52b6e168 416 return 0;
a6c684ee
EG		 417}
418
a812cba9
AB		 419/*
420 * Enable LP XTAL to avoid HW bug where device may consume much power if
421 * FW is not loaded after device reset. LP XTAL is disabled by default
422 * after device HW reset. Do it only if XTAL is fed by internal source.
423 * Configure device's "persistence" mode to avoid resetting XTAL again when
424 * SHRD_HW_RST occurs in S3.
425 */
426static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
427{
428 int ret;
429 u32 apmg_gp1_reg;
430 u32 apmg_xtal_cfg_reg;
431 u32 dl_cfg_reg;
432
433 /* Force XTAL ON */
434 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
435 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
436
870c2a11 437 iwl_trans_pcie_sw_reset(trans);
a812cba9 438
c96b5eec
JB		 439 ret = iwl_finish_nic_init(trans);
440 if (WARN_ON(ret)) {
a812cba9
AB		 441 /* Release XTAL ON request */
442 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
443 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
444 return;
445 }
446
447 /*
448 * Clear "disable persistence" to avoid LP XTAL resetting when
449 * SHRD_HW_RST is applied in S3.
450 */
451 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
452 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
453
454 /*
455 * Force APMG XTAL to be active to prevent its disabling by HW
456 * caused by APMG idle state.
457 */
458 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
459 SHR_APMG_XTAL_CFG_REG);
460 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
461 apmg_xtal_cfg_reg |
462 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
463
870c2a11 464 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 465
466 /* Enable LP XTAL by indirect access through CSR */
467 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
468 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
469 SHR_APMG_GP1_WF_XTAL_LP_EN |
470 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
471
472 /* Clear delay line clock power up */
473 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
474 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
475 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
476
477 /*
478 * Enable persistence mode to avoid LP XTAL resetting when
479 * SHRD_HW_RST is applied in S3.
480 */
481 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
482 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
483
484 /*
485 * Clear "initialization complete" bit to move adapter from
486 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
487 */
488 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 489 BIT(trans->cfg->csr->flag_init_done));
a812cba9
AB		 490
491 /* Activates XTAL resources monitor */
492 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
493 CSR_MONITOR_XTAL_RESOURCES);
494
495 /* Release XTAL ON request */
496 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
497 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
498 udelay(10);
499
500 /* Release APMG XTAL */
501 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
502 apmg_xtal_cfg_reg &
503 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
504}
505
e8c8935e 506void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 507{
e8c8935e 508 int ret;
cc56feb2
EG		 509
510 /* stop device's busmaster DMA activity */
a8cbb46f
GBA		 511 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
512 BIT(trans->cfg->csr->flag_stop_master));
cc56feb2 513
a8cbb46f
GBA		 514 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
515 BIT(trans->cfg->csr->flag_master_dis),
516 BIT(trans->cfg->csr->flag_master_dis), 100);
7f2ac8fb 517 if (ret < 0)
cc56feb2
EG		 518 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
519
520 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 521}
522
b7aaeae4 523static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 524{
525 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
526
b7aaeae4
EG		 527 if (op_mode_leave) {
528 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
529 iwl_pcie_apm_init(trans);
530
531 /* inform ME that we are leaving */
532 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
533 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
534 APMG_PCIDEV_STT_VAL_WAKE_ME);
6e584873 535 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 536 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
537 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 538 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
539 CSR_HW_IF_CONFIG_REG_PREPARE |
540 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 541 mdelay(1);
542 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
543 CSR_RESET_LINK_PWR_MGMT_DISABLED);
544 }
b7aaeae4
EG		 545 mdelay(5);
546 }
547
eb7ff77e 548 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 549
550 /* Stop device's DMA activity */
7afe3705 551 iwl_pcie_apm_stop_master(trans);
cc56feb2 552
a812cba9
AB		 553 if (trans->cfg->lp_xtal_workaround) {
554 iwl_pcie_apm_lp_xtal_enable(trans);
555 return;
556 }
557
870c2a11 558 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 559
560 /*
561 * Clear "initialization complete" bit to move adapter from
562 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
563 */
564 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 565 BIT(trans->cfg->csr->flag_init_done));
cc56feb2
EG		 566}
567
7afe3705 568static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 569{
7b11488f 570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 571 int ret;
392f8b78
EG		 572
573 /* nic_init */
7b70bd63 574 spin_lock(&trans_pcie->irq_lock);
52b6e168 575 ret = iwl_pcie_apm_init(trans);
7b70bd63 576 spin_unlock(&trans_pcie->irq_lock);
392f8b78 577
52b6e168
EG		 578 if (ret)
579 return ret;
580
95411d04 581 iwl_pcie_set_pwr(trans, false);
392f8b78 582
ecdb975c 583 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 584
585 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 586 iwl_pcie_rx_init(trans);
392f8b78
EG		 587
588 /* Allocate or reset and init all Tx and Command queues */
f02831be 589 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 590 return -ENOMEM;
591
035f7ff2 592 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 593 /* enable shadow regs in HW */
20d3b647 594 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 595 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 596 }
597
392f8b78
EG		 598 return 0;
599}
600
601#define HW_READY_TIMEOUT (50)
602
603/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 604static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 605{
606 int ret;
607
1042db2a 608 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 610
611 /* See if we got it */
1042db2a 612 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 613 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
614 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
615 HW_READY_TIMEOUT);
392f8b78 616
6a08f514
EG		 617 if (ret >= 0)
618 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
619
6d8f6eeb 620 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 621 return ret;
622}
623
624/* Note: returns standard 0/-ERROR code */
eda50cde 625int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 626{
627 int ret;
289e5501 628 int t = 0;
501fd989 629 int iter;
392f8b78 630
6d8f6eeb 631 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 632
7afe3705 633 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 634 /* If the card is ready, exit 0 */
392f8b78
EG		 635 if (ret >= 0)
636 return 0;
637
c9fdec9f
EG		 638 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
639 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 640 usleep_range(1000, 2000);
c9fdec9f 641
501fd989
EG		 642 for (iter = 0; iter < 10; iter++) {
643 /* If HW is not ready, prepare the conditions to check again */
644 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
645 CSR_HW_IF_CONFIG_REG_PREPARE);
646
647 do {
648 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 649 if (ret >= 0)
650 return 0;
392f8b78 651
501fd989
EG		 652 usleep_range(200, 1000);
653 t += 200;
654 } while (t < 150000);
655 msleep(25);
656 }
392f8b78 657
7f2ac8fb 658 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 659
392f8b78
EG		 660 return ret;
661}
662
cf614297
EG		 663/*
664 * ucode
665 */
564cdce7
SS		 666static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
667 u32 dst_addr, dma_addr_t phy_addr,
668 u32 byte_cnt)
cf614297 669{
bac842da
EG		 670 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
671 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
672
673 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
674 dst_addr);
675
676 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
677 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
678
679 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
680 (iwl_get_dma_hi_addr(phy_addr)
681 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
682
683 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
684 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
685 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
686 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
687
688 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
689 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
690 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
691 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 692}
693
564cdce7
SS		 694static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
695 u32 dst_addr, dma_addr_t phy_addr,
696 u32 byte_cnt)
697{
698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
699 unsigned long flags;
700 int ret;
701
702 trans_pcie->ucode_write_complete = false;
703
704 if (!iwl_trans_grab_nic_access(trans, &flags))
705 return -EIO;
706
eda50cde
SS		 707 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
708 byte_cnt);
bac842da 709 iwl_trans_release_nic_access(trans, &flags);
cf614297 710
13df1aab
JB		 711 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
712 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 713 if (!ret) {
83f84d7b 714 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 715 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 716 return -ETIMEDOUT;
717 }
718
719 return 0;
720}
721
7afe3705 722static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 723 const struct fw_desc *section)
cf614297 724{
83f84d7b
JB		 725 u8 *v_addr;
726 dma_addr_t p_addr;
baa21e83 727 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 728 int ret = 0;
729
83f84d7b
JB		 730 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
731 section_num);
732
c571573a
EG		 733 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
734 GFP_KERNEL | __GFP_NOWARN);
735 if (!v_addr) {
736 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
737 chunk_sz = PAGE_SIZE;
738 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
739 &p_addr, GFP_KERNEL);
740 if (!v_addr)
741 return -ENOMEM;
742 }
83f84d7b 743
c571573a 744 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 745 u32 copy_size, dst_addr;
746 bool extended_addr = false;
83f84d7b 747
c571573a 748 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 749 dst_addr = section->offset + offset;
750
751 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
752 dst_addr <= IWL_FW_MEM_EXTENDED_END)
753 extended_addr = true;
754
755 if (extended_addr)
756 iwl_set_bits_prph(trans, LMPM_CHICK,
757 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 758
83f84d7b 759 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 760 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
761 copy_size);
762
763 if (extended_addr)
764 iwl_clear_bits_prph(trans, LMPM_CHICK,
765 LMPM_CHICK_EXTENDED_ADDR_SPACE);
766
83f84d7b
JB		 767 if (ret) {
768 IWL_ERR(trans,
769 "Could not load the [%d] uCode section\n",
770 section_num);
771 break;
6dfa8d01 772 }
83f84d7b
JB		 773 }
774
c571573a 775 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 776 return ret;
777}
778
5dd9c68a
EG		 779static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
780 const struct fw_img *image,
781 int cpu,
782 int *first_ucode_section)
e2d6f4e7
EH		 783{
784 int shift_param;
dcab8ecd
EH		 785 int i, ret = 0, sec_num = 0x1;
786 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 787
788 if (cpu == 1) {
789 shift_param = 0;
034846cf 790 *first_ucode_section = 0;
e2d6f4e7
EH		 791 } else {
792 shift_param = 16;
034846cf 793 (*first_ucode_section)++;
e2d6f4e7
EH		 794 }
795
eef187a7 796 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 797 last_read_idx = i;
798
a6c4fb44
MG		 799 /*
800 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
801 * CPU1 to CPU2.
802 * PAGING_SEPARATOR_SECTION delimiter - separate between
803 * CPU2 non paged to CPU2 paging sec.
804 */
034846cf 805 if (!image->sec[i].data ||
a6c4fb44
MG		 806 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
807 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 808 IWL_DEBUG_FW(trans,
809 "Break since Data not valid or Empty section, sec = %d\n",
810 i);
189fa2fa 811 break;
034846cf
EH		 812 }
813
189fa2fa
EH		 814 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
815 if (ret)
816 return ret;
dcab8ecd 817
d6a2c5c7 818 /* Notify ucode of loaded section number and status */
eda50cde
SS		 819 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
820 val = val | (sec_num << shift_param);
821 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
822
dcab8ecd 823 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 824 }
825
034846cf
EH		 826 *first_ucode_section = last_read_idx;
827
2aabdbdc
EG		 828 iwl_enable_interrupts(trans);
829
d6a2c5c7
SS		 830 if (trans->cfg->use_tfh) {
831 if (cpu == 1)
832 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
833 0xFFFF);
834 else
835 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
836 0xFFFFFFFF);
837 } else {
838 if (cpu == 1)
839 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
840 0xFFFF);
841 else
842 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
843 0xFFFFFFFF);
844 }
afb88917 845
189fa2fa
EH		 846 return 0;
847}
e2d6f4e7 848
189fa2fa
EH		 849static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
850 const struct fw_img *image,
034846cf
EH		 851 int cpu,
852 int *first_ucode_section)
189fa2fa 853{
189fa2fa 854 int i, ret = 0;
034846cf 855 u32 last_read_idx = 0;
189fa2fa 856
3ce4a038 857 if (cpu == 1)
034846cf 858 *first_ucode_section = 0;
3ce4a038 859 else
034846cf 860 (*first_ucode_section)++;
189fa2fa 861
eef187a7 862 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 863 last_read_idx = i;
864
a6c4fb44
MG		 865 /*
866 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
867 * CPU1 to CPU2.
868 * PAGING_SEPARATOR_SECTION delimiter - separate between
869 * CPU2 non paged to CPU2 paging sec.
870 */
034846cf 871 if (!image->sec[i].data ||
a6c4fb44
MG		 872 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
873 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 874 IWL_DEBUG_FW(trans,
875 "Break since Data not valid or Empty section, sec = %d\n",
876 i);
189fa2fa 877 break;
034846cf
EH		 878 }
879
189fa2fa
EH		 880 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
881 if (ret)
882 return ret;
e2d6f4e7
EH		 883 }
884
034846cf
EH		 885 *first_ucode_section = last_read_idx;
886
e2d6f4e7
EH		 887 return 0;
888}
889
c9be849d 890void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 891{
fd527eb5 892 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
09e350f7
LK		 893 int i;
894
7a14c23d
SS		 895 if (trans->ini_valid) {
896 if (!trans->num_blocks)
897 return;
898
ea695b7c
ST		 899 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
900 trans->fw_mon[0].physical >>
901 MON_BUFF_SHIFT_VER2);
902 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
903 (trans->fw_mon[0].physical +
904 trans->fw_mon[0].size - 256) >>
905 MON_BUFF_SHIFT_VER2);
7a14c23d
SS		 906 return;
907 }
908
09e350f7
LK		 909 IWL_INFO(trans, "Applying debug destination %s\n",
910 get_fw_dbg_mode_string(dest->monitor_mode));
911
912 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 913 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 914 else
915 IWL_WARN(trans, "PCI should have external buffer debug\n");
916
17b809c9 917 for (i = 0; i < trans->dbg_n_dest_reg; i++) {
09e350f7
LK		 918 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
919 u32 val = le32_to_cpu(dest->reg_ops[i].val);
920
921 switch (dest->reg_ops[i].op) {
922 case CSR_ASSIGN:
923 iwl_write32(trans, addr, val);
924 break;
925 case CSR_SETBIT:
926 iwl_set_bit(trans, addr, BIT(val));
927 break;
928 case CSR_CLEARBIT:
929 iwl_clear_bit(trans, addr, BIT(val));
930 break;
931 case PRPH_ASSIGN:
932 iwl_write_prph(trans, addr, val);
933 break;
934 case PRPH_SETBIT:
935 iwl_set_bits_prph(trans, addr, BIT(val));
936 break;
937 case PRPH_CLEARBIT:
938 iwl_clear_bits_prph(trans, addr, BIT(val));
939 break;
869f3b15
HD		 940 case PRPH_BLOCKBIT:
941 if (iwl_read_prph(trans, addr) & BIT(val)) {
942 IWL_ERR(trans,
943 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
944 val, addr);
945 goto monitor;
946 }
947 break;
09e350f7
LK		 948 default:
949 IWL_ERR(trans, "FW debug - unknown OP %d\n",
950 dest->reg_ops[i].op);
951 break;
952 }
953 }
954
869f3b15 955monitor:
88964b2e 956 if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) {
09e350f7 957 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
88964b2e 958 trans->fw_mon[0].physical >> dest->base_shift);
6e584873 959 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 960 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
88964b2e
SS		 961 (trans->fw_mon[0].physical +
962 trans->fw_mon[0].size - 256) >>
62d7476d
EG		 963 dest->end_shift);
964 else
965 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
88964b2e
SS		 966 (trans->fw_mon[0].physical +
967 trans->fw_mon[0].size) >>
62d7476d 968 dest->end_shift);
09e350f7
LK		 969 }
970}
971
7afe3705 972static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 973 const struct fw_img *image)
cf614297 974{
189fa2fa 975 int ret = 0;
034846cf 976 int first_ucode_section;
cf614297 977
dcab8ecd 978 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 979 image->is_dual_cpus ? "Dual" : "Single");
980
dcab8ecd
EH		 981 /* load to FW the binary non secured sections of CPU1 */
982 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
983 if (ret)
984 return ret;
e2d6f4e7
EH		 985
986 if (image->is_dual_cpus) {
189fa2fa
EH		 987 /* set CPU2 header address */
988 iwl_write_prph(trans,
989 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
990 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 991
189fa2fa 992 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 993 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
994 &first_ucode_section);
189fa2fa
EH		 995 if (ret)
996 return ret;
e2d6f4e7 997 }
cf614297 998
c2d20201
EG		 999 /* supported for 7000 only for the moment */
1000 if (iwlwifi_mod_params.fw_monitor &&
1001 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1002 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201 1003
88964b2e 1004 if (trans->fw_mon[0].size) {
c2d20201 1005 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
88964b2e 1006 trans->fw_mon[0].physical >> 4);
c2d20201 1007 iwl_write_prph(trans, MON_BUFF_END_ADDR,
88964b2e
SS		 1008 (trans->fw_mon[0].physical +
1009 trans->fw_mon[0].size) >> 4);
c2d20201 1010 }
7a14c23d 1011 } else if (iwl_pcie_dbg_on(trans)) {
09e350f7 1012 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1013 }
1014
2aabdbdc
EG		 1015 iwl_enable_interrupts(trans);
1016
e12ba844 1017 /* release CPU reset */
5dd9c68a 1018 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1019
dcab8ecd
EH		 1020 return 0;
1021}
189fa2fa 1022
5dd9c68a
EG		 1023static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1024 const struct fw_img *image)
dcab8ecd
EH		 1025{
1026 int ret = 0;
1027 int first_ucode_section;
dcab8ecd
EH		 1028
1029 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1030 image->is_dual_cpus ? "Dual" : "Single");
1031
7a14c23d 1032 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 1033 iwl_pcie_apply_destination(trans);
1034
82ea7966
SS		 1035 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1036 iwl_read_prph(trans, WFPM_GP2));
1037
1038 /*
1039 * Set default value. On resume reading the values that were
1040 * zeored can provide debug data on the resume flow.
1041 * This is for debugging only and has no functional impact.
1042 */
1043 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1044
dcab8ecd
EH		 1045 /* configure the ucode to be ready to get the secured image */
1046 /* release CPU reset */
1047 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1048
1049 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1050 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1051 &first_ucode_section);
dcab8ecd
EH		 1052 if (ret)
1053 return ret;
1054
1055 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1056 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1057 &first_ucode_section);
cf614297
EG		 1058}
1059
9ad8fd0b 1060bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1061{
326477e4 1062 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1063 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1064 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1065 bool report;
727c02df 1066
326477e4
JB		 1067 if (hw_rfkill) {
1068 set_bit(STATUS_RFKILL_HW, &trans->status);
1069 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1070 } else {
1071 clear_bit(STATUS_RFKILL_HW, &trans->status);
1072 if (trans_pcie->opmode_down)
1073 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1074 }
1075
1076 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1077
326477e4
JB		 1078 if (prev != report)
1079 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1080
1081 return hw_rfkill;
1082}
1083
7ca00409
HD		 1084struct iwl_causes_list {
1085 u32 cause_num;
1086 u32 mask_reg;
1087 u8 addr;
1088};
1089
1090static struct iwl_causes_list causes_list[] = {
1091 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1092 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1093 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1094 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1095 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1096 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
ff911dca 1097 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12},
7ca00409
HD		 1098 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1099 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1100 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1101 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1102 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1103 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1104 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1105 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1106};
1107
9b58419e
GBA		 1108static struct iwl_causes_list causes_list_v2[] = {
1109 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1110 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1111 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1112 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1113 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1114 {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1115 {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15},
1116 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1117 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1118 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1119 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1120 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1121 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1122 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1123};
1124
7ca00409
HD		 1125static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1126{
1127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1128 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
9b58419e 1129 int i, arr_size =
ff911dca 1130 (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ?
9b58419e 1131 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
7ca00409
HD		 1132
1133 /*
1134 * Access all non RX causes and map them to the default irq.
1135 * In case we are missing at least one interrupt vector,
1136 * the first interrupt vector will serve non-RX and FBQ causes.
1137 */
9b58419e
GBA		 1138 for (i = 0; i < arr_size; i++) {
1139 struct iwl_causes_list *causes =
ff911dca 1140 (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ?
9b58419e
GBA		 1141 causes_list : causes_list_v2;
1142
1143 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1144 iwl_clear_bit(trans, causes[i].mask_reg,
1145 causes[i].cause_num);
7ca00409
HD		 1146 }
1147}
1148
1149static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1150{
1151 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1152 u32 offset =
1153 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1154 u32 val, idx;
1155
1156 /*
1157 * The first RX queue - fallback queue, which is designated for
1158 * management frame, command responses etc, is always mapped to the
1159 * first interrupt vector. The other RX queues are mapped to
1160 * the other (N - 2) interrupt vectors.
1161 */
1162 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1163 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1164 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1165 MSIX_FH_INT_CAUSES_Q(idx - offset));
1166 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1167 }
1168 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1169
1170 val = MSIX_FH_INT_CAUSES_Q(0);
1171 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1172 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1173 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1174
1175 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1176 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1177}
1178
77c09bc8 1179void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1180{
1181 struct iwl_trans *trans = trans_pcie->trans;
1182
1183 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1184 if (trans->cfg->mq_rx_supported &&
1185 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1186 iwl_write_umac_prph(trans, UREG_CHICK,
1187 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1188 return;
1189 }
d7270d61
HD		 1190 /*
1191 * The IVAR table needs to be configured again after reset,
1192 * but if the device is disabled, we can't write to
1193 * prph.
1194 */
1195 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1196 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1197
1198 /*
1199 * Each cause from the causes list above and the RX causes is
1200 * represented as a byte in the IVAR table. The first nibble
1201 * represents the bound interrupt vector of the cause, the second
1202 * represents no auto clear for this cause. This will be set if its
1203 * interrupt vector is bound to serve other causes.
1204 */
1205 iwl_pcie_map_rx_causes(trans);
1206
1207 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1208}
1209
1210static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1211{
1212 struct iwl_trans *trans = trans_pcie->trans;
1213
1214 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1215
83730058
HD		 1216 if (!trans_pcie->msix_enabled)
1217 return;
1218
1219 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1220 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1221 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1222 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1223}
1224
fa9f3281 1225static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1226{
43e58856 1227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1228
fa9f3281
EG		 1229 lockdep_assert_held(&trans_pcie->mutex);
1230
1231 if (trans_pcie->is_down)
1232 return;
1233
1234 trans_pcie->is_down = true;
1235
0232d2cd 1236 /* Stop dbgc before stopping device */
5cfe79c8 1237 _iwl_fw_dbg_stop_recording(trans, NULL);
0232d2cd 1238
43e58856 1239 /* tell the device to stop sending interrupts */
ae2c30bf 1240 iwl_disable_interrupts(trans);
ae2c30bf 1241
ab6cf8e8 1242 /* device going down, Stop using ICT table */
990aa6d7 1243 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1244
1245 /*
1246 * If a HW restart happens during firmware loading,
1247 * then the firmware loading might call this function
1248 * and later it might be called again due to the
1249 * restart. So don't process again if the device is
1250 * already dead.
1251 */
31b8b343 1252 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1253 IWL_DEBUG_INFO(trans,
1254 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1255 iwl_pcie_tx_stop(trans);
9805c446 1256 iwl_pcie_rx_stop(trans);
6379103e 1257
ab6cf8e8 1258 /* Power-down device's busmaster DMA clocks */
95411d04 1259 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1260 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1261 APMG_CLK_VAL_DMA_CLK_RQT);
1262 udelay(5);
1263 }
ab6cf8e8
EG		 1264 }
1265
1266 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1267 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1268 BIT(trans->cfg->csr->flag_mac_access_req));
ab6cf8e8
EG		 1269
1270 /* Stop the device, and put it in low power state */
b7aaeae4 1271 iwl_pcie_apm_stop(trans, false);
43e58856 1272
870c2a11 1273 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1274
f4a1f04a
GBA		 1275 /*
1276 * Upon stop, the IVAR table gets erased, so msi-x won't
1277 * work. This causes a bug in RF-KILL flows, since the interrupt
1278 * that enables radio won't fire on the correct irq, and the
1279 * driver won't be able to handle the interrupt.
1280 * Configure the IVAR table again after reset.
1281 */
1282 iwl_pcie_conf_msix_hw(trans_pcie);
1283
03d6c3b0
EG		 1284 /*
1285 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1286 * This is a bug in certain verions of the hardware.
1287 * Certain devices also keep sending HW RF kill interrupt all
1288 * the time, unless the interrupt is ACKed even if the interrupt
1289 * should be masked. Re-ACK all the interrupts here.
43e58856 1290 */
43e58856 1291 iwl_disable_interrupts(trans);
43e58856 1292
74fda971 1293 /* clear all status bits */
eb7ff77e
AN		 1294 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1295 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1296 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1297
1298 /*
1299 * Even if we stop the HW, we still want the RF kill
1300 * interrupt
1301 */
1302 iwl_enable_rfkill_int(trans);
1303
a6bd005f 1304 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1305 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1306}
1307
eda50cde 1308void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1309{
1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1311
1312 if (trans_pcie->msix_enabled) {
1313 int i;
1314
496d83ca 1315 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1316 synchronize_irq(trans_pcie->msix_entries[i].vector);
1317 } else {
1318 synchronize_irq(trans_pcie->pci_dev->irq);
1319 }
1320}
1321
a6bd005f
EG		 1322static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1323 const struct fw_img *fw, bool run_in_rfkill)
1324{
1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1326 bool hw_rfkill;
1327 int ret;
1328
1329 /* This may fail if AMT took ownership of the device */
1330 if (iwl_pcie_prepare_card_hw(trans)) {
1331 IWL_WARN(trans, "Exit HW not ready\n");
1332 ret = -EIO;
1333 goto out;
1334 }
1335
1336 iwl_enable_rfkill_int(trans);
1337
1338 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1339
1340 /*
1341 * We enabled the RF-Kill interrupt and the handler may very
1342 * well be running. Disable the interrupts to make sure no other
1343 * interrupt can be fired.
1344 */
1345 iwl_disable_interrupts(trans);
1346
1347 /* Make sure it finished running */
2e5d4a8f 1348 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1349
1350 mutex_lock(&trans_pcie->mutex);
1351
1352 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1353 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1354 if (hw_rfkill && !run_in_rfkill) {
1355 ret = -ERFKILL;
1356 goto out;
1357 }
1358
1359 /* Someone called stop_device, don't try to start_fw */
1360 if (trans_pcie->is_down) {
1361 IWL_WARN(trans,
1362 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1363 ret = -EIO;
a6bd005f
EG		 1364 goto out;
1365 }
1366
1367 /* make sure rfkill handshake bits are cleared */
1368 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1369 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1370 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1371
1372 /* clear (again), then enable host interrupts */
1373 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1374
1375 ret = iwl_pcie_nic_init(trans);
1376 if (ret) {
1377 IWL_ERR(trans, "Unable to init nic\n");
1378 goto out;
1379 }
1380
1381 /*
1382 * Now, we load the firmware and don't want to be interrupted, even
1383 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1384 * FH_TX interrupt which is needed to load the firmware). If the
1385 * RF-Kill switch is toggled, we will find out after having loaded
1386 * the firmware and return the proper value to the caller.
1387 */
1388 iwl_enable_fw_load_int(trans);
1389
1390 /* really make sure rfkill handshake bits are cleared */
1391 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1392 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1393
1394 /* Load the given image to the HW */
6e584873 1395 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1396 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1397 else
1398 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1399
1400 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1401 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1402 if (hw_rfkill && !run_in_rfkill)
1403 ret = -ERFKILL;
1404
1405out:
1406 mutex_unlock(&trans_pcie->mutex);
1407 return ret;
1408}
1409
1410static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1411{
1412 iwl_pcie_reset_ict(trans);
1413 iwl_pcie_tx_start(trans, scd_addr);
1414}
1415
326477e4
JB		 1416void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1417 bool was_in_rfkill)
1418{
1419 bool hw_rfkill;
1420
1421 /*
1422 * Check again since the RF kill state may have changed while
1423 * all the interrupts were disabled, in this case we couldn't
1424 * receive the RF kill interrupt and update the state in the
1425 * op_mode.
1426 * Don't call the op_mode if the rkfill state hasn't changed.
1427 * This allows the op_mode to call stop_device from the rfkill
1428 * notification without endless recursion. Under very rare
1429 * circumstances, we might have a small recursion if the rfkill
1430 * state changed exactly now while we were called from stop_device.
1431 * This is very unlikely but can happen and is supported.
1432 */
1433 hw_rfkill = iwl_is_rfkill_set(trans);
1434 if (hw_rfkill) {
1435 set_bit(STATUS_RFKILL_HW, &trans->status);
1436 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1437 } else {
1438 clear_bit(STATUS_RFKILL_HW, &trans->status);
1439 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1440 }
1441 if (hw_rfkill != was_in_rfkill)
1442 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1443}
1444
fa9f3281
EG		 1445static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1446{
1447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1448 bool was_in_rfkill;
fa9f3281
EG		 1449
1450 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1451 trans_pcie->opmode_down = true;
1452 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
fa9f3281 1453 _iwl_trans_pcie_stop_device(trans, low_power);
326477e4 1454 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1455 mutex_unlock(&trans_pcie->mutex);
1456}
1457
14cfca71
JB		 1458void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1459{
fa9f3281
EG		 1460 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1461 IWL_TRANS_GET_PCIE_TRANS(trans);
1462
1463 lockdep_assert_held(&trans_pcie->mutex);
1464
326477e4
JB		 1465 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1466 state ? "disabled" : "enabled");
77c09bc8
SS		 1467 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1468 if (trans->cfg->gen2)
1469 _iwl_trans_pcie_gen2_stop_device(trans, true);
1470 else
1471 _iwl_trans_pcie_stop_device(trans, true);
1472 }
ab6cf8e8
EG		 1473}
1474
23ae6128
MG		 1475static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1476 bool reset)
2dd4f9f7 1477{
23ae6128 1478 if (!reset) {
6dfb36c8
EP		 1479 /* Enable persistence mode to avoid reset */
1480 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1481 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1482 }
1483
2dd4f9f7 1484 iwl_disable_interrupts(trans);
debff618
JB		 1485
1486 /*
1487 * in testing mode, the host stays awake and the
1488 * hardware won't be reset (not even partially)
1489 */
1490 if (test)
1491 return;
1492
ddaf5a5b
JB		 1493 iwl_pcie_disable_ict(trans);
1494
2e5d4a8f 1495 iwl_pcie_synchronize_irqs(trans);
33b56af1 1496
2dd4f9f7 1497 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1498 BIT(trans->cfg->csr->flag_mac_access_req));
ddaf5a5b 1499 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1500 BIT(trans->cfg->csr->flag_init_done));
ddaf5a5b 1501
23ae6128 1502 if (reset) {
6dfb36c8
EP		 1503 /*
1504 * reset TX queues -- some of their registers reset during S3
1505 * so if we don't reset everything here the D3 image would try
1506 * to execute some invalid memory upon resume
1507 */
1508 iwl_trans_pcie_tx_reset(trans);
1509 }
ddaf5a5b
JB		 1510
1511 iwl_pcie_set_pwr(trans, true);
1512}
1513
1514static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1515 enum iwl_d3_status *status,
23ae6128 1516 bool test, bool reset)
ddaf5a5b 1517{
d7270d61 1518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1519 u32 val;
1520 int ret;
1521
debff618
JB		 1522 if (test) {
1523 iwl_enable_interrupts(trans);
1524 *status = IWL_D3_STATUS_ALIVE;
1525 return 0;
1526 }
1527
a8cbb46f
GBA		 1528 iwl_set_bit(trans, CSR_GP_CNTRL,
1529 BIT(trans->cfg->csr->flag_mac_access_req));
ddaf5a5b 1530
c96b5eec
JB		 1531 ret = iwl_finish_nic_init(trans);
1532 if (ret)
ddaf5a5b 1533 return ret;
ddaf5a5b 1534
f98ad635
EG		 1535 /*
1536 * Reconfigure IVAR table in case of MSIX or reset ict table in
1537 * MSI mode since HW reset erased it.
1538 * Also enables interrupts - none will happen as
1539 * the device doesn't know we're waking it up, only when
1540 * the opmode actually tells it after this call.
1541 */
1542 iwl_pcie_conf_msix_hw(trans_pcie);
1543 if (!trans_pcie->msix_enabled)
1544 iwl_pcie_reset_ict(trans);
1545 iwl_enable_interrupts(trans);
1546
a3ead656
EG		 1547 iwl_pcie_set_pwr(trans, false);
1548
23ae6128 1549 if (!reset) {
6dfb36c8 1550 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1551 BIT(trans->cfg->csr->flag_mac_access_req));
6dfb36c8
EP		 1552 } else {
1553 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1554
6dfb36c8
EP		 1555 ret = iwl_pcie_rx_init(trans);
1556 if (ret) {
1557 IWL_ERR(trans,
1558 "Failed to resume the device (RX reset)\n");
1559 return ret;
1560 }
ddaf5a5b
JB		 1561 }
1562
82ea7966 1563 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1564 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1565
a3ead656
EG		 1566 val = iwl_read32(trans, CSR_RESET);
1567 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1568 *status = IWL_D3_STATUS_RESET;
1569 else
1570 *status = IWL_D3_STATUS_ALIVE;
1571
ddaf5a5b 1572 return 0;
2dd4f9f7
JB		 1573}
1574
2e5d4a8f
HD		 1575static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1576 struct iwl_trans *trans)
1577{
1578 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1579 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1580 u16 pci_cmd;
2e5d4a8f 1581
06f4b081
SS		 1582 if (!trans->cfg->mq_rx_supported)
1583 goto enable_msi;
1584
ab1068d6 1585 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1586 for (i = 0; i < max_irqs; i++)
1587 trans_pcie->msix_entries[i].entry = i;
496d83ca 1588
06f4b081
SS		 1589 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1590 MSIX_MIN_INTERRUPT_VECTORS,
1591 max_irqs);
1592 if (num_irqs < 0) {
2e5d4a8f 1593 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1594 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1595 num_irqs);
1596 goto enable_msi;
1597 }
1598 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1599
06f4b081
SS		 1600 IWL_DEBUG_INFO(trans,
1601 "MSI-X enabled. %d interrupt vectors were allocated\n",
1602 num_irqs);
1603
1604 /*
1605 * In case the OS provides fewer interrupts than requested, different
1606 * causes will share the same interrupt vector as follows:
1607 * One interrupt less: non rx causes shared with FBQ.
1608 * Two interrupts less: non rx causes shared with FBQ and RSS.
1609 * More than two interrupts: we will use fewer RSS queues.
1610 */
ab1068d6 1611 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1612 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1613 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1614 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1615 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1616 trans_pcie->trans->num_rx_queues = num_irqs;
1617 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1618 } else {
1619 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1620 }
ab1068d6 1621 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1622
06f4b081
SS		 1623 trans_pcie->alloc_vecs = num_irqs;
1624 trans_pcie->msix_enabled = true;
1625 return;
1626
1627enable_msi:
1628 ret = pci_enable_msi(pdev);
1629 if (ret) {
1630 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1631 /* enable rfkill interrupt: hw bug w/a */
1632 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1633 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1634 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1635 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1636 }
1637 }
1638}
1639
7c8d91eb
HD		 1640static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1641{
1642 int iter_rx_q, i, ret, cpu, offset;
1643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1644
1645 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1646 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1647 offset = 1 + i;
1648 for (; i < iter_rx_q ; i++) {
1649 /*
1650 * Get the cpu prior to the place to search
1651 * (i.e. return will be > i - 1).
1652 */
1653 cpu = cpumask_next(i - offset, cpu_online_mask);
1654 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1655 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1656 &trans_pcie->affinity_mask[i]);
1657 if (ret)
1658 IWL_ERR(trans_pcie->trans,
1659 "Failed to set affinity mask for IRQ %d\n",
1660 i);
1661 }
1662}
1663
2e5d4a8f
HD		 1664static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1665 struct iwl_trans_pcie *trans_pcie)
1666{
496d83ca 1667 int i;
2e5d4a8f 1668
496d83ca 1669 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1670 int ret;
5a41a86c 1671 struct msix_entry *msix_entry;
64fa3aff
SD		 1672 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1673
1674 if (!qname)
1675 return -ENOMEM;
5a41a86c
SD		 1676
1677 msix_entry = &trans_pcie->msix_entries[i];
1678 ret = devm_request_threaded_irq(&pdev->dev,
1679 msix_entry->vector,
1680 iwl_pcie_msix_isr,
1681 (i == trans_pcie->def_irq) ?
1682 iwl_pcie_irq_msix_handler :
1683 iwl_pcie_irq_rx_msix_handler,
1684 IRQF_SHARED,
64fa3aff 1685 qname,
5a41a86c 1686 msix_entry);
2e5d4a8f 1687 if (ret) {
2e5d4a8f
HD		 1688 IWL_ERR(trans_pcie->trans,
1689 "Error allocating IRQ %d\n", i);
5a41a86c 1690
2e5d4a8f
HD		 1691 return ret;
1692 }
1693 }
7c8d91eb 1694 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1695
1696 return 0;
1697}
1698
fa9f3281 1699static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1700{
fa9f3281 1701 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
8954e1eb 1702 u32 hpm;
a8b691e6 1703 int err;
e6bb4c9c 1704
fa9f3281
EG		 1705 lockdep_assert_held(&trans_pcie->mutex);
1706
7afe3705 1707 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1708 if (err) {
d6f1c316 1709 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1710 return err;
ebb7678d 1711 }
a6c684ee 1712
ea695b7c 1713 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
8954e1eb 1714 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
ea695b7c
ST		 1715 int wfpm_val = iwl_read_umac_prph_no_grab(trans,
1716 PREG_PRPH_WPROT_0);
1717
1718 if (wfpm_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1719 IWL_ERR(trans,
1720 "Error, can not clear persistence bit\n");
1721 return -EPERM;
1722 }
ea695b7c
ST		 1723 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1724 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1725 }
1726
870c2a11 1727 iwl_trans_pcie_sw_reset(trans);
2997494f 1728
52b6e168
EG		 1729 err = iwl_pcie_apm_init(trans);
1730 if (err)
1731 return err;
a6c684ee 1732
2e5d4a8f 1733 iwl_pcie_init_msix(trans_pcie);
83730058 1734
226c02ca
EG		 1735 /* From now on, the op_mode will be kept updated about RF kill state */
1736 iwl_enable_rfkill_int(trans);
1737
326477e4
JB		 1738 trans_pcie->opmode_down = false;
1739
fa9f3281
EG		 1740 /* Set is_down to false here so that...*/
1741 trans_pcie->is_down = false;
1742
727c02df 1743 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1744 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1745
4cbb8e50
LC		 1746 /* Make sure we sync here, because we'll need full access later */
1747 if (low_power)
1748 pm_runtime_resume(trans->dev);
1749
a8b691e6 1750 return 0;
e6bb4c9c
EG		 1751}
1752
fa9f3281
EG		 1753static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1754{
1755 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1756 int ret;
1757
1758 mutex_lock(&trans_pcie->mutex);
1759 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1760 mutex_unlock(&trans_pcie->mutex);
1761
1762 return ret;
1763}
1764
a4082843 1765static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1766{
20d3b647 1767 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1768
fa9f3281
EG		 1769 mutex_lock(&trans_pcie->mutex);
1770
a4082843 1771 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1772 iwl_disable_interrupts(trans);
ee7d737c 1773
b7aaeae4 1774 iwl_pcie_apm_stop(trans, true);
cc56feb2 1775
218733cf 1776 iwl_disable_interrupts(trans);
1df06bdc 1777
8d96bb61 1778 iwl_pcie_disable_ict(trans);
33b56af1 1779
fa9f3281 1780 mutex_unlock(&trans_pcie->mutex);
33b56af1 1781
2e5d4a8f 1782 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1783}
1784
03905495
EG		 1785static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1786{
05f5b97e 1787 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1788}
1789
1790static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1791{
05f5b97e 1792 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1793}
1794
1795static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1796{
05f5b97e 1797 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1798}
1799
84fb372c
SS		 1800static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1801{
1802 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1803 return 0x00FFFFFF;
1804 else
1805 return 0x000FFFFF;
1806}
1807
6a06b6c1
EG		 1808static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1809{
84fb372c
SS		 1810 u32 mask = iwl_trans_pcie_prph_msk(trans);
1811
f9477c17 1812 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1813 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1814 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1815}
1816
1817static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1818 u32 val)
1819{
84fb372c
SS		 1820 u32 mask = iwl_trans_pcie_prph_msk(trans);
1821
6a06b6c1 1822 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1823 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1824 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1825}
1826
c6f600fc 1827static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1828 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1829{
1830 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1831
1832 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1833 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1834 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1835 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1836 trans_pcie->n_no_reclaim_cmds = 0;
1837 else
1838 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1839 if (trans_pcie->n_no_reclaim_cmds)
1840 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1841 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1842
6c4fbcbc
EG		 1843 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1844 trans_pcie->rx_page_order =
1845 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1846
046db346 1847 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1848 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1849 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1850
21cb3222
JB		 1851 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1852 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1853
39bdb17e
SD		 1854 trans->command_groups = trans_cfg->command_groups;
1855 trans->command_groups_size = trans_cfg->command_groups_size;
1856
f14d6b39
JB		 1857 /* Initialize NAPI here - it should be before registering to mac80211
1858 * in the opmode but after the HW struct is allocated.
1859 * As this function may be called again in some corner cases don't
1860 * do anything if NAPI was already initialized.
1861 */
bce97731 1862 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1863 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1864}
1865
d1ff5253 1866void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1867{
20d3b647 1868 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1869 int i;
a42a1844 1870
2e5d4a8f 1871 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1872
13a3a390
SS		 1873 if (trans->cfg->gen2)
1874 iwl_pcie_gen2_tx_free(trans);
1875 else
1876 iwl_pcie_tx_free(trans);
9805c446 1877 iwl_pcie_rx_free(trans);
6379103e 1878
10a54d81
LC		 1879 if (trans_pcie->rba.alloc_wq) {
1880 destroy_workqueue(trans_pcie->rba.alloc_wq);
1881 trans_pcie->rba.alloc_wq = NULL;
1882 }
1883
2e5d4a8f 1884 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1885 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1886 irq_set_affinity_hint(
1887 trans_pcie->msix_entries[i].vector,
1888 NULL);
7c8d91eb 1889 }
2e5d4a8f 1890
2e5d4a8f
HD		 1891 trans_pcie->msix_enabled = false;
1892 } else {
2e5d4a8f 1893 iwl_pcie_free_ict(trans);
2e5d4a8f 1894 }
a42a1844 1895
c2d20201
EG		 1896 iwl_pcie_free_fw_monitor(trans);
1897
6eb5e529
EG		 1898 for_each_possible_cpu(i) {
1899 struct iwl_tso_hdr_page *p =
1900 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1901
1902 if (p->page)
1903 __free_page(p->page);
1904 }
1905
1906 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1907 mutex_destroy(&trans_pcie->mutex);
7b501d10 1908 iwl_trans_free(trans);
34c1b7ba
EG		 1909}
1910
47107e84
DF		 1911static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1912{
47107e84 1913 if (state)
eb7ff77e 1914 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1915 else
eb7ff77e 1916 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1917}
1918
49564a80
LC		 1919struct iwl_trans_pcie_removal {
1920 struct pci_dev *pdev;
1921 struct work_struct work;
1922};
1923
1924static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1925{
1926 struct iwl_trans_pcie_removal *removal =
1927 container_of(wk, struct iwl_trans_pcie_removal, work);
1928 struct pci_dev *pdev = removal->pdev;
aba1e632 1929 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
49564a80
LC		 1930
1931 dev_err(&pdev->dev, "Device gone - attempting removal\n");
1932 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1933 pci_lock_rescan_remove();
1934 pci_dev_put(pdev);
1935 pci_stop_and_remove_bus_device(pdev);
1936 pci_unlock_rescan_remove();
1937
1938 kfree(removal);
1939 module_put(THIS_MODULE);
1940}
1941
23ba9340
EG		 1942static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1943 unsigned long *flags)
7a65d170
EG		 1944{
1945 int ret;
cfb4e624
JB		 1946 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1947
1948 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1949
fc8a350d 1950 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1951 goto out;
1952
7a65d170 1953 /* this bit wakes up the NIC */
e139dc4a 1954 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1955 BIT(trans->cfg->csr->flag_mac_access_req));
6e584873 1956 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 1957 udelay(2);
7a65d170
EG		 1958
1959 /*
1960 * These bits say the device is running, and should keep running for
1961 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1962 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 1963 * HW with volatile SRAM must save/restore contents to/from
1964 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 1965 * Each direction takes approximately 1/4 millisecond; with this
1966 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1967 * series of register accesses are expected (e.g. reading Event Log),
1968 * to keep device from sleeping.
1969 *
1970 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1971 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 1972 * is just for hardware register access; but GP1 MAC_SLEEP
1973 * check is a good idea before accessing the SRAM of HW with
1974 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 1975 *
1976 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1977 * and do not save/restore SRAM when power cycling.
1978 */
1979 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 1980 BIT(trans->cfg->csr->flag_val_mac_access_en),
1981 (BIT(trans->cfg->csr->flag_mac_clock_ready) |
7a65d170
EG		 1982 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1983 if (unlikely(ret < 0)) {
49564a80
LC		 1984 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
1985
23ba9340
EG		 1986 WARN_ONCE(1,
1987 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 1988 cntrl);
1989
1990 iwl_trans_pcie_dump_regs(trans);
1991
1992 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
1993 struct iwl_trans_pcie_removal *removal;
1994
f60c9e59 1995 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
49564a80
LC		 1996 goto err;
1997
1998 IWL_ERR(trans, "Device gone - scheduling removal!\n");
1999
2000 /*
2001 * get a module reference to avoid doing this
2002 * while unloading anyway and to avoid
2003 * scheduling a work with code that's being
2004 * removed.
2005 */
2006 if (!try_module_get(THIS_MODULE)) {
2007 IWL_ERR(trans,
2008 "Module is being unloaded - abort\n");
2009 goto err;
2010 }
2011
2012 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2013 if (!removal) {
2014 module_put(THIS_MODULE);
2015 goto err;
2016 }
2017 /*
2018 * we don't need to clear this flag, because
2019 * the trans will be freed and reallocated.
2020 */
f60c9e59 2021 set_bit(STATUS_TRANS_DEAD, &trans->status);
49564a80
LC		 2022
2023 removal->pdev = to_pci_dev(trans->dev);
2024 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2025 pci_dev_get(removal->pdev);
2026 schedule_work(&removal->work);
2027 } else {
2028 iwl_write32(trans, CSR_RESET,
2029 CSR_RESET_REG_FLAG_FORCE_NMI);
2030 }
2031
2032err:
23ba9340
EG		 2033 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2034 return false;
7a65d170
EG		 2035 }
2036
b9439491 2037out:
e56b04ef
LE		 2038 /*
2039 * Fool sparse by faking we release the lock - sparse will
2040 * track nic_access anyway.
2041 */
cfb4e624 2042 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2043 return true;
2044}
2045
e56b04ef
LE		 2046static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2047 unsigned long *flags)
7a65d170 2048{
cfb4e624 2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2050
cfb4e624 2051 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2052
2053 /*
2054 * Fool sparse by faking we acquiring the lock - sparse will
2055 * track nic_access anyway.
2056 */
cfb4e624 2057 __acquire(&trans_pcie->reg_lock);
e56b04ef 2058
fc8a350d 2059 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2060 goto out;
2061
e139dc4a 2062 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 2063 BIT(trans->cfg->csr->flag_mac_access_req));
7a65d170
EG		 2064 /*
2065 * Above we read the CSR_GP_CNTRL register, which will flush
2066 * any previous writes, but we need the write that clears the
2067 * MAC_ACCESS_REQ bit to be performed before any other writes
2068 * scheduled on different CPUs (after we drop reg_lock).
2069 */
2070 mmiowb();
b9439491 2071out:
cfb4e624 2072 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2073}
2074
4fd442db
EG		 2075static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2076 void *buf, int dwords)
2077{
2078 unsigned long flags;
2079 int offs, ret = 0;
2080 u32 *vals = buf;
2081
23ba9340 2082 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2083 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2084 for (offs = 0; offs < dwords; offs++)
2085 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2086 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2087 } else {
2088 ret = -EBUSY;
2089 }
4fd442db
EG		 2090 return ret;
2091}
2092
2093static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2094 const void *buf, int dwords)
4fd442db
EG		 2095{
2096 unsigned long flags;
2097 int offs, ret = 0;
bf0fd5da 2098 const u32 *vals = buf;
4fd442db 2099
23ba9340 2100 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2101 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2102 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2103 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2104 vals ? vals[offs] : 0);
e56b04ef 2105 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2106 } else {
2107 ret = -EBUSY;
2108 }
4fd442db
EG		 2109 return ret;
2110}
7a65d170 2111
e0b8d405
EG		 2112static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2113 unsigned long txqs,
2114 bool freeze)
2115{
2116 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2117 int queue;
2118
2119 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2120 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2121 unsigned long now;
2122
2123 spin_lock_bh(&txq->lock);
2124
2125 now = jiffies;
2126
2127 if (txq->frozen == freeze)
2128 goto next_queue;
2129
2130 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2131 freeze ? "Freezing" : "Waking", queue);
2132
2133 txq->frozen = freeze;
2134
bb98ecd4 2135 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2136 goto next_queue;
2137
2138 if (freeze) {
2139 if (unlikely(time_after(now,
2140 txq->stuck_timer.expires))) {
2141 /*
2142 * The timer should have fired, maybe it is
2143 * spinning right now on the lock.
2144 */
2145 goto next_queue;
2146 }
2147 /* remember how long until the timer fires */
2148 txq->frozen_expiry_remainder =
2149 txq->stuck_timer.expires - now;
2150 del_timer(&txq->stuck_timer);
2151 goto next_queue;
2152 }
2153
2154 /*
2155 * Wake a non-empty queue -> arm timer with the
2156 * remainder before it froze
2157 */
2158 mod_timer(&txq->stuck_timer,
2159 now + txq->frozen_expiry_remainder);
2160
2161next_queue:
2162 spin_unlock_bh(&txq->lock);
2163 }
2164}
2165
0cd58eaa
EG		 2166static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2167{
2168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2169 int i;
2170
2171 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2172 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2173
2174 if (i == trans_pcie->cmd_queue)
2175 continue;
2176
2177 spin_lock_bh(&txq->lock);
2178
2179 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2180 txq->block--;
2181 if (!txq->block) {
2182 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2183 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2184 }
2185 } else if (block) {
2186 txq->block++;
2187 }
2188
2189 spin_unlock_bh(&txq->lock);
2190 }
2191}
2192
5f178cd2
EG		 2193#define IWL_FLUSH_WAIT_MS 2000
2194
38398efb
SS		 2195void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2196{
afb84431
EG		 2197 u32 txq_id = txq->id;
2198 u32 status;
2199 bool active;
2200 u8 fifo;
38398efb 2201
afb84431
EG		 2202 if (trans->cfg->use_tfh) {
2203 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2204 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2205 /* TODO: access new SCD registers and dump them */
2206 return;
38398efb 2207 }
afb84431
EG		 2208
2209 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2210 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2211 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2212
2213 IWL_ERR(trans,
2214 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2215 txq_id, active ? "" : "in", fifo,
2216 jiffies_to_msecs(txq->wd_timeout),
2217 txq->read_ptr, txq->write_ptr,
2218 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
7b3e42ea 2219 (trans->cfg->base_params->max_tfd_queue_size - 1),
afb84431 2220 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
7b3e42ea 2221 (trans->cfg->base_params->max_tfd_queue_size - 1),
afb84431 2222 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2223}
2224
92536c96
SS		 2225static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2226 struct iwl_trans_rxq_dma_data *data)
2227{
2228 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2229
2230 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2231 return -EINVAL;
2232
2233 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2234 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2235 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2236 data->fr_bd_wid = 0;
2237
2238 return 0;
2239}
2240
d6d517b7 2241static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2242{
8ad71bef 2243 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2244 struct iwl_txq *txq;
5f178cd2 2245 unsigned long now = jiffies;
2ae48edc 2246 bool overflow_tx;
d6d517b7
SS		 2247 u8 wr_ptr;
2248
2b3fae66 2249 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2250 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2251 return -ENODEV;
2b3fae66 2252
d6d517b7
SS		 2253 if (!test_bit(txq_idx, trans_pcie->queue_used))
2254 return -EINVAL;
2255
2256 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2257 txq = trans_pcie->txq[txq_idx];
2ae48edc
SS		 2258
2259 spin_lock_bh(&txq->lock);
2260 overflow_tx = txq->overflow_tx ||
2261 !skb_queue_empty(&txq->overflow_q);
2262 spin_unlock_bh(&txq->lock);
2263
6aa7de05 2264 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2265
2ae48edc
SS		 2266 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2267 overflow_tx) &&
d6d517b7
SS		 2268 !time_after(jiffies,
2269 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2270 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2271
2ae48edc
SS		 2272 /*
2273 * If write pointer moved during the wait, warn only
2274 * if the TX came from op mode. In case TX came from
2275 * trans layer (overflow TX) don't warn.
2276 */
2277 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2278 "WR pointer moved while flushing %d -> %d\n",
2279 wr_ptr, write_ptr))
2280 return -ETIMEDOUT;
2ae48edc
SS		 2281 wr_ptr = write_ptr;
2282
d6d517b7 2283 usleep_range(1000, 2000);
2ae48edc
SS		 2284
2285 spin_lock_bh(&txq->lock);
2286 overflow_tx = txq->overflow_tx ||
2287 !skb_queue_empty(&txq->overflow_q);
2288 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2289 }
2290
2291 if (txq->read_ptr != txq->write_ptr) {
2292 IWL_ERR(trans,
2293 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2294 iwl_trans_pcie_log_scd_error(trans, txq);
2295 return -ETIMEDOUT;
2296 }
2297
2298 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2299
2300 return 0;
2301}
2302
2303static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2304{
2305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2306 int cnt;
5f178cd2
EG		 2307 int ret = 0;
2308
2309 /* waiting for all the tx frames complete might take a while */
035f7ff2 2310 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd 2311
9ba1947a 2312 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2313 continue;
3cafdbe6
EG		 2314 if (!test_bit(cnt, trans_pcie->queue_used))
2315 continue;
2316 if (!(BIT(cnt) & txq_bm))
2317 continue;
748fa67c 2318
d6d517b7
SS		 2319 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2320 if (ret)
5f178cd2 2321 break;
5f178cd2 2322 }
1c3fea82 2323
5f178cd2
EG		 2324 return ret;
2325}
2326
e139dc4a
LE		 2327static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2328 u32 mask, u32 value)
2329{
e56b04ef 2330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2331 unsigned long flags;
2332
e56b04ef 2333 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2334 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2335 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2336}
2337
c24c7f58 2338static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2339{
2340 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2341
2342 if (iwlwifi_mod_params.d0i3_disable)
2343 return;
2344
b3ff1270 2345 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2346
2347#ifdef CONFIG_PM
2348 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2349 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2350#endif /* CONFIG_PM */
7616f334
EP		 2351}
2352
c24c7f58 2353static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2354{
2355 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2356
2357 if (iwlwifi_mod_params.d0i3_disable)
2358 return;
2359
b3ff1270
LC		 2360 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2361 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2362
5d93f3a2
LC		 2363#ifdef CONFIG_PM
2364 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2365 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2366#endif /* CONFIG_PM */
7616f334
EP		 2367}
2368
ff620849
EG		 2369static const char *get_csr_string(int cmd)
2370{
d9fb6465 2371#define IWL_CMD(x) case x: return #x
ff620849
EG		 2372 switch (cmd) {
2373 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2374 IWL_CMD(CSR_INT_COALESCING);
2375 IWL_CMD(CSR_INT);
2376 IWL_CMD(CSR_INT_MASK);
2377 IWL_CMD(CSR_FH_INT_STATUS);
2378 IWL_CMD(CSR_GPIO_IN);
2379 IWL_CMD(CSR_RESET);
2380 IWL_CMD(CSR_GP_CNTRL);
2381 IWL_CMD(CSR_HW_REV);
2382 IWL_CMD(CSR_EEPROM_REG);
2383 IWL_CMD(CSR_EEPROM_GP);
2384 IWL_CMD(CSR_OTP_GP_REG);
2385 IWL_CMD(CSR_GIO_REG);
2386 IWL_CMD(CSR_GP_UCODE_REG);
2387 IWL_CMD(CSR_GP_DRIVER_REG);
2388 IWL_CMD(CSR_UCODE_DRV_GP1);
2389 IWL_CMD(CSR_UCODE_DRV_GP2);
2390 IWL_CMD(CSR_LED_REG);
2391 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2392 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2393 IWL_CMD(CSR_ANA_PLL_CFG);
2394 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2395 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2396 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2397 default:
2398 return "UNKNOWN";
2399 }
d9fb6465 2400#undef IWL_CMD
ff620849
EG		 2401}
2402
990aa6d7 2403void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2404{
2405 int i;
2406 static const u32 csr_tbl[] = {
2407 CSR_HW_IF_CONFIG_REG,
2408 CSR_INT_COALESCING,
2409 CSR_INT,
2410 CSR_INT_MASK,
2411 CSR_FH_INT_STATUS,
2412 CSR_GPIO_IN,
2413 CSR_RESET,
2414 CSR_GP_CNTRL,
2415 CSR_HW_REV,
2416 CSR_EEPROM_REG,
2417 CSR_EEPROM_GP,
2418 CSR_OTP_GP_REG,
2419 CSR_GIO_REG,
2420 CSR_GP_UCODE_REG,
2421 CSR_GP_DRIVER_REG,
2422 CSR_UCODE_DRV_GP1,
2423 CSR_UCODE_DRV_GP2,
2424 CSR_LED_REG,
2425 CSR_DRAM_INT_TBL_REG,
2426 CSR_GIO_CHICKEN_BITS,
2427 CSR_ANA_PLL_CFG,
a812cba9 2428 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2429 CSR_HW_REV_WA_REG,
2430 CSR_DBG_HPET_MEM_REG
2431 };
2432 IWL_ERR(trans, "CSR values:\n");
2433 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2434 "CSR_INT_PERIODIC_REG)\n");
2435 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2436 IWL_ERR(trans, " %25s: 0X%08x\n",
2437 get_csr_string(csr_tbl[i]),
1042db2a 2438 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2439 }
2440}
2441
87e5666c
EG		 2442#ifdef CONFIG_IWLWIFI_DEBUGFS
2443/* create and remove of files */
2444#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2445 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2446 &iwl_dbgfs_##name##_ops)) \
9da987ac 2447 goto err; \
87e5666c
EG		 2448} while (0)
2449
2450/* file operation */
87e5666c 2451#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2452static const struct file_operations iwl_dbgfs_##name##_ops = { \
2453 .read = iwl_dbgfs_##name##_read, \
234e3405 2454 .open = simple_open, \
87e5666c
EG		 2455 .llseek = generic_file_llseek, \
2456};
2457
16db88ba 2458#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2459static const struct file_operations iwl_dbgfs_##name##_ops = { \
2460 .write = iwl_dbgfs_##name##_write, \
234e3405 2461 .open = simple_open, \
16db88ba
EG		 2462 .llseek = generic_file_llseek, \
2463};
2464
87e5666c 2465#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2466static const struct file_operations iwl_dbgfs_##name##_ops = { \
2467 .write = iwl_dbgfs_##name##_write, \
2468 .read = iwl_dbgfs_##name##_read, \
234e3405 2469 .open = simple_open, \
87e5666c
EG		 2470 .llseek = generic_file_llseek, \
2471};
2472
87e5666c 2473static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2474 char __user *user_buf,
2475 size_t count, loff_t *ppos)
8ad71bef 2476{
5a878bf6 2477 struct iwl_trans *trans = file->private_data;
8ad71bef 2478 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2479 struct iwl_txq *txq;
87e5666c
EG		 2480 char *buf;
2481 int pos = 0;
2482 int cnt;
2483 int ret;
1745e440
WYG		 2484 size_t bufsz;
2485
e0b8d405 2486 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2487
b2a3b1c1 2488 if (!trans_pcie->txq_memory)
87e5666c 2489 return -EAGAIN;
f9e75447 2490
87e5666c
EG		 2491 buf = kzalloc(bufsz, GFP_KERNEL);
2492 if (!buf)
2493 return -ENOMEM;
2494
035f7ff2 2495 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2496 txq = trans_pcie->txq[cnt];
87e5666c 2497 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2498 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2499 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2500 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2501 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2502 txq->need_update, txq->frozen,
f40faf62 2503 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2504 }
2505 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2506 kfree(buf);
2507 return ret;
2508}
2509
2510static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2511 char __user *user_buf,
2512 size_t count, loff_t *ppos)
2513{
5a878bf6 2514 struct iwl_trans *trans = file->private_data;
20d3b647 2515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2516 char *buf;
2517 int pos = 0, i, ret;
2518 size_t bufsz = sizeof(buf);
2519
2520 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2521
2522 if (!trans_pcie->rxq)
2523 return -EAGAIN;
2524
2525 buf = kzalloc(bufsz, GFP_KERNEL);
2526 if (!buf)
2527 return -ENOMEM;
2528
2529 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2530 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2531
2532 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2533 i);
2534 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2535 rxq->read);
2536 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2537 rxq->write);
2538 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2539 rxq->write_actual);
2540 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2541 rxq->need_update);
2542 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2543 rxq->free_count);
2544 if (rxq->rb_stts) {
0307c839
GBA		 2545 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2546 rxq));
78485054
SS		 2547 pos += scnprintf(buf + pos, bufsz - pos,
2548 "\tclosed_rb_num: %u\n",
0307c839 2549 r & 0x0FFF);
78485054
SS		 2550 } else {
2551 pos += scnprintf(buf + pos, bufsz - pos,
2552 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2553 }
87e5666c 2554 }
78485054
SS		 2555 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2556 kfree(buf);
2557
2558 return ret;
87e5666c
EG		 2559}
2560
1f7b6172
EG		 2561static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2562 char __user *user_buf,
20d3b647
JB		 2563 size_t count, loff_t *ppos)
2564{
1f7b6172 2565 struct iwl_trans *trans = file->private_data;
20d3b647 2566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2567 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2568
2569 int pos = 0;
2570 char *buf;
2571 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2572 ssize_t ret;
2573
2574 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2575 if (!buf)
1f7b6172 2576 return -ENOMEM;
1f7b6172
EG		 2577
2578 pos += scnprintf(buf + pos, bufsz - pos,
2579 "Interrupt Statistics Report:\n");
2580
2581 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2582 isr_stats->hw);
2583 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2584 isr_stats->sw);
2585 if (isr_stats->sw || isr_stats->hw) {
2586 pos += scnprintf(buf + pos, bufsz - pos,
2587 "\tLast Restarting Code: 0x%X\n",
2588 isr_stats->err_code);
2589 }
2590#ifdef CONFIG_IWLWIFI_DEBUG
2591 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2592 isr_stats->sch);
2593 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2594 isr_stats->alive);
2595#endif
2596 pos += scnprintf(buf + pos, bufsz - pos,
2597 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2598
2599 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2600 isr_stats->ctkill);
2601
2602 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2603 isr_stats->wakeup);
2604
2605 pos += scnprintf(buf + pos, bufsz - pos,
2606 "Rx command responses:\t\t %u\n", isr_stats->rx);
2607
2608 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2609 isr_stats->tx);
2610
2611 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2612 isr_stats->unhandled);
2613
2614 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2615 kfree(buf);
2616 return ret;
2617}
2618
2619static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2620 const char __user *user_buf,
2621 size_t count, loff_t *ppos)
2622{
2623 struct iwl_trans *trans = file->private_data;
20d3b647 2624 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2625 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2626 u32 reset_flag;
078f1131 2627 int ret;
1f7b6172 2628
078f1131
JB		 2629 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2630 if (ret)
2631 return ret;
1f7b6172
EG		 2632 if (reset_flag == 0)
2633 memset(isr_stats, 0, sizeof(*isr_stats));
2634
2635 return count;
2636}
2637
16db88ba 2638static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2639 const char __user *user_buf,
2640 size_t count, loff_t *ppos)
16db88ba
EG		 2641{
2642 struct iwl_trans *trans = file->private_data;
16db88ba 2643
990aa6d7 2644 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2645
2646 return count;
2647}
2648
16db88ba 2649static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2650 char __user *user_buf,
2651 size_t count, loff_t *ppos)
16db88ba
EG		 2652{
2653 struct iwl_trans *trans = file->private_data;
94543a8d 2654 char *buf = NULL;
56c2477f 2655 ssize_t ret;
16db88ba 2656
56c2477f
JB		 2657 ret = iwl_dump_fh(trans, &buf);
2658 if (ret < 0)
2659 return ret;
2660 if (!buf)
2661 return -EINVAL;
2662 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2663 kfree(buf);
16db88ba
EG		 2664 return ret;
2665}
2666
fa4de7f7
JB		 2667static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2668 char __user *user_buf,
2669 size_t count, loff_t *ppos)
2670{
2671 struct iwl_trans *trans = file->private_data;
2672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2673 char buf[100];
2674 int pos;
2675
2676 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2677 trans_pcie->debug_rfkill,
2678 !(iwl_read32(trans, CSR_GP_CNTRL) &
2679 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2680
2681 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2682}
2683
2684static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2685 const char __user *user_buf,
2686 size_t count, loff_t *ppos)
2687{
2688 struct iwl_trans *trans = file->private_data;
2689 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2690 bool old = trans_pcie->debug_rfkill;
2691 int ret;
2692
2693 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2694 if (ret)
2695 return ret;
2696 if (old == trans_pcie->debug_rfkill)
2697 return count;
2698 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2699 old, trans_pcie->debug_rfkill);
2700 iwl_pcie_handle_rfkill_irq(trans);
2701
2702 return count;
2703}
2704
f7805b33
LC		 2705static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2706 struct file *file)
2707{
2708 struct iwl_trans *trans = inode->i_private;
2709 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2710
2711 if (!trans->dbg_dest_tlv ||
2712 trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) {
2713 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2714 return -ENOENT;
2715 }
2716
2717 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2718 return -EBUSY;
2719
2720 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2721 return simple_open(inode, file);
2722}
2723
2724static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2725 struct file *file)
2726{
2727 struct iwl_trans_pcie *trans_pcie =
2728 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2729
2730 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2731 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2732 return 0;
2733}
2734
2735static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2736 void *buf, ssize_t *size,
2737 ssize_t *bytes_copied)
2738{
2739 int buf_size_left = count - *bytes_copied;
2740
2741 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2742 if (*size > buf_size_left)
2743 *size = buf_size_left;
2744
2745 *size -= copy_to_user(user_buf, buf, *size);
2746 *bytes_copied += *size;
2747
2748 if (buf_size_left == *size)
2749 return true;
2750 return false;
2751}
2752
2753static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2754 char __user *user_buf,
2755 size_t count, loff_t *ppos)
2756{
2757 struct iwl_trans *trans = file->private_data;
2758 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2759 void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf;
2760 struct cont_rec *data = &trans_pcie->fw_mon_data;
2761 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2762 ssize_t size, bytes_copied = 0;
2763 bool b_full;
2764
2765 if (trans->dbg_dest_tlv) {
2766 write_ptr_addr =
2767 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2768 wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2769 } else {
2770 write_ptr_addr = MON_BUFF_WRPTR;
2771 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2772 }
2773
2774 if (unlikely(!trans->dbg_rec_on))
2775 return 0;
2776
2777 mutex_lock(&data->mutex);
2778 if (data->state ==
2779 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2780 mutex_unlock(&data->mutex);
2781 return 0;
2782 }
2783
2784 /* write_ptr position in bytes rather then DW */
2785 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2786 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2787
2788 if (data->prev_wrap_cnt == wrap_cnt) {
2789 size = write_ptr - data->prev_wr_ptr;
2790 curr_buf = cpu_addr + data->prev_wr_ptr;
2791 b_full = iwl_write_to_user_buf(user_buf, count,
2792 curr_buf, &size,
2793 &bytes_copied);
2794 data->prev_wr_ptr += size;
2795
2796 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2797 write_ptr < data->prev_wr_ptr) {
2798 size = trans->fw_mon[0].size - data->prev_wr_ptr;
2799 curr_buf = cpu_addr + data->prev_wr_ptr;
2800 b_full = iwl_write_to_user_buf(user_buf, count,
2801 curr_buf, &size,
2802 &bytes_copied);
2803 data->prev_wr_ptr += size;
2804
2805 if (!b_full) {
2806 size = write_ptr;
2807 b_full = iwl_write_to_user_buf(user_buf, count,
2808 cpu_addr, &size,
2809 &bytes_copied);
2810 data->prev_wr_ptr = size;
2811 data->prev_wrap_cnt++;
2812 }
2813 } else {
2814 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2815 write_ptr > data->prev_wr_ptr)
2816 IWL_WARN(trans,
2817 "write pointer passed previous write pointer, start copying from the beginning\n");
2818 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2819 data->prev_wr_ptr == 0))
2820 IWL_WARN(trans,
2821 "monitor data is out of sync, start copying from the beginning\n");
2822
2823 size = write_ptr;
2824 b_full = iwl_write_to_user_buf(user_buf, count,
2825 cpu_addr, &size,
2826 &bytes_copied);
2827 data->prev_wr_ptr = size;
2828 data->prev_wrap_cnt = wrap_cnt;
2829 }
2830
2831 mutex_unlock(&data->mutex);
2832
2833 return bytes_copied;
2834}
2835
1f7b6172 2836DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2837DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2838DEBUGFS_READ_FILE_OPS(rx_queue);
2839DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2840DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2841DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2842
f7805b33
LC		 2843static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2844 .read = iwl_dbgfs_monitor_data_read,
2845 .open = iwl_dbgfs_monitor_data_open,
2846 .release = iwl_dbgfs_monitor_data_release,
2847};
2848
f8a1edb7
JB		 2849/* Create the debugfs files and directories */
2850int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2851{
f8a1edb7
JB		 2852 struct dentry *dir = trans->dbgfs_dir;
2853
2ef00c53
JP		 2854 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2855 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2856 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2857 DEBUGFS_ADD_FILE(csr, dir, 0200);
2858 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2859 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 2860 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
87e5666c 2861 return 0;
9da987ac
MV		 2862
2863err:
2864 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2865 return -ENOMEM;
87e5666c 2866}
f7805b33
LC		 2867
2868static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2869{
2870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2871 struct cont_rec *data = &trans_pcie->fw_mon_data;
2872
2873 mutex_lock(&data->mutex);
2874 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2875 mutex_unlock(&data->mutex);
2876}
aadede6e 2877#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2878
6983ba69 2879static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2880{
3cd1980b 2881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2882 u32 cmdlen = 0;
2883 int i;
2884
3cd1980b 2885 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2886 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2887
2888 return cmdlen;
2889}
2890
bd7fc617
EG		 2891static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2892 struct iwl_fw_error_dump_data **data,
2893 int allocated_rb_nums)
2894{
2895 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2896 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2897 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2898 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2899 u32 i, r, j, rb_len = 0;
2900
2901 spin_lock(&rxq->lock);
2902
0307c839 2903 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2904
2905 for (i = rxq->read, j = 0;
2906 i != r && j < allocated_rb_nums;
2907 i = (i + 1) & RX_QUEUE_MASK, j++) {
2908 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2909 struct iwl_fw_error_dump_rb *rb;
2910
2911 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2912 DMA_FROM_DEVICE);
2913
2914 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2915
2916 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2917 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2918 rb = (void *)(*data)->data;
2919 rb->index = cpu_to_le32(i);
2920 memcpy(rb->data, page_address(rxb->page), max_len);
2921 /* remap the page for the free benefit */
2922 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2923 max_len,
2924 DMA_FROM_DEVICE);
2925
2926 *data = iwl_fw_error_next_data(*data);
2927 }
2928
2929 spin_unlock(&rxq->lock);
2930
2931 return rb_len;
2932}
473ad712
EG		 2933#define IWL_CSR_TO_DUMP (0x250)
2934
2935static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2936 struct iwl_fw_error_dump_data **data)
2937{
2938 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2939 __le32 *val;
2940 int i;
2941
2942 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2943 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2944 val = (void *)(*data)->data;
2945
2946 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2947 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2948
2949 *data = iwl_fw_error_next_data(*data);
2950
2951 return csr_len;
2952}
2953
06d51e0d
LK		 2954static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2955 struct iwl_fw_error_dump_data **data)
2956{
2957 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2958 unsigned long flags;
2959 __le32 *val;
2960 int i;
2961
23ba9340 2962 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2963 return 0;
2964
2965 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2966 (*data)->len = cpu_to_le32(fh_regs_len);
2967 val = (void *)(*data)->data;
2968
723b45e2
LK		 2969 if (!trans->cfg->gen2)
2970 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2971 i += sizeof(u32))
2972 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2973 else
ea695b7c
ST		 2974 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
2975 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 2976 i += sizeof(u32))
2977 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2978 i));
06d51e0d
LK		 2979
2980 iwl_trans_release_nic_access(trans, &flags);
2981
2982 *data = iwl_fw_error_next_data(*data);
2983
2984 return sizeof(**data) + fh_regs_len;
2985}
2986
cc79ef66
LK		 2987static u32
2988iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2989 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2990 u32 monitor_len)
2991{
2992 u32 buf_size_in_dwords = (monitor_len >> 2);
2993 u32 *buffer = (u32 *)fw_mon_data->data;
2994 unsigned long flags;
2995 u32 i;
2996
23ba9340 2997 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2998 return 0;
2999
ea695b7c 3000 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 3001 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 3002 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3003 MON_DMARB_RD_DATA_ADDR);
3004 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 3005
3006 iwl_trans_release_nic_access(trans, &flags);
3007
3008 return monitor_len;
3009}
3010
7a14c23d
SS		 3011static void
3012iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3013 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3014{
c88580e1
SM		 3015 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3016
3017 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3018 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3019 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3020 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3021 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3022 } else if (trans->ini_valid) {
ea695b7c
ST		 3023 base = iwl_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2);
3024 write_ptr = iwl_umac_prph(trans, MON_BUFF_WRPTR_VER2);
3025 wrap_cnt = iwl_umac_prph(trans, MON_BUFF_CYCLE_CNT_VER2);
7a14c23d
SS		 3026 } else if (trans->dbg_dest_tlv) {
3027 write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
3028 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
3029 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3030 } else {
3031 base = MON_BUFF_BASE_ADDR;
3032 write_ptr = MON_BUFF_WRPTR;
3033 wrap_cnt = MON_BUFF_CYCLE_CNT;
3034 }
c88580e1
SM		 3035
3036 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3037 fw_mon_data->fw_mon_cycle_cnt =
3038 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3039 fw_mon_data->fw_mon_base_ptr =
3040 cpu_to_le32(iwl_read_prph(trans, base));
c88580e1
SM		 3041 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3042 fw_mon_data->fw_mon_base_high_ptr =
3043 cpu_to_le32(iwl_read_prph(trans, base_high));
3044 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3045 }
3046 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3047}
3048
36fb9017
OG		 3049static u32
3050iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3051 struct iwl_fw_error_dump_data **data,
3052 u32 monitor_len)
3053{
36fb9017
OG		 3054 u32 len = 0;
3055
88964b2e 3056 if ((trans->num_blocks &&
c88580e1
SM		 3057 (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3058 trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210 ||
3059 trans->ini_valid)) ||
3060 (trans->dbg_dest_tlv && !trans->ini_valid)) {
36fb9017 3061 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3062
3063 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3064 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3065
3066 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3067
3068 len += sizeof(**data) + sizeof(*fw_mon_data);
88964b2e 3069 if (trans->num_blocks) {
36fb9017 3070 memcpy(fw_mon_data->data,
88964b2e
SS		 3071 trans->fw_mon[0].block,
3072 trans->fw_mon[0].size);
36fb9017 3073
88964b2e 3074 monitor_len = trans->fw_mon[0].size;
36fb9017 3075 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3076 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3077 /*
3078 * Update pointers to reflect actual values after
3079 * shifting
3080 */
fd527eb5
GBA		 3081 if (trans->dbg_dest_tlv->version) {
3082 base = (iwl_read_prph(trans, base) &
3083 IWL_LDBG_M2S_BUF_BA_MSK) <<
3084 trans->dbg_dest_tlv->base_shift;
3085 base *= IWL_M2S_UNIT_SIZE;
3086 base += trans->cfg->smem_offset;
3087 } else {
3088 base = iwl_read_prph(trans, base) <<
3089 trans->dbg_dest_tlv->base_shift;
3090 }
3091
36fb9017
OG		 3092 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3093 monitor_len / sizeof(u32));
3094 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
3095 monitor_len =
3096 iwl_trans_pci_dump_marbh_monitor(trans,
3097 fw_mon_data,
3098 monitor_len);
3099 } else {
3100 /* Didn't match anything - output no monitor data */
3101 monitor_len = 0;
3102 }
3103
3104 len += monitor_len;
3105 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3106 }
3107
3108 return len;
3109}
3110
93079fd5 3111static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3112{
88964b2e 3113 if (trans->num_blocks) {
da752717
SM		 3114 *len += sizeof(struct iwl_fw_error_dump_data) +
3115 sizeof(struct iwl_fw_error_dump_fw_mon) +
88964b2e
SS		 3116 trans->fw_mon[0].size;
3117 return trans->fw_mon[0].size;
99684ae3 3118 } else if (trans->dbg_dest_tlv) {
da752717 3119 u32 base, end, cfg_reg, monitor_len;
99684ae3 3120
fd527eb5
GBA		 3121 if (trans->dbg_dest_tlv->version == 1) {
3122 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3123 cfg_reg = iwl_read_prph(trans, cfg_reg);
3124 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3125 trans->dbg_dest_tlv->base_shift;
3126 base *= IWL_M2S_UNIT_SIZE;
3127 base += trans->cfg->smem_offset;
99684ae3 3128
fd527eb5
GBA		 3129 monitor_len =
3130 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3131 trans->dbg_dest_tlv->end_shift;
3132 monitor_len *= IWL_M2S_UNIT_SIZE;
3133 } else {
3134 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3135 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
99684ae3 3136
fd527eb5
GBA		 3137 base = iwl_read_prph(trans, base) <<
3138 trans->dbg_dest_tlv->base_shift;
3139 end = iwl_read_prph(trans, end) <<
3140 trans->dbg_dest_tlv->end_shift;
3141
3142 /* Make "end" point to the actual end */
3143 if (trans->cfg->device_family >=
3144 IWL_DEVICE_FAMILY_8000 ||
3145 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
3146 end += (1 << trans->dbg_dest_tlv->end_shift);
3147 monitor_len = end - base;
3148 }
da752717
SM		 3149 *len += sizeof(struct iwl_fw_error_dump_data) +
3150 sizeof(struct iwl_fw_error_dump_fw_mon) +
3151 monitor_len;
3152 return monitor_len;
99684ae3 3153 }
da752717
SM		 3154 return 0;
3155}
3156
3157static struct iwl_trans_dump_data
3158*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
79f033f6 3159 u32 dump_mask)
da752717
SM		 3160{
3161 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3162 struct iwl_fw_error_dump_data *data;
3163 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3164 struct iwl_fw_error_dump_txcmd *txcmd;
3165 struct iwl_trans_dump_data *dump_data;
fefbf853 3166 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3167 int i, ptr;
3168 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3169 !trans->cfg->mq_rx_supported &&
79f033f6
SS		 3170 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3171
3172 if (!dump_mask)
3173 return NULL;
da752717
SM		 3174
3175 /* transport dump header */
3176 len = sizeof(*dump_data);
3177
3178 /* host commands */
8672aad3
SM		 3179 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD))
3180 len += sizeof(*data) +
3181 cmdq->n_window * (sizeof(*txcmd) +
3182 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3183
3184 /* FW monitor */
fefbf853
SM		 3185 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3186 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3187
3188 /* CSR registers */
79f033f6 3189 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3190 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3191
36fb9017 3192 /* FH registers */
79f033f6 3193 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
520f03ea
SM		 3194 if (trans->cfg->gen2)
3195 len += sizeof(*data) +
ea695b7c
ST		 3196 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3197 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3198 else
3199 len += sizeof(*data) +
3200 (FH_MEM_UPPER_BOUND -
3201 FH_MEM_LOWER_BOUND);
3202 }
36fb9017
OG		 3203
3204 if (dump_rbs) {
78485054
SS		 3205 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3206 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3207 /* RBs */
0307c839
GBA		 3208 num_rbs =
3209 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3210 & 0x0FFF;
78485054 3211 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3212 len += num_rbs * (sizeof(*data) +
3213 sizeof(struct iwl_fw_error_dump_rb) +
3214 (PAGE_SIZE << trans_pcie->rx_page_order));
3215 }
3216
5538409b 3217 /* Paged memory for gen2 HW */
79f033f6 3218 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3219 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3220 len += sizeof(*data) +
3221 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3222 trans->init_dram.paging[i].size;
5538409b 3223
48eb7b34
EG		 3224 dump_data = vzalloc(len);
3225 if (!dump_data)
3226 return NULL;
4d075007
JB		 3227
3228 len = 0;
48eb7b34 3229 data = (void *)dump_data->data;
520f03ea 3230
79f033f6 3231 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) {
520f03ea
SM		 3232 u16 tfd_size = trans_pcie->tfd_size;
3233
3234 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3235 txcmd = (void *)data->data;
3236 spin_lock_bh(&cmdq->lock);
3237 ptr = cmdq->write_ptr;
3238 for (i = 0; i < cmdq->n_window; i++) {
3239 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3240 u32 caplen, cmdlen;
3241
3242 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3243 cmdq->tfds +
3244 tfd_size * ptr);
3245 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3246
3247 if (cmdlen) {
3248 len += sizeof(*txcmd) + caplen;
3249 txcmd->cmdlen = cpu_to_le32(cmdlen);
3250 txcmd->caplen = cpu_to_le32(caplen);
3251 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3252 caplen);
3253 txcmd = (void *)((u8 *)txcmd->data + caplen);
3254 }
3255
3256 ptr = iwl_queue_dec_wrap(trans, ptr);
4d075007 3257 }
520f03ea 3258 spin_unlock_bh(&cmdq->lock);
4d075007 3259
520f03ea
SM		 3260 data->len = cpu_to_le32(len);
3261 len += sizeof(*data);
3262 data = iwl_fw_error_next_data(data);
4d075007 3263 }
67c65f2c 3264
79f033f6 3265 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3266 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3267 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3268 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3269 if (dump_rbs)
3270 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3271
5538409b 3272 /* Paged memory for gen2 HW */
79f033f6 3273 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3274 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3275 struct iwl_fw_error_dump_paging *paging;
505a00c0 3276 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3277
3278 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3279 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3280 paging = (void *)data->data;
3281 paging->index = cpu_to_le32(i);
5538409b 3282 memcpy(paging->data,
505a00c0 3283 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3284 data = iwl_fw_error_next_data(data);
3285
3286 len += sizeof(*data) + sizeof(*paging) + page_len;
3287 }
3288 }
79f033f6 3289 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3290 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3291
48eb7b34
EG		 3292 dump_data->len = len;
3293
3294 return dump_data;
4d075007 3295}
87e5666c 3296
4cbb8e50
LC		 3297#ifdef CONFIG_PM_SLEEP
3298static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3299{
e4c49c49
LC		 3300 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3301 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3302 return iwl_pci_fw_enter_d0i3(trans);
3303
3304 return 0;
3305}
3306
3307static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3308{
e4c49c49
LC		 3309 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3310 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3311 iwl_pci_fw_exit_d0i3(trans);
3312}
3313#endif /* CONFIG_PM_SLEEP */
3314
623e7766
SS		 3315#define IWL_TRANS_COMMON_OPS \
3316 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3317 .write8 = iwl_trans_pcie_write8, \
3318 .write32 = iwl_trans_pcie_write32, \
3319 .read32 = iwl_trans_pcie_read32, \
3320 .read_prph = iwl_trans_pcie_read_prph, \
3321 .write_prph = iwl_trans_pcie_write_prph, \
3322 .read_mem = iwl_trans_pcie_read_mem, \
3323 .write_mem = iwl_trans_pcie_write_mem, \
3324 .configure = iwl_trans_pcie_configure, \
3325 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3326 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3327 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3328 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3329 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3330 .ref = iwl_trans_pcie_ref, \
3331 .unref = iwl_trans_pcie_unref, \
3332 .dump_data = iwl_trans_pcie_dump_data, \
623e7766
SS		 3333 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3334 .d3_resume = iwl_trans_pcie_d3_resume
3335
3336#ifdef CONFIG_PM_SLEEP
3337#define IWL_TRANS_PM_OPS \
3338 .suspend = iwl_trans_pcie_suspend, \
3339 .resume = iwl_trans_pcie_resume,
3340#else
3341#define IWL_TRANS_PM_OPS
3342#endif /* CONFIG_PM_SLEEP */
3343
d1ff5253 3344static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3345 IWL_TRANS_COMMON_OPS,
3346 IWL_TRANS_PM_OPS
57a1dc89 3347 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3348 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3349 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3350 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3351
623e7766 3352 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3353
623e7766
SS		 3354 .tx = iwl_trans_pcie_tx,
3355 .reclaim = iwl_trans_pcie_reclaim,
3356
3357 .txq_disable = iwl_trans_pcie_txq_disable,
3358 .txq_enable = iwl_trans_pcie_txq_enable,
3359
3360 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3361
d6d517b7
SS		 3362 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3363
623e7766
SS		 3364 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3365 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3366#ifdef CONFIG_IWLWIFI_DEBUGFS
3367 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3368#endif
623e7766
SS		 3369};
3370
3371static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3372 IWL_TRANS_COMMON_OPS,
3373 IWL_TRANS_PM_OPS
3374 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3375 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3376 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3377 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3378
ca60da2e 3379 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3380
ab6c6445 3381 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3382 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3383
6b35ff91
SS		 3384 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3385 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3386 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3387 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
f7805b33
LC		 3388#ifdef CONFIG_IWLWIFI_DEBUGFS
3389 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3390#endif
e6bb4c9c 3391};
a42a1844 3392
87ce05a2 3393struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 3394 const struct pci_device_id *ent,
3395 const struct iwl_cfg *cfg)
a42a1844 3396{
a42a1844
EG		 3397 struct iwl_trans_pcie *trans_pcie;
3398 struct iwl_trans *trans;
96a6497b 3399 int ret, addr_size;
a42a1844 3400
5a41a86c
SD		 3401 ret = pcim_enable_device(pdev);
3402 if (ret)
3403 return ERR_PTR(ret);
3404
623e7766
SS		 3405 if (cfg->gen2)
3406 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3407 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3408 else
3409 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3410 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 3411 if (!trans)
3412 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3413
3414 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3415
a42a1844 3416 trans_pcie->trans = trans;
326477e4 3417 trans_pcie->opmode_down = true;
7b11488f 3418 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3419 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3420 mutex_init(&trans_pcie->mutex);
13df1aab 3421 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 3422 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3423 if (!trans_pcie->tso_hdr_page) {
3424 ret = -ENOMEM;
3425 goto out_no_pci;
3426 }
a42a1844 3427
d819c6cf 3428
f2532b04
EG		 3429 if (!cfg->base_params->pcie_l1_allowed) {
3430 /*
3431 * W/A - seems to solve weird behavior. We need to remove this
3432 * if we don't want to stay in L1 all the time. This wastes a
3433 * lot of power.
3434 */
3435 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3436 PCIE_LINK_STATE_L1 |
3437 PCIE_LINK_STATE_CLKPM);
3438 }
a42a1844 3439
9416560e
GBA		 3440 trans_pcie->def_rx_queue = 0;
3441
6983ba69 3442 if (cfg->use_tfh) {
2c6262b7 3443 addr_size = 64;
3cd1980b 3444 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3445 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3446 } else {
2c6262b7 3447 addr_size = 36;
3cd1980b 3448 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3449 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3450 }
3cd1980b
SS		 3451 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3452
a42a1844
EG		 3453 pci_set_master(pdev);
3454
96a6497b 3455 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3456 if (!ret)
96a6497b
SS		 3457 ret = pci_set_consistent_dma_mask(pdev,
3458 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3459 if (ret) {
3460 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3461 if (!ret)
3462 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3463 DMA_BIT_MASK(32));
a42a1844 3464 /* both attempts failed: */
af3f2f74 3465 if (ret) {
6a4b09f8 3466 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3467 goto out_no_pci;
a42a1844
EG		 3468 }
3469 }
3470
5a41a86c 3471 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3472 if (ret) {
5a41a86c
SD		 3473 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3474 goto out_no_pci;
a42a1844
EG		 3475 }
3476
5a41a86c 3477 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3478 if (!trans_pcie->hw_base) {
5a41a86c 3479 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3480 ret = -ENODEV;
5a41a86c 3481 goto out_no_pci;
a42a1844
EG		 3482 }
3483
a42a1844
EG		 3484 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3485 * PCI Tx retries from interfering with C3 CPU state */
3486 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3487
83f7a85f
EG		 3488 trans_pcie->pci_dev = pdev;
3489 iwl_disable_interrupts(trans);
3490
08079a49 3491 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3492 if (trans->hw_rev == 0xffffffff) {
3493 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3494 ret = -EIO;
3495 goto out_no_pci;
3496 }
3497
b513ee7f
LK		 3498 /*
3499 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3500 * changed, and now the revision step also includes bit 0-1 (no more
3501 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3502 * in the old format.
3503 */
6e584873 3504 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
7a42baa6 3505 unsigned long flags;
7a42baa6 3506
b513ee7f 3507 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3508 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3509
f9e5554c
EG		 3510 ret = iwl_pcie_prepare_card_hw(trans);
3511 if (ret) {
3512 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3513 goto out_no_pci;
f9e5554c
EG		 3514 }
3515
7a42baa6
EH		 3516 /*
3517 * in-order to recognize C step driver should read chip version
3518 * id located at the AUX bus MISC address space.
3519 */
c96b5eec
JB		 3520 ret = iwl_finish_nic_init(trans);
3521 if (ret)
5a41a86c 3522 goto out_no_pci;
7a42baa6 3523
23ba9340 3524 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3525 u32 hw_step;
3526
ea695b7c
ST		 3527 hw_step = iwl_read_umac_prph_no_grab(trans,
3528 WFPM_CTRL_REG);
7a42baa6 3529 hw_step |= ENABLE_WFPM;
ea695b7c
ST		 3530 iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG,
3531 hw_step);
14ef1b43 3532 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3533 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3534 if (hw_step == 0x3)
3535 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3536 (SILICON_C_STEP << 2);
3537 iwl_trans_release_nic_access(trans, &flags);
3538 }
3539 }
3540
99be6166
LC		 3541 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3542
f6586b69 3543#if IS_ENABLED(CONFIG_IWLMVM)
1afb0ae4 3544 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
33708052 3545
ff911dca
ST		 3546 if (cfg == &iwlax210_2ax_cfg_so_hr_a0) {
3547 if (trans->hw_rev == CSR_HW_REV_TYPE_TY) {
3548 trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0;
3549 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3550 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) {
3551 trans->cfg = &iwlax210_2ax_cfg_so_jf_a0;
3552 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3553 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) {
3554 trans->cfg = &iwlax210_2ax_cfg_so_gf_a0;
5bd757a6
ST		 3555 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3556 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF4)) {
3557 trans->cfg = &iwlax210_2ax_cfg_so_gf4_a0;
ff911dca 3558 }
085486de 3559 } else if (cfg == &iwl_ax101_cfg_qu_hr) {
b1bbc1a6
LC		 3560 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3561 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
085486de 3562 trans->cfg = &iwl_ax101_cfg_qu_hr;
b1bbc1a6
LC		 3563 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3564 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) {
3565 trans->cfg = &iwl22000_2ax_cfg_jf;
3566 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3567 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) {
3568 IWL_ERR(trans, "RF ID HRCDB is not supported\n");
3569 ret = -EINVAL;
3570 goto out_no_pci;
3571 } else {
3572 IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n",
3573 CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id));
3574 ret = -EINVAL;
3575 goto out_no_pci;
3576 }
3577 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
8093bb6d 3578 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) &&
99be6166
LC		 3579 (trans->cfg != &iwl22260_2ax_cfg ||
3580 trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0)) {
f6586b69
TP		 3581 u32 hw_status;
3582
3583 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
33708052
LC		 3584 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP)
3585 /*
3586 * b step fw is the same for physical card and fpga
3587 */
3588 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
3589 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) &&
3590 CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) {
3591 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0;
3592 } else {
3593 /*
3594 * a step no FPGA
3595 */
2f7a3863 3596 trans->cfg = &iwl22000_2ac_cfg_hr;
33708052 3597 }
f6586b69
TP		 3598 }
3599#endif
1afb0ae4 3600
2e5d4a8f 3601 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3602 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3603 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3604 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3605
69a10b29 3606 /* Initialize the wait queue for commands */
f946b529 3607 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3608
4cbb8e50
LC		 3609 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3610
2e5d4a8f 3611 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3612 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3613 if (ret)
5a41a86c 3614 goto out_no_pci;
2e5d4a8f
HD		 3615 } else {
3616 ret = iwl_pcie_alloc_ict(trans);
3617 if (ret)
5a41a86c 3618 goto out_no_pci;
a8b691e6 3619
5a41a86c
SD		 3620 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3621 iwl_pcie_isr,
3622 iwl_pcie_irq_handler,
3623 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3624 if (ret) {
3625 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3626 goto out_free_ict;
3627 }
3628 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3629 }
83f7a85f 3630
10a54d81
LC		 3631 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3632 WQ_HIGHPRI | WQ_UNBOUND, 1);
3633 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3634
b3ff1270
LC		 3635#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3636 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3637#else
3638 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3639#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3640
f7805b33
LC		 3641#ifdef CONFIG_IWLWIFI_DEBUGFS
3642 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3643 mutex_init(&trans_pcie->fw_mon_data.mutex);
3644#endif
3645
a42a1844
EG		 3646 return trans;
3647
a8b691e6
JB		 3648out_free_ict:
3649 iwl_pcie_free_ict(trans);
a42a1844 3650out_no_pci:
6eb5e529 3651 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3652 iwl_trans_free(trans);
af3f2f74 3653 return ERR_PTR(ret);
a42a1844 3654}
b8a7547d
SM		 3655
3656void iwl_trans_sync_nmi(struct iwl_trans *trans)
3657{
3658 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
3659
3660 iwl_disable_interrupts(trans);
3661 iwl_force_nmi(trans);
3662 while (time_after(timeout, jiffies)) {
3663 u32 inta_hw = iwl_read32(trans,
3664 CSR_MSIX_HW_INT_CAUSES_AD);
3665
3666 /* Error detected by uCode */
3667 if (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) {
3668 /* Clear causes register */
3669 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
3670 inta_hw &
3671 MSIX_HW_INT_CAUSES_REG_SW_ERR);
3672 break;
3673 }
3674
3675 mdelay(1);
3676 }
3677 iwl_enable_interrupts(trans);
3678 iwl_trans_fw_error(trans);
3679}
Linux 6.x block layer and io_uring tree(s)