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wifi: iwlwifi: pcie: point invalid TFDs to invalid data
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
8e99ea8d
JB		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
583c58e3 3 * Copyright (C) 2007-2015, 2018-2023 Intel Corporation
8e99ea8d
JB		 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
a42a1844 7#include <linux/pci.h>
e6bb4c9c 8#include <linux/interrupt.h>
87e5666c 9#include <linux/debugfs.h>
cf614297 10#include <linux/sched.h>
6d8f6eeb
EG		 11#include <linux/bitops.h>
12#include <linux/gfp.h>
48eb7b34 13#include <linux/vmalloc.h>
49564a80 14#include <linux/module.h>
f7805b33 15#include <linux/wait.h>
df67a1be 16#include <linux/seq_file.h>
e6bb4c9c 17
82575102 18#include "iwl-drv.h"
c85eb619 19#include "iwl-trans.h"
522376d2
EG		 20#include "iwl-csr.h"
21#include "iwl-prph.h"
cb6bb128 22#include "iwl-scd.h"
7a10e3e4 23#include "iwl-agn-hw.h"
d962f9b1 24#include "fw/error-dump.h"
520f03ea 25#include "fw/dbg.h"
a89c72ff 26#include "fw/api/tx.h"
6d19a5eb 27#include "mei/iwl-mei.h"
6468a01a 28#include "internal.h"
06d51e0d 29#include "iwl-fh.h"
6654cd4e 30#include "iwl-context-info-gen3.h"
0439bb62 31
fe45773b
AN		 32/* extended range in FW SRAM */
33#define IWL_FW_MEM_EXTENDED_START 0x40000
34#define IWL_FW_MEM_EXTENDED_END 0x57FFF
35
4290eaad 36void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad 37{
c4d3f2ee
LC		 38#define PCI_DUMP_SIZE 352
39#define PCI_MEM_DUMP_SIZE 64
40#define PCI_PARENT_DUMP_SIZE 524
41#define PREFIX_LEN 32
a6d24fad
RJ		 42 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
43 struct pci_dev *pdev = trans_pcie->pci_dev;
44 u32 i, pos, alloc_size, *ptr, *buf;
45 char *prefix;
46
47 if (trans_pcie->pcie_dbg_dumped_once)
48 return;
49
50 /* Should be a multiple of 4 */
51 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
c4d3f2ee
LC		 52 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
53 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
54
a6d24fad 55 /* Alloc a max size buffer */
c4d3f2ee
LC		 56 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
57 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
58 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
59 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
60
a6d24fad
RJ		 61 buf = kmalloc(alloc_size, GFP_ATOMIC);
62 if (!buf)
63 return;
64 prefix = (char *)buf + alloc_size - PREFIX_LEN;
65
66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
67
68 /* Print wifi device registers */
69 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
70 IWL_ERR(trans, "iwlwifi device config registers:\n");
71 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
72 if (pci_read_config_dword(pdev, i, ptr))
73 goto err_read;
74 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
75
76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
c4d3f2ee 77 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 78 *ptr = iwl_read32(trans, i);
79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
80
81 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
82 if (pos) {
83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
84 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
85 if (pci_read_config_dword(pdev, pos + i, ptr))
86 goto err_read;
87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
88 32, 4, buf, i, 0);
89 }
90
91 /* Print parent device registers next */
92 if (!pdev->bus->self)
93 goto out;
94
95 pdev = pdev->bus->self;
96 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
97
98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
99 pci_name(pdev));
c4d3f2ee 100 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 101 if (pci_read_config_dword(pdev, i, ptr))
102 goto err_read;
103 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
104
105 /* Print root port AER registers */
106 pos = 0;
107 pdev = pcie_find_root_port(pdev);
108 if (pdev)
109 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
110 if (pos) {
111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
112 pci_name(pdev));
113 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
114 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
115 if (pci_read_config_dword(pdev, pos + i, ptr))
116 goto err_read;
117 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
118 4, buf, i, 0);
119 }
f3402d6d 120 goto out;
a6d24fad
RJ		 121
122err_read:
123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
124 IWL_ERR(trans, "Read failed at 0x%X\n", i);
125out:
126 trans_pcie->pcie_dbg_dumped_once = 1;
127 kfree(buf);
128}
129
15bf5ac6
JB		 130static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
131 bool retake_ownership)
870c2a11
GBA		 132{
133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
ec80c231 134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
1b6598c3
RG		 135 iwl_set_bit(trans, CSR_GP_CNTRL,
136 CSR_GP_CNTRL_REG_FLAG_SW_RESET);
ec80c231
JB		 137 usleep_range(10000, 20000);
138 } else {
1b6598c3
RG		 139 iwl_set_bit(trans, CSR_RESET,
140 CSR_RESET_REG_FLAG_SW_RESET);
ec80c231
JB		 141 usleep_range(5000, 6000);
142 }
15bf5ac6
JB		 143
144 if (retake_ownership)
145 return iwl_pcie_prepare_card_hw(trans);
146
147 return 0;
870c2a11
GBA		 148}
149
c2d20201
EG		 150static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
151{
69f0e505 152 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 153
69f0e505
SM		 154 if (!fw_mon->size)
155 return;
156
157 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
158 fw_mon->physical);
159
160 fw_mon->block = NULL;
161 fw_mon->physical = 0;
162 fw_mon->size = 0;
c2d20201
EG		 163}
164
88964b2e 165static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
855e2f60 166 u8 max_power)
c2d20201 167{
69f0e505
SM		 168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
169 void *block = NULL;
170 dma_addr_t physical = 0;
96c285da 171 u32 size = 0;
c2d20201
EG		 172 u8 power;
173
583c58e3
JB		 174 if (fw_mon->size) {
175 memset(fw_mon->block, 0, fw_mon->size);
69f0e505 176 return;
583c58e3 177 }
69f0e505 178
855e2f60
JB		 179 /* need at least 2 KiB, so stop at 11 */
180 for (power = max_power; power >= 11; power--) {
c2d20201 181 size = BIT(power);
69f0e505
SM		 182 block = dma_alloc_coherent(trans->dev, size, &physical,
183 GFP_KERNEL | __GFP_NOWARN);
184 if (!block)
c2d20201
EG		 185 continue;
186
c2d20201 187 IWL_INFO(trans,
c5f97542
SM		 188 "Allocated 0x%08x bytes for firmware monitor.\n",
189 size);
c2d20201
EG		 190 break;
191 }
192
69f0e505 193 if (WARN_ON_ONCE(!block))
c2d20201
EG		 194 return;
195
96c285da
EG		 196 if (power != max_power)
197 IWL_ERR(trans,
198 "Sorry - debug buffer is only %luK while you requested %luK\n",
199 (unsigned long)BIT(power - 10),
200 (unsigned long)BIT(max_power - 10));
201
69f0e505
SM		 202 fw_mon->block = block;
203 fw_mon->physical = physical;
204 fw_mon->size = size;
88964b2e
SS		 205}
206
207void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
208{
209 if (!max_power) {
210 /* default max_power is maximum */
211 max_power = 26;
212 } else {
213 max_power += 11;
214 }
215
216 if (WARN(max_power > 26,
217 "External buffer size for monitor is too big %d, check the FW TLV\n",
218 max_power))
219 return;
220
855e2f60 221 iwl_pcie_alloc_fw_monitor_block(trans, max_power);
c2d20201
EG		 222}
223
a812cba9
AB		 224static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
225{
226 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
227 ((reg & 0x0000ffff) | (2 << 28)));
228 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
229}
230
231static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
232{
233 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
234 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
235 ((reg & 0x0000ffff) | (3 << 28)));
236}
237
ddaf5a5b 238static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 239{
66337b7c 240 if (trans->cfg->apmg_not_supported)
95411d04
AA		 241 return;
242
ddaf5a5b
JB		 243 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
244 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
245 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
246 ~APMG_PS_CTRL_MSK_PWR_SRC);
247 else
248 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
249 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
250 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 251}
252
af634bee
EG		 253/* PCI registers */
254#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 255
eda50cde 256void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 257{
20d3b647 258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 259 u16 lctl;
9180ac50 260 u16 cap;
af634bee 261
af634bee 262 /*
cc894b85
LC		 263 * L0S states have been found to be unstable with our devices
264 * and in newer hardware they are not officially supported at
265 * all, so we must always set the L0S_DISABLED bit.
af634bee 266 */
cc894b85
LC		 267 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
268
7afe3705 269 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
438a0f0a 270 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 271
272 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
273 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 274 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
275 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
276 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 277}
278
a6c684ee
EG		 279/*
280 * Start up NIC's basic functionality after it has been reset
7afe3705 281 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 282 * NOTE: This does not load uCode nor start the embedded processor
283 */
7afe3705 284static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 285{
52b6e168
EG		 286 int ret;
287
a6c684ee
EG		 288 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
289
290 /*
291 * Use "set_bit" below rather than "write", to preserve any hardware
292 * bits already set by default after reset.
293 */
294
295 /* Disable L0S exit timer (platform NMI Work/Around) */
286ca8eb 296 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 297 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
298 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 299
300 /*
301 * Disable L0s without affecting L1;
302 * don't wait for ICH L0s (ICH bug W/A)
303 */
304 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 305 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 306
307 /* Set FH wait threshold to maximum (HW error during stress W/A) */
308 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
309
310 /*
311 * Enable HAP INTA (interrupt from management bus) to
312 * wake device's PCI Express link L1a -> L0s
313 */
314 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 315 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 316
7afe3705 317 iwl_pcie_apm_config(trans);
a6c684ee
EG		 318
319 /* Configure analog phase-lock-loop before activating to D0A */
286ca8eb 320 if (trans->trans_cfg->base_params->pll_cfg)
77d76931 321 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 322
425d66d8 323 ret = iwl_finish_nic_init(trans);
c96b5eec 324 if (ret)
52b6e168 325 return ret;
a6c684ee 326
2d93aee1
EG		 327 if (trans->cfg->host_interrupt_operation_mode) {
328 /*
329 * This is a bit of an abuse - This is needed for 7260 / 3160
330 * only check host_interrupt_operation_mode even if this is
331 * not related to host_interrupt_operation_mode.
332 *
333 * Enable the oscillator to count wake up time for L1 exit. This
334 * consumes slightly more power (100uA) - but allows to be sure
335 * that we wake up from L1 on time.
336 *
337 * This looks weird: read twice the same register, discard the
338 * value, set a bit, and yet again, read that same register
339 * just to discard the value. But that's the way the hardware
340 * seems to like it.
341 */
342 iwl_read_prph(trans, OSC_CLK);
343 iwl_read_prph(trans, OSC_CLK);
344 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
345 iwl_read_prph(trans, OSC_CLK);
346 iwl_read_prph(trans, OSC_CLK);
347 }
348
a6c684ee
EG		 349 /*
350 * Enable DMA clock and wait for it to stabilize.
351 *
3073d8c0
EH		 352 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
353 * bits do not disable clocks. This preserves any hardware
354 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 355 */
95411d04 356 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 357 iwl_write_prph(trans, APMG_CLK_EN_REG,
358 APMG_CLK_VAL_DMA_CLK_RQT);
359 udelay(20);
360
361 /* Disable L1-Active */
362 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
363 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
364
365 /* Clear the interrupt in APMG if the NIC is in RFKILL */
366 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
367 APMG_RTC_INT_STT_RFKILL);
368 }
889b1696 369
eb7ff77e 370 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 371
52b6e168 372 return 0;
a6c684ee
EG		 373}
374
a812cba9
AB		 375/*
376 * Enable LP XTAL to avoid HW bug where device may consume much power if
377 * FW is not loaded after device reset. LP XTAL is disabled by default
378 * after device HW reset. Do it only if XTAL is fed by internal source.
379 * Configure device's "persistence" mode to avoid resetting XTAL again when
380 * SHRD_HW_RST occurs in S3.
381 */
382static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
383{
384 int ret;
385 u32 apmg_gp1_reg;
386 u32 apmg_xtal_cfg_reg;
387 u32 dl_cfg_reg;
388
389 /* Force XTAL ON */
390 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
391 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
392
15bf5ac6
JB		 393 ret = iwl_trans_pcie_sw_reset(trans, true);
394
395 if (!ret)
396 ret = iwl_finish_nic_init(trans);
a812cba9 397
c96b5eec 398 if (WARN_ON(ret)) {
a812cba9
AB		 399 /* Release XTAL ON request */
400 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
401 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
402 return;
403 }
404
405 /*
406 * Clear "disable persistence" to avoid LP XTAL resetting when
407 * SHRD_HW_RST is applied in S3.
408 */
409 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
410 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
411
412 /*
413 * Force APMG XTAL to be active to prevent its disabling by HW
414 * caused by APMG idle state.
415 */
416 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
417 SHR_APMG_XTAL_CFG_REG);
418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
419 apmg_xtal_cfg_reg |
420 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
421
15bf5ac6
JB		 422 ret = iwl_trans_pcie_sw_reset(trans, true);
423 if (ret)
424 IWL_ERR(trans,
425 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n");
a812cba9
AB		 426
427 /* Enable LP XTAL by indirect access through CSR */
428 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
429 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
430 SHR_APMG_GP1_WF_XTAL_LP_EN |
431 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
432
433 /* Clear delay line clock power up */
434 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
435 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
436 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
437
438 /*
439 * Enable persistence mode to avoid LP XTAL resetting when
440 * SHRD_HW_RST is applied in S3.
441 */
442 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
443 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
444
445 /*
446 * Clear "initialization complete" bit to move adapter from
447 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
448 */
6dece0e9 449 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
a812cba9
AB		 450
451 /* Activates XTAL resources monitor */
452 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
453 CSR_MONITOR_XTAL_RESOURCES);
454
455 /* Release XTAL ON request */
456 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
457 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
458 udelay(10);
459
460 /* Release APMG XTAL */
461 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
462 apmg_xtal_cfg_reg &
463 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
464}
465
e8c8935e 466void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 467{
e8c8935e 468 int ret;
cc56feb2
EG		 469
470 /* stop device's busmaster DMA activity */
cc56feb2 471
9ce041f5
JB		 472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
473 iwl_set_bit(trans, CSR_GP_CNTRL,
474 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
475
476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
477 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
478 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
479 100);
ec80c231 480 usleep_range(10000, 20000);
9ce041f5
JB		 481 } else {
482 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
483
484 ret = iwl_poll_bit(trans, CSR_RESET,
485 CSR_RESET_REG_FLAG_MASTER_DISABLED,
486 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
487 }
488
7f2ac8fb 489 if (ret < 0)
cc56feb2
EG		 490 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
491
492 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 493}
494
b7aaeae4 495static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 496{
497 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
498
b7aaeae4
EG		 499 if (op_mode_leave) {
500 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
501 iwl_pcie_apm_init(trans);
502
503 /* inform ME that we are leaving */
286ca8eb 504 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
b7aaeae4
EG		 505 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
506 APMG_PCIDEV_STT_VAL_WAKE_ME);
286ca8eb 507 else if (trans->trans_cfg->device_family >=
79b6c8fe 508 IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 509 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
510 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
512 CSR_HW_IF_CONFIG_REG_PREPARE |
513 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 514 mdelay(1);
515 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
516 CSR_RESET_LINK_PWR_MGMT_DISABLED);
517 }
b7aaeae4
EG		 518 mdelay(5);
519 }
520
eb7ff77e 521 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 522
523 /* Stop device's DMA activity */
7afe3705 524 iwl_pcie_apm_stop_master(trans);
cc56feb2 525
a812cba9
AB		 526 if (trans->cfg->lp_xtal_workaround) {
527 iwl_pcie_apm_lp_xtal_enable(trans);
528 return;
529 }
530
15bf5ac6 531 iwl_trans_pcie_sw_reset(trans, false);
cc56feb2
EG		 532
533 /*
534 * Clear "initialization complete" bit to move adapter from
535 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
536 */
6dece0e9 537 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
cc56feb2
EG		 538}
539
7afe3705 540static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 541{
7b11488f 542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 543 int ret;
392f8b78
EG		 544
545 /* nic_init */
25edc8f2 546 spin_lock_bh(&trans_pcie->irq_lock);
52b6e168 547 ret = iwl_pcie_apm_init(trans);
25edc8f2 548 spin_unlock_bh(&trans_pcie->irq_lock);
392f8b78 549
52b6e168
EG		 550 if (ret)
551 return ret;
552
95411d04 553 iwl_pcie_set_pwr(trans, false);
392f8b78 554
ecdb975c 555 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 556
557 /* Allocate the RX queue, or reset if it is already allocated */
9cf671d6
EG		 558 ret = iwl_pcie_rx_init(trans);
559 if (ret)
560 return ret;
392f8b78
EG		 561
562 /* Allocate or reset and init all Tx and Command queues */
9cf671d6
EG		 563 if (iwl_pcie_tx_init(trans)) {
564 iwl_pcie_rx_free(trans);
392f8b78 565 return -ENOMEM;
9cf671d6 566 }
392f8b78 567
286ca8eb 568 if (trans->trans_cfg->base_params->shadow_reg_enable) {
392f8b78 569 /* enable shadow regs in HW */
20d3b647 570 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 571 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 572 }
573
392f8b78
EG		 574 return 0;
575}
576
577#define HW_READY_TIMEOUT (50)
578
579/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 580static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 581{
582 int ret;
583
1042db2a 584 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 585 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 586
587 /* See if we got it */
1042db2a 588 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 589 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
590 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
591 HW_READY_TIMEOUT);
392f8b78 592
6a08f514
EG		 593 if (ret >= 0)
594 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
595
6d8f6eeb 596 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 597 return ret;
598}
599
600/* Note: returns standard 0/-ERROR code */
eda50cde 601int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 602{
603 int ret;
501fd989 604 int iter;
392f8b78 605
6d8f6eeb 606 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 607
7afe3705 608 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 609 /* If the card is ready, exit 0 */
6d19a5eb
EG		 610 if (ret >= 0) {
611 trans->csme_own = false;
392f8b78 612 return 0;
6d19a5eb 613 }
392f8b78 614
c9fdec9f
EG		 615 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
616 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 617 usleep_range(1000, 2000);
c9fdec9f 618
501fd989 619 for (iter = 0; iter < 10; iter++) {
28965ec0
EG		 620 int t = 0;
621
501fd989
EG		 622 /* If HW is not ready, prepare the conditions to check again */
623 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
624 CSR_HW_IF_CONFIG_REG_PREPARE);
625
626 do {
627 ret = iwl_pcie_set_hw_ready(trans);
6d19a5eb
EG		 628 if (ret >= 0) {
629 trans->csme_own = false;
03a19cbb 630 return 0;
6d19a5eb
EG		 631 }
632
633 if (iwl_mei_is_connected()) {
634 IWL_DEBUG_INFO(trans,
635 "Couldn't prepare the card but SAP is connected\n");
636 trans->csme_own = true;
637 if (trans->trans_cfg->device_family !=
638 IWL_DEVICE_FAMILY_9000)
639 IWL_ERR(trans,
640 "SAP not supported for this NIC family\n");
641
642 return -EBUSY;
643 }
392f8b78 644
501fd989
EG		 645 usleep_range(200, 1000);
646 t += 200;
647 } while (t < 150000);
648 msleep(25);
649 }
392f8b78 650
7f2ac8fb 651 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 652
392f8b78
EG		 653 return ret;
654}
655
cf614297
EG		 656/*
657 * ucode
658 */
564cdce7
SS		 659static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
660 u32 dst_addr, dma_addr_t phy_addr,
661 u32 byte_cnt)
cf614297 662{
bac842da
EG		 663 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
664 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
665
666 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
667 dst_addr);
668
669 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
670 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
671
672 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
673 (iwl_get_dma_hi_addr(phy_addr)
674 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
675
676 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
677 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
678 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
679 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
680
681 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
682 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
683 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
684 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 685}
686
564cdce7
SS		 687static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
688 u32 dst_addr, dma_addr_t phy_addr,
689 u32 byte_cnt)
690{
691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
564cdce7
SS		 692 int ret;
693
694 trans_pcie->ucode_write_complete = false;
695
1ed08f6f 696 if (!iwl_trans_grab_nic_access(trans))
564cdce7
SS		 697 return -EIO;
698
eda50cde
SS		 699 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
700 byte_cnt);
1ed08f6f 701 iwl_trans_release_nic_access(trans);
cf614297 702
13df1aab
JB		 703 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
704 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 705 if (!ret) {
83f84d7b 706 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 707 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 708 return -ETIMEDOUT;
709 }
710
711 return 0;
712}
713
7afe3705 714static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 715 const struct fw_desc *section)
cf614297 716{
83f84d7b
JB		 717 u8 *v_addr;
718 dma_addr_t p_addr;
baa21e83 719 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 720 int ret = 0;
721
83f84d7b
JB		 722 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
723 section_num);
724
c571573a
EG		 725 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
726 GFP_KERNEL | __GFP_NOWARN);
727 if (!v_addr) {
728 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
729 chunk_sz = PAGE_SIZE;
730 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
731 &p_addr, GFP_KERNEL);
732 if (!v_addr)
733 return -ENOMEM;
734 }
83f84d7b 735
c571573a 736 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 737 u32 copy_size, dst_addr;
738 bool extended_addr = false;
83f84d7b 739
c571573a 740 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 741 dst_addr = section->offset + offset;
742
743 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
744 dst_addr <= IWL_FW_MEM_EXTENDED_END)
745 extended_addr = true;
746
747 if (extended_addr)
748 iwl_set_bits_prph(trans, LMPM_CHICK,
749 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 750
73c289ba 751 memcpy(v_addr, (const u8 *)section->data + offset, copy_size);
fe45773b
AN		 752 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
753 copy_size);
754
755 if (extended_addr)
756 iwl_clear_bits_prph(trans, LMPM_CHICK,
757 LMPM_CHICK_EXTENDED_ADDR_SPACE);
758
83f84d7b
JB		 759 if (ret) {
760 IWL_ERR(trans,
761 "Could not load the [%d] uCode section\n",
762 section_num);
763 break;
6dfa8d01 764 }
83f84d7b
JB		 765 }
766
c571573a 767 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 768 return ret;
769}
770
5dd9c68a
EG		 771static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
772 const struct fw_img *image,
773 int cpu,
774 int *first_ucode_section)
e2d6f4e7
EH		 775{
776 int shift_param;
dcab8ecd
EH		 777 int i, ret = 0, sec_num = 0x1;
778 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 779
780 if (cpu == 1) {
781 shift_param = 0;
034846cf 782 *first_ucode_section = 0;
e2d6f4e7
EH		 783 } else {
784 shift_param = 16;
034846cf 785 (*first_ucode_section)++;
e2d6f4e7
EH		 786 }
787
eef187a7 788 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 789 last_read_idx = i;
790
a6c4fb44
MG		 791 /*
792 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
793 * CPU1 to CPU2.
794 * PAGING_SEPARATOR_SECTION delimiter - separate between
795 * CPU2 non paged to CPU2 paging sec.
796 */
034846cf 797 if (!image->sec[i].data ||
a6c4fb44
MG		 798 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
799 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 800 IWL_DEBUG_FW(trans,
801 "Break since Data not valid or Empty section, sec = %d\n",
802 i);
189fa2fa 803 break;
034846cf
EH		 804 }
805
189fa2fa
EH		 806 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
807 if (ret)
808 return ret;
dcab8ecd 809
d6a2c5c7 810 /* Notify ucode of loaded section number and status */
eda50cde
SS		 811 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
812 val = val | (sec_num << shift_param);
813 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
814
dcab8ecd 815 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 816 }
817
034846cf
EH		 818 *first_ucode_section = last_read_idx;
819
2aabdbdc
EG		 820 iwl_enable_interrupts(trans);
821
12a89f01 822 if (trans->trans_cfg->gen2) {
d6a2c5c7
SS		 823 if (cpu == 1)
824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
825 0xFFFF);
826 else
827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
828 0xFFFFFFFF);
829 } else {
830 if (cpu == 1)
831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
832 0xFFFF);
833 else
834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
835 0xFFFFFFFF);
836 }
afb88917 837
189fa2fa
EH		 838 return 0;
839}
e2d6f4e7 840
189fa2fa
EH		 841static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
842 const struct fw_img *image,
034846cf
EH		 843 int cpu,
844 int *first_ucode_section)
189fa2fa 845{
189fa2fa 846 int i, ret = 0;
034846cf 847 u32 last_read_idx = 0;
189fa2fa 848
3ce4a038 849 if (cpu == 1)
034846cf 850 *first_ucode_section = 0;
3ce4a038 851 else
034846cf 852 (*first_ucode_section)++;
189fa2fa 853
eef187a7 854 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 855 last_read_idx = i;
856
a6c4fb44
MG		 857 /*
858 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
859 * CPU1 to CPU2.
860 * PAGING_SEPARATOR_SECTION delimiter - separate between
861 * CPU2 non paged to CPU2 paging sec.
862 */
034846cf 863 if (!image->sec[i].data ||
a6c4fb44
MG		 864 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
865 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 866 IWL_DEBUG_FW(trans,
867 "Break since Data not valid or Empty section, sec = %d\n",
868 i);
189fa2fa 869 break;
034846cf
EH		 870 }
871
189fa2fa
EH		 872 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
873 if (ret)
874 return ret;
e2d6f4e7
EH		 875 }
876
034846cf
EH		 877 *first_ucode_section = last_read_idx;
878
e2d6f4e7
EH		 879 return 0;
880}
881
593fae3e
SM		 882static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
883{
884 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
885 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
886 &trans->dbg.fw_mon_cfg[alloc_id];
887 struct iwl_dram_data *frag;
888
889 if (!iwl_trans_dbg_ini_valid(trans))
890 return;
891
892 if (le32_to_cpu(fw_mon_cfg->buf_location) ==
893 IWL_FW_INI_LOCATION_SRAM_PATH) {
894 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
895 /* set sram monitor by enabling bit 7 */
896 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
897 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
898
899 return;
900 }
901
902 if (le32_to_cpu(fw_mon_cfg->buf_location) !=
903 IWL_FW_INI_LOCATION_DRAM_PATH ||
904 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
905 return;
906
907 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
908
909 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
910 alloc_id);
911
912 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
913 frag->physical >> MON_BUFF_SHIFT_VER2);
914 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
915 (frag->physical + frag->size - 256) >>
916 MON_BUFF_SHIFT_VER2);
917}
918
c9be849d 919void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 920{
91c28b83 921 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
69f0e505 922 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
09e350f7
LK		 923 int i;
924
a1af4c48 925 if (iwl_trans_dbg_ini_valid(trans)) {
593fae3e 926 iwl_pcie_apply_destination_ini(trans);
7a14c23d
SS		 927 return;
928 }
929
09e350f7
LK		 930 IWL_INFO(trans, "Applying debug destination %s\n",
931 get_fw_dbg_mode_string(dest->monitor_mode));
932
933 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 934 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 935 else
936 IWL_WARN(trans, "PCI should have external buffer debug\n");
937
91c28b83 938 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
09e350f7
LK		 939 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
940 u32 val = le32_to_cpu(dest->reg_ops[i].val);
941
942 switch (dest->reg_ops[i].op) {
943 case CSR_ASSIGN:
944 iwl_write32(trans, addr, val);
945 break;
946 case CSR_SETBIT:
947 iwl_set_bit(trans, addr, BIT(val));
948 break;
949 case CSR_CLEARBIT:
950 iwl_clear_bit(trans, addr, BIT(val));
951 break;
952 case PRPH_ASSIGN:
953 iwl_write_prph(trans, addr, val);
954 break;
955 case PRPH_SETBIT:
956 iwl_set_bits_prph(trans, addr, BIT(val));
957 break;
958 case PRPH_CLEARBIT:
959 iwl_clear_bits_prph(trans, addr, BIT(val));
960 break;
869f3b15
HD		 961 case PRPH_BLOCKBIT:
962 if (iwl_read_prph(trans, addr) & BIT(val)) {
963 IWL_ERR(trans,
964 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
965 val, addr);
966 goto monitor;
967 }
968 break;
09e350f7
LK		 969 default:
970 IWL_ERR(trans, "FW debug - unknown OP %d\n",
971 dest->reg_ops[i].op);
972 break;
973 }
974 }
975
869f3b15 976monitor:
69f0e505 977 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
09e350f7 978 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
69f0e505 979 fw_mon->physical >> dest->base_shift);
286ca8eb 980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 982 (fw_mon->physical + fw_mon->size -
983 256) >> dest->end_shift);
62d7476d
EG		 984 else
985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 986 (fw_mon->physical + fw_mon->size) >>
987 dest->end_shift);
09e350f7
LK		 988 }
989}
990
7afe3705 991static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 992 const struct fw_img *image)
cf614297 993{
189fa2fa 994 int ret = 0;
034846cf 995 int first_ucode_section;
cf614297 996
dcab8ecd 997 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 998 image->is_dual_cpus ? "Dual" : "Single");
999
dcab8ecd
EH		 1000 /* load to FW the binary non secured sections of CPU1 */
1001 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1002 if (ret)
1003 return ret;
e2d6f4e7
EH		 1004
1005 if (image->is_dual_cpus) {
189fa2fa
EH		 1006 /* set CPU2 header address */
1007 iwl_write_prph(trans,
1008 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1009 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1010
189fa2fa 1011 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1012 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1013 &first_ucode_section);
189fa2fa
EH		 1014 if (ret)
1015 return ret;
e2d6f4e7 1016 }
cf614297 1017
9efab1ad 1018 if (iwl_pcie_dbg_on(trans))
09e350f7 1019 iwl_pcie_apply_destination(trans);
c2d20201 1020
2aabdbdc
EG		 1021 iwl_enable_interrupts(trans);
1022
e12ba844 1023 /* release CPU reset */
5dd9c68a 1024 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1025
dcab8ecd
EH		 1026 return 0;
1027}
189fa2fa 1028
5dd9c68a
EG		 1029static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1030 const struct fw_img *image)
dcab8ecd
EH		 1031{
1032 int ret = 0;
1033 int first_ucode_section;
dcab8ecd
EH		 1034
1035 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1036 image->is_dual_cpus ? "Dual" : "Single");
1037
7a14c23d 1038 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 1039 iwl_pcie_apply_destination(trans);
1040
82ea7966
SS		 1041 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1042 iwl_read_prph(trans, WFPM_GP2));
1043
1044 /*
1045 * Set default value. On resume reading the values that were
1046 * zeored can provide debug data on the resume flow.
1047 * This is for debugging only and has no functional impact.
1048 */
1049 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1050
dcab8ecd
EH		 1051 /* configure the ucode to be ready to get the secured image */
1052 /* release CPU reset */
1053 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1054
1055 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1056 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1057 &first_ucode_section);
dcab8ecd
EH		 1058 if (ret)
1059 return ret;
1060
1061 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1062 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1063 &first_ucode_section);
cf614297
EG		 1064}
1065
9ad8fd0b 1066bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1067{
326477e4 1068 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1069 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1070 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1071 bool report;
727c02df 1072
326477e4
JB		 1073 if (hw_rfkill) {
1074 set_bit(STATUS_RFKILL_HW, &trans->status);
1075 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1076 } else {
1077 clear_bit(STATUS_RFKILL_HW, &trans->status);
1078 if (trans_pcie->opmode_down)
1079 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1080 }
1081
1082 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1083
326477e4
JB		 1084 if (prev != report)
1085 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1086
1087 return hw_rfkill;
1088}
1089
7ca00409 1090struct iwl_causes_list {
c1918196
JB		 1091 u16 mask_reg;
1092 u8 bit;
7ca00409
HD		 1093 u8 addr;
1094};
1095
9c683731 1096#define IWL_CAUSE(reg, mask) \
c1918196
JB		 1097 { \
1098 .mask_reg = reg, \
1099 .bit = ilog2(mask), \
1100 .addr = ilog2(mask) + \
1101 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \
1102 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \
1103 0xffff), /* causes overflow warning */ \
1104 }
1105
571836a0 1106static const struct iwl_causes_list causes_list_common[] = {
9c683731
JB		 1107 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM),
1108 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM),
1109 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D),
1110 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR),
1111 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE),
1112 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP),
1113 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE),
1114 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL),
1115 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL),
1116 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC),
1117 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD),
1118 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX),
1119 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR),
1120 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP),
7ca00409
HD		 1121};
1122
571836a0 1123static const struct iwl_causes_list causes_list_pre_bz[] = {
9c683731 1124 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR),
571836a0
MG		 1125};
1126
1127static const struct iwl_causes_list causes_list_bz[] = {
9c683731 1128 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ),
571836a0
MG		 1129};
1130
1131static void iwl_pcie_map_list(struct iwl_trans *trans,
1132 const struct iwl_causes_list *causes,
1133 int arr_size, int val)
1134{
1135 int i;
1136
1137 for (i = 0; i < arr_size; i++) {
1138 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1139 iwl_clear_bit(trans, causes[i].mask_reg,
c1918196 1140 BIT(causes[i].bit));
571836a0
MG		 1141 }
1142}
1143
7ca00409
HD		 1144static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1145{
1146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1147 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
7ca00409
HD		 1148 /*
1149 * Access all non RX causes and map them to the default irq.
1150 * In case we are missing at least one interrupt vector,
1151 * the first interrupt vector will serve non-RX and FBQ causes.
1152 */
571836a0
MG		 1153 iwl_pcie_map_list(trans, causes_list_common,
1154 ARRAY_SIZE(causes_list_common), val);
1155 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1156 iwl_pcie_map_list(trans, causes_list_bz,
1157 ARRAY_SIZE(causes_list_bz), val);
1158 else
1159 iwl_pcie_map_list(trans, causes_list_pre_bz,
1160 ARRAY_SIZE(causes_list_pre_bz), val);
7ca00409
HD		 1161}
1162
1163static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1164{
1165 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1166 u32 offset =
1167 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1168 u32 val, idx;
1169
1170 /*
1171 * The first RX queue - fallback queue, which is designated for
1172 * management frame, command responses etc, is always mapped to the
1173 * first interrupt vector. The other RX queues are mapped to
1174 * the other (N - 2) interrupt vectors.
1175 */
1176 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1177 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1178 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1179 MSIX_FH_INT_CAUSES_Q(idx - offset));
1180 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1181 }
1182 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1183
1184 val = MSIX_FH_INT_CAUSES_Q(0);
1185 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1186 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1187 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1188
1189 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1190 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1191}
1192
77c09bc8 1193void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1194{
1195 struct iwl_trans *trans = trans_pcie->trans;
1196
1197 if (!trans_pcie->msix_enabled) {
286ca8eb 1198 if (trans->trans_cfg->mq_rx_supported &&
d7270d61 1199 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1200 iwl_write_umac_prph(trans, UREG_CHICK,
1201 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1202 return;
1203 }
d7270d61
HD		 1204 /*
1205 * The IVAR table needs to be configured again after reset,
1206 * but if the device is disabled, we can't write to
1207 * prph.
1208 */
1209 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1210 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1211
1212 /*
1213 * Each cause from the causes list above and the RX causes is
1214 * represented as a byte in the IVAR table. The first nibble
1215 * represents the bound interrupt vector of the cause, the second
1216 * represents no auto clear for this cause. This will be set if its
1217 * interrupt vector is bound to serve other causes.
1218 */
1219 iwl_pcie_map_rx_causes(trans);
1220
1221 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1222}
1223
1224static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1225{
1226 struct iwl_trans *trans = trans_pcie->trans;
1227
1228 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1229
83730058
HD		 1230 if (!trans_pcie->msix_enabled)
1231 return;
1232
1233 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1234 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1235 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1236 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1237}
1238
bab3cb92 1239static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1240{
43e58856 1241 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1242
fa9f3281
EG		 1243 lockdep_assert_held(&trans_pcie->mutex);
1244
1245 if (trans_pcie->is_down)
1246 return;
1247
1248 trans_pcie->is_down = true;
1249
43e58856 1250 /* tell the device to stop sending interrupts */
ae2c30bf 1251 iwl_disable_interrupts(trans);
ae2c30bf 1252
ab6cf8e8 1253 /* device going down, Stop using ICT table */
990aa6d7 1254 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1255
1256 /*
1257 * If a HW restart happens during firmware loading,
1258 * then the firmware loading might call this function
1259 * and later it might be called again due to the
1260 * restart. So don't process again if the device is
1261 * already dead.
1262 */
31b8b343 1263 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1264 IWL_DEBUG_INFO(trans,
1265 "DEVICE_ENABLED bit was set and is now cleared\n");
5af2bb31 1266 iwl_pcie_rx_napi_sync(trans);
f02831be 1267 iwl_pcie_tx_stop(trans);
9805c446 1268 iwl_pcie_rx_stop(trans);
6379103e 1269
ab6cf8e8 1270 /* Power-down device's busmaster DMA clocks */
95411d04 1271 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1272 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1273 APMG_CLK_VAL_DMA_CLK_RQT);
1274 udelay(5);
1275 }
ab6cf8e8
EG		 1276 }
1277
1278 /* Make sure (redundant) we've released our request to stay awake */
1b6598c3
RG		 1279 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1280 iwl_clear_bit(trans, CSR_GP_CNTRL,
1281 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1282 else
1283 iwl_clear_bit(trans, CSR_GP_CNTRL,
1284 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1285
1286 /* Stop the device, and put it in low power state */
b7aaeae4 1287 iwl_pcie_apm_stop(trans, false);
43e58856 1288
15bf5ac6
JB		 1289 /* re-take ownership to prevent other users from stealing the device */
1290 iwl_trans_pcie_sw_reset(trans, true);
03d6c3b0 1291
f4a1f04a
GBA		 1292 /*
1293 * Upon stop, the IVAR table gets erased, so msi-x won't
1294 * work. This causes a bug in RF-KILL flows, since the interrupt
1295 * that enables radio won't fire on the correct irq, and the
1296 * driver won't be able to handle the interrupt.
1297 * Configure the IVAR table again after reset.
1298 */
1299 iwl_pcie_conf_msix_hw(trans_pcie);
1300
03d6c3b0
EG		 1301 /*
1302 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1303 * This is a bug in certain verions of the hardware.
1304 * Certain devices also keep sending HW RF kill interrupt all
1305 * the time, unless the interrupt is ACKed even if the interrupt
1306 * should be masked. Re-ACK all the interrupts here.
43e58856 1307 */
43e58856 1308 iwl_disable_interrupts(trans);
43e58856 1309
74fda971 1310 /* clear all status bits */
eb7ff77e
AN		 1311 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1312 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1313 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1314
1315 /*
1316 * Even if we stop the HW, we still want the RF kill
1317 * interrupt
1318 */
1319 iwl_enable_rfkill_int(trans);
14cfca71
JB		 1320}
1321
eda50cde 1322void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1323{
1324 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1325
1326 if (trans_pcie->msix_enabled) {
1327 int i;
1328
496d83ca 1329 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1330 synchronize_irq(trans_pcie->msix_entries[i].vector);
1331 } else {
1332 synchronize_irq(trans_pcie->pci_dev->irq);
1333 }
1334}
1335
a6bd005f
EG		 1336static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1337 const struct fw_img *fw, bool run_in_rfkill)
1338{
1339 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1340 bool hw_rfkill;
1341 int ret;
1342
1343 /* This may fail if AMT took ownership of the device */
1344 if (iwl_pcie_prepare_card_hw(trans)) {
1345 IWL_WARN(trans, "Exit HW not ready\n");
e9848aed 1346 return -EIO;
a6bd005f
EG		 1347 }
1348
1349 iwl_enable_rfkill_int(trans);
1350
1351 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1352
1353 /*
1354 * We enabled the RF-Kill interrupt and the handler may very
1355 * well be running. Disable the interrupts to make sure no other
1356 * interrupt can be fired.
1357 */
1358 iwl_disable_interrupts(trans);
1359
1360 /* Make sure it finished running */
2e5d4a8f 1361 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1362
1363 mutex_lock(&trans_pcie->mutex);
1364
1365 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1366 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1367 if (hw_rfkill && !run_in_rfkill) {
1368 ret = -ERFKILL;
1369 goto out;
1370 }
1371
1372 /* Someone called stop_device, don't try to start_fw */
1373 if (trans_pcie->is_down) {
1374 IWL_WARN(trans,
1375 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1376 ret = -EIO;
a6bd005f
EG		 1377 goto out;
1378 }
1379
1380 /* make sure rfkill handshake bits are cleared */
1381 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1382 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1383 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1384
1385 /* clear (again), then enable host interrupts */
1386 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1387
1388 ret = iwl_pcie_nic_init(trans);
1389 if (ret) {
1390 IWL_ERR(trans, "Unable to init nic\n");
1391 goto out;
1392 }
1393
1394 /*
1395 * Now, we load the firmware and don't want to be interrupted, even
1396 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1397 * FH_TX interrupt which is needed to load the firmware). If the
1398 * RF-Kill switch is toggled, we will find out after having loaded
1399 * the firmware and return the proper value to the caller.
1400 */
1401 iwl_enable_fw_load_int(trans);
1402
1403 /* really make sure rfkill handshake bits are cleared */
1404 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1405 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1406
1407 /* Load the given image to the HW */
286ca8eb 1408 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1409 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1410 else
1411 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1412
1413 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1414 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1415 if (hw_rfkill && !run_in_rfkill)
1416 ret = -ERFKILL;
1417
1418out:
1419 mutex_unlock(&trans_pcie->mutex);
1420 return ret;
1421}
1422
1423static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1424{
1425 iwl_pcie_reset_ict(trans);
1426 iwl_pcie_tx_start(trans, scd_addr);
1427}
1428
326477e4
JB		 1429void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1430 bool was_in_rfkill)
1431{
1432 bool hw_rfkill;
1433
1434 /*
1435 * Check again since the RF kill state may have changed while
1436 * all the interrupts were disabled, in this case we couldn't
1437 * receive the RF kill interrupt and update the state in the
1438 * op_mode.
1439 * Don't call the op_mode if the rkfill state hasn't changed.
1440 * This allows the op_mode to call stop_device from the rfkill
1441 * notification without endless recursion. Under very rare
1442 * circumstances, we might have a small recursion if the rfkill
1443 * state changed exactly now while we were called from stop_device.
1444 * This is very unlikely but can happen and is supported.
1445 */
1446 hw_rfkill = iwl_is_rfkill_set(trans);
1447 if (hw_rfkill) {
1448 set_bit(STATUS_RFKILL_HW, &trans->status);
1449 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1450 } else {
1451 clear_bit(STATUS_RFKILL_HW, &trans->status);
1452 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1453 }
1454 if (hw_rfkill != was_in_rfkill)
1455 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1456}
1457
bab3cb92 1458static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
fa9f3281
EG		 1459{
1460 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1461 bool was_in_rfkill;
fa9f3281 1462
d0129315
MG		 1463 iwl_op_mode_time_point(trans->op_mode,
1464 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1465 NULL);
1466
fa9f3281 1467 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1468 trans_pcie->opmode_down = true;
1469 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
bab3cb92 1470 _iwl_trans_pcie_stop_device(trans);
326477e4 1471 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1472 mutex_unlock(&trans_pcie->mutex);
1473}
1474
14cfca71
JB		 1475void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1476{
fa9f3281
EG		 1477 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1478 IWL_TRANS_GET_PCIE_TRANS(trans);
1479
1480 lockdep_assert_held(&trans_pcie->mutex);
1481
326477e4
JB		 1482 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1483 state ? "disabled" : "enabled");
77c09bc8 1484 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
286ca8eb 1485 if (trans->trans_cfg->gen2)
bab3cb92 1486 _iwl_trans_pcie_gen2_stop_device(trans);
77c09bc8 1487 else
bab3cb92 1488 _iwl_trans_pcie_stop_device(trans);
77c09bc8 1489 }
ab6cf8e8
EG		 1490}
1491
e5f3f215
HD		 1492void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1493 bool test, bool reset)
2dd4f9f7 1494{
2dd4f9f7 1495 iwl_disable_interrupts(trans);
debff618
JB		 1496
1497 /*
1498 * in testing mode, the host stays awake and the
1499 * hardware won't be reset (not even partially)
1500 */
1501 if (test)
1502 return;
1503
ddaf5a5b
JB		 1504 iwl_pcie_disable_ict(trans);
1505
2e5d4a8f 1506 iwl_pcie_synchronize_irqs(trans);
33b56af1 1507
2dd4f9f7 1508 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 1509 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1510 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
ddaf5a5b 1511
23ae6128 1512 if (reset) {
6dfb36c8
EP		 1513 /*
1514 * reset TX queues -- some of their registers reset during S3
1515 * so if we don't reset everything here the D3 image would try
1516 * to execute some invalid memory upon resume
1517 */
1518 iwl_trans_pcie_tx_reset(trans);
1519 }
ddaf5a5b
JB		 1520
1521 iwl_pcie_set_pwr(trans, true);
1522}
1523
af08571d
HD		 1524static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
1525{
1526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1527 int ret;
1528
277f56a1 1529 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
af08571d
HD		 1530 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1531 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
1532 UREG_DOORBELL_TO_ISR6_RESUME);
277f56a1 1533 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
af08571d
HD		 1534 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
1535 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
1536 CSR_IPC_SLEEP_CONTROL_RESUME);
277f56a1 1537 else
af08571d 1538 return 0;
af08571d
HD		 1539
1540 ret = wait_event_timeout(trans_pcie->sx_waitq,
1541 trans_pcie->sx_complete, 2 * HZ);
1542
1543 /* Invalidate it toward next suspend or resume */
1544 trans_pcie->sx_complete = false;
1545
1546 if (!ret) {
1547 IWL_ERR(trans, "Timeout %s D3\n",
1548 suspend ? "entering" : "exiting");
1549 return -ETIMEDOUT;
1550 }
1551
1552 return 0;
1553}
1554
e5f3f215
HD		 1555static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1556 bool reset)
1557{
1558 int ret;
e5f3f215 1559
771db3a1 1560 if (!reset)
e5f3f215
HD		 1561 /* Enable persistence mode to avoid reset */
1562 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1563 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
e5f3f215 1564
af08571d
HD		 1565 ret = iwl_pcie_d3_handshake(trans, true);
1566 if (ret)
1567 return ret;
e5f3f215 1568
e5f3f215
HD		 1569 iwl_pcie_d3_complete_suspend(trans, test, reset);
1570
1571 return 0;
1572}
1573
ddaf5a5b 1574static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1575 enum iwl_d3_status *status,
23ae6128 1576 bool test, bool reset)
ddaf5a5b 1577{
d7270d61 1578 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1579 u32 val;
1580 int ret;
1581
debff618
JB		 1582 if (test) {
1583 iwl_enable_interrupts(trans);
1584 *status = IWL_D3_STATUS_ALIVE;
af08571d 1585 ret = 0;
e5f3f215 1586 goto out;
debff618
JB		 1587 }
1588
a8cbb46f 1589 iwl_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 1590 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b 1591
425d66d8 1592 ret = iwl_finish_nic_init(trans);
c96b5eec 1593 if (ret)
ddaf5a5b 1594 return ret;
ddaf5a5b 1595
f98ad635
EG		 1596 /*
1597 * Reconfigure IVAR table in case of MSIX or reset ict table in
1598 * MSI mode since HW reset erased it.
1599 * Also enables interrupts - none will happen as
1600 * the device doesn't know we're waking it up, only when
1601 * the opmode actually tells it after this call.
1602 */
1603 iwl_pcie_conf_msix_hw(trans_pcie);
1604 if (!trans_pcie->msix_enabled)
1605 iwl_pcie_reset_ict(trans);
1606 iwl_enable_interrupts(trans);
1607
a3ead656
EG		 1608 iwl_pcie_set_pwr(trans, false);
1609
23ae6128 1610 if (!reset) {
6dfb36c8 1611 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1612 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6dfb36c8
EP		 1613 } else {
1614 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1615
6dfb36c8
EP		 1616 ret = iwl_pcie_rx_init(trans);
1617 if (ret) {
1618 IWL_ERR(trans,
1619 "Failed to resume the device (RX reset)\n");
1620 return ret;
1621 }
ddaf5a5b
JB		 1622 }
1623
82ea7966 1624 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1625 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1626
a3ead656
EG		 1627 val = iwl_read32(trans, CSR_RESET);
1628 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1629 *status = IWL_D3_STATUS_RESET;
1630 else
1631 *status = IWL_D3_STATUS_ALIVE;
1632
e5f3f215 1633out:
af08571d
HD		 1634 if (*status == IWL_D3_STATUS_ALIVE)
1635 ret = iwl_pcie_d3_handshake(trans, false);
e5f3f215 1636
af08571d 1637 return ret;
2dd4f9f7
JB		 1638}
1639
0c18714a
LC		 1640static void
1641iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1642 struct iwl_trans *trans,
1643 const struct iwl_cfg_trans_params *cfg_trans)
2e5d4a8f
HD		 1644{
1645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1646 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1647 u16 pci_cmd;
0cd38f4d 1648 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
2e5d4a8f 1649
0c18714a 1650 if (!cfg_trans->mq_rx_supported)
06f4b081
SS		 1651 goto enable_msi;
1652
0cd38f4d
MG		 1653 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1654 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1655
1656 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
06f4b081
SS		 1657 for (i = 0; i < max_irqs; i++)
1658 trans_pcie->msix_entries[i].entry = i;
496d83ca 1659
06f4b081
SS		 1660 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1661 MSIX_MIN_INTERRUPT_VECTORS,
1662 max_irqs);
1663 if (num_irqs < 0) {
2e5d4a8f 1664 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1665 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1666 num_irqs);
1667 goto enable_msi;
1668 }
1669 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1670
06f4b081
SS		 1671 IWL_DEBUG_INFO(trans,
1672 "MSI-X enabled. %d interrupt vectors were allocated\n",
1673 num_irqs);
1674
1675 /*
1676 * In case the OS provides fewer interrupts than requested, different
1677 * causes will share the same interrupt vector as follows:
1678 * One interrupt less: non rx causes shared with FBQ.
1679 * Two interrupts less: non rx causes shared with FBQ and RSS.
1680 * More than two interrupts: we will use fewer RSS queues.
1681 */
ab1068d6 1682 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1683 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1684 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1685 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1686 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1687 trans_pcie->trans->num_rx_queues = num_irqs;
1688 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1689 } else {
1690 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1691 }
9d401222
MG		 1692
1693 IWL_DEBUG_INFO(trans,
1694 "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1695 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1696
ab1068d6 1697 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1698
06f4b081
SS		 1699 trans_pcie->alloc_vecs = num_irqs;
1700 trans_pcie->msix_enabled = true;
1701 return;
1702
1703enable_msi:
1704 ret = pci_enable_msi(pdev);
1705 if (ret) {
1706 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1707 /* enable rfkill interrupt: hw bug w/a */
1708 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1709 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1710 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1711 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1712 }
1713 }
1714}
1715
7c8d91eb
HD		 1716static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1717{
1718 int iter_rx_q, i, ret, cpu, offset;
1719 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1720
1721 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1722 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1723 offset = 1 + i;
1724 for (; i < iter_rx_q ; i++) {
1725 /*
1726 * Get the cpu prior to the place to search
1727 * (i.e. return will be > i - 1).
1728 */
1729 cpu = cpumask_next(i - offset, cpu_online_mask);
1730 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1731 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1732 &trans_pcie->affinity_mask[i]);
1733 if (ret)
1734 IWL_ERR(trans_pcie->trans,
1735 "Failed to set affinity mask for IRQ %d\n",
57e6492c 1736 trans_pcie->msix_entries[i].vector);
7c8d91eb
HD		 1737 }
1738}
1739
2e5d4a8f
HD		 1740static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1741 struct iwl_trans_pcie *trans_pcie)
1742{
496d83ca 1743 int i;
2e5d4a8f 1744
496d83ca 1745 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1746 int ret;
5a41a86c 1747 struct msix_entry *msix_entry;
64fa3aff
SD		 1748 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1749
1750 if (!qname)
1751 return -ENOMEM;
5a41a86c
SD		 1752
1753 msix_entry = &trans_pcie->msix_entries[i];
1754 ret = devm_request_threaded_irq(&pdev->dev,
1755 msix_entry->vector,
1756 iwl_pcie_msix_isr,
1757 (i == trans_pcie->def_irq) ?
1758 iwl_pcie_irq_msix_handler :
1759 iwl_pcie_irq_rx_msix_handler,
1760 IRQF_SHARED,
64fa3aff 1761 qname,
5a41a86c 1762 msix_entry);
2e5d4a8f 1763 if (ret) {
2e5d4a8f
HD		 1764 IWL_ERR(trans_pcie->trans,
1765 "Error allocating IRQ %d\n", i);
5a41a86c 1766
2e5d4a8f
HD		 1767 return ret;
1768 }
1769 }
7c8d91eb 1770 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1771
1772 return 0;
1773}
1774
44f61b5c 1775static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
e6bb4c9c 1776{
44f61b5c 1777 u32 hpm, wprot;
fa9f3281 1778
286ca8eb 1779 switch (trans->trans_cfg->device_family) {
44f61b5c
SM		 1780 case IWL_DEVICE_FAMILY_9000:
1781 wprot = PREG_PRPH_WPROT_9000;
1782 break;
1783 case IWL_DEVICE_FAMILY_22000:
1784 wprot = PREG_PRPH_WPROT_22000;
1785 break;
1786 default:
1787 return 0;
ebb7678d 1788 }
a6c684ee 1789
ea695b7c 1790 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
d4f1a50c 1791 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
44f61b5c 1792 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
ea695b7c 1793
44f61b5c 1794 if (wprot_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1795 IWL_ERR(trans,
1796 "Error, can not clear persistence bit\n");
1797 return -EPERM;
1798 }
ea695b7c
ST		 1799 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1800 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1801 }
1802
44f61b5c
SM		 1803 return 0;
1804}
1805
0df36b90
LC		 1806static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1807{
1808 int ret;
1809
425d66d8 1810 ret = iwl_finish_nic_init(trans);
0df36b90
LC		 1811 if (ret < 0)
1812 return ret;
1813
1814 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1815 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1816 udelay(20);
1817 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1818 HPM_HIPM_GEN_CFG_CR_PG_EN |
1819 HPM_HIPM_GEN_CFG_CR_SLP_EN);
1820 udelay(20);
1821 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1822 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1823
15bf5ac6 1824 return iwl_trans_pcie_sw_reset(trans, true);
0df36b90
LC		 1825}
1826
bab3cb92 1827static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
44f61b5c
SM		 1828{
1829 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1830 int err;
1831
1832 lockdep_assert_held(&trans_pcie->mutex);
1833
1834 err = iwl_pcie_prepare_card_hw(trans);
1835 if (err) {
1836 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1837 return err;
1838 }
1839
1840 err = iwl_trans_pcie_clear_persistence_bit(trans);
1841 if (err)
1842 return err;
1843
15bf5ac6
JB		 1844 err = iwl_trans_pcie_sw_reset(trans, true);
1845 if (err)
1846 return err;
2997494f 1847
0df36b90 1848 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
7897dfa2 1849 trans->trans_cfg->integrated) {
0df36b90
LC		 1850 err = iwl_pcie_gen2_force_power_gating(trans);
1851 if (err)
1852 return err;
1853 }
1854
52b6e168
EG		 1855 err = iwl_pcie_apm_init(trans);
1856 if (err)
1857 return err;
a6c684ee 1858
2e5d4a8f 1859 iwl_pcie_init_msix(trans_pcie);
83730058 1860
226c02ca
EG		 1861 /* From now on, the op_mode will be kept updated about RF kill state */
1862 iwl_enable_rfkill_int(trans);
1863
326477e4
JB		 1864 trans_pcie->opmode_down = false;
1865
fa9f3281
EG		 1866 /* Set is_down to false here so that...*/
1867 trans_pcie->is_down = false;
1868
727c02df 1869 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1870 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1871
a8b691e6 1872 return 0;
e6bb4c9c
EG		 1873}
1874
bab3cb92 1875static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
fa9f3281
EG		 1876{
1877 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1878 int ret;
1879
1880 mutex_lock(&trans_pcie->mutex);
bab3cb92 1881 ret = _iwl_trans_pcie_start_hw(trans);
fa9f3281
EG		 1882 mutex_unlock(&trans_pcie->mutex);
1883
1884 return ret;
1885}
1886
a4082843 1887static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1888{
20d3b647 1889 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1890
fa9f3281
EG		 1891 mutex_lock(&trans_pcie->mutex);
1892
a4082843 1893 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1894 iwl_disable_interrupts(trans);
ee7d737c 1895
b7aaeae4 1896 iwl_pcie_apm_stop(trans, true);
cc56feb2 1897
218733cf 1898 iwl_disable_interrupts(trans);
1df06bdc 1899
8d96bb61 1900 iwl_pcie_disable_ict(trans);
33b56af1 1901
fa9f3281 1902 mutex_unlock(&trans_pcie->mutex);
33b56af1 1903
2e5d4a8f 1904 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1905}
1906
03905495
EG		 1907static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1908{
05f5b97e 1909 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1910}
1911
1912static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1913{
05f5b97e 1914 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1915}
1916
1917static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1918{
05f5b97e 1919 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1920}
1921
84fb372c
SS		 1922static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1923{
3681021f 1924 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
84fb372c
SS		 1925 return 0x00FFFFFF;
1926 else
1927 return 0x000FFFFF;
1928}
1929
6a06b6c1
EG		 1930static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1931{
84fb372c
SS		 1932 u32 mask = iwl_trans_pcie_prph_msk(trans);
1933
f9477c17 1934 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1935 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1936 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1937}
1938
1939static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1940 u32 val)
1941{
84fb372c
SS		 1942 u32 mask = iwl_trans_pcie_prph_msk(trans);
1943
6a06b6c1 1944 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1945 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1946 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1947}
1948
c6f600fc 1949static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1950 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1951{
1952 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1953
6ac57200
JB		 1954 /* free all first - we might be reconfigured for a different size */
1955 iwl_pcie_free_rbs_pool(trans);
1956
4f4822b7
MG		 1957 trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1958 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1959 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
22852fad
MG		 1960 trans->txqs.page_offs = trans_cfg->cb_data_offs;
1961 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
227f2597 1962 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver;
22852fad 1963
d663ee73
JB		 1964 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1965 trans_pcie->n_no_reclaim_cmds = 0;
1966 else
1967 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1968 if (trans_pcie->n_no_reclaim_cmds)
1969 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1970 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1971
6c4fbcbc
EG		 1972 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1973 trans_pcie->rx_page_order =
1974 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
80084e35
JB		 1975 trans_pcie->rx_buf_bytes =
1976 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
cfdc20ef
JB		 1977 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1978 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1979 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
7c5ba4a8 1980
8e3b79f8 1981 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1982 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1983
39bdb17e
SD		 1984 trans->command_groups = trans_cfg->command_groups;
1985 trans->command_groups_size = trans_cfg->command_groups_size;
1986
f14d6b39
JB		 1987 /* Initialize NAPI here - it should be before registering to mac80211
1988 * in the opmode but after the HW struct is allocated.
1989 * As this function may be called again in some corner cases don't
1990 * do anything if NAPI was already initialized.
1991 */
bce97731 1992 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1993 init_dummy_netdev(&trans_pcie->napi_dev);
906d4eb8
JB		 1994
1995 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
c6f600fc
MV		 1996}
1997
7c9c8477
AG		 1998void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
1999 struct device *dev)
f6fa5835
AG		 2000{
2001 u8 i;
7c9c8477 2002 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
f6fa5835 2003
7c9c8477
AG		 2004 /* free DRAM payloads */
2005 for (i = 0; i < dram_regions->n_regions; i++) {
2006 dma_free_coherent(dev, dram_regions->drams[i].size,
2007 dram_regions->drams[i].block,
2008 dram_regions->drams[i].physical);
f6fa5835 2009 }
7c9c8477 2010 dram_regions->n_regions = 0;
63b9e7b9 2011
7c9c8477 2012 /* free DRAM addresses array */
63b9e7b9
AG		 2013 if (desc_dram->block) {
2014 dma_free_coherent(dev, desc_dram->size,
2015 desc_dram->block,
2016 desc_dram->physical);
2017 }
7c9c8477 2018 memset(desc_dram, 0, sizeof(*desc_dram));
f6fa5835
AG		 2019}
2020
c83031af
JB		 2021static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans)
2022{
2023 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd);
2024}
2025
2026static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans)
2027{
2028 struct iwl_cmd_header_wide bad_cmd = {
2029 .cmd = INVALID_WR_PTR_CMD,
2030 .group_id = DEBUG_GROUP,
2031 .sequence = cpu_to_le16(0xffff),
2032 .length = cpu_to_le16(0),
2033 .version = 0,
2034 };
2035 int ret;
2036
2037 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd,
2038 sizeof(bad_cmd));
2039 if (ret)
2040 return ret;
2041 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd));
2042 return 0;
2043}
2044
d1ff5253 2045void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 2046{
20d3b647 2047 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 2048 int i;
a42a1844 2049
2e5d4a8f 2050 iwl_pcie_synchronize_irqs(trans);
0aa86df6 2051
286ca8eb 2052 if (trans->trans_cfg->gen2)
0cd1ad2d 2053 iwl_txq_gen2_tx_free(trans);
13a3a390
SS		 2054 else
2055 iwl_pcie_tx_free(trans);
9805c446 2056 iwl_pcie_rx_free(trans);
6379103e 2057
10a54d81
LC		 2058 if (trans_pcie->rba.alloc_wq) {
2059 destroy_workqueue(trans_pcie->rba.alloc_wq);
2060 trans_pcie->rba.alloc_wq = NULL;
2061 }
2062
2e5d4a8f 2063 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 2064 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2065 irq_set_affinity_hint(
2066 trans_pcie->msix_entries[i].vector,
2067 NULL);
7c8d91eb 2068 }
2e5d4a8f 2069
2e5d4a8f
HD		 2070 trans_pcie->msix_enabled = false;
2071 } else {
2e5d4a8f 2072 iwl_pcie_free_ict(trans);
2e5d4a8f 2073 }
a42a1844 2074
c83031af
JB		 2075 iwl_pcie_free_invalid_tx_cmd(trans);
2076
c2d20201
EG		 2077 iwl_pcie_free_fw_monitor(trans);
2078
7c9c8477
AG		 2079 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,
2080 trans->dev);
2081 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,
2082 trans->dev);
9dad325f 2083
a2a57a35 2084 mutex_destroy(&trans_pcie->mutex);
7b501d10 2085 iwl_trans_free(trans);
34c1b7ba
EG		 2086}
2087
47107e84
DF		 2088static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2089{
47107e84 2090 if (state)
eb7ff77e 2091 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 2092 else
eb7ff77e 2093 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 2094}
2095
49564a80
LC		 2096struct iwl_trans_pcie_removal {
2097 struct pci_dev *pdev;
2098 struct work_struct work;
b8133439 2099 bool rescan;
49564a80
LC		 2100};
2101
2102static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2103{
2104 struct iwl_trans_pcie_removal *removal =
2105 container_of(wk, struct iwl_trans_pcie_removal, work);
2106 struct pci_dev *pdev = removal->pdev;
aba1e632 2107 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
b8133439 2108 struct pci_bus *bus = pdev->bus;
49564a80
LC		 2109
2110 dev_err(&pdev->dev, "Device gone - attempting removal\n");
2111 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2112 pci_lock_rescan_remove();
2113 pci_dev_put(pdev);
2114 pci_stop_and_remove_bus_device(pdev);
b8133439
AS		 2115 if (removal->rescan)
2116 pci_rescan_bus(bus->parent);
49564a80
LC		 2117 pci_unlock_rescan_remove();
2118
2119 kfree(removal);
2120 module_put(THIS_MODULE);
2121}
2122
b8133439
AS		 2123void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan)
2124{
2125 struct iwl_trans_pcie_removal *removal;
2126
2127 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2128 return;
2129
2130 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2131
2132 /*
2133 * get a module reference to avoid doing this
2134 * while unloading anyway and to avoid
2135 * scheduling a work with code that's being
2136 * removed.
2137 */
2138 if (!try_module_get(THIS_MODULE)) {
2139 IWL_ERR(trans,
2140 "Module is being unloaded - abort\n");
2141 return;
2142 }
2143
2144 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2145 if (!removal) {
2146 module_put(THIS_MODULE);
2147 return;
2148 }
2149 /*
2150 * we don't need to clear this flag, because
2151 * the trans will be freed and reallocated.
2152 */
2153 set_bit(STATUS_TRANS_DEAD, &trans->status);
2154
2155 removal->pdev = to_pci_dev(trans->dev);
2156 removal->rescan = rescan;
2157 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2158 pci_dev_get(removal->pdev);
2159 schedule_work(&removal->work);
2160}
2161EXPORT_SYMBOL(iwl_trans_pcie_remove);
2162
c544d89b
JB		 2163/*
2164 * This version doesn't disable BHs but rather assumes they're
2165 * already disabled.
2166 */
2167bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
7a65d170
EG		 2168{
2169 int ret;
cfb4e624 2170 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9ce041f5
JB		 2171 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2172 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2173 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2174 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
cfb4e624 2175
c544d89b 2176 spin_lock(&trans_pcie->reg_lock);
7a65d170 2177
fc8a350d 2178 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2179 goto out;
2180
9ce041f5
JB		 2181 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2182 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2183 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2184 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2185 }
2186
7a65d170 2187 /* this bit wakes up the NIC */
9ce041f5 2188 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
286ca8eb 2189 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 2190 udelay(2);
7a65d170
EG		 2191
2192 /*
2193 * These bits say the device is running, and should keep running for
2194 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2195 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 2196 * HW with volatile SRAM must save/restore contents to/from
2197 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 2198 * Each direction takes approximately 1/4 millisecond; with this
2199 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2200 * series of register accesses are expected (e.g. reading Event Log),
2201 * to keep device from sleeping.
2202 *
2203 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2204 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 2205 * is just for hardware register access; but GP1 MAC_SLEEP
2206 * check is a good idea before accessing the SRAM of HW with
2207 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2208 *
2209 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2210 * and do not save/restore SRAM when power cycling.
2211 */
9ce041f5 2212 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
7a65d170 2213 if (unlikely(ret < 0)) {
49564a80
LC		 2214 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2215
23ba9340
EG		 2216 WARN_ONCE(1,
2217 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2218 cntrl);
2219
2220 iwl_trans_pcie_dump_regs(trans);
2221
b8133439
AS		 2222 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U)
2223 iwl_trans_pcie_remove(trans, false);
2224 else
49564a80
LC		 2225 iwl_write32(trans, CSR_RESET,
2226 CSR_RESET_REG_FLAG_FORCE_NMI);
49564a80 2227
c544d89b 2228 spin_unlock(&trans_pcie->reg_lock);
23ba9340 2229 return false;
7a65d170
EG		 2230 }
2231
b9439491 2232out:
e56b04ef
LE		 2233 /*
2234 * Fool sparse by faking we release the lock - sparse will
2235 * track nic_access anyway.
2236 */
cfb4e624 2237 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2238 return true;
2239}
2240
c544d89b
JB		 2241static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2242{
2243 bool ret;
2244
2245 local_bh_disable();
2246 ret = __iwl_trans_pcie_grab_nic_access(trans);
2247 if (ret) {
2248 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2249 return ret;
2250 }
2251 local_bh_enable();
2252 return false;
2253}
2254
1ed08f6f 2255static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
7a65d170 2256{
cfb4e624 2257 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2258
cfb4e624 2259 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2260
2261 /*
2262 * Fool sparse by faking we acquiring the lock - sparse will
2263 * track nic_access anyway.
2264 */
cfb4e624 2265 __acquire(&trans_pcie->reg_lock);
e56b04ef 2266
fc8a350d 2267 if (trans_pcie->cmd_hold_nic_awake)
b9439491 2268 goto out;
1b6598c3
RG		 2269 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2270 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2271 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
2272 else
2273 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2274 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2275 /*
2276 * Above we read the CSR_GP_CNTRL register, which will flush
2277 * any previous writes, but we need the write that clears the
2278 * MAC_ACCESS_REQ bit to be performed before any other writes
2279 * scheduled on different CPUs (after we drop reg_lock).
2280 */
b9439491 2281out:
874020f8 2282 spin_unlock_bh(&trans_pcie->reg_lock);
7a65d170
EG		 2283}
2284
4fd442db
EG		 2285static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2286 void *buf, int dwords)
2287{
04516706 2288 int offs = 0;
4fd442db
EG		 2289 u32 *vals = buf;
2290
04516706
JB		 2291 while (offs < dwords) {
2292 /* limit the time we spin here under lock to 1/2s */
67013174 2293 unsigned long end = jiffies + HZ / 2;
3d372c4e 2294 bool resched = false;
04516706 2295
1ed08f6f 2296 if (iwl_trans_grab_nic_access(trans)) {
04516706
JB		 2297 iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2298 addr + 4 * offs);
2299
2300 while (offs < dwords) {
2301 vals[offs] = iwl_read32(trans,
2302 HBUS_TARG_MEM_RDAT);
2303 offs++;
2304
3d372c4e
JB		 2305 if (time_after(jiffies, end)) {
2306 resched = true;
04516706 2307 break;
3d372c4e 2308 }
04516706 2309 }
1ed08f6f 2310 iwl_trans_release_nic_access(trans);
3d372c4e
JB		 2311
2312 if (resched)
2313 cond_resched();
04516706
JB		 2314 } else {
2315 return -EBUSY;
2316 }
4fd442db 2317 }
04516706
JB		 2318
2319 return 0;
4fd442db
EG		 2320}
2321
2322static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2323 const void *buf, int dwords)
4fd442db 2324{
4fd442db 2325 int offs, ret = 0;
bf0fd5da 2326 const u32 *vals = buf;
4fd442db 2327
1ed08f6f 2328 if (iwl_trans_grab_nic_access(trans)) {
4fd442db
EG		 2329 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2330 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2331 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2332 vals ? vals[offs] : 0);
1ed08f6f 2333 iwl_trans_release_nic_access(trans);
4fd442db
EG		 2334 } else {
2335 ret = -EBUSY;
2336 }
4fd442db
EG		 2337 return ret;
2338}
7a65d170 2339
7f1fe1d4
LC		 2340static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2341 u32 *val)
2342{
2343 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2344 ofs, val);
2345}
2346
0cd58eaa
EG		 2347static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2348{
0cd58eaa
EG		 2349 int i;
2350
286ca8eb 2351 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
4f4822b7 2352 struct iwl_txq *txq = trans->txqs.txq[i];
0cd58eaa 2353
4f4822b7 2354 if (i == trans->txqs.cmd.q_id)
0cd58eaa
EG		 2355 continue;
2356
2357 spin_lock_bh(&txq->lock);
2358
2359 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2360 txq->block--;
2361 if (!txq->block) {
2362 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2363 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2364 }
2365 } else if (block) {
2366 txq->block++;
2367 }
2368
2369 spin_unlock_bh(&txq->lock);
2370 }
2371}
2372
5f178cd2
EG		 2373#define IWL_FLUSH_WAIT_MS 2000
2374
92536c96
SS		 2375static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2376 struct iwl_trans_rxq_dma_data *data)
2377{
2378 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2379
2380 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2381 return -EINVAL;
2382
2383 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2384 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2385 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2386 data->fr_bd_wid = 0;
2387
2388 return 0;
2389}
2390
d6d517b7 2391static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2392{
990aa6d7 2393 struct iwl_txq *txq;
5f178cd2 2394 unsigned long now = jiffies;
2ae48edc 2395 bool overflow_tx;
d6d517b7
SS		 2396 u8 wr_ptr;
2397
2b3fae66 2398 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2399 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2400 return -ENODEV;
2b3fae66 2401
4f4822b7 2402 if (!test_bit(txq_idx, trans->txqs.queue_used))
d6d517b7
SS		 2403 return -EINVAL;
2404
2405 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
4f4822b7 2406 txq = trans->txqs.txq[txq_idx];
2ae48edc
SS		 2407
2408 spin_lock_bh(&txq->lock);
2409 overflow_tx = txq->overflow_tx ||
2410 !skb_queue_empty(&txq->overflow_q);
2411 spin_unlock_bh(&txq->lock);
2412
6aa7de05 2413 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2414
2ae48edc
SS		 2415 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2416 overflow_tx) &&
d6d517b7
SS		 2417 !time_after(jiffies,
2418 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2419 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2420
2ae48edc
SS		 2421 /*
2422 * If write pointer moved during the wait, warn only
2423 * if the TX came from op mode. In case TX came from
2424 * trans layer (overflow TX) don't warn.
2425 */
2426 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2427 "WR pointer moved while flushing %d -> %d\n",
2428 wr_ptr, write_ptr))
2429 return -ETIMEDOUT;
2ae48edc
SS		 2430 wr_ptr = write_ptr;
2431
d6d517b7 2432 usleep_range(1000, 2000);
2ae48edc
SS		 2433
2434 spin_lock_bh(&txq->lock);
2435 overflow_tx = txq->overflow_tx ||
2436 !skb_queue_empty(&txq->overflow_q);
2437 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2438 }
2439
2440 if (txq->read_ptr != txq->write_ptr) {
2441 IWL_ERR(trans,
2442 "fail to flush all tx fifo queues Q %d\n", txq_idx);
0cd1ad2d 2443 iwl_txq_log_scd_error(trans, txq);
d6d517b7
SS		 2444 return -ETIMEDOUT;
2445 }
2446
2447 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2448
2449 return 0;
2450}
2451
2452static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2453{
d6d517b7 2454 int cnt;
5f178cd2
EG		 2455 int ret = 0;
2456
2457 /* waiting for all the tx frames complete might take a while */
79b6c8fe 2458 for (cnt = 0;
286ca8eb 2459 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2460 cnt++) {
fa1a91fd 2461
4f4822b7 2462 if (cnt == trans->txqs.cmd.q_id)
5f178cd2 2463 continue;
4f4822b7 2464 if (!test_bit(cnt, trans->txqs.queue_used))
3cafdbe6
EG		 2465 continue;
2466 if (!(BIT(cnt) & txq_bm))
2467 continue;
748fa67c 2468
d6d517b7
SS		 2469 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2470 if (ret)
5f178cd2 2471 break;
5f178cd2 2472 }
1c3fea82 2473
5f178cd2
EG		 2474 return ret;
2475}
2476
e139dc4a
LE		 2477static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2478 u32 mask, u32 value)
2479{
e56b04ef 2480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a 2481
874020f8 2482 spin_lock_bh(&trans_pcie->reg_lock);
e139dc4a 2483 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
874020f8 2484 spin_unlock_bh(&trans_pcie->reg_lock);
e139dc4a
LE		 2485}
2486
ff620849
EG		 2487static const char *get_csr_string(int cmd)
2488{
d9fb6465 2489#define IWL_CMD(x) case x: return #x
ff620849
EG		 2490 switch (cmd) {
2491 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2492 IWL_CMD(CSR_INT_COALESCING);
2493 IWL_CMD(CSR_INT);
2494 IWL_CMD(CSR_INT_MASK);
2495 IWL_CMD(CSR_FH_INT_STATUS);
2496 IWL_CMD(CSR_GPIO_IN);
2497 IWL_CMD(CSR_RESET);
2498 IWL_CMD(CSR_GP_CNTRL);
2499 IWL_CMD(CSR_HW_REV);
2500 IWL_CMD(CSR_EEPROM_REG);
2501 IWL_CMD(CSR_EEPROM_GP);
2502 IWL_CMD(CSR_OTP_GP_REG);
2503 IWL_CMD(CSR_GIO_REG);
2504 IWL_CMD(CSR_GP_UCODE_REG);
2505 IWL_CMD(CSR_GP_DRIVER_REG);
2506 IWL_CMD(CSR_UCODE_DRV_GP1);
2507 IWL_CMD(CSR_UCODE_DRV_GP2);
2508 IWL_CMD(CSR_LED_REG);
2509 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2510 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2511 IWL_CMD(CSR_ANA_PLL_CFG);
2512 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2513 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2514 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2515 default:
2516 return "UNKNOWN";
2517 }
d9fb6465 2518#undef IWL_CMD
ff620849
EG		 2519}
2520
990aa6d7 2521void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2522{
2523 int i;
2524 static const u32 csr_tbl[] = {
2525 CSR_HW_IF_CONFIG_REG,
2526 CSR_INT_COALESCING,
2527 CSR_INT,
2528 CSR_INT_MASK,
2529 CSR_FH_INT_STATUS,
2530 CSR_GPIO_IN,
2531 CSR_RESET,
2532 CSR_GP_CNTRL,
2533 CSR_HW_REV,
2534 CSR_EEPROM_REG,
2535 CSR_EEPROM_GP,
2536 CSR_OTP_GP_REG,
2537 CSR_GIO_REG,
2538 CSR_GP_UCODE_REG,
2539 CSR_GP_DRIVER_REG,
2540 CSR_UCODE_DRV_GP1,
2541 CSR_UCODE_DRV_GP2,
2542 CSR_LED_REG,
2543 CSR_DRAM_INT_TBL_REG,
2544 CSR_GIO_CHICKEN_BITS,
2545 CSR_ANA_PLL_CFG,
a812cba9 2546 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2547 CSR_HW_REV_WA_REG,
2548 CSR_DBG_HPET_MEM_REG
2549 };
2550 IWL_ERR(trans, "CSR values:\n");
2551 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2552 "CSR_INT_PERIODIC_REG)\n");
2553 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2554 IWL_ERR(trans, " %25s: 0X%08x\n",
2555 get_csr_string(csr_tbl[i]),
1042db2a 2556 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2557 }
2558}
2559
87e5666c
EG		 2560#ifdef CONFIG_IWLWIFI_DEBUGFS
2561/* create and remove of files */
2562#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
cf5d5663
GKH		 2563 debugfs_create_file(#name, mode, parent, trans, \
2564 &iwl_dbgfs_##name##_ops); \
87e5666c
EG		 2565} while (0)
2566
2567/* file operation */
87e5666c 2568#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2569static const struct file_operations iwl_dbgfs_##name##_ops = { \
2570 .read = iwl_dbgfs_##name##_read, \
234e3405 2571 .open = simple_open, \
87e5666c
EG		 2572 .llseek = generic_file_llseek, \
2573};
2574
16db88ba 2575#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2576static const struct file_operations iwl_dbgfs_##name##_ops = { \
2577 .write = iwl_dbgfs_##name##_write, \
234e3405 2578 .open = simple_open, \
16db88ba
EG		 2579 .llseek = generic_file_llseek, \
2580};
2581
87e5666c 2582#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2583static const struct file_operations iwl_dbgfs_##name##_ops = { \
2584 .write = iwl_dbgfs_##name##_write, \
2585 .read = iwl_dbgfs_##name##_read, \
234e3405 2586 .open = simple_open, \
87e5666c
EG		 2587 .llseek = generic_file_llseek, \
2588};
2589
df67a1be
JB		 2590struct iwl_dbgfs_tx_queue_priv {
2591 struct iwl_trans *trans;
2592};
2593
2594struct iwl_dbgfs_tx_queue_state {
2595 loff_t pos;
2596};
2597
2598static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
8ad71bef 2599{
df67a1be
JB		 2600 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2601 struct iwl_dbgfs_tx_queue_state *state;
2602
2603 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2604 return NULL;
2605
2606 state = kmalloc(sizeof(*state), GFP_KERNEL);
2607 if (!state)
2608 return NULL;
2609 state->pos = *pos;
2610 return state;
2611}
2612
2613static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2614 void *v, loff_t *pos)
2615{
2616 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2617 struct iwl_dbgfs_tx_queue_state *state = v;
2618
2619 *pos = ++state->pos;
2620
2621 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2622 return NULL;
2623
2624 return state;
2625}
2626
2627static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2628{
2629 kfree(v);
2630}
2631
2632static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2633{
2634 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2635 struct iwl_dbgfs_tx_queue_state *state = v;
2636 struct iwl_trans *trans = priv->trans;
4f4822b7 2637 struct iwl_txq *txq = trans->txqs.txq[state->pos];
df67a1be
JB		 2638
2639 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2640 (unsigned int)state->pos,
4f4822b7
MG		 2641 !!test_bit(state->pos, trans->txqs.queue_used),
2642 !!test_bit(state->pos, trans->txqs.queue_stopped));
df67a1be
JB		 2643 if (txq)
2644 seq_printf(seq,
95a9e44f 2645 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
df67a1be 2646 txq->read_ptr, txq->write_ptr,
95a9e44f
JB		 2647 txq->need_update, txq->frozen,
2648 txq->n_window, txq->ampdu);
df67a1be
JB		 2649 else
2650 seq_puts(seq, "(unallocated)");
1745e440 2651
4f4822b7 2652 if (state->pos == trans->txqs.cmd.q_id)
df67a1be
JB		 2653 seq_puts(seq, " (HCMD)");
2654 seq_puts(seq, "\n");
87e5666c 2655
df67a1be
JB		 2656 return 0;
2657}
f9e75447 2658
df67a1be
JB		 2659static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2660 .start = iwl_dbgfs_tx_queue_seq_start,
2661 .next = iwl_dbgfs_tx_queue_seq_next,
2662 .stop = iwl_dbgfs_tx_queue_seq_stop,
2663 .show = iwl_dbgfs_tx_queue_seq_show,
2664};
2665
2666static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2667{
2668 struct iwl_dbgfs_tx_queue_priv *priv;
2669
2670 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2671 sizeof(*priv));
2672
2673 if (!priv)
87e5666c
EG		 2674 return -ENOMEM;
2675
df67a1be
JB		 2676 priv->trans = inode->i_private;
2677 return 0;
87e5666c
EG		 2678}
2679
2680static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2681 char __user *user_buf,
2682 size_t count, loff_t *ppos)
2683{
5a878bf6 2684 struct iwl_trans *trans = file->private_data;
20d3b647 2685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2686 char *buf;
2687 int pos = 0, i, ret;
eb3dc36e 2688 size_t bufsz;
78485054
SS		 2689
2690 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2691
2692 if (!trans_pcie->rxq)
2693 return -EAGAIN;
2694
2695 buf = kzalloc(bufsz, GFP_KERNEL);
2696 if (!buf)
2697 return -ENOMEM;
2698
2699 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2700 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2701
2702 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2703 i);
2704 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2705 rxq->read);
2706 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2707 rxq->write);
2708 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2709 rxq->write_actual);
2710 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2711 rxq->need_update);
2712 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2713 rxq->free_count);
2714 if (rxq->rb_stts) {
0307c839
GBA		 2715 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2716 rxq));
78485054
SS		 2717 pos += scnprintf(buf + pos, bufsz - pos,
2718 "\tclosed_rb_num: %u\n",
0307c839 2719 r & 0x0FFF);
78485054
SS		 2720 } else {
2721 pos += scnprintf(buf + pos, bufsz - pos,
2722 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2723 }
87e5666c 2724 }
78485054
SS		 2725 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2726 kfree(buf);
2727
2728 return ret;
87e5666c
EG		 2729}
2730
1f7b6172
EG		 2731static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2732 char __user *user_buf,
20d3b647
JB		 2733 size_t count, loff_t *ppos)
2734{
1f7b6172 2735 struct iwl_trans *trans = file->private_data;
20d3b647 2736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2737 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2738
2739 int pos = 0;
2740 char *buf;
2741 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2742 ssize_t ret;
2743
2744 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2745 if (!buf)
1f7b6172 2746 return -ENOMEM;
1f7b6172
EG		 2747
2748 pos += scnprintf(buf + pos, bufsz - pos,
2749 "Interrupt Statistics Report:\n");
2750
2751 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2752 isr_stats->hw);
2753 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2754 isr_stats->sw);
2755 if (isr_stats->sw || isr_stats->hw) {
2756 pos += scnprintf(buf + pos, bufsz - pos,
2757 "\tLast Restarting Code: 0x%X\n",
2758 isr_stats->err_code);
2759 }
2760#ifdef CONFIG_IWLWIFI_DEBUG
2761 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2762 isr_stats->sch);
2763 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2764 isr_stats->alive);
2765#endif
2766 pos += scnprintf(buf + pos, bufsz - pos,
2767 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2768
2769 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2770 isr_stats->ctkill);
2771
2772 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2773 isr_stats->wakeup);
2774
2775 pos += scnprintf(buf + pos, bufsz - pos,
2776 "Rx command responses:\t\t %u\n", isr_stats->rx);
2777
2778 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2779 isr_stats->tx);
2780
2781 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2782 isr_stats->unhandled);
2783
2784 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2785 kfree(buf);
2786 return ret;
2787}
2788
2789static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2790 const char __user *user_buf,
2791 size_t count, loff_t *ppos)
2792{
2793 struct iwl_trans *trans = file->private_data;
20d3b647 2794 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2795 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2796 u32 reset_flag;
078f1131 2797 int ret;
1f7b6172 2798
078f1131
JB		 2799 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2800 if (ret)
2801 return ret;
1f7b6172
EG		 2802 if (reset_flag == 0)
2803 memset(isr_stats, 0, sizeof(*isr_stats));
2804
2805 return count;
2806}
2807
16db88ba 2808static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2809 const char __user *user_buf,
2810 size_t count, loff_t *ppos)
16db88ba
EG		 2811{
2812 struct iwl_trans *trans = file->private_data;
16db88ba 2813
990aa6d7 2814 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2815
2816 return count;
2817}
2818
16db88ba 2819static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2820 char __user *user_buf,
2821 size_t count, loff_t *ppos)
16db88ba
EG		 2822{
2823 struct iwl_trans *trans = file->private_data;
94543a8d 2824 char *buf = NULL;
56c2477f 2825 ssize_t ret;
16db88ba 2826
56c2477f
JB		 2827 ret = iwl_dump_fh(trans, &buf);
2828 if (ret < 0)
2829 return ret;
2830 if (!buf)
2831 return -EINVAL;
2832 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2833 kfree(buf);
16db88ba
EG		 2834 return ret;
2835}
2836
fa4de7f7
JB		 2837static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2838 char __user *user_buf,
2839 size_t count, loff_t *ppos)
2840{
2841 struct iwl_trans *trans = file->private_data;
2842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2843 char buf[100];
2844 int pos;
2845
2846 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2847 trans_pcie->debug_rfkill,
2848 !(iwl_read32(trans, CSR_GP_CNTRL) &
2849 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2850
2851 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2852}
2853
2854static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2855 const char __user *user_buf,
2856 size_t count, loff_t *ppos)
2857{
2858 struct iwl_trans *trans = file->private_data;
2859 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c5bf4fa1 2860 bool new_value;
fa4de7f7
JB		 2861 int ret;
2862
c5bf4fa1 2863 ret = kstrtobool_from_user(user_buf, count, &new_value);
fa4de7f7
JB		 2864 if (ret)
2865 return ret;
c5bf4fa1 2866 if (new_value == trans_pcie->debug_rfkill)
fa4de7f7
JB		 2867 return count;
2868 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
c5bf4fa1
JB		 2869 trans_pcie->debug_rfkill, new_value);
2870 trans_pcie->debug_rfkill = new_value;
fa4de7f7
JB		 2871 iwl_pcie_handle_rfkill_irq(trans);
2872
2873 return count;
2874}
2875
f7805b33
LC		 2876static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2877 struct file *file)
2878{
2879 struct iwl_trans *trans = inode->i_private;
2880 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2881
91c28b83
SM		 2882 if (!trans->dbg.dest_tlv ||
2883 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
f7805b33
LC		 2884 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2885 return -ENOENT;
2886 }
2887
2888 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2889 return -EBUSY;
2890
2891 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2892 return simple_open(inode, file);
2893}
2894
2895static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2896 struct file *file)
2897{
2898 struct iwl_trans_pcie *trans_pcie =
2899 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2900
2901 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2902 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2903 return 0;
2904}
2905
2906static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2907 void *buf, ssize_t *size,
2908 ssize_t *bytes_copied)
2909{
58d1b717 2910 ssize_t buf_size_left = count - *bytes_copied;
f7805b33
LC		 2911
2912 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2913 if (*size > buf_size_left)
2914 *size = buf_size_left;
2915
2916 *size -= copy_to_user(user_buf, buf, *size);
2917 *bytes_copied += *size;
2918
2919 if (buf_size_left == *size)
2920 return true;
2921 return false;
2922}
2923
2924static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2925 char __user *user_buf,
2926 size_t count, loff_t *ppos)
2927{
2928 struct iwl_trans *trans = file->private_data;
2929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3827cb59 2930 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
f7805b33
LC		 2931 struct cont_rec *data = &trans_pcie->fw_mon_data;
2932 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2933 ssize_t size, bytes_copied = 0;
2934 bool b_full;
2935
91c28b83 2936 if (trans->dbg.dest_tlv) {
f7805b33 2937 write_ptr_addr =
91c28b83
SM		 2938 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2939 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
f7805b33
LC		 2940 } else {
2941 write_ptr_addr = MON_BUFF_WRPTR;
2942 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2943 }
2944
91c28b83 2945 if (unlikely(!trans->dbg.rec_on))
f7805b33
LC		 2946 return 0;
2947
2948 mutex_lock(&data->mutex);
2949 if (data->state ==
2950 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2951 mutex_unlock(&data->mutex);
2952 return 0;
2953 }
2954
2955 /* write_ptr position in bytes rather then DW */
2956 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2957 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2958
2959 if (data->prev_wrap_cnt == wrap_cnt) {
2960 size = write_ptr - data->prev_wr_ptr;
2961 curr_buf = cpu_addr + data->prev_wr_ptr;
2962 b_full = iwl_write_to_user_buf(user_buf, count,
2963 curr_buf, &size,
2964 &bytes_copied);
2965 data->prev_wr_ptr += size;
2966
2967 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2968 write_ptr < data->prev_wr_ptr) {
69f0e505 2969 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
f7805b33
LC		 2970 curr_buf = cpu_addr + data->prev_wr_ptr;
2971 b_full = iwl_write_to_user_buf(user_buf, count,
2972 curr_buf, &size,
2973 &bytes_copied);
2974 data->prev_wr_ptr += size;
2975
2976 if (!b_full) {
2977 size = write_ptr;
2978 b_full = iwl_write_to_user_buf(user_buf, count,
2979 cpu_addr, &size,
2980 &bytes_copied);
2981 data->prev_wr_ptr = size;
2982 data->prev_wrap_cnt++;
2983 }
2984 } else {
2985 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2986 write_ptr > data->prev_wr_ptr)
2987 IWL_WARN(trans,
2988 "write pointer passed previous write pointer, start copying from the beginning\n");
2989 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2990 data->prev_wr_ptr == 0))
2991 IWL_WARN(trans,
2992 "monitor data is out of sync, start copying from the beginning\n");
2993
2994 size = write_ptr;
2995 b_full = iwl_write_to_user_buf(user_buf, count,
2996 cpu_addr, &size,
2997 &bytes_copied);
2998 data->prev_wr_ptr = size;
2999 data->prev_wrap_cnt = wrap_cnt;
3000 }
3001
3002 mutex_unlock(&data->mutex);
3003
3004 return bytes_copied;
3005}
3006
aa899e68
JB		 3007static ssize_t iwl_dbgfs_rf_read(struct file *file,
3008 char __user *user_buf,
3009 size_t count, loff_t *ppos)
3010{
3011 struct iwl_trans *trans = file->private_data;
3012 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3013
3014 if (!trans_pcie->rf_name[0])
3015 return -ENODEV;
3016
3017 return simple_read_from_buffer(user_buf, count, ppos,
3018 trans_pcie->rf_name,
3019 strlen(trans_pcie->rf_name));
3020}
3021
1f7b6172 3022DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 3023DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c 3024DEBUGFS_READ_FILE_OPS(rx_queue);
16db88ba 3025DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 3026DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
aa899e68
JB		 3027DEBUGFS_READ_FILE_OPS(rf);
3028
df67a1be
JB		 3029static const struct file_operations iwl_dbgfs_tx_queue_ops = {
3030 .owner = THIS_MODULE,
3031 .open = iwl_dbgfs_tx_queue_open,
3032 .read = seq_read,
3033 .llseek = seq_lseek,
3034 .release = seq_release_private,
3035};
87e5666c 3036
f7805b33
LC		 3037static const struct file_operations iwl_dbgfs_monitor_data_ops = {
3038 .read = iwl_dbgfs_monitor_data_read,
3039 .open = iwl_dbgfs_monitor_data_open,
3040 .release = iwl_dbgfs_monitor_data_release,
3041};
3042
f8a1edb7 3043/* Create the debugfs files and directories */
cf5d5663 3044void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 3045{
f8a1edb7
JB		 3046 struct dentry *dir = trans->dbgfs_dir;
3047
2ef00c53
JP		 3048 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
3049 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
3050 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
3051 DEBUGFS_ADD_FILE(csr, dir, 0200);
3052 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
3053 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 3054 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
aa899e68 3055 DEBUGFS_ADD_FILE(rf, dir, 0400);
87e5666c 3056}
f7805b33
LC		 3057
3058static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
3059{
3060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3061 struct cont_rec *data = &trans_pcie->fw_mon_data;
3062
3063 mutex_lock(&data->mutex);
3064 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
3065 mutex_unlock(&data->mutex);
3066}
aadede6e 3067#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 3068
6983ba69 3069static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007
JB		 3070{
3071 u32 cmdlen = 0;
3072 int i;
3073
885375d0 3074 for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
0179bfff 3075 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 3076
3077 return cmdlen;
3078}
3079
bd7fc617
EG		 3080static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3081 struct iwl_fw_error_dump_data **data,
3082 int allocated_rb_nums)
3083{
3084 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
80084e35 3085 int max_len = trans_pcie->rx_buf_bytes;
78485054
SS		 3086 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3087 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 3088 u32 i, r, j, rb_len = 0;
3089
3090 spin_lock(&rxq->lock);
3091
0307c839 3092 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 3093
3094 for (i = rxq->read, j = 0;
3095 i != r && j < allocated_rb_nums;
3096 i = (i + 1) & RX_QUEUE_MASK, j++) {
3097 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3098 struct iwl_fw_error_dump_rb *rb;
3099
59a6ee97
JB		 3100 dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3101 max_len, DMA_FROM_DEVICE);
bd7fc617
EG		 3102
3103 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3104
3105 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3106 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3107 rb = (void *)(*data)->data;
3108 rb->index = cpu_to_le32(i);
3109 memcpy(rb->data, page_address(rxb->page), max_len);
bd7fc617
EG		 3110
3111 *data = iwl_fw_error_next_data(*data);
3112 }
3113
3114 spin_unlock(&rxq->lock);
3115
3116 return rb_len;
3117}
473ad712
EG		 3118#define IWL_CSR_TO_DUMP (0x250)
3119
3120static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3121 struct iwl_fw_error_dump_data **data)
3122{
3123 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3124 __le32 *val;
3125 int i;
3126
3127 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3128 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3129 val = (void *)(*data)->data;
3130
3131 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3132 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3133
3134 *data = iwl_fw_error_next_data(*data);
3135
3136 return csr_len;
3137}
3138
06d51e0d
LK		 3139static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3140 struct iwl_fw_error_dump_data **data)
3141{
3142 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
06d51e0d
LK		 3143 __le32 *val;
3144 int i;
3145
1ed08f6f 3146 if (!iwl_trans_grab_nic_access(trans))
06d51e0d
LK		 3147 return 0;
3148
3149 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3150 (*data)->len = cpu_to_le32(fh_regs_len);
3151 val = (void *)(*data)->data;
3152
286ca8eb 3153 if (!trans->trans_cfg->gen2)
723b45e2
LK		 3154 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3155 i += sizeof(u32))
3156 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3157 else
ea695b7c
ST		 3158 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3159 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 3160 i += sizeof(u32))
3161 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3162 i));
06d51e0d 3163
1ed08f6f 3164 iwl_trans_release_nic_access(trans);
06d51e0d
LK		 3165
3166 *data = iwl_fw_error_next_data(*data);
3167
3168 return sizeof(**data) + fh_regs_len;
3169}
3170
cc79ef66
LK		 3171static u32
3172iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3173 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3174 u32 monitor_len)
3175{
3176 u32 buf_size_in_dwords = (monitor_len >> 2);
3177 u32 *buffer = (u32 *)fw_mon_data->data;
cc79ef66
LK		 3178 u32 i;
3179
1ed08f6f 3180 if (!iwl_trans_grab_nic_access(trans))
cc79ef66
LK		 3181 return 0;
3182
ea695b7c 3183 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 3184 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 3185 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3186 MON_DMARB_RD_DATA_ADDR);
3187 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66 3188
1ed08f6f 3189 iwl_trans_release_nic_access(trans);
cc79ef66
LK		 3190
3191 return monitor_len;
3192}
3193
7a14c23d
SS		 3194static void
3195iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3196 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3197{
c88580e1 3198 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
7a14c23d 3199
286ca8eb 3200 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3201 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3202 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3203 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3204 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
91c28b83
SM		 3205 } else if (trans->dbg.dest_tlv) {
3206 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3207 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3208 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
7a14c23d
SS		 3209 } else {
3210 base = MON_BUFF_BASE_ADDR;
3211 write_ptr = MON_BUFF_WRPTR;
3212 wrap_cnt = MON_BUFF_CYCLE_CNT;
3213 }
c88580e1
SM		 3214
3215 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3216 fw_mon_data->fw_mon_cycle_cnt =
3217 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3218 fw_mon_data->fw_mon_base_ptr =
3219 cpu_to_le32(iwl_read_prph(trans, base));
286ca8eb 3220 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3221 fw_mon_data->fw_mon_base_high_ptr =
3222 cpu_to_le32(iwl_read_prph(trans, base_high));
3223 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
cc598782
RS		 3224 /* convert wrtPtr to DWs, to align with all HWs */
3225 write_ptr_val >>= 2;
c88580e1
SM		 3226 }
3227 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3228}
3229
36fb9017
OG		 3230static u32
3231iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3232 struct iwl_fw_error_dump_data **data,
3233 u32 monitor_len)
3234{
69f0e505 3235 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
36fb9017
OG		 3236 u32 len = 0;
3237
91c28b83 3238 if (trans->dbg.dest_tlv ||
69f0e505 3239 (fw_mon->size &&
286ca8eb
LC		 3240 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3241 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
36fb9017 3242 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3243
3244 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3245 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3246
3247 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3248
3249 len += sizeof(**data) + sizeof(*fw_mon_data);
69f0e505
SM		 3250 if (fw_mon->size) {
3251 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3252 monitor_len = fw_mon->size;
91c28b83 3253 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3254 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3255 /*
3256 * Update pointers to reflect actual values after
3257 * shifting
3258 */
91c28b83 3259 if (trans->dbg.dest_tlv->version) {
fd527eb5
GBA		 3260 base = (iwl_read_prph(trans, base) &
3261 IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3262 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3263 base *= IWL_M2S_UNIT_SIZE;
3264 base += trans->cfg->smem_offset;
3265 } else {
3266 base = iwl_read_prph(trans, base) <<
91c28b83 3267 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3268 }
3269
36fb9017
OG		 3270 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3271 monitor_len / sizeof(u32));
91c28b83 3272 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
36fb9017
OG		 3273 monitor_len =
3274 iwl_trans_pci_dump_marbh_monitor(trans,
3275 fw_mon_data,
3276 monitor_len);
3277 } else {
3278 /* Didn't match anything - output no monitor data */
3279 monitor_len = 0;
3280 }
3281
3282 len += monitor_len;
3283 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3284 }
3285
3286 return len;
3287}
3288
93079fd5 3289static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3290{
69f0e505 3291 if (trans->dbg.fw_mon.size) {
da752717
SM		 3292 *len += sizeof(struct iwl_fw_error_dump_data) +
3293 sizeof(struct iwl_fw_error_dump_fw_mon) +
69f0e505
SM		 3294 trans->dbg.fw_mon.size;
3295 return trans->dbg.fw_mon.size;
91c28b83 3296 } else if (trans->dbg.dest_tlv) {
da752717 3297 u32 base, end, cfg_reg, monitor_len;
99684ae3 3298
91c28b83
SM		 3299 if (trans->dbg.dest_tlv->version == 1) {
3300 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
fd527eb5
GBA		 3301 cfg_reg = iwl_read_prph(trans, cfg_reg);
3302 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3303 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3304 base *= IWL_M2S_UNIT_SIZE;
3305 base += trans->cfg->smem_offset;
99684ae3 3306
fd527eb5
GBA		 3307 monitor_len =
3308 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
91c28b83 3309 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3310 monitor_len *= IWL_M2S_UNIT_SIZE;
3311 } else {
91c28b83
SM		 3312 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3313 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
99684ae3 3314
fd527eb5 3315 base = iwl_read_prph(trans, base) <<
91c28b83 3316 trans->dbg.dest_tlv->base_shift;
fd527eb5 3317 end = iwl_read_prph(trans, end) <<
91c28b83 3318 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3319
3320 /* Make "end" point to the actual end */
286ca8eb 3321 if (trans->trans_cfg->device_family >=
fd527eb5 3322 IWL_DEVICE_FAMILY_8000 ||
91c28b83
SM		 3323 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3324 end += (1 << trans->dbg.dest_tlv->end_shift);
fd527eb5
GBA		 3325 monitor_len = end - base;
3326 }
da752717
SM		 3327 *len += sizeof(struct iwl_fw_error_dump_data) +
3328 sizeof(struct iwl_fw_error_dump_fw_mon) +
3329 monitor_len;
3330 return monitor_len;
99684ae3 3331 }
da752717
SM		 3332 return 0;
3333}
3334
fdb70083
JB		 3335static struct iwl_trans_dump_data *
3336iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3337 u32 dump_mask,
3338 const struct iwl_dump_sanitize_ops *sanitize_ops,
3339 void *sanitize_ctx)
da752717
SM		 3340{
3341 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3342 struct iwl_fw_error_dump_data *data;
4f4822b7 3343 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
da752717
SM		 3344 struct iwl_fw_error_dump_txcmd *txcmd;
3345 struct iwl_trans_dump_data *dump_data;
fefbf853 3346 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3347 int i, ptr;
3348 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
286ca8eb 3349 !trans->trans_cfg->mq_rx_supported &&
79f033f6
SS		 3350 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3351
3352 if (!dump_mask)
3353 return NULL;
da752717
SM		 3354
3355 /* transport dump header */
3356 len = sizeof(*dump_data);
3357
3358 /* host commands */
e4eee943 3359 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
8672aad3
SM		 3360 len += sizeof(*data) +
3361 cmdq->n_window * (sizeof(*txcmd) +
3362 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3363
3364 /* FW monitor */
fefbf853
SM		 3365 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3366 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3367
3368 /* CSR registers */
79f033f6 3369 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3370 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3371
36fb9017 3372 /* FH registers */
79f033f6 3373 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
286ca8eb 3374 if (trans->trans_cfg->gen2)
520f03ea 3375 len += sizeof(*data) +
ea695b7c
ST		 3376 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3377 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3378 else
3379 len += sizeof(*data) +
3380 (FH_MEM_UPPER_BOUND -
3381 FH_MEM_LOWER_BOUND);
3382 }
36fb9017
OG		 3383
3384 if (dump_rbs) {
78485054
SS		 3385 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3386 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3387 /* RBs */
0307c839
GBA		 3388 num_rbs =
3389 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3390 & 0x0FFF;
78485054 3391 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3392 len += num_rbs * (sizeof(*data) +
3393 sizeof(struct iwl_fw_error_dump_rb) +
3394 (PAGE_SIZE << trans_pcie->rx_page_order));
3395 }
3396
5538409b 3397 /* Paged memory for gen2 HW */
286ca8eb 3398 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3399 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3400 len += sizeof(*data) +
3401 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3402 trans->init_dram.paging[i].size;
5538409b 3403
48eb7b34
EG		 3404 dump_data = vzalloc(len);
3405 if (!dump_data)
3406 return NULL;
4d075007
JB		 3407
3408 len = 0;
48eb7b34 3409 data = (void *)dump_data->data;
520f03ea 3410
e4eee943 3411 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
885375d0 3412 u16 tfd_size = trans->txqs.tfd.size;
520f03ea
SM		 3413
3414 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3415 txcmd = (void *)data->data;
3416 spin_lock_bh(&cmdq->lock);
3417 ptr = cmdq->write_ptr;
3418 for (i = 0; i < cmdq->n_window; i++) {
0cd1ad2d 3419 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
08326a97 3420 u8 tfdidx;
520f03ea
SM		 3421 u32 caplen, cmdlen;
3422
12a89f01 3423 if (trans->trans_cfg->gen2)
08326a97
JB		 3424 tfdidx = idx;
3425 else
3426 tfdidx = ptr;
3427
520f03ea 3428 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
08326a97
JB		 3429 (u8 *)cmdq->tfds +
3430 tfd_size * tfdidx);
520f03ea
SM		 3431 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3432
3433 if (cmdlen) {
3434 len += sizeof(*txcmd) + caplen;
3435 txcmd->cmdlen = cpu_to_le32(cmdlen);
3436 txcmd->caplen = cpu_to_le32(caplen);
3437 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3438 caplen);
fdb70083
JB		 3439 if (sanitize_ops && sanitize_ops->frob_hcmd)
3440 sanitize_ops->frob_hcmd(sanitize_ctx,
3441 txcmd->data,
3442 caplen);
520f03ea
SM		 3443 txcmd = (void *)((u8 *)txcmd->data + caplen);
3444 }
3445
0cd1ad2d 3446 ptr = iwl_txq_dec_wrap(trans, ptr);
4d075007 3447 }
520f03ea 3448 spin_unlock_bh(&cmdq->lock);
4d075007 3449
520f03ea
SM		 3450 data->len = cpu_to_le32(len);
3451 len += sizeof(*data);
3452 data = iwl_fw_error_next_data(data);
4d075007 3453 }
67c65f2c 3454
79f033f6 3455 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3456 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3457 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3458 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3459 if (dump_rbs)
3460 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3461
5538409b 3462 /* Paged memory for gen2 HW */
286ca8eb 3463 if (trans->trans_cfg->gen2 &&
79b6c8fe 3464 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3465 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3466 struct iwl_fw_error_dump_paging *paging;
505a00c0 3467 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3468
3469 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3470 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3471 paging = (void *)data->data;
3472 paging->index = cpu_to_le32(i);
5538409b 3473 memcpy(paging->data,
505a00c0 3474 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3475 data = iwl_fw_error_next_data(data);
3476
3477 len += sizeof(*data) + sizeof(*paging) + page_len;
3478 }
3479 }
79f033f6 3480 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3481 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3482
48eb7b34
EG		 3483 dump_data->len = len;
3484
3485 return dump_data;
4d075007 3486}
87e5666c 3487
3161a34d 3488static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
4cbb8e50 3489{
3161a34d
MG		 3490 if (enable)
3491 iwl_enable_interrupts(trans);
3492 else
3493 iwl_disable_interrupts(trans);
4cbb8e50
LC		 3494}
3495
3161a34d 3496static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
4cbb8e50 3497{
3161a34d
MG		 3498 u32 inta_addr, sw_err_bit;
3499 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3500
3501 if (trans_pcie->msix_enabled) {
3502 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
571836a0
MG		 3503 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3504 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
3505 else
3506 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3161a34d
MG		 3507 } else {
3508 inta_addr = CSR_INT;
3509 sw_err_bit = CSR_INT_BIT_SW_ERR;
3510 }
3511
3512 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
4cbb8e50 3513}
4cbb8e50 3514
623e7766
SS		 3515#define IWL_TRANS_COMMON_OPS \
3516 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3517 .write8 = iwl_trans_pcie_write8, \
3518 .write32 = iwl_trans_pcie_write32, \
3519 .read32 = iwl_trans_pcie_read32, \
3520 .read_prph = iwl_trans_pcie_read_prph, \
3521 .write_prph = iwl_trans_pcie_write_prph, \
3522 .read_mem = iwl_trans_pcie_read_mem, \
3523 .write_mem = iwl_trans_pcie_write_mem, \
7f1fe1d4 3524 .read_config32 = iwl_trans_pcie_read_config32, \
623e7766
SS		 3525 .configure = iwl_trans_pcie_configure, \
3526 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3527 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3528 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3529 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3530 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
623e7766 3531 .dump_data = iwl_trans_pcie_dump_data, \
623e7766 3532 .d3_suspend = iwl_trans_pcie_d3_suspend, \
d1967ce6 3533 .d3_resume = iwl_trans_pcie_d3_resume, \
3161a34d 3534 .interrupts = iwl_trans_pci_interrupts, \
c0941ace
MS		 3535 .sync_nmi = iwl_trans_pcie_sync_nmi, \
3536 .imr_dma_data = iwl_trans_pcie_copy_imr \
623e7766 3537
d1ff5253 3538static const struct iwl_trans_ops trans_ops_pcie = {
623e7766 3539 IWL_TRANS_COMMON_OPS,
57a1dc89 3540 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3541 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3542 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3543 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3544
13f028b4 3545 .send_cmd = iwl_pcie_enqueue_hcmd,
2dd4f9f7 3546
623e7766 3547 .tx = iwl_trans_pcie_tx,
a4450980 3548 .reclaim = iwl_txq_reclaim,
623e7766
SS		 3549
3550 .txq_disable = iwl_trans_pcie_txq_disable,
3551 .txq_enable = iwl_trans_pcie_txq_enable,
3552
3553 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3554
d6d517b7
SS		 3555 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3556
a4450980 3557 .freeze_txq_timer = iwl_trans_txq_freeze_timer,
623e7766 3558 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3559#ifdef CONFIG_IWLWIFI_DEBUGFS
3560 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3561#endif
623e7766
SS		 3562};
3563
3564static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3565 IWL_TRANS_COMMON_OPS,
623e7766 3566 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3567 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3568 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3569 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3570
13f028b4 3571 .send_cmd = iwl_pcie_gen2_enqueue_hcmd,
c85eb619 3572
0cd1ad2d 3573 .tx = iwl_txq_gen2_tx,
a4450980 3574 .reclaim = iwl_txq_reclaim,
34c1b7ba 3575
a4450980 3576 .set_q_ptrs = iwl_txq_set_q_ptrs,
ba7136f3 3577
0cd1ad2d
MG		 3578 .txq_alloc = iwl_txq_dyn_alloc,
3579 .txq_free = iwl_txq_dyn_free,
d6d517b7 3580 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3581 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
194d1f84 3582 .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm,
6654cd4e 3583 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
c738fb61 3584 .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power,
9dad325f 3585 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
f7805b33
LC		 3586#ifdef CONFIG_IWLWIFI_DEBUGFS
3587 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3588#endif
e6bb4c9c 3589};
a42a1844 3590
87ce05a2 3591struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
7e8258c0
LC		 3592 const struct pci_device_id *ent,
3593 const struct iwl_cfg_trans_params *cfg_trans)
a42a1844 3594{
a42a1844
EG		 3595 struct iwl_trans_pcie *trans_pcie;
3596 struct iwl_trans *trans;
fda1bd0d 3597 int ret, addr_size;
a89c72ff 3598 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
f00c3f9e 3599 void __iomem * const *table;
a89c72ff 3600
fda1bd0d 3601 if (!cfg_trans->gen2)
a89c72ff 3602 ops = &trans_ops_pcie;
a42a1844 3603
5a41a86c
SD		 3604 ret = pcim_enable_device(pdev);
3605 if (ret)
3606 return ERR_PTR(ret);
3607
a89c72ff 3608 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
fda1bd0d 3609 cfg_trans);
7b501d10
JB		 3610 if (!trans)
3611 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3612
3613 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3614
a42a1844 3615 trans_pcie->trans = trans;
326477e4 3616 trans_pcie->opmode_down = true;
7b11488f 3617 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3618 spin_lock_init(&trans_pcie->reg_lock);
cfdc20ef 3619 spin_lock_init(&trans_pcie->alloc_page_lock);
fa9f3281 3620 mutex_init(&trans_pcie->mutex);
13df1aab 3621 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
906d4eb8 3622 init_waitqueue_head(&trans_pcie->fw_reset_waitq);
c0941ace 3623 init_waitqueue_head(&trans_pcie->imr_waitq);
8188a18e
JB		 3624
3625 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
4c1b3f26 3626 WQ_HIGHPRI | WQ_UNBOUND, 0);
8188a18e
JB		 3627 if (!trans_pcie->rba.alloc_wq) {
3628 ret = -ENOMEM;
3629 goto out_free_trans;
3630 }
3631 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3632
c5bf4fa1 3633 trans_pcie->debug_rfkill = -1;
d819c6cf 3634
7e8258c0 3635 if (!cfg_trans->base_params->pcie_l1_allowed) {
f2532b04
EG		 3636 /*
3637 * W/A - seems to solve weird behavior. We need to remove this
3638 * if we don't want to stay in L1 all the time. This wastes a
3639 * lot of power.
3640 */
3641 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3642 PCIE_LINK_STATE_L1 |
3643 PCIE_LINK_STATE_CLKPM);
3644 }
a42a1844 3645
a42a1844
EG		 3646 pci_set_master(pdev);
3647
885375d0 3648 addr_size = trans->txqs.tfd.addr_size;
ebe9e651 3649 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
af3f2f74 3650 if (ret) {
ebe9e651 3651 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
a42a1844 3652 /* both attempts failed: */
af3f2f74 3653 if (ret) {
6a4b09f8 3654 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3655 goto out_no_pci;
a42a1844
EG		 3656 }
3657 }
3658
5a41a86c 3659 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3660 if (ret) {
5a41a86c
SD		 3661 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3662 goto out_no_pci;
a42a1844
EG		 3663 }
3664
f00c3f9e
JB		 3665 table = pcim_iomap_table(pdev);
3666 if (!table) {
5a41a86c 3667 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
f00c3f9e
JB		 3668 ret = -ENOMEM;
3669 goto out_no_pci;
3670 }
3671
3672 trans_pcie->hw_base = table[0];
3673 if (!trans_pcie->hw_base) {
3674 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
af3f2f74 3675 ret = -ENODEV;
5a41a86c 3676 goto out_no_pci;
a42a1844
EG		 3677 }
3678
a42a1844
EG		 3679 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3680 * PCI Tx retries from interfering with C3 CPU state */
3681 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3682
83f7a85f
EG		 3683 trans_pcie->pci_dev = pdev;
3684 iwl_disable_interrupts(trans);
3685
08079a49 3686 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3687 if (trans->hw_rev == 0xffffffff) {
3688 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3689 ret = -EIO;
3690 goto out_no_pci;
3691 }
3692
b513ee7f
LK		 3693 /*
3694 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3695 * changed, and now the revision step also includes bit 0-1 (no more
3696 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3697 * in the old format.
3698 */
4adfaf9b 3699 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
55c6d8f8
MG		 3700 trans->hw_rev_step = trans->hw_rev & 0xF;
3701 else
3702 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2;
b513ee7f 3703
99be6166
LC		 3704 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3705
7e8258c0 3706 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
99673ee5 3707 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3708 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3709 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3710
e5f3f215
HD		 3711 init_waitqueue_head(&trans_pcie->sx_waitq);
3712
c83031af
JB		 3713 ret = iwl_pcie_alloc_invalid_tx_cmd(trans);
3714 if (ret)
3715 goto out_no_pci;
c239feec 3716
2e5d4a8f 3717 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3718 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3719 if (ret)
5a41a86c 3720 goto out_no_pci;
2e5d4a8f
HD		 3721 } else {
3722 ret = iwl_pcie_alloc_ict(trans);
3723 if (ret)
5a41a86c 3724 goto out_no_pci;
a8b691e6 3725
5a41a86c
SD		 3726 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3727 iwl_pcie_isr,
3728 iwl_pcie_irq_handler,
3729 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3730 if (ret) {
3731 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3732 goto out_free_ict;
3733 }
2e5d4a8f 3734 }
83f7a85f 3735
f7805b33
LC		 3736#ifdef CONFIG_IWLWIFI_DEBUGFS
3737 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3738 mutex_init(&trans_pcie->fw_mon_data.mutex);
3739#endif
3740
a9248de4
SM		 3741 iwl_dbg_tlv_init(trans);
3742
a42a1844
EG		 3743 return trans;
3744
a8b691e6
JB		 3745out_free_ict:
3746 iwl_pcie_free_ict(trans);
a42a1844 3747out_no_pci:
8188a18e
JB		 3748 destroy_workqueue(trans_pcie->rba.alloc_wq);
3749out_free_trans:
7b501d10 3750 iwl_trans_free(trans);
af3f2f74 3751 return ERR_PTR(ret);
a42a1844 3752}
c0941ace
MS		 3753
3754void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
3755 u32 dst_addr, u64 src_addr, u32 byte_cnt)
3756{
3757 iwl_write_prph(trans, IMR_UREG_CHICK,
3758 iwl_read_prph(trans, IMR_UREG_CHICK) |
3759 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
3760 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
3761 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
3762 (u32)(src_addr & 0xFFFFFFFF));
3763 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
3764 iwl_get_dma_hi_addr(src_addr));
3765 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
3766 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
3767 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
3768 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
3769 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
3770}
3771
3772int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
3773 u32 dst_addr, u64 src_addr, u32 byte_cnt)
3774{
3775 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3776 int ret = -1;
3777
3778 trans_pcie->imr_status = IMR_D2S_REQUESTED;
3779 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);
3780 ret = wait_event_timeout(trans_pcie->imr_waitq,
3781 trans_pcie->imr_status !=
3782 IMR_D2S_REQUESTED, 5 * HZ);
3783 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) {
3784 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");
3785 iwl_trans_pcie_dump_regs(trans);
3786 return -ETIMEDOUT;
3787 }
3788 trans_pcie->imr_status = IMR_D2S_IDLE;
3789 return 0;
3790}
Linux 6.x block layer and io_uring tree(s)