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iwlwifi: remove deprecated and unused iwl_mvm_keyinfo struct
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 11 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
c85eb619 22 * The full GNU General Public License is included in this distribution
410dc5aa 23 * in the file called COPYING.
c85eb619
EG		 24 *
25 * Contact Information:
cb2f8277 26 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
553452e5
LK		 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 34 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
a42a1844 64#include <linux/pci.h>
e6bb4c9c 65#include <linux/interrupt.h>
87e5666c 66#include <linux/debugfs.h>
cf614297 67#include <linux/sched.h>
6d8f6eeb
EG		 68#include <linux/bitops.h>
69#include <linux/gfp.h>
48eb7b34 70#include <linux/vmalloc.h>
49564a80 71#include <linux/module.h>
f7805b33 72#include <linux/wait.h>
df67a1be 73#include <linux/seq_file.h>
e6bb4c9c 74
82575102 75#include "iwl-drv.h"
c85eb619 76#include "iwl-trans.h"
522376d2
EG		 77#include "iwl-csr.h"
78#include "iwl-prph.h"
cb6bb128 79#include "iwl-scd.h"
7a10e3e4 80#include "iwl-agn-hw.h"
d962f9b1 81#include "fw/error-dump.h"
520f03ea 82#include "fw/dbg.h"
a89c72ff 83#include "fw/api/tx.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
4290eaad 91void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad 92{
c4d3f2ee
LC		 93#define PCI_DUMP_SIZE 352
94#define PCI_MEM_DUMP_SIZE 64
95#define PCI_PARENT_DUMP_SIZE 524
96#define PREFIX_LEN 32
a6d24fad
RJ		 97 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
98 struct pci_dev *pdev = trans_pcie->pci_dev;
99 u32 i, pos, alloc_size, *ptr, *buf;
100 char *prefix;
101
102 if (trans_pcie->pcie_dbg_dumped_once)
103 return;
104
105 /* Should be a multiple of 4 */
106 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
c4d3f2ee
LC		 107 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
108 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
109
a6d24fad 110 /* Alloc a max size buffer */
c4d3f2ee
LC		 111 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
112 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
113 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
114 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
115
a6d24fad
RJ		 116 buf = kmalloc(alloc_size, GFP_ATOMIC);
117 if (!buf)
118 return;
119 prefix = (char *)buf + alloc_size - PREFIX_LEN;
120
121 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
122
123 /* Print wifi device registers */
124 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
125 IWL_ERR(trans, "iwlwifi device config registers:\n");
126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
127 if (pci_read_config_dword(pdev, i, ptr))
128 goto err_read;
129 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
130
131 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
c4d3f2ee 132 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 133 *ptr = iwl_read32(trans, i);
134 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
135
136 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
137 if (pos) {
138 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
139 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
140 if (pci_read_config_dword(pdev, pos + i, ptr))
141 goto err_read;
142 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
143 32, 4, buf, i, 0);
144 }
145
146 /* Print parent device registers next */
147 if (!pdev->bus->self)
148 goto out;
149
150 pdev = pdev->bus->self;
151 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
152
153 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
154 pci_name(pdev));
c4d3f2ee 155 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 156 if (pci_read_config_dword(pdev, i, ptr))
157 goto err_read;
158 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
159
160 /* Print root port AER registers */
161 pos = 0;
162 pdev = pcie_find_root_port(pdev);
163 if (pdev)
164 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
165 if (pos) {
166 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
167 pci_name(pdev));
168 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
169 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
170 if (pci_read_config_dword(pdev, pos + i, ptr))
171 goto err_read;
172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
173 4, buf, i, 0);
174 }
f3402d6d 175 goto out;
a6d24fad
RJ		 176
177err_read:
178 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
179 IWL_ERR(trans, "Read failed at 0x%X\n", i);
180out:
181 trans_pcie->pcie_dbg_dumped_once = 1;
182 kfree(buf);
183}
184
870c2a11
GBA		 185static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
186{
187 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
6dece0e9 188 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
870c2a11
GBA		 189 usleep_range(5000, 6000);
190}
191
c2d20201
EG		 192static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
193{
69f0e505 194 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 195
69f0e505
SM		 196 if (!fw_mon->size)
197 return;
198
199 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
200 fw_mon->physical);
201
202 fw_mon->block = NULL;
203 fw_mon->physical = 0;
204 fw_mon->size = 0;
c2d20201
EG		 205}
206
88964b2e
SS		 207static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
208 u8 max_power, u8 min_power)
c2d20201 209{
69f0e505
SM		 210 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
211 void *block = NULL;
212 dma_addr_t physical = 0;
96c285da 213 u32 size = 0;
c2d20201
EG		 214 u8 power;
215
69f0e505
SM		 216 if (fw_mon->size)
217 return;
218
88964b2e 219 for (power = max_power; power >= min_power; power--) {
c2d20201 220 size = BIT(power);
69f0e505
SM		 221 block = dma_alloc_coherent(trans->dev, size, &physical,
222 GFP_KERNEL | __GFP_NOWARN);
223 if (!block)
c2d20201
EG		 224 continue;
225
c2d20201 226 IWL_INFO(trans,
c5f97542
SM		 227 "Allocated 0x%08x bytes for firmware monitor.\n",
228 size);
c2d20201
EG		 229 break;
230 }
231
69f0e505 232 if (WARN_ON_ONCE(!block))
c2d20201
EG		 233 return;
234
96c285da
EG		 235 if (power != max_power)
236 IWL_ERR(trans,
237 "Sorry - debug buffer is only %luK while you requested %luK\n",
238 (unsigned long)BIT(power - 10),
239 (unsigned long)BIT(max_power - 10));
240
69f0e505
SM		 241 fw_mon->block = block;
242 fw_mon->physical = physical;
243 fw_mon->size = size;
88964b2e
SS		 244}
245
246void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
247{
248 if (!max_power) {
249 /* default max_power is maximum */
250 max_power = 26;
251 } else {
252 max_power += 11;
253 }
254
255 if (WARN(max_power > 26,
256 "External buffer size for monitor is too big %d, check the FW TLV\n",
257 max_power))
258 return;
259
69f0e505 260 if (trans->dbg.fw_mon.size)
88964b2e
SS		 261 return;
262
263 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
c2d20201
EG		 264}
265
a812cba9
AB		 266static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
267{
268 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
269 ((reg & 0x0000ffff) | (2 << 28)));
270 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
271}
272
273static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
274{
275 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
276 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
277 ((reg & 0x0000ffff) | (3 << 28)));
278}
279
ddaf5a5b 280static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 281{
66337b7c 282 if (trans->cfg->apmg_not_supported)
95411d04
AA		 283 return;
284
ddaf5a5b
JB		 285 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
286 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
287 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
288 ~APMG_PS_CTRL_MSK_PWR_SRC);
289 else
290 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
291 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
292 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 293}
294
af634bee
EG		 295/* PCI registers */
296#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 297
eda50cde 298void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 299{
20d3b647 300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 301 u16 lctl;
9180ac50 302 u16 cap;
af634bee 303
af634bee 304 /*
cc894b85
LC		 305 * L0S states have been found to be unstable with our devices
306 * and in newer hardware they are not officially supported at
307 * all, so we must always set the L0S_DISABLED bit.
af634bee 308 */
cc894b85
LC		 309 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
310
7afe3705 311 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
438a0f0a 312 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 313
314 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
315 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 316 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
317 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
318 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 319}
320
a6c684ee
EG		 321/*
322 * Start up NIC's basic functionality after it has been reset
7afe3705 323 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 324 * NOTE: This does not load uCode nor start the embedded processor
325 */
7afe3705 326static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 327{
52b6e168
EG		 328 int ret;
329
a6c684ee
EG		 330 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
331
332 /*
333 * Use "set_bit" below rather than "write", to preserve any hardware
334 * bits already set by default after reset.
335 */
336
337 /* Disable L0S exit timer (platform NMI Work/Around) */
286ca8eb 338 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 339 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
340 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 341
342 /*
343 * Disable L0s without affecting L1;
344 * don't wait for ICH L0s (ICH bug W/A)
345 */
346 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 347 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 348
349 /* Set FH wait threshold to maximum (HW error during stress W/A) */
350 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
351
352 /*
353 * Enable HAP INTA (interrupt from management bus) to
354 * wake device's PCI Express link L1a -> L0s
355 */
356 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 357 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 358
7afe3705 359 iwl_pcie_apm_config(trans);
a6c684ee
EG		 360
361 /* Configure analog phase-lock-loop before activating to D0A */
286ca8eb 362 if (trans->trans_cfg->base_params->pll_cfg)
77d76931 363 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 364
7d34a7d7 365 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 366 if (ret)
52b6e168 367 return ret;
a6c684ee 368
2d93aee1
EG		 369 if (trans->cfg->host_interrupt_operation_mode) {
370 /*
371 * This is a bit of an abuse - This is needed for 7260 / 3160
372 * only check host_interrupt_operation_mode even if this is
373 * not related to host_interrupt_operation_mode.
374 *
375 * Enable the oscillator to count wake up time for L1 exit. This
376 * consumes slightly more power (100uA) - but allows to be sure
377 * that we wake up from L1 on time.
378 *
379 * This looks weird: read twice the same register, discard the
380 * value, set a bit, and yet again, read that same register
381 * just to discard the value. But that's the way the hardware
382 * seems to like it.
383 */
384 iwl_read_prph(trans, OSC_CLK);
385 iwl_read_prph(trans, OSC_CLK);
386 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
387 iwl_read_prph(trans, OSC_CLK);
388 iwl_read_prph(trans, OSC_CLK);
389 }
390
a6c684ee
EG		 391 /*
392 * Enable DMA clock and wait for it to stabilize.
393 *
3073d8c0
EH		 394 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
395 * bits do not disable clocks. This preserves any hardware
396 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 397 */
95411d04 398 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 399 iwl_write_prph(trans, APMG_CLK_EN_REG,
400 APMG_CLK_VAL_DMA_CLK_RQT);
401 udelay(20);
402
403 /* Disable L1-Active */
404 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
405 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
406
407 /* Clear the interrupt in APMG if the NIC is in RFKILL */
408 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
409 APMG_RTC_INT_STT_RFKILL);
410 }
889b1696 411
eb7ff77e 412 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 413
52b6e168 414 return 0;
a6c684ee
EG		 415}
416
a812cba9
AB		 417/*
418 * Enable LP XTAL to avoid HW bug where device may consume much power if
419 * FW is not loaded after device reset. LP XTAL is disabled by default
420 * after device HW reset. Do it only if XTAL is fed by internal source.
421 * Configure device's "persistence" mode to avoid resetting XTAL again when
422 * SHRD_HW_RST occurs in S3.
423 */
424static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
425{
426 int ret;
427 u32 apmg_gp1_reg;
428 u32 apmg_xtal_cfg_reg;
429 u32 dl_cfg_reg;
430
431 /* Force XTAL ON */
432 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
433 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
434
870c2a11 435 iwl_trans_pcie_sw_reset(trans);
a812cba9 436
7d34a7d7 437 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 438 if (WARN_ON(ret)) {
a812cba9
AB		 439 /* Release XTAL ON request */
440 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
441 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
442 return;
443 }
444
445 /*
446 * Clear "disable persistence" to avoid LP XTAL resetting when
447 * SHRD_HW_RST is applied in S3.
448 */
449 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
450 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
451
452 /*
453 * Force APMG XTAL to be active to prevent its disabling by HW
454 * caused by APMG idle state.
455 */
456 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
457 SHR_APMG_XTAL_CFG_REG);
458 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
459 apmg_xtal_cfg_reg |
460 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
461
870c2a11 462 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 463
464 /* Enable LP XTAL by indirect access through CSR */
465 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
466 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
467 SHR_APMG_GP1_WF_XTAL_LP_EN |
468 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
469
470 /* Clear delay line clock power up */
471 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
472 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
473 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
474
475 /*
476 * Enable persistence mode to avoid LP XTAL resetting when
477 * SHRD_HW_RST is applied in S3.
478 */
479 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
480 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
481
482 /*
483 * Clear "initialization complete" bit to move adapter from
484 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
485 */
6dece0e9 486 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
a812cba9
AB		 487
488 /* Activates XTAL resources monitor */
489 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
490 CSR_MONITOR_XTAL_RESOURCES);
491
492 /* Release XTAL ON request */
493 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
494 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
495 udelay(10);
496
497 /* Release APMG XTAL */
498 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
499 apmg_xtal_cfg_reg &
500 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
501}
502
e8c8935e 503void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 504{
e8c8935e 505 int ret;
cc56feb2
EG		 506
507 /* stop device's busmaster DMA activity */
6dece0e9 508 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
cc56feb2 509
6dece0e9
LC		 510 ret = iwl_poll_bit(trans, CSR_RESET,
511 CSR_RESET_REG_FLAG_MASTER_DISABLED,
512 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 513 if (ret < 0)
cc56feb2
EG		 514 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
515
516 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 517}
518
b7aaeae4 519static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 520{
521 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
522
b7aaeae4
EG		 523 if (op_mode_leave) {
524 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
525 iwl_pcie_apm_init(trans);
526
527 /* inform ME that we are leaving */
286ca8eb 528 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
b7aaeae4
EG		 529 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
530 APMG_PCIDEV_STT_VAL_WAKE_ME);
286ca8eb 531 else if (trans->trans_cfg->device_family >=
79b6c8fe 532 IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 533 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
534 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 535 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
536 CSR_HW_IF_CONFIG_REG_PREPARE |
537 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 538 mdelay(1);
539 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
540 CSR_RESET_LINK_PWR_MGMT_DISABLED);
541 }
b7aaeae4
EG		 542 mdelay(5);
543 }
544
eb7ff77e 545 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 546
547 /* Stop device's DMA activity */
7afe3705 548 iwl_pcie_apm_stop_master(trans);
cc56feb2 549
a812cba9
AB		 550 if (trans->cfg->lp_xtal_workaround) {
551 iwl_pcie_apm_lp_xtal_enable(trans);
552 return;
553 }
554
870c2a11 555 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 556
557 /*
558 * Clear "initialization complete" bit to move adapter from
559 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
560 */
6dece0e9 561 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
cc56feb2
EG		 562}
563
7afe3705 564static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 565{
7b11488f 566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 567 int ret;
392f8b78
EG		 568
569 /* nic_init */
7b70bd63 570 spin_lock(&trans_pcie->irq_lock);
52b6e168 571 ret = iwl_pcie_apm_init(trans);
7b70bd63 572 spin_unlock(&trans_pcie->irq_lock);
392f8b78 573
52b6e168
EG		 574 if (ret)
575 return ret;
576
95411d04 577 iwl_pcie_set_pwr(trans, false);
392f8b78 578
ecdb975c 579 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 580
581 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 582 iwl_pcie_rx_init(trans);
392f8b78
EG		 583
584 /* Allocate or reset and init all Tx and Command queues */
f02831be 585 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 586 return -ENOMEM;
587
286ca8eb 588 if (trans->trans_cfg->base_params->shadow_reg_enable) {
392f8b78 589 /* enable shadow regs in HW */
20d3b647 590 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 591 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 592 }
593
392f8b78
EG		 594 return 0;
595}
596
597#define HW_READY_TIMEOUT (50)
598
599/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 600static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 601{
602 int ret;
603
1042db2a 604 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 605 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 606
607 /* See if we got it */
1042db2a 608 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
610 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
611 HW_READY_TIMEOUT);
392f8b78 612
6a08f514
EG		 613 if (ret >= 0)
614 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
615
6d8f6eeb 616 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 617 return ret;
618}
619
620/* Note: returns standard 0/-ERROR code */
eda50cde 621int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 622{
623 int ret;
289e5501 624 int t = 0;
501fd989 625 int iter;
392f8b78 626
6d8f6eeb 627 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 628
7afe3705 629 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 630 /* If the card is ready, exit 0 */
392f8b78
EG		 631 if (ret >= 0)
632 return 0;
633
c9fdec9f
EG		 634 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
635 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 636 usleep_range(1000, 2000);
c9fdec9f 637
501fd989
EG		 638 for (iter = 0; iter < 10; iter++) {
639 /* If HW is not ready, prepare the conditions to check again */
640 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
641 CSR_HW_IF_CONFIG_REG_PREPARE);
642
643 do {
644 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 645 if (ret >= 0)
646 return 0;
392f8b78 647
501fd989
EG		 648 usleep_range(200, 1000);
649 t += 200;
650 } while (t < 150000);
651 msleep(25);
652 }
392f8b78 653
7f2ac8fb 654 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 655
392f8b78
EG		 656 return ret;
657}
658
cf614297
EG		 659/*
660 * ucode
661 */
564cdce7
SS		 662static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
663 u32 dst_addr, dma_addr_t phy_addr,
664 u32 byte_cnt)
cf614297 665{
bac842da
EG		 666 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
667 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
668
669 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
670 dst_addr);
671
672 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
673 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
674
675 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
676 (iwl_get_dma_hi_addr(phy_addr)
677 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
678
679 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
680 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
681 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
682 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
683
684 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
687 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 688}
689
564cdce7
SS		 690static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
691 u32 dst_addr, dma_addr_t phy_addr,
692 u32 byte_cnt)
693{
694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
695 unsigned long flags;
696 int ret;
697
698 trans_pcie->ucode_write_complete = false;
699
700 if (!iwl_trans_grab_nic_access(trans, &flags))
701 return -EIO;
702
eda50cde
SS		 703 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
704 byte_cnt);
bac842da 705 iwl_trans_release_nic_access(trans, &flags);
cf614297 706
13df1aab
JB		 707 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
708 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 709 if (!ret) {
83f84d7b 710 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 711 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 712 return -ETIMEDOUT;
713 }
714
715 return 0;
716}
717
7afe3705 718static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 719 const struct fw_desc *section)
cf614297 720{
83f84d7b
JB		 721 u8 *v_addr;
722 dma_addr_t p_addr;
baa21e83 723 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 724 int ret = 0;
725
83f84d7b
JB		 726 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
727 section_num);
728
c571573a
EG		 729 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
730 GFP_KERNEL | __GFP_NOWARN);
731 if (!v_addr) {
732 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
733 chunk_sz = PAGE_SIZE;
734 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
735 &p_addr, GFP_KERNEL);
736 if (!v_addr)
737 return -ENOMEM;
738 }
83f84d7b 739
c571573a 740 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 741 u32 copy_size, dst_addr;
742 bool extended_addr = false;
83f84d7b 743
c571573a 744 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 745 dst_addr = section->offset + offset;
746
747 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
748 dst_addr <= IWL_FW_MEM_EXTENDED_END)
749 extended_addr = true;
750
751 if (extended_addr)
752 iwl_set_bits_prph(trans, LMPM_CHICK,
753 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 754
83f84d7b 755 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 756 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
757 copy_size);
758
759 if (extended_addr)
760 iwl_clear_bits_prph(trans, LMPM_CHICK,
761 LMPM_CHICK_EXTENDED_ADDR_SPACE);
762
83f84d7b
JB		 763 if (ret) {
764 IWL_ERR(trans,
765 "Could not load the [%d] uCode section\n",
766 section_num);
767 break;
6dfa8d01 768 }
83f84d7b
JB		 769 }
770
c571573a 771 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 772 return ret;
773}
774
5dd9c68a
EG		 775static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
776 const struct fw_img *image,
777 int cpu,
778 int *first_ucode_section)
e2d6f4e7
EH		 779{
780 int shift_param;
dcab8ecd
EH		 781 int i, ret = 0, sec_num = 0x1;
782 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 783
784 if (cpu == 1) {
785 shift_param = 0;
034846cf 786 *first_ucode_section = 0;
e2d6f4e7
EH		 787 } else {
788 shift_param = 16;
034846cf 789 (*first_ucode_section)++;
e2d6f4e7
EH		 790 }
791
eef187a7 792 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 793 last_read_idx = i;
794
a6c4fb44
MG		 795 /*
796 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
797 * CPU1 to CPU2.
798 * PAGING_SEPARATOR_SECTION delimiter - separate between
799 * CPU2 non paged to CPU2 paging sec.
800 */
034846cf 801 if (!image->sec[i].data ||
a6c4fb44
MG		 802 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
803 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 804 IWL_DEBUG_FW(trans,
805 "Break since Data not valid or Empty section, sec = %d\n",
806 i);
189fa2fa 807 break;
034846cf
EH		 808 }
809
189fa2fa
EH		 810 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
811 if (ret)
812 return ret;
dcab8ecd 813
d6a2c5c7 814 /* Notify ucode of loaded section number and status */
eda50cde
SS		 815 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
816 val = val | (sec_num << shift_param);
817 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
818
dcab8ecd 819 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 820 }
821
034846cf
EH		 822 *first_ucode_section = last_read_idx;
823
2aabdbdc
EG		 824 iwl_enable_interrupts(trans);
825
286ca8eb 826 if (trans->trans_cfg->use_tfh) {
d6a2c5c7
SS		 827 if (cpu == 1)
828 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
829 0xFFFF);
830 else
831 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
832 0xFFFFFFFF);
833 } else {
834 if (cpu == 1)
835 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
836 0xFFFF);
837 else
838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
839 0xFFFFFFFF);
840 }
afb88917 841
189fa2fa
EH		 842 return 0;
843}
e2d6f4e7 844
189fa2fa
EH		 845static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
846 const struct fw_img *image,
034846cf
EH		 847 int cpu,
848 int *first_ucode_section)
189fa2fa 849{
189fa2fa 850 int i, ret = 0;
034846cf 851 u32 last_read_idx = 0;
189fa2fa 852
3ce4a038 853 if (cpu == 1)
034846cf 854 *first_ucode_section = 0;
3ce4a038 855 else
034846cf 856 (*first_ucode_section)++;
189fa2fa 857
eef187a7 858 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 859 last_read_idx = i;
860
a6c4fb44
MG		 861 /*
862 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
863 * CPU1 to CPU2.
864 * PAGING_SEPARATOR_SECTION delimiter - separate between
865 * CPU2 non paged to CPU2 paging sec.
866 */
034846cf 867 if (!image->sec[i].data ||
a6c4fb44
MG		 868 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
869 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 870 IWL_DEBUG_FW(trans,
871 "Break since Data not valid or Empty section, sec = %d\n",
872 i);
189fa2fa 873 break;
034846cf
EH		 874 }
875
189fa2fa
EH		 876 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
877 if (ret)
878 return ret;
e2d6f4e7
EH		 879 }
880
034846cf
EH		 881 *first_ucode_section = last_read_idx;
882
e2d6f4e7
EH		 883 return 0;
884}
885
593fae3e
SM		 886static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
887{
888 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
889 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
890 &trans->dbg.fw_mon_cfg[alloc_id];
891 struct iwl_dram_data *frag;
892
893 if (!iwl_trans_dbg_ini_valid(trans))
894 return;
895
896 if (le32_to_cpu(fw_mon_cfg->buf_location) ==
897 IWL_FW_INI_LOCATION_SRAM_PATH) {
898 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
899 /* set sram monitor by enabling bit 7 */
900 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
901 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
902
903 return;
904 }
905
906 if (le32_to_cpu(fw_mon_cfg->buf_location) !=
907 IWL_FW_INI_LOCATION_DRAM_PATH ||
908 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
909 return;
910
911 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
912
913 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
914 alloc_id);
915
916 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
917 frag->physical >> MON_BUFF_SHIFT_VER2);
918 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
919 (frag->physical + frag->size - 256) >>
920 MON_BUFF_SHIFT_VER2);
921}
922
c9be849d 923void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 924{
91c28b83 925 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
69f0e505 926 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
09e350f7
LK		 927 int i;
928
a1af4c48 929 if (iwl_trans_dbg_ini_valid(trans)) {
593fae3e 930 iwl_pcie_apply_destination_ini(trans);
7a14c23d
SS		 931 return;
932 }
933
09e350f7
LK		 934 IWL_INFO(trans, "Applying debug destination %s\n",
935 get_fw_dbg_mode_string(dest->monitor_mode));
936
937 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 938 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 939 else
940 IWL_WARN(trans, "PCI should have external buffer debug\n");
941
91c28b83 942 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
09e350f7
LK		 943 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
944 u32 val = le32_to_cpu(dest->reg_ops[i].val);
945
946 switch (dest->reg_ops[i].op) {
947 case CSR_ASSIGN:
948 iwl_write32(trans, addr, val);
949 break;
950 case CSR_SETBIT:
951 iwl_set_bit(trans, addr, BIT(val));
952 break;
953 case CSR_CLEARBIT:
954 iwl_clear_bit(trans, addr, BIT(val));
955 break;
956 case PRPH_ASSIGN:
957 iwl_write_prph(trans, addr, val);
958 break;
959 case PRPH_SETBIT:
960 iwl_set_bits_prph(trans, addr, BIT(val));
961 break;
962 case PRPH_CLEARBIT:
963 iwl_clear_bits_prph(trans, addr, BIT(val));
964 break;
869f3b15
HD		 965 case PRPH_BLOCKBIT:
966 if (iwl_read_prph(trans, addr) & BIT(val)) {
967 IWL_ERR(trans,
968 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
969 val, addr);
970 goto monitor;
971 }
972 break;
09e350f7
LK		 973 default:
974 IWL_ERR(trans, "FW debug - unknown OP %d\n",
975 dest->reg_ops[i].op);
976 break;
977 }
978 }
979
869f3b15 980monitor:
69f0e505 981 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
09e350f7 982 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
69f0e505 983 fw_mon->physical >> dest->base_shift);
286ca8eb 984 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 986 (fw_mon->physical + fw_mon->size -
987 256) >> dest->end_shift);
62d7476d
EG		 988 else
989 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 990 (fw_mon->physical + fw_mon->size) >>
991 dest->end_shift);
09e350f7
LK		 992 }
993}
994
7afe3705 995static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 996 const struct fw_img *image)
cf614297 997{
189fa2fa 998 int ret = 0;
034846cf 999 int first_ucode_section;
cf614297 1000
dcab8ecd 1001 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 1002 image->is_dual_cpus ? "Dual" : "Single");
1003
dcab8ecd
EH		 1004 /* load to FW the binary non secured sections of CPU1 */
1005 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1006 if (ret)
1007 return ret;
e2d6f4e7
EH		 1008
1009 if (image->is_dual_cpus) {
189fa2fa
EH		 1010 /* set CPU2 header address */
1011 iwl_write_prph(trans,
1012 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1013 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1014
189fa2fa 1015 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1016 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1017 &first_ucode_section);
189fa2fa
EH		 1018 if (ret)
1019 return ret;
e2d6f4e7 1020 }
cf614297 1021
c2d20201
EG		 1022 /* supported for 7000 only for the moment */
1023 if (iwlwifi_mod_params.fw_monitor &&
286ca8eb 1024 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
69f0e505 1025 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 1026
69f0e505
SM		 1027 iwl_pcie_alloc_fw_monitor(trans, 0);
1028 if (fw_mon->size) {
c2d20201 1029 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
69f0e505 1030 fw_mon->physical >> 4);
c2d20201 1031 iwl_write_prph(trans, MON_BUFF_END_ADDR,
69f0e505 1032 (fw_mon->physical + fw_mon->size) >> 4);
c2d20201 1033 }
7a14c23d 1034 } else if (iwl_pcie_dbg_on(trans)) {
09e350f7 1035 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1036 }
1037
2aabdbdc
EG		 1038 iwl_enable_interrupts(trans);
1039
e12ba844 1040 /* release CPU reset */
5dd9c68a 1041 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1042
dcab8ecd
EH		 1043 return 0;
1044}
189fa2fa 1045
5dd9c68a
EG		 1046static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1047 const struct fw_img *image)
dcab8ecd
EH		 1048{
1049 int ret = 0;
1050 int first_ucode_section;
dcab8ecd
EH		 1051
1052 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1053 image->is_dual_cpus ? "Dual" : "Single");
1054
7a14c23d 1055 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 1056 iwl_pcie_apply_destination(trans);
1057
82ea7966
SS		 1058 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1059 iwl_read_prph(trans, WFPM_GP2));
1060
1061 /*
1062 * Set default value. On resume reading the values that were
1063 * zeored can provide debug data on the resume flow.
1064 * This is for debugging only and has no functional impact.
1065 */
1066 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1067
dcab8ecd
EH		 1068 /* configure the ucode to be ready to get the secured image */
1069 /* release CPU reset */
1070 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1071
1072 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1073 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1074 &first_ucode_section);
dcab8ecd
EH		 1075 if (ret)
1076 return ret;
1077
1078 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1079 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1080 &first_ucode_section);
cf614297
EG		 1081}
1082
9ad8fd0b 1083bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1084{
326477e4 1085 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1086 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1087 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1088 bool report;
727c02df 1089
326477e4
JB		 1090 if (hw_rfkill) {
1091 set_bit(STATUS_RFKILL_HW, &trans->status);
1092 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1093 } else {
1094 clear_bit(STATUS_RFKILL_HW, &trans->status);
1095 if (trans_pcie->opmode_down)
1096 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1097 }
1098
1099 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1100
326477e4
JB		 1101 if (prev != report)
1102 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1103
1104 return hw_rfkill;
1105}
1106
7ca00409
HD		 1107struct iwl_causes_list {
1108 u32 cause_num;
1109 u32 mask_reg;
1110 u8 addr;
1111};
1112
1113static struct iwl_causes_list causes_list[] = {
1114 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1115 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1116 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1117 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1118 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1119 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
ff911dca 1120 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12},
7ca00409
HD		 1121 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1122 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1123 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1124 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1125 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1126 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1127 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1128 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1129};
1130
1131static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1132{
1133 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1134 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
3681021f
JB		 1135 int i, arr_size = ARRAY_SIZE(causes_list);
1136 struct iwl_causes_list *causes = causes_list;
7ca00409
HD		 1137
1138 /*
1139 * Access all non RX causes and map them to the default irq.
1140 * In case we are missing at least one interrupt vector,
1141 * the first interrupt vector will serve non-RX and FBQ causes.
1142 */
9b58419e 1143 for (i = 0; i < arr_size; i++) {
9b58419e
GBA		 1144 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1145 iwl_clear_bit(trans, causes[i].mask_reg,
1146 causes[i].cause_num);
7ca00409
HD		 1147 }
1148}
1149
1150static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1151{
1152 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1153 u32 offset =
1154 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1155 u32 val, idx;
1156
1157 /*
1158 * The first RX queue - fallback queue, which is designated for
1159 * management frame, command responses etc, is always mapped to the
1160 * first interrupt vector. The other RX queues are mapped to
1161 * the other (N - 2) interrupt vectors.
1162 */
1163 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1164 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1165 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1166 MSIX_FH_INT_CAUSES_Q(idx - offset));
1167 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1168 }
1169 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1170
1171 val = MSIX_FH_INT_CAUSES_Q(0);
1172 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1173 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1174 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1175
1176 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1177 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1178}
1179
77c09bc8 1180void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1181{
1182 struct iwl_trans *trans = trans_pcie->trans;
1183
1184 if (!trans_pcie->msix_enabled) {
286ca8eb 1185 if (trans->trans_cfg->mq_rx_supported &&
d7270d61 1186 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1187 iwl_write_umac_prph(trans, UREG_CHICK,
1188 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1189 return;
1190 }
d7270d61
HD		 1191 /*
1192 * The IVAR table needs to be configured again after reset,
1193 * but if the device is disabled, we can't write to
1194 * prph.
1195 */
1196 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1197 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1198
1199 /*
1200 * Each cause from the causes list above and the RX causes is
1201 * represented as a byte in the IVAR table. The first nibble
1202 * represents the bound interrupt vector of the cause, the second
1203 * represents no auto clear for this cause. This will be set if its
1204 * interrupt vector is bound to serve other causes.
1205 */
1206 iwl_pcie_map_rx_causes(trans);
1207
1208 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1209}
1210
1211static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1212{
1213 struct iwl_trans *trans = trans_pcie->trans;
1214
1215 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1216
83730058
HD		 1217 if (!trans_pcie->msix_enabled)
1218 return;
1219
1220 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1221 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1222 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1223 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1224}
1225
bab3cb92 1226static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1227{
43e58856 1228 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1229
fa9f3281
EG		 1230 lockdep_assert_held(&trans_pcie->mutex);
1231
1232 if (trans_pcie->is_down)
1233 return;
1234
1235 trans_pcie->is_down = true;
1236
43e58856 1237 /* tell the device to stop sending interrupts */
ae2c30bf 1238 iwl_disable_interrupts(trans);
ae2c30bf 1239
ab6cf8e8 1240 /* device going down, Stop using ICT table */
990aa6d7 1241 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1242
1243 /*
1244 * If a HW restart happens during firmware loading,
1245 * then the firmware loading might call this function
1246 * and later it might be called again due to the
1247 * restart. So don't process again if the device is
1248 * already dead.
1249 */
31b8b343 1250 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1251 IWL_DEBUG_INFO(trans,
1252 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1253 iwl_pcie_tx_stop(trans);
9805c446 1254 iwl_pcie_rx_stop(trans);
6379103e 1255
ab6cf8e8 1256 /* Power-down device's busmaster DMA clocks */
95411d04 1257 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1258 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1259 APMG_CLK_VAL_DMA_CLK_RQT);
1260 udelay(5);
1261 }
ab6cf8e8
EG		 1262 }
1263
1264 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1265 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1266 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1267
1268 /* Stop the device, and put it in low power state */
b7aaeae4 1269 iwl_pcie_apm_stop(trans, false);
43e58856 1270
870c2a11 1271 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1272
f4a1f04a
GBA		 1273 /*
1274 * Upon stop, the IVAR table gets erased, so msi-x won't
1275 * work. This causes a bug in RF-KILL flows, since the interrupt
1276 * that enables radio won't fire on the correct irq, and the
1277 * driver won't be able to handle the interrupt.
1278 * Configure the IVAR table again after reset.
1279 */
1280 iwl_pcie_conf_msix_hw(trans_pcie);
1281
03d6c3b0
EG		 1282 /*
1283 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1284 * This is a bug in certain verions of the hardware.
1285 * Certain devices also keep sending HW RF kill interrupt all
1286 * the time, unless the interrupt is ACKed even if the interrupt
1287 * should be masked. Re-ACK all the interrupts here.
43e58856 1288 */
43e58856 1289 iwl_disable_interrupts(trans);
43e58856 1290
74fda971 1291 /* clear all status bits */
eb7ff77e
AN		 1292 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1293 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1294 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1295
1296 /*
1297 * Even if we stop the HW, we still want the RF kill
1298 * interrupt
1299 */
1300 iwl_enable_rfkill_int(trans);
1301
a6bd005f 1302 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1303 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1304}
1305
eda50cde 1306void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1307{
1308 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1309
1310 if (trans_pcie->msix_enabled) {
1311 int i;
1312
496d83ca 1313 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1314 synchronize_irq(trans_pcie->msix_entries[i].vector);
1315 } else {
1316 synchronize_irq(trans_pcie->pci_dev->irq);
1317 }
1318}
1319
a6bd005f
EG		 1320static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1321 const struct fw_img *fw, bool run_in_rfkill)
1322{
1323 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1324 bool hw_rfkill;
1325 int ret;
1326
1327 /* This may fail if AMT took ownership of the device */
1328 if (iwl_pcie_prepare_card_hw(trans)) {
1329 IWL_WARN(trans, "Exit HW not ready\n");
1330 ret = -EIO;
1331 goto out;
1332 }
1333
1334 iwl_enable_rfkill_int(trans);
1335
1336 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1337
1338 /*
1339 * We enabled the RF-Kill interrupt and the handler may very
1340 * well be running. Disable the interrupts to make sure no other
1341 * interrupt can be fired.
1342 */
1343 iwl_disable_interrupts(trans);
1344
1345 /* Make sure it finished running */
2e5d4a8f 1346 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1347
1348 mutex_lock(&trans_pcie->mutex);
1349
1350 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1351 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1352 if (hw_rfkill && !run_in_rfkill) {
1353 ret = -ERFKILL;
1354 goto out;
1355 }
1356
1357 /* Someone called stop_device, don't try to start_fw */
1358 if (trans_pcie->is_down) {
1359 IWL_WARN(trans,
1360 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1361 ret = -EIO;
a6bd005f
EG		 1362 goto out;
1363 }
1364
1365 /* make sure rfkill handshake bits are cleared */
1366 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1367 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1368 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1369
1370 /* clear (again), then enable host interrupts */
1371 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1372
1373 ret = iwl_pcie_nic_init(trans);
1374 if (ret) {
1375 IWL_ERR(trans, "Unable to init nic\n");
1376 goto out;
1377 }
1378
1379 /*
1380 * Now, we load the firmware and don't want to be interrupted, even
1381 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1382 * FH_TX interrupt which is needed to load the firmware). If the
1383 * RF-Kill switch is toggled, we will find out after having loaded
1384 * the firmware and return the proper value to the caller.
1385 */
1386 iwl_enable_fw_load_int(trans);
1387
1388 /* really make sure rfkill handshake bits are cleared */
1389 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1390 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1391
1392 /* Load the given image to the HW */
286ca8eb 1393 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1394 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1395 else
1396 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1397
1398 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1399 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1400 if (hw_rfkill && !run_in_rfkill)
1401 ret = -ERFKILL;
1402
1403out:
1404 mutex_unlock(&trans_pcie->mutex);
1405 return ret;
1406}
1407
1408static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1409{
1410 iwl_pcie_reset_ict(trans);
1411 iwl_pcie_tx_start(trans, scd_addr);
1412}
1413
326477e4
JB		 1414void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1415 bool was_in_rfkill)
1416{
1417 bool hw_rfkill;
1418
1419 /*
1420 * Check again since the RF kill state may have changed while
1421 * all the interrupts were disabled, in this case we couldn't
1422 * receive the RF kill interrupt and update the state in the
1423 * op_mode.
1424 * Don't call the op_mode if the rkfill state hasn't changed.
1425 * This allows the op_mode to call stop_device from the rfkill
1426 * notification without endless recursion. Under very rare
1427 * circumstances, we might have a small recursion if the rfkill
1428 * state changed exactly now while we were called from stop_device.
1429 * This is very unlikely but can happen and is supported.
1430 */
1431 hw_rfkill = iwl_is_rfkill_set(trans);
1432 if (hw_rfkill) {
1433 set_bit(STATUS_RFKILL_HW, &trans->status);
1434 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1435 } else {
1436 clear_bit(STATUS_RFKILL_HW, &trans->status);
1437 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1438 }
1439 if (hw_rfkill != was_in_rfkill)
1440 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1441}
1442
bab3cb92 1443static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
fa9f3281
EG		 1444{
1445 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1446 bool was_in_rfkill;
fa9f3281
EG		 1447
1448 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1449 trans_pcie->opmode_down = true;
1450 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
bab3cb92 1451 _iwl_trans_pcie_stop_device(trans);
326477e4 1452 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1453 mutex_unlock(&trans_pcie->mutex);
1454}
1455
14cfca71
JB		 1456void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1457{
fa9f3281
EG		 1458 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1459 IWL_TRANS_GET_PCIE_TRANS(trans);
1460
1461 lockdep_assert_held(&trans_pcie->mutex);
1462
326477e4
JB		 1463 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1464 state ? "disabled" : "enabled");
77c09bc8 1465 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
286ca8eb 1466 if (trans->trans_cfg->gen2)
bab3cb92 1467 _iwl_trans_pcie_gen2_stop_device(trans);
77c09bc8 1468 else
bab3cb92 1469 _iwl_trans_pcie_stop_device(trans);
77c09bc8 1470 }
ab6cf8e8
EG		 1471}
1472
e5f3f215
HD		 1473void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1474 bool test, bool reset)
2dd4f9f7 1475{
2dd4f9f7 1476 iwl_disable_interrupts(trans);
debff618
JB		 1477
1478 /*
1479 * in testing mode, the host stays awake and the
1480 * hardware won't be reset (not even partially)
1481 */
1482 if (test)
1483 return;
1484
ddaf5a5b
JB		 1485 iwl_pcie_disable_ict(trans);
1486
2e5d4a8f 1487 iwl_pcie_synchronize_irqs(trans);
33b56af1 1488
2dd4f9f7 1489 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 1490 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1491 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
ddaf5a5b 1492
23ae6128 1493 if (reset) {
6dfb36c8
EP		 1494 /*
1495 * reset TX queues -- some of their registers reset during S3
1496 * so if we don't reset everything here the D3 image would try
1497 * to execute some invalid memory upon resume
1498 */
1499 iwl_trans_pcie_tx_reset(trans);
1500 }
ddaf5a5b
JB		 1501
1502 iwl_pcie_set_pwr(trans, true);
1503}
1504
e5f3f215
HD		 1505static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1506 bool reset)
1507{
1508 int ret;
1509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1510
1511 /*
1512 * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW.
1513 */
1514 if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
1515 /* Enable persistence mode to avoid reset */
1516 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1517 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1518 }
1519
1520 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1521 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1522 UREG_DOORBELL_TO_ISR6_SUSPEND);
1523
1524 ret = wait_event_timeout(trans_pcie->sx_waitq,
1525 trans_pcie->sx_complete, 2 * HZ);
1526 /*
1527 * Invalidate it toward resume.
1528 */
1529 trans_pcie->sx_complete = false;
1530
1531 if (!ret) {
1532 IWL_ERR(trans, "Timeout entering D3\n");
1533 return -ETIMEDOUT;
1534 }
1535 }
1536 iwl_pcie_d3_complete_suspend(trans, test, reset);
1537
1538 return 0;
1539}
1540
ddaf5a5b 1541static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1542 enum iwl_d3_status *status,
23ae6128 1543 bool test, bool reset)
ddaf5a5b 1544{
d7270d61 1545 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1546 u32 val;
1547 int ret;
1548
debff618
JB		 1549 if (test) {
1550 iwl_enable_interrupts(trans);
1551 *status = IWL_D3_STATUS_ALIVE;
e5f3f215 1552 goto out;
debff618
JB		 1553 }
1554
a8cbb46f 1555 iwl_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 1556 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b 1557
7d34a7d7 1558 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 1559 if (ret)
ddaf5a5b 1560 return ret;
ddaf5a5b 1561
f98ad635
EG		 1562 /*
1563 * Reconfigure IVAR table in case of MSIX or reset ict table in
1564 * MSI mode since HW reset erased it.
1565 * Also enables interrupts - none will happen as
1566 * the device doesn't know we're waking it up, only when
1567 * the opmode actually tells it after this call.
1568 */
1569 iwl_pcie_conf_msix_hw(trans_pcie);
1570 if (!trans_pcie->msix_enabled)
1571 iwl_pcie_reset_ict(trans);
1572 iwl_enable_interrupts(trans);
1573
a3ead656
EG		 1574 iwl_pcie_set_pwr(trans, false);
1575
23ae6128 1576 if (!reset) {
6dfb36c8 1577 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1578 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6dfb36c8
EP		 1579 } else {
1580 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1581
6dfb36c8
EP		 1582 ret = iwl_pcie_rx_init(trans);
1583 if (ret) {
1584 IWL_ERR(trans,
1585 "Failed to resume the device (RX reset)\n");
1586 return ret;
1587 }
ddaf5a5b
JB		 1588 }
1589
82ea7966 1590 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1591 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1592
a3ead656
EG		 1593 val = iwl_read32(trans, CSR_RESET);
1594 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1595 *status = IWL_D3_STATUS_RESET;
1596 else
1597 *status = IWL_D3_STATUS_ALIVE;
1598
e5f3f215
HD		 1599out:
1600 if (*status == IWL_D3_STATUS_ALIVE &&
1601 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1602 trans_pcie->sx_complete = false;
1603 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1604 UREG_DOORBELL_TO_ISR6_RESUME);
1605
1606 ret = wait_event_timeout(trans_pcie->sx_waitq,
1607 trans_pcie->sx_complete, 2 * HZ);
1608 /*
1609 * Invalidate it toward next suspend.
1610 */
1611 trans_pcie->sx_complete = false;
1612
1613 if (!ret) {
1614 IWL_ERR(trans, "Timeout exiting D3\n");
1615 return -ETIMEDOUT;
1616 }
1617 }
ddaf5a5b 1618 return 0;
2dd4f9f7
JB		 1619}
1620
0c18714a
LC		 1621static void
1622iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1623 struct iwl_trans *trans,
1624 const struct iwl_cfg_trans_params *cfg_trans)
2e5d4a8f
HD		 1625{
1626 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1627 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1628 u16 pci_cmd;
2e5d4a8f 1629
0c18714a 1630 if (!cfg_trans->mq_rx_supported)
06f4b081
SS		 1631 goto enable_msi;
1632
ab1068d6 1633 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1634 for (i = 0; i < max_irqs; i++)
1635 trans_pcie->msix_entries[i].entry = i;
496d83ca 1636
06f4b081
SS		 1637 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1638 MSIX_MIN_INTERRUPT_VECTORS,
1639 max_irqs);
1640 if (num_irqs < 0) {
2e5d4a8f 1641 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1642 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1643 num_irqs);
1644 goto enable_msi;
1645 }
1646 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1647
06f4b081
SS		 1648 IWL_DEBUG_INFO(trans,
1649 "MSI-X enabled. %d interrupt vectors were allocated\n",
1650 num_irqs);
1651
1652 /*
1653 * In case the OS provides fewer interrupts than requested, different
1654 * causes will share the same interrupt vector as follows:
1655 * One interrupt less: non rx causes shared with FBQ.
1656 * Two interrupts less: non rx causes shared with FBQ and RSS.
1657 * More than two interrupts: we will use fewer RSS queues.
1658 */
ab1068d6 1659 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1660 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1661 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1662 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1663 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1664 trans_pcie->trans->num_rx_queues = num_irqs;
1665 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1666 } else {
1667 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1668 }
ab1068d6 1669 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1670
06f4b081
SS		 1671 trans_pcie->alloc_vecs = num_irqs;
1672 trans_pcie->msix_enabled = true;
1673 return;
1674
1675enable_msi:
1676 ret = pci_enable_msi(pdev);
1677 if (ret) {
1678 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1679 /* enable rfkill interrupt: hw bug w/a */
1680 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1681 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1682 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1683 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1684 }
1685 }
1686}
1687
7c8d91eb
HD		 1688static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1689{
1690 int iter_rx_q, i, ret, cpu, offset;
1691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1692
1693 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1694 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1695 offset = 1 + i;
1696 for (; i < iter_rx_q ; i++) {
1697 /*
1698 * Get the cpu prior to the place to search
1699 * (i.e. return will be > i - 1).
1700 */
1701 cpu = cpumask_next(i - offset, cpu_online_mask);
1702 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1703 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1704 &trans_pcie->affinity_mask[i]);
1705 if (ret)
1706 IWL_ERR(trans_pcie->trans,
1707 "Failed to set affinity mask for IRQ %d\n",
1708 i);
1709 }
1710}
1711
2e5d4a8f
HD		 1712static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1713 struct iwl_trans_pcie *trans_pcie)
1714{
496d83ca 1715 int i;
2e5d4a8f 1716
496d83ca 1717 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1718 int ret;
5a41a86c 1719 struct msix_entry *msix_entry;
64fa3aff
SD		 1720 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1721
1722 if (!qname)
1723 return -ENOMEM;
5a41a86c
SD		 1724
1725 msix_entry = &trans_pcie->msix_entries[i];
1726 ret = devm_request_threaded_irq(&pdev->dev,
1727 msix_entry->vector,
1728 iwl_pcie_msix_isr,
1729 (i == trans_pcie->def_irq) ?
1730 iwl_pcie_irq_msix_handler :
1731 iwl_pcie_irq_rx_msix_handler,
1732 IRQF_SHARED,
64fa3aff 1733 qname,
5a41a86c 1734 msix_entry);
2e5d4a8f 1735 if (ret) {
2e5d4a8f
HD		 1736 IWL_ERR(trans_pcie->trans,
1737 "Error allocating IRQ %d\n", i);
5a41a86c 1738
2e5d4a8f
HD		 1739 return ret;
1740 }
1741 }
7c8d91eb 1742 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1743
1744 return 0;
1745}
1746
44f61b5c 1747static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
e6bb4c9c 1748{
44f61b5c 1749 u32 hpm, wprot;
fa9f3281 1750
286ca8eb 1751 switch (trans->trans_cfg->device_family) {
44f61b5c
SM		 1752 case IWL_DEVICE_FAMILY_9000:
1753 wprot = PREG_PRPH_WPROT_9000;
1754 break;
1755 case IWL_DEVICE_FAMILY_22000:
1756 wprot = PREG_PRPH_WPROT_22000;
1757 break;
1758 default:
1759 return 0;
ebb7678d 1760 }
a6c684ee 1761
ea695b7c 1762 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
8954e1eb 1763 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
44f61b5c 1764 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
ea695b7c 1765
44f61b5c 1766 if (wprot_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1767 IWL_ERR(trans,
1768 "Error, can not clear persistence bit\n");
1769 return -EPERM;
1770 }
ea695b7c
ST		 1771 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1772 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1773 }
1774
44f61b5c
SM		 1775 return 0;
1776}
1777
0df36b90
LC		 1778static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1779{
1780 int ret;
1781
1782 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1783 if (ret < 0)
1784 return ret;
1785
1786 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1787 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1788 udelay(20);
1789 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1790 HPM_HIPM_GEN_CFG_CR_PG_EN |
1791 HPM_HIPM_GEN_CFG_CR_SLP_EN);
1792 udelay(20);
1793 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1794 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1795
1796 iwl_trans_pcie_sw_reset(trans);
1797
1798 return 0;
1799}
1800
bab3cb92 1801static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
44f61b5c
SM		 1802{
1803 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1804 int err;
1805
1806 lockdep_assert_held(&trans_pcie->mutex);
1807
1808 err = iwl_pcie_prepare_card_hw(trans);
1809 if (err) {
1810 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1811 return err;
1812 }
1813
1814 err = iwl_trans_pcie_clear_persistence_bit(trans);
1815 if (err)
1816 return err;
1817
870c2a11 1818 iwl_trans_pcie_sw_reset(trans);
2997494f 1819
0df36b90 1820 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
7897dfa2 1821 trans->trans_cfg->integrated) {
0df36b90
LC		 1822 err = iwl_pcie_gen2_force_power_gating(trans);
1823 if (err)
1824 return err;
1825 }
1826
52b6e168
EG		 1827 err = iwl_pcie_apm_init(trans);
1828 if (err)
1829 return err;
a6c684ee 1830
2e5d4a8f 1831 iwl_pcie_init_msix(trans_pcie);
83730058 1832
226c02ca
EG		 1833 /* From now on, the op_mode will be kept updated about RF kill state */
1834 iwl_enable_rfkill_int(trans);
1835
326477e4
JB		 1836 trans_pcie->opmode_down = false;
1837
fa9f3281
EG		 1838 /* Set is_down to false here so that...*/
1839 trans_pcie->is_down = false;
1840
727c02df 1841 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1842 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1843
a8b691e6 1844 return 0;
e6bb4c9c
EG		 1845}
1846
bab3cb92 1847static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
fa9f3281
EG		 1848{
1849 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1850 int ret;
1851
1852 mutex_lock(&trans_pcie->mutex);
bab3cb92 1853 ret = _iwl_trans_pcie_start_hw(trans);
fa9f3281
EG		 1854 mutex_unlock(&trans_pcie->mutex);
1855
1856 return ret;
1857}
1858
a4082843 1859static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1860{
20d3b647 1861 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1862
fa9f3281
EG		 1863 mutex_lock(&trans_pcie->mutex);
1864
a4082843 1865 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1866 iwl_disable_interrupts(trans);
ee7d737c 1867
b7aaeae4 1868 iwl_pcie_apm_stop(trans, true);
cc56feb2 1869
218733cf 1870 iwl_disable_interrupts(trans);
1df06bdc 1871
8d96bb61 1872 iwl_pcie_disable_ict(trans);
33b56af1 1873
fa9f3281 1874 mutex_unlock(&trans_pcie->mutex);
33b56af1 1875
2e5d4a8f 1876 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1877}
1878
03905495
EG		 1879static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1880{
05f5b97e 1881 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1882}
1883
1884static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1885{
05f5b97e 1886 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1887}
1888
1889static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1890{
05f5b97e 1891 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1892}
1893
84fb372c
SS		 1894static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1895{
3681021f 1896 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
84fb372c
SS		 1897 return 0x00FFFFFF;
1898 else
1899 return 0x000FFFFF;
1900}
1901
6a06b6c1
EG		 1902static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1903{
84fb372c
SS		 1904 u32 mask = iwl_trans_pcie_prph_msk(trans);
1905
f9477c17 1906 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1907 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1908 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1909}
1910
1911static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1912 u32 val)
1913{
84fb372c
SS		 1914 u32 mask = iwl_trans_pcie_prph_msk(trans);
1915
6a06b6c1 1916 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1917 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1918 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1919}
1920
c6f600fc 1921static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1922 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1923{
1924 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1925
1926 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1927 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1928 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1929 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1930 trans_pcie->n_no_reclaim_cmds = 0;
1931 else
1932 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1933 if (trans_pcie->n_no_reclaim_cmds)
1934 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1935 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1936
6c4fbcbc
EG		 1937 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1938 trans_pcie->rx_page_order =
1939 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
80084e35
JB		 1940 trans_pcie->rx_buf_bytes =
1941 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
cfdc20ef
JB		 1942 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1943 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1944 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
7c5ba4a8 1945
046db346 1946 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1947 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1948 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1949
21cb3222
JB		 1950 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1951 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1952
39bdb17e
SD		 1953 trans->command_groups = trans_cfg->command_groups;
1954 trans->command_groups_size = trans_cfg->command_groups_size;
1955
f14d6b39
JB		 1956 /* Initialize NAPI here - it should be before registering to mac80211
1957 * in the opmode but after the HW struct is allocated.
1958 * As this function may be called again in some corner cases don't
1959 * do anything if NAPI was already initialized.
1960 */
bce97731 1961 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1962 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1963}
1964
d1ff5253 1965void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1966{
20d3b647 1967 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1968 int i;
a42a1844 1969
2e5d4a8f 1970 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1971
286ca8eb 1972 if (trans->trans_cfg->gen2)
13a3a390
SS		 1973 iwl_pcie_gen2_tx_free(trans);
1974 else
1975 iwl_pcie_tx_free(trans);
9805c446 1976 iwl_pcie_rx_free(trans);
6379103e 1977
10a54d81
LC		 1978 if (trans_pcie->rba.alloc_wq) {
1979 destroy_workqueue(trans_pcie->rba.alloc_wq);
1980 trans_pcie->rba.alloc_wq = NULL;
1981 }
1982
2e5d4a8f 1983 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1984 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1985 irq_set_affinity_hint(
1986 trans_pcie->msix_entries[i].vector,
1987 NULL);
7c8d91eb 1988 }
2e5d4a8f 1989
2e5d4a8f
HD		 1990 trans_pcie->msix_enabled = false;
1991 } else {
2e5d4a8f 1992 iwl_pcie_free_ict(trans);
2e5d4a8f 1993 }
a42a1844 1994
c2d20201
EG		 1995 iwl_pcie_free_fw_monitor(trans);
1996
6eb5e529
EG		 1997 for_each_possible_cpu(i) {
1998 struct iwl_tso_hdr_page *p =
1999 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
2000
2001 if (p->page)
2002 __free_page(p->page);
2003 }
2004
2005 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 2006 mutex_destroy(&trans_pcie->mutex);
7b501d10 2007 iwl_trans_free(trans);
34c1b7ba
EG		 2008}
2009
47107e84
DF		 2010static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2011{
47107e84 2012 if (state)
eb7ff77e 2013 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 2014 else
eb7ff77e 2015 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 2016}
2017
49564a80
LC		 2018struct iwl_trans_pcie_removal {
2019 struct pci_dev *pdev;
2020 struct work_struct work;
2021};
2022
2023static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2024{
2025 struct iwl_trans_pcie_removal *removal =
2026 container_of(wk, struct iwl_trans_pcie_removal, work);
2027 struct pci_dev *pdev = removal->pdev;
aba1e632 2028 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
49564a80
LC		 2029
2030 dev_err(&pdev->dev, "Device gone - attempting removal\n");
2031 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2032 pci_lock_rescan_remove();
2033 pci_dev_put(pdev);
2034 pci_stop_and_remove_bus_device(pdev);
2035 pci_unlock_rescan_remove();
2036
2037 kfree(removal);
2038 module_put(THIS_MODULE);
2039}
2040
23ba9340
EG		 2041static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2042 unsigned long *flags)
7a65d170
EG		 2043{
2044 int ret;
cfb4e624
JB		 2045 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2046
2047 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 2048
fc8a350d 2049 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2050 goto out;
2051
7a65d170 2052 /* this bit wakes up the NIC */
e139dc4a 2053 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 2054 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
286ca8eb 2055 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 2056 udelay(2);
7a65d170
EG		 2057
2058 /*
2059 * These bits say the device is running, and should keep running for
2060 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2061 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 2062 * HW with volatile SRAM must save/restore contents to/from
2063 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 2064 * Each direction takes approximately 1/4 millisecond; with this
2065 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2066 * series of register accesses are expected (e.g. reading Event Log),
2067 * to keep device from sleeping.
2068 *
2069 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2070 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 2071 * is just for hardware register access; but GP1 MAC_SLEEP
2072 * check is a good idea before accessing the SRAM of HW with
2073 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2074 *
2075 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2076 * and do not save/restore SRAM when power cycling.
2077 */
2078 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 2079 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2080 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
7a65d170
EG		 2081 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2082 if (unlikely(ret < 0)) {
49564a80
LC		 2083 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2084
23ba9340
EG		 2085 WARN_ONCE(1,
2086 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2087 cntrl);
2088
2089 iwl_trans_pcie_dump_regs(trans);
2090
2091 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2092 struct iwl_trans_pcie_removal *removal;
2093
f60c9e59 2094 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
49564a80
LC		 2095 goto err;
2096
2097 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2098
2099 /*
2100 * get a module reference to avoid doing this
2101 * while unloading anyway and to avoid
2102 * scheduling a work with code that's being
2103 * removed.
2104 */
2105 if (!try_module_get(THIS_MODULE)) {
2106 IWL_ERR(trans,
2107 "Module is being unloaded - abort\n");
2108 goto err;
2109 }
2110
2111 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2112 if (!removal) {
2113 module_put(THIS_MODULE);
2114 goto err;
2115 }
2116 /*
2117 * we don't need to clear this flag, because
2118 * the trans will be freed and reallocated.
2119 */
f60c9e59 2120 set_bit(STATUS_TRANS_DEAD, &trans->status);
49564a80
LC		 2121
2122 removal->pdev = to_pci_dev(trans->dev);
2123 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2124 pci_dev_get(removal->pdev);
2125 schedule_work(&removal->work);
2126 } else {
2127 iwl_write32(trans, CSR_RESET,
2128 CSR_RESET_REG_FLAG_FORCE_NMI);
2129 }
2130
2131err:
23ba9340
EG		 2132 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2133 return false;
7a65d170
EG		 2134 }
2135
b9439491 2136out:
e56b04ef
LE		 2137 /*
2138 * Fool sparse by faking we release the lock - sparse will
2139 * track nic_access anyway.
2140 */
cfb4e624 2141 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2142 return true;
2143}
2144
e56b04ef
LE		 2145static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2146 unsigned long *flags)
7a65d170 2147{
cfb4e624 2148 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2149
cfb4e624 2150 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2151
2152 /*
2153 * Fool sparse by faking we acquiring the lock - sparse will
2154 * track nic_access anyway.
2155 */
cfb4e624 2156 __acquire(&trans_pcie->reg_lock);
e56b04ef 2157
fc8a350d 2158 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2159 goto out;
2160
e139dc4a 2161 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 2162 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2163 /*
2164 * Above we read the CSR_GP_CNTRL register, which will flush
2165 * any previous writes, but we need the write that clears the
2166 * MAC_ACCESS_REQ bit to be performed before any other writes
2167 * scheduled on different CPUs (after we drop reg_lock).
2168 */
b9439491 2169out:
cfb4e624 2170 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2171}
2172
4fd442db
EG		 2173static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2174 void *buf, int dwords)
2175{
2176 unsigned long flags;
2177 int offs, ret = 0;
2178 u32 *vals = buf;
2179
23ba9340 2180 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2181 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2182 for (offs = 0; offs < dwords; offs++)
2183 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2184 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2185 } else {
2186 ret = -EBUSY;
2187 }
4fd442db
EG		 2188 return ret;
2189}
2190
2191static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2192 const void *buf, int dwords)
4fd442db
EG		 2193{
2194 unsigned long flags;
2195 int offs, ret = 0;
bf0fd5da 2196 const u32 *vals = buf;
4fd442db 2197
23ba9340 2198 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2199 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2200 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2201 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2202 vals ? vals[offs] : 0);
e56b04ef 2203 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2204 } else {
2205 ret = -EBUSY;
2206 }
4fd442db
EG		 2207 return ret;
2208}
7a65d170 2209
7f1fe1d4
LC		 2210static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2211 u32 *val)
2212{
2213 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2214 ofs, val);
2215}
2216
e0b8d405
EG		 2217static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2218 unsigned long txqs,
2219 bool freeze)
2220{
2221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2222 int queue;
2223
2224 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2225 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2226 unsigned long now;
2227
2228 spin_lock_bh(&txq->lock);
2229
2230 now = jiffies;
2231
2232 if (txq->frozen == freeze)
2233 goto next_queue;
2234
2235 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2236 freeze ? "Freezing" : "Waking", queue);
2237
2238 txq->frozen = freeze;
2239
bb98ecd4 2240 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2241 goto next_queue;
2242
2243 if (freeze) {
2244 if (unlikely(time_after(now,
2245 txq->stuck_timer.expires))) {
2246 /*
2247 * The timer should have fired, maybe it is
2248 * spinning right now on the lock.
2249 */
2250 goto next_queue;
2251 }
2252 /* remember how long until the timer fires */
2253 txq->frozen_expiry_remainder =
2254 txq->stuck_timer.expires - now;
2255 del_timer(&txq->stuck_timer);
2256 goto next_queue;
2257 }
2258
2259 /*
2260 * Wake a non-empty queue -> arm timer with the
2261 * remainder before it froze
2262 */
2263 mod_timer(&txq->stuck_timer,
2264 now + txq->frozen_expiry_remainder);
2265
2266next_queue:
2267 spin_unlock_bh(&txq->lock);
2268 }
2269}
2270
0cd58eaa
EG		 2271static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2272{
2273 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2274 int i;
2275
286ca8eb 2276 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2277 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2278
2279 if (i == trans_pcie->cmd_queue)
2280 continue;
2281
2282 spin_lock_bh(&txq->lock);
2283
2284 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2285 txq->block--;
2286 if (!txq->block) {
2287 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2288 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2289 }
2290 } else if (block) {
2291 txq->block++;
2292 }
2293
2294 spin_unlock_bh(&txq->lock);
2295 }
2296}
2297
5f178cd2
EG		 2298#define IWL_FLUSH_WAIT_MS 2000
2299
38398efb
SS		 2300void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2301{
afb84431
EG		 2302 u32 txq_id = txq->id;
2303 u32 status;
2304 bool active;
2305 u8 fifo;
38398efb 2306
286ca8eb 2307 if (trans->trans_cfg->use_tfh) {
afb84431
EG		 2308 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2309 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2310 /* TODO: access new SCD registers and dump them */
2311 return;
38398efb 2312 }
afb84431
EG		 2313
2314 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2315 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2316 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2317
2318 IWL_ERR(trans,
2319 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2320 txq_id, active ? "" : "in", fifo,
2321 jiffies_to_msecs(txq->wd_timeout),
2322 txq->read_ptr, txq->write_ptr,
2323 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
286ca8eb
LC		 2324 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2325 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2326 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2327 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2328}
2329
92536c96
SS		 2330static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2331 struct iwl_trans_rxq_dma_data *data)
2332{
2333 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2334
2335 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2336 return -EINVAL;
2337
2338 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2339 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2340 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2341 data->fr_bd_wid = 0;
2342
2343 return 0;
2344}
2345
d6d517b7 2346static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2347{
8ad71bef 2348 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2349 struct iwl_txq *txq;
5f178cd2 2350 unsigned long now = jiffies;
2ae48edc 2351 bool overflow_tx;
d6d517b7
SS		 2352 u8 wr_ptr;
2353
2b3fae66 2354 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2355 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2356 return -ENODEV;
2b3fae66 2357
d6d517b7
SS		 2358 if (!test_bit(txq_idx, trans_pcie->queue_used))
2359 return -EINVAL;
2360
2361 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2362 txq = trans_pcie->txq[txq_idx];
2ae48edc
SS		 2363
2364 spin_lock_bh(&txq->lock);
2365 overflow_tx = txq->overflow_tx ||
2366 !skb_queue_empty(&txq->overflow_q);
2367 spin_unlock_bh(&txq->lock);
2368
6aa7de05 2369 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2370
2ae48edc
SS		 2371 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2372 overflow_tx) &&
d6d517b7
SS		 2373 !time_after(jiffies,
2374 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2375 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2376
2ae48edc
SS		 2377 /*
2378 * If write pointer moved during the wait, warn only
2379 * if the TX came from op mode. In case TX came from
2380 * trans layer (overflow TX) don't warn.
2381 */
2382 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2383 "WR pointer moved while flushing %d -> %d\n",
2384 wr_ptr, write_ptr))
2385 return -ETIMEDOUT;
2ae48edc
SS		 2386 wr_ptr = write_ptr;
2387
d6d517b7 2388 usleep_range(1000, 2000);
2ae48edc
SS		 2389
2390 spin_lock_bh(&txq->lock);
2391 overflow_tx = txq->overflow_tx ||
2392 !skb_queue_empty(&txq->overflow_q);
2393 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2394 }
2395
2396 if (txq->read_ptr != txq->write_ptr) {
2397 IWL_ERR(trans,
2398 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2399 iwl_trans_pcie_log_scd_error(trans, txq);
2400 return -ETIMEDOUT;
2401 }
2402
2403 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2404
2405 return 0;
2406}
2407
2408static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2409{
2410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2411 int cnt;
5f178cd2
EG		 2412 int ret = 0;
2413
2414 /* waiting for all the tx frames complete might take a while */
79b6c8fe 2415 for (cnt = 0;
286ca8eb 2416 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2417 cnt++) {
fa1a91fd 2418
9ba1947a 2419 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2420 continue;
3cafdbe6
EG		 2421 if (!test_bit(cnt, trans_pcie->queue_used))
2422 continue;
2423 if (!(BIT(cnt) & txq_bm))
2424 continue;
748fa67c 2425
d6d517b7
SS		 2426 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2427 if (ret)
5f178cd2 2428 break;
5f178cd2 2429 }
1c3fea82 2430
5f178cd2
EG		 2431 return ret;
2432}
2433
e139dc4a
LE		 2434static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2435 u32 mask, u32 value)
2436{
e56b04ef 2437 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2438 unsigned long flags;
2439
e56b04ef 2440 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2441 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2442 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2443}
2444
ff620849
EG		 2445static const char *get_csr_string(int cmd)
2446{
d9fb6465 2447#define IWL_CMD(x) case x: return #x
ff620849
EG		 2448 switch (cmd) {
2449 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2450 IWL_CMD(CSR_INT_COALESCING);
2451 IWL_CMD(CSR_INT);
2452 IWL_CMD(CSR_INT_MASK);
2453 IWL_CMD(CSR_FH_INT_STATUS);
2454 IWL_CMD(CSR_GPIO_IN);
2455 IWL_CMD(CSR_RESET);
2456 IWL_CMD(CSR_GP_CNTRL);
2457 IWL_CMD(CSR_HW_REV);
2458 IWL_CMD(CSR_EEPROM_REG);
2459 IWL_CMD(CSR_EEPROM_GP);
2460 IWL_CMD(CSR_OTP_GP_REG);
2461 IWL_CMD(CSR_GIO_REG);
2462 IWL_CMD(CSR_GP_UCODE_REG);
2463 IWL_CMD(CSR_GP_DRIVER_REG);
2464 IWL_CMD(CSR_UCODE_DRV_GP1);
2465 IWL_CMD(CSR_UCODE_DRV_GP2);
2466 IWL_CMD(CSR_LED_REG);
2467 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2468 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2469 IWL_CMD(CSR_ANA_PLL_CFG);
2470 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2471 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2472 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2473 default:
2474 return "UNKNOWN";
2475 }
d9fb6465 2476#undef IWL_CMD
ff620849
EG		 2477}
2478
990aa6d7 2479void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2480{
2481 int i;
2482 static const u32 csr_tbl[] = {
2483 CSR_HW_IF_CONFIG_REG,
2484 CSR_INT_COALESCING,
2485 CSR_INT,
2486 CSR_INT_MASK,
2487 CSR_FH_INT_STATUS,
2488 CSR_GPIO_IN,
2489 CSR_RESET,
2490 CSR_GP_CNTRL,
2491 CSR_HW_REV,
2492 CSR_EEPROM_REG,
2493 CSR_EEPROM_GP,
2494 CSR_OTP_GP_REG,
2495 CSR_GIO_REG,
2496 CSR_GP_UCODE_REG,
2497 CSR_GP_DRIVER_REG,
2498 CSR_UCODE_DRV_GP1,
2499 CSR_UCODE_DRV_GP2,
2500 CSR_LED_REG,
2501 CSR_DRAM_INT_TBL_REG,
2502 CSR_GIO_CHICKEN_BITS,
2503 CSR_ANA_PLL_CFG,
a812cba9 2504 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2505 CSR_HW_REV_WA_REG,
2506 CSR_DBG_HPET_MEM_REG
2507 };
2508 IWL_ERR(trans, "CSR values:\n");
2509 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2510 "CSR_INT_PERIODIC_REG)\n");
2511 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2512 IWL_ERR(trans, " %25s: 0X%08x\n",
2513 get_csr_string(csr_tbl[i]),
1042db2a 2514 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2515 }
2516}
2517
87e5666c
EG		 2518#ifdef CONFIG_IWLWIFI_DEBUGFS
2519/* create and remove of files */
2520#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
cf5d5663
GKH		 2521 debugfs_create_file(#name, mode, parent, trans, \
2522 &iwl_dbgfs_##name##_ops); \
87e5666c
EG		 2523} while (0)
2524
2525/* file operation */
87e5666c 2526#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2527static const struct file_operations iwl_dbgfs_##name##_ops = { \
2528 .read = iwl_dbgfs_##name##_read, \
234e3405 2529 .open = simple_open, \
87e5666c
EG		 2530 .llseek = generic_file_llseek, \
2531};
2532
16db88ba 2533#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2534static const struct file_operations iwl_dbgfs_##name##_ops = { \
2535 .write = iwl_dbgfs_##name##_write, \
234e3405 2536 .open = simple_open, \
16db88ba
EG		 2537 .llseek = generic_file_llseek, \
2538};
2539
87e5666c 2540#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2541static const struct file_operations iwl_dbgfs_##name##_ops = { \
2542 .write = iwl_dbgfs_##name##_write, \
2543 .read = iwl_dbgfs_##name##_read, \
234e3405 2544 .open = simple_open, \
87e5666c
EG		 2545 .llseek = generic_file_llseek, \
2546};
2547
df67a1be
JB		 2548struct iwl_dbgfs_tx_queue_priv {
2549 struct iwl_trans *trans;
2550};
2551
2552struct iwl_dbgfs_tx_queue_state {
2553 loff_t pos;
2554};
2555
2556static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
8ad71bef 2557{
df67a1be
JB		 2558 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2559 struct iwl_dbgfs_tx_queue_state *state;
2560
2561 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2562 return NULL;
2563
2564 state = kmalloc(sizeof(*state), GFP_KERNEL);
2565 if (!state)
2566 return NULL;
2567 state->pos = *pos;
2568 return state;
2569}
2570
2571static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2572 void *v, loff_t *pos)
2573{
2574 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2575 struct iwl_dbgfs_tx_queue_state *state = v;
2576
2577 *pos = ++state->pos;
2578
2579 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2580 return NULL;
2581
2582 return state;
2583}
2584
2585static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2586{
2587 kfree(v);
2588}
2589
2590static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2591{
2592 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2593 struct iwl_dbgfs_tx_queue_state *state = v;
2594 struct iwl_trans *trans = priv->trans;
8ad71bef 2595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
df67a1be
JB		 2596 struct iwl_txq *txq = trans_pcie->txq[state->pos];
2597
2598 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2599 (unsigned int)state->pos,
2600 !!test_bit(state->pos, trans_pcie->queue_used),
2601 !!test_bit(state->pos, trans_pcie->queue_stopped));
2602 if (txq)
2603 seq_printf(seq,
95a9e44f 2604 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
df67a1be 2605 txq->read_ptr, txq->write_ptr,
95a9e44f
JB		 2606 txq->need_update, txq->frozen,
2607 txq->n_window, txq->ampdu);
df67a1be
JB		 2608 else
2609 seq_puts(seq, "(unallocated)");
1745e440 2610
df67a1be
JB		 2611 if (state->pos == trans_pcie->cmd_queue)
2612 seq_puts(seq, " (HCMD)");
2613 seq_puts(seq, "\n");
87e5666c 2614
df67a1be
JB		 2615 return 0;
2616}
f9e75447 2617
df67a1be
JB		 2618static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2619 .start = iwl_dbgfs_tx_queue_seq_start,
2620 .next = iwl_dbgfs_tx_queue_seq_next,
2621 .stop = iwl_dbgfs_tx_queue_seq_stop,
2622 .show = iwl_dbgfs_tx_queue_seq_show,
2623};
2624
2625static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2626{
2627 struct iwl_dbgfs_tx_queue_priv *priv;
2628
2629 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2630 sizeof(*priv));
2631
2632 if (!priv)
87e5666c
EG		 2633 return -ENOMEM;
2634
df67a1be
JB		 2635 priv->trans = inode->i_private;
2636 return 0;
87e5666c
EG		 2637}
2638
2639static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2640 char __user *user_buf,
2641 size_t count, loff_t *ppos)
2642{
5a878bf6 2643 struct iwl_trans *trans = file->private_data;
20d3b647 2644 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2645 char *buf;
2646 int pos = 0, i, ret;
eb3dc36e 2647 size_t bufsz;
78485054
SS		 2648
2649 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2650
2651 if (!trans_pcie->rxq)
2652 return -EAGAIN;
2653
2654 buf = kzalloc(bufsz, GFP_KERNEL);
2655 if (!buf)
2656 return -ENOMEM;
2657
2658 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2659 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2660
2661 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2662 i);
2663 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2664 rxq->read);
2665 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2666 rxq->write);
2667 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2668 rxq->write_actual);
2669 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2670 rxq->need_update);
2671 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2672 rxq->free_count);
2673 if (rxq->rb_stts) {
0307c839
GBA		 2674 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2675 rxq));
78485054
SS		 2676 pos += scnprintf(buf + pos, bufsz - pos,
2677 "\tclosed_rb_num: %u\n",
0307c839 2678 r & 0x0FFF);
78485054
SS		 2679 } else {
2680 pos += scnprintf(buf + pos, bufsz - pos,
2681 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2682 }
87e5666c 2683 }
78485054
SS		 2684 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2685 kfree(buf);
2686
2687 return ret;
87e5666c
EG		 2688}
2689
1f7b6172
EG		 2690static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2691 char __user *user_buf,
20d3b647
JB		 2692 size_t count, loff_t *ppos)
2693{
1f7b6172 2694 struct iwl_trans *trans = file->private_data;
20d3b647 2695 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2696 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2697
2698 int pos = 0;
2699 char *buf;
2700 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2701 ssize_t ret;
2702
2703 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2704 if (!buf)
1f7b6172 2705 return -ENOMEM;
1f7b6172
EG		 2706
2707 pos += scnprintf(buf + pos, bufsz - pos,
2708 "Interrupt Statistics Report:\n");
2709
2710 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2711 isr_stats->hw);
2712 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2713 isr_stats->sw);
2714 if (isr_stats->sw || isr_stats->hw) {
2715 pos += scnprintf(buf + pos, bufsz - pos,
2716 "\tLast Restarting Code: 0x%X\n",
2717 isr_stats->err_code);
2718 }
2719#ifdef CONFIG_IWLWIFI_DEBUG
2720 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2721 isr_stats->sch);
2722 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2723 isr_stats->alive);
2724#endif
2725 pos += scnprintf(buf + pos, bufsz - pos,
2726 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2727
2728 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2729 isr_stats->ctkill);
2730
2731 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2732 isr_stats->wakeup);
2733
2734 pos += scnprintf(buf + pos, bufsz - pos,
2735 "Rx command responses:\t\t %u\n", isr_stats->rx);
2736
2737 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2738 isr_stats->tx);
2739
2740 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2741 isr_stats->unhandled);
2742
2743 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2744 kfree(buf);
2745 return ret;
2746}
2747
2748static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2749 const char __user *user_buf,
2750 size_t count, loff_t *ppos)
2751{
2752 struct iwl_trans *trans = file->private_data;
20d3b647 2753 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2754 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2755 u32 reset_flag;
078f1131 2756 int ret;
1f7b6172 2757
078f1131
JB		 2758 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2759 if (ret)
2760 return ret;
1f7b6172
EG		 2761 if (reset_flag == 0)
2762 memset(isr_stats, 0, sizeof(*isr_stats));
2763
2764 return count;
2765}
2766
16db88ba 2767static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2768 const char __user *user_buf,
2769 size_t count, loff_t *ppos)
16db88ba
EG		 2770{
2771 struct iwl_trans *trans = file->private_data;
16db88ba 2772
990aa6d7 2773 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2774
2775 return count;
2776}
2777
16db88ba 2778static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2779 char __user *user_buf,
2780 size_t count, loff_t *ppos)
16db88ba
EG		 2781{
2782 struct iwl_trans *trans = file->private_data;
94543a8d 2783 char *buf = NULL;
56c2477f 2784 ssize_t ret;
16db88ba 2785
56c2477f
JB		 2786 ret = iwl_dump_fh(trans, &buf);
2787 if (ret < 0)
2788 return ret;
2789 if (!buf)
2790 return -EINVAL;
2791 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2792 kfree(buf);
16db88ba
EG		 2793 return ret;
2794}
2795
fa4de7f7
JB		 2796static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2797 char __user *user_buf,
2798 size_t count, loff_t *ppos)
2799{
2800 struct iwl_trans *trans = file->private_data;
2801 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2802 char buf[100];
2803 int pos;
2804
2805 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2806 trans_pcie->debug_rfkill,
2807 !(iwl_read32(trans, CSR_GP_CNTRL) &
2808 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2809
2810 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2811}
2812
2813static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2814 const char __user *user_buf,
2815 size_t count, loff_t *ppos)
2816{
2817 struct iwl_trans *trans = file->private_data;
2818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c5bf4fa1 2819 bool new_value;
fa4de7f7
JB		 2820 int ret;
2821
c5bf4fa1 2822 ret = kstrtobool_from_user(user_buf, count, &new_value);
fa4de7f7
JB		 2823 if (ret)
2824 return ret;
c5bf4fa1 2825 if (new_value == trans_pcie->debug_rfkill)
fa4de7f7
JB		 2826 return count;
2827 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
c5bf4fa1
JB		 2828 trans_pcie->debug_rfkill, new_value);
2829 trans_pcie->debug_rfkill = new_value;
fa4de7f7
JB		 2830 iwl_pcie_handle_rfkill_irq(trans);
2831
2832 return count;
2833}
2834
f7805b33
LC		 2835static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2836 struct file *file)
2837{
2838 struct iwl_trans *trans = inode->i_private;
2839 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2840
91c28b83
SM		 2841 if (!trans->dbg.dest_tlv ||
2842 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
f7805b33
LC		 2843 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2844 return -ENOENT;
2845 }
2846
2847 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2848 return -EBUSY;
2849
2850 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2851 return simple_open(inode, file);
2852}
2853
2854static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2855 struct file *file)
2856{
2857 struct iwl_trans_pcie *trans_pcie =
2858 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2859
2860 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2861 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2862 return 0;
2863}
2864
2865static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2866 void *buf, ssize_t *size,
2867 ssize_t *bytes_copied)
2868{
2869 int buf_size_left = count - *bytes_copied;
2870
2871 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2872 if (*size > buf_size_left)
2873 *size = buf_size_left;
2874
2875 *size -= copy_to_user(user_buf, buf, *size);
2876 *bytes_copied += *size;
2877
2878 if (buf_size_left == *size)
2879 return true;
2880 return false;
2881}
2882
2883static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2884 char __user *user_buf,
2885 size_t count, loff_t *ppos)
2886{
2887 struct iwl_trans *trans = file->private_data;
2888 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
69f0e505 2889 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
f7805b33
LC		 2890 struct cont_rec *data = &trans_pcie->fw_mon_data;
2891 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2892 ssize_t size, bytes_copied = 0;
2893 bool b_full;
2894
91c28b83 2895 if (trans->dbg.dest_tlv) {
f7805b33 2896 write_ptr_addr =
91c28b83
SM		 2897 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2898 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
f7805b33
LC		 2899 } else {
2900 write_ptr_addr = MON_BUFF_WRPTR;
2901 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2902 }
2903
91c28b83 2904 if (unlikely(!trans->dbg.rec_on))
f7805b33
LC		 2905 return 0;
2906
2907 mutex_lock(&data->mutex);
2908 if (data->state ==
2909 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2910 mutex_unlock(&data->mutex);
2911 return 0;
2912 }
2913
2914 /* write_ptr position in bytes rather then DW */
2915 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2916 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2917
2918 if (data->prev_wrap_cnt == wrap_cnt) {
2919 size = write_ptr - data->prev_wr_ptr;
2920 curr_buf = cpu_addr + data->prev_wr_ptr;
2921 b_full = iwl_write_to_user_buf(user_buf, count,
2922 curr_buf, &size,
2923 &bytes_copied);
2924 data->prev_wr_ptr += size;
2925
2926 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2927 write_ptr < data->prev_wr_ptr) {
69f0e505 2928 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
f7805b33
LC		 2929 curr_buf = cpu_addr + data->prev_wr_ptr;
2930 b_full = iwl_write_to_user_buf(user_buf, count,
2931 curr_buf, &size,
2932 &bytes_copied);
2933 data->prev_wr_ptr += size;
2934
2935 if (!b_full) {
2936 size = write_ptr;
2937 b_full = iwl_write_to_user_buf(user_buf, count,
2938 cpu_addr, &size,
2939 &bytes_copied);
2940 data->prev_wr_ptr = size;
2941 data->prev_wrap_cnt++;
2942 }
2943 } else {
2944 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2945 write_ptr > data->prev_wr_ptr)
2946 IWL_WARN(trans,
2947 "write pointer passed previous write pointer, start copying from the beginning\n");
2948 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2949 data->prev_wr_ptr == 0))
2950 IWL_WARN(trans,
2951 "monitor data is out of sync, start copying from the beginning\n");
2952
2953 size = write_ptr;
2954 b_full = iwl_write_to_user_buf(user_buf, count,
2955 cpu_addr, &size,
2956 &bytes_copied);
2957 data->prev_wr_ptr = size;
2958 data->prev_wrap_cnt = wrap_cnt;
2959 }
2960
2961 mutex_unlock(&data->mutex);
2962
2963 return bytes_copied;
2964}
2965
1f7b6172 2966DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2967DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c 2968DEBUGFS_READ_FILE_OPS(rx_queue);
16db88ba 2969DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2970DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
df67a1be
JB		 2971static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2972 .owner = THIS_MODULE,
2973 .open = iwl_dbgfs_tx_queue_open,
2974 .read = seq_read,
2975 .llseek = seq_lseek,
2976 .release = seq_release_private,
2977};
87e5666c 2978
f7805b33
LC		 2979static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2980 .read = iwl_dbgfs_monitor_data_read,
2981 .open = iwl_dbgfs_monitor_data_open,
2982 .release = iwl_dbgfs_monitor_data_release,
2983};
2984
f8a1edb7 2985/* Create the debugfs files and directories */
cf5d5663 2986void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2987{
f8a1edb7
JB		 2988 struct dentry *dir = trans->dbgfs_dir;
2989
2ef00c53
JP		 2990 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2991 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2992 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2993 DEBUGFS_ADD_FILE(csr, dir, 0200);
2994 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2995 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 2996 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
87e5666c 2997}
f7805b33
LC		 2998
2999static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
3000{
3001 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3002 struct cont_rec *data = &trans_pcie->fw_mon_data;
3003
3004 mutex_lock(&data->mutex);
3005 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
3006 mutex_unlock(&data->mutex);
3007}
aadede6e 3008#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 3009
6983ba69 3010static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 3011{
3cd1980b 3012 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 3013 u32 cmdlen = 0;
3014 int i;
3015
3cd1980b 3016 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 3017 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 3018
3019 return cmdlen;
3020}
3021
bd7fc617
EG		 3022static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3023 struct iwl_fw_error_dump_data **data,
3024 int allocated_rb_nums)
3025{
3026 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
80084e35 3027 int max_len = trans_pcie->rx_buf_bytes;
78485054
SS		 3028 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3029 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 3030 u32 i, r, j, rb_len = 0;
3031
3032 spin_lock(&rxq->lock);
3033
0307c839 3034 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 3035
3036 for (i = rxq->read, j = 0;
3037 i != r && j < allocated_rb_nums;
3038 i = (i + 1) & RX_QUEUE_MASK, j++) {
3039 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3040 struct iwl_fw_error_dump_rb *rb;
3041
3042 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
3043 DMA_FROM_DEVICE);
3044
3045 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3046
3047 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3048 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3049 rb = (void *)(*data)->data;
3050 rb->index = cpu_to_le32(i);
3051 memcpy(rb->data, page_address(rxb->page), max_len);
3052 /* remap the page for the free benefit */
cfdc20ef
JB		 3053 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
3054 rxb->offset, max_len,
3055 DMA_FROM_DEVICE);
bd7fc617
EG		 3056
3057 *data = iwl_fw_error_next_data(*data);
3058 }
3059
3060 spin_unlock(&rxq->lock);
3061
3062 return rb_len;
3063}
473ad712
EG		 3064#define IWL_CSR_TO_DUMP (0x250)
3065
3066static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3067 struct iwl_fw_error_dump_data **data)
3068{
3069 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3070 __le32 *val;
3071 int i;
3072
3073 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3074 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3075 val = (void *)(*data)->data;
3076
3077 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3078 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3079
3080 *data = iwl_fw_error_next_data(*data);
3081
3082 return csr_len;
3083}
3084
06d51e0d
LK		 3085static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3086 struct iwl_fw_error_dump_data **data)
3087{
3088 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3089 unsigned long flags;
3090 __le32 *val;
3091 int i;
3092
23ba9340 3093 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 3094 return 0;
3095
3096 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3097 (*data)->len = cpu_to_le32(fh_regs_len);
3098 val = (void *)(*data)->data;
3099
286ca8eb 3100 if (!trans->trans_cfg->gen2)
723b45e2
LK		 3101 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3102 i += sizeof(u32))
3103 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3104 else
ea695b7c
ST		 3105 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3106 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 3107 i += sizeof(u32))
3108 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3109 i));
06d51e0d
LK		 3110
3111 iwl_trans_release_nic_access(trans, &flags);
3112
3113 *data = iwl_fw_error_next_data(*data);
3114
3115 return sizeof(**data) + fh_regs_len;
3116}
3117
cc79ef66
LK		 3118static u32
3119iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3120 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3121 u32 monitor_len)
3122{
3123 u32 buf_size_in_dwords = (monitor_len >> 2);
3124 u32 *buffer = (u32 *)fw_mon_data->data;
3125 unsigned long flags;
3126 u32 i;
3127
23ba9340 3128 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 3129 return 0;
3130
ea695b7c 3131 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 3132 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 3133 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3134 MON_DMARB_RD_DATA_ADDR);
3135 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 3136
3137 iwl_trans_release_nic_access(trans, &flags);
3138
3139 return monitor_len;
3140}
3141
7a14c23d
SS		 3142static void
3143iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3144 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3145{
c88580e1 3146 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
7a14c23d 3147
286ca8eb 3148 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3149 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3150 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3151 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3152 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
91c28b83
SM		 3153 } else if (trans->dbg.dest_tlv) {
3154 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3155 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3156 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
7a14c23d
SS		 3157 } else {
3158 base = MON_BUFF_BASE_ADDR;
3159 write_ptr = MON_BUFF_WRPTR;
3160 wrap_cnt = MON_BUFF_CYCLE_CNT;
3161 }
c88580e1
SM		 3162
3163 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3164 fw_mon_data->fw_mon_cycle_cnt =
3165 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3166 fw_mon_data->fw_mon_base_ptr =
3167 cpu_to_le32(iwl_read_prph(trans, base));
286ca8eb 3168 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3169 fw_mon_data->fw_mon_base_high_ptr =
3170 cpu_to_le32(iwl_read_prph(trans, base_high));
3171 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3172 }
3173 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3174}
3175
36fb9017
OG		 3176static u32
3177iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3178 struct iwl_fw_error_dump_data **data,
3179 u32 monitor_len)
3180{
69f0e505 3181 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
36fb9017
OG		 3182 u32 len = 0;
3183
91c28b83 3184 if (trans->dbg.dest_tlv ||
69f0e505 3185 (fw_mon->size &&
286ca8eb
LC		 3186 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3187 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
36fb9017 3188 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3189
3190 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3191 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3192
3193 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3194
3195 len += sizeof(**data) + sizeof(*fw_mon_data);
69f0e505
SM		 3196 if (fw_mon->size) {
3197 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3198 monitor_len = fw_mon->size;
91c28b83 3199 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3200 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3201 /*
3202 * Update pointers to reflect actual values after
3203 * shifting
3204 */
91c28b83 3205 if (trans->dbg.dest_tlv->version) {
fd527eb5
GBA		 3206 base = (iwl_read_prph(trans, base) &
3207 IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3208 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3209 base *= IWL_M2S_UNIT_SIZE;
3210 base += trans->cfg->smem_offset;
3211 } else {
3212 base = iwl_read_prph(trans, base) <<
91c28b83 3213 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3214 }
3215
36fb9017
OG		 3216 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3217 monitor_len / sizeof(u32));
91c28b83 3218 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
36fb9017
OG		 3219 monitor_len =
3220 iwl_trans_pci_dump_marbh_monitor(trans,
3221 fw_mon_data,
3222 monitor_len);
3223 } else {
3224 /* Didn't match anything - output no monitor data */
3225 monitor_len = 0;
3226 }
3227
3228 len += monitor_len;
3229 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3230 }
3231
3232 return len;
3233}
3234
93079fd5 3235static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3236{
69f0e505 3237 if (trans->dbg.fw_mon.size) {
da752717
SM		 3238 *len += sizeof(struct iwl_fw_error_dump_data) +
3239 sizeof(struct iwl_fw_error_dump_fw_mon) +
69f0e505
SM		 3240 trans->dbg.fw_mon.size;
3241 return trans->dbg.fw_mon.size;
91c28b83 3242 } else if (trans->dbg.dest_tlv) {
da752717 3243 u32 base, end, cfg_reg, monitor_len;
99684ae3 3244
91c28b83
SM		 3245 if (trans->dbg.dest_tlv->version == 1) {
3246 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
fd527eb5
GBA		 3247 cfg_reg = iwl_read_prph(trans, cfg_reg);
3248 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3249 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3250 base *= IWL_M2S_UNIT_SIZE;
3251 base += trans->cfg->smem_offset;
99684ae3 3252
fd527eb5
GBA		 3253 monitor_len =
3254 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
91c28b83 3255 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3256 monitor_len *= IWL_M2S_UNIT_SIZE;
3257 } else {
91c28b83
SM		 3258 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3259 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
99684ae3 3260
fd527eb5 3261 base = iwl_read_prph(trans, base) <<
91c28b83 3262 trans->dbg.dest_tlv->base_shift;
fd527eb5 3263 end = iwl_read_prph(trans, end) <<
91c28b83 3264 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3265
3266 /* Make "end" point to the actual end */
286ca8eb 3267 if (trans->trans_cfg->device_family >=
fd527eb5 3268 IWL_DEVICE_FAMILY_8000 ||
91c28b83
SM		 3269 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3270 end += (1 << trans->dbg.dest_tlv->end_shift);
fd527eb5
GBA		 3271 monitor_len = end - base;
3272 }
da752717
SM		 3273 *len += sizeof(struct iwl_fw_error_dump_data) +
3274 sizeof(struct iwl_fw_error_dump_fw_mon) +
3275 monitor_len;
3276 return monitor_len;
99684ae3 3277 }
da752717
SM		 3278 return 0;
3279}
3280
3281static struct iwl_trans_dump_data
3282*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
79f033f6 3283 u32 dump_mask)
da752717
SM		 3284{
3285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3286 struct iwl_fw_error_dump_data *data;
3287 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3288 struct iwl_fw_error_dump_txcmd *txcmd;
3289 struct iwl_trans_dump_data *dump_data;
fefbf853 3290 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3291 int i, ptr;
3292 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
286ca8eb 3293 !trans->trans_cfg->mq_rx_supported &&
79f033f6
SS		 3294 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3295
3296 if (!dump_mask)
3297 return NULL;
da752717
SM		 3298
3299 /* transport dump header */
3300 len = sizeof(*dump_data);
3301
3302 /* host commands */
e4eee943 3303 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
8672aad3
SM		 3304 len += sizeof(*data) +
3305 cmdq->n_window * (sizeof(*txcmd) +
3306 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3307
3308 /* FW monitor */
fefbf853
SM		 3309 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3310 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3311
3312 /* CSR registers */
79f033f6 3313 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3314 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3315
36fb9017 3316 /* FH registers */
79f033f6 3317 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
286ca8eb 3318 if (trans->trans_cfg->gen2)
520f03ea 3319 len += sizeof(*data) +
ea695b7c
ST		 3320 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3321 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3322 else
3323 len += sizeof(*data) +
3324 (FH_MEM_UPPER_BOUND -
3325 FH_MEM_LOWER_BOUND);
3326 }
36fb9017
OG		 3327
3328 if (dump_rbs) {
78485054
SS		 3329 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3330 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3331 /* RBs */
0307c839
GBA		 3332 num_rbs =
3333 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3334 & 0x0FFF;
78485054 3335 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3336 len += num_rbs * (sizeof(*data) +
3337 sizeof(struct iwl_fw_error_dump_rb) +
3338 (PAGE_SIZE << trans_pcie->rx_page_order));
3339 }
3340
5538409b 3341 /* Paged memory for gen2 HW */
286ca8eb 3342 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3343 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3344 len += sizeof(*data) +
3345 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3346 trans->init_dram.paging[i].size;
5538409b 3347
48eb7b34
EG		 3348 dump_data = vzalloc(len);
3349 if (!dump_data)
3350 return NULL;
4d075007
JB		 3351
3352 len = 0;
48eb7b34 3353 data = (void *)dump_data->data;
520f03ea 3354
e4eee943 3355 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
520f03ea
SM		 3356 u16 tfd_size = trans_pcie->tfd_size;
3357
3358 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3359 txcmd = (void *)data->data;
3360 spin_lock_bh(&cmdq->lock);
3361 ptr = cmdq->write_ptr;
3362 for (i = 0; i < cmdq->n_window; i++) {
3363 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
08326a97 3364 u8 tfdidx;
520f03ea
SM		 3365 u32 caplen, cmdlen;
3366
08326a97
JB		 3367 if (trans->trans_cfg->use_tfh)
3368 tfdidx = idx;
3369 else
3370 tfdidx = ptr;
3371
520f03ea 3372 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
08326a97
JB		 3373 (u8 *)cmdq->tfds +
3374 tfd_size * tfdidx);
520f03ea
SM		 3375 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3376
3377 if (cmdlen) {
3378 len += sizeof(*txcmd) + caplen;
3379 txcmd->cmdlen = cpu_to_le32(cmdlen);
3380 txcmd->caplen = cpu_to_le32(caplen);
3381 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3382 caplen);
3383 txcmd = (void *)((u8 *)txcmd->data + caplen);
3384 }
3385
3386 ptr = iwl_queue_dec_wrap(trans, ptr);
4d075007 3387 }
520f03ea 3388 spin_unlock_bh(&cmdq->lock);
4d075007 3389
520f03ea
SM		 3390 data->len = cpu_to_le32(len);
3391 len += sizeof(*data);
3392 data = iwl_fw_error_next_data(data);
4d075007 3393 }
67c65f2c 3394
79f033f6 3395 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3396 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3397 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3398 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3399 if (dump_rbs)
3400 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3401
5538409b 3402 /* Paged memory for gen2 HW */
286ca8eb 3403 if (trans->trans_cfg->gen2 &&
79b6c8fe 3404 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3405 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3406 struct iwl_fw_error_dump_paging *paging;
505a00c0 3407 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3408
3409 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3410 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3411 paging = (void *)data->data;
3412 paging->index = cpu_to_le32(i);
5538409b 3413 memcpy(paging->data,
505a00c0 3414 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3415 data = iwl_fw_error_next_data(data);
3416
3417 len += sizeof(*data) + sizeof(*paging) + page_len;
3418 }
3419 }
79f033f6 3420 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3421 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3422
48eb7b34
EG		 3423 dump_data->len = len;
3424
3425 return dump_data;
4d075007 3426}
87e5666c 3427
4cbb8e50
LC		 3428#ifdef CONFIG_PM_SLEEP
3429static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3430{
4cbb8e50
LC		 3431 return 0;
3432}
3433
3434static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3435{
4cbb8e50
LC		 3436}
3437#endif /* CONFIG_PM_SLEEP */
3438
623e7766
SS		 3439#define IWL_TRANS_COMMON_OPS \
3440 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3441 .write8 = iwl_trans_pcie_write8, \
3442 .write32 = iwl_trans_pcie_write32, \
3443 .read32 = iwl_trans_pcie_read32, \
3444 .read_prph = iwl_trans_pcie_read_prph, \
3445 .write_prph = iwl_trans_pcie_write_prph, \
3446 .read_mem = iwl_trans_pcie_read_mem, \
3447 .write_mem = iwl_trans_pcie_write_mem, \
7f1fe1d4 3448 .read_config32 = iwl_trans_pcie_read_config32, \
623e7766
SS		 3449 .configure = iwl_trans_pcie_configure, \
3450 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3451 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3452 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3453 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3454 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
623e7766 3455 .dump_data = iwl_trans_pcie_dump_data, \
623e7766 3456 .d3_suspend = iwl_trans_pcie_d3_suspend, \
d1967ce6
SM		 3457 .d3_resume = iwl_trans_pcie_d3_resume, \
3458 .sync_nmi = iwl_trans_pcie_sync_nmi
623e7766
SS		 3459
3460#ifdef CONFIG_PM_SLEEP
3461#define IWL_TRANS_PM_OPS \
3462 .suspend = iwl_trans_pcie_suspend, \
3463 .resume = iwl_trans_pcie_resume,
3464#else
3465#define IWL_TRANS_PM_OPS
3466#endif /* CONFIG_PM_SLEEP */
3467
d1ff5253 3468static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3469 IWL_TRANS_COMMON_OPS,
3470 IWL_TRANS_PM_OPS
57a1dc89 3471 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3472 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3473 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3474 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3475
623e7766 3476 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3477
623e7766
SS		 3478 .tx = iwl_trans_pcie_tx,
3479 .reclaim = iwl_trans_pcie_reclaim,
3480
3481 .txq_disable = iwl_trans_pcie_txq_disable,
3482 .txq_enable = iwl_trans_pcie_txq_enable,
3483
3484 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3485
d6d517b7
SS		 3486 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3487
623e7766
SS		 3488 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3489 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3490#ifdef CONFIG_IWLWIFI_DEBUGFS
3491 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3492#endif
623e7766
SS		 3493};
3494
3495static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3496 IWL_TRANS_COMMON_OPS,
3497 IWL_TRANS_PM_OPS
3498 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3499 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3500 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3501 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3502
ca60da2e 3503 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3504
ab6c6445 3505 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3506 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3507
ba7136f3
AM		 3508 .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3509
6b35ff91
SS		 3510 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3511 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3512 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3513 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
f7805b33
LC		 3514#ifdef CONFIG_IWLWIFI_DEBUGFS
3515 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3516#endif
e6bb4c9c 3517};
a42a1844 3518
87ce05a2 3519struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
7e8258c0
LC		 3520 const struct pci_device_id *ent,
3521 const struct iwl_cfg_trans_params *cfg_trans)
a42a1844 3522{
a42a1844
EG		 3523 struct iwl_trans_pcie *trans_pcie;
3524 struct iwl_trans *trans;
a89c72ff
JB		 3525 int ret, addr_size, txcmd_size, txcmd_align;
3526 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3527
3528 if (!cfg_trans->gen2) {
3529 ops = &trans_ops_pcie;
3530 txcmd_size = sizeof(struct iwl_tx_cmd);
3531 txcmd_align = sizeof(void *);
3532 } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) {
3533 txcmd_size = sizeof(struct iwl_tx_cmd_gen2);
3534 txcmd_align = 64;
3535 } else {
3536 txcmd_size = sizeof(struct iwl_tx_cmd_gen3);
3537 txcmd_align = 128;
3538 }
3539
3540 txcmd_size += sizeof(struct iwl_cmd_header);
3541 txcmd_size += 36; /* biggest possible 802.11 header */
3542
3543 /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */
3544 if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align))
3545 return ERR_PTR(-EINVAL);
a42a1844 3546
5a41a86c
SD		 3547 ret = pcim_enable_device(pdev);
3548 if (ret)
3549 return ERR_PTR(ret);
3550
a89c72ff
JB		 3551 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3552 txcmd_size, txcmd_align);
7b501d10
JB		 3553 if (!trans)
3554 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3555
3556 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3557
a42a1844 3558 trans_pcie->trans = trans;
326477e4 3559 trans_pcie->opmode_down = true;
7b11488f 3560 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3561 spin_lock_init(&trans_pcie->reg_lock);
cfdc20ef 3562 spin_lock_init(&trans_pcie->alloc_page_lock);
fa9f3281 3563 mutex_init(&trans_pcie->mutex);
13df1aab 3564 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
8188a18e
JB		 3565
3566 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3567 WQ_HIGHPRI | WQ_UNBOUND, 1);
3568 if (!trans_pcie->rba.alloc_wq) {
3569 ret = -ENOMEM;
3570 goto out_free_trans;
3571 }
3572 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3573
6eb5e529
EG		 3574 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3575 if (!trans_pcie->tso_hdr_page) {
3576 ret = -ENOMEM;
3577 goto out_no_pci;
3578 }
c5bf4fa1 3579 trans_pcie->debug_rfkill = -1;
d819c6cf 3580
7e8258c0 3581 if (!cfg_trans->base_params->pcie_l1_allowed) {
f2532b04
EG		 3582 /*
3583 * W/A - seems to solve weird behavior. We need to remove this
3584 * if we don't want to stay in L1 all the time. This wastes a
3585 * lot of power.
3586 */
3587 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3588 PCIE_LINK_STATE_L1 |
3589 PCIE_LINK_STATE_CLKPM);
3590 }
a42a1844 3591
9416560e
GBA		 3592 trans_pcie->def_rx_queue = 0;
3593
7e8258c0 3594 if (cfg_trans->use_tfh) {
2c6262b7 3595 addr_size = 64;
3cd1980b 3596 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3597 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3598 } else {
2c6262b7 3599 addr_size = 36;
3cd1980b 3600 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3601 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3602 }
3cd1980b
SS		 3603 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3604
a42a1844
EG		 3605 pci_set_master(pdev);
3606
96a6497b 3607 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3608 if (!ret)
96a6497b
SS		 3609 ret = pci_set_consistent_dma_mask(pdev,
3610 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3611 if (ret) {
3612 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3613 if (!ret)
3614 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3615 DMA_BIT_MASK(32));
a42a1844 3616 /* both attempts failed: */
af3f2f74 3617 if (ret) {
6a4b09f8 3618 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3619 goto out_no_pci;
a42a1844
EG		 3620 }
3621 }
3622
5a41a86c 3623 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3624 if (ret) {
5a41a86c
SD		 3625 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3626 goto out_no_pci;
a42a1844
EG		 3627 }
3628
5a41a86c 3629 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3630 if (!trans_pcie->hw_base) {
5a41a86c 3631 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3632 ret = -ENODEV;
5a41a86c 3633 goto out_no_pci;
a42a1844
EG		 3634 }
3635
a42a1844
EG		 3636 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3637 * PCI Tx retries from interfering with C3 CPU state */
3638 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3639
83f7a85f
EG		 3640 trans_pcie->pci_dev = pdev;
3641 iwl_disable_interrupts(trans);
3642
08079a49 3643 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3644 if (trans->hw_rev == 0xffffffff) {
3645 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3646 ret = -EIO;
3647 goto out_no_pci;
3648 }
3649
b513ee7f
LK		 3650 /*
3651 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3652 * changed, and now the revision step also includes bit 0-1 (no more
3653 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3654 * in the old format.
3655 */
7e8258c0 3656 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
b513ee7f 3657 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3658 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3659
f9e5554c
EG		 3660 ret = iwl_pcie_prepare_card_hw(trans);
3661 if (ret) {
3662 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3663 goto out_no_pci;
f9e5554c
EG		 3664 }
3665
7a42baa6
EH		 3666 /*
3667 * in-order to recognize C step driver should read chip version
3668 * id located at the AUX bus MISC address space.
3669 */
7e8258c0 3670 ret = iwl_finish_nic_init(trans, cfg_trans);
c96b5eec 3671 if (ret)
5a41a86c 3672 goto out_no_pci;
7a42baa6 3673
7a42baa6
EH		 3674 }
3675
99be6166
LC		 3676 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3677
7e8258c0 3678 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
99673ee5 3679 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3680 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3681 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3682
69a10b29 3683 /* Initialize the wait queue for commands */
f946b529 3684 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3685
e5f3f215
HD		 3686 init_waitqueue_head(&trans_pcie->sx_waitq);
3687
2e5d4a8f 3688 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3689 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3690 if (ret)
5a41a86c 3691 goto out_no_pci;
2e5d4a8f
HD		 3692 } else {
3693 ret = iwl_pcie_alloc_ict(trans);
3694 if (ret)
5a41a86c 3695 goto out_no_pci;
a8b691e6 3696
5a41a86c
SD		 3697 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3698 iwl_pcie_isr,
3699 iwl_pcie_irq_handler,
3700 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3701 if (ret) {
3702 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3703 goto out_free_ict;
3704 }
3705 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3706 }
83f7a85f 3707
f7805b33
LC		 3708#ifdef CONFIG_IWLWIFI_DEBUGFS
3709 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3710 mutex_init(&trans_pcie->fw_mon_data.mutex);
3711#endif
3712
a9248de4
SM		 3713 iwl_dbg_tlv_init(trans);
3714
a42a1844
EG		 3715 return trans;
3716
a8b691e6
JB		 3717out_free_ict:
3718 iwl_pcie_free_ict(trans);
a42a1844 3719out_no_pci:
6eb5e529 3720 free_percpu(trans_pcie->tso_hdr_page);
8188a18e
JB		 3721 destroy_workqueue(trans_pcie->rba.alloc_wq);
3722out_free_trans:
7b501d10 3723 iwl_trans_free(trans);
af3f2f74 3724 return ERR_PTR(ret);
a42a1844 3725}
b8a7547d 3726
d1967ce6 3727void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
b8a7547d 3728{
1c6bca6d 3729 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
b8a7547d 3730 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
e4eee943 3731 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
1c6bca6d
SM		 3732 u32 inta_addr, sw_err_bit;
3733
3734 if (trans_pcie->msix_enabled) {
3735 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3736 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3737 } else {
3738 inta_addr = CSR_INT;
3739 sw_err_bit = CSR_INT_BIT_SW_ERR;
3740 }
b8a7547d 3741
e4eee943
SM		 3742 /* if the interrupts were already disabled, there is no point in
3743 * calling iwl_disable_interrupts
3744 */
3745 if (interrupts_enabled)
3746 iwl_disable_interrupts(trans);
3747
b8a7547d
SM		 3748 iwl_force_nmi(trans);
3749 while (time_after(timeout, jiffies)) {
1c6bca6d 3750 u32 inta_hw = iwl_read32(trans, inta_addr);
b8a7547d
SM		 3751
3752 /* Error detected by uCode */
1c6bca6d 3753 if (inta_hw & sw_err_bit) {
b8a7547d 3754 /* Clear causes register */
1c6bca6d 3755 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
b8a7547d
SM		 3756 break;
3757 }
3758
3759 mdelay(1);
3760 }
e4eee943
SM		 3761
3762 /* enable interrupts only if there were already enabled before this
3763 * function to avoid a case were the driver enable interrupts before
3764 * proper configurations were made
3765 */
3766 if (interrupts_enabled)
3767 iwl_enable_interrupts(trans);
3768
b8a7547d
SM		 3769 iwl_trans_fw_error(trans);
3770}
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