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iwlwifi: trans: add a new op for getting DMA data
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
a8cbb46f 11 * Copyright(c) 2018 Intel Corporation
c85eb619
EG		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * USA
26 *
27 * The full GNU General Public License is included in this distribution
410dc5aa 28 * in the file called COPYING.
c85eb619
EG		 29 *
30 * Contact Information:
cb2f8277 31 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *
34 * BSD LICENSE
35 *
553452e5
LK		 36 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
37 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 38 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
a8cbb46f 39 * Copyright(c) 2018 Intel Corporation
c85eb619
EG		 40 * All rights reserved.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
44 * are met:
45 *
46 * * Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * * Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in
50 * the documentation and/or other materials provided with the
51 * distribution.
52 * * Neither the name Intel Corporation nor the names of its
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
55 *
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
57 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
59 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
60 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
62 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 *
68 *****************************************************************************/
a42a1844
EG		 69#include <linux/pci.h>
70#include <linux/pci-aspm.h>
e6bb4c9c 71#include <linux/interrupt.h>
87e5666c 72#include <linux/debugfs.h>
cf614297 73#include <linux/sched.h>
6d8f6eeb
EG		 74#include <linux/bitops.h>
75#include <linux/gfp.h>
48eb7b34 76#include <linux/vmalloc.h>
b3ff1270 77#include <linux/pm_runtime.h>
49564a80 78#include <linux/module.h>
e6bb4c9c 79
82575102 80#include "iwl-drv.h"
c85eb619 81#include "iwl-trans.h"
522376d2
EG		 82#include "iwl-csr.h"
83#include "iwl-prph.h"
cb6bb128 84#include "iwl-scd.h"
7a10e3e4 85#include "iwl-agn-hw.h"
d962f9b1 86#include "fw/error-dump.h"
6468a01a 87#include "internal.h"
06d51e0d 88#include "iwl-fh.h"
0439bb62 89
fe45773b
AN		 90/* extended range in FW SRAM */
91#define IWL_FW_MEM_EXTENDED_START 0x40000
92#define IWL_FW_MEM_EXTENDED_END 0x57FFF
93
fb12777a 94static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad
RJ		 95{
96#define PCI_DUMP_SIZE 64
97#define PREFIX_LEN 32
98 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
99 struct pci_dev *pdev = trans_pcie->pci_dev;
100 u32 i, pos, alloc_size, *ptr, *buf;
101 char *prefix;
102
103 if (trans_pcie->pcie_dbg_dumped_once)
104 return;
105
106 /* Should be a multiple of 4 */
107 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
108 /* Alloc a max size buffer */
109 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
110 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
111 else
112 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
113 buf = kmalloc(alloc_size, GFP_ATOMIC);
114 if (!buf)
115 return;
116 prefix = (char *)buf + alloc_size - PREFIX_LEN;
117
118 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
119
120 /* Print wifi device registers */
121 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
122 IWL_ERR(trans, "iwlwifi device config registers:\n");
123 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
124 if (pci_read_config_dword(pdev, i, ptr))
125 goto err_read;
126 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
127
128 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
129 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
130 *ptr = iwl_read32(trans, i);
131 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
132
133 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
134 if (pos) {
135 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
136 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
137 if (pci_read_config_dword(pdev, pos + i, ptr))
138 goto err_read;
139 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
140 32, 4, buf, i, 0);
141 }
142
143 /* Print parent device registers next */
144 if (!pdev->bus->self)
145 goto out;
146
147 pdev = pdev->bus->self;
148 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
149
150 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
151 pci_name(pdev));
152 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
153 if (pci_read_config_dword(pdev, i, ptr))
154 goto err_read;
155 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
156
157 /* Print root port AER registers */
158 pos = 0;
159 pdev = pcie_find_root_port(pdev);
160 if (pdev)
161 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
162 if (pos) {
163 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
164 pci_name(pdev));
165 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
166 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
167 if (pci_read_config_dword(pdev, pos + i, ptr))
168 goto err_read;
169 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
170 4, buf, i, 0);
171 }
f3402d6d 172 goto out;
a6d24fad
RJ		 173
174err_read:
175 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
176 IWL_ERR(trans, "Read failed at 0x%X\n", i);
177out:
178 trans_pcie->pcie_dbg_dumped_once = 1;
179 kfree(buf);
180}
181
870c2a11
GBA		 182static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
183{
184 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
a8cbb46f
GBA		 185 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
186 BIT(trans->cfg->csr->flag_sw_reset));
870c2a11
GBA		 187 usleep_range(5000, 6000);
188}
189
c2d20201
EG		 190static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
191{
192 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
193
194 if (!trans_pcie->fw_mon_page)
195 return;
196
197 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
198 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
199 __free_pages(trans_pcie->fw_mon_page,
200 get_order(trans_pcie->fw_mon_size));
201 trans_pcie->fw_mon_page = NULL;
202 trans_pcie->fw_mon_phys = 0;
203 trans_pcie->fw_mon_size = 0;
204}
205
9f358c17 206void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 207{
208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 209 struct page *page = NULL;
c2d20201 210 dma_addr_t phys;
96c285da 211 u32 size = 0;
c2d20201
EG		 212 u8 power;
213
96c285da
EG		 214 if (!max_power) {
215 /* default max_power is maximum */
216 max_power = 26;
217 } else {
218 max_power += 11;
219 }
220
221 if (WARN(max_power > 26,
222 "External buffer size for monitor is too big %d, check the FW TLV\n",
223 max_power))
224 return;
225
c2d20201
EG		 226 if (trans_pcie->fw_mon_page) {
227 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
228 trans_pcie->fw_mon_size,
229 DMA_FROM_DEVICE);
230 return;
231 }
232
233 phys = 0;
96c285da 234 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 235 int order;
236
237 size = BIT(power);
238 order = get_order(size);
239 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
240 order);
241 if (!page)
242 continue;
243
244 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
245 DMA_FROM_DEVICE);
246 if (dma_mapping_error(trans->dev, phys)) {
247 __free_pages(page, order);
553452e5 248 page = NULL;
c2d20201
EG		 249 continue;
250 }
251 IWL_INFO(trans,
252 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
253 size, order);
254 break;
255 }
256
40a76905 257 if (WARN_ON_ONCE(!page))
c2d20201
EG		 258 return;
259
96c285da
EG		 260 if (power != max_power)
261 IWL_ERR(trans,
262 "Sorry - debug buffer is only %luK while you requested %luK\n",
263 (unsigned long)BIT(power - 10),
264 (unsigned long)BIT(max_power - 10));
265
c2d20201
EG		 266 trans_pcie->fw_mon_page = page;
267 trans_pcie->fw_mon_phys = phys;
268 trans_pcie->fw_mon_size = size;
269}
270
a812cba9
AB		 271static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
272{
273 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
274 ((reg & 0x0000ffff) | (2 << 28)));
275 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
276}
277
278static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
279{
280 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
281 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
282 ((reg & 0x0000ffff) | (3 << 28)));
283}
284
ddaf5a5b 285static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 286{
66337b7c 287 if (trans->cfg->apmg_not_supported)
95411d04
AA		 288 return;
289
ddaf5a5b
JB		 290 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
291 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
292 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
293 ~APMG_PS_CTRL_MSK_PWR_SRC);
294 else
295 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
296 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
297 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 298}
299
af634bee
EG		 300/* PCI registers */
301#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 302
eda50cde 303void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 304{
20d3b647 305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 306 u16 lctl;
9180ac50 307 u16 cap;
af634bee 308
af634bee
EG		 309 /*
310 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
311 * Check if BIOS (or OS) enabled L1-ASPM on this device.
312 * If so (likely), disable L0S, so device moves directly L0->L1;
313 * costs negligible amount of power savings.
314 * If not (unlikely), enable L0S, so there is at least some
315 * power savings, even without L1.
316 */
7afe3705 317 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 318 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 319 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 320 else
af634bee 321 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 322 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 323
324 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
325 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 326 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
327 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
328 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 329}
330
a6c684ee
EG		 331/*
332 * Start up NIC's basic functionality after it has been reset
7afe3705 333 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 334 * NOTE: This does not load uCode nor start the embedded processor
335 */
7afe3705 336static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 337{
52b6e168
EG		 338 int ret;
339
a6c684ee
EG		 340 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
341
342 /*
343 * Use "set_bit" below rather than "write", to preserve any hardware
344 * bits already set by default after reset.
345 */
346
347 /* Disable L0S exit timer (platform NMI Work/Around) */
6e584873 348 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 349 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
350 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 351
352 /*
353 * Disable L0s without affecting L1;
354 * don't wait for ICH L0s (ICH bug W/A)
355 */
356 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 357 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 358
359 /* Set FH wait threshold to maximum (HW error during stress W/A) */
360 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
361
362 /*
363 * Enable HAP INTA (interrupt from management bus) to
364 * wake device's PCI Express link L1a -> L0s
365 */
366 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 367 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 368
7afe3705 369 iwl_pcie_apm_config(trans);
a6c684ee
EG		 370
371 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 372 if (trans->cfg->base_params->pll_cfg)
373 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 374
375 /*
376 * Set "initialization complete" bit to move adapter from
377 * D0U* --> D0A* (powered-up active) state.
378 */
a8cbb46f
GBA		 379 iwl_set_bit(trans, CSR_GP_CNTRL,
380 BIT(trans->cfg->csr->flag_init_done));
a6c684ee
EG		 381
382 /*
383 * Wait for clock stabilization; once stabilized, access to
384 * device-internal resources is supported, e.g. iwl_write_prph()
385 * and accesses to uCode SRAM.
386 */
387 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 388 BIT(trans->cfg->csr->flag_mac_clock_ready),
389 BIT(trans->cfg->csr->flag_mac_clock_ready),
390 25000);
a6c684ee 391 if (ret < 0) {
52b6e168
EG		 392 IWL_ERR(trans, "Failed to init the card\n");
393 return ret;
a6c684ee
EG		 394 }
395
2d93aee1
EG		 396 if (trans->cfg->host_interrupt_operation_mode) {
397 /*
398 * This is a bit of an abuse - This is needed for 7260 / 3160
399 * only check host_interrupt_operation_mode even if this is
400 * not related to host_interrupt_operation_mode.
401 *
402 * Enable the oscillator to count wake up time for L1 exit. This
403 * consumes slightly more power (100uA) - but allows to be sure
404 * that we wake up from L1 on time.
405 *
406 * This looks weird: read twice the same register, discard the
407 * value, set a bit, and yet again, read that same register
408 * just to discard the value. But that's the way the hardware
409 * seems to like it.
410 */
411 iwl_read_prph(trans, OSC_CLK);
412 iwl_read_prph(trans, OSC_CLK);
413 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
414 iwl_read_prph(trans, OSC_CLK);
415 iwl_read_prph(trans, OSC_CLK);
416 }
417
a6c684ee
EG		 418 /*
419 * Enable DMA clock and wait for it to stabilize.
420 *
3073d8c0
EH		 421 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
422 * bits do not disable clocks. This preserves any hardware
423 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 424 */
95411d04 425 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 426 iwl_write_prph(trans, APMG_CLK_EN_REG,
427 APMG_CLK_VAL_DMA_CLK_RQT);
428 udelay(20);
429
430 /* Disable L1-Active */
431 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
432 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
433
434 /* Clear the interrupt in APMG if the NIC is in RFKILL */
435 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
436 APMG_RTC_INT_STT_RFKILL);
437 }
889b1696 438
eb7ff77e 439 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 440
52b6e168 441 return 0;
a6c684ee
EG		 442}
443
a812cba9
AB		 444/*
445 * Enable LP XTAL to avoid HW bug where device may consume much power if
446 * FW is not loaded after device reset. LP XTAL is disabled by default
447 * after device HW reset. Do it only if XTAL is fed by internal source.
448 * Configure device's "persistence" mode to avoid resetting XTAL again when
449 * SHRD_HW_RST occurs in S3.
450 */
451static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
452{
453 int ret;
454 u32 apmg_gp1_reg;
455 u32 apmg_xtal_cfg_reg;
456 u32 dl_cfg_reg;
457
458 /* Force XTAL ON */
459 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
460 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
461
870c2a11 462 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 463
464 /*
465 * Set "initialization complete" bit to move adapter from
466 * D0U* --> D0A* (powered-up active) state.
467 */
a8cbb46f
GBA		 468 iwl_set_bit(trans, CSR_GP_CNTRL,
469 BIT(trans->cfg->csr->flag_init_done));
a812cba9
AB		 470
471 /*
472 * Wait for clock stabilization; once stabilized, access to
473 * device-internal resources is possible.
474 */
475 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 476 BIT(trans->cfg->csr->flag_mac_clock_ready),
477 BIT(trans->cfg->csr->flag_mac_clock_ready),
a812cba9
AB		 478 25000);
479 if (WARN_ON(ret < 0)) {
480 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
481 /* Release XTAL ON request */
482 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
483 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
484 return;
485 }
486
487 /*
488 * Clear "disable persistence" to avoid LP XTAL resetting when
489 * SHRD_HW_RST is applied in S3.
490 */
491 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
492 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
493
494 /*
495 * Force APMG XTAL to be active to prevent its disabling by HW
496 * caused by APMG idle state.
497 */
498 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
499 SHR_APMG_XTAL_CFG_REG);
500 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
501 apmg_xtal_cfg_reg |
502 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
503
870c2a11 504 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 505
506 /* Enable LP XTAL by indirect access through CSR */
507 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
508 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
509 SHR_APMG_GP1_WF_XTAL_LP_EN |
510 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
511
512 /* Clear delay line clock power up */
513 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
514 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
515 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
516
517 /*
518 * Enable persistence mode to avoid LP XTAL resetting when
519 * SHRD_HW_RST is applied in S3.
520 */
521 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
522 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
523
524 /*
525 * Clear "initialization complete" bit to move adapter from
526 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
527 */
528 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 529 BIT(trans->cfg->csr->flag_init_done));
a812cba9
AB		 530
531 /* Activates XTAL resources monitor */
532 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
533 CSR_MONITOR_XTAL_RESOURCES);
534
535 /* Release XTAL ON request */
536 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
537 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
538 udelay(10);
539
540 /* Release APMG XTAL */
541 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
542 apmg_xtal_cfg_reg &
543 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
544}
545
e8c8935e 546void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 547{
e8c8935e 548 int ret;
cc56feb2
EG		 549
550 /* stop device's busmaster DMA activity */
a8cbb46f
GBA		 551 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
552 BIT(trans->cfg->csr->flag_stop_master));
cc56feb2 553
a8cbb46f
GBA		 554 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
555 BIT(trans->cfg->csr->flag_master_dis),
556 BIT(trans->cfg->csr->flag_master_dis), 100);
7f2ac8fb 557 if (ret < 0)
cc56feb2
EG		 558 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
559
560 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 561}
562
b7aaeae4 563static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 564{
565 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
566
b7aaeae4
EG		 567 if (op_mode_leave) {
568 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
569 iwl_pcie_apm_init(trans);
570
571 /* inform ME that we are leaving */
572 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
573 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
574 APMG_PCIDEV_STT_VAL_WAKE_ME);
6e584873 575 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 576 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
577 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 578 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
579 CSR_HW_IF_CONFIG_REG_PREPARE |
580 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 581 mdelay(1);
582 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
583 CSR_RESET_LINK_PWR_MGMT_DISABLED);
584 }
b7aaeae4
EG		 585 mdelay(5);
586 }
587
eb7ff77e 588 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 589
590 /* Stop device's DMA activity */
7afe3705 591 iwl_pcie_apm_stop_master(trans);
cc56feb2 592
a812cba9
AB		 593 if (trans->cfg->lp_xtal_workaround) {
594 iwl_pcie_apm_lp_xtal_enable(trans);
595 return;
596 }
597
870c2a11 598 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 599
600 /*
601 * Clear "initialization complete" bit to move adapter from
602 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
603 */
604 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 605 BIT(trans->cfg->csr->flag_init_done));
cc56feb2
EG		 606}
607
7afe3705 608static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 609{
7b11488f 610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 611 int ret;
392f8b78
EG		 612
613 /* nic_init */
7b70bd63 614 spin_lock(&trans_pcie->irq_lock);
52b6e168 615 ret = iwl_pcie_apm_init(trans);
7b70bd63 616 spin_unlock(&trans_pcie->irq_lock);
392f8b78 617
52b6e168
EG		 618 if (ret)
619 return ret;
620
95411d04 621 iwl_pcie_set_pwr(trans, false);
392f8b78 622
ecdb975c 623 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 624
625 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 626 iwl_pcie_rx_init(trans);
392f8b78
EG		 627
628 /* Allocate or reset and init all Tx and Command queues */
f02831be 629 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 630 return -ENOMEM;
631
035f7ff2 632 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 633 /* enable shadow regs in HW */
20d3b647 634 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 635 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 636 }
637
392f8b78
EG		 638 return 0;
639}
640
641#define HW_READY_TIMEOUT (50)
642
643/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 644static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 645{
646 int ret;
647
1042db2a 648 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 649 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 650
651 /* See if we got it */
1042db2a 652 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 653 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
654 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
655 HW_READY_TIMEOUT);
392f8b78 656
6a08f514
EG		 657 if (ret >= 0)
658 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
659
6d8f6eeb 660 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 661 return ret;
662}
663
664/* Note: returns standard 0/-ERROR code */
eda50cde 665int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 666{
667 int ret;
289e5501 668 int t = 0;
501fd989 669 int iter;
392f8b78 670
6d8f6eeb 671 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 672
7afe3705 673 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 674 /* If the card is ready, exit 0 */
392f8b78
EG		 675 if (ret >= 0)
676 return 0;
677
c9fdec9f
EG		 678 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
679 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 680 usleep_range(1000, 2000);
c9fdec9f 681
501fd989
EG		 682 for (iter = 0; iter < 10; iter++) {
683 /* If HW is not ready, prepare the conditions to check again */
684 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
685 CSR_HW_IF_CONFIG_REG_PREPARE);
686
687 do {
688 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 689 if (ret >= 0)
690 return 0;
392f8b78 691
501fd989
EG		 692 usleep_range(200, 1000);
693 t += 200;
694 } while (t < 150000);
695 msleep(25);
696 }
392f8b78 697
7f2ac8fb 698 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 699
392f8b78
EG		 700 return ret;
701}
702
cf614297
EG		 703/*
704 * ucode
705 */
564cdce7
SS		 706static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
707 u32 dst_addr, dma_addr_t phy_addr,
708 u32 byte_cnt)
cf614297 709{
bac842da
EG		 710 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
711 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
712
713 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
714 dst_addr);
715
716 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
717 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
718
719 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
720 (iwl_get_dma_hi_addr(phy_addr)
721 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
722
723 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
724 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
725 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
726 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
727
728 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
729 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
730 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
731 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 732}
733
564cdce7
SS		 734static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
735 u32 dst_addr, dma_addr_t phy_addr,
736 u32 byte_cnt)
737{
738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
739 unsigned long flags;
740 int ret;
741
742 trans_pcie->ucode_write_complete = false;
743
744 if (!iwl_trans_grab_nic_access(trans, &flags))
745 return -EIO;
746
eda50cde
SS		 747 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
748 byte_cnt);
bac842da 749 iwl_trans_release_nic_access(trans, &flags);
cf614297 750
13df1aab
JB		 751 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
752 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 753 if (!ret) {
83f84d7b 754 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 755 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 756 return -ETIMEDOUT;
757 }
758
759 return 0;
760}
761
7afe3705 762static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 763 const struct fw_desc *section)
cf614297 764{
83f84d7b
JB		 765 u8 *v_addr;
766 dma_addr_t p_addr;
baa21e83 767 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 768 int ret = 0;
769
83f84d7b
JB		 770 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
771 section_num);
772
c571573a
EG		 773 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
774 GFP_KERNEL | __GFP_NOWARN);
775 if (!v_addr) {
776 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
777 chunk_sz = PAGE_SIZE;
778 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
779 &p_addr, GFP_KERNEL);
780 if (!v_addr)
781 return -ENOMEM;
782 }
83f84d7b 783
c571573a 784 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 785 u32 copy_size, dst_addr;
786 bool extended_addr = false;
83f84d7b 787
c571573a 788 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 789 dst_addr = section->offset + offset;
790
791 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
792 dst_addr <= IWL_FW_MEM_EXTENDED_END)
793 extended_addr = true;
794
795 if (extended_addr)
796 iwl_set_bits_prph(trans, LMPM_CHICK,
797 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 798
83f84d7b 799 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 800 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
801 copy_size);
802
803 if (extended_addr)
804 iwl_clear_bits_prph(trans, LMPM_CHICK,
805 LMPM_CHICK_EXTENDED_ADDR_SPACE);
806
83f84d7b
JB		 807 if (ret) {
808 IWL_ERR(trans,
809 "Could not load the [%d] uCode section\n",
810 section_num);
811 break;
6dfa8d01 812 }
83f84d7b
JB		 813 }
814
c571573a 815 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 816 return ret;
817}
818
5dd9c68a
EG		 819static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
820 const struct fw_img *image,
821 int cpu,
822 int *first_ucode_section)
e2d6f4e7
EH		 823{
824 int shift_param;
dcab8ecd
EH		 825 int i, ret = 0, sec_num = 0x1;
826 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 827
828 if (cpu == 1) {
829 shift_param = 0;
034846cf 830 *first_ucode_section = 0;
e2d6f4e7
EH		 831 } else {
832 shift_param = 16;
034846cf 833 (*first_ucode_section)++;
e2d6f4e7
EH		 834 }
835
eef187a7 836 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 837 last_read_idx = i;
838
a6c4fb44
MG		 839 /*
840 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
841 * CPU1 to CPU2.
842 * PAGING_SEPARATOR_SECTION delimiter - separate between
843 * CPU2 non paged to CPU2 paging sec.
844 */
034846cf 845 if (!image->sec[i].data ||
a6c4fb44
MG		 846 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
847 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 848 IWL_DEBUG_FW(trans,
849 "Break since Data not valid or Empty section, sec = %d\n",
850 i);
189fa2fa 851 break;
034846cf
EH		 852 }
853
189fa2fa
EH		 854 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
855 if (ret)
856 return ret;
dcab8ecd 857
d6a2c5c7 858 /* Notify ucode of loaded section number and status */
eda50cde
SS		 859 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
860 val = val | (sec_num << shift_param);
861 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
862
dcab8ecd 863 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 864 }
865
034846cf
EH		 866 *first_ucode_section = last_read_idx;
867
2aabdbdc
EG		 868 iwl_enable_interrupts(trans);
869
d6a2c5c7
SS		 870 if (trans->cfg->use_tfh) {
871 if (cpu == 1)
872 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
873 0xFFFF);
874 else
875 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
876 0xFFFFFFFF);
877 } else {
878 if (cpu == 1)
879 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
880 0xFFFF);
881 else
882 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
883 0xFFFFFFFF);
884 }
afb88917 885
189fa2fa
EH		 886 return 0;
887}
e2d6f4e7 888
189fa2fa
EH		 889static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
890 const struct fw_img *image,
034846cf
EH		 891 int cpu,
892 int *first_ucode_section)
189fa2fa 893{
189fa2fa 894 int i, ret = 0;
034846cf 895 u32 last_read_idx = 0;
189fa2fa 896
3ce4a038 897 if (cpu == 1)
034846cf 898 *first_ucode_section = 0;
3ce4a038 899 else
034846cf 900 (*first_ucode_section)++;
189fa2fa 901
eef187a7 902 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 903 last_read_idx = i;
904
a6c4fb44
MG		 905 /*
906 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
907 * CPU1 to CPU2.
908 * PAGING_SEPARATOR_SECTION delimiter - separate between
909 * CPU2 non paged to CPU2 paging sec.
910 */
034846cf 911 if (!image->sec[i].data ||
a6c4fb44
MG		 912 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
913 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 914 IWL_DEBUG_FW(trans,
915 "Break since Data not valid or Empty section, sec = %d\n",
916 i);
189fa2fa 917 break;
034846cf
EH		 918 }
919
189fa2fa
EH		 920 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
921 if (ret)
922 return ret;
e2d6f4e7
EH		 923 }
924
034846cf
EH		 925 *first_ucode_section = last_read_idx;
926
e2d6f4e7
EH		 927 return 0;
928}
929
c9be849d 930void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7
LK		 931{
932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
fd527eb5 933 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
09e350f7
LK		 934 int i;
935
09e350f7
LK		 936 IWL_INFO(trans, "Applying debug destination %s\n",
937 get_fw_dbg_mode_string(dest->monitor_mode));
938
939 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 940 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 941 else
942 IWL_WARN(trans, "PCI should have external buffer debug\n");
943
944 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
945 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
946 u32 val = le32_to_cpu(dest->reg_ops[i].val);
947
948 switch (dest->reg_ops[i].op) {
949 case CSR_ASSIGN:
950 iwl_write32(trans, addr, val);
951 break;
952 case CSR_SETBIT:
953 iwl_set_bit(trans, addr, BIT(val));
954 break;
955 case CSR_CLEARBIT:
956 iwl_clear_bit(trans, addr, BIT(val));
957 break;
958 case PRPH_ASSIGN:
959 iwl_write_prph(trans, addr, val);
960 break;
961 case PRPH_SETBIT:
962 iwl_set_bits_prph(trans, addr, BIT(val));
963 break;
964 case PRPH_CLEARBIT:
965 iwl_clear_bits_prph(trans, addr, BIT(val));
966 break;
869f3b15
HD		 967 case PRPH_BLOCKBIT:
968 if (iwl_read_prph(trans, addr) & BIT(val)) {
969 IWL_ERR(trans,
970 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
971 val, addr);
972 goto monitor;
973 }
974 break;
09e350f7
LK		 975 default:
976 IWL_ERR(trans, "FW debug - unknown OP %d\n",
977 dest->reg_ops[i].op);
978 break;
979 }
980 }
981
869f3b15 982monitor:
09e350f7
LK		 983 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
984 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
985 trans_pcie->fw_mon_phys >> dest->base_shift);
6e584873 986 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d
EG		 987 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
988 (trans_pcie->fw_mon_phys +
989 trans_pcie->fw_mon_size - 256) >>
990 dest->end_shift);
991 else
992 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
993 (trans_pcie->fw_mon_phys +
994 trans_pcie->fw_mon_size) >>
995 dest->end_shift);
09e350f7
LK		 996 }
997}
998
7afe3705 999static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 1000 const struct fw_img *image)
cf614297 1001{
c2d20201 1002 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 1003 int ret = 0;
034846cf 1004 int first_ucode_section;
cf614297 1005
dcab8ecd 1006 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 1007 image->is_dual_cpus ? "Dual" : "Single");
1008
dcab8ecd
EH		 1009 /* load to FW the binary non secured sections of CPU1 */
1010 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1011 if (ret)
1012 return ret;
e2d6f4e7
EH		 1013
1014 if (image->is_dual_cpus) {
189fa2fa
EH		 1015 /* set CPU2 header address */
1016 iwl_write_prph(trans,
1017 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1018 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1019
189fa2fa 1020 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1021 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1022 &first_ucode_section);
189fa2fa
EH		 1023 if (ret)
1024 return ret;
e2d6f4e7 1025 }
cf614297 1026
c2d20201
EG		 1027 /* supported for 7000 only for the moment */
1028 if (iwlwifi_mod_params.fw_monitor &&
1029 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1030 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1031
1032 if (trans_pcie->fw_mon_size) {
1033 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1034 trans_pcie->fw_mon_phys >> 4);
1035 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1036 (trans_pcie->fw_mon_phys +
1037 trans_pcie->fw_mon_size) >> 4);
1038 }
09e350f7
LK		 1039 } else if (trans->dbg_dest_tlv) {
1040 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1041 }
1042
2aabdbdc
EG		 1043 iwl_enable_interrupts(trans);
1044
e12ba844 1045 /* release CPU reset */
5dd9c68a 1046 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1047
dcab8ecd
EH		 1048 return 0;
1049}
189fa2fa 1050
5dd9c68a
EG		 1051static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1052 const struct fw_img *image)
dcab8ecd
EH		 1053{
1054 int ret = 0;
1055 int first_ucode_section;
dcab8ecd
EH		 1056
1057 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1058 image->is_dual_cpus ? "Dual" : "Single");
1059
a2227ce2
EG		 1060 if (trans->dbg_dest_tlv)
1061 iwl_pcie_apply_destination(trans);
1062
82ea7966
SS		 1063 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1064 iwl_read_prph(trans, WFPM_GP2));
1065
1066 /*
1067 * Set default value. On resume reading the values that were
1068 * zeored can provide debug data on the resume flow.
1069 * This is for debugging only and has no functional impact.
1070 */
1071 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1072
dcab8ecd
EH		 1073 /* configure the ucode to be ready to get the secured image */
1074 /* release CPU reset */
1075 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1076
1077 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1078 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1079 &first_ucode_section);
dcab8ecd
EH		 1080 if (ret)
1081 return ret;
1082
1083 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1084 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1085 &first_ucode_section);
cf614297
EG		 1086}
1087
9ad8fd0b 1088bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1089{
326477e4 1090 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1091 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1092 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1093 bool report;
727c02df 1094
326477e4
JB		 1095 if (hw_rfkill) {
1096 set_bit(STATUS_RFKILL_HW, &trans->status);
1097 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1098 } else {
1099 clear_bit(STATUS_RFKILL_HW, &trans->status);
1100 if (trans_pcie->opmode_down)
1101 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1102 }
1103
1104 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1105
326477e4
JB		 1106 if (prev != report)
1107 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1108
1109 return hw_rfkill;
1110}
1111
7ca00409
HD		 1112struct iwl_causes_list {
1113 u32 cause_num;
1114 u32 mask_reg;
1115 u8 addr;
1116};
1117
1118static struct iwl_causes_list causes_list[] = {
1119 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1120 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1121 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1122 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1123 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1124 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1125 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1126 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1127 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1128 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1129 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1130 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1131 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1132 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1133};
1134
9b58419e
GBA		 1135static struct iwl_causes_list causes_list_v2[] = {
1136 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1137 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1138 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1139 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1140 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1141 {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1142 {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15},
1143 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1144 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1145 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1146 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1147 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1148 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1149 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1150};
1151
7ca00409
HD		 1152static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1153{
1154 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1155 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
9b58419e
GBA		 1156 int i, arr_size =
1157 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1158 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
7ca00409
HD		 1159
1160 /*
1161 * Access all non RX causes and map them to the default irq.
1162 * In case we are missing at least one interrupt vector,
1163 * the first interrupt vector will serve non-RX and FBQ causes.
1164 */
9b58419e
GBA		 1165 for (i = 0; i < arr_size; i++) {
1166 struct iwl_causes_list *causes =
1167 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1168 causes_list : causes_list_v2;
1169
1170 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1171 iwl_clear_bit(trans, causes[i].mask_reg,
1172 causes[i].cause_num);
7ca00409
HD		 1173 }
1174}
1175
1176static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1177{
1178 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1179 u32 offset =
1180 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1181 u32 val, idx;
1182
1183 /*
1184 * The first RX queue - fallback queue, which is designated for
1185 * management frame, command responses etc, is always mapped to the
1186 * first interrupt vector. The other RX queues are mapped to
1187 * the other (N - 2) interrupt vectors.
1188 */
1189 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1190 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1191 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1192 MSIX_FH_INT_CAUSES_Q(idx - offset));
1193 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1194 }
1195 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1196
1197 val = MSIX_FH_INT_CAUSES_Q(0);
1198 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1199 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1200 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1201
1202 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1203 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1204}
1205
77c09bc8 1206void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1207{
1208 struct iwl_trans *trans = trans_pcie->trans;
1209
1210 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1211 if (trans->cfg->mq_rx_supported &&
1212 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1213 iwl_write_prph(trans, UREG_CHICK,
1214 UREG_CHICK_MSI_ENABLE);
1215 return;
1216 }
d7270d61
HD		 1217 /*
1218 * The IVAR table needs to be configured again after reset,
1219 * but if the device is disabled, we can't write to
1220 * prph.
1221 */
1222 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1223 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1224
1225 /*
1226 * Each cause from the causes list above and the RX causes is
1227 * represented as a byte in the IVAR table. The first nibble
1228 * represents the bound interrupt vector of the cause, the second
1229 * represents no auto clear for this cause. This will be set if its
1230 * interrupt vector is bound to serve other causes.
1231 */
1232 iwl_pcie_map_rx_causes(trans);
1233
1234 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1235}
1236
1237static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1238{
1239 struct iwl_trans *trans = trans_pcie->trans;
1240
1241 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1242
83730058
HD		 1243 if (!trans_pcie->msix_enabled)
1244 return;
1245
1246 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1247 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1248 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1249 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1250}
1251
fa9f3281 1252static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1253{
43e58856 1254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1255
fa9f3281
EG		 1256 lockdep_assert_held(&trans_pcie->mutex);
1257
1258 if (trans_pcie->is_down)
1259 return;
1260
1261 trans_pcie->is_down = true;
1262
0232d2cd
SS		 1263 /* Stop dbgc before stopping device */
1264 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1265 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1266 } else {
1267 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1268 udelay(100);
1269 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1270 }
1271
43e58856 1272 /* tell the device to stop sending interrupts */
ae2c30bf 1273 iwl_disable_interrupts(trans);
ae2c30bf 1274
ab6cf8e8 1275 /* device going down, Stop using ICT table */
990aa6d7 1276 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1277
1278 /*
1279 * If a HW restart happens during firmware loading,
1280 * then the firmware loading might call this function
1281 * and later it might be called again due to the
1282 * restart. So don't process again if the device is
1283 * already dead.
1284 */
31b8b343 1285 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1286 IWL_DEBUG_INFO(trans,
1287 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1288 iwl_pcie_tx_stop(trans);
9805c446 1289 iwl_pcie_rx_stop(trans);
6379103e 1290
ab6cf8e8 1291 /* Power-down device's busmaster DMA clocks */
95411d04 1292 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1293 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1294 APMG_CLK_VAL_DMA_CLK_RQT);
1295 udelay(5);
1296 }
ab6cf8e8
EG		 1297 }
1298
1299 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1300 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1301 BIT(trans->cfg->csr->flag_mac_access_req));
ab6cf8e8
EG		 1302
1303 /* Stop the device, and put it in low power state */
b7aaeae4 1304 iwl_pcie_apm_stop(trans, false);
43e58856 1305
870c2a11 1306 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1307
f4a1f04a
GBA		 1308 /*
1309 * Upon stop, the IVAR table gets erased, so msi-x won't
1310 * work. This causes a bug in RF-KILL flows, since the interrupt
1311 * that enables radio won't fire on the correct irq, and the
1312 * driver won't be able to handle the interrupt.
1313 * Configure the IVAR table again after reset.
1314 */
1315 iwl_pcie_conf_msix_hw(trans_pcie);
1316
03d6c3b0
EG		 1317 /*
1318 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1319 * This is a bug in certain verions of the hardware.
1320 * Certain devices also keep sending HW RF kill interrupt all
1321 * the time, unless the interrupt is ACKed even if the interrupt
1322 * should be masked. Re-ACK all the interrupts here.
43e58856 1323 */
43e58856 1324 iwl_disable_interrupts(trans);
43e58856 1325
74fda971 1326 /* clear all status bits */
eb7ff77e
AN		 1327 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1328 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1329 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1330
1331 /*
1332 * Even if we stop the HW, we still want the RF kill
1333 * interrupt
1334 */
1335 iwl_enable_rfkill_int(trans);
1336
a6bd005f 1337 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1338 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1339}
1340
eda50cde 1341void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1342{
1343 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1344
1345 if (trans_pcie->msix_enabled) {
1346 int i;
1347
496d83ca 1348 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1349 synchronize_irq(trans_pcie->msix_entries[i].vector);
1350 } else {
1351 synchronize_irq(trans_pcie->pci_dev->irq);
1352 }
1353}
1354
a6bd005f
EG		 1355static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1356 const struct fw_img *fw, bool run_in_rfkill)
1357{
1358 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1359 bool hw_rfkill;
1360 int ret;
1361
1362 /* This may fail if AMT took ownership of the device */
1363 if (iwl_pcie_prepare_card_hw(trans)) {
1364 IWL_WARN(trans, "Exit HW not ready\n");
1365 ret = -EIO;
1366 goto out;
1367 }
1368
1369 iwl_enable_rfkill_int(trans);
1370
1371 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1372
1373 /*
1374 * We enabled the RF-Kill interrupt and the handler may very
1375 * well be running. Disable the interrupts to make sure no other
1376 * interrupt can be fired.
1377 */
1378 iwl_disable_interrupts(trans);
1379
1380 /* Make sure it finished running */
2e5d4a8f 1381 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1382
1383 mutex_lock(&trans_pcie->mutex);
1384
1385 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1386 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1387 if (hw_rfkill && !run_in_rfkill) {
1388 ret = -ERFKILL;
1389 goto out;
1390 }
1391
1392 /* Someone called stop_device, don't try to start_fw */
1393 if (trans_pcie->is_down) {
1394 IWL_WARN(trans,
1395 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1396 ret = -EIO;
a6bd005f
EG		 1397 goto out;
1398 }
1399
1400 /* make sure rfkill handshake bits are cleared */
1401 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1402 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1403 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1404
1405 /* clear (again), then enable host interrupts */
1406 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1407
1408 ret = iwl_pcie_nic_init(trans);
1409 if (ret) {
1410 IWL_ERR(trans, "Unable to init nic\n");
1411 goto out;
1412 }
1413
1414 /*
1415 * Now, we load the firmware and don't want to be interrupted, even
1416 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1417 * FH_TX interrupt which is needed to load the firmware). If the
1418 * RF-Kill switch is toggled, we will find out after having loaded
1419 * the firmware and return the proper value to the caller.
1420 */
1421 iwl_enable_fw_load_int(trans);
1422
1423 /* really make sure rfkill handshake bits are cleared */
1424 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1425 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1426
1427 /* Load the given image to the HW */
6e584873 1428 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1429 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1430 else
1431 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1432
1433 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1434 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1435 if (hw_rfkill && !run_in_rfkill)
1436 ret = -ERFKILL;
1437
1438out:
1439 mutex_unlock(&trans_pcie->mutex);
1440 return ret;
1441}
1442
1443static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1444{
1445 iwl_pcie_reset_ict(trans);
1446 iwl_pcie_tx_start(trans, scd_addr);
1447}
1448
326477e4
JB		 1449void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1450 bool was_in_rfkill)
1451{
1452 bool hw_rfkill;
1453
1454 /*
1455 * Check again since the RF kill state may have changed while
1456 * all the interrupts were disabled, in this case we couldn't
1457 * receive the RF kill interrupt and update the state in the
1458 * op_mode.
1459 * Don't call the op_mode if the rkfill state hasn't changed.
1460 * This allows the op_mode to call stop_device from the rfkill
1461 * notification without endless recursion. Under very rare
1462 * circumstances, we might have a small recursion if the rfkill
1463 * state changed exactly now while we were called from stop_device.
1464 * This is very unlikely but can happen and is supported.
1465 */
1466 hw_rfkill = iwl_is_rfkill_set(trans);
1467 if (hw_rfkill) {
1468 set_bit(STATUS_RFKILL_HW, &trans->status);
1469 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1470 } else {
1471 clear_bit(STATUS_RFKILL_HW, &trans->status);
1472 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1473 }
1474 if (hw_rfkill != was_in_rfkill)
1475 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1476}
1477
fa9f3281
EG		 1478static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1479{
1480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1481 bool was_in_rfkill;
fa9f3281
EG		 1482
1483 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1484 trans_pcie->opmode_down = true;
1485 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
fa9f3281 1486 _iwl_trans_pcie_stop_device(trans, low_power);
326477e4 1487 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1488 mutex_unlock(&trans_pcie->mutex);
1489}
1490
14cfca71
JB		 1491void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1492{
fa9f3281
EG		 1493 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1494 IWL_TRANS_GET_PCIE_TRANS(trans);
1495
1496 lockdep_assert_held(&trans_pcie->mutex);
1497
326477e4
JB		 1498 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1499 state ? "disabled" : "enabled");
77c09bc8
SS		 1500 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1501 if (trans->cfg->gen2)
1502 _iwl_trans_pcie_gen2_stop_device(trans, true);
1503 else
1504 _iwl_trans_pcie_stop_device(trans, true);
1505 }
ab6cf8e8
EG		 1506}
1507
23ae6128
MG		 1508static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1509 bool reset)
2dd4f9f7 1510{
23ae6128 1511 if (!reset) {
6dfb36c8
EP		 1512 /* Enable persistence mode to avoid reset */
1513 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1514 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1515 }
1516
2dd4f9f7 1517 iwl_disable_interrupts(trans);
debff618
JB		 1518
1519 /*
1520 * in testing mode, the host stays awake and the
1521 * hardware won't be reset (not even partially)
1522 */
1523 if (test)
1524 return;
1525
ddaf5a5b
JB		 1526 iwl_pcie_disable_ict(trans);
1527
2e5d4a8f 1528 iwl_pcie_synchronize_irqs(trans);
33b56af1 1529
2dd4f9f7 1530 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1531 BIT(trans->cfg->csr->flag_mac_access_req));
ddaf5a5b 1532 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1533 BIT(trans->cfg->csr->flag_init_done));
ddaf5a5b 1534
1316d595
SS		 1535 iwl_pcie_enable_rx_wake(trans, false);
1536
23ae6128 1537 if (reset) {
6dfb36c8
EP		 1538 /*
1539 * reset TX queues -- some of their registers reset during S3
1540 * so if we don't reset everything here the D3 image would try
1541 * to execute some invalid memory upon resume
1542 */
1543 iwl_trans_pcie_tx_reset(trans);
1544 }
ddaf5a5b
JB		 1545
1546 iwl_pcie_set_pwr(trans, true);
1547}
1548
1549static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1550 enum iwl_d3_status *status,
23ae6128 1551 bool test, bool reset)
ddaf5a5b 1552{
d7270d61 1553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1554 u32 val;
1555 int ret;
1556
debff618
JB		 1557 if (test) {
1558 iwl_enable_interrupts(trans);
1559 *status = IWL_D3_STATUS_ALIVE;
1560 return 0;
1561 }
1562
1316d595
SS		 1563 iwl_pcie_enable_rx_wake(trans, true);
1564
ddaf5a5b 1565 /*
d7270d61
HD		 1566 * Reconfigure IVAR table in case of MSIX or reset ict table in
1567 * MSI mode since HW reset erased it.
1568 * Also enables interrupts - none will happen as
1569 * the device doesn't know we're waking it up, only when
1570 * the opmode actually tells it after this call.
ddaf5a5b 1571 */
d7270d61
HD		 1572 iwl_pcie_conf_msix_hw(trans_pcie);
1573 if (!trans_pcie->msix_enabled)
1574 iwl_pcie_reset_ict(trans);
18dcb9a9 1575 iwl_enable_interrupts(trans);
ddaf5a5b 1576
a8cbb46f
GBA		 1577 iwl_set_bit(trans, CSR_GP_CNTRL,
1578 BIT(trans->cfg->csr->flag_mac_access_req));
1579 iwl_set_bit(trans, CSR_GP_CNTRL,
1580 BIT(trans->cfg->csr->flag_init_done));
ddaf5a5b 1581
6e584873 1582 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28
EG		 1583 udelay(2);
1584
ddaf5a5b 1585 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 1586 BIT(trans->cfg->csr->flag_mac_clock_ready),
1587 BIT(trans->cfg->csr->flag_mac_clock_ready),
ddaf5a5b 1588 25000);
7f2ac8fb 1589 if (ret < 0) {
ddaf5a5b
JB		 1590 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1591 return ret;
1592 }
1593
a3ead656
EG		 1594 iwl_pcie_set_pwr(trans, false);
1595
23ae6128 1596 if (!reset) {
6dfb36c8 1597 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1598 BIT(trans->cfg->csr->flag_mac_access_req));
6dfb36c8
EP		 1599 } else {
1600 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1601
6dfb36c8
EP		 1602 ret = iwl_pcie_rx_init(trans);
1603 if (ret) {
1604 IWL_ERR(trans,
1605 "Failed to resume the device (RX reset)\n");
1606 return ret;
1607 }
ddaf5a5b
JB		 1608 }
1609
82ea7966
SS		 1610 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1611 iwl_read_prph(trans, WFPM_GP2));
1612
a3ead656
EG		 1613 val = iwl_read32(trans, CSR_RESET);
1614 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1615 *status = IWL_D3_STATUS_RESET;
1616 else
1617 *status = IWL_D3_STATUS_ALIVE;
1618
ddaf5a5b 1619 return 0;
2dd4f9f7
JB		 1620}
1621
2e5d4a8f
HD		 1622static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1623 struct iwl_trans *trans)
1624{
1625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1626 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1627 u16 pci_cmd;
2e5d4a8f 1628
06f4b081
SS		 1629 if (!trans->cfg->mq_rx_supported)
1630 goto enable_msi;
1631
ab1068d6 1632 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1633 for (i = 0; i < max_irqs; i++)
1634 trans_pcie->msix_entries[i].entry = i;
496d83ca 1635
06f4b081
SS		 1636 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1637 MSIX_MIN_INTERRUPT_VECTORS,
1638 max_irqs);
1639 if (num_irqs < 0) {
2e5d4a8f 1640 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1641 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1642 num_irqs);
1643 goto enable_msi;
1644 }
1645 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1646
06f4b081
SS		 1647 IWL_DEBUG_INFO(trans,
1648 "MSI-X enabled. %d interrupt vectors were allocated\n",
1649 num_irqs);
1650
1651 /*
1652 * In case the OS provides fewer interrupts than requested, different
1653 * causes will share the same interrupt vector as follows:
1654 * One interrupt less: non rx causes shared with FBQ.
1655 * Two interrupts less: non rx causes shared with FBQ and RSS.
1656 * More than two interrupts: we will use fewer RSS queues.
1657 */
ab1068d6 1658 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1659 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1660 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1661 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1662 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1663 trans_pcie->trans->num_rx_queues = num_irqs;
1664 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1665 } else {
1666 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1667 }
ab1068d6 1668 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1669
06f4b081
SS		 1670 trans_pcie->alloc_vecs = num_irqs;
1671 trans_pcie->msix_enabled = true;
1672 return;
1673
1674enable_msi:
1675 ret = pci_enable_msi(pdev);
1676 if (ret) {
1677 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1678 /* enable rfkill interrupt: hw bug w/a */
1679 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1680 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1681 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1682 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1683 }
1684 }
1685}
1686
7c8d91eb
HD		 1687static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1688{
1689 int iter_rx_q, i, ret, cpu, offset;
1690 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1691
1692 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1693 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1694 offset = 1 + i;
1695 for (; i < iter_rx_q ; i++) {
1696 /*
1697 * Get the cpu prior to the place to search
1698 * (i.e. return will be > i - 1).
1699 */
1700 cpu = cpumask_next(i - offset, cpu_online_mask);
1701 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1702 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1703 &trans_pcie->affinity_mask[i]);
1704 if (ret)
1705 IWL_ERR(trans_pcie->trans,
1706 "Failed to set affinity mask for IRQ %d\n",
1707 i);
1708 }
1709}
1710
64fa3aff
SD		 1711static const char *queue_name(struct device *dev,
1712 struct iwl_trans_pcie *trans_p, int i)
1713{
1714 if (trans_p->shared_vec_mask) {
1715 int vec = trans_p->shared_vec_mask &
1716 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1717
1718 if (i == 0)
1719 return DRV_NAME ": shared IRQ";
1720
1721 return devm_kasprintf(dev, GFP_KERNEL,
1722 DRV_NAME ": queue %d", i + vec);
1723 }
1724 if (i == 0)
1725 return DRV_NAME ": default queue";
1726
1727 if (i == trans_p->alloc_vecs - 1)
1728 return DRV_NAME ": exception";
1729
1730 return devm_kasprintf(dev, GFP_KERNEL,
1731 DRV_NAME ": queue %d", i);
1732}
1733
2e5d4a8f
HD		 1734static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1735 struct iwl_trans_pcie *trans_pcie)
1736{
496d83ca 1737 int i;
2e5d4a8f 1738
496d83ca 1739 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1740 int ret;
5a41a86c 1741 struct msix_entry *msix_entry;
64fa3aff
SD		 1742 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1743
1744 if (!qname)
1745 return -ENOMEM;
5a41a86c
SD		 1746
1747 msix_entry = &trans_pcie->msix_entries[i];
1748 ret = devm_request_threaded_irq(&pdev->dev,
1749 msix_entry->vector,
1750 iwl_pcie_msix_isr,
1751 (i == trans_pcie->def_irq) ?
1752 iwl_pcie_irq_msix_handler :
1753 iwl_pcie_irq_rx_msix_handler,
1754 IRQF_SHARED,
64fa3aff 1755 qname,
5a41a86c 1756 msix_entry);
2e5d4a8f 1757 if (ret) {
2e5d4a8f
HD		 1758 IWL_ERR(trans_pcie->trans,
1759 "Error allocating IRQ %d\n", i);
5a41a86c 1760
2e5d4a8f
HD		 1761 return ret;
1762 }
1763 }
7c8d91eb 1764 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1765
1766 return 0;
1767}
1768
fa9f3281 1769static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1770{
fa9f3281 1771 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1772 int err;
e6bb4c9c 1773
fa9f3281
EG		 1774 lockdep_assert_held(&trans_pcie->mutex);
1775
7afe3705 1776 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1777 if (err) {
d6f1c316 1778 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1779 return err;
ebb7678d 1780 }
a6c684ee 1781
870c2a11 1782 iwl_trans_pcie_sw_reset(trans);
2997494f 1783
52b6e168
EG		 1784 err = iwl_pcie_apm_init(trans);
1785 if (err)
1786 return err;
a6c684ee 1787
2e5d4a8f 1788 iwl_pcie_init_msix(trans_pcie);
83730058 1789
226c02ca
EG		 1790 /* From now on, the op_mode will be kept updated about RF kill state */
1791 iwl_enable_rfkill_int(trans);
1792
326477e4
JB		 1793 trans_pcie->opmode_down = false;
1794
fa9f3281
EG		 1795 /* Set is_down to false here so that...*/
1796 trans_pcie->is_down = false;
1797
727c02df 1798 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1799 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1800
4cbb8e50
LC		 1801 /* Make sure we sync here, because we'll need full access later */
1802 if (low_power)
1803 pm_runtime_resume(trans->dev);
1804
a8b691e6 1805 return 0;
e6bb4c9c
EG		 1806}
1807
fa9f3281
EG		 1808static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1809{
1810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1811 int ret;
1812
1813 mutex_lock(&trans_pcie->mutex);
1814 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1815 mutex_unlock(&trans_pcie->mutex);
1816
1817 return ret;
1818}
1819
a4082843 1820static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1821{
20d3b647 1822 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1823
fa9f3281
EG		 1824 mutex_lock(&trans_pcie->mutex);
1825
a4082843 1826 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1827 iwl_disable_interrupts(trans);
ee7d737c 1828
b7aaeae4 1829 iwl_pcie_apm_stop(trans, true);
cc56feb2 1830
218733cf 1831 iwl_disable_interrupts(trans);
1df06bdc 1832
8d96bb61 1833 iwl_pcie_disable_ict(trans);
33b56af1 1834
fa9f3281 1835 mutex_unlock(&trans_pcie->mutex);
33b56af1 1836
2e5d4a8f 1837 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1838}
1839
03905495
EG		 1840static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1841{
05f5b97e 1842 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1843}
1844
1845static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1846{
05f5b97e 1847 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1848}
1849
1850static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1851{
05f5b97e 1852 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1853}
1854
6a06b6c1
EG		 1855static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1856{
f9477c17
AP		 1857 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1858 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1859 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1860}
1861
1862static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1863 u32 val)
1864{
1865 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1866 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1867 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1868}
1869
c6f600fc 1870static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1871 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1872{
1873 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1874
1875 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1876 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1877 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1878 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1879 trans_pcie->n_no_reclaim_cmds = 0;
1880 else
1881 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1882 if (trans_pcie->n_no_reclaim_cmds)
1883 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1884 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1885
6c4fbcbc
EG		 1886 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1887 trans_pcie->rx_page_order =
1888 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1889
046db346 1890 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1891 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1892 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1893
21cb3222
JB		 1894 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1895 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1896
39bdb17e
SD		 1897 trans->command_groups = trans_cfg->command_groups;
1898 trans->command_groups_size = trans_cfg->command_groups_size;
1899
f14d6b39
JB		 1900 /* Initialize NAPI here - it should be before registering to mac80211
1901 * in the opmode but after the HW struct is allocated.
1902 * As this function may be called again in some corner cases don't
1903 * do anything if NAPI was already initialized.
1904 */
bce97731 1905 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1906 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1907}
1908
d1ff5253 1909void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1910{
20d3b647 1911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1912 int i;
a42a1844 1913
2e5d4a8f 1914 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1915
13a3a390
SS		 1916 if (trans->cfg->gen2)
1917 iwl_pcie_gen2_tx_free(trans);
1918 else
1919 iwl_pcie_tx_free(trans);
9805c446 1920 iwl_pcie_rx_free(trans);
6379103e 1921
10a54d81
LC		 1922 if (trans_pcie->rba.alloc_wq) {
1923 destroy_workqueue(trans_pcie->rba.alloc_wq);
1924 trans_pcie->rba.alloc_wq = NULL;
1925 }
1926
2e5d4a8f 1927 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1928 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1929 irq_set_affinity_hint(
1930 trans_pcie->msix_entries[i].vector,
1931 NULL);
7c8d91eb 1932 }
2e5d4a8f 1933
2e5d4a8f
HD		 1934 trans_pcie->msix_enabled = false;
1935 } else {
2e5d4a8f 1936 iwl_pcie_free_ict(trans);
2e5d4a8f 1937 }
a42a1844 1938
c2d20201
EG		 1939 iwl_pcie_free_fw_monitor(trans);
1940
6eb5e529
EG		 1941 for_each_possible_cpu(i) {
1942 struct iwl_tso_hdr_page *p =
1943 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1944
1945 if (p->page)
1946 __free_page(p->page);
1947 }
1948
1949 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1950 mutex_destroy(&trans_pcie->mutex);
7b501d10 1951 iwl_trans_free(trans);
34c1b7ba
EG		 1952}
1953
47107e84
DF		 1954static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1955{
47107e84 1956 if (state)
eb7ff77e 1957 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1958 else
eb7ff77e 1959 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1960}
1961
49564a80
LC		 1962struct iwl_trans_pcie_removal {
1963 struct pci_dev *pdev;
1964 struct work_struct work;
1965};
1966
1967static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1968{
1969 struct iwl_trans_pcie_removal *removal =
1970 container_of(wk, struct iwl_trans_pcie_removal, work);
1971 struct pci_dev *pdev = removal->pdev;
1972 char *prop[] = {"EVENT=INACCESSIBLE", NULL};
1973
1974 dev_err(&pdev->dev, "Device gone - attempting removal\n");
1975 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1976 pci_lock_rescan_remove();
1977 pci_dev_put(pdev);
1978 pci_stop_and_remove_bus_device(pdev);
1979 pci_unlock_rescan_remove();
1980
1981 kfree(removal);
1982 module_put(THIS_MODULE);
1983}
1984
23ba9340
EG		 1985static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1986 unsigned long *flags)
7a65d170
EG		 1987{
1988 int ret;
cfb4e624
JB		 1989 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1990
1991 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1992
fc8a350d 1993 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1994 goto out;
1995
7a65d170 1996 /* this bit wakes up the NIC */
e139dc4a 1997 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1998 BIT(trans->cfg->csr->flag_mac_access_req));
6e584873 1999 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 2000 udelay(2);
7a65d170
EG		 2001
2002 /*
2003 * These bits say the device is running, and should keep running for
2004 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2005 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 2006 * HW with volatile SRAM must save/restore contents to/from
2007 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 2008 * Each direction takes approximately 1/4 millisecond; with this
2009 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2010 * series of register accesses are expected (e.g. reading Event Log),
2011 * to keep device from sleeping.
2012 *
2013 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2014 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 2015 * is just for hardware register access; but GP1 MAC_SLEEP
2016 * check is a good idea before accessing the SRAM of HW with
2017 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2018 *
2019 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2020 * and do not save/restore SRAM when power cycling.
2021 */
2022 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 2023 BIT(trans->cfg->csr->flag_val_mac_access_en),
2024 (BIT(trans->cfg->csr->flag_mac_clock_ready) |
7a65d170
EG		 2025 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2026 if (unlikely(ret < 0)) {
49564a80
LC		 2027 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2028
23ba9340
EG		 2029 WARN_ONCE(1,
2030 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2031 cntrl);
2032
2033 iwl_trans_pcie_dump_regs(trans);
2034
2035 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2036 struct iwl_trans_pcie_removal *removal;
2037
2038 if (trans_pcie->scheduled_for_removal)
2039 goto err;
2040
2041 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2042
2043 /*
2044 * get a module reference to avoid doing this
2045 * while unloading anyway and to avoid
2046 * scheduling a work with code that's being
2047 * removed.
2048 */
2049 if (!try_module_get(THIS_MODULE)) {
2050 IWL_ERR(trans,
2051 "Module is being unloaded - abort\n");
2052 goto err;
2053 }
2054
2055 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2056 if (!removal) {
2057 module_put(THIS_MODULE);
2058 goto err;
2059 }
2060 /*
2061 * we don't need to clear this flag, because
2062 * the trans will be freed and reallocated.
2063 */
2064 trans_pcie->scheduled_for_removal = true;
2065
2066 removal->pdev = to_pci_dev(trans->dev);
2067 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2068 pci_dev_get(removal->pdev);
2069 schedule_work(&removal->work);
2070 } else {
2071 iwl_write32(trans, CSR_RESET,
2072 CSR_RESET_REG_FLAG_FORCE_NMI);
2073 }
2074
2075err:
23ba9340
EG		 2076 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2077 return false;
7a65d170
EG		 2078 }
2079
b9439491 2080out:
e56b04ef
LE		 2081 /*
2082 * Fool sparse by faking we release the lock - sparse will
2083 * track nic_access anyway.
2084 */
cfb4e624 2085 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2086 return true;
2087}
2088
e56b04ef
LE		 2089static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2090 unsigned long *flags)
7a65d170 2091{
cfb4e624 2092 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2093
cfb4e624 2094 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2095
2096 /*
2097 * Fool sparse by faking we acquiring the lock - sparse will
2098 * track nic_access anyway.
2099 */
cfb4e624 2100 __acquire(&trans_pcie->reg_lock);
e56b04ef 2101
fc8a350d 2102 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2103 goto out;
2104
e139dc4a 2105 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 2106 BIT(trans->cfg->csr->flag_mac_access_req));
7a65d170
EG		 2107 /*
2108 * Above we read the CSR_GP_CNTRL register, which will flush
2109 * any previous writes, but we need the write that clears the
2110 * MAC_ACCESS_REQ bit to be performed before any other writes
2111 * scheduled on different CPUs (after we drop reg_lock).
2112 */
2113 mmiowb();
b9439491 2114out:
cfb4e624 2115 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2116}
2117
4fd442db
EG		 2118static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2119 void *buf, int dwords)
2120{
2121 unsigned long flags;
2122 int offs, ret = 0;
2123 u32 *vals = buf;
2124
23ba9340 2125 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2126 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2127 for (offs = 0; offs < dwords; offs++)
2128 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2129 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2130 } else {
2131 ret = -EBUSY;
2132 }
4fd442db
EG		 2133 return ret;
2134}
2135
2136static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2137 const void *buf, int dwords)
4fd442db
EG		 2138{
2139 unsigned long flags;
2140 int offs, ret = 0;
bf0fd5da 2141 const u32 *vals = buf;
4fd442db 2142
23ba9340 2143 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2144 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2145 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2146 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2147 vals ? vals[offs] : 0);
e56b04ef 2148 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2149 } else {
2150 ret = -EBUSY;
2151 }
4fd442db
EG		 2152 return ret;
2153}
7a65d170 2154
e0b8d405
EG		 2155static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2156 unsigned long txqs,
2157 bool freeze)
2158{
2159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2160 int queue;
2161
2162 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2163 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2164 unsigned long now;
2165
2166 spin_lock_bh(&txq->lock);
2167
2168 now = jiffies;
2169
2170 if (txq->frozen == freeze)
2171 goto next_queue;
2172
2173 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2174 freeze ? "Freezing" : "Waking", queue);
2175
2176 txq->frozen = freeze;
2177
bb98ecd4 2178 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2179 goto next_queue;
2180
2181 if (freeze) {
2182 if (unlikely(time_after(now,
2183 txq->stuck_timer.expires))) {
2184 /*
2185 * The timer should have fired, maybe it is
2186 * spinning right now on the lock.
2187 */
2188 goto next_queue;
2189 }
2190 /* remember how long until the timer fires */
2191 txq->frozen_expiry_remainder =
2192 txq->stuck_timer.expires - now;
2193 del_timer(&txq->stuck_timer);
2194 goto next_queue;
2195 }
2196
2197 /*
2198 * Wake a non-empty queue -> arm timer with the
2199 * remainder before it froze
2200 */
2201 mod_timer(&txq->stuck_timer,
2202 now + txq->frozen_expiry_remainder);
2203
2204next_queue:
2205 spin_unlock_bh(&txq->lock);
2206 }
2207}
2208
0cd58eaa
EG		 2209static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2210{
2211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2212 int i;
2213
2214 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2215 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2216
2217 if (i == trans_pcie->cmd_queue)
2218 continue;
2219
2220 spin_lock_bh(&txq->lock);
2221
2222 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2223 txq->block--;
2224 if (!txq->block) {
2225 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2226 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2227 }
2228 } else if (block) {
2229 txq->block++;
2230 }
2231
2232 spin_unlock_bh(&txq->lock);
2233 }
2234}
2235
5f178cd2
EG		 2236#define IWL_FLUSH_WAIT_MS 2000
2237
38398efb
SS		 2238void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2239{
afb84431
EG		 2240 u32 txq_id = txq->id;
2241 u32 status;
2242 bool active;
2243 u8 fifo;
38398efb 2244
afb84431
EG		 2245 if (trans->cfg->use_tfh) {
2246 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2247 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2248 /* TODO: access new SCD registers and dump them */
2249 return;
38398efb 2250 }
afb84431
EG		 2251
2252 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2253 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2254 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2255
2256 IWL_ERR(trans,
2257 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2258 txq_id, active ? "" : "in", fifo,
2259 jiffies_to_msecs(txq->wd_timeout),
2260 txq->read_ptr, txq->write_ptr,
2261 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
7b3e42ea 2262 (trans->cfg->base_params->max_tfd_queue_size - 1),
afb84431 2263 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
7b3e42ea 2264 (trans->cfg->base_params->max_tfd_queue_size - 1),
afb84431 2265 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2266}
2267
92536c96
SS		 2268static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2269 struct iwl_trans_rxq_dma_data *data)
2270{
2271 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2272
2273 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2274 return -EINVAL;
2275
2276 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2277 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2278 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2279 data->fr_bd_wid = 0;
2280
2281 return 0;
2282}
2283
d6d517b7 2284static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2285{
8ad71bef 2286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2287 struct iwl_txq *txq;
5f178cd2 2288 unsigned long now = jiffies;
d6d517b7
SS		 2289 u8 wr_ptr;
2290
2291 if (!test_bit(txq_idx, trans_pcie->queue_used))
2292 return -EINVAL;
2293
2294 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2295 txq = trans_pcie->txq[txq_idx];
6aa7de05 2296 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2297
6aa7de05 2298 while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
d6d517b7
SS		 2299 !time_after(jiffies,
2300 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2301 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7
SS		 2302
2303 if (WARN_ONCE(wr_ptr != write_ptr,
2304 "WR pointer moved while flushing %d -> %d\n",
2305 wr_ptr, write_ptr))
2306 return -ETIMEDOUT;
2307 usleep_range(1000, 2000);
2308 }
2309
2310 if (txq->read_ptr != txq->write_ptr) {
2311 IWL_ERR(trans,
2312 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2313 iwl_trans_pcie_log_scd_error(trans, txq);
2314 return -ETIMEDOUT;
2315 }
2316
2317 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2318
2319 return 0;
2320}
2321
2322static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2323{
2324 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2325 int cnt;
5f178cd2
EG		 2326 int ret = 0;
2327
2328 /* waiting for all the tx frames complete might take a while */
035f7ff2 2329 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd 2330
9ba1947a 2331 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2332 continue;
3cafdbe6
EG		 2333 if (!test_bit(cnt, trans_pcie->queue_used))
2334 continue;
2335 if (!(BIT(cnt) & txq_bm))
2336 continue;
748fa67c 2337
d6d517b7
SS		 2338 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2339 if (ret)
5f178cd2 2340 break;
5f178cd2 2341 }
1c3fea82 2342
5f178cd2
EG		 2343 return ret;
2344}
2345
e139dc4a
LE		 2346static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2347 u32 mask, u32 value)
2348{
e56b04ef 2349 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2350 unsigned long flags;
2351
e56b04ef 2352 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2353 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2354 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2355}
2356
c24c7f58 2357static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2358{
2359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2360
2361 if (iwlwifi_mod_params.d0i3_disable)
2362 return;
2363
b3ff1270 2364 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2365
2366#ifdef CONFIG_PM
2367 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2368 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2369#endif /* CONFIG_PM */
7616f334
EP		 2370}
2371
c24c7f58 2372static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2373{
2374 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2375
2376 if (iwlwifi_mod_params.d0i3_disable)
2377 return;
2378
b3ff1270
LC		 2379 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2380 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2381
5d93f3a2
LC		 2382#ifdef CONFIG_PM
2383 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2384 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2385#endif /* CONFIG_PM */
7616f334
EP		 2386}
2387
ff620849
EG		 2388static const char *get_csr_string(int cmd)
2389{
d9fb6465 2390#define IWL_CMD(x) case x: return #x
ff620849
EG		 2391 switch (cmd) {
2392 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2393 IWL_CMD(CSR_INT_COALESCING);
2394 IWL_CMD(CSR_INT);
2395 IWL_CMD(CSR_INT_MASK);
2396 IWL_CMD(CSR_FH_INT_STATUS);
2397 IWL_CMD(CSR_GPIO_IN);
2398 IWL_CMD(CSR_RESET);
2399 IWL_CMD(CSR_GP_CNTRL);
2400 IWL_CMD(CSR_HW_REV);
2401 IWL_CMD(CSR_EEPROM_REG);
2402 IWL_CMD(CSR_EEPROM_GP);
2403 IWL_CMD(CSR_OTP_GP_REG);
2404 IWL_CMD(CSR_GIO_REG);
2405 IWL_CMD(CSR_GP_UCODE_REG);
2406 IWL_CMD(CSR_GP_DRIVER_REG);
2407 IWL_CMD(CSR_UCODE_DRV_GP1);
2408 IWL_CMD(CSR_UCODE_DRV_GP2);
2409 IWL_CMD(CSR_LED_REG);
2410 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2411 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2412 IWL_CMD(CSR_ANA_PLL_CFG);
2413 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2414 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2415 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2416 default:
2417 return "UNKNOWN";
2418 }
d9fb6465 2419#undef IWL_CMD
ff620849
EG		 2420}
2421
990aa6d7 2422void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2423{
2424 int i;
2425 static const u32 csr_tbl[] = {
2426 CSR_HW_IF_CONFIG_REG,
2427 CSR_INT_COALESCING,
2428 CSR_INT,
2429 CSR_INT_MASK,
2430 CSR_FH_INT_STATUS,
2431 CSR_GPIO_IN,
2432 CSR_RESET,
2433 CSR_GP_CNTRL,
2434 CSR_HW_REV,
2435 CSR_EEPROM_REG,
2436 CSR_EEPROM_GP,
2437 CSR_OTP_GP_REG,
2438 CSR_GIO_REG,
2439 CSR_GP_UCODE_REG,
2440 CSR_GP_DRIVER_REG,
2441 CSR_UCODE_DRV_GP1,
2442 CSR_UCODE_DRV_GP2,
2443 CSR_LED_REG,
2444 CSR_DRAM_INT_TBL_REG,
2445 CSR_GIO_CHICKEN_BITS,
2446 CSR_ANA_PLL_CFG,
a812cba9 2447 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2448 CSR_HW_REV_WA_REG,
2449 CSR_DBG_HPET_MEM_REG
2450 };
2451 IWL_ERR(trans, "CSR values:\n");
2452 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2453 "CSR_INT_PERIODIC_REG)\n");
2454 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2455 IWL_ERR(trans, " %25s: 0X%08x\n",
2456 get_csr_string(csr_tbl[i]),
1042db2a 2457 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2458 }
2459}
2460
87e5666c
EG		 2461#ifdef CONFIG_IWLWIFI_DEBUGFS
2462/* create and remove of files */
2463#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2464 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2465 &iwl_dbgfs_##name##_ops)) \
9da987ac 2466 goto err; \
87e5666c
EG		 2467} while (0)
2468
2469/* file operation */
87e5666c 2470#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2471static const struct file_operations iwl_dbgfs_##name##_ops = { \
2472 .read = iwl_dbgfs_##name##_read, \
234e3405 2473 .open = simple_open, \
87e5666c
EG		 2474 .llseek = generic_file_llseek, \
2475};
2476
16db88ba 2477#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2478static const struct file_operations iwl_dbgfs_##name##_ops = { \
2479 .write = iwl_dbgfs_##name##_write, \
234e3405 2480 .open = simple_open, \
16db88ba
EG		 2481 .llseek = generic_file_llseek, \
2482};
2483
87e5666c 2484#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2485static const struct file_operations iwl_dbgfs_##name##_ops = { \
2486 .write = iwl_dbgfs_##name##_write, \
2487 .read = iwl_dbgfs_##name##_read, \
234e3405 2488 .open = simple_open, \
87e5666c
EG		 2489 .llseek = generic_file_llseek, \
2490};
2491
87e5666c 2492static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2493 char __user *user_buf,
2494 size_t count, loff_t *ppos)
8ad71bef 2495{
5a878bf6 2496 struct iwl_trans *trans = file->private_data;
8ad71bef 2497 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2498 struct iwl_txq *txq;
87e5666c
EG		 2499 char *buf;
2500 int pos = 0;
2501 int cnt;
2502 int ret;
1745e440
WYG		 2503 size_t bufsz;
2504
e0b8d405 2505 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2506
b2a3b1c1 2507 if (!trans_pcie->txq_memory)
87e5666c 2508 return -EAGAIN;
f9e75447 2509
87e5666c
EG		 2510 buf = kzalloc(bufsz, GFP_KERNEL);
2511 if (!buf)
2512 return -ENOMEM;
2513
035f7ff2 2514 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2515 txq = trans_pcie->txq[cnt];
87e5666c 2516 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2517 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2518 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2519 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2520 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2521 txq->need_update, txq->frozen,
f40faf62 2522 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2523 }
2524 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2525 kfree(buf);
2526 return ret;
2527}
2528
2529static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2530 char __user *user_buf,
2531 size_t count, loff_t *ppos)
2532{
5a878bf6 2533 struct iwl_trans *trans = file->private_data;
20d3b647 2534 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2535 char *buf;
2536 int pos = 0, i, ret;
2537 size_t bufsz = sizeof(buf);
2538
2539 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2540
2541 if (!trans_pcie->rxq)
2542 return -EAGAIN;
2543
2544 buf = kzalloc(bufsz, GFP_KERNEL);
2545 if (!buf)
2546 return -ENOMEM;
2547
2548 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2549 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2550
2551 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2552 i);
2553 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2554 rxq->read);
2555 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2556 rxq->write);
2557 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2558 rxq->write_actual);
2559 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2560 rxq->need_update);
2561 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2562 rxq->free_count);
2563 if (rxq->rb_stts) {
0307c839
GBA		 2564 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2565 rxq));
78485054
SS		 2566 pos += scnprintf(buf + pos, bufsz - pos,
2567 "\tclosed_rb_num: %u\n",
0307c839 2568 r & 0x0FFF);
78485054
SS		 2569 } else {
2570 pos += scnprintf(buf + pos, bufsz - pos,
2571 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2572 }
87e5666c 2573 }
78485054
SS		 2574 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2575 kfree(buf);
2576
2577 return ret;
87e5666c
EG		 2578}
2579
1f7b6172
EG		 2580static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2581 char __user *user_buf,
20d3b647
JB		 2582 size_t count, loff_t *ppos)
2583{
1f7b6172 2584 struct iwl_trans *trans = file->private_data;
20d3b647 2585 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2586 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2587
2588 int pos = 0;
2589 char *buf;
2590 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2591 ssize_t ret;
2592
2593 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2594 if (!buf)
1f7b6172 2595 return -ENOMEM;
1f7b6172
EG		 2596
2597 pos += scnprintf(buf + pos, bufsz - pos,
2598 "Interrupt Statistics Report:\n");
2599
2600 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2601 isr_stats->hw);
2602 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2603 isr_stats->sw);
2604 if (isr_stats->sw || isr_stats->hw) {
2605 pos += scnprintf(buf + pos, bufsz - pos,
2606 "\tLast Restarting Code: 0x%X\n",
2607 isr_stats->err_code);
2608 }
2609#ifdef CONFIG_IWLWIFI_DEBUG
2610 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2611 isr_stats->sch);
2612 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2613 isr_stats->alive);
2614#endif
2615 pos += scnprintf(buf + pos, bufsz - pos,
2616 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2617
2618 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2619 isr_stats->ctkill);
2620
2621 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2622 isr_stats->wakeup);
2623
2624 pos += scnprintf(buf + pos, bufsz - pos,
2625 "Rx command responses:\t\t %u\n", isr_stats->rx);
2626
2627 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2628 isr_stats->tx);
2629
2630 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2631 isr_stats->unhandled);
2632
2633 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2634 kfree(buf);
2635 return ret;
2636}
2637
2638static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2639 const char __user *user_buf,
2640 size_t count, loff_t *ppos)
2641{
2642 struct iwl_trans *trans = file->private_data;
20d3b647 2643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2644 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2645 u32 reset_flag;
078f1131 2646 int ret;
1f7b6172 2647
078f1131
JB		 2648 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2649 if (ret)
2650 return ret;
1f7b6172
EG		 2651 if (reset_flag == 0)
2652 memset(isr_stats, 0, sizeof(*isr_stats));
2653
2654 return count;
2655}
2656
16db88ba 2657static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2658 const char __user *user_buf,
2659 size_t count, loff_t *ppos)
16db88ba
EG		 2660{
2661 struct iwl_trans *trans = file->private_data;
16db88ba 2662
990aa6d7 2663 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2664
2665 return count;
2666}
2667
16db88ba 2668static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2669 char __user *user_buf,
2670 size_t count, loff_t *ppos)
16db88ba
EG		 2671{
2672 struct iwl_trans *trans = file->private_data;
94543a8d 2673 char *buf = NULL;
56c2477f 2674 ssize_t ret;
16db88ba 2675
56c2477f
JB		 2676 ret = iwl_dump_fh(trans, &buf);
2677 if (ret < 0)
2678 return ret;
2679 if (!buf)
2680 return -EINVAL;
2681 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2682 kfree(buf);
16db88ba
EG		 2683 return ret;
2684}
2685
fa4de7f7
JB		 2686static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2687 char __user *user_buf,
2688 size_t count, loff_t *ppos)
2689{
2690 struct iwl_trans *trans = file->private_data;
2691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2692 char buf[100];
2693 int pos;
2694
2695 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2696 trans_pcie->debug_rfkill,
2697 !(iwl_read32(trans, CSR_GP_CNTRL) &
2698 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2699
2700 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2701}
2702
2703static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2704 const char __user *user_buf,
2705 size_t count, loff_t *ppos)
2706{
2707 struct iwl_trans *trans = file->private_data;
2708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2709 bool old = trans_pcie->debug_rfkill;
2710 int ret;
2711
2712 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2713 if (ret)
2714 return ret;
2715 if (old == trans_pcie->debug_rfkill)
2716 return count;
2717 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2718 old, trans_pcie->debug_rfkill);
2719 iwl_pcie_handle_rfkill_irq(trans);
2720
2721 return count;
2722}
2723
1f7b6172 2724DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2725DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2726DEBUGFS_READ_FILE_OPS(rx_queue);
2727DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2728DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2729DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2730
f8a1edb7
JB		 2731/* Create the debugfs files and directories */
2732int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2733{
f8a1edb7
JB		 2734 struct dentry *dir = trans->dbgfs_dir;
2735
2ef00c53
JP		 2736 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2737 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2738 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2739 DEBUGFS_ADD_FILE(csr, dir, 0200);
2740 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2741 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
87e5666c 2742 return 0;
9da987ac
MV		 2743
2744err:
2745 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2746 return -ENOMEM;
87e5666c 2747}
aadede6e 2748#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2749
6983ba69 2750static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2751{
3cd1980b 2752 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2753 u32 cmdlen = 0;
2754 int i;
2755
3cd1980b 2756 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2757 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2758
2759 return cmdlen;
2760}
2761
bd7fc617
EG		 2762static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2763 struct iwl_fw_error_dump_data **data,
2764 int allocated_rb_nums)
2765{
2766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2767 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2768 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2769 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2770 u32 i, r, j, rb_len = 0;
2771
2772 spin_lock(&rxq->lock);
2773
0307c839 2774 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2775
2776 for (i = rxq->read, j = 0;
2777 i != r && j < allocated_rb_nums;
2778 i = (i + 1) & RX_QUEUE_MASK, j++) {
2779 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2780 struct iwl_fw_error_dump_rb *rb;
2781
2782 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2783 DMA_FROM_DEVICE);
2784
2785 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2786
2787 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2788 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2789 rb = (void *)(*data)->data;
2790 rb->index = cpu_to_le32(i);
2791 memcpy(rb->data, page_address(rxb->page), max_len);
2792 /* remap the page for the free benefit */
2793 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2794 max_len,
2795 DMA_FROM_DEVICE);
2796
2797 *data = iwl_fw_error_next_data(*data);
2798 }
2799
2800 spin_unlock(&rxq->lock);
2801
2802 return rb_len;
2803}
473ad712
EG		 2804#define IWL_CSR_TO_DUMP (0x250)
2805
2806static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2807 struct iwl_fw_error_dump_data **data)
2808{
2809 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2810 __le32 *val;
2811 int i;
2812
2813 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2814 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2815 val = (void *)(*data)->data;
2816
2817 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2818 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2819
2820 *data = iwl_fw_error_next_data(*data);
2821
2822 return csr_len;
2823}
2824
06d51e0d
LK		 2825static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2826 struct iwl_fw_error_dump_data **data)
2827{
2828 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2829 unsigned long flags;
2830 __le32 *val;
2831 int i;
2832
23ba9340 2833 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2834 return 0;
2835
2836 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2837 (*data)->len = cpu_to_le32(fh_regs_len);
2838 val = (void *)(*data)->data;
2839
723b45e2
LK		 2840 if (!trans->cfg->gen2)
2841 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2842 i += sizeof(u32))
2843 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2844 else
2845 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2846 i += sizeof(u32))
2847 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2848 i));
06d51e0d
LK		 2849
2850 iwl_trans_release_nic_access(trans, &flags);
2851
2852 *data = iwl_fw_error_next_data(*data);
2853
2854 return sizeof(**data) + fh_regs_len;
2855}
2856
cc79ef66
LK		 2857static u32
2858iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2859 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2860 u32 monitor_len)
2861{
2862 u32 buf_size_in_dwords = (monitor_len >> 2);
2863 u32 *buffer = (u32 *)fw_mon_data->data;
2864 unsigned long flags;
2865 u32 i;
2866
23ba9340 2867 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2868 return 0;
2869
14ef1b43 2870 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2871 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2872 buffer[i] = iwl_read_prph_no_grab(trans,
2873 MON_DMARB_RD_DATA_ADDR);
2874 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2875
2876 iwl_trans_release_nic_access(trans, &flags);
2877
2878 return monitor_len;
2879}
2880
36fb9017
OG		 2881static u32
2882iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2883 struct iwl_fw_error_dump_data **data,
2884 u32 monitor_len)
2885{
2886 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2887 u32 len = 0;
2888
2889 if ((trans_pcie->fw_mon_page &&
2890 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2891 trans->dbg_dest_tlv) {
2892 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2893 u32 base, write_ptr, wrap_cnt;
2894
2895 /* If there was a dest TLV - use the values from there */
2896 if (trans->dbg_dest_tlv) {
2897 write_ptr =
2898 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2899 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2900 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2901 } else {
2902 base = MON_BUFF_BASE_ADDR;
2903 write_ptr = MON_BUFF_WRPTR;
2904 wrap_cnt = MON_BUFF_CYCLE_CNT;
2905 }
2906
2907 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2908 fw_mon_data = (void *)(*data)->data;
2909 fw_mon_data->fw_mon_wr_ptr =
2910 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2911 fw_mon_data->fw_mon_cycle_cnt =
2912 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2913 fw_mon_data->fw_mon_base_ptr =
2914 cpu_to_le32(iwl_read_prph(trans, base));
2915
2916 len += sizeof(**data) + sizeof(*fw_mon_data);
2917 if (trans_pcie->fw_mon_page) {
2918 /*
2919 * The firmware is now asserted, it won't write anything
2920 * to the buffer. CPU can take ownership to fetch the
2921 * data. The buffer will be handed back to the device
2922 * before the firmware will be restarted.
2923 */
2924 dma_sync_single_for_cpu(trans->dev,
2925 trans_pcie->fw_mon_phys,
2926 trans_pcie->fw_mon_size,
2927 DMA_FROM_DEVICE);
2928 memcpy(fw_mon_data->data,
2929 page_address(trans_pcie->fw_mon_page),
2930 trans_pcie->fw_mon_size);
2931
2932 monitor_len = trans_pcie->fw_mon_size;
2933 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2934 /*
2935 * Update pointers to reflect actual values after
2936 * shifting
2937 */
fd527eb5
GBA		 2938 if (trans->dbg_dest_tlv->version) {
2939 base = (iwl_read_prph(trans, base) &
2940 IWL_LDBG_M2S_BUF_BA_MSK) <<
2941 trans->dbg_dest_tlv->base_shift;
2942 base *= IWL_M2S_UNIT_SIZE;
2943 base += trans->cfg->smem_offset;
2944 } else {
2945 base = iwl_read_prph(trans, base) <<
2946 trans->dbg_dest_tlv->base_shift;
2947 }
2948
36fb9017
OG		 2949 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2950 monitor_len / sizeof(u32));
2951 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2952 monitor_len =
2953 iwl_trans_pci_dump_marbh_monitor(trans,
2954 fw_mon_data,
2955 monitor_len);
2956 } else {
2957 /* Didn't match anything - output no monitor data */
2958 monitor_len = 0;
2959 }
2960
2961 len += monitor_len;
2962 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2963 }
2964
2965 return len;
2966}
2967
2968static struct iwl_trans_dump_data
2969*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2970 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2971{
2972 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2973 struct iwl_fw_error_dump_data *data;
b2a3b1c1 2974 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
4d075007 2975 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2976 struct iwl_trans_dump_data *dump_data;
514c3069 2977 u32 len, num_rbs = 0;
99684ae3 2978 u32 monitor_len;
4d075007 2979 int i, ptr;
96a6497b
SS		 2980 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2981 !trans->cfg->mq_rx_supported;
4d075007 2982
473ad712
EG		 2983 /* transport dump header */
2984 len = sizeof(*dump_data);
2985
2986 /* host commands */
2987 len += sizeof(*data) +
bb98ecd4 2988 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2989
473ad712 2990 /* FW monitor */
99684ae3 2991 if (trans_pcie->fw_mon_page) {
c544e9c4 2992 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2993 trans_pcie->fw_mon_size;
2994 monitor_len = trans_pcie->fw_mon_size;
2995 } else if (trans->dbg_dest_tlv) {
fd527eb5 2996 u32 base, end, cfg_reg;
99684ae3 2997
fd527eb5
GBA		 2998 if (trans->dbg_dest_tlv->version == 1) {
2999 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3000 cfg_reg = iwl_read_prph(trans, cfg_reg);
3001 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3002 trans->dbg_dest_tlv->base_shift;
3003 base *= IWL_M2S_UNIT_SIZE;
3004 base += trans->cfg->smem_offset;
99684ae3 3005
fd527eb5
GBA		 3006 monitor_len =
3007 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3008 trans->dbg_dest_tlv->end_shift;
3009 monitor_len *= IWL_M2S_UNIT_SIZE;
3010 } else {
3011 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3012 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
99684ae3 3013
fd527eb5
GBA		 3014 base = iwl_read_prph(trans, base) <<
3015 trans->dbg_dest_tlv->base_shift;
3016 end = iwl_read_prph(trans, end) <<
3017 trans->dbg_dest_tlv->end_shift;
3018
3019 /* Make "end" point to the actual end */
3020 if (trans->cfg->device_family >=
3021 IWL_DEVICE_FAMILY_8000 ||
3022 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
3023 end += (1 << trans->dbg_dest_tlv->end_shift);
3024 monitor_len = end - base;
3025 }
99684ae3
LK		 3026 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
3027 monitor_len;
3028 } else {
3029 monitor_len = 0;
3030 }
c2d20201 3031
36fb9017
OG		 3032 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
3033 dump_data = vzalloc(len);
3034 if (!dump_data)
3035 return NULL;
3036
3037 data = (void *)dump_data->data;
3038 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3039 dump_data->len = len;
3040
3041 return dump_data;
3042 }
3043
3044 /* CSR registers */
3045 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3046
36fb9017 3047 /* FH registers */
723b45e2
LK		 3048 if (trans->cfg->gen2)
3049 len += sizeof(*data) +
3050 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
3051 else
3052 len += sizeof(*data) +
3053 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
36fb9017
OG		 3054
3055 if (dump_rbs) {
78485054
SS		 3056 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3057 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3058 /* RBs */
0307c839
GBA		 3059 num_rbs =
3060 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3061 & 0x0FFF;
78485054 3062 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3063 len += num_rbs * (sizeof(*data) +
3064 sizeof(struct iwl_fw_error_dump_rb) +
3065 (PAGE_SIZE << trans_pcie->rx_page_order));
3066 }
3067
5538409b
LK		 3068 /* Paged memory for gen2 HW */
3069 if (trans->cfg->gen2)
3070 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
3071 len += sizeof(*data) +
3072 sizeof(struct iwl_fw_error_dump_paging) +
3073 trans_pcie->init_dram.paging[i].size;
3074
48eb7b34
EG		 3075 dump_data = vzalloc(len);
3076 if (!dump_data)
3077 return NULL;
4d075007
JB		 3078
3079 len = 0;
48eb7b34 3080 data = (void *)dump_data->data;
4d075007
JB		 3081 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3082 txcmd = (void *)data->data;
3083 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 3084 ptr = cmdq->write_ptr;
3085 for (i = 0; i < cmdq->n_window; i++) {
4ecab561 3086 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
4d075007
JB		 3087 u32 caplen, cmdlen;
3088
6983ba69
SS		 3089 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
3090 trans_pcie->tfd_size * ptr);
4d075007
JB		 3091 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3092
3093 if (cmdlen) {
3094 len += sizeof(*txcmd) + caplen;
3095 txcmd->cmdlen = cpu_to_le32(cmdlen);
3096 txcmd->caplen = cpu_to_le32(caplen);
3097 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
3098 txcmd = (void *)((u8 *)txcmd->data + caplen);
3099 }
3100
7b3e42ea 3101 ptr = iwl_queue_dec_wrap(trans, ptr);
4d075007
JB		 3102 }
3103 spin_unlock_bh(&cmdq->lock);
3104
3105 data->len = cpu_to_le32(len);
c2d20201 3106 len += sizeof(*data);
67c65f2c
EG		 3107 data = iwl_fw_error_next_data(data);
3108
473ad712 3109 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 3110 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3111 if (dump_rbs)
3112 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3113
5538409b
LK		 3114 /* Paged memory for gen2 HW */
3115 if (trans->cfg->gen2) {
3116 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
3117 struct iwl_fw_error_dump_paging *paging;
3118 dma_addr_t addr =
3119 trans_pcie->init_dram.paging[i].physical;
3120 u32 page_len = trans_pcie->init_dram.paging[i].size;
3121
3122 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3123 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3124 paging = (void *)data->data;
3125 paging->index = cpu_to_le32(i);
3126 dma_sync_single_for_cpu(trans->dev, addr, page_len,
3127 DMA_BIDIRECTIONAL);
3128 memcpy(paging->data,
3129 trans_pcie->init_dram.paging[i].block, page_len);
3130 data = iwl_fw_error_next_data(data);
3131
3132 len += sizeof(*data) + sizeof(*paging) + page_len;
3133 }
3134 }
3135
36fb9017 3136 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3137
48eb7b34
EG		 3138 dump_data->len = len;
3139
3140 return dump_data;
4d075007 3141}
87e5666c 3142
4cbb8e50
LC		 3143#ifdef CONFIG_PM_SLEEP
3144static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3145{
e4c49c49
LC		 3146 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3147 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3148 return iwl_pci_fw_enter_d0i3(trans);
3149
3150 return 0;
3151}
3152
3153static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3154{
e4c49c49
LC		 3155 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3156 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3157 iwl_pci_fw_exit_d0i3(trans);
3158}
3159#endif /* CONFIG_PM_SLEEP */
3160
623e7766
SS		 3161#define IWL_TRANS_COMMON_OPS \
3162 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3163 .write8 = iwl_trans_pcie_write8, \
3164 .write32 = iwl_trans_pcie_write32, \
3165 .read32 = iwl_trans_pcie_read32, \
3166 .read_prph = iwl_trans_pcie_read_prph, \
3167 .write_prph = iwl_trans_pcie_write_prph, \
3168 .read_mem = iwl_trans_pcie_read_mem, \
3169 .write_mem = iwl_trans_pcie_write_mem, \
3170 .configure = iwl_trans_pcie_configure, \
3171 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3172 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3173 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3174 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3175 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3176 .ref = iwl_trans_pcie_ref, \
3177 .unref = iwl_trans_pcie_unref, \
3178 .dump_data = iwl_trans_pcie_dump_data, \
fb12777a 3179 .dump_regs = iwl_trans_pcie_dump_regs, \
623e7766
SS		 3180 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3181 .d3_resume = iwl_trans_pcie_d3_resume
3182
3183#ifdef CONFIG_PM_SLEEP
3184#define IWL_TRANS_PM_OPS \
3185 .suspend = iwl_trans_pcie_suspend, \
3186 .resume = iwl_trans_pcie_resume,
3187#else
3188#define IWL_TRANS_PM_OPS
3189#endif /* CONFIG_PM_SLEEP */
3190
d1ff5253 3191static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3192 IWL_TRANS_COMMON_OPS,
3193 IWL_TRANS_PM_OPS
57a1dc89 3194 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3195 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3196 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3197 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3198
623e7766 3199 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3200
623e7766
SS		 3201 .tx = iwl_trans_pcie_tx,
3202 .reclaim = iwl_trans_pcie_reclaim,
3203
3204 .txq_disable = iwl_trans_pcie_txq_disable,
3205 .txq_enable = iwl_trans_pcie_txq_enable,
3206
3207 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3208
d6d517b7
SS		 3209 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3210
623e7766
SS		 3211 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3212 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3213};
3214
3215static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3216 IWL_TRANS_COMMON_OPS,
3217 IWL_TRANS_PM_OPS
3218 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3219 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3220 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3221 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3222
ca60da2e 3223 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3224
ab6c6445 3225 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3226 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3227
6b35ff91
SS		 3228 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3229 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3230 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3231 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
e6bb4c9c 3232};
a42a1844 3233
87ce05a2 3234struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 3235 const struct pci_device_id *ent,
3236 const struct iwl_cfg *cfg)
a42a1844 3237{
a42a1844
EG		 3238 struct iwl_trans_pcie *trans_pcie;
3239 struct iwl_trans *trans;
96a6497b 3240 int ret, addr_size;
a42a1844 3241
5a41a86c
SD		 3242 ret = pcim_enable_device(pdev);
3243 if (ret)
3244 return ERR_PTR(ret);
3245
623e7766
SS		 3246 if (cfg->gen2)
3247 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3248 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3249 else
3250 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3251 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 3252 if (!trans)
3253 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3254
3255 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3256
a42a1844 3257 trans_pcie->trans = trans;
326477e4 3258 trans_pcie->opmode_down = true;
7b11488f 3259 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3260 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3261 mutex_init(&trans_pcie->mutex);
13df1aab 3262 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 3263 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3264 if (!trans_pcie->tso_hdr_page) {
3265 ret = -ENOMEM;
3266 goto out_no_pci;
3267 }
a42a1844 3268
d819c6cf 3269
f2532b04
EG		 3270 if (!cfg->base_params->pcie_l1_allowed) {
3271 /*
3272 * W/A - seems to solve weird behavior. We need to remove this
3273 * if we don't want to stay in L1 all the time. This wastes a
3274 * lot of power.
3275 */
3276 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3277 PCIE_LINK_STATE_L1 |
3278 PCIE_LINK_STATE_CLKPM);
3279 }
a42a1844 3280
6983ba69 3281 if (cfg->use_tfh) {
2c6262b7 3282 addr_size = 64;
3cd1980b 3283 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3284 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3285 } else {
2c6262b7 3286 addr_size = 36;
3cd1980b 3287 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3288 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3289 }
3cd1980b
SS		 3290 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3291
a42a1844
EG		 3292 pci_set_master(pdev);
3293
96a6497b 3294 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3295 if (!ret)
96a6497b
SS		 3296 ret = pci_set_consistent_dma_mask(pdev,
3297 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3298 if (ret) {
3299 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3300 if (!ret)
3301 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3302 DMA_BIT_MASK(32));
a42a1844 3303 /* both attempts failed: */
af3f2f74 3304 if (ret) {
6a4b09f8 3305 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3306 goto out_no_pci;
a42a1844
EG		 3307 }
3308 }
3309
5a41a86c 3310 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3311 if (ret) {
5a41a86c
SD		 3312 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3313 goto out_no_pci;
a42a1844
EG		 3314 }
3315
5a41a86c 3316 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3317 if (!trans_pcie->hw_base) {
5a41a86c 3318 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3319 ret = -ENODEV;
5a41a86c 3320 goto out_no_pci;
a42a1844
EG		 3321 }
3322
a42a1844
EG		 3323 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3324 * PCI Tx retries from interfering with C3 CPU state */
3325 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3326
83f7a85f
EG		 3327 trans_pcie->pci_dev = pdev;
3328 iwl_disable_interrupts(trans);
3329
08079a49 3330 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3331 /*
3332 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3333 * changed, and now the revision step also includes bit 0-1 (no more
3334 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3335 * in the old format.
3336 */
6e584873 3337 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
7a42baa6 3338 unsigned long flags;
7a42baa6 3339
b513ee7f 3340 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3341 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3342
f9e5554c
EG		 3343 ret = iwl_pcie_prepare_card_hw(trans);
3344 if (ret) {
3345 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3346 goto out_no_pci;
f9e5554c
EG		 3347 }
3348
7a42baa6
EH		 3349 /*
3350 * in-order to recognize C step driver should read chip version
3351 * id located at the AUX bus MISC address space.
3352 */
3353 iwl_set_bit(trans, CSR_GP_CNTRL,
a8cbb46f 3354 BIT(trans->cfg->csr->flag_init_done));
7a42baa6
EH		 3355 udelay(2);
3356
3357 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 3358 BIT(trans->cfg->csr->flag_mac_clock_ready),
3359 BIT(trans->cfg->csr->flag_mac_clock_ready),
7a42baa6
EH		 3360 25000);
3361 if (ret < 0) {
3362 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3363 goto out_no_pci;
7a42baa6
EH		 3364 }
3365
23ba9340 3366 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3367 u32 hw_step;
3368
14ef1b43 3369 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3370 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3371 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3372 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3373 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3374 if (hw_step == 0x3)
3375 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3376 (SILICON_C_STEP << 2);
3377 iwl_trans_release_nic_access(trans, &flags);
3378 }
3379 }
3380
c00ee467
JB		 3381 /*
3382 * 9000-series integrated A-step has a problem with suspend/resume
3383 * and sometimes even causes the whole platform to get stuck. This
3384 * workaround makes the hardware not go into the problematic state.
3385 */
3386 if (trans->cfg->integrated &&
3387 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3388 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3389 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3390 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3391
f6586b69 3392#if IS_ENABLED(CONFIG_IWLMVM)
1afb0ae4 3393 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
33708052
LC		 3394
3395 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3396 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
f6586b69
TP		 3397 u32 hw_status;
3398
3399 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
33708052
LC		 3400 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP)
3401 /*
3402 * b step fw is the same for physical card and fpga
3403 */
3404 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
3405 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) &&
3406 CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) {
3407 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0;
3408 } else {
3409 /*
3410 * a step no FPGA
3411 */
2f7a3863 3412 trans->cfg = &iwl22000_2ac_cfg_hr;
33708052 3413 }
f6586b69
TP		 3414 }
3415#endif
1afb0ae4 3416
2e5d4a8f 3417 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3418 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3419 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3420 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3421
69a10b29 3422 /* Initialize the wait queue for commands */
f946b529 3423 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3424
4cbb8e50
LC		 3425 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3426
2e5d4a8f 3427 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3428 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3429 if (ret)
5a41a86c 3430 goto out_no_pci;
2e5d4a8f
HD		 3431 } else {
3432 ret = iwl_pcie_alloc_ict(trans);
3433 if (ret)
5a41a86c 3434 goto out_no_pci;
a8b691e6 3435
5a41a86c
SD		 3436 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3437 iwl_pcie_isr,
3438 iwl_pcie_irq_handler,
3439 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3440 if (ret) {
3441 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3442 goto out_free_ict;
3443 }
3444 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3445 }
83f7a85f 3446
10a54d81
LC		 3447 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3448 WQ_HIGHPRI | WQ_UNBOUND, 1);
3449 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3450
b3ff1270
LC		 3451#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3452 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3453#else
3454 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3455#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3456
a42a1844
EG		 3457 return trans;
3458
a8b691e6
JB		 3459out_free_ict:
3460 iwl_pcie_free_ict(trans);
a42a1844 3461out_no_pci:
6eb5e529 3462 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3463 iwl_trans_free(trans);
af3f2f74 3464 return ERR_PTR(ret);
a42a1844 3465}
Linux 6.x block layer and io_uring tree(s)