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iwlwifi: mvm: enable SF also when we have HE
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 11 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
c85eb619 22 * The full GNU General Public License is included in this distribution
410dc5aa 23 * in the file called COPYING.
c85eb619
EG		 24 *
25 * Contact Information:
cb2f8277 26 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
553452e5
LK		 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 34 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
a42a1844 64#include <linux/pci.h>
e6bb4c9c 65#include <linux/interrupt.h>
87e5666c 66#include <linux/debugfs.h>
cf614297 67#include <linux/sched.h>
6d8f6eeb
EG		 68#include <linux/bitops.h>
69#include <linux/gfp.h>
48eb7b34 70#include <linux/vmalloc.h>
49564a80 71#include <linux/module.h>
f7805b33 72#include <linux/wait.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
d962f9b1 80#include "fw/error-dump.h"
520f03ea 81#include "fw/dbg.h"
a89c72ff 82#include "fw/api/tx.h"
6468a01a 83#include "internal.h"
06d51e0d 84#include "iwl-fh.h"
0439bb62 85
fe45773b
AN		 86/* extended range in FW SRAM */
87#define IWL_FW_MEM_EXTENDED_START 0x40000
88#define IWL_FW_MEM_EXTENDED_END 0x57FFF
89
4290eaad 90void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad 91{
c4d3f2ee
LC		 92#define PCI_DUMP_SIZE 352
93#define PCI_MEM_DUMP_SIZE 64
94#define PCI_PARENT_DUMP_SIZE 524
95#define PREFIX_LEN 32
a6d24fad
RJ		 96 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
97 struct pci_dev *pdev = trans_pcie->pci_dev;
98 u32 i, pos, alloc_size, *ptr, *buf;
99 char *prefix;
100
101 if (trans_pcie->pcie_dbg_dumped_once)
102 return;
103
104 /* Should be a multiple of 4 */
105 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
c4d3f2ee
LC		 106 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
107 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
108
a6d24fad 109 /* Alloc a max size buffer */
c4d3f2ee
LC		 110 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
111 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
112 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
113 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
114
a6d24fad
RJ		 115 buf = kmalloc(alloc_size, GFP_ATOMIC);
116 if (!buf)
117 return;
118 prefix = (char *)buf + alloc_size - PREFIX_LEN;
119
120 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
121
122 /* Print wifi device registers */
123 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
124 IWL_ERR(trans, "iwlwifi device config registers:\n");
125 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
126 if (pci_read_config_dword(pdev, i, ptr))
127 goto err_read;
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
129
130 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
c4d3f2ee 131 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 132 *ptr = iwl_read32(trans, i);
133 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
134
135 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
136 if (pos) {
137 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
138 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
139 if (pci_read_config_dword(pdev, pos + i, ptr))
140 goto err_read;
141 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
142 32, 4, buf, i, 0);
143 }
144
145 /* Print parent device registers next */
146 if (!pdev->bus->self)
147 goto out;
148
149 pdev = pdev->bus->self;
150 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
151
152 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
153 pci_name(pdev));
c4d3f2ee 154 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 155 if (pci_read_config_dword(pdev, i, ptr))
156 goto err_read;
157 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
158
159 /* Print root port AER registers */
160 pos = 0;
161 pdev = pcie_find_root_port(pdev);
162 if (pdev)
163 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
164 if (pos) {
165 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
166 pci_name(pdev));
167 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
168 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
169 if (pci_read_config_dword(pdev, pos + i, ptr))
170 goto err_read;
171 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
172 4, buf, i, 0);
173 }
f3402d6d 174 goto out;
a6d24fad
RJ		 175
176err_read:
177 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
178 IWL_ERR(trans, "Read failed at 0x%X\n", i);
179out:
180 trans_pcie->pcie_dbg_dumped_once = 1;
181 kfree(buf);
182}
183
870c2a11
GBA		 184static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
185{
186 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
6dece0e9 187 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
870c2a11
GBA		 188 usleep_range(5000, 6000);
189}
190
c2d20201
EG		 191static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
192{
69f0e505 193 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 194
69f0e505
SM		 195 if (!fw_mon->size)
196 return;
197
198 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
199 fw_mon->physical);
200
201 fw_mon->block = NULL;
202 fw_mon->physical = 0;
203 fw_mon->size = 0;
c2d20201
EG		 204}
205
88964b2e
SS		 206static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
207 u8 max_power, u8 min_power)
c2d20201 208{
69f0e505
SM		 209 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
210 void *block = NULL;
211 dma_addr_t physical = 0;
96c285da 212 u32 size = 0;
c2d20201
EG		 213 u8 power;
214
69f0e505
SM		 215 if (fw_mon->size)
216 return;
217
88964b2e 218 for (power = max_power; power >= min_power; power--) {
c2d20201 219 size = BIT(power);
69f0e505
SM		 220 block = dma_alloc_coherent(trans->dev, size, &physical,
221 GFP_KERNEL | __GFP_NOWARN);
222 if (!block)
c2d20201
EG		 223 continue;
224
c2d20201 225 IWL_INFO(trans,
c5f97542
SM		 226 "Allocated 0x%08x bytes for firmware monitor.\n",
227 size);
c2d20201
EG		 228 break;
229 }
230
69f0e505 231 if (WARN_ON_ONCE(!block))
c2d20201
EG		 232 return;
233
96c285da
EG		 234 if (power != max_power)
235 IWL_ERR(trans,
236 "Sorry - debug buffer is only %luK while you requested %luK\n",
237 (unsigned long)BIT(power - 10),
238 (unsigned long)BIT(max_power - 10));
239
69f0e505
SM		 240 fw_mon->block = block;
241 fw_mon->physical = physical;
242 fw_mon->size = size;
88964b2e
SS		 243}
244
245void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
246{
247 if (!max_power) {
248 /* default max_power is maximum */
249 max_power = 26;
250 } else {
251 max_power += 11;
252 }
253
254 if (WARN(max_power > 26,
255 "External buffer size for monitor is too big %d, check the FW TLV\n",
256 max_power))
257 return;
258
69f0e505 259 if (trans->dbg.fw_mon.size)
88964b2e
SS		 260 return;
261
262 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
c2d20201
EG		 263}
264
a812cba9
AB		 265static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
266{
267 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
268 ((reg & 0x0000ffff) | (2 << 28)));
269 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
270}
271
272static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
273{
274 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
275 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
276 ((reg & 0x0000ffff) | (3 << 28)));
277}
278
ddaf5a5b 279static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 280{
66337b7c 281 if (trans->cfg->apmg_not_supported)
95411d04
AA		 282 return;
283
ddaf5a5b
JB		 284 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
285 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
286 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
287 ~APMG_PS_CTRL_MSK_PWR_SRC);
288 else
289 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
290 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
291 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 292}
293
af634bee
EG		 294/* PCI registers */
295#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 296
eda50cde 297void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 298{
20d3b647 299 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 300 u16 lctl;
9180ac50 301 u16 cap;
af634bee 302
af634bee 303 /*
cc894b85
LC		 304 * L0S states have been found to be unstable with our devices
305 * and in newer hardware they are not officially supported at
306 * all, so we must always set the L0S_DISABLED bit.
af634bee 307 */
cc894b85
LC		 308 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
309
7afe3705 310 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
438a0f0a 311 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 312
313 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
314 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 315 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
316 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
317 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 318}
319
a6c684ee
EG		 320/*
321 * Start up NIC's basic functionality after it has been reset
7afe3705 322 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 323 * NOTE: This does not load uCode nor start the embedded processor
324 */
7afe3705 325static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 326{
52b6e168
EG		 327 int ret;
328
a6c684ee
EG		 329 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
330
331 /*
332 * Use "set_bit" below rather than "write", to preserve any hardware
333 * bits already set by default after reset.
334 */
335
336 /* Disable L0S exit timer (platform NMI Work/Around) */
286ca8eb 337 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 338 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
339 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 340
341 /*
342 * Disable L0s without affecting L1;
343 * don't wait for ICH L0s (ICH bug W/A)
344 */
345 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 346 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 347
348 /* Set FH wait threshold to maximum (HW error during stress W/A) */
349 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
350
351 /*
352 * Enable HAP INTA (interrupt from management bus) to
353 * wake device's PCI Express link L1a -> L0s
354 */
355 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 356 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 357
7afe3705 358 iwl_pcie_apm_config(trans);
a6c684ee
EG		 359
360 /* Configure analog phase-lock-loop before activating to D0A */
286ca8eb 361 if (trans->trans_cfg->base_params->pll_cfg)
77d76931 362 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 363
7d34a7d7 364 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 365 if (ret)
52b6e168 366 return ret;
a6c684ee 367
2d93aee1
EG		 368 if (trans->cfg->host_interrupt_operation_mode) {
369 /*
370 * This is a bit of an abuse - This is needed for 7260 / 3160
371 * only check host_interrupt_operation_mode even if this is
372 * not related to host_interrupt_operation_mode.
373 *
374 * Enable the oscillator to count wake up time for L1 exit. This
375 * consumes slightly more power (100uA) - but allows to be sure
376 * that we wake up from L1 on time.
377 *
378 * This looks weird: read twice the same register, discard the
379 * value, set a bit, and yet again, read that same register
380 * just to discard the value. But that's the way the hardware
381 * seems to like it.
382 */
383 iwl_read_prph(trans, OSC_CLK);
384 iwl_read_prph(trans, OSC_CLK);
385 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
386 iwl_read_prph(trans, OSC_CLK);
387 iwl_read_prph(trans, OSC_CLK);
388 }
389
a6c684ee
EG		 390 /*
391 * Enable DMA clock and wait for it to stabilize.
392 *
3073d8c0
EH		 393 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
394 * bits do not disable clocks. This preserves any hardware
395 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 396 */
95411d04 397 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 398 iwl_write_prph(trans, APMG_CLK_EN_REG,
399 APMG_CLK_VAL_DMA_CLK_RQT);
400 udelay(20);
401
402 /* Disable L1-Active */
403 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
404 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
405
406 /* Clear the interrupt in APMG if the NIC is in RFKILL */
407 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
408 APMG_RTC_INT_STT_RFKILL);
409 }
889b1696 410
eb7ff77e 411 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 412
52b6e168 413 return 0;
a6c684ee
EG		 414}
415
a812cba9
AB		 416/*
417 * Enable LP XTAL to avoid HW bug where device may consume much power if
418 * FW is not loaded after device reset. LP XTAL is disabled by default
419 * after device HW reset. Do it only if XTAL is fed by internal source.
420 * Configure device's "persistence" mode to avoid resetting XTAL again when
421 * SHRD_HW_RST occurs in S3.
422 */
423static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
424{
425 int ret;
426 u32 apmg_gp1_reg;
427 u32 apmg_xtal_cfg_reg;
428 u32 dl_cfg_reg;
429
430 /* Force XTAL ON */
431 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
432 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
433
870c2a11 434 iwl_trans_pcie_sw_reset(trans);
a812cba9 435
7d34a7d7 436 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 437 if (WARN_ON(ret)) {
a812cba9
AB		 438 /* Release XTAL ON request */
439 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
440 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
441 return;
442 }
443
444 /*
445 * Clear "disable persistence" to avoid LP XTAL resetting when
446 * SHRD_HW_RST is applied in S3.
447 */
448 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
449 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
450
451 /*
452 * Force APMG XTAL to be active to prevent its disabling by HW
453 * caused by APMG idle state.
454 */
455 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
456 SHR_APMG_XTAL_CFG_REG);
457 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
458 apmg_xtal_cfg_reg |
459 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
460
870c2a11 461 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 462
463 /* Enable LP XTAL by indirect access through CSR */
464 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
465 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
466 SHR_APMG_GP1_WF_XTAL_LP_EN |
467 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
468
469 /* Clear delay line clock power up */
470 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
471 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
472 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
473
474 /*
475 * Enable persistence mode to avoid LP XTAL resetting when
476 * SHRD_HW_RST is applied in S3.
477 */
478 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
479 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
480
481 /*
482 * Clear "initialization complete" bit to move adapter from
483 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
484 */
6dece0e9 485 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
a812cba9
AB		 486
487 /* Activates XTAL resources monitor */
488 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
489 CSR_MONITOR_XTAL_RESOURCES);
490
491 /* Release XTAL ON request */
492 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
493 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
494 udelay(10);
495
496 /* Release APMG XTAL */
497 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
498 apmg_xtal_cfg_reg &
499 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
500}
501
e8c8935e 502void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 503{
e8c8935e 504 int ret;
cc56feb2
EG		 505
506 /* stop device's busmaster DMA activity */
6dece0e9 507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
cc56feb2 508
6dece0e9
LC		 509 ret = iwl_poll_bit(trans, CSR_RESET,
510 CSR_RESET_REG_FLAG_MASTER_DISABLED,
511 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 512 if (ret < 0)
cc56feb2
EG		 513 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
514
515 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 516}
517
b7aaeae4 518static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 519{
520 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
521
b7aaeae4
EG		 522 if (op_mode_leave) {
523 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
524 iwl_pcie_apm_init(trans);
525
526 /* inform ME that we are leaving */
286ca8eb 527 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
b7aaeae4
EG		 528 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
529 APMG_PCIDEV_STT_VAL_WAKE_ME);
286ca8eb 530 else if (trans->trans_cfg->device_family >=
79b6c8fe 531 IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 532 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
533 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 534 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
535 CSR_HW_IF_CONFIG_REG_PREPARE |
536 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 537 mdelay(1);
538 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
539 CSR_RESET_LINK_PWR_MGMT_DISABLED);
540 }
b7aaeae4
EG		 541 mdelay(5);
542 }
543
eb7ff77e 544 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 545
546 /* Stop device's DMA activity */
7afe3705 547 iwl_pcie_apm_stop_master(trans);
cc56feb2 548
a812cba9
AB		 549 if (trans->cfg->lp_xtal_workaround) {
550 iwl_pcie_apm_lp_xtal_enable(trans);
551 return;
552 }
553
870c2a11 554 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 555
556 /*
557 * Clear "initialization complete" bit to move adapter from
558 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
559 */
6dece0e9 560 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
cc56feb2
EG		 561}
562
7afe3705 563static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 564{
7b11488f 565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 566 int ret;
392f8b78
EG		 567
568 /* nic_init */
7b70bd63 569 spin_lock(&trans_pcie->irq_lock);
52b6e168 570 ret = iwl_pcie_apm_init(trans);
7b70bd63 571 spin_unlock(&trans_pcie->irq_lock);
392f8b78 572
52b6e168
EG		 573 if (ret)
574 return ret;
575
95411d04 576 iwl_pcie_set_pwr(trans, false);
392f8b78 577
ecdb975c 578 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 579
580 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 581 iwl_pcie_rx_init(trans);
392f8b78
EG		 582
583 /* Allocate or reset and init all Tx and Command queues */
f02831be 584 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 585 return -ENOMEM;
586
286ca8eb 587 if (trans->trans_cfg->base_params->shadow_reg_enable) {
392f8b78 588 /* enable shadow regs in HW */
20d3b647 589 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 590 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 591 }
592
392f8b78
EG		 593 return 0;
594}
595
596#define HW_READY_TIMEOUT (50)
597
598/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 599static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 600{
601 int ret;
602
1042db2a 603 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 604 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 605
606 /* See if we got it */
1042db2a 607 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 608 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
610 HW_READY_TIMEOUT);
392f8b78 611
6a08f514
EG		 612 if (ret >= 0)
613 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
614
6d8f6eeb 615 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 616 return ret;
617}
618
619/* Note: returns standard 0/-ERROR code */
eda50cde 620int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 621{
622 int ret;
289e5501 623 int t = 0;
501fd989 624 int iter;
392f8b78 625
6d8f6eeb 626 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 627
7afe3705 628 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 629 /* If the card is ready, exit 0 */
392f8b78
EG		 630 if (ret >= 0)
631 return 0;
632
c9fdec9f
EG		 633 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
634 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 635 usleep_range(1000, 2000);
c9fdec9f 636
501fd989
EG		 637 for (iter = 0; iter < 10; iter++) {
638 /* If HW is not ready, prepare the conditions to check again */
639 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
640 CSR_HW_IF_CONFIG_REG_PREPARE);
641
642 do {
643 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 644 if (ret >= 0)
645 return 0;
392f8b78 646
501fd989
EG		 647 usleep_range(200, 1000);
648 t += 200;
649 } while (t < 150000);
650 msleep(25);
651 }
392f8b78 652
7f2ac8fb 653 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 654
392f8b78
EG		 655 return ret;
656}
657
cf614297
EG		 658/*
659 * ucode
660 */
564cdce7
SS		 661static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
662 u32 dst_addr, dma_addr_t phy_addr,
663 u32 byte_cnt)
cf614297 664{
bac842da
EG		 665 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
666 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
667
668 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
669 dst_addr);
670
671 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
672 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
673
674 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
675 (iwl_get_dma_hi_addr(phy_addr)
676 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
677
678 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
679 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
680 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
681 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
682
683 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
684 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
686 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 687}
688
564cdce7
SS		 689static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
690 u32 dst_addr, dma_addr_t phy_addr,
691 u32 byte_cnt)
692{
693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
694 unsigned long flags;
695 int ret;
696
697 trans_pcie->ucode_write_complete = false;
698
699 if (!iwl_trans_grab_nic_access(trans, &flags))
700 return -EIO;
701
eda50cde
SS		 702 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
703 byte_cnt);
bac842da 704 iwl_trans_release_nic_access(trans, &flags);
cf614297 705
13df1aab
JB		 706 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
707 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 708 if (!ret) {
83f84d7b 709 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 710 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 711 return -ETIMEDOUT;
712 }
713
714 return 0;
715}
716
7afe3705 717static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 718 const struct fw_desc *section)
cf614297 719{
83f84d7b
JB		 720 u8 *v_addr;
721 dma_addr_t p_addr;
baa21e83 722 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 723 int ret = 0;
724
83f84d7b
JB		 725 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
726 section_num);
727
c571573a
EG		 728 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
729 GFP_KERNEL | __GFP_NOWARN);
730 if (!v_addr) {
731 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
732 chunk_sz = PAGE_SIZE;
733 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
734 &p_addr, GFP_KERNEL);
735 if (!v_addr)
736 return -ENOMEM;
737 }
83f84d7b 738
c571573a 739 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 740 u32 copy_size, dst_addr;
741 bool extended_addr = false;
83f84d7b 742
c571573a 743 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 744 dst_addr = section->offset + offset;
745
746 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
747 dst_addr <= IWL_FW_MEM_EXTENDED_END)
748 extended_addr = true;
749
750 if (extended_addr)
751 iwl_set_bits_prph(trans, LMPM_CHICK,
752 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 753
83f84d7b 754 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 755 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
756 copy_size);
757
758 if (extended_addr)
759 iwl_clear_bits_prph(trans, LMPM_CHICK,
760 LMPM_CHICK_EXTENDED_ADDR_SPACE);
761
83f84d7b
JB		 762 if (ret) {
763 IWL_ERR(trans,
764 "Could not load the [%d] uCode section\n",
765 section_num);
766 break;
6dfa8d01 767 }
83f84d7b
JB		 768 }
769
c571573a 770 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 771 return ret;
772}
773
5dd9c68a
EG		 774static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
775 const struct fw_img *image,
776 int cpu,
777 int *first_ucode_section)
e2d6f4e7
EH		 778{
779 int shift_param;
dcab8ecd
EH		 780 int i, ret = 0, sec_num = 0x1;
781 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 782
783 if (cpu == 1) {
784 shift_param = 0;
034846cf 785 *first_ucode_section = 0;
e2d6f4e7
EH		 786 } else {
787 shift_param = 16;
034846cf 788 (*first_ucode_section)++;
e2d6f4e7
EH		 789 }
790
eef187a7 791 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 792 last_read_idx = i;
793
a6c4fb44
MG		 794 /*
795 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
796 * CPU1 to CPU2.
797 * PAGING_SEPARATOR_SECTION delimiter - separate between
798 * CPU2 non paged to CPU2 paging sec.
799 */
034846cf 800 if (!image->sec[i].data ||
a6c4fb44
MG		 801 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
802 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 803 IWL_DEBUG_FW(trans,
804 "Break since Data not valid or Empty section, sec = %d\n",
805 i);
189fa2fa 806 break;
034846cf
EH		 807 }
808
189fa2fa
EH		 809 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
810 if (ret)
811 return ret;
dcab8ecd 812
d6a2c5c7 813 /* Notify ucode of loaded section number and status */
eda50cde
SS		 814 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
815 val = val | (sec_num << shift_param);
816 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
817
dcab8ecd 818 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 819 }
820
034846cf
EH		 821 *first_ucode_section = last_read_idx;
822
2aabdbdc
EG		 823 iwl_enable_interrupts(trans);
824
286ca8eb 825 if (trans->trans_cfg->use_tfh) {
d6a2c5c7
SS		 826 if (cpu == 1)
827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
828 0xFFFF);
829 else
830 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
831 0xFFFFFFFF);
832 } else {
833 if (cpu == 1)
834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
835 0xFFFF);
836 else
837 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
838 0xFFFFFFFF);
839 }
afb88917 840
189fa2fa
EH		 841 return 0;
842}
e2d6f4e7 843
189fa2fa
EH		 844static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
845 const struct fw_img *image,
034846cf
EH		 846 int cpu,
847 int *first_ucode_section)
189fa2fa 848{
189fa2fa 849 int i, ret = 0;
034846cf 850 u32 last_read_idx = 0;
189fa2fa 851
3ce4a038 852 if (cpu == 1)
034846cf 853 *first_ucode_section = 0;
3ce4a038 854 else
034846cf 855 (*first_ucode_section)++;
189fa2fa 856
eef187a7 857 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 858 last_read_idx = i;
859
a6c4fb44
MG		 860 /*
861 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
862 * CPU1 to CPU2.
863 * PAGING_SEPARATOR_SECTION delimiter - separate between
864 * CPU2 non paged to CPU2 paging sec.
865 */
034846cf 866 if (!image->sec[i].data ||
a6c4fb44
MG		 867 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
868 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 869 IWL_DEBUG_FW(trans,
870 "Break since Data not valid or Empty section, sec = %d\n",
871 i);
189fa2fa 872 break;
034846cf
EH		 873 }
874
189fa2fa
EH		 875 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
876 if (ret)
877 return ret;
e2d6f4e7
EH		 878 }
879
034846cf
EH		 880 *first_ucode_section = last_read_idx;
881
e2d6f4e7
EH		 882 return 0;
883}
884
593fae3e
SM		 885static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
886{
887 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
888 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
889 &trans->dbg.fw_mon_cfg[alloc_id];
890 struct iwl_dram_data *frag;
891
892 if (!iwl_trans_dbg_ini_valid(trans))
893 return;
894
895 if (le32_to_cpu(fw_mon_cfg->buf_location) ==
896 IWL_FW_INI_LOCATION_SRAM_PATH) {
897 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
898 /* set sram monitor by enabling bit 7 */
899 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
900 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
901
902 return;
903 }
904
905 if (le32_to_cpu(fw_mon_cfg->buf_location) !=
906 IWL_FW_INI_LOCATION_DRAM_PATH ||
907 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
908 return;
909
910 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
911
912 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
913 alloc_id);
914
915 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
916 frag->physical >> MON_BUFF_SHIFT_VER2);
917 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
918 (frag->physical + frag->size - 256) >>
919 MON_BUFF_SHIFT_VER2);
920}
921
c9be849d 922void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 923{
91c28b83 924 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
69f0e505 925 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
09e350f7
LK		 926 int i;
927
a1af4c48 928 if (iwl_trans_dbg_ini_valid(trans)) {
593fae3e 929 iwl_pcie_apply_destination_ini(trans);
7a14c23d
SS		 930 return;
931 }
932
09e350f7
LK		 933 IWL_INFO(trans, "Applying debug destination %s\n",
934 get_fw_dbg_mode_string(dest->monitor_mode));
935
936 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 937 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 938 else
939 IWL_WARN(trans, "PCI should have external buffer debug\n");
940
91c28b83 941 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
09e350f7
LK		 942 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
943 u32 val = le32_to_cpu(dest->reg_ops[i].val);
944
945 switch (dest->reg_ops[i].op) {
946 case CSR_ASSIGN:
947 iwl_write32(trans, addr, val);
948 break;
949 case CSR_SETBIT:
950 iwl_set_bit(trans, addr, BIT(val));
951 break;
952 case CSR_CLEARBIT:
953 iwl_clear_bit(trans, addr, BIT(val));
954 break;
955 case PRPH_ASSIGN:
956 iwl_write_prph(trans, addr, val);
957 break;
958 case PRPH_SETBIT:
959 iwl_set_bits_prph(trans, addr, BIT(val));
960 break;
961 case PRPH_CLEARBIT:
962 iwl_clear_bits_prph(trans, addr, BIT(val));
963 break;
869f3b15
HD		 964 case PRPH_BLOCKBIT:
965 if (iwl_read_prph(trans, addr) & BIT(val)) {
966 IWL_ERR(trans,
967 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
968 val, addr);
969 goto monitor;
970 }
971 break;
09e350f7
LK		 972 default:
973 IWL_ERR(trans, "FW debug - unknown OP %d\n",
974 dest->reg_ops[i].op);
975 break;
976 }
977 }
978
869f3b15 979monitor:
69f0e505 980 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
09e350f7 981 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
69f0e505 982 fw_mon->physical >> dest->base_shift);
286ca8eb 983 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 984 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 985 (fw_mon->physical + fw_mon->size -
986 256) >> dest->end_shift);
62d7476d
EG		 987 else
988 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 989 (fw_mon->physical + fw_mon->size) >>
990 dest->end_shift);
09e350f7
LK		 991 }
992}
993
7afe3705 994static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 995 const struct fw_img *image)
cf614297 996{
189fa2fa 997 int ret = 0;
034846cf 998 int first_ucode_section;
cf614297 999
dcab8ecd 1000 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 1001 image->is_dual_cpus ? "Dual" : "Single");
1002
dcab8ecd
EH		 1003 /* load to FW the binary non secured sections of CPU1 */
1004 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1005 if (ret)
1006 return ret;
e2d6f4e7
EH		 1007
1008 if (image->is_dual_cpus) {
189fa2fa
EH		 1009 /* set CPU2 header address */
1010 iwl_write_prph(trans,
1011 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1012 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1013
189fa2fa 1014 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1015 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1016 &first_ucode_section);
189fa2fa
EH		 1017 if (ret)
1018 return ret;
e2d6f4e7 1019 }
cf614297 1020
c2d20201
EG		 1021 /* supported for 7000 only for the moment */
1022 if (iwlwifi_mod_params.fw_monitor &&
286ca8eb 1023 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
69f0e505 1024 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 1025
69f0e505
SM		 1026 iwl_pcie_alloc_fw_monitor(trans, 0);
1027 if (fw_mon->size) {
c2d20201 1028 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
69f0e505 1029 fw_mon->physical >> 4);
c2d20201 1030 iwl_write_prph(trans, MON_BUFF_END_ADDR,
69f0e505 1031 (fw_mon->physical + fw_mon->size) >> 4);
c2d20201 1032 }
7a14c23d 1033 } else if (iwl_pcie_dbg_on(trans)) {
09e350f7 1034 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1035 }
1036
2aabdbdc
EG		 1037 iwl_enable_interrupts(trans);
1038
e12ba844 1039 /* release CPU reset */
5dd9c68a 1040 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1041
dcab8ecd
EH		 1042 return 0;
1043}
189fa2fa 1044
5dd9c68a
EG		 1045static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1046 const struct fw_img *image)
dcab8ecd
EH		 1047{
1048 int ret = 0;
1049 int first_ucode_section;
dcab8ecd
EH		 1050
1051 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1052 image->is_dual_cpus ? "Dual" : "Single");
1053
7a14c23d 1054 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 1055 iwl_pcie_apply_destination(trans);
1056
82ea7966
SS		 1057 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1058 iwl_read_prph(trans, WFPM_GP2));
1059
1060 /*
1061 * Set default value. On resume reading the values that were
1062 * zeored can provide debug data on the resume flow.
1063 * This is for debugging only and has no functional impact.
1064 */
1065 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1066
dcab8ecd
EH		 1067 /* configure the ucode to be ready to get the secured image */
1068 /* release CPU reset */
1069 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1070
1071 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1072 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1073 &first_ucode_section);
dcab8ecd
EH		 1074 if (ret)
1075 return ret;
1076
1077 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1078 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1079 &first_ucode_section);
cf614297
EG		 1080}
1081
9ad8fd0b 1082bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1083{
326477e4 1084 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1085 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1086 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1087 bool report;
727c02df 1088
326477e4
JB		 1089 if (hw_rfkill) {
1090 set_bit(STATUS_RFKILL_HW, &trans->status);
1091 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1092 } else {
1093 clear_bit(STATUS_RFKILL_HW, &trans->status);
1094 if (trans_pcie->opmode_down)
1095 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1096 }
1097
1098 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1099
326477e4
JB		 1100 if (prev != report)
1101 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1102
1103 return hw_rfkill;
1104}
1105
7ca00409
HD		 1106struct iwl_causes_list {
1107 u32 cause_num;
1108 u32 mask_reg;
1109 u8 addr;
1110};
1111
1112static struct iwl_causes_list causes_list[] = {
1113 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1114 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1115 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1116 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1117 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1118 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
ff911dca 1119 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12},
7ca00409
HD		 1120 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1121 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1122 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1123 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1124 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1125 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1126 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1127 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1128};
1129
1130static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1131{
1132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1133 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
3681021f
JB		 1134 int i, arr_size = ARRAY_SIZE(causes_list);
1135 struct iwl_causes_list *causes = causes_list;
7ca00409
HD		 1136
1137 /*
1138 * Access all non RX causes and map them to the default irq.
1139 * In case we are missing at least one interrupt vector,
1140 * the first interrupt vector will serve non-RX and FBQ causes.
1141 */
9b58419e 1142 for (i = 0; i < arr_size; i++) {
9b58419e
GBA		 1143 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1144 iwl_clear_bit(trans, causes[i].mask_reg,
1145 causes[i].cause_num);
7ca00409
HD		 1146 }
1147}
1148
1149static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1150{
1151 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1152 u32 offset =
1153 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1154 u32 val, idx;
1155
1156 /*
1157 * The first RX queue - fallback queue, which is designated for
1158 * management frame, command responses etc, is always mapped to the
1159 * first interrupt vector. The other RX queues are mapped to
1160 * the other (N - 2) interrupt vectors.
1161 */
1162 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1163 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1164 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1165 MSIX_FH_INT_CAUSES_Q(idx - offset));
1166 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1167 }
1168 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1169
1170 val = MSIX_FH_INT_CAUSES_Q(0);
1171 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1172 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1173 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1174
1175 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1176 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1177}
1178
77c09bc8 1179void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1180{
1181 struct iwl_trans *trans = trans_pcie->trans;
1182
1183 if (!trans_pcie->msix_enabled) {
286ca8eb 1184 if (trans->trans_cfg->mq_rx_supported &&
d7270d61 1185 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1186 iwl_write_umac_prph(trans, UREG_CHICK,
1187 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1188 return;
1189 }
d7270d61
HD		 1190 /*
1191 * The IVAR table needs to be configured again after reset,
1192 * but if the device is disabled, we can't write to
1193 * prph.
1194 */
1195 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1196 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1197
1198 /*
1199 * Each cause from the causes list above and the RX causes is
1200 * represented as a byte in the IVAR table. The first nibble
1201 * represents the bound interrupt vector of the cause, the second
1202 * represents no auto clear for this cause. This will be set if its
1203 * interrupt vector is bound to serve other causes.
1204 */
1205 iwl_pcie_map_rx_causes(trans);
1206
1207 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1208}
1209
1210static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1211{
1212 struct iwl_trans *trans = trans_pcie->trans;
1213
1214 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1215
83730058
HD		 1216 if (!trans_pcie->msix_enabled)
1217 return;
1218
1219 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1220 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1221 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1222 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1223}
1224
bab3cb92 1225static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1226{
43e58856 1227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1228
fa9f3281
EG		 1229 lockdep_assert_held(&trans_pcie->mutex);
1230
1231 if (trans_pcie->is_down)
1232 return;
1233
1234 trans_pcie->is_down = true;
1235
43e58856 1236 /* tell the device to stop sending interrupts */
ae2c30bf 1237 iwl_disable_interrupts(trans);
ae2c30bf 1238
ab6cf8e8 1239 /* device going down, Stop using ICT table */
990aa6d7 1240 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1241
1242 /*
1243 * If a HW restart happens during firmware loading,
1244 * then the firmware loading might call this function
1245 * and later it might be called again due to the
1246 * restart. So don't process again if the device is
1247 * already dead.
1248 */
31b8b343 1249 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1250 IWL_DEBUG_INFO(trans,
1251 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1252 iwl_pcie_tx_stop(trans);
9805c446 1253 iwl_pcie_rx_stop(trans);
6379103e 1254
ab6cf8e8 1255 /* Power-down device's busmaster DMA clocks */
95411d04 1256 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1257 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1258 APMG_CLK_VAL_DMA_CLK_RQT);
1259 udelay(5);
1260 }
ab6cf8e8
EG		 1261 }
1262
1263 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1264 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1265 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1266
1267 /* Stop the device, and put it in low power state */
b7aaeae4 1268 iwl_pcie_apm_stop(trans, false);
43e58856 1269
870c2a11 1270 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1271
f4a1f04a
GBA		 1272 /*
1273 * Upon stop, the IVAR table gets erased, so msi-x won't
1274 * work. This causes a bug in RF-KILL flows, since the interrupt
1275 * that enables radio won't fire on the correct irq, and the
1276 * driver won't be able to handle the interrupt.
1277 * Configure the IVAR table again after reset.
1278 */
1279 iwl_pcie_conf_msix_hw(trans_pcie);
1280
03d6c3b0
EG		 1281 /*
1282 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1283 * This is a bug in certain verions of the hardware.
1284 * Certain devices also keep sending HW RF kill interrupt all
1285 * the time, unless the interrupt is ACKed even if the interrupt
1286 * should be masked. Re-ACK all the interrupts here.
43e58856 1287 */
43e58856 1288 iwl_disable_interrupts(trans);
43e58856 1289
74fda971 1290 /* clear all status bits */
eb7ff77e
AN		 1291 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1292 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1293 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1294
1295 /*
1296 * Even if we stop the HW, we still want the RF kill
1297 * interrupt
1298 */
1299 iwl_enable_rfkill_int(trans);
1300
a6bd005f 1301 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1302 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1303}
1304
eda50cde 1305void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1306{
1307 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1308
1309 if (trans_pcie->msix_enabled) {
1310 int i;
1311
496d83ca 1312 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1313 synchronize_irq(trans_pcie->msix_entries[i].vector);
1314 } else {
1315 synchronize_irq(trans_pcie->pci_dev->irq);
1316 }
1317}
1318
a6bd005f
EG		 1319static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1320 const struct fw_img *fw, bool run_in_rfkill)
1321{
1322 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1323 bool hw_rfkill;
1324 int ret;
1325
1326 /* This may fail if AMT took ownership of the device */
1327 if (iwl_pcie_prepare_card_hw(trans)) {
1328 IWL_WARN(trans, "Exit HW not ready\n");
1329 ret = -EIO;
1330 goto out;
1331 }
1332
1333 iwl_enable_rfkill_int(trans);
1334
1335 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1336
1337 /*
1338 * We enabled the RF-Kill interrupt and the handler may very
1339 * well be running. Disable the interrupts to make sure no other
1340 * interrupt can be fired.
1341 */
1342 iwl_disable_interrupts(trans);
1343
1344 /* Make sure it finished running */
2e5d4a8f 1345 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1346
1347 mutex_lock(&trans_pcie->mutex);
1348
1349 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1350 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1351 if (hw_rfkill && !run_in_rfkill) {
1352 ret = -ERFKILL;
1353 goto out;
1354 }
1355
1356 /* Someone called stop_device, don't try to start_fw */
1357 if (trans_pcie->is_down) {
1358 IWL_WARN(trans,
1359 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1360 ret = -EIO;
a6bd005f
EG		 1361 goto out;
1362 }
1363
1364 /* make sure rfkill handshake bits are cleared */
1365 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1366 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1367 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1368
1369 /* clear (again), then enable host interrupts */
1370 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1371
1372 ret = iwl_pcie_nic_init(trans);
1373 if (ret) {
1374 IWL_ERR(trans, "Unable to init nic\n");
1375 goto out;
1376 }
1377
1378 /*
1379 * Now, we load the firmware and don't want to be interrupted, even
1380 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1381 * FH_TX interrupt which is needed to load the firmware). If the
1382 * RF-Kill switch is toggled, we will find out after having loaded
1383 * the firmware and return the proper value to the caller.
1384 */
1385 iwl_enable_fw_load_int(trans);
1386
1387 /* really make sure rfkill handshake bits are cleared */
1388 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1389 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1390
1391 /* Load the given image to the HW */
286ca8eb 1392 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1393 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1394 else
1395 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1396
1397 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1398 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1399 if (hw_rfkill && !run_in_rfkill)
1400 ret = -ERFKILL;
1401
1402out:
1403 mutex_unlock(&trans_pcie->mutex);
1404 return ret;
1405}
1406
1407static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1408{
1409 iwl_pcie_reset_ict(trans);
1410 iwl_pcie_tx_start(trans, scd_addr);
1411}
1412
326477e4
JB		 1413void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1414 bool was_in_rfkill)
1415{
1416 bool hw_rfkill;
1417
1418 /*
1419 * Check again since the RF kill state may have changed while
1420 * all the interrupts were disabled, in this case we couldn't
1421 * receive the RF kill interrupt and update the state in the
1422 * op_mode.
1423 * Don't call the op_mode if the rkfill state hasn't changed.
1424 * This allows the op_mode to call stop_device from the rfkill
1425 * notification without endless recursion. Under very rare
1426 * circumstances, we might have a small recursion if the rfkill
1427 * state changed exactly now while we were called from stop_device.
1428 * This is very unlikely but can happen and is supported.
1429 */
1430 hw_rfkill = iwl_is_rfkill_set(trans);
1431 if (hw_rfkill) {
1432 set_bit(STATUS_RFKILL_HW, &trans->status);
1433 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1434 } else {
1435 clear_bit(STATUS_RFKILL_HW, &trans->status);
1436 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1437 }
1438 if (hw_rfkill != was_in_rfkill)
1439 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1440}
1441
bab3cb92 1442static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
fa9f3281
EG		 1443{
1444 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1445 bool was_in_rfkill;
fa9f3281
EG		 1446
1447 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1448 trans_pcie->opmode_down = true;
1449 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
bab3cb92 1450 _iwl_trans_pcie_stop_device(trans);
326477e4 1451 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1452 mutex_unlock(&trans_pcie->mutex);
1453}
1454
14cfca71
JB		 1455void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1456{
fa9f3281
EG		 1457 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1458 IWL_TRANS_GET_PCIE_TRANS(trans);
1459
1460 lockdep_assert_held(&trans_pcie->mutex);
1461
326477e4
JB		 1462 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1463 state ? "disabled" : "enabled");
77c09bc8 1464 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
286ca8eb 1465 if (trans->trans_cfg->gen2)
bab3cb92 1466 _iwl_trans_pcie_gen2_stop_device(trans);
77c09bc8 1467 else
bab3cb92 1468 _iwl_trans_pcie_stop_device(trans);
77c09bc8 1469 }
ab6cf8e8
EG		 1470}
1471
e5f3f215
HD		 1472void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1473 bool test, bool reset)
2dd4f9f7 1474{
2dd4f9f7 1475 iwl_disable_interrupts(trans);
debff618
JB		 1476
1477 /*
1478 * in testing mode, the host stays awake and the
1479 * hardware won't be reset (not even partially)
1480 */
1481 if (test)
1482 return;
1483
ddaf5a5b
JB		 1484 iwl_pcie_disable_ict(trans);
1485
2e5d4a8f 1486 iwl_pcie_synchronize_irqs(trans);
33b56af1 1487
2dd4f9f7 1488 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 1489 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1490 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
ddaf5a5b 1491
23ae6128 1492 if (reset) {
6dfb36c8
EP		 1493 /*
1494 * reset TX queues -- some of their registers reset during S3
1495 * so if we don't reset everything here the D3 image would try
1496 * to execute some invalid memory upon resume
1497 */
1498 iwl_trans_pcie_tx_reset(trans);
1499 }
ddaf5a5b
JB		 1500
1501 iwl_pcie_set_pwr(trans, true);
1502}
1503
e5f3f215
HD		 1504static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1505 bool reset)
1506{
1507 int ret;
1508 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1509
1510 /*
1511 * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW.
1512 */
1513 if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
1514 /* Enable persistence mode to avoid reset */
1515 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1516 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1517 }
1518
1519 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1520 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1521 UREG_DOORBELL_TO_ISR6_SUSPEND);
1522
1523 ret = wait_event_timeout(trans_pcie->sx_waitq,
1524 trans_pcie->sx_complete, 2 * HZ);
1525 /*
1526 * Invalidate it toward resume.
1527 */
1528 trans_pcie->sx_complete = false;
1529
1530 if (!ret) {
1531 IWL_ERR(trans, "Timeout entering D3\n");
1532 return -ETIMEDOUT;
1533 }
1534 }
1535 iwl_pcie_d3_complete_suspend(trans, test, reset);
1536
1537 return 0;
1538}
1539
ddaf5a5b 1540static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1541 enum iwl_d3_status *status,
23ae6128 1542 bool test, bool reset)
ddaf5a5b 1543{
d7270d61 1544 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1545 u32 val;
1546 int ret;
1547
debff618
JB		 1548 if (test) {
1549 iwl_enable_interrupts(trans);
1550 *status = IWL_D3_STATUS_ALIVE;
e5f3f215 1551 goto out;
debff618
JB		 1552 }
1553
a8cbb46f 1554 iwl_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 1555 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b 1556
7d34a7d7 1557 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 1558 if (ret)
ddaf5a5b 1559 return ret;
ddaf5a5b 1560
f98ad635
EG		 1561 /*
1562 * Reconfigure IVAR table in case of MSIX or reset ict table in
1563 * MSI mode since HW reset erased it.
1564 * Also enables interrupts - none will happen as
1565 * the device doesn't know we're waking it up, only when
1566 * the opmode actually tells it after this call.
1567 */
1568 iwl_pcie_conf_msix_hw(trans_pcie);
1569 if (!trans_pcie->msix_enabled)
1570 iwl_pcie_reset_ict(trans);
1571 iwl_enable_interrupts(trans);
1572
a3ead656
EG		 1573 iwl_pcie_set_pwr(trans, false);
1574
23ae6128 1575 if (!reset) {
6dfb36c8 1576 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1577 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6dfb36c8
EP		 1578 } else {
1579 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1580
6dfb36c8
EP		 1581 ret = iwl_pcie_rx_init(trans);
1582 if (ret) {
1583 IWL_ERR(trans,
1584 "Failed to resume the device (RX reset)\n");
1585 return ret;
1586 }
ddaf5a5b
JB		 1587 }
1588
82ea7966 1589 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1590 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1591
a3ead656
EG		 1592 val = iwl_read32(trans, CSR_RESET);
1593 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1594 *status = IWL_D3_STATUS_RESET;
1595 else
1596 *status = IWL_D3_STATUS_ALIVE;
1597
e5f3f215
HD		 1598out:
1599 if (*status == IWL_D3_STATUS_ALIVE &&
1600 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1601 trans_pcie->sx_complete = false;
1602 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1603 UREG_DOORBELL_TO_ISR6_RESUME);
1604
1605 ret = wait_event_timeout(trans_pcie->sx_waitq,
1606 trans_pcie->sx_complete, 2 * HZ);
1607 /*
1608 * Invalidate it toward next suspend.
1609 */
1610 trans_pcie->sx_complete = false;
1611
1612 if (!ret) {
1613 IWL_ERR(trans, "Timeout exiting D3\n");
1614 return -ETIMEDOUT;
1615 }
1616 }
ddaf5a5b 1617 return 0;
2dd4f9f7
JB		 1618}
1619
0c18714a
LC		 1620static void
1621iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1622 struct iwl_trans *trans,
1623 const struct iwl_cfg_trans_params *cfg_trans)
2e5d4a8f
HD		 1624{
1625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1626 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1627 u16 pci_cmd;
2e5d4a8f 1628
0c18714a 1629 if (!cfg_trans->mq_rx_supported)
06f4b081
SS		 1630 goto enable_msi;
1631
ab1068d6 1632 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1633 for (i = 0; i < max_irqs; i++)
1634 trans_pcie->msix_entries[i].entry = i;
496d83ca 1635
06f4b081
SS		 1636 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1637 MSIX_MIN_INTERRUPT_VECTORS,
1638 max_irqs);
1639 if (num_irqs < 0) {
2e5d4a8f 1640 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1641 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1642 num_irqs);
1643 goto enable_msi;
1644 }
1645 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1646
06f4b081
SS		 1647 IWL_DEBUG_INFO(trans,
1648 "MSI-X enabled. %d interrupt vectors were allocated\n",
1649 num_irqs);
1650
1651 /*
1652 * In case the OS provides fewer interrupts than requested, different
1653 * causes will share the same interrupt vector as follows:
1654 * One interrupt less: non rx causes shared with FBQ.
1655 * Two interrupts less: non rx causes shared with FBQ and RSS.
1656 * More than two interrupts: we will use fewer RSS queues.
1657 */
ab1068d6 1658 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1659 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1660 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1661 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1662 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1663 trans_pcie->trans->num_rx_queues = num_irqs;
1664 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1665 } else {
1666 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1667 }
ab1068d6 1668 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1669
06f4b081
SS		 1670 trans_pcie->alloc_vecs = num_irqs;
1671 trans_pcie->msix_enabled = true;
1672 return;
1673
1674enable_msi:
1675 ret = pci_enable_msi(pdev);
1676 if (ret) {
1677 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1678 /* enable rfkill interrupt: hw bug w/a */
1679 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1680 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1681 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1682 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1683 }
1684 }
1685}
1686
7c8d91eb
HD		 1687static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1688{
1689 int iter_rx_q, i, ret, cpu, offset;
1690 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1691
1692 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1693 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1694 offset = 1 + i;
1695 for (; i < iter_rx_q ; i++) {
1696 /*
1697 * Get the cpu prior to the place to search
1698 * (i.e. return will be > i - 1).
1699 */
1700 cpu = cpumask_next(i - offset, cpu_online_mask);
1701 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1702 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1703 &trans_pcie->affinity_mask[i]);
1704 if (ret)
1705 IWL_ERR(trans_pcie->trans,
1706 "Failed to set affinity mask for IRQ %d\n",
1707 i);
1708 }
1709}
1710
2e5d4a8f
HD		 1711static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1712 struct iwl_trans_pcie *trans_pcie)
1713{
496d83ca 1714 int i;
2e5d4a8f 1715
496d83ca 1716 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1717 int ret;
5a41a86c 1718 struct msix_entry *msix_entry;
64fa3aff
SD		 1719 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1720
1721 if (!qname)
1722 return -ENOMEM;
5a41a86c
SD		 1723
1724 msix_entry = &trans_pcie->msix_entries[i];
1725 ret = devm_request_threaded_irq(&pdev->dev,
1726 msix_entry->vector,
1727 iwl_pcie_msix_isr,
1728 (i == trans_pcie->def_irq) ?
1729 iwl_pcie_irq_msix_handler :
1730 iwl_pcie_irq_rx_msix_handler,
1731 IRQF_SHARED,
64fa3aff 1732 qname,
5a41a86c 1733 msix_entry);
2e5d4a8f 1734 if (ret) {
2e5d4a8f
HD		 1735 IWL_ERR(trans_pcie->trans,
1736 "Error allocating IRQ %d\n", i);
5a41a86c 1737
2e5d4a8f
HD		 1738 return ret;
1739 }
1740 }
7c8d91eb 1741 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1742
1743 return 0;
1744}
1745
44f61b5c 1746static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
e6bb4c9c 1747{
44f61b5c 1748 u32 hpm, wprot;
fa9f3281 1749
286ca8eb 1750 switch (trans->trans_cfg->device_family) {
44f61b5c
SM		 1751 case IWL_DEVICE_FAMILY_9000:
1752 wprot = PREG_PRPH_WPROT_9000;
1753 break;
1754 case IWL_DEVICE_FAMILY_22000:
1755 wprot = PREG_PRPH_WPROT_22000;
1756 break;
1757 default:
1758 return 0;
ebb7678d 1759 }
a6c684ee 1760
ea695b7c 1761 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
8954e1eb 1762 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
44f61b5c 1763 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
ea695b7c 1764
44f61b5c 1765 if (wprot_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1766 IWL_ERR(trans,
1767 "Error, can not clear persistence bit\n");
1768 return -EPERM;
1769 }
ea695b7c
ST		 1770 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1771 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1772 }
1773
44f61b5c
SM		 1774 return 0;
1775}
1776
0df36b90
LC		 1777static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1778{
1779 int ret;
1780
1781 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1782 if (ret < 0)
1783 return ret;
1784
1785 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1786 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1787 udelay(20);
1788 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1789 HPM_HIPM_GEN_CFG_CR_PG_EN |
1790 HPM_HIPM_GEN_CFG_CR_SLP_EN);
1791 udelay(20);
1792 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1793 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1794
1795 iwl_trans_pcie_sw_reset(trans);
1796
1797 return 0;
1798}
1799
bab3cb92 1800static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
44f61b5c
SM		 1801{
1802 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1803 int err;
1804
1805 lockdep_assert_held(&trans_pcie->mutex);
1806
1807 err = iwl_pcie_prepare_card_hw(trans);
1808 if (err) {
1809 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1810 return err;
1811 }
1812
1813 err = iwl_trans_pcie_clear_persistence_bit(trans);
1814 if (err)
1815 return err;
1816
870c2a11 1817 iwl_trans_pcie_sw_reset(trans);
2997494f 1818
0df36b90
LC		 1819 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1820 trans->cfg->integrated) {
1821 err = iwl_pcie_gen2_force_power_gating(trans);
1822 if (err)
1823 return err;
1824 }
1825
52b6e168
EG		 1826 err = iwl_pcie_apm_init(trans);
1827 if (err)
1828 return err;
a6c684ee 1829
2e5d4a8f 1830 iwl_pcie_init_msix(trans_pcie);
83730058 1831
226c02ca
EG		 1832 /* From now on, the op_mode will be kept updated about RF kill state */
1833 iwl_enable_rfkill_int(trans);
1834
326477e4
JB		 1835 trans_pcie->opmode_down = false;
1836
fa9f3281
EG		 1837 /* Set is_down to false here so that...*/
1838 trans_pcie->is_down = false;
1839
727c02df 1840 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1841 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1842
a8b691e6 1843 return 0;
e6bb4c9c
EG		 1844}
1845
bab3cb92 1846static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
fa9f3281
EG		 1847{
1848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1849 int ret;
1850
1851 mutex_lock(&trans_pcie->mutex);
bab3cb92 1852 ret = _iwl_trans_pcie_start_hw(trans);
fa9f3281
EG		 1853 mutex_unlock(&trans_pcie->mutex);
1854
1855 return ret;
1856}
1857
a4082843 1858static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1859{
20d3b647 1860 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1861
fa9f3281
EG		 1862 mutex_lock(&trans_pcie->mutex);
1863
a4082843 1864 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1865 iwl_disable_interrupts(trans);
ee7d737c 1866
b7aaeae4 1867 iwl_pcie_apm_stop(trans, true);
cc56feb2 1868
218733cf 1869 iwl_disable_interrupts(trans);
1df06bdc 1870
8d96bb61 1871 iwl_pcie_disable_ict(trans);
33b56af1 1872
fa9f3281 1873 mutex_unlock(&trans_pcie->mutex);
33b56af1 1874
2e5d4a8f 1875 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1876}
1877
03905495
EG		 1878static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1879{
05f5b97e 1880 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1881}
1882
1883static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1884{
05f5b97e 1885 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1886}
1887
1888static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1889{
05f5b97e 1890 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1891}
1892
84fb372c
SS		 1893static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1894{
3681021f 1895 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
84fb372c
SS		 1896 return 0x00FFFFFF;
1897 else
1898 return 0x000FFFFF;
1899}
1900
6a06b6c1
EG		 1901static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1902{
84fb372c
SS		 1903 u32 mask = iwl_trans_pcie_prph_msk(trans);
1904
f9477c17 1905 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1906 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1907 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1908}
1909
1910static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1911 u32 val)
1912{
84fb372c
SS		 1913 u32 mask = iwl_trans_pcie_prph_msk(trans);
1914
6a06b6c1 1915 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1916 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1917 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1918}
1919
c6f600fc 1920static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1921 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1922{
1923 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1924
1925 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1926 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1927 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1928 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1929 trans_pcie->n_no_reclaim_cmds = 0;
1930 else
1931 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1932 if (trans_pcie->n_no_reclaim_cmds)
1933 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1934 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1935
6c4fbcbc
EG		 1936 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1937 trans_pcie->rx_page_order =
1938 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
80084e35
JB		 1939 trans_pcie->rx_buf_bytes =
1940 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
cfdc20ef
JB		 1941 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1942 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1943 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
7c5ba4a8 1944
046db346 1945 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1946 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1947 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1948
21cb3222
JB		 1949 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1950 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1951
39bdb17e
SD		 1952 trans->command_groups = trans_cfg->command_groups;
1953 trans->command_groups_size = trans_cfg->command_groups_size;
1954
f14d6b39
JB		 1955 /* Initialize NAPI here - it should be before registering to mac80211
1956 * in the opmode but after the HW struct is allocated.
1957 * As this function may be called again in some corner cases don't
1958 * do anything if NAPI was already initialized.
1959 */
bce97731 1960 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1961 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1962}
1963
d1ff5253 1964void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1965{
20d3b647 1966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1967 int i;
a42a1844 1968
2e5d4a8f 1969 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1970
286ca8eb 1971 if (trans->trans_cfg->gen2)
13a3a390
SS		 1972 iwl_pcie_gen2_tx_free(trans);
1973 else
1974 iwl_pcie_tx_free(trans);
9805c446 1975 iwl_pcie_rx_free(trans);
6379103e 1976
10a54d81
LC		 1977 if (trans_pcie->rba.alloc_wq) {
1978 destroy_workqueue(trans_pcie->rba.alloc_wq);
1979 trans_pcie->rba.alloc_wq = NULL;
1980 }
1981
2e5d4a8f 1982 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1983 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1984 irq_set_affinity_hint(
1985 trans_pcie->msix_entries[i].vector,
1986 NULL);
7c8d91eb 1987 }
2e5d4a8f 1988
2e5d4a8f
HD		 1989 trans_pcie->msix_enabled = false;
1990 } else {
2e5d4a8f 1991 iwl_pcie_free_ict(trans);
2e5d4a8f 1992 }
a42a1844 1993
c2d20201
EG		 1994 iwl_pcie_free_fw_monitor(trans);
1995
6eb5e529
EG		 1996 for_each_possible_cpu(i) {
1997 struct iwl_tso_hdr_page *p =
1998 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1999
2000 if (p->page)
2001 __free_page(p->page);
2002 }
2003
2004 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 2005 mutex_destroy(&trans_pcie->mutex);
7b501d10 2006 iwl_trans_free(trans);
34c1b7ba
EG		 2007}
2008
47107e84
DF		 2009static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2010{
47107e84 2011 if (state)
eb7ff77e 2012 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 2013 else
eb7ff77e 2014 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 2015}
2016
49564a80
LC		 2017struct iwl_trans_pcie_removal {
2018 struct pci_dev *pdev;
2019 struct work_struct work;
2020};
2021
2022static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2023{
2024 struct iwl_trans_pcie_removal *removal =
2025 container_of(wk, struct iwl_trans_pcie_removal, work);
2026 struct pci_dev *pdev = removal->pdev;
aba1e632 2027 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
49564a80
LC		 2028
2029 dev_err(&pdev->dev, "Device gone - attempting removal\n");
2030 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2031 pci_lock_rescan_remove();
2032 pci_dev_put(pdev);
2033 pci_stop_and_remove_bus_device(pdev);
2034 pci_unlock_rescan_remove();
2035
2036 kfree(removal);
2037 module_put(THIS_MODULE);
2038}
2039
23ba9340
EG		 2040static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2041 unsigned long *flags)
7a65d170
EG		 2042{
2043 int ret;
cfb4e624
JB		 2044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2045
2046 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 2047
fc8a350d 2048 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2049 goto out;
2050
7a65d170 2051 /* this bit wakes up the NIC */
e139dc4a 2052 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 2053 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
286ca8eb 2054 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 2055 udelay(2);
7a65d170
EG		 2056
2057 /*
2058 * These bits say the device is running, and should keep running for
2059 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2060 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 2061 * HW with volatile SRAM must save/restore contents to/from
2062 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 2063 * Each direction takes approximately 1/4 millisecond; with this
2064 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2065 * series of register accesses are expected (e.g. reading Event Log),
2066 * to keep device from sleeping.
2067 *
2068 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2069 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 2070 * is just for hardware register access; but GP1 MAC_SLEEP
2071 * check is a good idea before accessing the SRAM of HW with
2072 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2073 *
2074 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2075 * and do not save/restore SRAM when power cycling.
2076 */
2077 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 2078 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2079 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
7a65d170
EG		 2080 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2081 if (unlikely(ret < 0)) {
49564a80
LC		 2082 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2083
23ba9340
EG		 2084 WARN_ONCE(1,
2085 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2086 cntrl);
2087
2088 iwl_trans_pcie_dump_regs(trans);
2089
2090 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2091 struct iwl_trans_pcie_removal *removal;
2092
f60c9e59 2093 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
49564a80
LC		 2094 goto err;
2095
2096 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2097
2098 /*
2099 * get a module reference to avoid doing this
2100 * while unloading anyway and to avoid
2101 * scheduling a work with code that's being
2102 * removed.
2103 */
2104 if (!try_module_get(THIS_MODULE)) {
2105 IWL_ERR(trans,
2106 "Module is being unloaded - abort\n");
2107 goto err;
2108 }
2109
2110 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2111 if (!removal) {
2112 module_put(THIS_MODULE);
2113 goto err;
2114 }
2115 /*
2116 * we don't need to clear this flag, because
2117 * the trans will be freed and reallocated.
2118 */
f60c9e59 2119 set_bit(STATUS_TRANS_DEAD, &trans->status);
49564a80
LC		 2120
2121 removal->pdev = to_pci_dev(trans->dev);
2122 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2123 pci_dev_get(removal->pdev);
2124 schedule_work(&removal->work);
2125 } else {
2126 iwl_write32(trans, CSR_RESET,
2127 CSR_RESET_REG_FLAG_FORCE_NMI);
2128 }
2129
2130err:
23ba9340
EG		 2131 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2132 return false;
7a65d170
EG		 2133 }
2134
b9439491 2135out:
e56b04ef
LE		 2136 /*
2137 * Fool sparse by faking we release the lock - sparse will
2138 * track nic_access anyway.
2139 */
cfb4e624 2140 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2141 return true;
2142}
2143
e56b04ef
LE		 2144static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2145 unsigned long *flags)
7a65d170 2146{
cfb4e624 2147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2148
cfb4e624 2149 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2150
2151 /*
2152 * Fool sparse by faking we acquiring the lock - sparse will
2153 * track nic_access anyway.
2154 */
cfb4e624 2155 __acquire(&trans_pcie->reg_lock);
e56b04ef 2156
fc8a350d 2157 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2158 goto out;
2159
e139dc4a 2160 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 2161 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2162 /*
2163 * Above we read the CSR_GP_CNTRL register, which will flush
2164 * any previous writes, but we need the write that clears the
2165 * MAC_ACCESS_REQ bit to be performed before any other writes
2166 * scheduled on different CPUs (after we drop reg_lock).
2167 */
b9439491 2168out:
cfb4e624 2169 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2170}
2171
4fd442db
EG		 2172static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2173 void *buf, int dwords)
2174{
2175 unsigned long flags;
2176 int offs, ret = 0;
2177 u32 *vals = buf;
2178
23ba9340 2179 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2180 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2181 for (offs = 0; offs < dwords; offs++)
2182 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2183 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2184 } else {
2185 ret = -EBUSY;
2186 }
4fd442db
EG		 2187 return ret;
2188}
2189
2190static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2191 const void *buf, int dwords)
4fd442db
EG		 2192{
2193 unsigned long flags;
2194 int offs, ret = 0;
bf0fd5da 2195 const u32 *vals = buf;
4fd442db 2196
23ba9340 2197 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2198 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2199 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2200 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2201 vals ? vals[offs] : 0);
e56b04ef 2202 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2203 } else {
2204 ret = -EBUSY;
2205 }
4fd442db
EG		 2206 return ret;
2207}
7a65d170 2208
7f1fe1d4
LC		 2209static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2210 u32 *val)
2211{
2212 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2213 ofs, val);
2214}
2215
e0b8d405
EG		 2216static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2217 unsigned long txqs,
2218 bool freeze)
2219{
2220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2221 int queue;
2222
2223 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2224 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2225 unsigned long now;
2226
2227 spin_lock_bh(&txq->lock);
2228
2229 now = jiffies;
2230
2231 if (txq->frozen == freeze)
2232 goto next_queue;
2233
2234 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2235 freeze ? "Freezing" : "Waking", queue);
2236
2237 txq->frozen = freeze;
2238
bb98ecd4 2239 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2240 goto next_queue;
2241
2242 if (freeze) {
2243 if (unlikely(time_after(now,
2244 txq->stuck_timer.expires))) {
2245 /*
2246 * The timer should have fired, maybe it is
2247 * spinning right now on the lock.
2248 */
2249 goto next_queue;
2250 }
2251 /* remember how long until the timer fires */
2252 txq->frozen_expiry_remainder =
2253 txq->stuck_timer.expires - now;
2254 del_timer(&txq->stuck_timer);
2255 goto next_queue;
2256 }
2257
2258 /*
2259 * Wake a non-empty queue -> arm timer with the
2260 * remainder before it froze
2261 */
2262 mod_timer(&txq->stuck_timer,
2263 now + txq->frozen_expiry_remainder);
2264
2265next_queue:
2266 spin_unlock_bh(&txq->lock);
2267 }
2268}
2269
0cd58eaa
EG		 2270static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2271{
2272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2273 int i;
2274
286ca8eb 2275 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2276 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2277
2278 if (i == trans_pcie->cmd_queue)
2279 continue;
2280
2281 spin_lock_bh(&txq->lock);
2282
2283 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2284 txq->block--;
2285 if (!txq->block) {
2286 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2287 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2288 }
2289 } else if (block) {
2290 txq->block++;
2291 }
2292
2293 spin_unlock_bh(&txq->lock);
2294 }
2295}
2296
5f178cd2
EG		 2297#define IWL_FLUSH_WAIT_MS 2000
2298
38398efb
SS		 2299void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2300{
afb84431
EG		 2301 u32 txq_id = txq->id;
2302 u32 status;
2303 bool active;
2304 u8 fifo;
38398efb 2305
286ca8eb 2306 if (trans->trans_cfg->use_tfh) {
afb84431
EG		 2307 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2308 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2309 /* TODO: access new SCD registers and dump them */
2310 return;
38398efb 2311 }
afb84431
EG		 2312
2313 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2314 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2315 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2316
2317 IWL_ERR(trans,
2318 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2319 txq_id, active ? "" : "in", fifo,
2320 jiffies_to_msecs(txq->wd_timeout),
2321 txq->read_ptr, txq->write_ptr,
2322 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
286ca8eb
LC		 2323 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2324 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2325 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2326 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2327}
2328
92536c96
SS		 2329static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2330 struct iwl_trans_rxq_dma_data *data)
2331{
2332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2333
2334 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2335 return -EINVAL;
2336
2337 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2338 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2339 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2340 data->fr_bd_wid = 0;
2341
2342 return 0;
2343}
2344
d6d517b7 2345static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2346{
8ad71bef 2347 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2348 struct iwl_txq *txq;
5f178cd2 2349 unsigned long now = jiffies;
2ae48edc 2350 bool overflow_tx;
d6d517b7
SS		 2351 u8 wr_ptr;
2352
2b3fae66 2353 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2354 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2355 return -ENODEV;
2b3fae66 2356
d6d517b7
SS		 2357 if (!test_bit(txq_idx, trans_pcie->queue_used))
2358 return -EINVAL;
2359
2360 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2361 txq = trans_pcie->txq[txq_idx];
2ae48edc
SS		 2362
2363 spin_lock_bh(&txq->lock);
2364 overflow_tx = txq->overflow_tx ||
2365 !skb_queue_empty(&txq->overflow_q);
2366 spin_unlock_bh(&txq->lock);
2367
6aa7de05 2368 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2369
2ae48edc
SS		 2370 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2371 overflow_tx) &&
d6d517b7
SS		 2372 !time_after(jiffies,
2373 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2374 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2375
2ae48edc
SS		 2376 /*
2377 * If write pointer moved during the wait, warn only
2378 * if the TX came from op mode. In case TX came from
2379 * trans layer (overflow TX) don't warn.
2380 */
2381 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2382 "WR pointer moved while flushing %d -> %d\n",
2383 wr_ptr, write_ptr))
2384 return -ETIMEDOUT;
2ae48edc
SS		 2385 wr_ptr = write_ptr;
2386
d6d517b7 2387 usleep_range(1000, 2000);
2ae48edc
SS		 2388
2389 spin_lock_bh(&txq->lock);
2390 overflow_tx = txq->overflow_tx ||
2391 !skb_queue_empty(&txq->overflow_q);
2392 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2393 }
2394
2395 if (txq->read_ptr != txq->write_ptr) {
2396 IWL_ERR(trans,
2397 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2398 iwl_trans_pcie_log_scd_error(trans, txq);
2399 return -ETIMEDOUT;
2400 }
2401
2402 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2403
2404 return 0;
2405}
2406
2407static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2408{
2409 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2410 int cnt;
5f178cd2
EG		 2411 int ret = 0;
2412
2413 /* waiting for all the tx frames complete might take a while */
79b6c8fe 2414 for (cnt = 0;
286ca8eb 2415 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2416 cnt++) {
fa1a91fd 2417
9ba1947a 2418 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2419 continue;
3cafdbe6
EG		 2420 if (!test_bit(cnt, trans_pcie->queue_used))
2421 continue;
2422 if (!(BIT(cnt) & txq_bm))
2423 continue;
748fa67c 2424
d6d517b7
SS		 2425 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2426 if (ret)
5f178cd2 2427 break;
5f178cd2 2428 }
1c3fea82 2429
5f178cd2
EG		 2430 return ret;
2431}
2432
e139dc4a
LE		 2433static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2434 u32 mask, u32 value)
2435{
e56b04ef 2436 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2437 unsigned long flags;
2438
e56b04ef 2439 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2440 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2441 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2442}
2443
ff620849
EG		 2444static const char *get_csr_string(int cmd)
2445{
d9fb6465 2446#define IWL_CMD(x) case x: return #x
ff620849
EG		 2447 switch (cmd) {
2448 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2449 IWL_CMD(CSR_INT_COALESCING);
2450 IWL_CMD(CSR_INT);
2451 IWL_CMD(CSR_INT_MASK);
2452 IWL_CMD(CSR_FH_INT_STATUS);
2453 IWL_CMD(CSR_GPIO_IN);
2454 IWL_CMD(CSR_RESET);
2455 IWL_CMD(CSR_GP_CNTRL);
2456 IWL_CMD(CSR_HW_REV);
2457 IWL_CMD(CSR_EEPROM_REG);
2458 IWL_CMD(CSR_EEPROM_GP);
2459 IWL_CMD(CSR_OTP_GP_REG);
2460 IWL_CMD(CSR_GIO_REG);
2461 IWL_CMD(CSR_GP_UCODE_REG);
2462 IWL_CMD(CSR_GP_DRIVER_REG);
2463 IWL_CMD(CSR_UCODE_DRV_GP1);
2464 IWL_CMD(CSR_UCODE_DRV_GP2);
2465 IWL_CMD(CSR_LED_REG);
2466 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2467 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2468 IWL_CMD(CSR_ANA_PLL_CFG);
2469 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2470 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2471 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2472 default:
2473 return "UNKNOWN";
2474 }
d9fb6465 2475#undef IWL_CMD
ff620849
EG		 2476}
2477
990aa6d7 2478void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2479{
2480 int i;
2481 static const u32 csr_tbl[] = {
2482 CSR_HW_IF_CONFIG_REG,
2483 CSR_INT_COALESCING,
2484 CSR_INT,
2485 CSR_INT_MASK,
2486 CSR_FH_INT_STATUS,
2487 CSR_GPIO_IN,
2488 CSR_RESET,
2489 CSR_GP_CNTRL,
2490 CSR_HW_REV,
2491 CSR_EEPROM_REG,
2492 CSR_EEPROM_GP,
2493 CSR_OTP_GP_REG,
2494 CSR_GIO_REG,
2495 CSR_GP_UCODE_REG,
2496 CSR_GP_DRIVER_REG,
2497 CSR_UCODE_DRV_GP1,
2498 CSR_UCODE_DRV_GP2,
2499 CSR_LED_REG,
2500 CSR_DRAM_INT_TBL_REG,
2501 CSR_GIO_CHICKEN_BITS,
2502 CSR_ANA_PLL_CFG,
a812cba9 2503 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2504 CSR_HW_REV_WA_REG,
2505 CSR_DBG_HPET_MEM_REG
2506 };
2507 IWL_ERR(trans, "CSR values:\n");
2508 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2509 "CSR_INT_PERIODIC_REG)\n");
2510 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2511 IWL_ERR(trans, " %25s: 0X%08x\n",
2512 get_csr_string(csr_tbl[i]),
1042db2a 2513 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2514 }
2515}
2516
87e5666c
EG		 2517#ifdef CONFIG_IWLWIFI_DEBUGFS
2518/* create and remove of files */
2519#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
cf5d5663
GKH		 2520 debugfs_create_file(#name, mode, parent, trans, \
2521 &iwl_dbgfs_##name##_ops); \
87e5666c
EG		 2522} while (0)
2523
2524/* file operation */
87e5666c 2525#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2526static const struct file_operations iwl_dbgfs_##name##_ops = { \
2527 .read = iwl_dbgfs_##name##_read, \
234e3405 2528 .open = simple_open, \
87e5666c
EG		 2529 .llseek = generic_file_llseek, \
2530};
2531
16db88ba 2532#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2533static const struct file_operations iwl_dbgfs_##name##_ops = { \
2534 .write = iwl_dbgfs_##name##_write, \
234e3405 2535 .open = simple_open, \
16db88ba
EG		 2536 .llseek = generic_file_llseek, \
2537};
2538
87e5666c 2539#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2540static const struct file_operations iwl_dbgfs_##name##_ops = { \
2541 .write = iwl_dbgfs_##name##_write, \
2542 .read = iwl_dbgfs_##name##_read, \
234e3405 2543 .open = simple_open, \
87e5666c
EG		 2544 .llseek = generic_file_llseek, \
2545};
2546
87e5666c 2547static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2548 char __user *user_buf,
2549 size_t count, loff_t *ppos)
8ad71bef 2550{
5a878bf6 2551 struct iwl_trans *trans = file->private_data;
8ad71bef 2552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2553 struct iwl_txq *txq;
87e5666c
EG		 2554 char *buf;
2555 int pos = 0;
2556 int cnt;
2557 int ret;
1745e440
WYG		 2558 size_t bufsz;
2559
79b6c8fe 2560 bufsz = sizeof(char) * 75 *
286ca8eb 2561 trans->trans_cfg->base_params->num_of_queues;
87e5666c 2562
b2a3b1c1 2563 if (!trans_pcie->txq_memory)
87e5666c 2564 return -EAGAIN;
f9e75447 2565
87e5666c
EG		 2566 buf = kzalloc(bufsz, GFP_KERNEL);
2567 if (!buf)
2568 return -ENOMEM;
2569
79b6c8fe 2570 for (cnt = 0;
286ca8eb 2571 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2572 cnt++) {
b2a3b1c1 2573 txq = trans_pcie->txq[cnt];
87e5666c 2574 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2575 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2576 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2577 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2578 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2579 txq->need_update, txq->frozen,
f40faf62 2580 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2581 }
2582 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2583 kfree(buf);
2584 return ret;
2585}
2586
2587static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2588 char __user *user_buf,
2589 size_t count, loff_t *ppos)
2590{
5a878bf6 2591 struct iwl_trans *trans = file->private_data;
20d3b647 2592 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2593 char *buf;
2594 int pos = 0, i, ret;
eb3dc36e 2595 size_t bufsz;
78485054
SS		 2596
2597 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2598
2599 if (!trans_pcie->rxq)
2600 return -EAGAIN;
2601
2602 buf = kzalloc(bufsz, GFP_KERNEL);
2603 if (!buf)
2604 return -ENOMEM;
2605
2606 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2607 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2608
2609 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2610 i);
2611 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2612 rxq->read);
2613 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2614 rxq->write);
2615 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2616 rxq->write_actual);
2617 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2618 rxq->need_update);
2619 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2620 rxq->free_count);
2621 if (rxq->rb_stts) {
0307c839
GBA		 2622 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2623 rxq));
78485054
SS		 2624 pos += scnprintf(buf + pos, bufsz - pos,
2625 "\tclosed_rb_num: %u\n",
0307c839 2626 r & 0x0FFF);
78485054
SS		 2627 } else {
2628 pos += scnprintf(buf + pos, bufsz - pos,
2629 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2630 }
87e5666c 2631 }
78485054
SS		 2632 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2633 kfree(buf);
2634
2635 return ret;
87e5666c
EG		 2636}
2637
1f7b6172
EG		 2638static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2639 char __user *user_buf,
20d3b647
JB		 2640 size_t count, loff_t *ppos)
2641{
1f7b6172 2642 struct iwl_trans *trans = file->private_data;
20d3b647 2643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2644 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2645
2646 int pos = 0;
2647 char *buf;
2648 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2649 ssize_t ret;
2650
2651 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2652 if (!buf)
1f7b6172 2653 return -ENOMEM;
1f7b6172
EG		 2654
2655 pos += scnprintf(buf + pos, bufsz - pos,
2656 "Interrupt Statistics Report:\n");
2657
2658 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2659 isr_stats->hw);
2660 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2661 isr_stats->sw);
2662 if (isr_stats->sw || isr_stats->hw) {
2663 pos += scnprintf(buf + pos, bufsz - pos,
2664 "\tLast Restarting Code: 0x%X\n",
2665 isr_stats->err_code);
2666 }
2667#ifdef CONFIG_IWLWIFI_DEBUG
2668 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2669 isr_stats->sch);
2670 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2671 isr_stats->alive);
2672#endif
2673 pos += scnprintf(buf + pos, bufsz - pos,
2674 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2675
2676 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2677 isr_stats->ctkill);
2678
2679 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2680 isr_stats->wakeup);
2681
2682 pos += scnprintf(buf + pos, bufsz - pos,
2683 "Rx command responses:\t\t %u\n", isr_stats->rx);
2684
2685 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2686 isr_stats->tx);
2687
2688 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2689 isr_stats->unhandled);
2690
2691 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2692 kfree(buf);
2693 return ret;
2694}
2695
2696static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2697 const char __user *user_buf,
2698 size_t count, loff_t *ppos)
2699{
2700 struct iwl_trans *trans = file->private_data;
20d3b647 2701 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2702 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2703 u32 reset_flag;
078f1131 2704 int ret;
1f7b6172 2705
078f1131
JB		 2706 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2707 if (ret)
2708 return ret;
1f7b6172
EG		 2709 if (reset_flag == 0)
2710 memset(isr_stats, 0, sizeof(*isr_stats));
2711
2712 return count;
2713}
2714
16db88ba 2715static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2716 const char __user *user_buf,
2717 size_t count, loff_t *ppos)
16db88ba
EG		 2718{
2719 struct iwl_trans *trans = file->private_data;
16db88ba 2720
990aa6d7 2721 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2722
2723 return count;
2724}
2725
16db88ba 2726static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2727 char __user *user_buf,
2728 size_t count, loff_t *ppos)
16db88ba
EG		 2729{
2730 struct iwl_trans *trans = file->private_data;
94543a8d 2731 char *buf = NULL;
56c2477f 2732 ssize_t ret;
16db88ba 2733
56c2477f
JB		 2734 ret = iwl_dump_fh(trans, &buf);
2735 if (ret < 0)
2736 return ret;
2737 if (!buf)
2738 return -EINVAL;
2739 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2740 kfree(buf);
16db88ba
EG		 2741 return ret;
2742}
2743
fa4de7f7
JB		 2744static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2745 char __user *user_buf,
2746 size_t count, loff_t *ppos)
2747{
2748 struct iwl_trans *trans = file->private_data;
2749 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2750 char buf[100];
2751 int pos;
2752
2753 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2754 trans_pcie->debug_rfkill,
2755 !(iwl_read32(trans, CSR_GP_CNTRL) &
2756 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2757
2758 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2759}
2760
2761static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2762 const char __user *user_buf,
2763 size_t count, loff_t *ppos)
2764{
2765 struct iwl_trans *trans = file->private_data;
2766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c5bf4fa1 2767 bool new_value;
fa4de7f7
JB		 2768 int ret;
2769
c5bf4fa1 2770 ret = kstrtobool_from_user(user_buf, count, &new_value);
fa4de7f7
JB		 2771 if (ret)
2772 return ret;
c5bf4fa1 2773 if (new_value == trans_pcie->debug_rfkill)
fa4de7f7
JB		 2774 return count;
2775 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
c5bf4fa1
JB		 2776 trans_pcie->debug_rfkill, new_value);
2777 trans_pcie->debug_rfkill = new_value;
fa4de7f7
JB		 2778 iwl_pcie_handle_rfkill_irq(trans);
2779
2780 return count;
2781}
2782
f7805b33
LC		 2783static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2784 struct file *file)
2785{
2786 struct iwl_trans *trans = inode->i_private;
2787 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2788
91c28b83
SM		 2789 if (!trans->dbg.dest_tlv ||
2790 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
f7805b33
LC		 2791 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2792 return -ENOENT;
2793 }
2794
2795 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2796 return -EBUSY;
2797
2798 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2799 return simple_open(inode, file);
2800}
2801
2802static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2803 struct file *file)
2804{
2805 struct iwl_trans_pcie *trans_pcie =
2806 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2807
2808 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2809 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2810 return 0;
2811}
2812
2813static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2814 void *buf, ssize_t *size,
2815 ssize_t *bytes_copied)
2816{
2817 int buf_size_left = count - *bytes_copied;
2818
2819 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2820 if (*size > buf_size_left)
2821 *size = buf_size_left;
2822
2823 *size -= copy_to_user(user_buf, buf, *size);
2824 *bytes_copied += *size;
2825
2826 if (buf_size_left == *size)
2827 return true;
2828 return false;
2829}
2830
2831static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2832 char __user *user_buf,
2833 size_t count, loff_t *ppos)
2834{
2835 struct iwl_trans *trans = file->private_data;
2836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
69f0e505 2837 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
f7805b33
LC		 2838 struct cont_rec *data = &trans_pcie->fw_mon_data;
2839 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2840 ssize_t size, bytes_copied = 0;
2841 bool b_full;
2842
91c28b83 2843 if (trans->dbg.dest_tlv) {
f7805b33 2844 write_ptr_addr =
91c28b83
SM		 2845 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2846 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
f7805b33
LC		 2847 } else {
2848 write_ptr_addr = MON_BUFF_WRPTR;
2849 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2850 }
2851
91c28b83 2852 if (unlikely(!trans->dbg.rec_on))
f7805b33
LC		 2853 return 0;
2854
2855 mutex_lock(&data->mutex);
2856 if (data->state ==
2857 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2858 mutex_unlock(&data->mutex);
2859 return 0;
2860 }
2861
2862 /* write_ptr position in bytes rather then DW */
2863 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2864 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2865
2866 if (data->prev_wrap_cnt == wrap_cnt) {
2867 size = write_ptr - data->prev_wr_ptr;
2868 curr_buf = cpu_addr + data->prev_wr_ptr;
2869 b_full = iwl_write_to_user_buf(user_buf, count,
2870 curr_buf, &size,
2871 &bytes_copied);
2872 data->prev_wr_ptr += size;
2873
2874 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2875 write_ptr < data->prev_wr_ptr) {
69f0e505 2876 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
f7805b33
LC		 2877 curr_buf = cpu_addr + data->prev_wr_ptr;
2878 b_full = iwl_write_to_user_buf(user_buf, count,
2879 curr_buf, &size,
2880 &bytes_copied);
2881 data->prev_wr_ptr += size;
2882
2883 if (!b_full) {
2884 size = write_ptr;
2885 b_full = iwl_write_to_user_buf(user_buf, count,
2886 cpu_addr, &size,
2887 &bytes_copied);
2888 data->prev_wr_ptr = size;
2889 data->prev_wrap_cnt++;
2890 }
2891 } else {
2892 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2893 write_ptr > data->prev_wr_ptr)
2894 IWL_WARN(trans,
2895 "write pointer passed previous write pointer, start copying from the beginning\n");
2896 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2897 data->prev_wr_ptr == 0))
2898 IWL_WARN(trans,
2899 "monitor data is out of sync, start copying from the beginning\n");
2900
2901 size = write_ptr;
2902 b_full = iwl_write_to_user_buf(user_buf, count,
2903 cpu_addr, &size,
2904 &bytes_copied);
2905 data->prev_wr_ptr = size;
2906 data->prev_wrap_cnt = wrap_cnt;
2907 }
2908
2909 mutex_unlock(&data->mutex);
2910
2911 return bytes_copied;
2912}
2913
1f7b6172 2914DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2915DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2916DEBUGFS_READ_FILE_OPS(rx_queue);
2917DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2918DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2919DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2920
f7805b33
LC		 2921static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2922 .read = iwl_dbgfs_monitor_data_read,
2923 .open = iwl_dbgfs_monitor_data_open,
2924 .release = iwl_dbgfs_monitor_data_release,
2925};
2926
f8a1edb7 2927/* Create the debugfs files and directories */
cf5d5663 2928void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2929{
f8a1edb7
JB		 2930 struct dentry *dir = trans->dbgfs_dir;
2931
2ef00c53
JP		 2932 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2933 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2934 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2935 DEBUGFS_ADD_FILE(csr, dir, 0200);
2936 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2937 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 2938 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
87e5666c 2939}
f7805b33
LC		 2940
2941static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2942{
2943 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2944 struct cont_rec *data = &trans_pcie->fw_mon_data;
2945
2946 mutex_lock(&data->mutex);
2947 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2948 mutex_unlock(&data->mutex);
2949}
aadede6e 2950#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2951
6983ba69 2952static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2953{
3cd1980b 2954 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2955 u32 cmdlen = 0;
2956 int i;
2957
3cd1980b 2958 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2959 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2960
2961 return cmdlen;
2962}
2963
bd7fc617
EG		 2964static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2965 struct iwl_fw_error_dump_data **data,
2966 int allocated_rb_nums)
2967{
2968 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
80084e35 2969 int max_len = trans_pcie->rx_buf_bytes;
78485054
SS		 2970 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2971 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2972 u32 i, r, j, rb_len = 0;
2973
2974 spin_lock(&rxq->lock);
2975
0307c839 2976 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2977
2978 for (i = rxq->read, j = 0;
2979 i != r && j < allocated_rb_nums;
2980 i = (i + 1) & RX_QUEUE_MASK, j++) {
2981 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2982 struct iwl_fw_error_dump_rb *rb;
2983
2984 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2985 DMA_FROM_DEVICE);
2986
2987 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2988
2989 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2990 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2991 rb = (void *)(*data)->data;
2992 rb->index = cpu_to_le32(i);
2993 memcpy(rb->data, page_address(rxb->page), max_len);
2994 /* remap the page for the free benefit */
cfdc20ef
JB		 2995 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
2996 rxb->offset, max_len,
2997 DMA_FROM_DEVICE);
bd7fc617
EG		 2998
2999 *data = iwl_fw_error_next_data(*data);
3000 }
3001
3002 spin_unlock(&rxq->lock);
3003
3004 return rb_len;
3005}
473ad712
EG		 3006#define IWL_CSR_TO_DUMP (0x250)
3007
3008static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3009 struct iwl_fw_error_dump_data **data)
3010{
3011 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3012 __le32 *val;
3013 int i;
3014
3015 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3016 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3017 val = (void *)(*data)->data;
3018
3019 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3020 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3021
3022 *data = iwl_fw_error_next_data(*data);
3023
3024 return csr_len;
3025}
3026
06d51e0d
LK		 3027static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3028 struct iwl_fw_error_dump_data **data)
3029{
3030 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3031 unsigned long flags;
3032 __le32 *val;
3033 int i;
3034
23ba9340 3035 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 3036 return 0;
3037
3038 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3039 (*data)->len = cpu_to_le32(fh_regs_len);
3040 val = (void *)(*data)->data;
3041
286ca8eb 3042 if (!trans->trans_cfg->gen2)
723b45e2
LK		 3043 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3044 i += sizeof(u32))
3045 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3046 else
ea695b7c
ST		 3047 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3048 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 3049 i += sizeof(u32))
3050 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3051 i));
06d51e0d
LK		 3052
3053 iwl_trans_release_nic_access(trans, &flags);
3054
3055 *data = iwl_fw_error_next_data(*data);
3056
3057 return sizeof(**data) + fh_regs_len;
3058}
3059
cc79ef66
LK		 3060static u32
3061iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3062 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3063 u32 monitor_len)
3064{
3065 u32 buf_size_in_dwords = (monitor_len >> 2);
3066 u32 *buffer = (u32 *)fw_mon_data->data;
3067 unsigned long flags;
3068 u32 i;
3069
23ba9340 3070 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 3071 return 0;
3072
ea695b7c 3073 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 3074 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 3075 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3076 MON_DMARB_RD_DATA_ADDR);
3077 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 3078
3079 iwl_trans_release_nic_access(trans, &flags);
3080
3081 return monitor_len;
3082}
3083
7a14c23d
SS		 3084static void
3085iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3086 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3087{
c88580e1 3088 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
7a14c23d 3089
286ca8eb 3090 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3091 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3092 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3093 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3094 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
91c28b83
SM		 3095 } else if (trans->dbg.dest_tlv) {
3096 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3097 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3098 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
7a14c23d
SS		 3099 } else {
3100 base = MON_BUFF_BASE_ADDR;
3101 write_ptr = MON_BUFF_WRPTR;
3102 wrap_cnt = MON_BUFF_CYCLE_CNT;
3103 }
c88580e1
SM		 3104
3105 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3106 fw_mon_data->fw_mon_cycle_cnt =
3107 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3108 fw_mon_data->fw_mon_base_ptr =
3109 cpu_to_le32(iwl_read_prph(trans, base));
286ca8eb 3110 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3111 fw_mon_data->fw_mon_base_high_ptr =
3112 cpu_to_le32(iwl_read_prph(trans, base_high));
3113 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3114 }
3115 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3116}
3117
36fb9017
OG		 3118static u32
3119iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3120 struct iwl_fw_error_dump_data **data,
3121 u32 monitor_len)
3122{
69f0e505 3123 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
36fb9017
OG		 3124 u32 len = 0;
3125
91c28b83 3126 if (trans->dbg.dest_tlv ||
69f0e505 3127 (fw_mon->size &&
286ca8eb
LC		 3128 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3129 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
36fb9017 3130 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3131
3132 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3133 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3134
3135 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3136
3137 len += sizeof(**data) + sizeof(*fw_mon_data);
69f0e505
SM		 3138 if (fw_mon->size) {
3139 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3140 monitor_len = fw_mon->size;
91c28b83 3141 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3142 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3143 /*
3144 * Update pointers to reflect actual values after
3145 * shifting
3146 */
91c28b83 3147 if (trans->dbg.dest_tlv->version) {
fd527eb5
GBA		 3148 base = (iwl_read_prph(trans, base) &
3149 IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3150 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3151 base *= IWL_M2S_UNIT_SIZE;
3152 base += trans->cfg->smem_offset;
3153 } else {
3154 base = iwl_read_prph(trans, base) <<
91c28b83 3155 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3156 }
3157
36fb9017
OG		 3158 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3159 monitor_len / sizeof(u32));
91c28b83 3160 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
36fb9017
OG		 3161 monitor_len =
3162 iwl_trans_pci_dump_marbh_monitor(trans,
3163 fw_mon_data,
3164 monitor_len);
3165 } else {
3166 /* Didn't match anything - output no monitor data */
3167 monitor_len = 0;
3168 }
3169
3170 len += monitor_len;
3171 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3172 }
3173
3174 return len;
3175}
3176
93079fd5 3177static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3178{
69f0e505 3179 if (trans->dbg.fw_mon.size) {
da752717
SM		 3180 *len += sizeof(struct iwl_fw_error_dump_data) +
3181 sizeof(struct iwl_fw_error_dump_fw_mon) +
69f0e505
SM		 3182 trans->dbg.fw_mon.size;
3183 return trans->dbg.fw_mon.size;
91c28b83 3184 } else if (trans->dbg.dest_tlv) {
da752717 3185 u32 base, end, cfg_reg, monitor_len;
99684ae3 3186
91c28b83
SM		 3187 if (trans->dbg.dest_tlv->version == 1) {
3188 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
fd527eb5
GBA		 3189 cfg_reg = iwl_read_prph(trans, cfg_reg);
3190 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3191 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3192 base *= IWL_M2S_UNIT_SIZE;
3193 base += trans->cfg->smem_offset;
99684ae3 3194
fd527eb5
GBA		 3195 monitor_len =
3196 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
91c28b83 3197 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3198 monitor_len *= IWL_M2S_UNIT_SIZE;
3199 } else {
91c28b83
SM		 3200 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3201 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
99684ae3 3202
fd527eb5 3203 base = iwl_read_prph(trans, base) <<
91c28b83 3204 trans->dbg.dest_tlv->base_shift;
fd527eb5 3205 end = iwl_read_prph(trans, end) <<
91c28b83 3206 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3207
3208 /* Make "end" point to the actual end */
286ca8eb 3209 if (trans->trans_cfg->device_family >=
fd527eb5 3210 IWL_DEVICE_FAMILY_8000 ||
91c28b83
SM		 3211 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3212 end += (1 << trans->dbg.dest_tlv->end_shift);
fd527eb5
GBA		 3213 monitor_len = end - base;
3214 }
da752717
SM		 3215 *len += sizeof(struct iwl_fw_error_dump_data) +
3216 sizeof(struct iwl_fw_error_dump_fw_mon) +
3217 monitor_len;
3218 return monitor_len;
99684ae3 3219 }
da752717
SM		 3220 return 0;
3221}
3222
3223static struct iwl_trans_dump_data
3224*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
79f033f6 3225 u32 dump_mask)
da752717
SM		 3226{
3227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3228 struct iwl_fw_error_dump_data *data;
3229 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3230 struct iwl_fw_error_dump_txcmd *txcmd;
3231 struct iwl_trans_dump_data *dump_data;
fefbf853 3232 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3233 int i, ptr;
3234 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
286ca8eb 3235 !trans->trans_cfg->mq_rx_supported &&
79f033f6
SS		 3236 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3237
3238 if (!dump_mask)
3239 return NULL;
da752717
SM		 3240
3241 /* transport dump header */
3242 len = sizeof(*dump_data);
3243
3244 /* host commands */
e4eee943 3245 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
8672aad3
SM		 3246 len += sizeof(*data) +
3247 cmdq->n_window * (sizeof(*txcmd) +
3248 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3249
3250 /* FW monitor */
fefbf853
SM		 3251 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3252 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3253
3254 /* CSR registers */
79f033f6 3255 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3256 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3257
36fb9017 3258 /* FH registers */
79f033f6 3259 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
286ca8eb 3260 if (trans->trans_cfg->gen2)
520f03ea 3261 len += sizeof(*data) +
ea695b7c
ST		 3262 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3263 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3264 else
3265 len += sizeof(*data) +
3266 (FH_MEM_UPPER_BOUND -
3267 FH_MEM_LOWER_BOUND);
3268 }
36fb9017
OG		 3269
3270 if (dump_rbs) {
78485054
SS		 3271 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3272 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3273 /* RBs */
0307c839
GBA		 3274 num_rbs =
3275 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3276 & 0x0FFF;
78485054 3277 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3278 len += num_rbs * (sizeof(*data) +
3279 sizeof(struct iwl_fw_error_dump_rb) +
3280 (PAGE_SIZE << trans_pcie->rx_page_order));
3281 }
3282
5538409b 3283 /* Paged memory for gen2 HW */
286ca8eb 3284 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3285 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3286 len += sizeof(*data) +
3287 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3288 trans->init_dram.paging[i].size;
5538409b 3289
48eb7b34
EG		 3290 dump_data = vzalloc(len);
3291 if (!dump_data)
3292 return NULL;
4d075007
JB		 3293
3294 len = 0;
48eb7b34 3295 data = (void *)dump_data->data;
520f03ea 3296
e4eee943 3297 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
520f03ea
SM		 3298 u16 tfd_size = trans_pcie->tfd_size;
3299
3300 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3301 txcmd = (void *)data->data;
3302 spin_lock_bh(&cmdq->lock);
3303 ptr = cmdq->write_ptr;
3304 for (i = 0; i < cmdq->n_window; i++) {
3305 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
08326a97 3306 u8 tfdidx;
520f03ea
SM		 3307 u32 caplen, cmdlen;
3308
08326a97
JB		 3309 if (trans->trans_cfg->use_tfh)
3310 tfdidx = idx;
3311 else
3312 tfdidx = ptr;
3313
520f03ea 3314 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
08326a97
JB		 3315 (u8 *)cmdq->tfds +
3316 tfd_size * tfdidx);
520f03ea
SM		 3317 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3318
3319 if (cmdlen) {
3320 len += sizeof(*txcmd) + caplen;
3321 txcmd->cmdlen = cpu_to_le32(cmdlen);
3322 txcmd->caplen = cpu_to_le32(caplen);
3323 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3324 caplen);
3325 txcmd = (void *)((u8 *)txcmd->data + caplen);
3326 }
3327
3328 ptr = iwl_queue_dec_wrap(trans, ptr);
4d075007 3329 }
520f03ea 3330 spin_unlock_bh(&cmdq->lock);
4d075007 3331
520f03ea
SM		 3332 data->len = cpu_to_le32(len);
3333 len += sizeof(*data);
3334 data = iwl_fw_error_next_data(data);
4d075007 3335 }
67c65f2c 3336
79f033f6 3337 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3338 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3339 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3340 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3341 if (dump_rbs)
3342 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3343
5538409b 3344 /* Paged memory for gen2 HW */
286ca8eb 3345 if (trans->trans_cfg->gen2 &&
79b6c8fe 3346 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3347 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3348 struct iwl_fw_error_dump_paging *paging;
505a00c0 3349 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3350
3351 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3352 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3353 paging = (void *)data->data;
3354 paging->index = cpu_to_le32(i);
5538409b 3355 memcpy(paging->data,
505a00c0 3356 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3357 data = iwl_fw_error_next_data(data);
3358
3359 len += sizeof(*data) + sizeof(*paging) + page_len;
3360 }
3361 }
79f033f6 3362 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3363 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3364
48eb7b34
EG		 3365 dump_data->len = len;
3366
3367 return dump_data;
4d075007 3368}
87e5666c 3369
4cbb8e50
LC		 3370#ifdef CONFIG_PM_SLEEP
3371static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3372{
4cbb8e50
LC		 3373 return 0;
3374}
3375
3376static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3377{
4cbb8e50
LC		 3378}
3379#endif /* CONFIG_PM_SLEEP */
3380
623e7766
SS		 3381#define IWL_TRANS_COMMON_OPS \
3382 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3383 .write8 = iwl_trans_pcie_write8, \
3384 .write32 = iwl_trans_pcie_write32, \
3385 .read32 = iwl_trans_pcie_read32, \
3386 .read_prph = iwl_trans_pcie_read_prph, \
3387 .write_prph = iwl_trans_pcie_write_prph, \
3388 .read_mem = iwl_trans_pcie_read_mem, \
3389 .write_mem = iwl_trans_pcie_write_mem, \
7f1fe1d4 3390 .read_config32 = iwl_trans_pcie_read_config32, \
623e7766
SS		 3391 .configure = iwl_trans_pcie_configure, \
3392 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3393 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3394 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3395 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3396 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
623e7766 3397 .dump_data = iwl_trans_pcie_dump_data, \
623e7766 3398 .d3_suspend = iwl_trans_pcie_d3_suspend, \
d1967ce6
SM		 3399 .d3_resume = iwl_trans_pcie_d3_resume, \
3400 .sync_nmi = iwl_trans_pcie_sync_nmi
623e7766
SS		 3401
3402#ifdef CONFIG_PM_SLEEP
3403#define IWL_TRANS_PM_OPS \
3404 .suspend = iwl_trans_pcie_suspend, \
3405 .resume = iwl_trans_pcie_resume,
3406#else
3407#define IWL_TRANS_PM_OPS
3408#endif /* CONFIG_PM_SLEEP */
3409
d1ff5253 3410static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3411 IWL_TRANS_COMMON_OPS,
3412 IWL_TRANS_PM_OPS
57a1dc89 3413 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3414 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3415 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3416 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3417
623e7766 3418 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3419
623e7766
SS		 3420 .tx = iwl_trans_pcie_tx,
3421 .reclaim = iwl_trans_pcie_reclaim,
3422
3423 .txq_disable = iwl_trans_pcie_txq_disable,
3424 .txq_enable = iwl_trans_pcie_txq_enable,
3425
3426 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3427
d6d517b7
SS		 3428 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3429
623e7766
SS		 3430 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3431 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3432#ifdef CONFIG_IWLWIFI_DEBUGFS
3433 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3434#endif
623e7766
SS		 3435};
3436
3437static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3438 IWL_TRANS_COMMON_OPS,
3439 IWL_TRANS_PM_OPS
3440 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3441 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3442 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3443 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3444
ca60da2e 3445 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3446
ab6c6445 3447 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3448 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3449
ba7136f3
AM		 3450 .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3451
6b35ff91
SS		 3452 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3453 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3454 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3455 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
f7805b33
LC		 3456#ifdef CONFIG_IWLWIFI_DEBUGFS
3457 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3458#endif
e6bb4c9c 3459};
a42a1844 3460
87ce05a2 3461struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
7e8258c0
LC		 3462 const struct pci_device_id *ent,
3463 const struct iwl_cfg_trans_params *cfg_trans)
a42a1844 3464{
a42a1844
EG		 3465 struct iwl_trans_pcie *trans_pcie;
3466 struct iwl_trans *trans;
a89c72ff
JB		 3467 int ret, addr_size, txcmd_size, txcmd_align;
3468 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3469
3470 if (!cfg_trans->gen2) {
3471 ops = &trans_ops_pcie;
3472 txcmd_size = sizeof(struct iwl_tx_cmd);
3473 txcmd_align = sizeof(void *);
3474 } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) {
3475 txcmd_size = sizeof(struct iwl_tx_cmd_gen2);
3476 txcmd_align = 64;
3477 } else {
3478 txcmd_size = sizeof(struct iwl_tx_cmd_gen3);
3479 txcmd_align = 128;
3480 }
3481
3482 txcmd_size += sizeof(struct iwl_cmd_header);
3483 txcmd_size += 36; /* biggest possible 802.11 header */
3484
3485 /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */
3486 if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align))
3487 return ERR_PTR(-EINVAL);
a42a1844 3488
5a41a86c
SD		 3489 ret = pcim_enable_device(pdev);
3490 if (ret)
3491 return ERR_PTR(ret);
3492
a89c72ff
JB		 3493 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3494 txcmd_size, txcmd_align);
7b501d10
JB		 3495 if (!trans)
3496 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3497
3498 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3499
a42a1844 3500 trans_pcie->trans = trans;
326477e4 3501 trans_pcie->opmode_down = true;
7b11488f 3502 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3503 spin_lock_init(&trans_pcie->reg_lock);
cfdc20ef 3504 spin_lock_init(&trans_pcie->alloc_page_lock);
fa9f3281 3505 mutex_init(&trans_pcie->mutex);
13df1aab 3506 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
8188a18e
JB		 3507
3508 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3509 WQ_HIGHPRI | WQ_UNBOUND, 1);
3510 if (!trans_pcie->rba.alloc_wq) {
3511 ret = -ENOMEM;
3512 goto out_free_trans;
3513 }
3514 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3515
6eb5e529
EG		 3516 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3517 if (!trans_pcie->tso_hdr_page) {
3518 ret = -ENOMEM;
3519 goto out_no_pci;
3520 }
c5bf4fa1 3521 trans_pcie->debug_rfkill = -1;
d819c6cf 3522
7e8258c0 3523 if (!cfg_trans->base_params->pcie_l1_allowed) {
f2532b04
EG		 3524 /*
3525 * W/A - seems to solve weird behavior. We need to remove this
3526 * if we don't want to stay in L1 all the time. This wastes a
3527 * lot of power.
3528 */
3529 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3530 PCIE_LINK_STATE_L1 |
3531 PCIE_LINK_STATE_CLKPM);
3532 }
a42a1844 3533
9416560e
GBA		 3534 trans_pcie->def_rx_queue = 0;
3535
7e8258c0 3536 if (cfg_trans->use_tfh) {
2c6262b7 3537 addr_size = 64;
3cd1980b 3538 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3539 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3540 } else {
2c6262b7 3541 addr_size = 36;
3cd1980b 3542 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3543 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3544 }
3cd1980b
SS		 3545 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3546
a42a1844
EG		 3547 pci_set_master(pdev);
3548
96a6497b 3549 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3550 if (!ret)
96a6497b
SS		 3551 ret = pci_set_consistent_dma_mask(pdev,
3552 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3553 if (ret) {
3554 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3555 if (!ret)
3556 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3557 DMA_BIT_MASK(32));
a42a1844 3558 /* both attempts failed: */
af3f2f74 3559 if (ret) {
6a4b09f8 3560 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3561 goto out_no_pci;
a42a1844
EG		 3562 }
3563 }
3564
5a41a86c 3565 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3566 if (ret) {
5a41a86c
SD		 3567 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3568 goto out_no_pci;
a42a1844
EG		 3569 }
3570
5a41a86c 3571 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3572 if (!trans_pcie->hw_base) {
5a41a86c 3573 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3574 ret = -ENODEV;
5a41a86c 3575 goto out_no_pci;
a42a1844
EG		 3576 }
3577
a42a1844
EG		 3578 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3579 * PCI Tx retries from interfering with C3 CPU state */
3580 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3581
83f7a85f
EG		 3582 trans_pcie->pci_dev = pdev;
3583 iwl_disable_interrupts(trans);
3584
08079a49 3585 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3586 if (trans->hw_rev == 0xffffffff) {
3587 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3588 ret = -EIO;
3589 goto out_no_pci;
3590 }
3591
b513ee7f
LK		 3592 /*
3593 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3594 * changed, and now the revision step also includes bit 0-1 (no more
3595 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3596 * in the old format.
3597 */
7e8258c0 3598 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
b513ee7f 3599 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3600 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3601
f9e5554c
EG		 3602 ret = iwl_pcie_prepare_card_hw(trans);
3603 if (ret) {
3604 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3605 goto out_no_pci;
f9e5554c
EG		 3606 }
3607
7a42baa6
EH		 3608 /*
3609 * in-order to recognize C step driver should read chip version
3610 * id located at the AUX bus MISC address space.
3611 */
7e8258c0 3612 ret = iwl_finish_nic_init(trans, cfg_trans);
c96b5eec 3613 if (ret)
5a41a86c 3614 goto out_no_pci;
7a42baa6 3615
7a42baa6
EH		 3616 }
3617
99be6166
LC		 3618 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3619
7e8258c0 3620 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
99673ee5 3621 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3622 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3623 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3624
69a10b29 3625 /* Initialize the wait queue for commands */
f946b529 3626 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3627
e5f3f215
HD		 3628 init_waitqueue_head(&trans_pcie->sx_waitq);
3629
2e5d4a8f 3630 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3631 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3632 if (ret)
5a41a86c 3633 goto out_no_pci;
2e5d4a8f
HD		 3634 } else {
3635 ret = iwl_pcie_alloc_ict(trans);
3636 if (ret)
5a41a86c 3637 goto out_no_pci;
a8b691e6 3638
5a41a86c
SD		 3639 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3640 iwl_pcie_isr,
3641 iwl_pcie_irq_handler,
3642 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3643 if (ret) {
3644 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3645 goto out_free_ict;
3646 }
3647 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3648 }
83f7a85f 3649
f7805b33
LC		 3650#ifdef CONFIG_IWLWIFI_DEBUGFS
3651 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3652 mutex_init(&trans_pcie->fw_mon_data.mutex);
3653#endif
3654
a9248de4
SM		 3655 iwl_dbg_tlv_init(trans);
3656
a42a1844
EG		 3657 return trans;
3658
a8b691e6
JB		 3659out_free_ict:
3660 iwl_pcie_free_ict(trans);
a42a1844 3661out_no_pci:
6eb5e529 3662 free_percpu(trans_pcie->tso_hdr_page);
8188a18e
JB		 3663 destroy_workqueue(trans_pcie->rba.alloc_wq);
3664out_free_trans:
7b501d10 3665 iwl_trans_free(trans);
af3f2f74 3666 return ERR_PTR(ret);
a42a1844 3667}
b8a7547d 3668
d1967ce6 3669void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
b8a7547d 3670{
1c6bca6d 3671 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
b8a7547d 3672 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
e4eee943 3673 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
1c6bca6d
SM		 3674 u32 inta_addr, sw_err_bit;
3675
3676 if (trans_pcie->msix_enabled) {
3677 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3678 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3679 } else {
3680 inta_addr = CSR_INT;
3681 sw_err_bit = CSR_INT_BIT_SW_ERR;
3682 }
b8a7547d 3683
e4eee943
SM		 3684 /* if the interrupts were already disabled, there is no point in
3685 * calling iwl_disable_interrupts
3686 */
3687 if (interrupts_enabled)
3688 iwl_disable_interrupts(trans);
3689
b8a7547d
SM		 3690 iwl_force_nmi(trans);
3691 while (time_after(timeout, jiffies)) {
1c6bca6d 3692 u32 inta_hw = iwl_read32(trans, inta_addr);
b8a7547d
SM		 3693
3694 /* Error detected by uCode */
1c6bca6d 3695 if (inta_hw & sw_err_bit) {
b8a7547d 3696 /* Clear causes register */
1c6bca6d 3697 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
b8a7547d
SM		 3698 break;
3699 }
3700
3701 mdelay(1);
3702 }
e4eee943
SM		 3703
3704 /* enable interrupts only if there were already enabled before this
3705 * function to avoid a case were the driver enable interrupts before
3706 * proper configurations were made
3707 */
3708 if (interrupts_enabled)
3709 iwl_enable_interrupts(trans);
3710
b8a7547d
SM		 3711 iwl_trans_fw_error(trans);
3712}
Linux 6.x block layer and io_uring tree(s)