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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
553452e5 LK |
8 | * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. |
9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
afb84431 | 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
ea695b7c | 11 | * Copyright(c) 2018 - 2019 Intel Corporation |
c85eb619 EG |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of version 2 of the GNU General Public License as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
c85eb619 | 22 | * The full GNU General Public License is included in this distribution |
410dc5aa | 23 | * in the file called COPYING. |
c85eb619 EG |
24 | * |
25 | * Contact Information: | |
cb2f8277 | 26 | * Intel Linux Wireless <linuxwifi@intel.com> |
c85eb619 EG |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | * BSD LICENSE | |
30 | * | |
553452e5 LK |
31 | * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. |
32 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
afb84431 | 33 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
ea695b7c | 34 | * Copyright(c) 2018 - 2019 Intel Corporation |
c85eb619 EG |
35 | * All rights reserved. |
36 | * | |
37 | * Redistribution and use in source and binary forms, with or without | |
38 | * modification, are permitted provided that the following conditions | |
39 | * are met: | |
40 | * | |
41 | * * Redistributions of source code must retain the above copyright | |
42 | * notice, this list of conditions and the following disclaimer. | |
43 | * * Redistributions in binary form must reproduce the above copyright | |
44 | * notice, this list of conditions and the following disclaimer in | |
45 | * the documentation and/or other materials provided with the | |
46 | * distribution. | |
47 | * * Neither the name Intel Corporation nor the names of its | |
48 | * contributors may be used to endorse or promote products derived | |
49 | * from this software without specific prior written permission. | |
50 | * | |
51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
52 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
53 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
54 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
55 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
56 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
57 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
58 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
59 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
60 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
61 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
62 | * | |
63 | *****************************************************************************/ | |
a42a1844 EG |
64 | #include <linux/pci.h> |
65 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 66 | #include <linux/interrupt.h> |
87e5666c | 67 | #include <linux/debugfs.h> |
cf614297 | 68 | #include <linux/sched.h> |
6d8f6eeb EG |
69 | #include <linux/bitops.h> |
70 | #include <linux/gfp.h> | |
48eb7b34 | 71 | #include <linux/vmalloc.h> |
49564a80 | 72 | #include <linux/module.h> |
f7805b33 | 73 | #include <linux/wait.h> |
e6bb4c9c | 74 | |
82575102 | 75 | #include "iwl-drv.h" |
c85eb619 | 76 | #include "iwl-trans.h" |
522376d2 EG |
77 | #include "iwl-csr.h" |
78 | #include "iwl-prph.h" | |
cb6bb128 | 79 | #include "iwl-scd.h" |
7a10e3e4 | 80 | #include "iwl-agn-hw.h" |
d962f9b1 | 81 | #include "fw/error-dump.h" |
520f03ea | 82 | #include "fw/dbg.h" |
6468a01a | 83 | #include "internal.h" |
06d51e0d | 84 | #include "iwl-fh.h" |
0439bb62 | 85 | |
fe45773b AN |
86 | /* extended range in FW SRAM */ |
87 | #define IWL_FW_MEM_EXTENDED_START 0x40000 | |
88 | #define IWL_FW_MEM_EXTENDED_END 0x57FFF | |
89 | ||
4290eaad | 90 | void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) |
a6d24fad | 91 | { |
c4d3f2ee LC |
92 | #define PCI_DUMP_SIZE 352 |
93 | #define PCI_MEM_DUMP_SIZE 64 | |
94 | #define PCI_PARENT_DUMP_SIZE 524 | |
95 | #define PREFIX_LEN 32 | |
a6d24fad RJ |
96 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
97 | struct pci_dev *pdev = trans_pcie->pci_dev; | |
98 | u32 i, pos, alloc_size, *ptr, *buf; | |
99 | char *prefix; | |
100 | ||
101 | if (trans_pcie->pcie_dbg_dumped_once) | |
102 | return; | |
103 | ||
104 | /* Should be a multiple of 4 */ | |
105 | BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); | |
c4d3f2ee LC |
106 | BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); |
107 | BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); | |
108 | ||
a6d24fad | 109 | /* Alloc a max size buffer */ |
c4d3f2ee LC |
110 | alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; |
111 | alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); | |
112 | alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); | |
113 | alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); | |
114 | ||
a6d24fad RJ |
115 | buf = kmalloc(alloc_size, GFP_ATOMIC); |
116 | if (!buf) | |
117 | return; | |
118 | prefix = (char *)buf + alloc_size - PREFIX_LEN; | |
119 | ||
120 | IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); | |
121 | ||
122 | /* Print wifi device registers */ | |
123 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); | |
124 | IWL_ERR(trans, "iwlwifi device config registers:\n"); | |
125 | for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) | |
126 | if (pci_read_config_dword(pdev, i, ptr)) | |
127 | goto err_read; | |
128 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
129 | ||
130 | IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); | |
c4d3f2ee | 131 | for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) |
a6d24fad RJ |
132 | *ptr = iwl_read32(trans, i); |
133 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
134 | ||
135 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); | |
136 | if (pos) { | |
137 | IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); | |
138 | for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) | |
139 | if (pci_read_config_dword(pdev, pos + i, ptr)) | |
140 | goto err_read; | |
141 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, | |
142 | 32, 4, buf, i, 0); | |
143 | } | |
144 | ||
145 | /* Print parent device registers next */ | |
146 | if (!pdev->bus->self) | |
147 | goto out; | |
148 | ||
149 | pdev = pdev->bus->self; | |
150 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); | |
151 | ||
152 | IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", | |
153 | pci_name(pdev)); | |
c4d3f2ee | 154 | for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) |
a6d24fad RJ |
155 | if (pci_read_config_dword(pdev, i, ptr)) |
156 | goto err_read; | |
157 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
158 | ||
159 | /* Print root port AER registers */ | |
160 | pos = 0; | |
161 | pdev = pcie_find_root_port(pdev); | |
162 | if (pdev) | |
163 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); | |
164 | if (pos) { | |
165 | IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", | |
166 | pci_name(pdev)); | |
167 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); | |
168 | for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) | |
169 | if (pci_read_config_dword(pdev, pos + i, ptr)) | |
170 | goto err_read; | |
171 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, | |
172 | 4, buf, i, 0); | |
173 | } | |
f3402d6d | 174 | goto out; |
a6d24fad RJ |
175 | |
176 | err_read: | |
177 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
178 | IWL_ERR(trans, "Read failed at 0x%X\n", i); | |
179 | out: | |
180 | trans_pcie->pcie_dbg_dumped_once = 1; | |
181 | kfree(buf); | |
182 | } | |
183 | ||
870c2a11 GBA |
184 | static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) |
185 | { | |
186 | /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ | |
79b6c8fe LC |
187 | iwl_set_bit(trans, trans->cfg->trans.csr->addr_sw_reset, |
188 | BIT(trans->cfg->trans.csr->flag_sw_reset)); | |
870c2a11 GBA |
189 | usleep_range(5000, 6000); |
190 | } | |
191 | ||
c2d20201 EG |
192 | static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) |
193 | { | |
88964b2e | 194 | int i; |
c2d20201 | 195 | |
91c28b83 SM |
196 | for (i = 0; i < trans->dbg.num_blocks; i++) { |
197 | dma_free_coherent(trans->dev, trans->dbg.fw_mon[i].size, | |
198 | trans->dbg.fw_mon[i].block, | |
199 | trans->dbg.fw_mon[i].physical); | |
200 | trans->dbg.fw_mon[i].block = NULL; | |
201 | trans->dbg.fw_mon[i].physical = 0; | |
202 | trans->dbg.fw_mon[i].size = 0; | |
203 | trans->dbg.num_blocks--; | |
88964b2e | 204 | } |
c2d20201 EG |
205 | } |
206 | ||
88964b2e SS |
207 | static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, |
208 | u8 max_power, u8 min_power) | |
c2d20201 | 209 | { |
c5f97542 | 210 | void *cpu_addr = NULL; |
88964b2e | 211 | dma_addr_t phys = 0; |
96c285da | 212 | u32 size = 0; |
c2d20201 EG |
213 | u8 power; |
214 | ||
88964b2e | 215 | for (power = max_power; power >= min_power; power--) { |
c2d20201 | 216 | size = BIT(power); |
c5f97542 | 217 | cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, |
2d46f7af | 218 | GFP_KERNEL | __GFP_NOWARN); |
c5f97542 | 219 | if (!cpu_addr) |
c2d20201 EG |
220 | continue; |
221 | ||
c2d20201 | 222 | IWL_INFO(trans, |
c5f97542 SM |
223 | "Allocated 0x%08x bytes for firmware monitor.\n", |
224 | size); | |
c2d20201 EG |
225 | break; |
226 | } | |
227 | ||
c5f97542 | 228 | if (WARN_ON_ONCE(!cpu_addr)) |
c2d20201 EG |
229 | return; |
230 | ||
96c285da EG |
231 | if (power != max_power) |
232 | IWL_ERR(trans, | |
233 | "Sorry - debug buffer is only %luK while you requested %luK\n", | |
234 | (unsigned long)BIT(power - 10), | |
235 | (unsigned long)BIT(max_power - 10)); | |
236 | ||
91c28b83 SM |
237 | trans->dbg.fw_mon[trans->dbg.num_blocks].block = cpu_addr; |
238 | trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys; | |
239 | trans->dbg.fw_mon[trans->dbg.num_blocks].size = size; | |
240 | trans->dbg.num_blocks++; | |
88964b2e SS |
241 | } |
242 | ||
243 | void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) | |
244 | { | |
245 | if (!max_power) { | |
246 | /* default max_power is maximum */ | |
247 | max_power = 26; | |
248 | } else { | |
249 | max_power += 11; | |
250 | } | |
251 | ||
252 | if (WARN(max_power > 26, | |
253 | "External buffer size for monitor is too big %d, check the FW TLV\n", | |
254 | max_power)) | |
255 | return; | |
256 | ||
257 | /* | |
258 | * This function allocats the default fw monitor. | |
259 | * The optional additional ones will be allocated in runtime | |
260 | */ | |
91c28b83 | 261 | if (trans->dbg.num_blocks) |
88964b2e SS |
262 | return; |
263 | ||
264 | iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); | |
c2d20201 EG |
265 | } |
266 | ||
a812cba9 AB |
267 | static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) |
268 | { | |
269 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
270 | ((reg & 0x0000ffff) | (2 << 28))); | |
271 | return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); | |
272 | } | |
273 | ||
274 | static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) | |
275 | { | |
276 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); | |
277 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
278 | ((reg & 0x0000ffff) | (3 << 28))); | |
279 | } | |
280 | ||
ddaf5a5b | 281 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 282 | { |
66337b7c | 283 | if (trans->cfg->apmg_not_supported) |
95411d04 AA |
284 | return; |
285 | ||
ddaf5a5b JB |
286 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
287 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
288 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
289 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
290 | else | |
291 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
292 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
293 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
294 | } |
295 | ||
af634bee EG |
296 | /* PCI registers */ |
297 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 298 | |
eda50cde | 299 | void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 300 | { |
20d3b647 | 301 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 302 | u16 lctl; |
9180ac50 | 303 | u16 cap; |
af634bee | 304 | |
af634bee EG |
305 | /* |
306 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
307 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
308 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
309 | * costs negligible amount of power savings. | |
310 | * If not (unlikely), enable L0S, so there is at least some | |
311 | * power savings, even without L1. | |
312 | */ | |
7afe3705 | 313 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
9180ac50 | 314 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) |
af634bee | 315 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
9180ac50 | 316 | else |
af634bee | 317 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
438a0f0a | 318 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
9180ac50 EG |
319 | |
320 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); | |
321 | trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; | |
d74a61fc LC |
322 | IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", |
323 | (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", | |
324 | trans->ltr_enabled ? "En" : "Dis"); | |
af634bee EG |
325 | } |
326 | ||
a6c684ee EG |
327 | /* |
328 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 329 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
330 | * NOTE: This does not load uCode nor start the embedded processor |
331 | */ | |
7afe3705 | 332 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee | 333 | { |
52b6e168 EG |
334 | int ret; |
335 | ||
a6c684ee EG |
336 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); |
337 | ||
338 | /* | |
339 | * Use "set_bit" below rather than "write", to preserve any hardware | |
340 | * bits already set by default after reset. | |
341 | */ | |
342 | ||
343 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
79b6c8fe | 344 | if (trans->cfg->trans.device_family < IWL_DEVICE_FAMILY_8000) |
e4a9f8ce EH |
345 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, |
346 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
a6c684ee EG |
347 | |
348 | /* | |
349 | * Disable L0s without affecting L1; | |
350 | * don't wait for ICH L0s (ICH bug W/A) | |
351 | */ | |
352 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 353 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
354 | |
355 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
356 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
357 | ||
358 | /* | |
359 | * Enable HAP INTA (interrupt from management bus) to | |
360 | * wake device's PCI Express link L1a -> L0s | |
361 | */ | |
362 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 363 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 364 | |
7afe3705 | 365 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
366 | |
367 | /* Configure analog phase-lock-loop before activating to D0A */ | |
79b6c8fe | 368 | if (trans->cfg->trans.base_params->pll_cfg) |
77d76931 | 369 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); |
a6c684ee | 370 | |
79b6c8fe | 371 | ret = iwl_finish_nic_init(trans, &trans->cfg->trans); |
c96b5eec | 372 | if (ret) |
52b6e168 | 373 | return ret; |
a6c684ee | 374 | |
2d93aee1 EG |
375 | if (trans->cfg->host_interrupt_operation_mode) { |
376 | /* | |
377 | * This is a bit of an abuse - This is needed for 7260 / 3160 | |
378 | * only check host_interrupt_operation_mode even if this is | |
379 | * not related to host_interrupt_operation_mode. | |
380 | * | |
381 | * Enable the oscillator to count wake up time for L1 exit. This | |
382 | * consumes slightly more power (100uA) - but allows to be sure | |
383 | * that we wake up from L1 on time. | |
384 | * | |
385 | * This looks weird: read twice the same register, discard the | |
386 | * value, set a bit, and yet again, read that same register | |
387 | * just to discard the value. But that's the way the hardware | |
388 | * seems to like it. | |
389 | */ | |
390 | iwl_read_prph(trans, OSC_CLK); | |
391 | iwl_read_prph(trans, OSC_CLK); | |
392 | iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); | |
393 | iwl_read_prph(trans, OSC_CLK); | |
394 | iwl_read_prph(trans, OSC_CLK); | |
395 | } | |
396 | ||
a6c684ee EG |
397 | /* |
398 | * Enable DMA clock and wait for it to stabilize. | |
399 | * | |
3073d8c0 EH |
400 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" |
401 | * bits do not disable clocks. This preserves any hardware | |
402 | * bits already set by default in "CLK_CTRL_REG" after reset. | |
a6c684ee | 403 | */ |
95411d04 | 404 | if (!trans->cfg->apmg_not_supported) { |
3073d8c0 EH |
405 | iwl_write_prph(trans, APMG_CLK_EN_REG, |
406 | APMG_CLK_VAL_DMA_CLK_RQT); | |
407 | udelay(20); | |
408 | ||
409 | /* Disable L1-Active */ | |
410 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
411 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
412 | ||
413 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ | |
414 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, | |
415 | APMG_RTC_INT_STT_RFKILL); | |
416 | } | |
889b1696 | 417 | |
eb7ff77e | 418 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee | 419 | |
52b6e168 | 420 | return 0; |
a6c684ee EG |
421 | } |
422 | ||
a812cba9 AB |
423 | /* |
424 | * Enable LP XTAL to avoid HW bug where device may consume much power if | |
425 | * FW is not loaded after device reset. LP XTAL is disabled by default | |
426 | * after device HW reset. Do it only if XTAL is fed by internal source. | |
427 | * Configure device's "persistence" mode to avoid resetting XTAL again when | |
428 | * SHRD_HW_RST occurs in S3. | |
429 | */ | |
430 | static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) | |
431 | { | |
432 | int ret; | |
433 | u32 apmg_gp1_reg; | |
434 | u32 apmg_xtal_cfg_reg; | |
435 | u32 dl_cfg_reg; | |
436 | ||
437 | /* Force XTAL ON */ | |
438 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
439 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
440 | ||
870c2a11 | 441 | iwl_trans_pcie_sw_reset(trans); |
a812cba9 | 442 | |
79b6c8fe | 443 | ret = iwl_finish_nic_init(trans, &trans->cfg->trans); |
c96b5eec | 444 | if (WARN_ON(ret)) { |
a812cba9 AB |
445 | /* Release XTAL ON request */ |
446 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
447 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
448 | return; | |
449 | } | |
450 | ||
451 | /* | |
452 | * Clear "disable persistence" to avoid LP XTAL resetting when | |
453 | * SHRD_HW_RST is applied in S3. | |
454 | */ | |
455 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
456 | APMG_PCIDEV_STT_VAL_PERSIST_DIS); | |
457 | ||
458 | /* | |
459 | * Force APMG XTAL to be active to prevent its disabling by HW | |
460 | * caused by APMG idle state. | |
461 | */ | |
462 | apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, | |
463 | SHR_APMG_XTAL_CFG_REG); | |
464 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
465 | apmg_xtal_cfg_reg | | |
466 | SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
467 | ||
870c2a11 | 468 | iwl_trans_pcie_sw_reset(trans); |
a812cba9 AB |
469 | |
470 | /* Enable LP XTAL by indirect access through CSR */ | |
471 | apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); | |
472 | iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | | |
473 | SHR_APMG_GP1_WF_XTAL_LP_EN | | |
474 | SHR_APMG_GP1_CHICKEN_BIT_SELECT); | |
475 | ||
476 | /* Clear delay line clock power up */ | |
477 | dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); | |
478 | iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & | |
479 | ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); | |
480 | ||
481 | /* | |
482 | * Enable persistence mode to avoid LP XTAL resetting when | |
483 | * SHRD_HW_RST is applied in S3. | |
484 | */ | |
485 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
486 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
487 | ||
488 | /* | |
489 | * Clear "initialization complete" bit to move adapter from | |
490 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
491 | */ | |
492 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
79b6c8fe | 493 | BIT(trans->cfg->trans.csr->flag_init_done)); |
a812cba9 AB |
494 | |
495 | /* Activates XTAL resources monitor */ | |
496 | __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, | |
497 | CSR_MONITOR_XTAL_RESOURCES); | |
498 | ||
499 | /* Release XTAL ON request */ | |
500 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
501 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
502 | udelay(10); | |
503 | ||
504 | /* Release APMG XTAL */ | |
505 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
506 | apmg_xtal_cfg_reg & | |
507 | ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
508 | } | |
509 | ||
e8c8935e | 510 | void iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 | 511 | { |
e8c8935e | 512 | int ret; |
cc56feb2 EG |
513 | |
514 | /* stop device's busmaster DMA activity */ | |
79b6c8fe LC |
515 | iwl_set_bit(trans, trans->cfg->trans.csr->addr_sw_reset, |
516 | BIT(trans->cfg->trans.csr->flag_stop_master)); | |
cc56feb2 | 517 | |
79b6c8fe LC |
518 | ret = iwl_poll_bit(trans, trans->cfg->trans.csr->addr_sw_reset, |
519 | BIT(trans->cfg->trans.csr->flag_master_dis), | |
520 | BIT(trans->cfg->trans.csr->flag_master_dis), 100); | |
7f2ac8fb | 521 | if (ret < 0) |
cc56feb2 EG |
522 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); |
523 | ||
524 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
cc56feb2 EG |
525 | } |
526 | ||
b7aaeae4 | 527 | static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) |
cc56feb2 EG |
528 | { |
529 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
530 | ||
b7aaeae4 EG |
531 | if (op_mode_leave) { |
532 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
533 | iwl_pcie_apm_init(trans); | |
534 | ||
535 | /* inform ME that we are leaving */ | |
79b6c8fe | 536 | if (trans->cfg->trans.device_family == IWL_DEVICE_FAMILY_7000) |
b7aaeae4 EG |
537 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, |
538 | APMG_PCIDEV_STT_VAL_WAKE_ME); | |
79b6c8fe LC |
539 | else if (trans->cfg->trans.device_family >= |
540 | IWL_DEVICE_FAMILY_8000) { | |
c9fdec9f EG |
541 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
542 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
b7aaeae4 EG |
543 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
544 | CSR_HW_IF_CONFIG_REG_PREPARE | | |
545 | CSR_HW_IF_CONFIG_REG_ENABLE_PME); | |
c9fdec9f EG |
546 | mdelay(1); |
547 | iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, | |
548 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
549 | } | |
b7aaeae4 EG |
550 | mdelay(5); |
551 | } | |
552 | ||
eb7ff77e | 553 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
554 | |
555 | /* Stop device's DMA activity */ | |
7afe3705 | 556 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 | 557 | |
a812cba9 AB |
558 | if (trans->cfg->lp_xtal_workaround) { |
559 | iwl_pcie_apm_lp_xtal_enable(trans); | |
560 | return; | |
561 | } | |
562 | ||
870c2a11 | 563 | iwl_trans_pcie_sw_reset(trans); |
cc56feb2 EG |
564 | |
565 | /* | |
566 | * Clear "initialization complete" bit to move adapter from | |
567 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
568 | */ | |
569 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
79b6c8fe | 570 | BIT(trans->cfg->trans.csr->flag_init_done)); |
cc56feb2 EG |
571 | } |
572 | ||
7afe3705 | 573 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 574 | { |
7b11488f | 575 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
52b6e168 | 576 | int ret; |
392f8b78 EG |
577 | |
578 | /* nic_init */ | |
7b70bd63 | 579 | spin_lock(&trans_pcie->irq_lock); |
52b6e168 | 580 | ret = iwl_pcie_apm_init(trans); |
7b70bd63 | 581 | spin_unlock(&trans_pcie->irq_lock); |
392f8b78 | 582 | |
52b6e168 EG |
583 | if (ret) |
584 | return ret; | |
585 | ||
95411d04 | 586 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 587 | |
ecdb975c | 588 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
589 | |
590 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 591 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
592 | |
593 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 594 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
595 | return -ENOMEM; |
596 | ||
79b6c8fe | 597 | if (trans->cfg->trans.base_params->shadow_reg_enable) { |
392f8b78 | 598 | /* enable shadow regs in HW */ |
20d3b647 | 599 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 600 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
601 | } |
602 | ||
392f8b78 EG |
603 | return 0; |
604 | } | |
605 | ||
606 | #define HW_READY_TIMEOUT (50) | |
607 | ||
608 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 609 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
610 | { |
611 | int ret; | |
612 | ||
1042db2a | 613 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 614 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
615 | |
616 | /* See if we got it */ | |
1042db2a | 617 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
618 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
619 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
620 | HW_READY_TIMEOUT); | |
392f8b78 | 621 | |
6a08f514 EG |
622 | if (ret >= 0) |
623 | iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); | |
624 | ||
6d8f6eeb | 625 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
626 | return ret; |
627 | } | |
628 | ||
629 | /* Note: returns standard 0/-ERROR code */ | |
eda50cde | 630 | int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
631 | { |
632 | int ret; | |
289e5501 | 633 | int t = 0; |
501fd989 | 634 | int iter; |
392f8b78 | 635 | |
6d8f6eeb | 636 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 637 | |
7afe3705 | 638 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 639 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
640 | if (ret >= 0) |
641 | return 0; | |
642 | ||
c9fdec9f EG |
643 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
644 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
192185d6 | 645 | usleep_range(1000, 2000); |
c9fdec9f | 646 | |
501fd989 EG |
647 | for (iter = 0; iter < 10; iter++) { |
648 | /* If HW is not ready, prepare the conditions to check again */ | |
649 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
650 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
651 | ||
652 | do { | |
653 | ret = iwl_pcie_set_hw_ready(trans); | |
03a19cbb EG |
654 | if (ret >= 0) |
655 | return 0; | |
392f8b78 | 656 | |
501fd989 EG |
657 | usleep_range(200, 1000); |
658 | t += 200; | |
659 | } while (t < 150000); | |
660 | msleep(25); | |
661 | } | |
392f8b78 | 662 | |
7f2ac8fb | 663 | IWL_ERR(trans, "Couldn't prepare the card\n"); |
392f8b78 | 664 | |
392f8b78 EG |
665 | return ret; |
666 | } | |
667 | ||
cf614297 EG |
668 | /* |
669 | * ucode | |
670 | */ | |
564cdce7 SS |
671 | static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, |
672 | u32 dst_addr, dma_addr_t phy_addr, | |
673 | u32 byte_cnt) | |
cf614297 | 674 | { |
bac842da EG |
675 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
676 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
677 | ||
678 | iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), | |
679 | dst_addr); | |
680 | ||
681 | iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
682 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
683 | ||
684 | iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), | |
685 | (iwl_get_dma_hi_addr(phy_addr) | |
686 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
687 | ||
688 | iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
689 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | | |
690 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | | |
691 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
692 | ||
693 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
694 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
695 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
696 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
564cdce7 SS |
697 | } |
698 | ||
564cdce7 SS |
699 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, |
700 | u32 dst_addr, dma_addr_t phy_addr, | |
701 | u32 byte_cnt) | |
702 | { | |
703 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
704 | unsigned long flags; | |
705 | int ret; | |
706 | ||
707 | trans_pcie->ucode_write_complete = false; | |
708 | ||
709 | if (!iwl_trans_grab_nic_access(trans, &flags)) | |
710 | return -EIO; | |
711 | ||
eda50cde SS |
712 | iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, |
713 | byte_cnt); | |
bac842da | 714 | iwl_trans_release_nic_access(trans, &flags); |
cf614297 | 715 | |
13df1aab JB |
716 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
717 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 718 | if (!ret) { |
83f84d7b | 719 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
fb12777a | 720 | iwl_trans_pcie_dump_regs(trans); |
cf614297 EG |
721 | return -ETIMEDOUT; |
722 | } | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
7afe3705 | 727 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 728 | const struct fw_desc *section) |
cf614297 | 729 | { |
83f84d7b JB |
730 | u8 *v_addr; |
731 | dma_addr_t p_addr; | |
baa21e83 | 732 | u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); |
cf614297 EG |
733 | int ret = 0; |
734 | ||
83f84d7b JB |
735 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
736 | section_num); | |
737 | ||
c571573a EG |
738 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
739 | GFP_KERNEL | __GFP_NOWARN); | |
740 | if (!v_addr) { | |
741 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
742 | chunk_sz = PAGE_SIZE; | |
743 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
744 | &p_addr, GFP_KERNEL); | |
745 | if (!v_addr) | |
746 | return -ENOMEM; | |
747 | } | |
83f84d7b | 748 | |
c571573a | 749 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
fe45773b AN |
750 | u32 copy_size, dst_addr; |
751 | bool extended_addr = false; | |
83f84d7b | 752 | |
c571573a | 753 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
fe45773b AN |
754 | dst_addr = section->offset + offset; |
755 | ||
756 | if (dst_addr >= IWL_FW_MEM_EXTENDED_START && | |
757 | dst_addr <= IWL_FW_MEM_EXTENDED_END) | |
758 | extended_addr = true; | |
759 | ||
760 | if (extended_addr) | |
761 | iwl_set_bits_prph(trans, LMPM_CHICK, | |
762 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
cf614297 | 763 | |
83f84d7b | 764 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
fe45773b AN |
765 | ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, |
766 | copy_size); | |
767 | ||
768 | if (extended_addr) | |
769 | iwl_clear_bits_prph(trans, LMPM_CHICK, | |
770 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
771 | ||
83f84d7b JB |
772 | if (ret) { |
773 | IWL_ERR(trans, | |
774 | "Could not load the [%d] uCode section\n", | |
775 | section_num); | |
776 | break; | |
6dfa8d01 | 777 | } |
83f84d7b JB |
778 | } |
779 | ||
c571573a | 780 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
781 | return ret; |
782 | } | |
783 | ||
5dd9c68a EG |
784 | static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, |
785 | const struct fw_img *image, | |
786 | int cpu, | |
787 | int *first_ucode_section) | |
e2d6f4e7 EH |
788 | { |
789 | int shift_param; | |
dcab8ecd EH |
790 | int i, ret = 0, sec_num = 0x1; |
791 | u32 val, last_read_idx = 0; | |
e2d6f4e7 EH |
792 | |
793 | if (cpu == 1) { | |
794 | shift_param = 0; | |
034846cf | 795 | *first_ucode_section = 0; |
e2d6f4e7 EH |
796 | } else { |
797 | shift_param = 16; | |
034846cf | 798 | (*first_ucode_section)++; |
e2d6f4e7 EH |
799 | } |
800 | ||
eef187a7 | 801 | for (i = *first_ucode_section; i < image->num_sec; i++) { |
034846cf EH |
802 | last_read_idx = i; |
803 | ||
a6c4fb44 MG |
804 | /* |
805 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between | |
806 | * CPU1 to CPU2. | |
807 | * PAGING_SEPARATOR_SECTION delimiter - separate between | |
808 | * CPU2 non paged to CPU2 paging sec. | |
809 | */ | |
034846cf | 810 | if (!image->sec[i].data || |
a6c4fb44 MG |
811 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
812 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { | |
034846cf EH |
813 | IWL_DEBUG_FW(trans, |
814 | "Break since Data not valid or Empty section, sec = %d\n", | |
815 | i); | |
189fa2fa | 816 | break; |
034846cf EH |
817 | } |
818 | ||
189fa2fa EH |
819 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
820 | if (ret) | |
821 | return ret; | |
dcab8ecd | 822 | |
d6a2c5c7 | 823 | /* Notify ucode of loaded section number and status */ |
eda50cde SS |
824 | val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); |
825 | val = val | (sec_num << shift_param); | |
826 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); | |
827 | ||
dcab8ecd | 828 | sec_num = (sec_num << 1) | 0x1; |
e2d6f4e7 EH |
829 | } |
830 | ||
034846cf EH |
831 | *first_ucode_section = last_read_idx; |
832 | ||
2aabdbdc EG |
833 | iwl_enable_interrupts(trans); |
834 | ||
79b6c8fe | 835 | if (trans->cfg->trans.use_tfh) { |
d6a2c5c7 SS |
836 | if (cpu == 1) |
837 | iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, | |
838 | 0xFFFF); | |
839 | else | |
840 | iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, | |
841 | 0xFFFFFFFF); | |
842 | } else { | |
843 | if (cpu == 1) | |
844 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, | |
845 | 0xFFFF); | |
846 | else | |
847 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, | |
848 | 0xFFFFFFFF); | |
849 | } | |
afb88917 | 850 | |
189fa2fa EH |
851 | return 0; |
852 | } | |
e2d6f4e7 | 853 | |
189fa2fa EH |
854 | static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, |
855 | const struct fw_img *image, | |
034846cf EH |
856 | int cpu, |
857 | int *first_ucode_section) | |
189fa2fa | 858 | { |
189fa2fa | 859 | int i, ret = 0; |
034846cf | 860 | u32 last_read_idx = 0; |
189fa2fa | 861 | |
3ce4a038 | 862 | if (cpu == 1) |
034846cf | 863 | *first_ucode_section = 0; |
3ce4a038 | 864 | else |
034846cf | 865 | (*first_ucode_section)++; |
189fa2fa | 866 | |
eef187a7 | 867 | for (i = *first_ucode_section; i < image->num_sec; i++) { |
034846cf EH |
868 | last_read_idx = i; |
869 | ||
a6c4fb44 MG |
870 | /* |
871 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between | |
872 | * CPU1 to CPU2. | |
873 | * PAGING_SEPARATOR_SECTION delimiter - separate between | |
874 | * CPU2 non paged to CPU2 paging sec. | |
875 | */ | |
034846cf | 876 | if (!image->sec[i].data || |
a6c4fb44 MG |
877 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
878 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { | |
034846cf EH |
879 | IWL_DEBUG_FW(trans, |
880 | "Break since Data not valid or Empty section, sec = %d\n", | |
881 | i); | |
189fa2fa | 882 | break; |
034846cf EH |
883 | } |
884 | ||
189fa2fa EH |
885 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
886 | if (ret) | |
887 | return ret; | |
e2d6f4e7 EH |
888 | } |
889 | ||
034846cf EH |
890 | *first_ucode_section = last_read_idx; |
891 | ||
e2d6f4e7 EH |
892 | return 0; |
893 | } | |
894 | ||
c9be849d | 895 | void iwl_pcie_apply_destination(struct iwl_trans *trans) |
09e350f7 | 896 | { |
91c28b83 | 897 | const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; |
09e350f7 LK |
898 | int i; |
899 | ||
a1af4c48 | 900 | if (iwl_trans_dbg_ini_valid(trans)) { |
91c28b83 | 901 | if (!trans->dbg.num_blocks) |
7a14c23d SS |
902 | return; |
903 | ||
53032e6e | 904 | IWL_DEBUG_FW(trans, |
a64d4e8d | 905 | "WRT: Applying DRAM buffer[0] destination\n"); |
ea695b7c | 906 | iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, |
91c28b83 | 907 | trans->dbg.fw_mon[0].physical >> |
ea695b7c ST |
908 | MON_BUFF_SHIFT_VER2); |
909 | iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, | |
91c28b83 SM |
910 | (trans->dbg.fw_mon[0].physical + |
911 | trans->dbg.fw_mon[0].size - 256) >> | |
ea695b7c | 912 | MON_BUFF_SHIFT_VER2); |
7a14c23d SS |
913 | return; |
914 | } | |
915 | ||
09e350f7 LK |
916 | IWL_INFO(trans, "Applying debug destination %s\n", |
917 | get_fw_dbg_mode_string(dest->monitor_mode)); | |
918 | ||
919 | if (dest->monitor_mode == EXTERNAL_MODE) | |
96c285da | 920 | iwl_pcie_alloc_fw_monitor(trans, dest->size_power); |
09e350f7 LK |
921 | else |
922 | IWL_WARN(trans, "PCI should have external buffer debug\n"); | |
923 | ||
91c28b83 | 924 | for (i = 0; i < trans->dbg.n_dest_reg; i++) { |
09e350f7 LK |
925 | u32 addr = le32_to_cpu(dest->reg_ops[i].addr); |
926 | u32 val = le32_to_cpu(dest->reg_ops[i].val); | |
927 | ||
928 | switch (dest->reg_ops[i].op) { | |
929 | case CSR_ASSIGN: | |
930 | iwl_write32(trans, addr, val); | |
931 | break; | |
932 | case CSR_SETBIT: | |
933 | iwl_set_bit(trans, addr, BIT(val)); | |
934 | break; | |
935 | case CSR_CLEARBIT: | |
936 | iwl_clear_bit(trans, addr, BIT(val)); | |
937 | break; | |
938 | case PRPH_ASSIGN: | |
939 | iwl_write_prph(trans, addr, val); | |
940 | break; | |
941 | case PRPH_SETBIT: | |
942 | iwl_set_bits_prph(trans, addr, BIT(val)); | |
943 | break; | |
944 | case PRPH_CLEARBIT: | |
945 | iwl_clear_bits_prph(trans, addr, BIT(val)); | |
946 | break; | |
869f3b15 HD |
947 | case PRPH_BLOCKBIT: |
948 | if (iwl_read_prph(trans, addr) & BIT(val)) { | |
949 | IWL_ERR(trans, | |
950 | "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", | |
951 | val, addr); | |
952 | goto monitor; | |
953 | } | |
954 | break; | |
09e350f7 LK |
955 | default: |
956 | IWL_ERR(trans, "FW debug - unknown OP %d\n", | |
957 | dest->reg_ops[i].op); | |
958 | break; | |
959 | } | |
960 | } | |
961 | ||
869f3b15 | 962 | monitor: |
91c28b83 | 963 | if (dest->monitor_mode == EXTERNAL_MODE && trans->dbg.fw_mon[0].size) { |
09e350f7 | 964 | iwl_write_prph(trans, le32_to_cpu(dest->base_reg), |
91c28b83 SM |
965 | trans->dbg.fw_mon[0].physical >> |
966 | dest->base_shift); | |
79b6c8fe | 967 | if (trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_8000) |
62d7476d | 968 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), |
91c28b83 SM |
969 | (trans->dbg.fw_mon[0].physical + |
970 | trans->dbg.fw_mon[0].size - 256) >> | |
62d7476d EG |
971 | dest->end_shift); |
972 | else | |
973 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), | |
91c28b83 SM |
974 | (trans->dbg.fw_mon[0].physical + |
975 | trans->dbg.fw_mon[0].size) >> | |
62d7476d | 976 | dest->end_shift); |
09e350f7 LK |
977 | } |
978 | } | |
979 | ||
7afe3705 | 980 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 981 | const struct fw_img *image) |
cf614297 | 982 | { |
189fa2fa | 983 | int ret = 0; |
034846cf | 984 | int first_ucode_section; |
cf614297 | 985 | |
dcab8ecd | 986 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
e2d6f4e7 EH |
987 | image->is_dual_cpus ? "Dual" : "Single"); |
988 | ||
dcab8ecd EH |
989 | /* load to FW the binary non secured sections of CPU1 */ |
990 | ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); | |
991 | if (ret) | |
992 | return ret; | |
e2d6f4e7 EH |
993 | |
994 | if (image->is_dual_cpus) { | |
189fa2fa EH |
995 | /* set CPU2 header address */ |
996 | iwl_write_prph(trans, | |
997 | LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, | |
998 | LMPM_SECURE_CPU2_HDR_MEM_SPACE); | |
e2d6f4e7 | 999 | |
189fa2fa | 1000 | /* load to FW the binary sections of CPU2 */ |
dcab8ecd EH |
1001 | ret = iwl_pcie_load_cpu_sections(trans, image, 2, |
1002 | &first_ucode_section); | |
189fa2fa EH |
1003 | if (ret) |
1004 | return ret; | |
e2d6f4e7 | 1005 | } |
cf614297 | 1006 | |
c2d20201 EG |
1007 | /* supported for 7000 only for the moment */ |
1008 | if (iwlwifi_mod_params.fw_monitor && | |
79b6c8fe | 1009 | trans->cfg->trans.device_family == IWL_DEVICE_FAMILY_7000) { |
96c285da | 1010 | iwl_pcie_alloc_fw_monitor(trans, 0); |
c2d20201 | 1011 | |
91c28b83 | 1012 | if (trans->dbg.fw_mon[0].size) { |
c2d20201 | 1013 | iwl_write_prph(trans, MON_BUFF_BASE_ADDR, |
91c28b83 | 1014 | trans->dbg.fw_mon[0].physical >> 4); |
c2d20201 | 1015 | iwl_write_prph(trans, MON_BUFF_END_ADDR, |
91c28b83 SM |
1016 | (trans->dbg.fw_mon[0].physical + |
1017 | trans->dbg.fw_mon[0].size) >> 4); | |
c2d20201 | 1018 | } |
7a14c23d | 1019 | } else if (iwl_pcie_dbg_on(trans)) { |
09e350f7 | 1020 | iwl_pcie_apply_destination(trans); |
c2d20201 EG |
1021 | } |
1022 | ||
2aabdbdc EG |
1023 | iwl_enable_interrupts(trans); |
1024 | ||
e12ba844 | 1025 | /* release CPU reset */ |
5dd9c68a | 1026 | iwl_write32(trans, CSR_RESET, 0); |
e12ba844 | 1027 | |
dcab8ecd EH |
1028 | return 0; |
1029 | } | |
189fa2fa | 1030 | |
5dd9c68a EG |
1031 | static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, |
1032 | const struct fw_img *image) | |
dcab8ecd EH |
1033 | { |
1034 | int ret = 0; | |
1035 | int first_ucode_section; | |
dcab8ecd EH |
1036 | |
1037 | IWL_DEBUG_FW(trans, "working with %s CPU\n", | |
1038 | image->is_dual_cpus ? "Dual" : "Single"); | |
1039 | ||
7a14c23d | 1040 | if (iwl_pcie_dbg_on(trans)) |
a2227ce2 EG |
1041 | iwl_pcie_apply_destination(trans); |
1042 | ||
82ea7966 SS |
1043 | IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", |
1044 | iwl_read_prph(trans, WFPM_GP2)); | |
1045 | ||
1046 | /* | |
1047 | * Set default value. On resume reading the values that were | |
1048 | * zeored can provide debug data on the resume flow. | |
1049 | * This is for debugging only and has no functional impact. | |
1050 | */ | |
1051 | iwl_write_prph(trans, WFPM_GP2, 0x01010101); | |
1052 | ||
dcab8ecd EH |
1053 | /* configure the ucode to be ready to get the secured image */ |
1054 | /* release CPU reset */ | |
1055 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); | |
1056 | ||
1057 | /* load to FW the binary Secured sections of CPU1 */ | |
5dd9c68a EG |
1058 | ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, |
1059 | &first_ucode_section); | |
dcab8ecd EH |
1060 | if (ret) |
1061 | return ret; | |
1062 | ||
1063 | /* load to FW the binary sections of CPU2 */ | |
47dbab26 EG |
1064 | return iwl_pcie_load_cpu_sections_8000(trans, image, 2, |
1065 | &first_ucode_section); | |
cf614297 EG |
1066 | } |
1067 | ||
9ad8fd0b | 1068 | bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) |
727c02df | 1069 | { |
326477e4 | 1070 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
727c02df | 1071 | bool hw_rfkill = iwl_is_rfkill_set(trans); |
326477e4 JB |
1072 | bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); |
1073 | bool report; | |
727c02df | 1074 | |
326477e4 JB |
1075 | if (hw_rfkill) { |
1076 | set_bit(STATUS_RFKILL_HW, &trans->status); | |
1077 | set_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1078 | } else { | |
1079 | clear_bit(STATUS_RFKILL_HW, &trans->status); | |
1080 | if (trans_pcie->opmode_down) | |
1081 | clear_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1082 | } | |
1083 | ||
1084 | report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
727c02df | 1085 | |
326477e4 JB |
1086 | if (prev != report) |
1087 | iwl_trans_pcie_rf_kill(trans, report); | |
727c02df SS |
1088 | |
1089 | return hw_rfkill; | |
1090 | } | |
1091 | ||
7ca00409 HD |
1092 | struct iwl_causes_list { |
1093 | u32 cause_num; | |
1094 | u32 mask_reg; | |
1095 | u8 addr; | |
1096 | }; | |
1097 | ||
1098 | static struct iwl_causes_list causes_list[] = { | |
1099 | {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, | |
1100 | {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, | |
1101 | {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, | |
1102 | {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, | |
1103 | {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, | |
1104 | {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, | |
ff911dca | 1105 | {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, |
7ca00409 HD |
1106 | {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, |
1107 | {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, | |
1108 | {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, | |
1109 | {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, | |
1110 | {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, | |
1111 | {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, | |
1112 | {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, | |
1113 | {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, | |
1114 | }; | |
1115 | ||
9b58419e GBA |
1116 | static struct iwl_causes_list causes_list_v2[] = { |
1117 | {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, | |
1118 | {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, | |
1119 | {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, | |
1120 | {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, | |
1121 | {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, | |
1122 | {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, | |
1123 | {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, | |
1124 | {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, | |
1125 | {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, | |
1126 | {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, | |
1127 | {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, | |
1128 | {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, | |
1129 | {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, | |
1130 | {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, | |
1131 | }; | |
1132 | ||
7ca00409 HD |
1133 | static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) |
1134 | { | |
1135 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1136 | int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; | |
9b58419e | 1137 | int i, arr_size = |
79b6c8fe | 1138 | (trans->cfg->trans.device_family != IWL_DEVICE_FAMILY_22560) ? |
9b58419e | 1139 | ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); |
7ca00409 HD |
1140 | |
1141 | /* | |
1142 | * Access all non RX causes and map them to the default irq. | |
1143 | * In case we are missing at least one interrupt vector, | |
1144 | * the first interrupt vector will serve non-RX and FBQ causes. | |
1145 | */ | |
9b58419e GBA |
1146 | for (i = 0; i < arr_size; i++) { |
1147 | struct iwl_causes_list *causes = | |
79b6c8fe LC |
1148 | (trans->cfg->trans.device_family != |
1149 | IWL_DEVICE_FAMILY_22560) ? | |
9b58419e GBA |
1150 | causes_list : causes_list_v2; |
1151 | ||
1152 | iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); | |
1153 | iwl_clear_bit(trans, causes[i].mask_reg, | |
1154 | causes[i].cause_num); | |
7ca00409 HD |
1155 | } |
1156 | } | |
1157 | ||
1158 | static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) | |
1159 | { | |
1160 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1161 | u32 offset = | |
1162 | trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; | |
1163 | u32 val, idx; | |
1164 | ||
1165 | /* | |
1166 | * The first RX queue - fallback queue, which is designated for | |
1167 | * management frame, command responses etc, is always mapped to the | |
1168 | * first interrupt vector. The other RX queues are mapped to | |
1169 | * the other (N - 2) interrupt vectors. | |
1170 | */ | |
1171 | val = BIT(MSIX_FH_INT_CAUSES_Q(0)); | |
1172 | for (idx = 1; idx < trans->num_rx_queues; idx++) { | |
1173 | iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), | |
1174 | MSIX_FH_INT_CAUSES_Q(idx - offset)); | |
1175 | val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); | |
1176 | } | |
1177 | iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); | |
1178 | ||
1179 | val = MSIX_FH_INT_CAUSES_Q(0); | |
1180 | if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) | |
1181 | val |= MSIX_NON_AUTO_CLEAR_CAUSE; | |
1182 | iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); | |
1183 | ||
1184 | if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) | |
1185 | iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); | |
1186 | } | |
1187 | ||
77c09bc8 | 1188 | void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) |
7ca00409 HD |
1189 | { |
1190 | struct iwl_trans *trans = trans_pcie->trans; | |
1191 | ||
1192 | if (!trans_pcie->msix_enabled) { | |
79b6c8fe | 1193 | if (trans->cfg->trans.mq_rx_supported && |
d7270d61 | 1194 | test_bit(STATUS_DEVICE_ENABLED, &trans->status)) |
ea695b7c ST |
1195 | iwl_write_umac_prph(trans, UREG_CHICK, |
1196 | UREG_CHICK_MSI_ENABLE); | |
7ca00409 HD |
1197 | return; |
1198 | } | |
d7270d61 HD |
1199 | /* |
1200 | * The IVAR table needs to be configured again after reset, | |
1201 | * but if the device is disabled, we can't write to | |
1202 | * prph. | |
1203 | */ | |
1204 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
ea695b7c | 1205 | iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); |
7ca00409 HD |
1206 | |
1207 | /* | |
1208 | * Each cause from the causes list above and the RX causes is | |
1209 | * represented as a byte in the IVAR table. The first nibble | |
1210 | * represents the bound interrupt vector of the cause, the second | |
1211 | * represents no auto clear for this cause. This will be set if its | |
1212 | * interrupt vector is bound to serve other causes. | |
1213 | */ | |
1214 | iwl_pcie_map_rx_causes(trans); | |
1215 | ||
1216 | iwl_pcie_map_non_rx_causes(trans); | |
83730058 HD |
1217 | } |
1218 | ||
1219 | static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) | |
1220 | { | |
1221 | struct iwl_trans *trans = trans_pcie->trans; | |
1222 | ||
1223 | iwl_pcie_conf_msix_hw(trans_pcie); | |
7ca00409 | 1224 | |
83730058 HD |
1225 | if (!trans_pcie->msix_enabled) |
1226 | return; | |
1227 | ||
1228 | trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); | |
7ca00409 | 1229 | trans_pcie->fh_mask = trans_pcie->fh_init_mask; |
83730058 | 1230 | trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); |
7ca00409 HD |
1231 | trans_pcie->hw_mask = trans_pcie->hw_init_mask; |
1232 | } | |
1233 | ||
bab3cb92 | 1234 | static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 1235 | { |
43e58856 | 1236 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3dc3374f | 1237 | |
fa9f3281 EG |
1238 | lockdep_assert_held(&trans_pcie->mutex); |
1239 | ||
1240 | if (trans_pcie->is_down) | |
1241 | return; | |
1242 | ||
1243 | trans_pcie->is_down = true; | |
1244 | ||
43e58856 | 1245 | /* tell the device to stop sending interrupts */ |
ae2c30bf | 1246 | iwl_disable_interrupts(trans); |
ae2c30bf | 1247 | |
ab6cf8e8 | 1248 | /* device going down, Stop using ICT table */ |
990aa6d7 | 1249 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
1250 | |
1251 | /* | |
1252 | * If a HW restart happens during firmware loading, | |
1253 | * then the firmware loading might call this function | |
1254 | * and later it might be called again due to the | |
1255 | * restart. So don't process again if the device is | |
1256 | * already dead. | |
1257 | */ | |
31b8b343 | 1258 | if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
a6bd005f EG |
1259 | IWL_DEBUG_INFO(trans, |
1260 | "DEVICE_ENABLED bit was set and is now cleared\n"); | |
f02831be | 1261 | iwl_pcie_tx_stop(trans); |
9805c446 | 1262 | iwl_pcie_rx_stop(trans); |
6379103e | 1263 | |
ab6cf8e8 | 1264 | /* Power-down device's busmaster DMA clocks */ |
95411d04 | 1265 | if (!trans->cfg->apmg_not_supported) { |
1aa02b5a AA |
1266 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
1267 | APMG_CLK_VAL_DMA_CLK_RQT); | |
1268 | udelay(5); | |
1269 | } | |
ab6cf8e8 EG |
1270 | } |
1271 | ||
1272 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1273 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
79b6c8fe | 1274 | BIT(trans->cfg->trans.csr->flag_mac_access_req)); |
ab6cf8e8 EG |
1275 | |
1276 | /* Stop the device, and put it in low power state */ | |
b7aaeae4 | 1277 | iwl_pcie_apm_stop(trans, false); |
43e58856 | 1278 | |
870c2a11 | 1279 | iwl_trans_pcie_sw_reset(trans); |
03d6c3b0 | 1280 | |
f4a1f04a GBA |
1281 | /* |
1282 | * Upon stop, the IVAR table gets erased, so msi-x won't | |
1283 | * work. This causes a bug in RF-KILL flows, since the interrupt | |
1284 | * that enables radio won't fire on the correct irq, and the | |
1285 | * driver won't be able to handle the interrupt. | |
1286 | * Configure the IVAR table again after reset. | |
1287 | */ | |
1288 | iwl_pcie_conf_msix_hw(trans_pcie); | |
1289 | ||
03d6c3b0 EG |
1290 | /* |
1291 | * Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1292 | * This is a bug in certain verions of the hardware. | |
1293 | * Certain devices also keep sending HW RF kill interrupt all | |
1294 | * the time, unless the interrupt is ACKed even if the interrupt | |
1295 | * should be masked. Re-ACK all the interrupts here. | |
43e58856 | 1296 | */ |
43e58856 | 1297 | iwl_disable_interrupts(trans); |
43e58856 | 1298 | |
74fda971 | 1299 | /* clear all status bits */ |
eb7ff77e AN |
1300 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
1301 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
eb7ff77e | 1302 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
a4082843 AN |
1303 | |
1304 | /* | |
1305 | * Even if we stop the HW, we still want the RF kill | |
1306 | * interrupt | |
1307 | */ | |
1308 | iwl_enable_rfkill_int(trans); | |
1309 | ||
a6bd005f | 1310 | /* re-take ownership to prevent other users from stealing the device */ |
655e5cf0 | 1311 | iwl_pcie_prepare_card_hw(trans); |
14cfca71 JB |
1312 | } |
1313 | ||
eda50cde | 1314 | void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) |
2e5d4a8f HD |
1315 | { |
1316 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1317 | ||
1318 | if (trans_pcie->msix_enabled) { | |
1319 | int i; | |
1320 | ||
496d83ca | 1321 | for (i = 0; i < trans_pcie->alloc_vecs; i++) |
2e5d4a8f HD |
1322 | synchronize_irq(trans_pcie->msix_entries[i].vector); |
1323 | } else { | |
1324 | synchronize_irq(trans_pcie->pci_dev->irq); | |
1325 | } | |
1326 | } | |
1327 | ||
a6bd005f EG |
1328 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
1329 | const struct fw_img *fw, bool run_in_rfkill) | |
1330 | { | |
1331 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1332 | bool hw_rfkill; | |
1333 | int ret; | |
1334 | ||
1335 | /* This may fail if AMT took ownership of the device */ | |
1336 | if (iwl_pcie_prepare_card_hw(trans)) { | |
1337 | IWL_WARN(trans, "Exit HW not ready\n"); | |
1338 | ret = -EIO; | |
1339 | goto out; | |
1340 | } | |
1341 | ||
1342 | iwl_enable_rfkill_int(trans); | |
1343 | ||
1344 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
1345 | ||
1346 | /* | |
1347 | * We enabled the RF-Kill interrupt and the handler may very | |
1348 | * well be running. Disable the interrupts to make sure no other | |
1349 | * interrupt can be fired. | |
1350 | */ | |
1351 | iwl_disable_interrupts(trans); | |
1352 | ||
1353 | /* Make sure it finished running */ | |
2e5d4a8f | 1354 | iwl_pcie_synchronize_irqs(trans); |
a6bd005f EG |
1355 | |
1356 | mutex_lock(&trans_pcie->mutex); | |
1357 | ||
1358 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
9ad8fd0b | 1359 | hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); |
a6bd005f EG |
1360 | if (hw_rfkill && !run_in_rfkill) { |
1361 | ret = -ERFKILL; | |
1362 | goto out; | |
1363 | } | |
1364 | ||
1365 | /* Someone called stop_device, don't try to start_fw */ | |
1366 | if (trans_pcie->is_down) { | |
1367 | IWL_WARN(trans, | |
1368 | "Can't start_fw since the HW hasn't been started\n"); | |
20aa99bb | 1369 | ret = -EIO; |
a6bd005f EG |
1370 | goto out; |
1371 | } | |
1372 | ||
1373 | /* make sure rfkill handshake bits are cleared */ | |
1374 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1375 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
1376 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | |
1377 | ||
1378 | /* clear (again), then enable host interrupts */ | |
1379 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
1380 | ||
1381 | ret = iwl_pcie_nic_init(trans); | |
1382 | if (ret) { | |
1383 | IWL_ERR(trans, "Unable to init nic\n"); | |
1384 | goto out; | |
1385 | } | |
1386 | ||
1387 | /* | |
1388 | * Now, we load the firmware and don't want to be interrupted, even | |
1389 | * by the RF-Kill interrupt (hence mask all the interrupt besides the | |
1390 | * FH_TX interrupt which is needed to load the firmware). If the | |
1391 | * RF-Kill switch is toggled, we will find out after having loaded | |
1392 | * the firmware and return the proper value to the caller. | |
1393 | */ | |
1394 | iwl_enable_fw_load_int(trans); | |
1395 | ||
1396 | /* really make sure rfkill handshake bits are cleared */ | |
1397 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1398 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1399 | ||
1400 | /* Load the given image to the HW */ | |
79b6c8fe | 1401 | if (trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_8000) |
a6bd005f EG |
1402 | ret = iwl_pcie_load_given_ucode_8000(trans, fw); |
1403 | else | |
1404 | ret = iwl_pcie_load_given_ucode(trans, fw); | |
a6bd005f EG |
1405 | |
1406 | /* re-check RF-Kill state since we may have missed the interrupt */ | |
9ad8fd0b | 1407 | hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); |
a6bd005f EG |
1408 | if (hw_rfkill && !run_in_rfkill) |
1409 | ret = -ERFKILL; | |
1410 | ||
1411 | out: | |
1412 | mutex_unlock(&trans_pcie->mutex); | |
1413 | return ret; | |
1414 | } | |
1415 | ||
1416 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) | |
1417 | { | |
1418 | iwl_pcie_reset_ict(trans); | |
1419 | iwl_pcie_tx_start(trans, scd_addr); | |
1420 | } | |
1421 | ||
326477e4 JB |
1422 | void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, |
1423 | bool was_in_rfkill) | |
1424 | { | |
1425 | bool hw_rfkill; | |
1426 | ||
1427 | /* | |
1428 | * Check again since the RF kill state may have changed while | |
1429 | * all the interrupts were disabled, in this case we couldn't | |
1430 | * receive the RF kill interrupt and update the state in the | |
1431 | * op_mode. | |
1432 | * Don't call the op_mode if the rkfill state hasn't changed. | |
1433 | * This allows the op_mode to call stop_device from the rfkill | |
1434 | * notification without endless recursion. Under very rare | |
1435 | * circumstances, we might have a small recursion if the rfkill | |
1436 | * state changed exactly now while we were called from stop_device. | |
1437 | * This is very unlikely but can happen and is supported. | |
1438 | */ | |
1439 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1440 | if (hw_rfkill) { | |
1441 | set_bit(STATUS_RFKILL_HW, &trans->status); | |
1442 | set_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1443 | } else { | |
1444 | clear_bit(STATUS_RFKILL_HW, &trans->status); | |
1445 | clear_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1446 | } | |
1447 | if (hw_rfkill != was_in_rfkill) | |
1448 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); | |
1449 | } | |
1450 | ||
bab3cb92 | 1451 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
fa9f3281 EG |
1452 | { |
1453 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
326477e4 | 1454 | bool was_in_rfkill; |
fa9f3281 EG |
1455 | |
1456 | mutex_lock(&trans_pcie->mutex); | |
326477e4 JB |
1457 | trans_pcie->opmode_down = true; |
1458 | was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
bab3cb92 | 1459 | _iwl_trans_pcie_stop_device(trans); |
326477e4 | 1460 | iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); |
fa9f3281 EG |
1461 | mutex_unlock(&trans_pcie->mutex); |
1462 | } | |
1463 | ||
14cfca71 JB |
1464 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) |
1465 | { | |
fa9f3281 EG |
1466 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1467 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1468 | ||
1469 | lockdep_assert_held(&trans_pcie->mutex); | |
1470 | ||
326477e4 JB |
1471 | IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", |
1472 | state ? "disabled" : "enabled"); | |
77c09bc8 | 1473 | if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { |
79b6c8fe | 1474 | if (trans->cfg->trans.gen2) |
bab3cb92 | 1475 | _iwl_trans_pcie_gen2_stop_device(trans); |
77c09bc8 | 1476 | else |
bab3cb92 | 1477 | _iwl_trans_pcie_stop_device(trans); |
77c09bc8 | 1478 | } |
ab6cf8e8 EG |
1479 | } |
1480 | ||
23ae6128 MG |
1481 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, |
1482 | bool reset) | |
2dd4f9f7 | 1483 | { |
23ae6128 | 1484 | if (!reset) { |
6dfb36c8 EP |
1485 | /* Enable persistence mode to avoid reset */ |
1486 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
1487 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
1488 | } | |
1489 | ||
2dd4f9f7 | 1490 | iwl_disable_interrupts(trans); |
debff618 JB |
1491 | |
1492 | /* | |
1493 | * in testing mode, the host stays awake and the | |
1494 | * hardware won't be reset (not even partially) | |
1495 | */ | |
1496 | if (test) | |
1497 | return; | |
1498 | ||
ddaf5a5b JB |
1499 | iwl_pcie_disable_ict(trans); |
1500 | ||
2e5d4a8f | 1501 | iwl_pcie_synchronize_irqs(trans); |
33b56af1 | 1502 | |
2dd4f9f7 | 1503 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
79b6c8fe | 1504 | BIT(trans->cfg->trans.csr->flag_mac_access_req)); |
ddaf5a5b | 1505 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
79b6c8fe | 1506 | BIT(trans->cfg->trans.csr->flag_init_done)); |
ddaf5a5b | 1507 | |
23ae6128 | 1508 | if (reset) { |
6dfb36c8 EP |
1509 | /* |
1510 | * reset TX queues -- some of their registers reset during S3 | |
1511 | * so if we don't reset everything here the D3 image would try | |
1512 | * to execute some invalid memory upon resume | |
1513 | */ | |
1514 | iwl_trans_pcie_tx_reset(trans); | |
1515 | } | |
ddaf5a5b JB |
1516 | |
1517 | iwl_pcie_set_pwr(trans, true); | |
1518 | } | |
1519 | ||
1520 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 | 1521 | enum iwl_d3_status *status, |
23ae6128 | 1522 | bool test, bool reset) |
ddaf5a5b | 1523 | { |
d7270d61 | 1524 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ddaf5a5b JB |
1525 | u32 val; |
1526 | int ret; | |
1527 | ||
debff618 JB |
1528 | if (test) { |
1529 | iwl_enable_interrupts(trans); | |
1530 | *status = IWL_D3_STATUS_ALIVE; | |
1531 | return 0; | |
1532 | } | |
1533 | ||
a8cbb46f | 1534 | iwl_set_bit(trans, CSR_GP_CNTRL, |
79b6c8fe | 1535 | BIT(trans->cfg->trans.csr->flag_mac_access_req)); |
ddaf5a5b | 1536 | |
79b6c8fe | 1537 | ret = iwl_finish_nic_init(trans, &trans->cfg->trans); |
c96b5eec | 1538 | if (ret) |
ddaf5a5b | 1539 | return ret; |
ddaf5a5b | 1540 | |
f98ad635 EG |
1541 | /* |
1542 | * Reconfigure IVAR table in case of MSIX or reset ict table in | |
1543 | * MSI mode since HW reset erased it. | |
1544 | * Also enables interrupts - none will happen as | |
1545 | * the device doesn't know we're waking it up, only when | |
1546 | * the opmode actually tells it after this call. | |
1547 | */ | |
1548 | iwl_pcie_conf_msix_hw(trans_pcie); | |
1549 | if (!trans_pcie->msix_enabled) | |
1550 | iwl_pcie_reset_ict(trans); | |
1551 | iwl_enable_interrupts(trans); | |
1552 | ||
a3ead656 EG |
1553 | iwl_pcie_set_pwr(trans, false); |
1554 | ||
23ae6128 | 1555 | if (!reset) { |
6dfb36c8 | 1556 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
79b6c8fe | 1557 | BIT(trans->cfg->trans.csr->flag_mac_access_req)); |
6dfb36c8 EP |
1558 | } else { |
1559 | iwl_trans_pcie_tx_reset(trans); | |
ddaf5a5b | 1560 | |
6dfb36c8 EP |
1561 | ret = iwl_pcie_rx_init(trans); |
1562 | if (ret) { | |
1563 | IWL_ERR(trans, | |
1564 | "Failed to resume the device (RX reset)\n"); | |
1565 | return ret; | |
1566 | } | |
ddaf5a5b JB |
1567 | } |
1568 | ||
82ea7966 | 1569 | IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", |
ea695b7c | 1570 | iwl_read_umac_prph(trans, WFPM_GP2)); |
82ea7966 | 1571 | |
a3ead656 EG |
1572 | val = iwl_read32(trans, CSR_RESET); |
1573 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) | |
1574 | *status = IWL_D3_STATUS_RESET; | |
1575 | else | |
1576 | *status = IWL_D3_STATUS_ALIVE; | |
1577 | ||
ddaf5a5b | 1578 | return 0; |
2dd4f9f7 JB |
1579 | } |
1580 | ||
0c18714a LC |
1581 | static void |
1582 | iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, | |
1583 | struct iwl_trans *trans, | |
1584 | const struct iwl_cfg_trans_params *cfg_trans) | |
2e5d4a8f HD |
1585 | { |
1586 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
ab1068d6 | 1587 | int max_irqs, num_irqs, i, ret; |
2e5d4a8f | 1588 | u16 pci_cmd; |
2e5d4a8f | 1589 | |
0c18714a | 1590 | if (!cfg_trans->mq_rx_supported) |
06f4b081 SS |
1591 | goto enable_msi; |
1592 | ||
ab1068d6 | 1593 | max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); |
06f4b081 SS |
1594 | for (i = 0; i < max_irqs; i++) |
1595 | trans_pcie->msix_entries[i].entry = i; | |
496d83ca | 1596 | |
06f4b081 SS |
1597 | num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, |
1598 | MSIX_MIN_INTERRUPT_VECTORS, | |
1599 | max_irqs); | |
1600 | if (num_irqs < 0) { | |
2e5d4a8f | 1601 | IWL_DEBUG_INFO(trans, |
06f4b081 SS |
1602 | "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", |
1603 | num_irqs); | |
1604 | goto enable_msi; | |
1605 | } | |
1606 | trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; | |
496d83ca | 1607 | |
06f4b081 SS |
1608 | IWL_DEBUG_INFO(trans, |
1609 | "MSI-X enabled. %d interrupt vectors were allocated\n", | |
1610 | num_irqs); | |
1611 | ||
1612 | /* | |
1613 | * In case the OS provides fewer interrupts than requested, different | |
1614 | * causes will share the same interrupt vector as follows: | |
1615 | * One interrupt less: non rx causes shared with FBQ. | |
1616 | * Two interrupts less: non rx causes shared with FBQ and RSS. | |
1617 | * More than two interrupts: we will use fewer RSS queues. | |
1618 | */ | |
ab1068d6 | 1619 | if (num_irqs <= max_irqs - 2) { |
06f4b081 SS |
1620 | trans_pcie->trans->num_rx_queues = num_irqs + 1; |
1621 | trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | | |
1622 | IWL_SHARED_IRQ_FIRST_RSS; | |
ab1068d6 | 1623 | } else if (num_irqs == max_irqs - 1) { |
06f4b081 SS |
1624 | trans_pcie->trans->num_rx_queues = num_irqs; |
1625 | trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; | |
1626 | } else { | |
1627 | trans_pcie->trans->num_rx_queues = num_irqs - 1; | |
2e5d4a8f | 1628 | } |
ab1068d6 | 1629 | WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); |
2e5d4a8f | 1630 | |
06f4b081 SS |
1631 | trans_pcie->alloc_vecs = num_irqs; |
1632 | trans_pcie->msix_enabled = true; | |
1633 | return; | |
1634 | ||
1635 | enable_msi: | |
1636 | ret = pci_enable_msi(pdev); | |
1637 | if (ret) { | |
1638 | dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); | |
2e5d4a8f HD |
1639 | /* enable rfkill interrupt: hw bug w/a */ |
1640 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1641 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1642 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1643 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1644 | } | |
1645 | } | |
1646 | } | |
1647 | ||
7c8d91eb HD |
1648 | static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) |
1649 | { | |
1650 | int iter_rx_q, i, ret, cpu, offset; | |
1651 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1652 | ||
1653 | i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; | |
1654 | iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; | |
1655 | offset = 1 + i; | |
1656 | for (; i < iter_rx_q ; i++) { | |
1657 | /* | |
1658 | * Get the cpu prior to the place to search | |
1659 | * (i.e. return will be > i - 1). | |
1660 | */ | |
1661 | cpu = cpumask_next(i - offset, cpu_online_mask); | |
1662 | cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); | |
1663 | ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, | |
1664 | &trans_pcie->affinity_mask[i]); | |
1665 | if (ret) | |
1666 | IWL_ERR(trans_pcie->trans, | |
1667 | "Failed to set affinity mask for IRQ %d\n", | |
1668 | i); | |
1669 | } | |
1670 | } | |
1671 | ||
2e5d4a8f HD |
1672 | static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, |
1673 | struct iwl_trans_pcie *trans_pcie) | |
1674 | { | |
496d83ca | 1675 | int i; |
2e5d4a8f | 1676 | |
496d83ca | 1677 | for (i = 0; i < trans_pcie->alloc_vecs; i++) { |
2e5d4a8f | 1678 | int ret; |
5a41a86c | 1679 | struct msix_entry *msix_entry; |
64fa3aff SD |
1680 | const char *qname = queue_name(&pdev->dev, trans_pcie, i); |
1681 | ||
1682 | if (!qname) | |
1683 | return -ENOMEM; | |
5a41a86c SD |
1684 | |
1685 | msix_entry = &trans_pcie->msix_entries[i]; | |
1686 | ret = devm_request_threaded_irq(&pdev->dev, | |
1687 | msix_entry->vector, | |
1688 | iwl_pcie_msix_isr, | |
1689 | (i == trans_pcie->def_irq) ? | |
1690 | iwl_pcie_irq_msix_handler : | |
1691 | iwl_pcie_irq_rx_msix_handler, | |
1692 | IRQF_SHARED, | |
64fa3aff | 1693 | qname, |
5a41a86c | 1694 | msix_entry); |
2e5d4a8f | 1695 | if (ret) { |
2e5d4a8f HD |
1696 | IWL_ERR(trans_pcie->trans, |
1697 | "Error allocating IRQ %d\n", i); | |
5a41a86c | 1698 | |
2e5d4a8f HD |
1699 | return ret; |
1700 | } | |
1701 | } | |
7c8d91eb | 1702 | iwl_pcie_irq_set_affinity(trans_pcie->trans); |
2e5d4a8f HD |
1703 | |
1704 | return 0; | |
1705 | } | |
1706 | ||
44f61b5c | 1707 | static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) |
e6bb4c9c | 1708 | { |
44f61b5c | 1709 | u32 hpm, wprot; |
fa9f3281 | 1710 | |
79b6c8fe | 1711 | switch (trans->cfg->trans.device_family) { |
44f61b5c SM |
1712 | case IWL_DEVICE_FAMILY_9000: |
1713 | wprot = PREG_PRPH_WPROT_9000; | |
1714 | break; | |
1715 | case IWL_DEVICE_FAMILY_22000: | |
1716 | wprot = PREG_PRPH_WPROT_22000; | |
1717 | break; | |
1718 | default: | |
1719 | return 0; | |
ebb7678d | 1720 | } |
a6c684ee | 1721 | |
ea695b7c | 1722 | hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); |
8954e1eb | 1723 | if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { |
44f61b5c | 1724 | u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); |
ea695b7c | 1725 | |
44f61b5c | 1726 | if (wprot_val & PREG_WFPM_ACCESS) { |
8954e1eb SM |
1727 | IWL_ERR(trans, |
1728 | "Error, can not clear persistence bit\n"); | |
1729 | return -EPERM; | |
1730 | } | |
ea695b7c ST |
1731 | iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, |
1732 | hpm & ~PERSISTENCE_BIT); | |
8954e1eb SM |
1733 | } |
1734 | ||
44f61b5c SM |
1735 | return 0; |
1736 | } | |
1737 | ||
bab3cb92 | 1738 | static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
44f61b5c SM |
1739 | { |
1740 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1741 | int err; | |
1742 | ||
1743 | lockdep_assert_held(&trans_pcie->mutex); | |
1744 | ||
1745 | err = iwl_pcie_prepare_card_hw(trans); | |
1746 | if (err) { | |
1747 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); | |
1748 | return err; | |
1749 | } | |
1750 | ||
1751 | err = iwl_trans_pcie_clear_persistence_bit(trans); | |
1752 | if (err) | |
1753 | return err; | |
1754 | ||
870c2a11 | 1755 | iwl_trans_pcie_sw_reset(trans); |
2997494f | 1756 | |
52b6e168 EG |
1757 | err = iwl_pcie_apm_init(trans); |
1758 | if (err) | |
1759 | return err; | |
a6c684ee | 1760 | |
2e5d4a8f | 1761 | iwl_pcie_init_msix(trans_pcie); |
83730058 | 1762 | |
226c02ca EG |
1763 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1764 | iwl_enable_rfkill_int(trans); | |
1765 | ||
326477e4 JB |
1766 | trans_pcie->opmode_down = false; |
1767 | ||
fa9f3281 EG |
1768 | /* Set is_down to false here so that...*/ |
1769 | trans_pcie->is_down = false; | |
1770 | ||
727c02df | 1771 | /* ...rfkill can call stop_device and set it false if needed */ |
9ad8fd0b | 1772 | iwl_pcie_check_hw_rf_kill(trans); |
d48e2074 | 1773 | |
a8b691e6 | 1774 | return 0; |
e6bb4c9c EG |
1775 | } |
1776 | ||
bab3cb92 | 1777 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
fa9f3281 EG |
1778 | { |
1779 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1780 | int ret; | |
1781 | ||
1782 | mutex_lock(&trans_pcie->mutex); | |
bab3cb92 | 1783 | ret = _iwl_trans_pcie_start_hw(trans); |
fa9f3281 EG |
1784 | mutex_unlock(&trans_pcie->mutex); |
1785 | ||
1786 | return ret; | |
1787 | } | |
1788 | ||
a4082843 | 1789 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 1790 | { |
20d3b647 | 1791 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1792 | |
fa9f3281 EG |
1793 | mutex_lock(&trans_pcie->mutex); |
1794 | ||
a4082843 | 1795 | /* disable interrupts - don't enable HW RF kill interrupt */ |
ee7d737c | 1796 | iwl_disable_interrupts(trans); |
ee7d737c | 1797 | |
b7aaeae4 | 1798 | iwl_pcie_apm_stop(trans, true); |
cc56feb2 | 1799 | |
218733cf | 1800 | iwl_disable_interrupts(trans); |
1df06bdc | 1801 | |
8d96bb61 | 1802 | iwl_pcie_disable_ict(trans); |
33b56af1 | 1803 | |
fa9f3281 | 1804 | mutex_unlock(&trans_pcie->mutex); |
33b56af1 | 1805 | |
2e5d4a8f | 1806 | iwl_pcie_synchronize_irqs(trans); |
cc56feb2 EG |
1807 | } |
1808 | ||
03905495 EG |
1809 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1810 | { | |
05f5b97e | 1811 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1812 | } |
1813 | ||
1814 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1815 | { | |
05f5b97e | 1816 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1817 | } |
1818 | ||
1819 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1820 | { | |
05f5b97e | 1821 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1822 | } |
1823 | ||
84fb372c SS |
1824 | static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) |
1825 | { | |
79b6c8fe | 1826 | if (trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_22560) |
84fb372c SS |
1827 | return 0x00FFFFFF; |
1828 | else | |
1829 | return 0x000FFFFF; | |
1830 | } | |
1831 | ||
6a06b6c1 EG |
1832 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
1833 | { | |
84fb372c SS |
1834 | u32 mask = iwl_trans_pcie_prph_msk(trans); |
1835 | ||
f9477c17 | 1836 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
84fb372c | 1837 | ((reg & mask) | (3 << 24))); |
6a06b6c1 EG |
1838 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
1839 | } | |
1840 | ||
1841 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
1842 | u32 val) | |
1843 | { | |
84fb372c SS |
1844 | u32 mask = iwl_trans_pcie_prph_msk(trans); |
1845 | ||
6a06b6c1 | 1846 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, |
84fb372c | 1847 | ((addr & mask) | (3 << 24))); |
6a06b6c1 EG |
1848 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
1849 | } | |
1850 | ||
c6f600fc | 1851 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1852 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1853 | { |
1854 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1855 | ||
1856 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 1857 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
4cf677fd | 1858 | trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; |
d663ee73 JB |
1859 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1860 | trans_pcie->n_no_reclaim_cmds = 0; | |
1861 | else | |
1862 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1863 | if (trans_pcie->n_no_reclaim_cmds) | |
1864 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1865 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 1866 | |
6c4fbcbc EG |
1867 | trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; |
1868 | trans_pcie->rx_page_order = | |
1869 | iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); | |
7c5ba4a8 | 1870 | |
046db346 | 1871 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
3a736bcb | 1872 | trans_pcie->scd_set_active = trans_cfg->scd_set_active; |
41837ca9 | 1873 | trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; |
f14d6b39 | 1874 | |
21cb3222 JB |
1875 | trans_pcie->page_offs = trans_cfg->cb_data_offs; |
1876 | trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); | |
1877 | ||
39bdb17e SD |
1878 | trans->command_groups = trans_cfg->command_groups; |
1879 | trans->command_groups_size = trans_cfg->command_groups_size; | |
1880 | ||
f14d6b39 JB |
1881 | /* Initialize NAPI here - it should be before registering to mac80211 |
1882 | * in the opmode but after the HW struct is allocated. | |
1883 | * As this function may be called again in some corner cases don't | |
1884 | * do anything if NAPI was already initialized. | |
1885 | */ | |
bce97731 | 1886 | if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) |
f14d6b39 | 1887 | init_dummy_netdev(&trans_pcie->napi_dev); |
c6f600fc MV |
1888 | } |
1889 | ||
d1ff5253 | 1890 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1891 | { |
20d3b647 | 1892 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
6eb5e529 | 1893 | int i; |
a42a1844 | 1894 | |
2e5d4a8f | 1895 | iwl_pcie_synchronize_irqs(trans); |
0aa86df6 | 1896 | |
79b6c8fe | 1897 | if (trans->cfg->trans.gen2) |
13a3a390 SS |
1898 | iwl_pcie_gen2_tx_free(trans); |
1899 | else | |
1900 | iwl_pcie_tx_free(trans); | |
9805c446 | 1901 | iwl_pcie_rx_free(trans); |
6379103e | 1902 | |
10a54d81 LC |
1903 | if (trans_pcie->rba.alloc_wq) { |
1904 | destroy_workqueue(trans_pcie->rba.alloc_wq); | |
1905 | trans_pcie->rba.alloc_wq = NULL; | |
1906 | } | |
1907 | ||
2e5d4a8f | 1908 | if (trans_pcie->msix_enabled) { |
7c8d91eb HD |
1909 | for (i = 0; i < trans_pcie->alloc_vecs; i++) { |
1910 | irq_set_affinity_hint( | |
1911 | trans_pcie->msix_entries[i].vector, | |
1912 | NULL); | |
7c8d91eb | 1913 | } |
2e5d4a8f | 1914 | |
2e5d4a8f HD |
1915 | trans_pcie->msix_enabled = false; |
1916 | } else { | |
2e5d4a8f | 1917 | iwl_pcie_free_ict(trans); |
2e5d4a8f | 1918 | } |
a42a1844 | 1919 | |
c2d20201 EG |
1920 | iwl_pcie_free_fw_monitor(trans); |
1921 | ||
6eb5e529 EG |
1922 | for_each_possible_cpu(i) { |
1923 | struct iwl_tso_hdr_page *p = | |
1924 | per_cpu_ptr(trans_pcie->tso_hdr_page, i); | |
1925 | ||
1926 | if (p->page) | |
1927 | __free_page(p->page); | |
1928 | } | |
1929 | ||
1930 | free_percpu(trans_pcie->tso_hdr_page); | |
a2a57a35 | 1931 | mutex_destroy(&trans_pcie->mutex); |
7b501d10 | 1932 | iwl_trans_free(trans); |
34c1b7ba EG |
1933 | } |
1934 | ||
47107e84 DF |
1935 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1936 | { | |
47107e84 | 1937 | if (state) |
eb7ff77e | 1938 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 1939 | else |
eb7ff77e | 1940 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
1941 | } |
1942 | ||
49564a80 LC |
1943 | struct iwl_trans_pcie_removal { |
1944 | struct pci_dev *pdev; | |
1945 | struct work_struct work; | |
1946 | }; | |
1947 | ||
1948 | static void iwl_trans_pcie_removal_wk(struct work_struct *wk) | |
1949 | { | |
1950 | struct iwl_trans_pcie_removal *removal = | |
1951 | container_of(wk, struct iwl_trans_pcie_removal, work); | |
1952 | struct pci_dev *pdev = removal->pdev; | |
aba1e632 | 1953 | static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; |
49564a80 LC |
1954 | |
1955 | dev_err(&pdev->dev, "Device gone - attempting removal\n"); | |
1956 | kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); | |
1957 | pci_lock_rescan_remove(); | |
1958 | pci_dev_put(pdev); | |
1959 | pci_stop_and_remove_bus_device(pdev); | |
1960 | pci_unlock_rescan_remove(); | |
1961 | ||
1962 | kfree(removal); | |
1963 | module_put(THIS_MODULE); | |
1964 | } | |
1965 | ||
23ba9340 EG |
1966 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, |
1967 | unsigned long *flags) | |
7a65d170 EG |
1968 | { |
1969 | int ret; | |
cfb4e624 JB |
1970 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1971 | ||
1972 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 | 1973 | |
fc8a350d | 1974 | if (trans_pcie->cmd_hold_nic_awake) |
b9439491 EG |
1975 | goto out; |
1976 | ||
7a65d170 | 1977 | /* this bit wakes up the NIC */ |
e139dc4a | 1978 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
79b6c8fe LC |
1979 | BIT(trans->cfg->trans.csr->flag_mac_access_req)); |
1980 | if (trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_8000) | |
01e58a28 | 1981 | udelay(2); |
7a65d170 EG |
1982 | |
1983 | /* | |
1984 | * These bits say the device is running, and should keep running for | |
1985 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
1986 | * but they do not indicate that embedded SRAM is restored yet; | |
fb70d49f LC |
1987 | * HW with volatile SRAM must save/restore contents to/from |
1988 | * host DRAM when sleeping/waking for power-saving. | |
7a65d170 EG |
1989 | * Each direction takes approximately 1/4 millisecond; with this |
1990 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
1991 | * series of register accesses are expected (e.g. reading Event Log), | |
1992 | * to keep device from sleeping. | |
1993 | * | |
1994 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
1995 | * SRAM is okay/restored. We don't check that here because this call | |
fb70d49f LC |
1996 | * is just for hardware register access; but GP1 MAC_SLEEP |
1997 | * check is a good idea before accessing the SRAM of HW with | |
1998 | * volatile SRAM (e.g. reading Event Log). | |
7a65d170 EG |
1999 | * |
2000 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
2001 | * and do not save/restore SRAM when power cycling. | |
2002 | */ | |
2003 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
79b6c8fe LC |
2004 | BIT(trans->cfg->trans.csr->flag_val_mac_access_en), |
2005 | (BIT(trans->cfg->trans.csr->flag_mac_clock_ready) | | |
7a65d170 EG |
2006 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); |
2007 | if (unlikely(ret < 0)) { | |
49564a80 LC |
2008 | u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); |
2009 | ||
23ba9340 EG |
2010 | WARN_ONCE(1, |
2011 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
49564a80 LC |
2012 | cntrl); |
2013 | ||
2014 | iwl_trans_pcie_dump_regs(trans); | |
2015 | ||
2016 | if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { | |
2017 | struct iwl_trans_pcie_removal *removal; | |
2018 | ||
f60c9e59 | 2019 | if (test_bit(STATUS_TRANS_DEAD, &trans->status)) |
49564a80 LC |
2020 | goto err; |
2021 | ||
2022 | IWL_ERR(trans, "Device gone - scheduling removal!\n"); | |
2023 | ||
2024 | /* | |
2025 | * get a module reference to avoid doing this | |
2026 | * while unloading anyway and to avoid | |
2027 | * scheduling a work with code that's being | |
2028 | * removed. | |
2029 | */ | |
2030 | if (!try_module_get(THIS_MODULE)) { | |
2031 | IWL_ERR(trans, | |
2032 | "Module is being unloaded - abort\n"); | |
2033 | goto err; | |
2034 | } | |
2035 | ||
2036 | removal = kzalloc(sizeof(*removal), GFP_ATOMIC); | |
2037 | if (!removal) { | |
2038 | module_put(THIS_MODULE); | |
2039 | goto err; | |
2040 | } | |
2041 | /* | |
2042 | * we don't need to clear this flag, because | |
2043 | * the trans will be freed and reallocated. | |
2044 | */ | |
f60c9e59 | 2045 | set_bit(STATUS_TRANS_DEAD, &trans->status); |
49564a80 LC |
2046 | |
2047 | removal->pdev = to_pci_dev(trans->dev); | |
2048 | INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); | |
2049 | pci_dev_get(removal->pdev); | |
2050 | schedule_work(&removal->work); | |
2051 | } else { | |
2052 | iwl_write32(trans, CSR_RESET, | |
2053 | CSR_RESET_REG_FLAG_FORCE_NMI); | |
2054 | } | |
2055 | ||
2056 | err: | |
23ba9340 EG |
2057 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
2058 | return false; | |
7a65d170 EG |
2059 | } |
2060 | ||
b9439491 | 2061 | out: |
e56b04ef LE |
2062 | /* |
2063 | * Fool sparse by faking we release the lock - sparse will | |
2064 | * track nic_access anyway. | |
2065 | */ | |
cfb4e624 | 2066 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
2067 | return true; |
2068 | } | |
2069 | ||
e56b04ef LE |
2070 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
2071 | unsigned long *flags) | |
7a65d170 | 2072 | { |
cfb4e624 | 2073 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 2074 | |
cfb4e624 | 2075 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
2076 | |
2077 | /* | |
2078 | * Fool sparse by faking we acquiring the lock - sparse will | |
2079 | * track nic_access anyway. | |
2080 | */ | |
cfb4e624 | 2081 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 2082 | |
fc8a350d | 2083 | if (trans_pcie->cmd_hold_nic_awake) |
b9439491 EG |
2084 | goto out; |
2085 | ||
e139dc4a | 2086 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
79b6c8fe | 2087 | BIT(trans->cfg->trans.csr->flag_mac_access_req)); |
7a65d170 EG |
2088 | /* |
2089 | * Above we read the CSR_GP_CNTRL register, which will flush | |
2090 | * any previous writes, but we need the write that clears the | |
2091 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
2092 | * scheduled on different CPUs (after we drop reg_lock). | |
2093 | */ | |
b9439491 | 2094 | out: |
cfb4e624 | 2095 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
2096 | } |
2097 | ||
4fd442db EG |
2098 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
2099 | void *buf, int dwords) | |
2100 | { | |
2101 | unsigned long flags; | |
2102 | int offs, ret = 0; | |
2103 | u32 *vals = buf; | |
2104 | ||
23ba9340 | 2105 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
4fd442db EG |
2106 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
2107 | for (offs = 0; offs < dwords; offs++) | |
2108 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 2109 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
2110 | } else { |
2111 | ret = -EBUSY; | |
2112 | } | |
4fd442db EG |
2113 | return ret; |
2114 | } | |
2115 | ||
2116 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 2117 | const void *buf, int dwords) |
4fd442db EG |
2118 | { |
2119 | unsigned long flags; | |
2120 | int offs, ret = 0; | |
bf0fd5da | 2121 | const u32 *vals = buf; |
4fd442db | 2122 | |
23ba9340 | 2123 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
4fd442db EG |
2124 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
2125 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
2126 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
2127 | vals ? vals[offs] : 0); | |
e56b04ef | 2128 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
2129 | } else { |
2130 | ret = -EBUSY; | |
2131 | } | |
4fd442db EG |
2132 | return ret; |
2133 | } | |
7a65d170 | 2134 | |
e0b8d405 EG |
2135 | static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, |
2136 | unsigned long txqs, | |
2137 | bool freeze) | |
2138 | { | |
2139 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2140 | int queue; | |
2141 | ||
2142 | for_each_set_bit(queue, &txqs, BITS_PER_LONG) { | |
b2a3b1c1 | 2143 | struct iwl_txq *txq = trans_pcie->txq[queue]; |
e0b8d405 EG |
2144 | unsigned long now; |
2145 | ||
2146 | spin_lock_bh(&txq->lock); | |
2147 | ||
2148 | now = jiffies; | |
2149 | ||
2150 | if (txq->frozen == freeze) | |
2151 | goto next_queue; | |
2152 | ||
2153 | IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", | |
2154 | freeze ? "Freezing" : "Waking", queue); | |
2155 | ||
2156 | txq->frozen = freeze; | |
2157 | ||
bb98ecd4 | 2158 | if (txq->read_ptr == txq->write_ptr) |
e0b8d405 EG |
2159 | goto next_queue; |
2160 | ||
2161 | if (freeze) { | |
2162 | if (unlikely(time_after(now, | |
2163 | txq->stuck_timer.expires))) { | |
2164 | /* | |
2165 | * The timer should have fired, maybe it is | |
2166 | * spinning right now on the lock. | |
2167 | */ | |
2168 | goto next_queue; | |
2169 | } | |
2170 | /* remember how long until the timer fires */ | |
2171 | txq->frozen_expiry_remainder = | |
2172 | txq->stuck_timer.expires - now; | |
2173 | del_timer(&txq->stuck_timer); | |
2174 | goto next_queue; | |
2175 | } | |
2176 | ||
2177 | /* | |
2178 | * Wake a non-empty queue -> arm timer with the | |
2179 | * remainder before it froze | |
2180 | */ | |
2181 | mod_timer(&txq->stuck_timer, | |
2182 | now + txq->frozen_expiry_remainder); | |
2183 | ||
2184 | next_queue: | |
2185 | spin_unlock_bh(&txq->lock); | |
2186 | } | |
2187 | } | |
2188 | ||
0cd58eaa EG |
2189 | static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) |
2190 | { | |
2191 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2192 | int i; | |
2193 | ||
79b6c8fe | 2194 | for (i = 0; i < trans->cfg->trans.base_params->num_of_queues; i++) { |
b2a3b1c1 | 2195 | struct iwl_txq *txq = trans_pcie->txq[i]; |
0cd58eaa EG |
2196 | |
2197 | if (i == trans_pcie->cmd_queue) | |
2198 | continue; | |
2199 | ||
2200 | spin_lock_bh(&txq->lock); | |
2201 | ||
2202 | if (!block && !(WARN_ON_ONCE(!txq->block))) { | |
2203 | txq->block--; | |
2204 | if (!txq->block) { | |
2205 | iwl_write32(trans, HBUS_TARG_WRPTR, | |
bb98ecd4 | 2206 | txq->write_ptr | (i << 8)); |
0cd58eaa EG |
2207 | } |
2208 | } else if (block) { | |
2209 | txq->block++; | |
2210 | } | |
2211 | ||
2212 | spin_unlock_bh(&txq->lock); | |
2213 | } | |
2214 | } | |
2215 | ||
5f178cd2 EG |
2216 | #define IWL_FLUSH_WAIT_MS 2000 |
2217 | ||
38398efb SS |
2218 | void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) |
2219 | { | |
afb84431 EG |
2220 | u32 txq_id = txq->id; |
2221 | u32 status; | |
2222 | bool active; | |
2223 | u8 fifo; | |
38398efb | 2224 | |
79b6c8fe | 2225 | if (trans->cfg->trans.use_tfh) { |
afb84431 EG |
2226 | IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, |
2227 | txq->read_ptr, txq->write_ptr); | |
ae79785f SS |
2228 | /* TODO: access new SCD registers and dump them */ |
2229 | return; | |
38398efb | 2230 | } |
afb84431 EG |
2231 | |
2232 | status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); | |
2233 | fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
2234 | active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
2235 | ||
2236 | IWL_ERR(trans, | |
2237 | "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", | |
2238 | txq_id, active ? "" : "in", fifo, | |
2239 | jiffies_to_msecs(txq->wd_timeout), | |
2240 | txq->read_ptr, txq->write_ptr, | |
2241 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & | |
79b6c8fe | 2242 | (trans->cfg->trans.base_params->max_tfd_queue_size - 1), |
afb84431 | 2243 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & |
79b6c8fe | 2244 | (trans->cfg->trans.base_params->max_tfd_queue_size - 1), |
afb84431 | 2245 | iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); |
38398efb SS |
2246 | } |
2247 | ||
92536c96 SS |
2248 | static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, |
2249 | struct iwl_trans_rxq_dma_data *data) | |
2250 | { | |
2251 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2252 | ||
2253 | if (queue >= trans->num_rx_queues || !trans_pcie->rxq) | |
2254 | return -EINVAL; | |
2255 | ||
2256 | data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; | |
2257 | data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; | |
2258 | data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; | |
2259 | data->fr_bd_wid = 0; | |
2260 | ||
2261 | return 0; | |
2262 | } | |
2263 | ||
d6d517b7 | 2264 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) |
5f178cd2 | 2265 | { |
8ad71bef | 2266 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 2267 | struct iwl_txq *txq; |
5f178cd2 | 2268 | unsigned long now = jiffies; |
2ae48edc | 2269 | bool overflow_tx; |
d6d517b7 SS |
2270 | u8 wr_ptr; |
2271 | ||
2b3fae66 | 2272 | /* Make sure the NIC is still alive in the bus */ |
f60c9e59 EG |
2273 | if (test_bit(STATUS_TRANS_DEAD, &trans->status)) |
2274 | return -ENODEV; | |
2b3fae66 | 2275 | |
d6d517b7 SS |
2276 | if (!test_bit(txq_idx, trans_pcie->queue_used)) |
2277 | return -EINVAL; | |
2278 | ||
2279 | IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); | |
2280 | txq = trans_pcie->txq[txq_idx]; | |
2ae48edc SS |
2281 | |
2282 | spin_lock_bh(&txq->lock); | |
2283 | overflow_tx = txq->overflow_tx || | |
2284 | !skb_queue_empty(&txq->overflow_q); | |
2285 | spin_unlock_bh(&txq->lock); | |
2286 | ||
6aa7de05 | 2287 | wr_ptr = READ_ONCE(txq->write_ptr); |
d6d517b7 | 2288 | |
2ae48edc SS |
2289 | while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || |
2290 | overflow_tx) && | |
d6d517b7 SS |
2291 | !time_after(jiffies, |
2292 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { | |
6aa7de05 | 2293 | u8 write_ptr = READ_ONCE(txq->write_ptr); |
d6d517b7 | 2294 | |
2ae48edc SS |
2295 | /* |
2296 | * If write pointer moved during the wait, warn only | |
2297 | * if the TX came from op mode. In case TX came from | |
2298 | * trans layer (overflow TX) don't warn. | |
2299 | */ | |
2300 | if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, | |
d6d517b7 SS |
2301 | "WR pointer moved while flushing %d -> %d\n", |
2302 | wr_ptr, write_ptr)) | |
2303 | return -ETIMEDOUT; | |
2ae48edc SS |
2304 | wr_ptr = write_ptr; |
2305 | ||
d6d517b7 | 2306 | usleep_range(1000, 2000); |
2ae48edc SS |
2307 | |
2308 | spin_lock_bh(&txq->lock); | |
2309 | overflow_tx = txq->overflow_tx || | |
2310 | !skb_queue_empty(&txq->overflow_q); | |
2311 | spin_unlock_bh(&txq->lock); | |
d6d517b7 SS |
2312 | } |
2313 | ||
2314 | if (txq->read_ptr != txq->write_ptr) { | |
2315 | IWL_ERR(trans, | |
2316 | "fail to flush all tx fifo queues Q %d\n", txq_idx); | |
2317 | iwl_trans_pcie_log_scd_error(trans, txq); | |
2318 | return -ETIMEDOUT; | |
2319 | } | |
2320 | ||
2321 | IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); | |
2322 | ||
2323 | return 0; | |
2324 | } | |
2325 | ||
2326 | static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) | |
2327 | { | |
2328 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2329 | int cnt; | |
5f178cd2 EG |
2330 | int ret = 0; |
2331 | ||
2332 | /* waiting for all the tx frames complete might take a while */ | |
79b6c8fe LC |
2333 | for (cnt = 0; |
2334 | cnt < trans->cfg->trans.base_params->num_of_queues; | |
2335 | cnt++) { | |
fa1a91fd | 2336 | |
9ba1947a | 2337 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 2338 | continue; |
3cafdbe6 EG |
2339 | if (!test_bit(cnt, trans_pcie->queue_used)) |
2340 | continue; | |
2341 | if (!(BIT(cnt) & txq_bm)) | |
2342 | continue; | |
748fa67c | 2343 | |
d6d517b7 SS |
2344 | ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); |
2345 | if (ret) | |
5f178cd2 | 2346 | break; |
5f178cd2 | 2347 | } |
1c3fea82 | 2348 | |
5f178cd2 EG |
2349 | return ret; |
2350 | } | |
2351 | ||
e139dc4a LE |
2352 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
2353 | u32 mask, u32 value) | |
2354 | { | |
e56b04ef | 2355 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
2356 | unsigned long flags; |
2357 | ||
e56b04ef | 2358 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 2359 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 2360 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
2361 | } |
2362 | ||
ff620849 EG |
2363 | static const char *get_csr_string(int cmd) |
2364 | { | |
d9fb6465 | 2365 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
2366 | switch (cmd) { |
2367 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
2368 | IWL_CMD(CSR_INT_COALESCING); | |
2369 | IWL_CMD(CSR_INT); | |
2370 | IWL_CMD(CSR_INT_MASK); | |
2371 | IWL_CMD(CSR_FH_INT_STATUS); | |
2372 | IWL_CMD(CSR_GPIO_IN); | |
2373 | IWL_CMD(CSR_RESET); | |
2374 | IWL_CMD(CSR_GP_CNTRL); | |
2375 | IWL_CMD(CSR_HW_REV); | |
2376 | IWL_CMD(CSR_EEPROM_REG); | |
2377 | IWL_CMD(CSR_EEPROM_GP); | |
2378 | IWL_CMD(CSR_OTP_GP_REG); | |
2379 | IWL_CMD(CSR_GIO_REG); | |
2380 | IWL_CMD(CSR_GP_UCODE_REG); | |
2381 | IWL_CMD(CSR_GP_DRIVER_REG); | |
2382 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
2383 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
2384 | IWL_CMD(CSR_LED_REG); | |
2385 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
2386 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
2387 | IWL_CMD(CSR_ANA_PLL_CFG); | |
2388 | IWL_CMD(CSR_HW_REV_WA_REG); | |
a812cba9 | 2389 | IWL_CMD(CSR_MONITOR_STATUS_REG); |
ff620849 EG |
2390 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
2391 | default: | |
2392 | return "UNKNOWN"; | |
2393 | } | |
d9fb6465 | 2394 | #undef IWL_CMD |
ff620849 EG |
2395 | } |
2396 | ||
990aa6d7 | 2397 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
2398 | { |
2399 | int i; | |
2400 | static const u32 csr_tbl[] = { | |
2401 | CSR_HW_IF_CONFIG_REG, | |
2402 | CSR_INT_COALESCING, | |
2403 | CSR_INT, | |
2404 | CSR_INT_MASK, | |
2405 | CSR_FH_INT_STATUS, | |
2406 | CSR_GPIO_IN, | |
2407 | CSR_RESET, | |
2408 | CSR_GP_CNTRL, | |
2409 | CSR_HW_REV, | |
2410 | CSR_EEPROM_REG, | |
2411 | CSR_EEPROM_GP, | |
2412 | CSR_OTP_GP_REG, | |
2413 | CSR_GIO_REG, | |
2414 | CSR_GP_UCODE_REG, | |
2415 | CSR_GP_DRIVER_REG, | |
2416 | CSR_UCODE_DRV_GP1, | |
2417 | CSR_UCODE_DRV_GP2, | |
2418 | CSR_LED_REG, | |
2419 | CSR_DRAM_INT_TBL_REG, | |
2420 | CSR_GIO_CHICKEN_BITS, | |
2421 | CSR_ANA_PLL_CFG, | |
a812cba9 | 2422 | CSR_MONITOR_STATUS_REG, |
ff620849 EG |
2423 | CSR_HW_REV_WA_REG, |
2424 | CSR_DBG_HPET_MEM_REG | |
2425 | }; | |
2426 | IWL_ERR(trans, "CSR values:\n"); | |
2427 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
2428 | "CSR_INT_PERIODIC_REG)\n"); | |
2429 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
2430 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
2431 | get_csr_string(csr_tbl[i]), | |
1042db2a | 2432 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
2433 | } |
2434 | } | |
2435 | ||
87e5666c EG |
2436 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
2437 | /* create and remove of files */ | |
2438 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
cf5d5663 GKH |
2439 | debugfs_create_file(#name, mode, parent, trans, \ |
2440 | &iwl_dbgfs_##name##_ops); \ | |
87e5666c EG |
2441 | } while (0) |
2442 | ||
2443 | /* file operation */ | |
87e5666c | 2444 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
2445 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2446 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 2447 | .open = simple_open, \ |
87e5666c EG |
2448 | .llseek = generic_file_llseek, \ |
2449 | }; | |
2450 | ||
16db88ba | 2451 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
2452 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2453 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 2454 | .open = simple_open, \ |
16db88ba EG |
2455 | .llseek = generic_file_llseek, \ |
2456 | }; | |
2457 | ||
87e5666c | 2458 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
2459 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2460 | .write = iwl_dbgfs_##name##_write, \ | |
2461 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 2462 | .open = simple_open, \ |
87e5666c EG |
2463 | .llseek = generic_file_llseek, \ |
2464 | }; | |
2465 | ||
87e5666c | 2466 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
2467 | char __user *user_buf, |
2468 | size_t count, loff_t *ppos) | |
8ad71bef | 2469 | { |
5a878bf6 | 2470 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 2471 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 2472 | struct iwl_txq *txq; |
87e5666c EG |
2473 | char *buf; |
2474 | int pos = 0; | |
2475 | int cnt; | |
2476 | int ret; | |
1745e440 WYG |
2477 | size_t bufsz; |
2478 | ||
79b6c8fe LC |
2479 | bufsz = sizeof(char) * 75 * |
2480 | trans->cfg->trans.base_params->num_of_queues; | |
87e5666c | 2481 | |
b2a3b1c1 | 2482 | if (!trans_pcie->txq_memory) |
87e5666c | 2483 | return -EAGAIN; |
f9e75447 | 2484 | |
87e5666c EG |
2485 | buf = kzalloc(bufsz, GFP_KERNEL); |
2486 | if (!buf) | |
2487 | return -ENOMEM; | |
2488 | ||
79b6c8fe LC |
2489 | for (cnt = 0; |
2490 | cnt < trans->cfg->trans.base_params->num_of_queues; | |
2491 | cnt++) { | |
b2a3b1c1 | 2492 | txq = trans_pcie->txq[cnt]; |
87e5666c | 2493 | pos += scnprintf(buf + pos, bufsz - pos, |
e0b8d405 | 2494 | "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", |
bb98ecd4 | 2495 | cnt, txq->read_ptr, txq->write_ptr, |
9eae88fa | 2496 | !!test_bit(cnt, trans_pcie->queue_used), |
f40faf62 | 2497 | !!test_bit(cnt, trans_pcie->queue_stopped), |
e0b8d405 | 2498 | txq->need_update, txq->frozen, |
f40faf62 | 2499 | (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); |
87e5666c EG |
2500 | } |
2501 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2502 | kfree(buf); | |
2503 | return ret; | |
2504 | } | |
2505 | ||
2506 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
2507 | char __user *user_buf, |
2508 | size_t count, loff_t *ppos) | |
2509 | { | |
5a878bf6 | 2510 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 2511 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
78485054 SS |
2512 | char *buf; |
2513 | int pos = 0, i, ret; | |
2514 | size_t bufsz = sizeof(buf); | |
2515 | ||
2516 | bufsz = sizeof(char) * 121 * trans->num_rx_queues; | |
2517 | ||
2518 | if (!trans_pcie->rxq) | |
2519 | return -EAGAIN; | |
2520 | ||
2521 | buf = kzalloc(bufsz, GFP_KERNEL); | |
2522 | if (!buf) | |
2523 | return -ENOMEM; | |
2524 | ||
2525 | for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { | |
2526 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
2527 | ||
2528 | pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", | |
2529 | i); | |
2530 | pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", | |
2531 | rxq->read); | |
2532 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", | |
2533 | rxq->write); | |
2534 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", | |
2535 | rxq->write_actual); | |
2536 | pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", | |
2537 | rxq->need_update); | |
2538 | pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", | |
2539 | rxq->free_count); | |
2540 | if (rxq->rb_stts) { | |
0307c839 GBA |
2541 | u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, |
2542 | rxq)); | |
78485054 SS |
2543 | pos += scnprintf(buf + pos, bufsz - pos, |
2544 | "\tclosed_rb_num: %u\n", | |
0307c839 | 2545 | r & 0x0FFF); |
78485054 SS |
2546 | } else { |
2547 | pos += scnprintf(buf + pos, bufsz - pos, | |
2548 | "\tclosed_rb_num: Not Allocated\n"); | |
60c0a88f | 2549 | } |
87e5666c | 2550 | } |
78485054 SS |
2551 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
2552 | kfree(buf); | |
2553 | ||
2554 | return ret; | |
87e5666c EG |
2555 | } |
2556 | ||
1f7b6172 EG |
2557 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
2558 | char __user *user_buf, | |
20d3b647 JB |
2559 | size_t count, loff_t *ppos) |
2560 | { | |
1f7b6172 | 2561 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 2562 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
2563 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
2564 | ||
2565 | int pos = 0; | |
2566 | char *buf; | |
2567 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
2568 | ssize_t ret; | |
2569 | ||
2570 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 2571 | if (!buf) |
1f7b6172 | 2572 | return -ENOMEM; |
1f7b6172 EG |
2573 | |
2574 | pos += scnprintf(buf + pos, bufsz - pos, | |
2575 | "Interrupt Statistics Report:\n"); | |
2576 | ||
2577 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
2578 | isr_stats->hw); | |
2579 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
2580 | isr_stats->sw); | |
2581 | if (isr_stats->sw || isr_stats->hw) { | |
2582 | pos += scnprintf(buf + pos, bufsz - pos, | |
2583 | "\tLast Restarting Code: 0x%X\n", | |
2584 | isr_stats->err_code); | |
2585 | } | |
2586 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2587 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
2588 | isr_stats->sch); | |
2589 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
2590 | isr_stats->alive); | |
2591 | #endif | |
2592 | pos += scnprintf(buf + pos, bufsz - pos, | |
2593 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
2594 | ||
2595 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
2596 | isr_stats->ctkill); | |
2597 | ||
2598 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
2599 | isr_stats->wakeup); | |
2600 | ||
2601 | pos += scnprintf(buf + pos, bufsz - pos, | |
2602 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
2603 | ||
2604 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
2605 | isr_stats->tx); | |
2606 | ||
2607 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
2608 | isr_stats->unhandled); | |
2609 | ||
2610 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2611 | kfree(buf); | |
2612 | return ret; | |
2613 | } | |
2614 | ||
2615 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
2616 | const char __user *user_buf, | |
2617 | size_t count, loff_t *ppos) | |
2618 | { | |
2619 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 2620 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 | 2621 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1f7b6172 | 2622 | u32 reset_flag; |
078f1131 | 2623 | int ret; |
1f7b6172 | 2624 | |
078f1131 JB |
2625 | ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); |
2626 | if (ret) | |
2627 | return ret; | |
1f7b6172 EG |
2628 | if (reset_flag == 0) |
2629 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
2630 | ||
2631 | return count; | |
2632 | } | |
2633 | ||
16db88ba | 2634 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
2635 | const char __user *user_buf, |
2636 | size_t count, loff_t *ppos) | |
16db88ba EG |
2637 | { |
2638 | struct iwl_trans *trans = file->private_data; | |
16db88ba | 2639 | |
990aa6d7 | 2640 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
2641 | |
2642 | return count; | |
2643 | } | |
2644 | ||
16db88ba | 2645 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
2646 | char __user *user_buf, |
2647 | size_t count, loff_t *ppos) | |
16db88ba EG |
2648 | { |
2649 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 2650 | char *buf = NULL; |
56c2477f | 2651 | ssize_t ret; |
16db88ba | 2652 | |
56c2477f JB |
2653 | ret = iwl_dump_fh(trans, &buf); |
2654 | if (ret < 0) | |
2655 | return ret; | |
2656 | if (!buf) | |
2657 | return -EINVAL; | |
2658 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); | |
2659 | kfree(buf); | |
16db88ba EG |
2660 | return ret; |
2661 | } | |
2662 | ||
fa4de7f7 JB |
2663 | static ssize_t iwl_dbgfs_rfkill_read(struct file *file, |
2664 | char __user *user_buf, | |
2665 | size_t count, loff_t *ppos) | |
2666 | { | |
2667 | struct iwl_trans *trans = file->private_data; | |
2668 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2669 | char buf[100]; | |
2670 | int pos; | |
2671 | ||
2672 | pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", | |
2673 | trans_pcie->debug_rfkill, | |
2674 | !(iwl_read32(trans, CSR_GP_CNTRL) & | |
2675 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); | |
2676 | ||
2677 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2678 | } | |
2679 | ||
2680 | static ssize_t iwl_dbgfs_rfkill_write(struct file *file, | |
2681 | const char __user *user_buf, | |
2682 | size_t count, loff_t *ppos) | |
2683 | { | |
2684 | struct iwl_trans *trans = file->private_data; | |
2685 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
c5bf4fa1 | 2686 | bool new_value; |
fa4de7f7 JB |
2687 | int ret; |
2688 | ||
c5bf4fa1 | 2689 | ret = kstrtobool_from_user(user_buf, count, &new_value); |
fa4de7f7 JB |
2690 | if (ret) |
2691 | return ret; | |
c5bf4fa1 | 2692 | if (new_value == trans_pcie->debug_rfkill) |
fa4de7f7 JB |
2693 | return count; |
2694 | IWL_WARN(trans, "changing debug rfkill %d->%d\n", | |
c5bf4fa1 JB |
2695 | trans_pcie->debug_rfkill, new_value); |
2696 | trans_pcie->debug_rfkill = new_value; | |
fa4de7f7 JB |
2697 | iwl_pcie_handle_rfkill_irq(trans); |
2698 | ||
2699 | return count; | |
2700 | } | |
2701 | ||
f7805b33 LC |
2702 | static int iwl_dbgfs_monitor_data_open(struct inode *inode, |
2703 | struct file *file) | |
2704 | { | |
2705 | struct iwl_trans *trans = inode->i_private; | |
2706 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2707 | ||
91c28b83 SM |
2708 | if (!trans->dbg.dest_tlv || |
2709 | trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { | |
f7805b33 LC |
2710 | IWL_ERR(trans, "Debug destination is not set to DRAM\n"); |
2711 | return -ENOENT; | |
2712 | } | |
2713 | ||
2714 | if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) | |
2715 | return -EBUSY; | |
2716 | ||
2717 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; | |
2718 | return simple_open(inode, file); | |
2719 | } | |
2720 | ||
2721 | static int iwl_dbgfs_monitor_data_release(struct inode *inode, | |
2722 | struct file *file) | |
2723 | { | |
2724 | struct iwl_trans_pcie *trans_pcie = | |
2725 | IWL_TRANS_GET_PCIE_TRANS(inode->i_private); | |
2726 | ||
2727 | if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) | |
2728 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; | |
2729 | return 0; | |
2730 | } | |
2731 | ||
2732 | static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, | |
2733 | void *buf, ssize_t *size, | |
2734 | ssize_t *bytes_copied) | |
2735 | { | |
2736 | int buf_size_left = count - *bytes_copied; | |
2737 | ||
2738 | buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); | |
2739 | if (*size > buf_size_left) | |
2740 | *size = buf_size_left; | |
2741 | ||
2742 | *size -= copy_to_user(user_buf, buf, *size); | |
2743 | *bytes_copied += *size; | |
2744 | ||
2745 | if (buf_size_left == *size) | |
2746 | return true; | |
2747 | return false; | |
2748 | } | |
2749 | ||
2750 | static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, | |
2751 | char __user *user_buf, | |
2752 | size_t count, loff_t *ppos) | |
2753 | { | |
2754 | struct iwl_trans *trans = file->private_data; | |
2755 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
91c28b83 | 2756 | void *cpu_addr = (void *)trans->dbg.fw_mon[0].block, *curr_buf; |
f7805b33 LC |
2757 | struct cont_rec *data = &trans_pcie->fw_mon_data; |
2758 | u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; | |
2759 | ssize_t size, bytes_copied = 0; | |
2760 | bool b_full; | |
2761 | ||
91c28b83 | 2762 | if (trans->dbg.dest_tlv) { |
f7805b33 | 2763 | write_ptr_addr = |
91c28b83 SM |
2764 | le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); |
2765 | wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); | |
f7805b33 LC |
2766 | } else { |
2767 | write_ptr_addr = MON_BUFF_WRPTR; | |
2768 | wrap_cnt_addr = MON_BUFF_CYCLE_CNT; | |
2769 | } | |
2770 | ||
91c28b83 | 2771 | if (unlikely(!trans->dbg.rec_on)) |
f7805b33 LC |
2772 | return 0; |
2773 | ||
2774 | mutex_lock(&data->mutex); | |
2775 | if (data->state == | |
2776 | IWL_FW_MON_DBGFS_STATE_DISABLED) { | |
2777 | mutex_unlock(&data->mutex); | |
2778 | return 0; | |
2779 | } | |
2780 | ||
2781 | /* write_ptr position in bytes rather then DW */ | |
2782 | write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); | |
2783 | wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); | |
2784 | ||
2785 | if (data->prev_wrap_cnt == wrap_cnt) { | |
2786 | size = write_ptr - data->prev_wr_ptr; | |
2787 | curr_buf = cpu_addr + data->prev_wr_ptr; | |
2788 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2789 | curr_buf, &size, | |
2790 | &bytes_copied); | |
2791 | data->prev_wr_ptr += size; | |
2792 | ||
2793 | } else if (data->prev_wrap_cnt == wrap_cnt - 1 && | |
2794 | write_ptr < data->prev_wr_ptr) { | |
91c28b83 | 2795 | size = trans->dbg.fw_mon[0].size - data->prev_wr_ptr; |
f7805b33 LC |
2796 | curr_buf = cpu_addr + data->prev_wr_ptr; |
2797 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2798 | curr_buf, &size, | |
2799 | &bytes_copied); | |
2800 | data->prev_wr_ptr += size; | |
2801 | ||
2802 | if (!b_full) { | |
2803 | size = write_ptr; | |
2804 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2805 | cpu_addr, &size, | |
2806 | &bytes_copied); | |
2807 | data->prev_wr_ptr = size; | |
2808 | data->prev_wrap_cnt++; | |
2809 | } | |
2810 | } else { | |
2811 | if (data->prev_wrap_cnt == wrap_cnt - 1 && | |
2812 | write_ptr > data->prev_wr_ptr) | |
2813 | IWL_WARN(trans, | |
2814 | "write pointer passed previous write pointer, start copying from the beginning\n"); | |
2815 | else if (!unlikely(data->prev_wrap_cnt == 0 && | |
2816 | data->prev_wr_ptr == 0)) | |
2817 | IWL_WARN(trans, | |
2818 | "monitor data is out of sync, start copying from the beginning\n"); | |
2819 | ||
2820 | size = write_ptr; | |
2821 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2822 | cpu_addr, &size, | |
2823 | &bytes_copied); | |
2824 | data->prev_wr_ptr = size; | |
2825 | data->prev_wrap_cnt = wrap_cnt; | |
2826 | } | |
2827 | ||
2828 | mutex_unlock(&data->mutex); | |
2829 | ||
2830 | return bytes_copied; | |
2831 | } | |
2832 | ||
1f7b6172 | 2833 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2834 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2835 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2836 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2837 | DEBUGFS_WRITE_FILE_OPS(csr); |
fa4de7f7 | 2838 | DEBUGFS_READ_WRITE_FILE_OPS(rfkill); |
87e5666c | 2839 | |
f7805b33 LC |
2840 | static const struct file_operations iwl_dbgfs_monitor_data_ops = { |
2841 | .read = iwl_dbgfs_monitor_data_read, | |
2842 | .open = iwl_dbgfs_monitor_data_open, | |
2843 | .release = iwl_dbgfs_monitor_data_release, | |
2844 | }; | |
2845 | ||
f8a1edb7 | 2846 | /* Create the debugfs files and directories */ |
cf5d5663 | 2847 | void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) |
87e5666c | 2848 | { |
f8a1edb7 JB |
2849 | struct dentry *dir = trans->dbgfs_dir; |
2850 | ||
2ef00c53 JP |
2851 | DEBUGFS_ADD_FILE(rx_queue, dir, 0400); |
2852 | DEBUGFS_ADD_FILE(tx_queue, dir, 0400); | |
2853 | DEBUGFS_ADD_FILE(interrupt, dir, 0600); | |
2854 | DEBUGFS_ADD_FILE(csr, dir, 0200); | |
2855 | DEBUGFS_ADD_FILE(fh_reg, dir, 0400); | |
2856 | DEBUGFS_ADD_FILE(rfkill, dir, 0600); | |
f7805b33 | 2857 | DEBUGFS_ADD_FILE(monitor_data, dir, 0400); |
87e5666c | 2858 | } |
f7805b33 LC |
2859 | |
2860 | static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) | |
2861 | { | |
2862 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2863 | struct cont_rec *data = &trans_pcie->fw_mon_data; | |
2864 | ||
2865 | mutex_lock(&data->mutex); | |
2866 | data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; | |
2867 | mutex_unlock(&data->mutex); | |
2868 | } | |
aadede6e | 2869 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
4d075007 | 2870 | |
6983ba69 | 2871 | static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) |
4d075007 | 2872 | { |
3cd1980b | 2873 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4d075007 JB |
2874 | u32 cmdlen = 0; |
2875 | int i; | |
2876 | ||
3cd1980b | 2877 | for (i = 0; i < trans_pcie->max_tbs; i++) |
6983ba69 | 2878 | cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); |
4d075007 JB |
2879 | |
2880 | return cmdlen; | |
2881 | } | |
2882 | ||
bd7fc617 EG |
2883 | static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, |
2884 | struct iwl_fw_error_dump_data **data, | |
2885 | int allocated_rb_nums) | |
2886 | { | |
2887 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2888 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; | |
78485054 SS |
2889 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
2890 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; | |
bd7fc617 EG |
2891 | u32 i, r, j, rb_len = 0; |
2892 | ||
2893 | spin_lock(&rxq->lock); | |
2894 | ||
0307c839 | 2895 | r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; |
bd7fc617 EG |
2896 | |
2897 | for (i = rxq->read, j = 0; | |
2898 | i != r && j < allocated_rb_nums; | |
2899 | i = (i + 1) & RX_QUEUE_MASK, j++) { | |
2900 | struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; | |
2901 | struct iwl_fw_error_dump_rb *rb; | |
2902 | ||
2903 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, | |
2904 | DMA_FROM_DEVICE); | |
2905 | ||
2906 | rb_len += sizeof(**data) + sizeof(*rb) + max_len; | |
2907 | ||
2908 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); | |
2909 | (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); | |
2910 | rb = (void *)(*data)->data; | |
2911 | rb->index = cpu_to_le32(i); | |
2912 | memcpy(rb->data, page_address(rxb->page), max_len); | |
2913 | /* remap the page for the free benefit */ | |
2914 | rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, | |
2915 | max_len, | |
2916 | DMA_FROM_DEVICE); | |
2917 | ||
2918 | *data = iwl_fw_error_next_data(*data); | |
2919 | } | |
2920 | ||
2921 | spin_unlock(&rxq->lock); | |
2922 | ||
2923 | return rb_len; | |
2924 | } | |
473ad712 EG |
2925 | #define IWL_CSR_TO_DUMP (0x250) |
2926 | ||
2927 | static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, | |
2928 | struct iwl_fw_error_dump_data **data) | |
2929 | { | |
2930 | u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; | |
2931 | __le32 *val; | |
2932 | int i; | |
2933 | ||
2934 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); | |
2935 | (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); | |
2936 | val = (void *)(*data)->data; | |
2937 | ||
2938 | for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) | |
2939 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2940 | ||
2941 | *data = iwl_fw_error_next_data(*data); | |
2942 | ||
2943 | return csr_len; | |
2944 | } | |
2945 | ||
06d51e0d LK |
2946 | static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, |
2947 | struct iwl_fw_error_dump_data **data) | |
2948 | { | |
2949 | u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; | |
2950 | unsigned long flags; | |
2951 | __le32 *val; | |
2952 | int i; | |
2953 | ||
23ba9340 | 2954 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
06d51e0d LK |
2955 | return 0; |
2956 | ||
2957 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); | |
2958 | (*data)->len = cpu_to_le32(fh_regs_len); | |
2959 | val = (void *)(*data)->data; | |
2960 | ||
79b6c8fe | 2961 | if (!trans->cfg->trans.gen2) |
723b45e2 LK |
2962 | for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; |
2963 | i += sizeof(u32)) | |
2964 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2965 | else | |
ea695b7c ST |
2966 | for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); |
2967 | i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); | |
723b45e2 LK |
2968 | i += sizeof(u32)) |
2969 | *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, | |
2970 | i)); | |
06d51e0d LK |
2971 | |
2972 | iwl_trans_release_nic_access(trans, &flags); | |
2973 | ||
2974 | *data = iwl_fw_error_next_data(*data); | |
2975 | ||
2976 | return sizeof(**data) + fh_regs_len; | |
2977 | } | |
2978 | ||
cc79ef66 LK |
2979 | static u32 |
2980 | iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, | |
2981 | struct iwl_fw_error_dump_fw_mon *fw_mon_data, | |
2982 | u32 monitor_len) | |
2983 | { | |
2984 | u32 buf_size_in_dwords = (monitor_len >> 2); | |
2985 | u32 *buffer = (u32 *)fw_mon_data->data; | |
2986 | unsigned long flags; | |
2987 | u32 i; | |
2988 | ||
23ba9340 | 2989 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
cc79ef66 LK |
2990 | return 0; |
2991 | ||
ea695b7c | 2992 | iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); |
cc79ef66 | 2993 | for (i = 0; i < buf_size_in_dwords; i++) |
ea695b7c ST |
2994 | buffer[i] = iwl_read_umac_prph_no_grab(trans, |
2995 | MON_DMARB_RD_DATA_ADDR); | |
2996 | iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); | |
cc79ef66 LK |
2997 | |
2998 | iwl_trans_release_nic_access(trans, &flags); | |
2999 | ||
3000 | return monitor_len; | |
3001 | } | |
3002 | ||
7a14c23d SS |
3003 | static void |
3004 | iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, | |
3005 | struct iwl_fw_error_dump_fw_mon *fw_mon_data) | |
3006 | { | |
c88580e1 | 3007 | u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; |
7a14c23d | 3008 | |
79b6c8fe | 3009 | if (trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_AX210) { |
c88580e1 SM |
3010 | base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; |
3011 | base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; | |
3012 | write_ptr = DBGC_CUR_DBGBUF_STATUS; | |
3013 | wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; | |
91c28b83 SM |
3014 | } else if (trans->dbg.dest_tlv) { |
3015 | write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); | |
3016 | wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); | |
3017 | base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); | |
7a14c23d SS |
3018 | } else { |
3019 | base = MON_BUFF_BASE_ADDR; | |
3020 | write_ptr = MON_BUFF_WRPTR; | |
3021 | wrap_cnt = MON_BUFF_CYCLE_CNT; | |
3022 | } | |
c88580e1 SM |
3023 | |
3024 | write_ptr_val = iwl_read_prph(trans, write_ptr); | |
7a14c23d SS |
3025 | fw_mon_data->fw_mon_cycle_cnt = |
3026 | cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); | |
3027 | fw_mon_data->fw_mon_base_ptr = | |
3028 | cpu_to_le32(iwl_read_prph(trans, base)); | |
79b6c8fe | 3029 | if (trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_AX210) { |
c88580e1 SM |
3030 | fw_mon_data->fw_mon_base_high_ptr = |
3031 | cpu_to_le32(iwl_read_prph(trans, base_high)); | |
3032 | write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; | |
3033 | } | |
3034 | fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); | |
7a14c23d SS |
3035 | } |
3036 | ||
36fb9017 OG |
3037 | static u32 |
3038 | iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, | |
3039 | struct iwl_fw_error_dump_data **data, | |
3040 | u32 monitor_len) | |
3041 | { | |
36fb9017 OG |
3042 | u32 len = 0; |
3043 | ||
91c28b83 SM |
3044 | if (trans->dbg.dest_tlv || |
3045 | (trans->dbg.num_blocks && | |
79b6c8fe LC |
3046 | (trans->cfg->trans.device_family == IWL_DEVICE_FAMILY_7000 || |
3047 | trans->cfg->trans.device_family >= IWL_DEVICE_FAMILY_AX210))) { | |
36fb9017 | 3048 | struct iwl_fw_error_dump_fw_mon *fw_mon_data; |
36fb9017 OG |
3049 | |
3050 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); | |
3051 | fw_mon_data = (void *)(*data)->data; | |
7a14c23d SS |
3052 | |
3053 | iwl_trans_pcie_dump_pointers(trans, fw_mon_data); | |
36fb9017 OG |
3054 | |
3055 | len += sizeof(**data) + sizeof(*fw_mon_data); | |
91c28b83 | 3056 | if (trans->dbg.num_blocks) { |
36fb9017 | 3057 | memcpy(fw_mon_data->data, |
91c28b83 SM |
3058 | trans->dbg.fw_mon[0].block, |
3059 | trans->dbg.fw_mon[0].size); | |
36fb9017 | 3060 | |
91c28b83 SM |
3061 | monitor_len = trans->dbg.fw_mon[0].size; |
3062 | } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { | |
7a14c23d | 3063 | u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); |
36fb9017 OG |
3064 | /* |
3065 | * Update pointers to reflect actual values after | |
3066 | * shifting | |
3067 | */ | |
91c28b83 | 3068 | if (trans->dbg.dest_tlv->version) { |
fd527eb5 GBA |
3069 | base = (iwl_read_prph(trans, base) & |
3070 | IWL_LDBG_M2S_BUF_BA_MSK) << | |
91c28b83 | 3071 | trans->dbg.dest_tlv->base_shift; |
fd527eb5 GBA |
3072 | base *= IWL_M2S_UNIT_SIZE; |
3073 | base += trans->cfg->smem_offset; | |
3074 | } else { | |
3075 | base = iwl_read_prph(trans, base) << | |
91c28b83 | 3076 | trans->dbg.dest_tlv->base_shift; |
fd527eb5 GBA |
3077 | } |
3078 | ||
36fb9017 OG |
3079 | iwl_trans_read_mem(trans, base, fw_mon_data->data, |
3080 | monitor_len / sizeof(u32)); | |
91c28b83 | 3081 | } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { |
36fb9017 OG |
3082 | monitor_len = |
3083 | iwl_trans_pci_dump_marbh_monitor(trans, | |
3084 | fw_mon_data, | |
3085 | monitor_len); | |
3086 | } else { | |
3087 | /* Didn't match anything - output no monitor data */ | |
3088 | monitor_len = 0; | |
3089 | } | |
3090 | ||
3091 | len += monitor_len; | |
3092 | (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); | |
3093 | } | |
3094 | ||
3095 | return len; | |
3096 | } | |
3097 | ||
93079fd5 | 3098 | static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) |
4d075007 | 3099 | { |
91c28b83 | 3100 | if (trans->dbg.num_blocks) { |
da752717 SM |
3101 | *len += sizeof(struct iwl_fw_error_dump_data) + |
3102 | sizeof(struct iwl_fw_error_dump_fw_mon) + | |
91c28b83 SM |
3103 | trans->dbg.fw_mon[0].size; |
3104 | return trans->dbg.fw_mon[0].size; | |
3105 | } else if (trans->dbg.dest_tlv) { | |
da752717 | 3106 | u32 base, end, cfg_reg, monitor_len; |
99684ae3 | 3107 | |
91c28b83 SM |
3108 | if (trans->dbg.dest_tlv->version == 1) { |
3109 | cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); | |
fd527eb5 GBA |
3110 | cfg_reg = iwl_read_prph(trans, cfg_reg); |
3111 | base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << | |
91c28b83 | 3112 | trans->dbg.dest_tlv->base_shift; |
fd527eb5 GBA |
3113 | base *= IWL_M2S_UNIT_SIZE; |
3114 | base += trans->cfg->smem_offset; | |
99684ae3 | 3115 | |
fd527eb5 GBA |
3116 | monitor_len = |
3117 | (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> | |
91c28b83 | 3118 | trans->dbg.dest_tlv->end_shift; |
fd527eb5 GBA |
3119 | monitor_len *= IWL_M2S_UNIT_SIZE; |
3120 | } else { | |
91c28b83 SM |
3121 | base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); |
3122 | end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); | |
99684ae3 | 3123 | |
fd527eb5 | 3124 | base = iwl_read_prph(trans, base) << |
91c28b83 | 3125 | trans->dbg.dest_tlv->base_shift; |
fd527eb5 | 3126 | end = iwl_read_prph(trans, end) << |
91c28b83 | 3127 | trans->dbg.dest_tlv->end_shift; |
fd527eb5 GBA |
3128 | |
3129 | /* Make "end" point to the actual end */ | |
79b6c8fe | 3130 | if (trans->cfg->trans.device_family >= |
fd527eb5 | 3131 | IWL_DEVICE_FAMILY_8000 || |
91c28b83 SM |
3132 | trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) |
3133 | end += (1 << trans->dbg.dest_tlv->end_shift); | |
fd527eb5 GBA |
3134 | monitor_len = end - base; |
3135 | } | |
da752717 SM |
3136 | *len += sizeof(struct iwl_fw_error_dump_data) + |
3137 | sizeof(struct iwl_fw_error_dump_fw_mon) + | |
3138 | monitor_len; | |
3139 | return monitor_len; | |
99684ae3 | 3140 | } |
da752717 SM |
3141 | return 0; |
3142 | } | |
3143 | ||
3144 | static struct iwl_trans_dump_data | |
3145 | *iwl_trans_pcie_dump_data(struct iwl_trans *trans, | |
79f033f6 | 3146 | u32 dump_mask) |
da752717 SM |
3147 | { |
3148 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
3149 | struct iwl_fw_error_dump_data *data; | |
3150 | struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; | |
3151 | struct iwl_fw_error_dump_txcmd *txcmd; | |
3152 | struct iwl_trans_dump_data *dump_data; | |
fefbf853 | 3153 | u32 len, num_rbs = 0, monitor_len = 0; |
da752717 SM |
3154 | int i, ptr; |
3155 | bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && | |
79b6c8fe | 3156 | !trans->cfg->trans.mq_rx_supported && |
79f033f6 SS |
3157 | dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); |
3158 | ||
3159 | if (!dump_mask) | |
3160 | return NULL; | |
da752717 SM |
3161 | |
3162 | /* transport dump header */ | |
3163 | len = sizeof(*dump_data); | |
3164 | ||
3165 | /* host commands */ | |
e4eee943 | 3166 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) |
8672aad3 SM |
3167 | len += sizeof(*data) + |
3168 | cmdq->n_window * (sizeof(*txcmd) + | |
3169 | TFD_MAX_PAYLOAD_SIZE); | |
da752717 SM |
3170 | |
3171 | /* FW monitor */ | |
fefbf853 SM |
3172 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) |
3173 | monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); | |
36fb9017 OG |
3174 | |
3175 | /* CSR registers */ | |
79f033f6 | 3176 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) |
520f03ea | 3177 | len += sizeof(*data) + IWL_CSR_TO_DUMP; |
36fb9017 | 3178 | |
36fb9017 | 3179 | /* FH registers */ |
79f033f6 | 3180 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { |
79b6c8fe | 3181 | if (trans->cfg->trans.gen2) |
520f03ea | 3182 | len += sizeof(*data) + |
ea695b7c ST |
3183 | (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - |
3184 | iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); | |
520f03ea SM |
3185 | else |
3186 | len += sizeof(*data) + | |
3187 | (FH_MEM_UPPER_BOUND - | |
3188 | FH_MEM_LOWER_BOUND); | |
3189 | } | |
36fb9017 OG |
3190 | |
3191 | if (dump_rbs) { | |
78485054 SS |
3192 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
3193 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; | |
36fb9017 | 3194 | /* RBs */ |
0307c839 GBA |
3195 | num_rbs = |
3196 | le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) | |
3197 | & 0x0FFF; | |
78485054 | 3198 | num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; |
36fb9017 OG |
3199 | len += num_rbs * (sizeof(*data) + |
3200 | sizeof(struct iwl_fw_error_dump_rb) + | |
3201 | (PAGE_SIZE << trans_pcie->rx_page_order)); | |
3202 | } | |
3203 | ||
5538409b | 3204 | /* Paged memory for gen2 HW */ |
79b6c8fe | 3205 | if (trans->cfg->trans.gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) |
505a00c0 | 3206 | for (i = 0; i < trans->init_dram.paging_cnt; i++) |
5538409b LK |
3207 | len += sizeof(*data) + |
3208 | sizeof(struct iwl_fw_error_dump_paging) + | |
505a00c0 | 3209 | trans->init_dram.paging[i].size; |
5538409b | 3210 | |
48eb7b34 EG |
3211 | dump_data = vzalloc(len); |
3212 | if (!dump_data) | |
3213 | return NULL; | |
4d075007 JB |
3214 | |
3215 | len = 0; | |
48eb7b34 | 3216 | data = (void *)dump_data->data; |
520f03ea | 3217 | |
e4eee943 | 3218 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { |
520f03ea SM |
3219 | u16 tfd_size = trans_pcie->tfd_size; |
3220 | ||
3221 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); | |
3222 | txcmd = (void *)data->data; | |
3223 | spin_lock_bh(&cmdq->lock); | |
3224 | ptr = cmdq->write_ptr; | |
3225 | for (i = 0; i < cmdq->n_window; i++) { | |
3226 | u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); | |
3227 | u32 caplen, cmdlen; | |
3228 | ||
3229 | cmdlen = iwl_trans_pcie_get_cmdlen(trans, | |
3230 | cmdq->tfds + | |
3231 | tfd_size * ptr); | |
3232 | caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); | |
3233 | ||
3234 | if (cmdlen) { | |
3235 | len += sizeof(*txcmd) + caplen; | |
3236 | txcmd->cmdlen = cpu_to_le32(cmdlen); | |
3237 | txcmd->caplen = cpu_to_le32(caplen); | |
3238 | memcpy(txcmd->data, cmdq->entries[idx].cmd, | |
3239 | caplen); | |
3240 | txcmd = (void *)((u8 *)txcmd->data + caplen); | |
3241 | } | |
3242 | ||
3243 | ptr = iwl_queue_dec_wrap(trans, ptr); | |
4d075007 | 3244 | } |
520f03ea | 3245 | spin_unlock_bh(&cmdq->lock); |
4d075007 | 3246 | |
520f03ea SM |
3247 | data->len = cpu_to_le32(len); |
3248 | len += sizeof(*data); | |
3249 | data = iwl_fw_error_next_data(data); | |
4d075007 | 3250 | } |
67c65f2c | 3251 | |
79f033f6 | 3252 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) |
520f03ea | 3253 | len += iwl_trans_pcie_dump_csr(trans, &data); |
79f033f6 | 3254 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) |
520f03ea | 3255 | len += iwl_trans_pcie_fh_regs_dump(trans, &data); |
bd7fc617 EG |
3256 | if (dump_rbs) |
3257 | len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); | |
c2d20201 | 3258 | |
5538409b | 3259 | /* Paged memory for gen2 HW */ |
79b6c8fe LC |
3260 | if (trans->cfg->trans.gen2 && |
3261 | dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { | |
505a00c0 | 3262 | for (i = 0; i < trans->init_dram.paging_cnt; i++) { |
5538409b | 3263 | struct iwl_fw_error_dump_paging *paging; |
505a00c0 | 3264 | u32 page_len = trans->init_dram.paging[i].size; |
5538409b LK |
3265 | |
3266 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); | |
3267 | data->len = cpu_to_le32(sizeof(*paging) + page_len); | |
3268 | paging = (void *)data->data; | |
3269 | paging->index = cpu_to_le32(i); | |
5538409b | 3270 | memcpy(paging->data, |
505a00c0 | 3271 | trans->init_dram.paging[i].block, page_len); |
5538409b LK |
3272 | data = iwl_fw_error_next_data(data); |
3273 | ||
3274 | len += sizeof(*data) + sizeof(*paging) + page_len; | |
3275 | } | |
3276 | } | |
79f033f6 | 3277 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) |
520f03ea | 3278 | len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); |
c2d20201 | 3279 | |
48eb7b34 EG |
3280 | dump_data->len = len; |
3281 | ||
3282 | return dump_data; | |
4d075007 | 3283 | } |
87e5666c | 3284 | |
4cbb8e50 LC |
3285 | #ifdef CONFIG_PM_SLEEP |
3286 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) | |
3287 | { | |
4cbb8e50 LC |
3288 | return 0; |
3289 | } | |
3290 | ||
3291 | static void iwl_trans_pcie_resume(struct iwl_trans *trans) | |
3292 | { | |
4cbb8e50 LC |
3293 | } |
3294 | #endif /* CONFIG_PM_SLEEP */ | |
3295 | ||
623e7766 SS |
3296 | #define IWL_TRANS_COMMON_OPS \ |
3297 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ | |
3298 | .write8 = iwl_trans_pcie_write8, \ | |
3299 | .write32 = iwl_trans_pcie_write32, \ | |
3300 | .read32 = iwl_trans_pcie_read32, \ | |
3301 | .read_prph = iwl_trans_pcie_read_prph, \ | |
3302 | .write_prph = iwl_trans_pcie_write_prph, \ | |
3303 | .read_mem = iwl_trans_pcie_read_mem, \ | |
3304 | .write_mem = iwl_trans_pcie_write_mem, \ | |
3305 | .configure = iwl_trans_pcie_configure, \ | |
3306 | .set_pmi = iwl_trans_pcie_set_pmi, \ | |
870c2a11 | 3307 | .sw_reset = iwl_trans_pcie_sw_reset, \ |
623e7766 SS |
3308 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ |
3309 | .release_nic_access = iwl_trans_pcie_release_nic_access, \ | |
3310 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ | |
623e7766 | 3311 | .dump_data = iwl_trans_pcie_dump_data, \ |
623e7766 | 3312 | .d3_suspend = iwl_trans_pcie_d3_suspend, \ |
d1967ce6 SM |
3313 | .d3_resume = iwl_trans_pcie_d3_resume, \ |
3314 | .sync_nmi = iwl_trans_pcie_sync_nmi | |
623e7766 SS |
3315 | |
3316 | #ifdef CONFIG_PM_SLEEP | |
3317 | #define IWL_TRANS_PM_OPS \ | |
3318 | .suspend = iwl_trans_pcie_suspend, \ | |
3319 | .resume = iwl_trans_pcie_resume, | |
3320 | #else | |
3321 | #define IWL_TRANS_PM_OPS | |
3322 | #endif /* CONFIG_PM_SLEEP */ | |
3323 | ||
d1ff5253 | 3324 | static const struct iwl_trans_ops trans_ops_pcie = { |
623e7766 SS |
3325 | IWL_TRANS_COMMON_OPS, |
3326 | IWL_TRANS_PM_OPS | |
57a1dc89 | 3327 | .start_hw = iwl_trans_pcie_start_hw, |
ed6a3803 | 3328 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 3329 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 3330 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 3331 | |
623e7766 | 3332 | .send_cmd = iwl_trans_pcie_send_hcmd, |
2dd4f9f7 | 3333 | |
623e7766 SS |
3334 | .tx = iwl_trans_pcie_tx, |
3335 | .reclaim = iwl_trans_pcie_reclaim, | |
3336 | ||
3337 | .txq_disable = iwl_trans_pcie_txq_disable, | |
3338 | .txq_enable = iwl_trans_pcie_txq_enable, | |
3339 | ||
3340 | .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, | |
3341 | ||
d6d517b7 SS |
3342 | .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, |
3343 | ||
623e7766 SS |
3344 | .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, |
3345 | .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, | |
f7805b33 LC |
3346 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3347 | .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, | |
3348 | #endif | |
623e7766 SS |
3349 | }; |
3350 | ||
3351 | static const struct iwl_trans_ops trans_ops_pcie_gen2 = { | |
3352 | IWL_TRANS_COMMON_OPS, | |
3353 | IWL_TRANS_PM_OPS | |
3354 | .start_hw = iwl_trans_pcie_start_hw, | |
eda50cde SS |
3355 | .fw_alive = iwl_trans_pcie_gen2_fw_alive, |
3356 | .start_fw = iwl_trans_pcie_gen2_start_fw, | |
77c09bc8 | 3357 | .stop_device = iwl_trans_pcie_gen2_stop_device, |
4cbb8e50 | 3358 | |
ca60da2e | 3359 | .send_cmd = iwl_trans_pcie_gen2_send_hcmd, |
c85eb619 | 3360 | |
ab6c6445 | 3361 | .tx = iwl_trans_pcie_gen2_tx, |
a0eaad71 | 3362 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 3363 | |
ba7136f3 AM |
3364 | .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, |
3365 | ||
6b35ff91 SS |
3366 | .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, |
3367 | .txq_free = iwl_trans_pcie_dyn_txq_free, | |
d6d517b7 | 3368 | .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, |
92536c96 | 3369 | .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, |
f7805b33 LC |
3370 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3371 | .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, | |
3372 | #endif | |
e6bb4c9c | 3373 | }; |
a42a1844 | 3374 | |
87ce05a2 | 3375 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
7e8258c0 LC |
3376 | const struct pci_device_id *ent, |
3377 | const struct iwl_cfg_trans_params *cfg_trans) | |
a42a1844 | 3378 | { |
a42a1844 EG |
3379 | struct iwl_trans_pcie *trans_pcie; |
3380 | struct iwl_trans *trans; | |
96a6497b | 3381 | int ret, addr_size; |
a42a1844 | 3382 | |
5a41a86c SD |
3383 | ret = pcim_enable_device(pdev); |
3384 | if (ret) | |
3385 | return ERR_PTR(ret); | |
3386 | ||
7e8258c0 | 3387 | if (cfg_trans->gen2) |
623e7766 | 3388 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), |
0c18714a | 3389 | &pdev->dev, &trans_ops_pcie_gen2); |
623e7766 SS |
3390 | else |
3391 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), | |
0c18714a LC |
3392 | &pdev->dev, &trans_ops_pcie); |
3393 | ||
7b501d10 JB |
3394 | if (!trans) |
3395 | return ERR_PTR(-ENOMEM); | |
a42a1844 EG |
3396 | |
3397 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
3398 | ||
a42a1844 | 3399 | trans_pcie->trans = trans; |
326477e4 | 3400 | trans_pcie->opmode_down = true; |
7b11488f | 3401 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 3402 | spin_lock_init(&trans_pcie->reg_lock); |
fa9f3281 | 3403 | mutex_init(&trans_pcie->mutex); |
13df1aab | 3404 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
6eb5e529 EG |
3405 | trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); |
3406 | if (!trans_pcie->tso_hdr_page) { | |
3407 | ret = -ENOMEM; | |
3408 | goto out_no_pci; | |
3409 | } | |
c5bf4fa1 | 3410 | trans_pcie->debug_rfkill = -1; |
d819c6cf | 3411 | |
7e8258c0 | 3412 | if (!cfg_trans->base_params->pcie_l1_allowed) { |
f2532b04 EG |
3413 | /* |
3414 | * W/A - seems to solve weird behavior. We need to remove this | |
3415 | * if we don't want to stay in L1 all the time. This wastes a | |
3416 | * lot of power. | |
3417 | */ | |
3418 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
3419 | PCIE_LINK_STATE_L1 | | |
3420 | PCIE_LINK_STATE_CLKPM); | |
3421 | } | |
a42a1844 | 3422 | |
9416560e GBA |
3423 | trans_pcie->def_rx_queue = 0; |
3424 | ||
7e8258c0 | 3425 | if (cfg_trans->use_tfh) { |
2c6262b7 | 3426 | addr_size = 64; |
3cd1980b | 3427 | trans_pcie->max_tbs = IWL_TFH_NUM_TBS; |
8352e62a | 3428 | trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); |
6983ba69 | 3429 | } else { |
2c6262b7 | 3430 | addr_size = 36; |
3cd1980b | 3431 | trans_pcie->max_tbs = IWL_NUM_OF_TBS; |
6983ba69 SS |
3432 | trans_pcie->tfd_size = sizeof(struct iwl_tfd); |
3433 | } | |
3cd1980b SS |
3434 | trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); |
3435 | ||
a42a1844 EG |
3436 | pci_set_master(pdev); |
3437 | ||
96a6497b | 3438 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); |
af3f2f74 | 3439 | if (!ret) |
96a6497b SS |
3440 | ret = pci_set_consistent_dma_mask(pdev, |
3441 | DMA_BIT_MASK(addr_size)); | |
af3f2f74 EG |
3442 | if (ret) { |
3443 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
3444 | if (!ret) | |
3445 | ret = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 3446 | DMA_BIT_MASK(32)); |
a42a1844 | 3447 | /* both attempts failed: */ |
af3f2f74 | 3448 | if (ret) { |
6a4b09f8 | 3449 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
5a41a86c | 3450 | goto out_no_pci; |
a42a1844 EG |
3451 | } |
3452 | } | |
3453 | ||
5a41a86c | 3454 | ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); |
af3f2f74 | 3455 | if (ret) { |
5a41a86c SD |
3456 | dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); |
3457 | goto out_no_pci; | |
a42a1844 EG |
3458 | } |
3459 | ||
5a41a86c | 3460 | trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; |
a42a1844 | 3461 | if (!trans_pcie->hw_base) { |
5a41a86c | 3462 | dev_err(&pdev->dev, "pcim_iomap_table failed\n"); |
af3f2f74 | 3463 | ret = -ENODEV; |
5a41a86c | 3464 | goto out_no_pci; |
a42a1844 EG |
3465 | } |
3466 | ||
a42a1844 EG |
3467 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3468 | * PCI Tx retries from interfering with C3 CPU state */ | |
3469 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3470 | ||
83f7a85f EG |
3471 | trans_pcie->pci_dev = pdev; |
3472 | iwl_disable_interrupts(trans); | |
3473 | ||
08079a49 | 3474 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
9a098a89 RJ |
3475 | if (trans->hw_rev == 0xffffffff) { |
3476 | dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); | |
3477 | ret = -EIO; | |
3478 | goto out_no_pci; | |
3479 | } | |
3480 | ||
b513ee7f LK |
3481 | /* |
3482 | * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have | |
3483 | * changed, and now the revision step also includes bit 0-1 (no more | |
3484 | * "dash" value). To keep hw_rev backwards compatible - we'll store it | |
3485 | * in the old format. | |
3486 | */ | |
7e8258c0 | 3487 | if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) { |
b513ee7f | 3488 | trans->hw_rev = (trans->hw_rev & 0xfff0) | |
1fc0e221 | 3489 | (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); |
b513ee7f | 3490 | |
f9e5554c EG |
3491 | ret = iwl_pcie_prepare_card_hw(trans); |
3492 | if (ret) { | |
3493 | IWL_WARN(trans, "Exit HW not ready\n"); | |
5a41a86c | 3494 | goto out_no_pci; |
f9e5554c EG |
3495 | } |
3496 | ||
7a42baa6 EH |
3497 | /* |
3498 | * in-order to recognize C step driver should read chip version | |
3499 | * id located at the AUX bus MISC address space. | |
3500 | */ | |
7e8258c0 | 3501 | ret = iwl_finish_nic_init(trans, cfg_trans); |
c96b5eec | 3502 | if (ret) |
5a41a86c | 3503 | goto out_no_pci; |
7a42baa6 | 3504 | |
7a42baa6 EH |
3505 | } |
3506 | ||
99be6166 LC |
3507 | IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); |
3508 | ||
7e8258c0 | 3509 | iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); |
99673ee5 | 3510 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
3511 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
3512 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 3513 | |
69a10b29 | 3514 | /* Initialize the wait queue for commands */ |
f946b529 | 3515 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 3516 | |
2e5d4a8f | 3517 | if (trans_pcie->msix_enabled) { |
2388bd7b DC |
3518 | ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); |
3519 | if (ret) | |
5a41a86c | 3520 | goto out_no_pci; |
2e5d4a8f HD |
3521 | } else { |
3522 | ret = iwl_pcie_alloc_ict(trans); | |
3523 | if (ret) | |
5a41a86c | 3524 | goto out_no_pci; |
a8b691e6 | 3525 | |
5a41a86c SD |
3526 | ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, |
3527 | iwl_pcie_isr, | |
3528 | iwl_pcie_irq_handler, | |
3529 | IRQF_SHARED, DRV_NAME, trans); | |
2e5d4a8f HD |
3530 | if (ret) { |
3531 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); | |
3532 | goto out_free_ict; | |
3533 | } | |
3534 | trans_pcie->inta_mask = CSR_INI_SET_MASK; | |
3535 | } | |
83f7a85f | 3536 | |
10a54d81 LC |
3537 | trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", |
3538 | WQ_HIGHPRI | WQ_UNBOUND, 1); | |
3539 | INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); | |
3540 | ||
f7805b33 LC |
3541 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3542 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; | |
3543 | mutex_init(&trans_pcie->fw_mon_data.mutex); | |
3544 | #endif | |
3545 | ||
a42a1844 EG |
3546 | return trans; |
3547 | ||
a8b691e6 JB |
3548 | out_free_ict: |
3549 | iwl_pcie_free_ict(trans); | |
a42a1844 | 3550 | out_no_pci: |
6eb5e529 | 3551 | free_percpu(trans_pcie->tso_hdr_page); |
7b501d10 | 3552 | iwl_trans_free(trans); |
af3f2f74 | 3553 | return ERR_PTR(ret); |
a42a1844 | 3554 | } |
b8a7547d | 3555 | |
d1967ce6 | 3556 | void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) |
b8a7547d | 3557 | { |
1c6bca6d | 3558 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b8a7547d | 3559 | unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; |
e4eee943 | 3560 | bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); |
1c6bca6d SM |
3561 | u32 inta_addr, sw_err_bit; |
3562 | ||
3563 | if (trans_pcie->msix_enabled) { | |
3564 | inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; | |
3565 | sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; | |
3566 | } else { | |
3567 | inta_addr = CSR_INT; | |
3568 | sw_err_bit = CSR_INT_BIT_SW_ERR; | |
3569 | } | |
b8a7547d | 3570 | |
e4eee943 SM |
3571 | /* if the interrupts were already disabled, there is no point in |
3572 | * calling iwl_disable_interrupts | |
3573 | */ | |
3574 | if (interrupts_enabled) | |
3575 | iwl_disable_interrupts(trans); | |
3576 | ||
b8a7547d SM |
3577 | iwl_force_nmi(trans); |
3578 | while (time_after(timeout, jiffies)) { | |
1c6bca6d | 3579 | u32 inta_hw = iwl_read32(trans, inta_addr); |
b8a7547d SM |
3580 | |
3581 | /* Error detected by uCode */ | |
1c6bca6d | 3582 | if (inta_hw & sw_err_bit) { |
b8a7547d | 3583 | /* Clear causes register */ |
1c6bca6d | 3584 | iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); |
b8a7547d SM |
3585 | break; |
3586 | } | |
3587 | ||
3588 | mdelay(1); | |
3589 | } | |
e4eee943 SM |
3590 | |
3591 | /* enable interrupts only if there were already enabled before this | |
3592 | * function to avoid a case were the driver enable interrupts before | |
3593 | * proper configurations were made | |
3594 | */ | |
3595 | if (interrupts_enabled) | |
3596 | iwl_enable_interrupts(trans); | |
3597 | ||
b8a7547d SM |
3598 | iwl_trans_fw_error(trans); |
3599 | } |