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iwlwifi: pcie: move msix conf functions above other functions
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 10 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 37 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
4d075007 83#include "iwl-fw-error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
c2d20201
EG		 91static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92{
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105}
106
96c285da 107static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 108{
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 110 struct page *page = NULL;
c2d20201 111 dma_addr_t phys;
96c285da 112 u32 size = 0;
c2d20201
EG		 113 u8 power;
114
96c285da
EG		 115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
c2d20201
EG		 127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
96c285da 135 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
553452e5 149 page = NULL;
c2d20201
EG		 150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
40a76905 158 if (WARN_ON_ONCE(!page))
c2d20201
EG		 159 return;
160
96c285da
EG		 161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
c2d20201
EG		 167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170}
171
a812cba9
AB		 172static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173{
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177}
178
179static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180{
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184}
185
ddaf5a5b 186static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 187{
66337b7c 188 if (trans->cfg->apmg_not_supported)
95411d04
AA		 189 return;
190
ddaf5a5b
JB		 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 199}
200
af634bee
EG		 201/* PCI registers */
202#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 203
7afe3705 204static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 205{
20d3b647 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 207 u16 lctl;
9180ac50 208 u16 cap;
af634bee 209
af634bee
EG		 210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
7afe3705 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 221 else
af634bee 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 230}
231
a6c684ee
EG		 232/*
233 * Start up NIC's basic functionality after it has been reset
7afe3705 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 235 * NOTE: This does not load uCode nor start the embedded processor
236 */
7afe3705 237static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 238{
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 268
7afe3705 269 iwl_pcie_apm_config(trans);
a6c684ee
EG		 270
271 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 363 usleep_range(1000, 2000);
a812cba9
AB		 364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 409 usleep_range(1000, 2000);
a812cba9
AB		 410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
b7aaeae4
EG		 491 mdelay(5);
492 }
493
eb7ff77e 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 495
496 /* Stop device's DMA activity */
7afe3705 497 iwl_pcie_apm_stop_master(trans);
cc56feb2 498
a812cba9
AB		 499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
cc56feb2
EG		 504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 506 usleep_range(1000, 2000);
cc56feb2
EG		 507
508 /*
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
511 */
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
514}
515
7afe3705 516static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 517{
7b11488f 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 519
520 /* nic_init */
7b70bd63 521 spin_lock(&trans_pcie->irq_lock);
7afe3705 522 iwl_pcie_apm_init(trans);
392f8b78 523
7b70bd63 524 spin_unlock(&trans_pcie->irq_lock);
392f8b78 525
95411d04 526 iwl_pcie_set_pwr(trans, false);
392f8b78 527
ecdb975c 528 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 529
530 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 531 iwl_pcie_rx_init(trans);
392f8b78
EG		 532
533 /* Allocate or reset and init all Tx and Command queues */
f02831be 534 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 535 return -ENOMEM;
536
035f7ff2 537 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 538 /* enable shadow regs in HW */
20d3b647 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 541 }
542
392f8b78
EG		 543 return 0;
544}
545
546#define HW_READY_TIMEOUT (50)
547
548/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 549static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 550{
551 int ret;
552
1042db2a 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 555
556 /* See if we got it */
1042db2a 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 HW_READY_TIMEOUT);
392f8b78 561
6a08f514
EG		 562 if (ret >= 0)
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
564
6d8f6eeb 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 566 return ret;
567}
568
569/* Note: returns standard 0/-ERROR code */
7afe3705 570static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 571{
572 int ret;
289e5501 573 int t = 0;
501fd989 574 int iter;
392f8b78 575
6d8f6eeb 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 577
7afe3705 578 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 579 /* If the card is ready, exit 0 */
392f8b78
EG		 580 if (ret >= 0)
581 return 0;
582
c9fdec9f
EG		 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 585 usleep_range(1000, 2000);
c9fdec9f 586
501fd989
EG		 587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
591
592 do {
593 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 594 if (ret >= 0)
595 return 0;
392f8b78 596
501fd989
EG		 597 usleep_range(200, 1000);
598 t += 200;
599 } while (t < 150000);
600 msleep(25);
601 }
392f8b78 602
7f2ac8fb 603 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 604
392f8b78
EG		 605 return ret;
606}
607
cf614297
EG		 608/*
609 * ucode
610 */
564cdce7
SS		 611static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
613 u32 byte_cnt)
cf614297 614{
bac842da
EG		 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
617
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
619 dst_addr);
620
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
623
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 637}
638
639static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
641 u32 byte_cnt)
642{
643 /* Stop DMA channel */
644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0);
645
646 /* Configure SRAM address */
647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR,
648 dst_addr);
649
650 /* Configure DRAM address - 64 bit */
651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr);
bac842da 652
564cdce7
SS		 653 /* Configure byte count to transfer */
654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt);
655
656 /* Enable the DRAM2SRAM to start */
657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP |
658 TFH_SRV_DMA_TO_DRIVER |
659 TFH_SRV_DMA_START);
660}
661
662static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
663 u32 dst_addr, dma_addr_t phy_addr,
664 u32 byte_cnt)
665{
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
667 unsigned long flags;
668 int ret;
669
670 trans_pcie->ucode_write_complete = false;
671
672 if (!iwl_trans_grab_nic_access(trans, &flags))
673 return -EIO;
674
675 if (trans->cfg->use_tfh)
676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr,
677 byte_cnt);
678 else
679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
680 byte_cnt);
bac842da 681 iwl_trans_release_nic_access(trans, &flags);
cf614297 682
13df1aab
JB		 683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
684 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 685 if (!ret) {
83f84d7b 686 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 687 return -ETIMEDOUT;
688 }
689
690 return 0;
691}
692
7afe3705 693static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 694 const struct fw_desc *section)
cf614297 695{
83f84d7b
JB		 696 u8 *v_addr;
697 dma_addr_t p_addr;
baa21e83 698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 699 int ret = 0;
700
83f84d7b
JB		 701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
702 section_num);
703
c571573a
EG		 704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
705 GFP_KERNEL | __GFP_NOWARN);
706 if (!v_addr) {
707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
708 chunk_sz = PAGE_SIZE;
709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
710 &p_addr, GFP_KERNEL);
711 if (!v_addr)
712 return -ENOMEM;
713 }
83f84d7b 714
c571573a 715 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 716 u32 copy_size, dst_addr;
717 bool extended_addr = false;
83f84d7b 718
c571573a 719 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 720 dst_addr = section->offset + offset;
721
722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
723 dst_addr <= IWL_FW_MEM_EXTENDED_END)
724 extended_addr = true;
725
726 if (extended_addr)
727 iwl_set_bits_prph(trans, LMPM_CHICK,
728 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 729
83f84d7b 730 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
732 copy_size);
733
734 if (extended_addr)
735 iwl_clear_bits_prph(trans, LMPM_CHICK,
736 LMPM_CHICK_EXTENDED_ADDR_SPACE);
737
83f84d7b
JB		 738 if (ret) {
739 IWL_ERR(trans,
740 "Could not load the [%d] uCode section\n",
741 section_num);
742 break;
6dfa8d01 743 }
83f84d7b
JB		 744 }
745
c571573a 746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 747 return ret;
748}
749
16bc119b
EH		 750/*
751 * Driver Takes the ownership on secure machine before FW load
752 * and prevent race with the BT load.
753 * W/A for ROM bug. (should be remove in the next Si step)
754 */
755static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
756{
757 u32 val, loop = 1000;
758
1e167071
EH		 759 /*
760 * Check the RSA semaphore is accessible.
761 * If the HW isn't locked and the rsa semaphore isn't accessible,
762 * we are in trouble.
763 */
16bc119b
EH		 764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
765 if (val & (BIT(1) | BIT(17))) {
9fc515bc
EG		 766 IWL_DEBUG_INFO(trans,
767 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 768 return 0;
769 }
770
771 /* take ownership on the AUX IF */
772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
774
775 do {
776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
778 if (val == 0x1) {
779 iwl_write_prph(trans, RSA_ENABLE, 0);
780 return 0;
781 }
782
783 udelay(10);
784 loop--;
785 } while (loop > 0);
786
787 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
788 return -EIO;
789}
790
5dd9c68a
EG		 791static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
792 const struct fw_img *image,
793 int cpu,
794 int *first_ucode_section)
e2d6f4e7
EH		 795{
796 int shift_param;
dcab8ecd
EH		 797 int i, ret = 0, sec_num = 0x1;
798 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 799
800 if (cpu == 1) {
801 shift_param = 0;
034846cf 802 *first_ucode_section = 0;
e2d6f4e7
EH		 803 } else {
804 shift_param = 16;
034846cf 805 (*first_ucode_section)++;
e2d6f4e7
EH		 806 }
807
eef187a7 808 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 809 last_read_idx = i;
810
a6c4fb44
MG		 811 /*
812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
813 * CPU1 to CPU2.
814 * PAGING_SEPARATOR_SECTION delimiter - separate between
815 * CPU2 non paged to CPU2 paging sec.
816 */
034846cf 817 if (!image->sec[i].data ||
a6c4fb44
MG		 818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 820 IWL_DEBUG_FW(trans,
821 "Break since Data not valid or Empty section, sec = %d\n",
822 i);
189fa2fa 823 break;
034846cf
EH		 824 }
825
189fa2fa
EH		 826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
827 if (ret)
828 return ret;
dcab8ecd 829
d6a2c5c7
SS		 830 /* Notify ucode of loaded section number and status */
831 if (trans->cfg->use_tfh) {
832 val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS);
833 val = val | (sec_num << shift_param);
834 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val);
835 } else {
836 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
837 val = val | (sec_num << shift_param);
838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
839 }
dcab8ecd 840 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 841 }
842
034846cf
EH		 843 *first_ucode_section = last_read_idx;
844
2aabdbdc
EG		 845 iwl_enable_interrupts(trans);
846
d6a2c5c7
SS		 847 if (trans->cfg->use_tfh) {
848 if (cpu == 1)
849 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
850 0xFFFF);
851 else
852 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
853 0xFFFFFFFF);
854 } else {
855 if (cpu == 1)
856 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
857 0xFFFF);
858 else
859 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
860 0xFFFFFFFF);
861 }
afb88917 862
189fa2fa
EH		 863 return 0;
864}
e2d6f4e7 865
189fa2fa
EH		 866static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
867 const struct fw_img *image,
034846cf
EH		 868 int cpu,
869 int *first_ucode_section)
189fa2fa 870{
189fa2fa 871 int i, ret = 0;
034846cf 872 u32 last_read_idx = 0;
189fa2fa 873
3ce4a038 874 if (cpu == 1)
034846cf 875 *first_ucode_section = 0;
3ce4a038 876 else
034846cf 877 (*first_ucode_section)++;
189fa2fa 878
eef187a7 879 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 880 last_read_idx = i;
881
a6c4fb44
MG		 882 /*
883 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
884 * CPU1 to CPU2.
885 * PAGING_SEPARATOR_SECTION delimiter - separate between
886 * CPU2 non paged to CPU2 paging sec.
887 */
034846cf 888 if (!image->sec[i].data ||
a6c4fb44
MG		 889 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
890 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 891 IWL_DEBUG_FW(trans,
892 "Break since Data not valid or Empty section, sec = %d\n",
893 i);
189fa2fa 894 break;
034846cf
EH		 895 }
896
189fa2fa
EH		 897 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
898 if (ret)
899 return ret;
e2d6f4e7
EH		 900 }
901
034846cf
EH		 902 *first_ucode_section = last_read_idx;
903
e2d6f4e7
EH		 904 return 0;
905}
906
09e350f7
LK		 907static void iwl_pcie_apply_destination(struct iwl_trans *trans)
908{
909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
910 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
911 int i;
912
913 if (dest->version)
914 IWL_ERR(trans,
915 "DBG DEST version is %d - expect issues\n",
916 dest->version);
917
918 IWL_INFO(trans, "Applying debug destination %s\n",
919 get_fw_dbg_mode_string(dest->monitor_mode));
920
921 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 922 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 923 else
924 IWL_WARN(trans, "PCI should have external buffer debug\n");
925
926 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
927 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
928 u32 val = le32_to_cpu(dest->reg_ops[i].val);
929
930 switch (dest->reg_ops[i].op) {
931 case CSR_ASSIGN:
932 iwl_write32(trans, addr, val);
933 break;
934 case CSR_SETBIT:
935 iwl_set_bit(trans, addr, BIT(val));
936 break;
937 case CSR_CLEARBIT:
938 iwl_clear_bit(trans, addr, BIT(val));
939 break;
940 case PRPH_ASSIGN:
941 iwl_write_prph(trans, addr, val);
942 break;
943 case PRPH_SETBIT:
944 iwl_set_bits_prph(trans, addr, BIT(val));
945 break;
946 case PRPH_CLEARBIT:
947 iwl_clear_bits_prph(trans, addr, BIT(val));
948 break;
869f3b15
HD		 949 case PRPH_BLOCKBIT:
950 if (iwl_read_prph(trans, addr) & BIT(val)) {
951 IWL_ERR(trans,
952 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
953 val, addr);
954 goto monitor;
955 }
956 break;
09e350f7
LK		 957 default:
958 IWL_ERR(trans, "FW debug - unknown OP %d\n",
959 dest->reg_ops[i].op);
960 break;
961 }
962 }
963
869f3b15 964monitor:
09e350f7
LK		 965 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
966 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
967 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 968 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
970 (trans_pcie->fw_mon_phys +
971 trans_pcie->fw_mon_size - 256) >>
972 dest->end_shift);
973 else
974 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
975 (trans_pcie->fw_mon_phys +
976 trans_pcie->fw_mon_size) >>
977 dest->end_shift);
09e350f7
LK		 978 }
979}
980
7afe3705 981static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 982 const struct fw_img *image)
cf614297 983{
c2d20201 984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 985 int ret = 0;
034846cf 986 int first_ucode_section;
cf614297 987
dcab8ecd 988 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 989 image->is_dual_cpus ? "Dual" : "Single");
990
dcab8ecd
EH		 991 /* load to FW the binary non secured sections of CPU1 */
992 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
993 if (ret)
994 return ret;
e2d6f4e7
EH		 995
996 if (image->is_dual_cpus) {
189fa2fa
EH		 997 /* set CPU2 header address */
998 iwl_write_prph(trans,
999 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1000 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1001
189fa2fa 1002 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1003 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1004 &first_ucode_section);
189fa2fa
EH		 1005 if (ret)
1006 return ret;
e2d6f4e7 1007 }
cf614297 1008
c2d20201
EG		 1009 /* supported for 7000 only for the moment */
1010 if (iwlwifi_mod_params.fw_monitor &&
1011 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1012 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1013
1014 if (trans_pcie->fw_mon_size) {
1015 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1016 trans_pcie->fw_mon_phys >> 4);
1017 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1018 (trans_pcie->fw_mon_phys +
1019 trans_pcie->fw_mon_size) >> 4);
1020 }
09e350f7
LK		 1021 } else if (trans->dbg_dest_tlv) {
1022 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1023 }
1024
2aabdbdc
EG		 1025 iwl_enable_interrupts(trans);
1026
e12ba844 1027 /* release CPU reset */
5dd9c68a 1028 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1029
dcab8ecd
EH		 1030 return 0;
1031}
189fa2fa 1032
5dd9c68a
EG		 1033static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1034 const struct fw_img *image)
dcab8ecd
EH		 1035{
1036 int ret = 0;
1037 int first_ucode_section;
dcab8ecd
EH		 1038
1039 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1040 image->is_dual_cpus ? "Dual" : "Single");
1041
a2227ce2
EG		 1042 if (trans->dbg_dest_tlv)
1043 iwl_pcie_apply_destination(trans);
1044
16bc119b
EH		 1045 /* TODO: remove in the next Si step */
1046 ret = iwl_pcie_rsa_race_bug_wa(trans);
1047 if (ret)
1048 return ret;
1049
dcab8ecd
EH		 1050 /* configure the ucode to be ready to get the secured image */
1051 /* release CPU reset */
1052 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1053
1054 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1055 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1056 &first_ucode_section);
dcab8ecd
EH		 1057 if (ret)
1058 return ret;
1059
1060 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1061 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1062 &first_ucode_section);
cf614297
EG		 1063}
1064
727c02df
SS		 1065static bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans)
1066{
1067 bool hw_rfkill = iwl_is_rfkill_set(trans);
1068
1069 if (hw_rfkill)
1070 set_bit(STATUS_RFKILL, &trans->status);
1071 else
1072 clear_bit(STATUS_RFKILL, &trans->status);
1073
1074 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1075
1076 return hw_rfkill;
1077}
1078
7ca00409
HD		 1079struct iwl_causes_list {
1080 u32 cause_num;
1081 u32 mask_reg;
1082 u8 addr;
1083};
1084
1085static struct iwl_causes_list causes_list[] = {
1086 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1087 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1088 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1089 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1090 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1091 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1092 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1093 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1094 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1095 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1096 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1097 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1098 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1099 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1100};
1101
1102static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1103{
1104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1105 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1106 int i;
1107
1108 /*
1109 * Access all non RX causes and map them to the default irq.
1110 * In case we are missing at least one interrupt vector,
1111 * the first interrupt vector will serve non-RX and FBQ causes.
1112 */
1113 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1114 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1115 iwl_clear_bit(trans, causes_list[i].mask_reg,
1116 causes_list[i].cause_num);
1117 }
1118}
1119
1120static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1121{
1122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1123 u32 offset =
1124 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1125 u32 val, idx;
1126
1127 /*
1128 * The first RX queue - fallback queue, which is designated for
1129 * management frame, command responses etc, is always mapped to the
1130 * first interrupt vector. The other RX queues are mapped to
1131 * the other (N - 2) interrupt vectors.
1132 */
1133 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1134 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1135 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1136 MSIX_FH_INT_CAUSES_Q(idx - offset));
1137 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1138 }
1139 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1140
1141 val = MSIX_FH_INT_CAUSES_Q(0);
1142 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1143 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1144 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1145
1146 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1147 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1148}
1149
1150static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1151{
1152 struct iwl_trans *trans = trans_pcie->trans;
1153
1154 if (!trans_pcie->msix_enabled) {
1155 if (trans->cfg->mq_rx_supported)
1156 iwl_write_prph(trans, UREG_CHICK,
1157 UREG_CHICK_MSI_ENABLE);
1158 return;
1159 }
1160
1161 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1162
1163 /*
1164 * Each cause from the causes list above and the RX causes is
1165 * represented as a byte in the IVAR table. The first nibble
1166 * represents the bound interrupt vector of the cause, the second
1167 * represents no auto clear for this cause. This will be set if its
1168 * interrupt vector is bound to serve other causes.
1169 */
1170 iwl_pcie_map_rx_causes(trans);
1171
1172 iwl_pcie_map_non_rx_causes(trans);
1173
1174 trans_pcie->fh_init_mask =
1175 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1176 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1177 trans_pcie->hw_init_mask =
1178 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1179 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1180}
1181
fa9f3281 1182static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1183{
43e58856 1184 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1185 bool hw_rfkill, was_hw_rfkill;
1186
fa9f3281
EG		 1187 lockdep_assert_held(&trans_pcie->mutex);
1188
1189 if (trans_pcie->is_down)
1190 return;
1191
1192 trans_pcie->is_down = true;
1193
3dc3374f 1194 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1195
43e58856 1196 /* tell the device to stop sending interrupts */
ae2c30bf 1197 iwl_disable_interrupts(trans);
ae2c30bf 1198
ab6cf8e8 1199 /* device going down, Stop using ICT table */
990aa6d7 1200 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1201
1202 /*
1203 * If a HW restart happens during firmware loading,
1204 * then the firmware loading might call this function
1205 * and later it might be called again due to the
1206 * restart. So don't process again if the device is
1207 * already dead.
1208 */
31b8b343 1209 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1210 IWL_DEBUG_INFO(trans,
1211 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1212 iwl_pcie_tx_stop(trans);
9805c446 1213 iwl_pcie_rx_stop(trans);
6379103e 1214
ab6cf8e8 1215 /* Power-down device's busmaster DMA clocks */
95411d04 1216 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1217 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1218 APMG_CLK_VAL_DMA_CLK_RQT);
1219 udelay(5);
1220 }
ab6cf8e8
EG		 1221 }
1222
1223 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1224 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1225 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1226
1227 /* Stop the device, and put it in low power state */
b7aaeae4 1228 iwl_pcie_apm_stop(trans, false);
43e58856 1229
03d6c3b0
EG		 1230 /* stop and reset the on-board processor */
1231 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1232 usleep_range(1000, 2000);
03d6c3b0
EG		 1233
1234 /*
1235 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1236 * This is a bug in certain verions of the hardware.
1237 * Certain devices also keep sending HW RF kill interrupt all
1238 * the time, unless the interrupt is ACKed even if the interrupt
1239 * should be masked. Re-ACK all the interrupts here.
43e58856 1240 */
43e58856 1241 iwl_disable_interrupts(trans);
43e58856 1242
74fda971 1243 /* clear all status bits */
eb7ff77e
AN		 1244 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1245 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1246 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1247 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1248
1249 /*
1250 * Even if we stop the HW, we still want the RF kill
1251 * interrupt
1252 */
1253 iwl_enable_rfkill_int(trans);
1254
1255 /*
1256 * Check again since the RF kill state may have changed while
1257 * all the interrupts were disabled, in this case we couldn't
1258 * receive the RF kill interrupt and update the state in the
1259 * op_mode.
3dc3374f
EG		 1260 * Don't call the op_mode if the rkfill state hasn't changed.
1261 * This allows the op_mode to call stop_device from the rfkill
1262 * notification without endless recursion. Under very rare
1263 * circumstances, we might have a small recursion if the rfkill
1264 * state changed exactly now while we were called from stop_device.
1265 * This is very unlikely but can happen and is supported.
a4082843
AN		 1266 */
1267 hw_rfkill = iwl_is_rfkill_set(trans);
1268 if (hw_rfkill)
eb7ff77e 1269 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1270 else
eb7ff77e 1271 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1272 if (hw_rfkill != was_hw_rfkill)
14cfca71 1273 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0 1274
a6bd005f 1275 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1276 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1277}
1278
2e5d4a8f
HD		 1279static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1280{
1281 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1282
1283 if (trans_pcie->msix_enabled) {
1284 int i;
1285
496d83ca 1286 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1287 synchronize_irq(trans_pcie->msix_entries[i].vector);
1288 } else {
1289 synchronize_irq(trans_pcie->pci_dev->irq);
1290 }
1291}
1292
a6bd005f
EG		 1293static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1294 const struct fw_img *fw, bool run_in_rfkill)
1295{
1296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1297 bool hw_rfkill;
1298 int ret;
1299
1300 /* This may fail if AMT took ownership of the device */
1301 if (iwl_pcie_prepare_card_hw(trans)) {
1302 IWL_WARN(trans, "Exit HW not ready\n");
1303 ret = -EIO;
1304 goto out;
1305 }
1306
1307 iwl_enable_rfkill_int(trans);
1308
1309 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1310
1311 /*
1312 * We enabled the RF-Kill interrupt and the handler may very
1313 * well be running. Disable the interrupts to make sure no other
1314 * interrupt can be fired.
1315 */
1316 iwl_disable_interrupts(trans);
1317
1318 /* Make sure it finished running */
2e5d4a8f 1319 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1320
1321 mutex_lock(&trans_pcie->mutex);
1322
1323 /* If platform's RF_KILL switch is NOT set to KILL */
727c02df 1324 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1325 if (hw_rfkill && !run_in_rfkill) {
1326 ret = -ERFKILL;
1327 goto out;
1328 }
1329
1330 /* Someone called stop_device, don't try to start_fw */
1331 if (trans_pcie->is_down) {
1332 IWL_WARN(trans,
1333 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1334 ret = -EIO;
a6bd005f
EG		 1335 goto out;
1336 }
1337
1338 /* make sure rfkill handshake bits are cleared */
1339 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1340 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1341 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1342
1343 /* clear (again), then enable host interrupts */
1344 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1345
1346 ret = iwl_pcie_nic_init(trans);
1347 if (ret) {
1348 IWL_ERR(trans, "Unable to init nic\n");
1349 goto out;
1350 }
1351
1352 /*
1353 * Now, we load the firmware and don't want to be interrupted, even
1354 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1355 * FH_TX interrupt which is needed to load the firmware). If the
1356 * RF-Kill switch is toggled, we will find out after having loaded
1357 * the firmware and return the proper value to the caller.
1358 */
1359 iwl_enable_fw_load_int(trans);
1360
1361 /* really make sure rfkill handshake bits are cleared */
1362 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1363 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1364
1365 /* Load the given image to the HW */
1366 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1367 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1368 else
1369 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1370
1371 /* re-check RF-Kill state since we may have missed the interrupt */
727c02df 1372 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1373 if (hw_rfkill && !run_in_rfkill)
1374 ret = -ERFKILL;
1375
1376out:
1377 mutex_unlock(&trans_pcie->mutex);
1378 return ret;
1379}
1380
1381static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1382{
1383 iwl_pcie_reset_ict(trans);
1384 iwl_pcie_tx_start(trans, scd_addr);
1385}
1386
fa9f3281
EG		 1387static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1388{
1389 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1390
1391 mutex_lock(&trans_pcie->mutex);
1392 _iwl_trans_pcie_stop_device(trans, low_power);
1393 mutex_unlock(&trans_pcie->mutex);
1394}
1395
14cfca71
JB		 1396void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1397{
fa9f3281
EG		 1398 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1399 IWL_TRANS_GET_PCIE_TRANS(trans);
1400
1401 lockdep_assert_held(&trans_pcie->mutex);
1402
14cfca71 1403 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1404 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1405}
1406
23ae6128
MG		 1407static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1408 bool reset)
2dd4f9f7 1409{
23ae6128 1410 if (!reset) {
6dfb36c8
EP		 1411 /* Enable persistence mode to avoid reset */
1412 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1413 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1414 }
1415
2dd4f9f7 1416 iwl_disable_interrupts(trans);
debff618
JB		 1417
1418 /*
1419 * in testing mode, the host stays awake and the
1420 * hardware won't be reset (not even partially)
1421 */
1422 if (test)
1423 return;
1424
ddaf5a5b
JB		 1425 iwl_pcie_disable_ict(trans);
1426
2e5d4a8f 1427 iwl_pcie_synchronize_irqs(trans);
33b56af1 1428
2dd4f9f7
JB		 1429 iwl_clear_bit(trans, CSR_GP_CNTRL,
1430 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1431 iwl_clear_bit(trans, CSR_GP_CNTRL,
1432 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1433
1316d595
SS		 1434 iwl_pcie_enable_rx_wake(trans, false);
1435
23ae6128 1436 if (reset) {
6dfb36c8
EP		 1437 /*
1438 * reset TX queues -- some of their registers reset during S3
1439 * so if we don't reset everything here the D3 image would try
1440 * to execute some invalid memory upon resume
1441 */
1442 iwl_trans_pcie_tx_reset(trans);
1443 }
ddaf5a5b
JB		 1444
1445 iwl_pcie_set_pwr(trans, true);
1446}
1447
1448static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1449 enum iwl_d3_status *status,
23ae6128 1450 bool test, bool reset)
ddaf5a5b
JB		 1451{
1452 u32 val;
1453 int ret;
1454
debff618
JB		 1455 if (test) {
1456 iwl_enable_interrupts(trans);
1457 *status = IWL_D3_STATUS_ALIVE;
1458 return 0;
1459 }
1460
1316d595
SS		 1461 iwl_pcie_enable_rx_wake(trans, true);
1462
ddaf5a5b
JB		 1463 /*
1464 * Also enables interrupts - none will happen as the device doesn't
1465 * know we're waking it up, only when the opmode actually tells it
1466 * after this call.
1467 */
1468 iwl_pcie_reset_ict(trans);
18dcb9a9 1469 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1470
1471 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1472 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1473
01e58a28
EG		 1474 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1475 udelay(2);
1476
ddaf5a5b
JB		 1477 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1478 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1479 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1480 25000);
7f2ac8fb 1481 if (ret < 0) {
ddaf5a5b
JB		 1482 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1483 return ret;
1484 }
1485
a3ead656
EG		 1486 iwl_pcie_set_pwr(trans, false);
1487
23ae6128 1488 if (!reset) {
6dfb36c8
EP		 1489 iwl_clear_bit(trans, CSR_GP_CNTRL,
1490 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1491 } else {
1492 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1493
6dfb36c8
EP		 1494 ret = iwl_pcie_rx_init(trans);
1495 if (ret) {
1496 IWL_ERR(trans,
1497 "Failed to resume the device (RX reset)\n");
1498 return ret;
1499 }
ddaf5a5b
JB		 1500 }
1501
a3ead656
EG		 1502 val = iwl_read32(trans, CSR_RESET);
1503 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1504 *status = IWL_D3_STATUS_RESET;
1505 else
1506 *status = IWL_D3_STATUS_ALIVE;
1507
ddaf5a5b 1508 return 0;
2dd4f9f7
JB		 1509}
1510
2e5d4a8f
HD		 1511static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1512 struct iwl_trans *trans)
1513{
1514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9fb064df 1515 int max_irqs, num_irqs, i, ret, nr_online_cpus;
2e5d4a8f 1516 u16 pci_cmd;
2e5d4a8f 1517
06f4b081
SS		 1518 if (!trans->cfg->mq_rx_supported)
1519 goto enable_msi;
1520
9fb064df
HD		 1521 nr_online_cpus = num_online_cpus();
1522 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1523 for (i = 0; i < max_irqs; i++)
1524 trans_pcie->msix_entries[i].entry = i;
496d83ca 1525
06f4b081
SS		 1526 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1527 MSIX_MIN_INTERRUPT_VECTORS,
1528 max_irqs);
1529 if (num_irqs < 0) {
2e5d4a8f 1530 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1531 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1532 num_irqs);
1533 goto enable_msi;
1534 }
1535 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1536
06f4b081
SS		 1537 IWL_DEBUG_INFO(trans,
1538 "MSI-X enabled. %d interrupt vectors were allocated\n",
1539 num_irqs);
1540
1541 /*
1542 * In case the OS provides fewer interrupts than requested, different
1543 * causes will share the same interrupt vector as follows:
1544 * One interrupt less: non rx causes shared with FBQ.
1545 * Two interrupts less: non rx causes shared with FBQ and RSS.
1546 * More than two interrupts: we will use fewer RSS queues.
1547 */
9fb064df 1548 if (num_irqs <= nr_online_cpus) {
06f4b081
SS		 1549 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1550 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1551 IWL_SHARED_IRQ_FIRST_RSS;
9fb064df 1552 } else if (num_irqs == nr_online_cpus + 1) {
06f4b081
SS		 1553 trans_pcie->trans->num_rx_queues = num_irqs;
1554 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1555 } else {
1556 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f
HD		 1557 }
1558
06f4b081
SS		 1559 trans_pcie->alloc_vecs = num_irqs;
1560 trans_pcie->msix_enabled = true;
1561 return;
1562
1563enable_msi:
1564 ret = pci_enable_msi(pdev);
1565 if (ret) {
1566 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1567 /* enable rfkill interrupt: hw bug w/a */
1568 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1569 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1570 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1571 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1572 }
1573 }
1574}
1575
7c8d91eb
HD		 1576static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1577{
1578 int iter_rx_q, i, ret, cpu, offset;
1579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1580
1581 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1582 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1583 offset = 1 + i;
1584 for (; i < iter_rx_q ; i++) {
1585 /*
1586 * Get the cpu prior to the place to search
1587 * (i.e. return will be > i - 1).
1588 */
1589 cpu = cpumask_next(i - offset, cpu_online_mask);
1590 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1591 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1592 &trans_pcie->affinity_mask[i]);
1593 if (ret)
1594 IWL_ERR(trans_pcie->trans,
1595 "Failed to set affinity mask for IRQ %d\n",
1596 i);
1597 }
1598}
1599
64fa3aff
SD		 1600static const char *queue_name(struct device *dev,
1601 struct iwl_trans_pcie *trans_p, int i)
1602{
1603 if (trans_p->shared_vec_mask) {
1604 int vec = trans_p->shared_vec_mask &
1605 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1606
1607 if (i == 0)
1608 return DRV_NAME ": shared IRQ";
1609
1610 return devm_kasprintf(dev, GFP_KERNEL,
1611 DRV_NAME ": queue %d", i + vec);
1612 }
1613 if (i == 0)
1614 return DRV_NAME ": default queue";
1615
1616 if (i == trans_p->alloc_vecs - 1)
1617 return DRV_NAME ": exception";
1618
1619 return devm_kasprintf(dev, GFP_KERNEL,
1620 DRV_NAME ": queue %d", i);
1621}
1622
2e5d4a8f
HD		 1623static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1624 struct iwl_trans_pcie *trans_pcie)
1625{
496d83ca 1626 int i;
2e5d4a8f 1627
496d83ca 1628 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1629 int ret;
5a41a86c 1630 struct msix_entry *msix_entry;
64fa3aff
SD		 1631 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1632
1633 if (!qname)
1634 return -ENOMEM;
5a41a86c
SD		 1635
1636 msix_entry = &trans_pcie->msix_entries[i];
1637 ret = devm_request_threaded_irq(&pdev->dev,
1638 msix_entry->vector,
1639 iwl_pcie_msix_isr,
1640 (i == trans_pcie->def_irq) ?
1641 iwl_pcie_irq_msix_handler :
1642 iwl_pcie_irq_rx_msix_handler,
1643 IRQF_SHARED,
64fa3aff 1644 qname,
5a41a86c 1645 msix_entry);
2e5d4a8f 1646 if (ret) {
2e5d4a8f
HD		 1647 IWL_ERR(trans_pcie->trans,
1648 "Error allocating IRQ %d\n", i);
5a41a86c 1649
2e5d4a8f
HD		 1650 return ret;
1651 }
1652 }
7c8d91eb 1653 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1654
1655 return 0;
1656}
1657
fa9f3281 1658static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1659{
fa9f3281 1660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1661 int err;
e6bb4c9c 1662
fa9f3281
EG		 1663 lockdep_assert_held(&trans_pcie->mutex);
1664
7afe3705 1665 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1666 if (err) {
d6f1c316 1667 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1668 return err;
ebb7678d 1669 }
a6c684ee 1670
2997494f 1671 /* Reset the entire device */
ce836c76 1672 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1673 usleep_range(1000, 2000);
2997494f 1674
7afe3705 1675 iwl_pcie_apm_init(trans);
a6c684ee 1676
2e5d4a8f 1677 iwl_pcie_init_msix(trans_pcie);
226c02ca
EG		 1678 /* From now on, the op_mode will be kept updated about RF kill state */
1679 iwl_enable_rfkill_int(trans);
1680
fa9f3281
EG		 1681 /* Set is_down to false here so that...*/
1682 trans_pcie->is_down = false;
1683
727c02df
SS		 1684 /* ...rfkill can call stop_device and set it false if needed */
1685 iwl_trans_check_hw_rf_kill(trans);
d48e2074 1686
4cbb8e50
LC		 1687 /* Make sure we sync here, because we'll need full access later */
1688 if (low_power)
1689 pm_runtime_resume(trans->dev);
1690
a8b691e6 1691 return 0;
e6bb4c9c
EG		 1692}
1693
fa9f3281
EG		 1694static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1695{
1696 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1697 int ret;
1698
1699 mutex_lock(&trans_pcie->mutex);
1700 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1701 mutex_unlock(&trans_pcie->mutex);
1702
1703 return ret;
1704}
1705
a4082843 1706static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1707{
20d3b647 1708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1709
fa9f3281
EG		 1710 mutex_lock(&trans_pcie->mutex);
1711
a4082843 1712 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1713 iwl_disable_interrupts(trans);
ee7d737c 1714
b7aaeae4 1715 iwl_pcie_apm_stop(trans, true);
cc56feb2 1716
218733cf 1717 iwl_disable_interrupts(trans);
1df06bdc 1718
8d96bb61 1719 iwl_pcie_disable_ict(trans);
33b56af1 1720
fa9f3281 1721 mutex_unlock(&trans_pcie->mutex);
33b56af1 1722
2e5d4a8f 1723 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1724}
1725
03905495
EG		 1726static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1727{
05f5b97e 1728 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1729}
1730
1731static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1732{
05f5b97e 1733 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1734}
1735
1736static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1737{
05f5b97e 1738 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1739}
1740
6a06b6c1
EG		 1741static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1742{
f9477c17
AP		 1743 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1744 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1745 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1746}
1747
1748static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1749 u32 val)
1750{
1751 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1752 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1753 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1754}
1755
c6f600fc 1756static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1757 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1758{
1759 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1760
1761 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1762 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1763 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1764 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1765 trans_pcie->n_no_reclaim_cmds = 0;
1766 else
1767 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1768 if (trans_pcie->n_no_reclaim_cmds)
1769 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1770 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1771
6c4fbcbc
EG		 1772 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1773 trans_pcie->rx_page_order =
1774 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1775
046db346 1776 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1777 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1778 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1779
21cb3222
JB		 1780 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1781 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1782
39bdb17e
SD		 1783 trans->command_groups = trans_cfg->command_groups;
1784 trans->command_groups_size = trans_cfg->command_groups_size;
1785
f14d6b39
JB		 1786 /* Initialize NAPI here - it should be before registering to mac80211
1787 * in the opmode but after the HW struct is allocated.
1788 * As this function may be called again in some corner cases don't
1789 * do anything if NAPI was already initialized.
1790 */
bce97731 1791 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1792 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1793}
1794
d1ff5253 1795void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1796{
20d3b647 1797 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1798 int i;
a42a1844 1799
2e5d4a8f 1800 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1801
f02831be 1802 iwl_pcie_tx_free(trans);
9805c446 1803 iwl_pcie_rx_free(trans);
6379103e 1804
2e5d4a8f 1805 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1806 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1807 irq_set_affinity_hint(
1808 trans_pcie->msix_entries[i].vector,
1809 NULL);
7c8d91eb 1810 }
2e5d4a8f 1811
2e5d4a8f
HD		 1812 trans_pcie->msix_enabled = false;
1813 } else {
2e5d4a8f 1814 iwl_pcie_free_ict(trans);
2e5d4a8f 1815 }
a42a1844 1816
c2d20201
EG		 1817 iwl_pcie_free_fw_monitor(trans);
1818
6eb5e529
EG		 1819 for_each_possible_cpu(i) {
1820 struct iwl_tso_hdr_page *p =
1821 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1822
1823 if (p->page)
1824 __free_page(p->page);
1825 }
1826
1827 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1828 mutex_destroy(&trans_pcie->mutex);
7b501d10 1829 iwl_trans_free(trans);
34c1b7ba
EG		 1830}
1831
47107e84
DF		 1832static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1833{
47107e84 1834 if (state)
eb7ff77e 1835 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1836 else
eb7ff77e 1837 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1838}
1839
23ba9340
EG		 1840static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1841 unsigned long *flags)
7a65d170
EG		 1842{
1843 int ret;
cfb4e624
JB		 1844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1845
1846 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1847
fc8a350d 1848 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1849 goto out;
1850
7a65d170 1851 /* this bit wakes up the NIC */
e139dc4a
LE		 1852 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1853 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1854 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1855 udelay(2);
7a65d170
EG		 1856
1857 /*
1858 * These bits say the device is running, and should keep running for
1859 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1860 * but they do not indicate that embedded SRAM is restored yet;
1861 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1862 * to/from host DRAM when sleeping/waking for power-saving.
1863 * Each direction takes approximately 1/4 millisecond; with this
1864 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1865 * series of register accesses are expected (e.g. reading Event Log),
1866 * to keep device from sleeping.
1867 *
1868 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1869 * SRAM is okay/restored. We don't check that here because this call
1870 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1871 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1872 *
1873 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1874 * and do not save/restore SRAM when power cycling.
1875 */
1876 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1877 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1878 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1879 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1880 if (unlikely(ret < 0)) {
1881 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1882 WARN_ONCE(1,
1883 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1884 iwl_read32(trans, CSR_GP_CNTRL));
1885 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1886 return false;
7a65d170
EG		 1887 }
1888
b9439491 1889out:
e56b04ef
LE		 1890 /*
1891 * Fool sparse by faking we release the lock - sparse will
1892 * track nic_access anyway.
1893 */
cfb4e624 1894 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1895 return true;
1896}
1897
e56b04ef
LE		 1898static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1899 unsigned long *flags)
7a65d170 1900{
cfb4e624 1901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1902
cfb4e624 1903 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1904
1905 /*
1906 * Fool sparse by faking we acquiring the lock - sparse will
1907 * track nic_access anyway.
1908 */
cfb4e624 1909 __acquire(&trans_pcie->reg_lock);
e56b04ef 1910
fc8a350d 1911 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1912 goto out;
1913
e139dc4a
LE		 1914 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1915 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1916 /*
1917 * Above we read the CSR_GP_CNTRL register, which will flush
1918 * any previous writes, but we need the write that clears the
1919 * MAC_ACCESS_REQ bit to be performed before any other writes
1920 * scheduled on different CPUs (after we drop reg_lock).
1921 */
1922 mmiowb();
b9439491 1923out:
cfb4e624 1924 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1925}
1926
4fd442db
EG		 1927static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1928 void *buf, int dwords)
1929{
1930 unsigned long flags;
1931 int offs, ret = 0;
1932 u32 *vals = buf;
1933
23ba9340 1934 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1935 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1936 for (offs = 0; offs < dwords; offs++)
1937 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1938 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1939 } else {
1940 ret = -EBUSY;
1941 }
4fd442db
EG		 1942 return ret;
1943}
1944
1945static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1946 const void *buf, int dwords)
4fd442db
EG		 1947{
1948 unsigned long flags;
1949 int offs, ret = 0;
bf0fd5da 1950 const u32 *vals = buf;
4fd442db 1951
23ba9340 1952 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1953 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1954 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1955 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1956 vals ? vals[offs] : 0);
e56b04ef 1957 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1958 } else {
1959 ret = -EBUSY;
1960 }
4fd442db
EG		 1961 return ret;
1962}
7a65d170 1963
e0b8d405
EG		 1964static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1965 unsigned long txqs,
1966 bool freeze)
1967{
1968 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1969 int queue;
1970
1971 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1972 struct iwl_txq *txq = &trans_pcie->txq[queue];
1973 unsigned long now;
1974
1975 spin_lock_bh(&txq->lock);
1976
1977 now = jiffies;
1978
1979 if (txq->frozen == freeze)
1980 goto next_queue;
1981
1982 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1983 freeze ? "Freezing" : "Waking", queue);
1984
1985 txq->frozen = freeze;
1986
bb98ecd4 1987 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 1988 goto next_queue;
1989
1990 if (freeze) {
1991 if (unlikely(time_after(now,
1992 txq->stuck_timer.expires))) {
1993 /*
1994 * The timer should have fired, maybe it is
1995 * spinning right now on the lock.
1996 */
1997 goto next_queue;
1998 }
1999 /* remember how long until the timer fires */
2000 txq->frozen_expiry_remainder =
2001 txq->stuck_timer.expires - now;
2002 del_timer(&txq->stuck_timer);
2003 goto next_queue;
2004 }
2005
2006 /*
2007 * Wake a non-empty queue -> arm timer with the
2008 * remainder before it froze
2009 */
2010 mod_timer(&txq->stuck_timer,
2011 now + txq->frozen_expiry_remainder);
2012
2013next_queue:
2014 spin_unlock_bh(&txq->lock);
2015 }
2016}
2017
0cd58eaa
EG		 2018static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2019{
2020 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2021 int i;
2022
2023 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2024 struct iwl_txq *txq = &trans_pcie->txq[i];
2025
2026 if (i == trans_pcie->cmd_queue)
2027 continue;
2028
2029 spin_lock_bh(&txq->lock);
2030
2031 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2032 txq->block--;
2033 if (!txq->block) {
2034 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2035 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2036 }
2037 } else if (block) {
2038 txq->block++;
2039 }
2040
2041 spin_unlock_bh(&txq->lock);
2042 }
2043}
2044
5f178cd2
EG		 2045#define IWL_FLUSH_WAIT_MS 2000
2046
38398efb
SS		 2047void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2048{
2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2050 u32 scd_sram_addr;
2051 u8 buf[16];
2052 int cnt;
2053
2054 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
bb98ecd4 2055 txq->read_ptr, txq->write_ptr);
38398efb 2056
ae79785f
SS		 2057 if (trans->cfg->use_tfh)
2058 /* TODO: access new SCD registers and dump them */
2059 return;
2060
38398efb 2061 scd_sram_addr = trans_pcie->scd_base_addr +
bb98ecd4 2062 SCD_TX_STTS_QUEUE_OFFSET(txq->id);
38398efb
SS		 2063 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
2064
2065 iwl_print_hex_error(trans, buf, sizeof(buf));
2066
2067 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
2068 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
2069 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
2070
2071 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2072 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
2073 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2074 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2075 u32 tbl_dw =
2076 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
2077 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
2078
2079 if (cnt & 0x1)
2080 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
2081 else
2082 tbl_dw = tbl_dw & 0x0000FFFF;
2083
2084 IWL_ERR(trans,
2085 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
2086 cnt, active ? "" : "in", fifo, tbl_dw,
2087 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
2088 (TFD_QUEUE_SIZE_MAX - 1),
2089 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
2090 }
2091}
2092
3cafdbe6 2093static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 2094{
8ad71bef 2095 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2096 struct iwl_txq *txq;
5f178cd2
EG		 2097 int cnt;
2098 unsigned long now = jiffies;
2099 int ret = 0;
2100
2101 /* waiting for all the tx frames complete might take a while */
035f7ff2 2102 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 2103 u8 wr_ptr;
2104
9ba1947a 2105 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2106 continue;
3cafdbe6
EG		 2107 if (!test_bit(cnt, trans_pcie->queue_used))
2108 continue;
2109 if (!(BIT(cnt) & txq_bm))
2110 continue;
748fa67c
EG		 2111
2112 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 2113 txq = &trans_pcie->txq[cnt];
bb98ecd4 2114 wr_ptr = ACCESS_ONCE(txq->write_ptr);
fa1a91fd 2115
bb98ecd4 2116 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
fa1a91fd
EG		 2117 !time_after(jiffies,
2118 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
bb98ecd4 2119 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
fa1a91fd
EG		 2120
2121 if (WARN_ONCE(wr_ptr != write_ptr,
2122 "WR pointer moved while flushing %d -> %d\n",
2123 wr_ptr, write_ptr))
2124 return -ETIMEDOUT;
192185d6 2125 usleep_range(1000, 2000);
fa1a91fd 2126 }
5f178cd2 2127
bb98ecd4 2128 if (txq->read_ptr != txq->write_ptr) {
1c3fea82
EG		 2129 IWL_ERR(trans,
2130 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 2131 ret = -ETIMEDOUT;
2132 break;
2133 }
748fa67c 2134 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 2135 }
1c3fea82 2136
38398efb
SS		 2137 if (ret)
2138 iwl_trans_pcie_log_scd_error(trans, txq);
1c3fea82 2139
5f178cd2
EG		 2140 return ret;
2141}
2142
e139dc4a
LE		 2143static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2144 u32 mask, u32 value)
2145{
e56b04ef 2146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2147 unsigned long flags;
2148
e56b04ef 2149 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2150 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2151 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2152}
2153
c24c7f58 2154static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2155{
2156 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2157
2158 if (iwlwifi_mod_params.d0i3_disable)
2159 return;
2160
b3ff1270 2161 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2162
2163#ifdef CONFIG_PM
2164 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2165 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2166#endif /* CONFIG_PM */
7616f334
EP		 2167}
2168
c24c7f58 2169static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2170{
2171 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2172
2173 if (iwlwifi_mod_params.d0i3_disable)
2174 return;
2175
b3ff1270
LC		 2176 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2177 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2178
5d93f3a2
LC		 2179#ifdef CONFIG_PM
2180 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2181 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2182#endif /* CONFIG_PM */
7616f334
EP		 2183}
2184
ff620849
EG		 2185static const char *get_csr_string(int cmd)
2186{
d9fb6465 2187#define IWL_CMD(x) case x: return #x
ff620849
EG		 2188 switch (cmd) {
2189 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2190 IWL_CMD(CSR_INT_COALESCING);
2191 IWL_CMD(CSR_INT);
2192 IWL_CMD(CSR_INT_MASK);
2193 IWL_CMD(CSR_FH_INT_STATUS);
2194 IWL_CMD(CSR_GPIO_IN);
2195 IWL_CMD(CSR_RESET);
2196 IWL_CMD(CSR_GP_CNTRL);
2197 IWL_CMD(CSR_HW_REV);
2198 IWL_CMD(CSR_EEPROM_REG);
2199 IWL_CMD(CSR_EEPROM_GP);
2200 IWL_CMD(CSR_OTP_GP_REG);
2201 IWL_CMD(CSR_GIO_REG);
2202 IWL_CMD(CSR_GP_UCODE_REG);
2203 IWL_CMD(CSR_GP_DRIVER_REG);
2204 IWL_CMD(CSR_UCODE_DRV_GP1);
2205 IWL_CMD(CSR_UCODE_DRV_GP2);
2206 IWL_CMD(CSR_LED_REG);
2207 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2208 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2209 IWL_CMD(CSR_ANA_PLL_CFG);
2210 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2211 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2212 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2213 default:
2214 return "UNKNOWN";
2215 }
d9fb6465 2216#undef IWL_CMD
ff620849
EG		 2217}
2218
990aa6d7 2219void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2220{
2221 int i;
2222 static const u32 csr_tbl[] = {
2223 CSR_HW_IF_CONFIG_REG,
2224 CSR_INT_COALESCING,
2225 CSR_INT,
2226 CSR_INT_MASK,
2227 CSR_FH_INT_STATUS,
2228 CSR_GPIO_IN,
2229 CSR_RESET,
2230 CSR_GP_CNTRL,
2231 CSR_HW_REV,
2232 CSR_EEPROM_REG,
2233 CSR_EEPROM_GP,
2234 CSR_OTP_GP_REG,
2235 CSR_GIO_REG,
2236 CSR_GP_UCODE_REG,
2237 CSR_GP_DRIVER_REG,
2238 CSR_UCODE_DRV_GP1,
2239 CSR_UCODE_DRV_GP2,
2240 CSR_LED_REG,
2241 CSR_DRAM_INT_TBL_REG,
2242 CSR_GIO_CHICKEN_BITS,
2243 CSR_ANA_PLL_CFG,
a812cba9 2244 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2245 CSR_HW_REV_WA_REG,
2246 CSR_DBG_HPET_MEM_REG
2247 };
2248 IWL_ERR(trans, "CSR values:\n");
2249 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2250 "CSR_INT_PERIODIC_REG)\n");
2251 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2252 IWL_ERR(trans, " %25s: 0X%08x\n",
2253 get_csr_string(csr_tbl[i]),
1042db2a 2254 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2255 }
2256}
2257
87e5666c
EG		 2258#ifdef CONFIG_IWLWIFI_DEBUGFS
2259/* create and remove of files */
2260#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2261 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2262 &iwl_dbgfs_##name##_ops)) \
9da987ac 2263 goto err; \
87e5666c
EG		 2264} while (0)
2265
2266/* file operation */
87e5666c 2267#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2268static const struct file_operations iwl_dbgfs_##name##_ops = { \
2269 .read = iwl_dbgfs_##name##_read, \
234e3405 2270 .open = simple_open, \
87e5666c
EG		 2271 .llseek = generic_file_llseek, \
2272};
2273
16db88ba 2274#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2275static const struct file_operations iwl_dbgfs_##name##_ops = { \
2276 .write = iwl_dbgfs_##name##_write, \
234e3405 2277 .open = simple_open, \
16db88ba
EG		 2278 .llseek = generic_file_llseek, \
2279};
2280
87e5666c 2281#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2282static const struct file_operations iwl_dbgfs_##name##_ops = { \
2283 .write = iwl_dbgfs_##name##_write, \
2284 .read = iwl_dbgfs_##name##_read, \
234e3405 2285 .open = simple_open, \
87e5666c
EG		 2286 .llseek = generic_file_llseek, \
2287};
2288
87e5666c 2289static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2290 char __user *user_buf,
2291 size_t count, loff_t *ppos)
8ad71bef 2292{
5a878bf6 2293 struct iwl_trans *trans = file->private_data;
8ad71bef 2294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2295 struct iwl_txq *txq;
87e5666c
EG		 2296 char *buf;
2297 int pos = 0;
2298 int cnt;
2299 int ret;
1745e440
WYG		 2300 size_t bufsz;
2301
e0b8d405 2302 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2303
f9e75447 2304 if (!trans_pcie->txq)
87e5666c 2305 return -EAGAIN;
f9e75447 2306
87e5666c
EG		 2307 buf = kzalloc(bufsz, GFP_KERNEL);
2308 if (!buf)
2309 return -ENOMEM;
2310
035f7ff2 2311 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 2312 txq = &trans_pcie->txq[cnt];
87e5666c 2313 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2314 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2315 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2316 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2317 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2318 txq->need_update, txq->frozen,
f40faf62 2319 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2320 }
2321 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2322 kfree(buf);
2323 return ret;
2324}
2325
2326static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2327 char __user *user_buf,
2328 size_t count, loff_t *ppos)
2329{
5a878bf6 2330 struct iwl_trans *trans = file->private_data;
20d3b647 2331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2332 char *buf;
2333 int pos = 0, i, ret;
2334 size_t bufsz = sizeof(buf);
2335
2336 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2337
2338 if (!trans_pcie->rxq)
2339 return -EAGAIN;
2340
2341 buf = kzalloc(bufsz, GFP_KERNEL);
2342 if (!buf)
2343 return -ENOMEM;
2344
2345 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2346 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2347
2348 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2349 i);
2350 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2351 rxq->read);
2352 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2353 rxq->write);
2354 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2355 rxq->write_actual);
2356 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2357 rxq->need_update);
2358 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2359 rxq->free_count);
2360 if (rxq->rb_stts) {
2361 pos += scnprintf(buf + pos, bufsz - pos,
2362 "\tclosed_rb_num: %u\n",
2363 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2364 0x0FFF);
2365 } else {
2366 pos += scnprintf(buf + pos, bufsz - pos,
2367 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2368 }
87e5666c 2369 }
78485054
SS		 2370 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2371 kfree(buf);
2372
2373 return ret;
87e5666c
EG		 2374}
2375
1f7b6172
EG		 2376static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2377 char __user *user_buf,
20d3b647
JB		 2378 size_t count, loff_t *ppos)
2379{
1f7b6172 2380 struct iwl_trans *trans = file->private_data;
20d3b647 2381 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2382 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2383
2384 int pos = 0;
2385 char *buf;
2386 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2387 ssize_t ret;
2388
2389 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2390 if (!buf)
1f7b6172 2391 return -ENOMEM;
1f7b6172
EG		 2392
2393 pos += scnprintf(buf + pos, bufsz - pos,
2394 "Interrupt Statistics Report:\n");
2395
2396 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2397 isr_stats->hw);
2398 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2399 isr_stats->sw);
2400 if (isr_stats->sw || isr_stats->hw) {
2401 pos += scnprintf(buf + pos, bufsz - pos,
2402 "\tLast Restarting Code: 0x%X\n",
2403 isr_stats->err_code);
2404 }
2405#ifdef CONFIG_IWLWIFI_DEBUG
2406 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2407 isr_stats->sch);
2408 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2409 isr_stats->alive);
2410#endif
2411 pos += scnprintf(buf + pos, bufsz - pos,
2412 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2413
2414 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2415 isr_stats->ctkill);
2416
2417 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2418 isr_stats->wakeup);
2419
2420 pos += scnprintf(buf + pos, bufsz - pos,
2421 "Rx command responses:\t\t %u\n", isr_stats->rx);
2422
2423 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2424 isr_stats->tx);
2425
2426 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2427 isr_stats->unhandled);
2428
2429 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2430 kfree(buf);
2431 return ret;
2432}
2433
2434static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2435 const char __user *user_buf,
2436 size_t count, loff_t *ppos)
2437{
2438 struct iwl_trans *trans = file->private_data;
20d3b647 2439 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2440 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2441
2442 char buf[8];
2443 int buf_size;
2444 u32 reset_flag;
2445
2446 memset(buf, 0, sizeof(buf));
2447 buf_size = min(count, sizeof(buf) - 1);
2448 if (copy_from_user(buf, user_buf, buf_size))
2449 return -EFAULT;
2450 if (sscanf(buf, "%x", &reset_flag) != 1)
2451 return -EFAULT;
2452 if (reset_flag == 0)
2453 memset(isr_stats, 0, sizeof(*isr_stats));
2454
2455 return count;
2456}
2457
16db88ba 2458static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2459 const char __user *user_buf,
2460 size_t count, loff_t *ppos)
16db88ba
EG		 2461{
2462 struct iwl_trans *trans = file->private_data;
2463 char buf[8];
2464 int buf_size;
2465 int csr;
2466
2467 memset(buf, 0, sizeof(buf));
2468 buf_size = min(count, sizeof(buf) - 1);
2469 if (copy_from_user(buf, user_buf, buf_size))
2470 return -EFAULT;
2471 if (sscanf(buf, "%d", &csr) != 1)
2472 return -EFAULT;
2473
990aa6d7 2474 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2475
2476 return count;
2477}
2478
16db88ba 2479static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2480 char __user *user_buf,
2481 size_t count, loff_t *ppos)
16db88ba
EG		 2482{
2483 struct iwl_trans *trans = file->private_data;
94543a8d 2484 char *buf = NULL;
56c2477f 2485 ssize_t ret;
16db88ba 2486
56c2477f
JB		 2487 ret = iwl_dump_fh(trans, &buf);
2488 if (ret < 0)
2489 return ret;
2490 if (!buf)
2491 return -EINVAL;
2492 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2493 kfree(buf);
16db88ba
EG		 2494 return ret;
2495}
2496
1f7b6172 2497DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2498DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2499DEBUGFS_READ_FILE_OPS(rx_queue);
2500DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2501DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2502
f8a1edb7
JB		 2503/* Create the debugfs files and directories */
2504int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2505{
f8a1edb7
JB		 2506 struct dentry *dir = trans->dbgfs_dir;
2507
87e5666c
EG		 2508 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2509 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2510 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2511 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2512 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2513 return 0;
9da987ac
MV		 2514
2515err:
2516 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2517 return -ENOMEM;
87e5666c 2518}
aadede6e 2519#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2520
6983ba69 2521static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2522{
3cd1980b 2523 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2524 u32 cmdlen = 0;
2525 int i;
2526
3cd1980b 2527 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2528 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2529
2530 return cmdlen;
2531}
2532
bd7fc617
EG		 2533static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2534 struct iwl_fw_error_dump_data **data,
2535 int allocated_rb_nums)
2536{
2537 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2538 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2539 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2540 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2541 u32 i, r, j, rb_len = 0;
2542
2543 spin_lock(&rxq->lock);
2544
2545 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2546
2547 for (i = rxq->read, j = 0;
2548 i != r && j < allocated_rb_nums;
2549 i = (i + 1) & RX_QUEUE_MASK, j++) {
2550 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2551 struct iwl_fw_error_dump_rb *rb;
2552
2553 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2554 DMA_FROM_DEVICE);
2555
2556 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2557
2558 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2559 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2560 rb = (void *)(*data)->data;
2561 rb->index = cpu_to_le32(i);
2562 memcpy(rb->data, page_address(rxb->page), max_len);
2563 /* remap the page for the free benefit */
2564 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2565 max_len,
2566 DMA_FROM_DEVICE);
2567
2568 *data = iwl_fw_error_next_data(*data);
2569 }
2570
2571 spin_unlock(&rxq->lock);
2572
2573 return rb_len;
2574}
473ad712
EG		 2575#define IWL_CSR_TO_DUMP (0x250)
2576
2577static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2578 struct iwl_fw_error_dump_data **data)
2579{
2580 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2581 __le32 *val;
2582 int i;
2583
2584 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2585 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2586 val = (void *)(*data)->data;
2587
2588 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2589 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2590
2591 *data = iwl_fw_error_next_data(*data);
2592
2593 return csr_len;
2594}
2595
06d51e0d
LK		 2596static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2597 struct iwl_fw_error_dump_data **data)
2598{
2599 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2600 unsigned long flags;
2601 __le32 *val;
2602 int i;
2603
23ba9340 2604 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2605 return 0;
2606
2607 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2608 (*data)->len = cpu_to_le32(fh_regs_len);
2609 val = (void *)(*data)->data;
2610
2611 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2612 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2613
2614 iwl_trans_release_nic_access(trans, &flags);
2615
2616 *data = iwl_fw_error_next_data(*data);
2617
2618 return sizeof(**data) + fh_regs_len;
2619}
2620
cc79ef66
LK		 2621static u32
2622iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2623 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2624 u32 monitor_len)
2625{
2626 u32 buf_size_in_dwords = (monitor_len >> 2);
2627 u32 *buffer = (u32 *)fw_mon_data->data;
2628 unsigned long flags;
2629 u32 i;
2630
23ba9340 2631 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2632 return 0;
2633
14ef1b43 2634 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2635 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2636 buffer[i] = iwl_read_prph_no_grab(trans,
2637 MON_DMARB_RD_DATA_ADDR);
2638 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2639
2640 iwl_trans_release_nic_access(trans, &flags);
2641
2642 return monitor_len;
2643}
2644
36fb9017
OG		 2645static u32
2646iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2647 struct iwl_fw_error_dump_data **data,
2648 u32 monitor_len)
2649{
2650 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2651 u32 len = 0;
2652
2653 if ((trans_pcie->fw_mon_page &&
2654 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2655 trans->dbg_dest_tlv) {
2656 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2657 u32 base, write_ptr, wrap_cnt;
2658
2659 /* If there was a dest TLV - use the values from there */
2660 if (trans->dbg_dest_tlv) {
2661 write_ptr =
2662 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2663 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2664 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2665 } else {
2666 base = MON_BUFF_BASE_ADDR;
2667 write_ptr = MON_BUFF_WRPTR;
2668 wrap_cnt = MON_BUFF_CYCLE_CNT;
2669 }
2670
2671 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2672 fw_mon_data = (void *)(*data)->data;
2673 fw_mon_data->fw_mon_wr_ptr =
2674 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2675 fw_mon_data->fw_mon_cycle_cnt =
2676 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2677 fw_mon_data->fw_mon_base_ptr =
2678 cpu_to_le32(iwl_read_prph(trans, base));
2679
2680 len += sizeof(**data) + sizeof(*fw_mon_data);
2681 if (trans_pcie->fw_mon_page) {
2682 /*
2683 * The firmware is now asserted, it won't write anything
2684 * to the buffer. CPU can take ownership to fetch the
2685 * data. The buffer will be handed back to the device
2686 * before the firmware will be restarted.
2687 */
2688 dma_sync_single_for_cpu(trans->dev,
2689 trans_pcie->fw_mon_phys,
2690 trans_pcie->fw_mon_size,
2691 DMA_FROM_DEVICE);
2692 memcpy(fw_mon_data->data,
2693 page_address(trans_pcie->fw_mon_page),
2694 trans_pcie->fw_mon_size);
2695
2696 monitor_len = trans_pcie->fw_mon_size;
2697 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2698 /*
2699 * Update pointers to reflect actual values after
2700 * shifting
2701 */
2702 base = iwl_read_prph(trans, base) <<
2703 trans->dbg_dest_tlv->base_shift;
2704 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2705 monitor_len / sizeof(u32));
2706 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2707 monitor_len =
2708 iwl_trans_pci_dump_marbh_monitor(trans,
2709 fw_mon_data,
2710 monitor_len);
2711 } else {
2712 /* Didn't match anything - output no monitor data */
2713 monitor_len = 0;
2714 }
2715
2716 len += monitor_len;
2717 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2718 }
2719
2720 return len;
2721}
2722
2723static struct iwl_trans_dump_data
2724*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2725 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2726{
2727 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2728 struct iwl_fw_error_dump_data *data;
2729 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2730 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2731 struct iwl_trans_dump_data *dump_data;
bd7fc617 2732 u32 len, num_rbs;
99684ae3 2733 u32 monitor_len;
4d075007 2734 int i, ptr;
96a6497b
SS		 2735 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2736 !trans->cfg->mq_rx_supported;
4d075007 2737
473ad712
EG		 2738 /* transport dump header */
2739 len = sizeof(*dump_data);
2740
2741 /* host commands */
2742 len += sizeof(*data) +
bb98ecd4 2743 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2744
473ad712 2745 /* FW monitor */
99684ae3 2746 if (trans_pcie->fw_mon_page) {
c544e9c4 2747 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2748 trans_pcie->fw_mon_size;
2749 monitor_len = trans_pcie->fw_mon_size;
2750 } else if (trans->dbg_dest_tlv) {
2751 u32 base, end;
2752
2753 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2754 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2755
2756 base = iwl_read_prph(trans, base) <<
2757 trans->dbg_dest_tlv->base_shift;
2758 end = iwl_read_prph(trans, end) <<
2759 trans->dbg_dest_tlv->end_shift;
2760
2761 /* Make "end" point to the actual end */
cc79ef66
LK		 2762 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2763 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2764 end += (1 << trans->dbg_dest_tlv->end_shift);
2765 monitor_len = end - base;
2766 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2767 monitor_len;
2768 } else {
2769 monitor_len = 0;
2770 }
c2d20201 2771
36fb9017
OG		 2772 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2773 dump_data = vzalloc(len);
2774 if (!dump_data)
2775 return NULL;
2776
2777 data = (void *)dump_data->data;
2778 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2779 dump_data->len = len;
2780
2781 return dump_data;
2782 }
2783
2784 /* CSR registers */
2785 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2786
36fb9017
OG		 2787 /* FH registers */
2788 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2789
2790 if (dump_rbs) {
78485054
SS		 2791 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2792 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2793 /* RBs */
78485054 2794 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2795 & 0x0FFF;
78485054 2796 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2797 len += num_rbs * (sizeof(*data) +
2798 sizeof(struct iwl_fw_error_dump_rb) +
2799 (PAGE_SIZE << trans_pcie->rx_page_order));
2800 }
2801
48eb7b34
EG		 2802 dump_data = vzalloc(len);
2803 if (!dump_data)
2804 return NULL;
4d075007
JB		 2805
2806 len = 0;
48eb7b34 2807 data = (void *)dump_data->data;
4d075007
JB		 2808 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2809 txcmd = (void *)data->data;
2810 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 2811 ptr = cmdq->write_ptr;
2812 for (i = 0; i < cmdq->n_window; i++) {
2813 u8 idx = get_cmd_index(cmdq, ptr);
4d075007
JB		 2814 u32 caplen, cmdlen;
2815
6983ba69
SS		 2816 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2817 trans_pcie->tfd_size * ptr);
4d075007
JB		 2818 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2819
2820 if (cmdlen) {
2821 len += sizeof(*txcmd) + caplen;
2822 txcmd->cmdlen = cpu_to_le32(cmdlen);
2823 txcmd->caplen = cpu_to_le32(caplen);
2824 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2825 txcmd = (void *)((u8 *)txcmd->data + caplen);
2826 }
2827
2828 ptr = iwl_queue_dec_wrap(ptr);
2829 }
2830 spin_unlock_bh(&cmdq->lock);
2831
2832 data->len = cpu_to_le32(len);
c2d20201 2833 len += sizeof(*data);
67c65f2c
EG		 2834 data = iwl_fw_error_next_data(data);
2835
473ad712 2836 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2837 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2838 if (dump_rbs)
2839 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2840
36fb9017 2841 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2842
48eb7b34
EG		 2843 dump_data->len = len;
2844
2845 return dump_data;
4d075007 2846}
87e5666c 2847
4cbb8e50
LC		 2848#ifdef CONFIG_PM_SLEEP
2849static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2850{
2851 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2852 return iwl_pci_fw_enter_d0i3(trans);
2853
2854 return 0;
2855}
2856
2857static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2858{
2859 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2860 iwl_pci_fw_exit_d0i3(trans);
2861}
2862#endif /* CONFIG_PM_SLEEP */
2863
d1ff5253 2864static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2865 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2866 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2867 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2868 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2869 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2870
ddaf5a5b
JB		 2871 .d3_suspend = iwl_trans_pcie_d3_suspend,
2872 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2873
4cbb8e50
LC		 2874#ifdef CONFIG_PM_SLEEP
2875 .suspend = iwl_trans_pcie_suspend,
2876 .resume = iwl_trans_pcie_resume,
2877#endif /* CONFIG_PM_SLEEP */
2878
f02831be 2879 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2880
e6bb4c9c 2881 .tx = iwl_trans_pcie_tx,
a0eaad71 2882 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2883
d0624be6 2884 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2885 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2886
8aacf4b7
SS		 2887 .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table,
2888
42db09c1
LK		 2889 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2890
990aa6d7 2891 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2892 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
0cd58eaa 2893 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
5f178cd2 2894
03905495
EG		 2895 .write8 = iwl_trans_pcie_write8,
2896 .write32 = iwl_trans_pcie_write32,
2897 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2898 .read_prph = iwl_trans_pcie_read_prph,
2899 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2900 .read_mem = iwl_trans_pcie_read_mem,
2901 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2902 .configure = iwl_trans_pcie_configure,
47107e84 2903 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2904 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2905 .release_nic_access = iwl_trans_pcie_release_nic_access,
2906 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2907
7616f334
EP		 2908 .ref = iwl_trans_pcie_ref,
2909 .unref = iwl_trans_pcie_unref,
2910
4d075007 2911 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2912};
a42a1844 2913
87ce05a2 2914struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2915 const struct pci_device_id *ent,
2916 const struct iwl_cfg *cfg)
a42a1844 2917{
a42a1844
EG		 2918 struct iwl_trans_pcie *trans_pcie;
2919 struct iwl_trans *trans;
96a6497b 2920 int ret, addr_size;
a42a1844 2921
5a41a86c
SD		 2922 ret = pcim_enable_device(pdev);
2923 if (ret)
2924 return ERR_PTR(ret);
2925
7b501d10
JB		 2926 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2927 &pdev->dev, cfg, &trans_ops_pcie, 0);
2928 if (!trans)
2929 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2930
2931 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2932
a42a1844 2933 trans_pcie->trans = trans;
7b11488f 2934 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2935 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 2936 mutex_init(&trans_pcie->mutex);
13df1aab 2937 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2938 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2939 if (!trans_pcie->tso_hdr_page) {
2940 ret = -ENOMEM;
2941 goto out_no_pci;
2942 }
a42a1844 2943
d819c6cf 2944
f2532b04
EG		 2945 if (!cfg->base_params->pcie_l1_allowed) {
2946 /*
2947 * W/A - seems to solve weird behavior. We need to remove this
2948 * if we don't want to stay in L1 all the time. This wastes a
2949 * lot of power.
2950 */
2951 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2952 PCIE_LINK_STATE_L1 |
2953 PCIE_LINK_STATE_CLKPM);
2954 }
a42a1844 2955
6983ba69 2956 if (cfg->use_tfh) {
2c6262b7 2957 addr_size = 64;
3cd1980b 2958 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 2959 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 2960 } else {
2c6262b7 2961 addr_size = 36;
3cd1980b 2962 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 2963 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2964 }
3cd1980b
SS		 2965 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2966
a42a1844
EG		 2967 pci_set_master(pdev);
2968
96a6497b 2969 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 2970 if (!ret)
96a6497b
SS		 2971 ret = pci_set_consistent_dma_mask(pdev,
2972 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 2973 if (ret) {
2974 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2975 if (!ret)
2976 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2977 DMA_BIT_MASK(32));
a42a1844 2978 /* both attempts failed: */
af3f2f74 2979 if (ret) {
6a4b09f8 2980 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 2981 goto out_no_pci;
a42a1844
EG		 2982 }
2983 }
2984
5a41a86c 2985 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 2986 if (ret) {
5a41a86c
SD		 2987 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
2988 goto out_no_pci;
a42a1844
EG		 2989 }
2990
5a41a86c 2991 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 2992 if (!trans_pcie->hw_base) {
5a41a86c 2993 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 2994 ret = -ENODEV;
5a41a86c 2995 goto out_no_pci;
a42a1844
EG		 2996 }
2997
a42a1844
EG		 2998 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2999 * PCI Tx retries from interfering with C3 CPU state */
3000 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3001
83f7a85f
EG		 3002 trans->dev = &pdev->dev;
3003 trans_pcie->pci_dev = pdev;
3004 iwl_disable_interrupts(trans);
3005
08079a49 3006 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3007 /*
3008 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3009 * changed, and now the revision step also includes bit 0-1 (no more
3010 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3011 * in the old format.
3012 */
7a42baa6
EH		 3013 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
3014 unsigned long flags;
7a42baa6 3015
b513ee7f 3016 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3017 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3018
f9e5554c
EG		 3019 ret = iwl_pcie_prepare_card_hw(trans);
3020 if (ret) {
3021 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3022 goto out_no_pci;
f9e5554c
EG		 3023 }
3024
7a42baa6
EH		 3025 /*
3026 * in-order to recognize C step driver should read chip version
3027 * id located at the AUX bus MISC address space.
3028 */
3029 iwl_set_bit(trans, CSR_GP_CNTRL,
3030 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3031 udelay(2);
3032
3033 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3034 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3035 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3036 25000);
3037 if (ret < 0) {
3038 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3039 goto out_no_pci;
7a42baa6
EH		 3040 }
3041
23ba9340 3042 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3043 u32 hw_step;
3044
14ef1b43 3045 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3046 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3047 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3048 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3049 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3050 if (hw_step == 0x3)
3051 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3052 (SILICON_C_STEP << 2);
3053 iwl_trans_release_nic_access(trans, &flags);
3054 }
3055 }
3056
1afb0ae4
HD		 3057 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3058
2e5d4a8f 3059 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3060 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3061 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3062 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3063
69a10b29 3064 /* Initialize the wait queue for commands */
f946b529 3065 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3066
4cbb8e50
LC		 3067 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3068
2e5d4a8f
HD		 3069 if (trans_pcie->msix_enabled) {
3070 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
5a41a86c 3071 goto out_no_pci;
2e5d4a8f
HD		 3072 } else {
3073 ret = iwl_pcie_alloc_ict(trans);
3074 if (ret)
5a41a86c 3075 goto out_no_pci;
a8b691e6 3076
5a41a86c
SD		 3077 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3078 iwl_pcie_isr,
3079 iwl_pcie_irq_handler,
3080 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3081 if (ret) {
3082 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3083 goto out_free_ict;
3084 }
3085 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3086 }
83f7a85f 3087
b3ff1270
LC		 3088#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3089 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3090#else
3091 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3092#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3093
a42a1844
EG		 3094 return trans;
3095
a8b691e6
JB		 3096out_free_ict:
3097 iwl_pcie_free_ict(trans);
a42a1844 3098out_no_pci:
6eb5e529 3099 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3100 iwl_trans_free(trans);
af3f2f74 3101 return ERR_PTR(ret);
a42a1844 3102}
Linux 6.x block layer and io_uring tree(s)