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iwlwifi: mvm: support v4 of the TX power command
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 10 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 37 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
4d075007 83#include "iwl-fw-error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
c2d20201
EG		 91static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92{
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105}
106
96c285da 107static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 108{
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 110 struct page *page = NULL;
c2d20201 111 dma_addr_t phys;
96c285da 112 u32 size = 0;
c2d20201
EG		 113 u8 power;
114
96c285da
EG		 115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
c2d20201
EG		 127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
96c285da 135 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
553452e5 149 page = NULL;
c2d20201
EG		 150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
40a76905 158 if (WARN_ON_ONCE(!page))
c2d20201
EG		 159 return;
160
96c285da
EG		 161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
c2d20201
EG		 167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170}
171
a812cba9
AB		 172static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173{
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177}
178
179static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180{
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184}
185
ddaf5a5b 186static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 187{
66337b7c 188 if (trans->cfg->apmg_not_supported)
95411d04
AA		 189 return;
190
ddaf5a5b
JB		 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 199}
200
af634bee
EG		 201/* PCI registers */
202#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 203
7afe3705 204static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 205{
20d3b647 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 207 u16 lctl;
9180ac50 208 u16 cap;
af634bee 209
af634bee
EG		 210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
7afe3705 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 221 else
af634bee 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 230}
231
a6c684ee
EG		 232/*
233 * Start up NIC's basic functionality after it has been reset
7afe3705 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 235 * NOTE: This does not load uCode nor start the embedded processor
236 */
7afe3705 237static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 238{
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 268
7afe3705 269 iwl_pcie_apm_config(trans);
a6c684ee
EG		 270
271 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 363 usleep_range(1000, 2000);
a812cba9
AB		 364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 409 usleep_range(1000, 2000);
a812cba9
AB		 410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
b7aaeae4
EG		 491 mdelay(5);
492 }
493
eb7ff77e 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 495
496 /* Stop device's DMA activity */
7afe3705 497 iwl_pcie_apm_stop_master(trans);
cc56feb2 498
a812cba9
AB		 499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
cc56feb2
EG		 504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 506 usleep_range(1000, 2000);
cc56feb2
EG		 507
508 /*
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
511 */
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
514}
515
7afe3705 516static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 517{
7b11488f 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 519
520 /* nic_init */
7b70bd63 521 spin_lock(&trans_pcie->irq_lock);
7afe3705 522 iwl_pcie_apm_init(trans);
392f8b78 523
7b70bd63 524 spin_unlock(&trans_pcie->irq_lock);
392f8b78 525
95411d04 526 iwl_pcie_set_pwr(trans, false);
392f8b78 527
ecdb975c 528 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 529
530 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 531 iwl_pcie_rx_init(trans);
392f8b78
EG		 532
533 /* Allocate or reset and init all Tx and Command queues */
f02831be 534 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 535 return -ENOMEM;
536
035f7ff2 537 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 538 /* enable shadow regs in HW */
20d3b647 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 541 }
542
392f8b78
EG		 543 return 0;
544}
545
546#define HW_READY_TIMEOUT (50)
547
548/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 549static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 550{
551 int ret;
552
1042db2a 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 555
556 /* See if we got it */
1042db2a 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 HW_READY_TIMEOUT);
392f8b78 561
6a08f514
EG		 562 if (ret >= 0)
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
564
6d8f6eeb 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 566 return ret;
567}
568
569/* Note: returns standard 0/-ERROR code */
7afe3705 570static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 571{
572 int ret;
289e5501 573 int t = 0;
501fd989 574 int iter;
392f8b78 575
6d8f6eeb 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 577
7afe3705 578 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 579 /* If the card is ready, exit 0 */
392f8b78
EG		 580 if (ret >= 0)
581 return 0;
582
c9fdec9f
EG		 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 585 usleep_range(1000, 2000);
c9fdec9f 586
501fd989
EG		 587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
591
592 do {
593 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 594 if (ret >= 0)
595 return 0;
392f8b78 596
501fd989
EG		 597 usleep_range(200, 1000);
598 t += 200;
599 } while (t < 150000);
600 msleep(25);
601 }
392f8b78 602
7f2ac8fb 603 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 604
392f8b78
EG		 605 return ret;
606}
607
cf614297
EG		 608/*
609 * ucode
610 */
564cdce7
SS		 611static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
613 u32 byte_cnt)
cf614297 614{
bac842da
EG		 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
617
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
619 dst_addr);
620
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
623
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 637}
638
639static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
641 u32 byte_cnt)
642{
643 /* Stop DMA channel */
644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0);
645
646 /* Configure SRAM address */
647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR,
648 dst_addr);
649
650 /* Configure DRAM address - 64 bit */
651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr);
bac842da 652
564cdce7
SS		 653 /* Configure byte count to transfer */
654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt);
655
656 /* Enable the DRAM2SRAM to start */
657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP |
658 TFH_SRV_DMA_TO_DRIVER |
659 TFH_SRV_DMA_START);
660}
661
662static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
663 u32 dst_addr, dma_addr_t phy_addr,
664 u32 byte_cnt)
665{
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
667 unsigned long flags;
668 int ret;
669
670 trans_pcie->ucode_write_complete = false;
671
672 if (!iwl_trans_grab_nic_access(trans, &flags))
673 return -EIO;
674
675 if (trans->cfg->use_tfh)
676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr,
677 byte_cnt);
678 else
679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
680 byte_cnt);
bac842da 681 iwl_trans_release_nic_access(trans, &flags);
cf614297 682
13df1aab
JB		 683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
684 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 685 if (!ret) {
83f84d7b 686 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 687 return -ETIMEDOUT;
688 }
689
690 return 0;
691}
692
7afe3705 693static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 694 const struct fw_desc *section)
cf614297 695{
83f84d7b
JB		 696 u8 *v_addr;
697 dma_addr_t p_addr;
baa21e83 698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 699 int ret = 0;
700
83f84d7b
JB		 701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
702 section_num);
703
c571573a
EG		 704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
705 GFP_KERNEL | __GFP_NOWARN);
706 if (!v_addr) {
707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
708 chunk_sz = PAGE_SIZE;
709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
710 &p_addr, GFP_KERNEL);
711 if (!v_addr)
712 return -ENOMEM;
713 }
83f84d7b 714
c571573a 715 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 716 u32 copy_size, dst_addr;
717 bool extended_addr = false;
83f84d7b 718
c571573a 719 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 720 dst_addr = section->offset + offset;
721
722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
723 dst_addr <= IWL_FW_MEM_EXTENDED_END)
724 extended_addr = true;
725
726 if (extended_addr)
727 iwl_set_bits_prph(trans, LMPM_CHICK,
728 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 729
83f84d7b 730 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
732 copy_size);
733
734 if (extended_addr)
735 iwl_clear_bits_prph(trans, LMPM_CHICK,
736 LMPM_CHICK_EXTENDED_ADDR_SPACE);
737
83f84d7b
JB		 738 if (ret) {
739 IWL_ERR(trans,
740 "Could not load the [%d] uCode section\n",
741 section_num);
742 break;
6dfa8d01 743 }
83f84d7b
JB		 744 }
745
c571573a 746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 747 return ret;
748}
749
16bc119b
EH		 750/*
751 * Driver Takes the ownership on secure machine before FW load
752 * and prevent race with the BT load.
753 * W/A for ROM bug. (should be remove in the next Si step)
754 */
755static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
756{
757 u32 val, loop = 1000;
758
1e167071
EH		 759 /*
760 * Check the RSA semaphore is accessible.
761 * If the HW isn't locked and the rsa semaphore isn't accessible,
762 * we are in trouble.
763 */
16bc119b
EH		 764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
765 if (val & (BIT(1) | BIT(17))) {
9fc515bc
EG		 766 IWL_DEBUG_INFO(trans,
767 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 768 return 0;
769 }
770
771 /* take ownership on the AUX IF */
772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
774
775 do {
776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
778 if (val == 0x1) {
779 iwl_write_prph(trans, RSA_ENABLE, 0);
780 return 0;
781 }
782
783 udelay(10);
784 loop--;
785 } while (loop > 0);
786
787 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
788 return -EIO;
789}
790
5dd9c68a
EG		 791static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
792 const struct fw_img *image,
793 int cpu,
794 int *first_ucode_section)
e2d6f4e7
EH		 795{
796 int shift_param;
dcab8ecd
EH		 797 int i, ret = 0, sec_num = 0x1;
798 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 799
800 if (cpu == 1) {
801 shift_param = 0;
034846cf 802 *first_ucode_section = 0;
e2d6f4e7
EH		 803 } else {
804 shift_param = 16;
034846cf 805 (*first_ucode_section)++;
e2d6f4e7
EH		 806 }
807
034846cf
EH		 808 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
809 last_read_idx = i;
810
a6c4fb44
MG		 811 /*
812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
813 * CPU1 to CPU2.
814 * PAGING_SEPARATOR_SECTION delimiter - separate between
815 * CPU2 non paged to CPU2 paging sec.
816 */
034846cf 817 if (!image->sec[i].data ||
a6c4fb44
MG		 818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 820 IWL_DEBUG_FW(trans,
821 "Break since Data not valid or Empty section, sec = %d\n",
822 i);
189fa2fa 823 break;
034846cf
EH		 824 }
825
189fa2fa
EH		 826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
827 if (ret)
828 return ret;
dcab8ecd
EH		 829
830 /* Notify the ucode of the loaded section number and status */
831 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
832 val = val | (sec_num << shift_param);
833 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
834 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 835 }
836
034846cf
EH		 837 *first_ucode_section = last_read_idx;
838
2aabdbdc
EG		 839 iwl_enable_interrupts(trans);
840
afb88917
EH		 841 if (cpu == 1)
842 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
843 else
844 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
845
189fa2fa
EH		 846 return 0;
847}
e2d6f4e7 848
189fa2fa
EH		 849static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
850 const struct fw_img *image,
034846cf
EH		 851 int cpu,
852 int *first_ucode_section)
189fa2fa
EH		 853{
854 int shift_param;
189fa2fa 855 int i, ret = 0;
034846cf 856 u32 last_read_idx = 0;
189fa2fa
EH		 857
858 if (cpu == 1) {
859 shift_param = 0;
034846cf 860 *first_ucode_section = 0;
189fa2fa
EH		 861 } else {
862 shift_param = 16;
034846cf 863 (*first_ucode_section)++;
189fa2fa
EH		 864 }
865
034846cf
EH		 866 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
867 last_read_idx = i;
868
a6c4fb44
MG		 869 /*
870 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
871 * CPU1 to CPU2.
872 * PAGING_SEPARATOR_SECTION delimiter - separate between
873 * CPU2 non paged to CPU2 paging sec.
874 */
034846cf 875 if (!image->sec[i].data ||
a6c4fb44
MG		 876 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
877 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 878 IWL_DEBUG_FW(trans,
879 "Break since Data not valid or Empty section, sec = %d\n",
880 i);
189fa2fa 881 break;
034846cf
EH		 882 }
883
189fa2fa
EH		 884 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
885 if (ret)
886 return ret;
e2d6f4e7
EH		 887 }
888
189fa2fa
EH		 889 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
890 iwl_set_bits_prph(trans,
891 CSR_UCODE_LOAD_STATUS_ADDR,
892 (LMPM_CPU_UCODE_LOADING_COMPLETED |
893 LMPM_CPU_HDRS_LOADING_COMPLETED |
894 LMPM_CPU_UCODE_LOADING_STARTED) <<
895 shift_param);
896
034846cf
EH		 897 *first_ucode_section = last_read_idx;
898
e2d6f4e7
EH		 899 return 0;
900}
901
09e350f7
LK		 902static void iwl_pcie_apply_destination(struct iwl_trans *trans)
903{
904 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
905 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
906 int i;
907
908 if (dest->version)
909 IWL_ERR(trans,
910 "DBG DEST version is %d - expect issues\n",
911 dest->version);
912
913 IWL_INFO(trans, "Applying debug destination %s\n",
914 get_fw_dbg_mode_string(dest->monitor_mode));
915
916 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 917 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 918 else
919 IWL_WARN(trans, "PCI should have external buffer debug\n");
920
921 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
922 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
923 u32 val = le32_to_cpu(dest->reg_ops[i].val);
924
925 switch (dest->reg_ops[i].op) {
926 case CSR_ASSIGN:
927 iwl_write32(trans, addr, val);
928 break;
929 case CSR_SETBIT:
930 iwl_set_bit(trans, addr, BIT(val));
931 break;
932 case CSR_CLEARBIT:
933 iwl_clear_bit(trans, addr, BIT(val));
934 break;
935 case PRPH_ASSIGN:
936 iwl_write_prph(trans, addr, val);
937 break;
938 case PRPH_SETBIT:
939 iwl_set_bits_prph(trans, addr, BIT(val));
940 break;
941 case PRPH_CLEARBIT:
942 iwl_clear_bits_prph(trans, addr, BIT(val));
943 break;
869f3b15
HD		 944 case PRPH_BLOCKBIT:
945 if (iwl_read_prph(trans, addr) & BIT(val)) {
946 IWL_ERR(trans,
947 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
948 val, addr);
949 goto monitor;
950 }
951 break;
09e350f7
LK		 952 default:
953 IWL_ERR(trans, "FW debug - unknown OP %d\n",
954 dest->reg_ops[i].op);
955 break;
956 }
957 }
958
869f3b15 959monitor:
09e350f7
LK		 960 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
961 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
962 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 963 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
964 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
965 (trans_pcie->fw_mon_phys +
966 trans_pcie->fw_mon_size - 256) >>
967 dest->end_shift);
968 else
969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
970 (trans_pcie->fw_mon_phys +
971 trans_pcie->fw_mon_size) >>
972 dest->end_shift);
09e350f7
LK		 973 }
974}
975
7afe3705 976static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 977 const struct fw_img *image)
cf614297 978{
c2d20201 979 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 980 int ret = 0;
034846cf 981 int first_ucode_section;
cf614297 982
dcab8ecd 983 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 984 image->is_dual_cpus ? "Dual" : "Single");
985
dcab8ecd
EH		 986 /* load to FW the binary non secured sections of CPU1 */
987 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
988 if (ret)
989 return ret;
e2d6f4e7
EH		 990
991 if (image->is_dual_cpus) {
189fa2fa
EH		 992 /* set CPU2 header address */
993 iwl_write_prph(trans,
994 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
995 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 996
189fa2fa 997 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 998 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
999 &first_ucode_section);
189fa2fa
EH		 1000 if (ret)
1001 return ret;
e2d6f4e7 1002 }
cf614297 1003
c2d20201
EG		 1004 /* supported for 7000 only for the moment */
1005 if (iwlwifi_mod_params.fw_monitor &&
1006 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1007 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1008
1009 if (trans_pcie->fw_mon_size) {
1010 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1011 trans_pcie->fw_mon_phys >> 4);
1012 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1013 (trans_pcie->fw_mon_phys +
1014 trans_pcie->fw_mon_size) >> 4);
1015 }
09e350f7
LK		 1016 } else if (trans->dbg_dest_tlv) {
1017 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1018 }
1019
2aabdbdc
EG		 1020 iwl_enable_interrupts(trans);
1021
e12ba844 1022 /* release CPU reset */
5dd9c68a 1023 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1024
dcab8ecd
EH		 1025 return 0;
1026}
189fa2fa 1027
5dd9c68a
EG		 1028static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1029 const struct fw_img *image)
dcab8ecd
EH		 1030{
1031 int ret = 0;
1032 int first_ucode_section;
dcab8ecd
EH		 1033
1034 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1035 image->is_dual_cpus ? "Dual" : "Single");
1036
a2227ce2
EG		 1037 if (trans->dbg_dest_tlv)
1038 iwl_pcie_apply_destination(trans);
1039
16bc119b
EH		 1040 /* TODO: remove in the next Si step */
1041 ret = iwl_pcie_rsa_race_bug_wa(trans);
1042 if (ret)
1043 return ret;
1044
dcab8ecd
EH		 1045 /* configure the ucode to be ready to get the secured image */
1046 /* release CPU reset */
1047 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1048
1049 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1050 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1051 &first_ucode_section);
dcab8ecd
EH		 1052 if (ret)
1053 return ret;
1054
1055 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1056 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1057 &first_ucode_section);
cf614297
EG		 1058}
1059
fa9f3281 1060static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1061{
43e58856 1062 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1063 bool hw_rfkill, was_hw_rfkill;
1064
fa9f3281
EG		 1065 lockdep_assert_held(&trans_pcie->mutex);
1066
1067 if (trans_pcie->is_down)
1068 return;
1069
1070 trans_pcie->is_down = true;
1071
3dc3374f 1072 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1073
43e58856 1074 /* tell the device to stop sending interrupts */
ae2c30bf 1075 iwl_disable_interrupts(trans);
ae2c30bf 1076
ab6cf8e8 1077 /* device going down, Stop using ICT table */
990aa6d7 1078 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1079
1080 /*
1081 * If a HW restart happens during firmware loading,
1082 * then the firmware loading might call this function
1083 * and later it might be called again due to the
1084 * restart. So don't process again if the device is
1085 * already dead.
1086 */
31b8b343 1087 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1088 IWL_DEBUG_INFO(trans,
1089 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1090 iwl_pcie_tx_stop(trans);
9805c446 1091 iwl_pcie_rx_stop(trans);
6379103e 1092
ab6cf8e8 1093 /* Power-down device's busmaster DMA clocks */
95411d04 1094 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1095 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1096 APMG_CLK_VAL_DMA_CLK_RQT);
1097 udelay(5);
1098 }
ab6cf8e8
EG		 1099 }
1100
1101 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1102 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1104
1105 /* Stop the device, and put it in low power state */
b7aaeae4 1106 iwl_pcie_apm_stop(trans, false);
43e58856 1107
03d6c3b0
EG		 1108 /* stop and reset the on-board processor */
1109 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1110 usleep_range(1000, 2000);
03d6c3b0
EG		 1111
1112 /*
1113 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1114 * This is a bug in certain verions of the hardware.
1115 * Certain devices also keep sending HW RF kill interrupt all
1116 * the time, unless the interrupt is ACKed even if the interrupt
1117 * should be masked. Re-ACK all the interrupts here.
43e58856 1118 */
43e58856 1119 iwl_disable_interrupts(trans);
43e58856 1120
74fda971 1121 /* clear all status bits */
eb7ff77e
AN		 1122 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1123 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1124 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1125 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1126
1127 /*
1128 * Even if we stop the HW, we still want the RF kill
1129 * interrupt
1130 */
1131 iwl_enable_rfkill_int(trans);
1132
1133 /*
1134 * Check again since the RF kill state may have changed while
1135 * all the interrupts were disabled, in this case we couldn't
1136 * receive the RF kill interrupt and update the state in the
1137 * op_mode.
3dc3374f
EG		 1138 * Don't call the op_mode if the rkfill state hasn't changed.
1139 * This allows the op_mode to call stop_device from the rfkill
1140 * notification without endless recursion. Under very rare
1141 * circumstances, we might have a small recursion if the rfkill
1142 * state changed exactly now while we were called from stop_device.
1143 * This is very unlikely but can happen and is supported.
a4082843
AN		 1144 */
1145 hw_rfkill = iwl_is_rfkill_set(trans);
1146 if (hw_rfkill)
eb7ff77e 1147 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1148 else
eb7ff77e 1149 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1150 if (hw_rfkill != was_hw_rfkill)
14cfca71 1151 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0 1152
a6bd005f 1153 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1154 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1155}
1156
2e5d4a8f
HD		 1157static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1158{
1159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1160
1161 if (trans_pcie->msix_enabled) {
1162 int i;
1163
1164 for (i = 0; i < trans_pcie->allocated_vector; i++)
1165 synchronize_irq(trans_pcie->msix_entries[i].vector);
1166 } else {
1167 synchronize_irq(trans_pcie->pci_dev->irq);
1168 }
1169}
1170
a6bd005f
EG		 1171static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1172 const struct fw_img *fw, bool run_in_rfkill)
1173{
1174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1175 bool hw_rfkill;
1176 int ret;
1177
1178 /* This may fail if AMT took ownership of the device */
1179 if (iwl_pcie_prepare_card_hw(trans)) {
1180 IWL_WARN(trans, "Exit HW not ready\n");
1181 ret = -EIO;
1182 goto out;
1183 }
1184
1185 iwl_enable_rfkill_int(trans);
1186
1187 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1188
1189 /*
1190 * We enabled the RF-Kill interrupt and the handler may very
1191 * well be running. Disable the interrupts to make sure no other
1192 * interrupt can be fired.
1193 */
1194 iwl_disable_interrupts(trans);
1195
1196 /* Make sure it finished running */
2e5d4a8f 1197 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1198
1199 mutex_lock(&trans_pcie->mutex);
1200
1201 /* If platform's RF_KILL switch is NOT set to KILL */
1202 hw_rfkill = iwl_is_rfkill_set(trans);
1203 if (hw_rfkill)
1204 set_bit(STATUS_RFKILL, &trans->status);
1205 else
1206 clear_bit(STATUS_RFKILL, &trans->status);
1207 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1208 if (hw_rfkill && !run_in_rfkill) {
1209 ret = -ERFKILL;
1210 goto out;
1211 }
1212
1213 /* Someone called stop_device, don't try to start_fw */
1214 if (trans_pcie->is_down) {
1215 IWL_WARN(trans,
1216 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1217 ret = -EIO;
a6bd005f
EG		 1218 goto out;
1219 }
1220
1221 /* make sure rfkill handshake bits are cleared */
1222 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1223 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1224 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1225
1226 /* clear (again), then enable host interrupts */
1227 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1228
1229 ret = iwl_pcie_nic_init(trans);
1230 if (ret) {
1231 IWL_ERR(trans, "Unable to init nic\n");
1232 goto out;
1233 }
1234
1235 /*
1236 * Now, we load the firmware and don't want to be interrupted, even
1237 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1238 * FH_TX interrupt which is needed to load the firmware). If the
1239 * RF-Kill switch is toggled, we will find out after having loaded
1240 * the firmware and return the proper value to the caller.
1241 */
1242 iwl_enable_fw_load_int(trans);
1243
1244 /* really make sure rfkill handshake bits are cleared */
1245 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1246 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1247
1248 /* Load the given image to the HW */
1249 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1250 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1251 else
1252 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1253
1254 /* re-check RF-Kill state since we may have missed the interrupt */
1255 hw_rfkill = iwl_is_rfkill_set(trans);
1256 if (hw_rfkill)
1257 set_bit(STATUS_RFKILL, &trans->status);
1258 else
1259 clear_bit(STATUS_RFKILL, &trans->status);
1260
1261 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1262 if (hw_rfkill && !run_in_rfkill)
1263 ret = -ERFKILL;
1264
1265out:
1266 mutex_unlock(&trans_pcie->mutex);
1267 return ret;
1268}
1269
1270static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1271{
1272 iwl_pcie_reset_ict(trans);
1273 iwl_pcie_tx_start(trans, scd_addr);
1274}
1275
fa9f3281
EG		 1276static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1277{
1278 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1279
1280 mutex_lock(&trans_pcie->mutex);
1281 _iwl_trans_pcie_stop_device(trans, low_power);
1282 mutex_unlock(&trans_pcie->mutex);
1283}
1284
14cfca71
JB		 1285void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1286{
fa9f3281
EG		 1287 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1288 IWL_TRANS_GET_PCIE_TRANS(trans);
1289
1290 lockdep_assert_held(&trans_pcie->mutex);
1291
14cfca71 1292 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1293 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1294}
1295
23ae6128
MG		 1296static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1297 bool reset)
2dd4f9f7 1298{
23ae6128 1299 if (!reset) {
6dfb36c8
EP		 1300 /* Enable persistence mode to avoid reset */
1301 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1302 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1303 }
1304
2dd4f9f7 1305 iwl_disable_interrupts(trans);
debff618
JB		 1306
1307 /*
1308 * in testing mode, the host stays awake and the
1309 * hardware won't be reset (not even partially)
1310 */
1311 if (test)
1312 return;
1313
ddaf5a5b
JB		 1314 iwl_pcie_disable_ict(trans);
1315
2e5d4a8f 1316 iwl_pcie_synchronize_irqs(trans);
33b56af1 1317
2dd4f9f7
JB		 1318 iwl_clear_bit(trans, CSR_GP_CNTRL,
1319 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1320 iwl_clear_bit(trans, CSR_GP_CNTRL,
1321 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1322
1316d595
SS		 1323 iwl_pcie_enable_rx_wake(trans, false);
1324
23ae6128 1325 if (reset) {
6dfb36c8
EP		 1326 /*
1327 * reset TX queues -- some of their registers reset during S3
1328 * so if we don't reset everything here the D3 image would try
1329 * to execute some invalid memory upon resume
1330 */
1331 iwl_trans_pcie_tx_reset(trans);
1332 }
ddaf5a5b
JB		 1333
1334 iwl_pcie_set_pwr(trans, true);
1335}
1336
1337static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1338 enum iwl_d3_status *status,
23ae6128 1339 bool test, bool reset)
ddaf5a5b
JB		 1340{
1341 u32 val;
1342 int ret;
1343
debff618
JB		 1344 if (test) {
1345 iwl_enable_interrupts(trans);
1346 *status = IWL_D3_STATUS_ALIVE;
1347 return 0;
1348 }
1349
1316d595
SS		 1350 iwl_pcie_enable_rx_wake(trans, true);
1351
ddaf5a5b
JB		 1352 /*
1353 * Also enables interrupts - none will happen as the device doesn't
1354 * know we're waking it up, only when the opmode actually tells it
1355 * after this call.
1356 */
1357 iwl_pcie_reset_ict(trans);
18dcb9a9 1358 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1359
1360 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1361 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1362
01e58a28
EG		 1363 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1364 udelay(2);
1365
ddaf5a5b
JB		 1366 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1367 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1368 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1369 25000);
7f2ac8fb 1370 if (ret < 0) {
ddaf5a5b
JB		 1371 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1372 return ret;
1373 }
1374
a3ead656
EG		 1375 iwl_pcie_set_pwr(trans, false);
1376
23ae6128 1377 if (!reset) {
6dfb36c8
EP		 1378 iwl_clear_bit(trans, CSR_GP_CNTRL,
1379 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1380 } else {
1381 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1382
6dfb36c8
EP		 1383 ret = iwl_pcie_rx_init(trans);
1384 if (ret) {
1385 IWL_ERR(trans,
1386 "Failed to resume the device (RX reset)\n");
1387 return ret;
1388 }
ddaf5a5b
JB		 1389 }
1390
a3ead656
EG		 1391 val = iwl_read32(trans, CSR_RESET);
1392 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1393 *status = IWL_D3_STATUS_RESET;
1394 else
1395 *status = IWL_D3_STATUS_ALIVE;
1396
ddaf5a5b 1397 return 0;
2dd4f9f7
JB		 1398}
1399
2e5d4a8f
HD		 1400struct iwl_causes_list {
1401 u32 cause_num;
1402 u32 mask_reg;
1403 u8 addr;
1404};
1405
1406static struct iwl_causes_list causes_list[] = {
1407 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1408 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1409 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1410 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1411 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1412 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1413 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1414 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1415 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1416 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1417 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1418 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1419 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1420 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1421};
1422
1423static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1424{
1425 u32 val, max_rx_vector, i;
1426 struct iwl_trans *trans = trans_pcie->trans;
1427
1428 max_rx_vector = trans_pcie->allocated_vector - 1;
1429
54f315cb
IY		 1430 if (!trans_pcie->msix_enabled) {
1431 if (trans->cfg->mq_rx_supported)
1432 iwl_write_prph(trans, UREG_CHICK,
1433 UREG_CHICK_MSI_ENABLE);
2e5d4a8f 1434 return;
54f315cb 1435 }
2e5d4a8f
HD		 1436
1437 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1438
1439 /*
1440 * Each cause from the list above and the RX causes is represented as
1441 * a byte in the IVAR table. We access the first (N - 1) bytes and map
1442 * them to the (N - 1) vectors so these vectors will be used as rx
1443 * vectors. Then access all non rx causes and map them to the
1444 * default queue (N'th queue).
1445 */
1446 for (i = 0; i < max_rx_vector; i++) {
1447 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i));
1448 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD,
1449 BIT(MSIX_FH_INT_CAUSES_Q(i)));
1450 }
1451
1452 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1453 val = trans_pcie->default_irq_num |
1454 MSIX_NON_AUTO_CLEAR_CAUSE;
1455 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1456 iwl_clear_bit(trans, causes_list[i].mask_reg,
1457 causes_list[i].cause_num);
1458 }
1459 trans_pcie->fh_init_mask =
1460 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1461 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1462 trans_pcie->hw_init_mask =
1463 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1464 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1465}
1466
1467static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1468 struct iwl_trans *trans)
1469{
1470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1471 u16 pci_cmd;
1472 int max_vector;
1473 int ret, i;
1474
1475 if (trans->cfg->mq_rx_supported) {
013a67ea 1476 max_vector = min_t(u32, (num_possible_cpus() + 2),
2e5d4a8f
HD		 1477 IWL_MAX_RX_HW_QUEUES);
1478 for (i = 0; i < max_vector; i++)
1479 trans_pcie->msix_entries[i].entry = i;
1480
1481 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1482 MSIX_MIN_INTERRUPT_VECTORS,
1483 max_vector);
1484 if (ret > 1) {
1485 IWL_DEBUG_INFO(trans,
1486 "Enable MSI-X allocate %d interrupt vector\n",
1487 ret);
1488 trans_pcie->allocated_vector = ret;
1489 trans_pcie->default_irq_num =
1490 trans_pcie->allocated_vector - 1;
1491 trans_pcie->trans->num_rx_queues =
1492 trans_pcie->allocated_vector - 1;
1493 trans_pcie->msix_enabled = true;
1494
1495 return;
1496 }
1497 IWL_DEBUG_INFO(trans,
1498 "ret = %d %s move to msi mode\n", ret,
1499 (ret == 1) ?
1500 "can't allocate more than 1 interrupt vector" :
1501 "failed to enable msi-x mode");
1502 pci_disable_msix(pdev);
1503 }
1504
1505 ret = pci_enable_msi(pdev);
1506 if (ret) {
6ed5e4d6 1507 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1508 /* enable rfkill interrupt: hw bug w/a */
1509 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1510 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1511 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1512 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1513 }
1514 }
1515}
1516
1517static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1518 struct iwl_trans_pcie *trans_pcie)
1519{
1520 int i, last_vector;
1521
1522 last_vector = trans_pcie->trans->num_rx_queues;
1523
1524 for (i = 0; i < trans_pcie->allocated_vector; i++) {
1525 int ret;
1526
1527 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector,
1528 iwl_pcie_msix_isr,
1529 (i == last_vector) ?
1530 iwl_pcie_irq_msix_handler :
1531 iwl_pcie_irq_rx_msix_handler,
1532 IRQF_SHARED,
1533 DRV_NAME,
1534 &trans_pcie->msix_entries[i]);
1535 if (ret) {
1536 int j;
1537
1538 IWL_ERR(trans_pcie->trans,
1539 "Error allocating IRQ %d\n", i);
1540 for (j = 0; j < i; j++)
8d80717a
HD		 1541 free_irq(trans_pcie->msix_entries[j].vector,
1542 &trans_pcie->msix_entries[j]);
2e5d4a8f
HD		 1543 pci_disable_msix(pdev);
1544 return ret;
1545 }
1546 }
1547
1548 return 0;
1549}
1550
fa9f3281 1551static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1552{
fa9f3281 1553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1554 bool hw_rfkill;
a8b691e6 1555 int err;
e6bb4c9c 1556
fa9f3281
EG		 1557 lockdep_assert_held(&trans_pcie->mutex);
1558
7afe3705 1559 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1560 if (err) {
d6f1c316 1561 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1562 return err;
ebb7678d 1563 }
a6c684ee 1564
2997494f 1565 /* Reset the entire device */
ce836c76 1566 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1567 usleep_range(1000, 2000);
2997494f 1568
7afe3705 1569 iwl_pcie_apm_init(trans);
a6c684ee 1570
2e5d4a8f 1571 iwl_pcie_init_msix(trans_pcie);
226c02ca
EG		 1572 /* From now on, the op_mode will be kept updated about RF kill state */
1573 iwl_enable_rfkill_int(trans);
1574
fa9f3281
EG		 1575 /* Set is_down to false here so that...*/
1576 trans_pcie->is_down = false;
1577
8d425517 1578 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1579 if (hw_rfkill)
eb7ff77e 1580 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1581 else
eb7ff77e 1582 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1583 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1584 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1585
4cbb8e50
LC		 1586 /* Make sure we sync here, because we'll need full access later */
1587 if (low_power)
1588 pm_runtime_resume(trans->dev);
1589
a8b691e6 1590 return 0;
e6bb4c9c
EG		 1591}
1592
fa9f3281
EG		 1593static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1594{
1595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1596 int ret;
1597
1598 mutex_lock(&trans_pcie->mutex);
1599 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1600 mutex_unlock(&trans_pcie->mutex);
1601
1602 return ret;
1603}
1604
a4082843 1605static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1606{
20d3b647 1607 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1608
fa9f3281
EG		 1609 mutex_lock(&trans_pcie->mutex);
1610
a4082843 1611 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1612 iwl_disable_interrupts(trans);
ee7d737c 1613
b7aaeae4 1614 iwl_pcie_apm_stop(trans, true);
cc56feb2 1615
218733cf 1616 iwl_disable_interrupts(trans);
1df06bdc 1617
8d96bb61 1618 iwl_pcie_disable_ict(trans);
33b56af1 1619
fa9f3281 1620 mutex_unlock(&trans_pcie->mutex);
33b56af1 1621
2e5d4a8f 1622 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1623}
1624
03905495
EG		 1625static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1626{
05f5b97e 1627 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1628}
1629
1630static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1631{
05f5b97e 1632 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1633}
1634
1635static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1636{
05f5b97e 1637 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1638}
1639
6a06b6c1
EG		 1640static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1641{
f9477c17
AP		 1642 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1643 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1644 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1645}
1646
1647static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1648 u32 val)
1649{
1650 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1651 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1652 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1653}
1654
c6f600fc 1655static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1656 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1657{
1658 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1659
1660 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1661 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1662 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1663 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1664 trans_pcie->n_no_reclaim_cmds = 0;
1665 else
1666 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1667 if (trans_pcie->n_no_reclaim_cmds)
1668 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1669 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1670
6c4fbcbc
EG		 1671 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1672 trans_pcie->rx_page_order =
1673 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1674
ab02165c 1675 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
046db346 1676 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1677 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1678 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1679
21cb3222
JB		 1680 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1681 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1682
39bdb17e
SD		 1683 trans->command_groups = trans_cfg->command_groups;
1684 trans->command_groups_size = trans_cfg->command_groups_size;
1685
f14d6b39
JB		 1686 /* Initialize NAPI here - it should be before registering to mac80211
1687 * in the opmode but after the HW struct is allocated.
1688 * As this function may be called again in some corner cases don't
1689 * do anything if NAPI was already initialized.
1690 */
bce97731 1691 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1692 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1693}
1694
d1ff5253 1695void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1696{
20d3b647 1697 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1698 int i;
a42a1844 1699
2e5d4a8f 1700 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1701
f02831be 1702 iwl_pcie_tx_free(trans);
9805c446 1703 iwl_pcie_rx_free(trans);
6379103e 1704
2e5d4a8f
HD		 1705 if (trans_pcie->msix_enabled) {
1706 for (i = 0; i < trans_pcie->allocated_vector; i++)
1707 free_irq(trans_pcie->msix_entries[i].vector,
1708 &trans_pcie->msix_entries[i]);
1709
1710 pci_disable_msix(trans_pcie->pci_dev);
1711 trans_pcie->msix_enabled = false;
1712 } else {
1713 free_irq(trans_pcie->pci_dev->irq, trans);
a42a1844 1714
2e5d4a8f
HD		 1715 iwl_pcie_free_ict(trans);
1716
1717 pci_disable_msi(trans_pcie->pci_dev);
1718 }
05f5b97e 1719 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1720 pci_release_regions(trans_pcie->pci_dev);
1721 pci_disable_device(trans_pcie->pci_dev);
1722
c2d20201
EG		 1723 iwl_pcie_free_fw_monitor(trans);
1724
6eb5e529
EG		 1725 for_each_possible_cpu(i) {
1726 struct iwl_tso_hdr_page *p =
1727 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1728
1729 if (p->page)
1730 __free_page(p->page);
1731 }
1732
1733 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1734 mutex_destroy(&trans_pcie->mutex);
7b501d10 1735 iwl_trans_free(trans);
34c1b7ba
EG		 1736}
1737
47107e84
DF		 1738static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1739{
47107e84 1740 if (state)
eb7ff77e 1741 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1742 else
eb7ff77e 1743 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1744}
1745
23ba9340
EG		 1746static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1747 unsigned long *flags)
7a65d170
EG		 1748{
1749 int ret;
cfb4e624
JB		 1750 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1751
1752 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1753
fc8a350d 1754 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1755 goto out;
1756
7a65d170 1757 /* this bit wakes up the NIC */
e139dc4a
LE		 1758 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1759 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1760 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1761 udelay(2);
7a65d170
EG		 1762
1763 /*
1764 * These bits say the device is running, and should keep running for
1765 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1766 * but they do not indicate that embedded SRAM is restored yet;
1767 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1768 * to/from host DRAM when sleeping/waking for power-saving.
1769 * Each direction takes approximately 1/4 millisecond; with this
1770 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1771 * series of register accesses are expected (e.g. reading Event Log),
1772 * to keep device from sleeping.
1773 *
1774 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1775 * SRAM is okay/restored. We don't check that here because this call
1776 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1777 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1778 *
1779 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1780 * and do not save/restore SRAM when power cycling.
1781 */
1782 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1783 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1784 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1785 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1786 if (unlikely(ret < 0)) {
1787 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1788 WARN_ONCE(1,
1789 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1790 iwl_read32(trans, CSR_GP_CNTRL));
1791 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1792 return false;
7a65d170
EG		 1793 }
1794
b9439491 1795out:
e56b04ef
LE		 1796 /*
1797 * Fool sparse by faking we release the lock - sparse will
1798 * track nic_access anyway.
1799 */
cfb4e624 1800 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1801 return true;
1802}
1803
e56b04ef
LE		 1804static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1805 unsigned long *flags)
7a65d170 1806{
cfb4e624 1807 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1808
cfb4e624 1809 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1810
1811 /*
1812 * Fool sparse by faking we acquiring the lock - sparse will
1813 * track nic_access anyway.
1814 */
cfb4e624 1815 __acquire(&trans_pcie->reg_lock);
e56b04ef 1816
fc8a350d 1817 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1818 goto out;
1819
e139dc4a
LE		 1820 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1821 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1822 /*
1823 * Above we read the CSR_GP_CNTRL register, which will flush
1824 * any previous writes, but we need the write that clears the
1825 * MAC_ACCESS_REQ bit to be performed before any other writes
1826 * scheduled on different CPUs (after we drop reg_lock).
1827 */
1828 mmiowb();
b9439491 1829out:
cfb4e624 1830 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1831}
1832
4fd442db
EG		 1833static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1834 void *buf, int dwords)
1835{
1836 unsigned long flags;
1837 int offs, ret = 0;
1838 u32 *vals = buf;
1839
23ba9340 1840 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1841 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1842 for (offs = 0; offs < dwords; offs++)
1843 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1844 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1845 } else {
1846 ret = -EBUSY;
1847 }
4fd442db
EG		 1848 return ret;
1849}
1850
1851static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1852 const void *buf, int dwords)
4fd442db
EG		 1853{
1854 unsigned long flags;
1855 int offs, ret = 0;
bf0fd5da 1856 const u32 *vals = buf;
4fd442db 1857
23ba9340 1858 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1859 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1860 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1861 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1862 vals ? vals[offs] : 0);
e56b04ef 1863 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1864 } else {
1865 ret = -EBUSY;
1866 }
4fd442db
EG		 1867 return ret;
1868}
7a65d170 1869
e0b8d405
EG		 1870static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1871 unsigned long txqs,
1872 bool freeze)
1873{
1874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1875 int queue;
1876
1877 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1878 struct iwl_txq *txq = &trans_pcie->txq[queue];
1879 unsigned long now;
1880
1881 spin_lock_bh(&txq->lock);
1882
1883 now = jiffies;
1884
1885 if (txq->frozen == freeze)
1886 goto next_queue;
1887
1888 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1889 freeze ? "Freezing" : "Waking", queue);
1890
1891 txq->frozen = freeze;
1892
1893 if (txq->q.read_ptr == txq->q.write_ptr)
1894 goto next_queue;
1895
1896 if (freeze) {
1897 if (unlikely(time_after(now,
1898 txq->stuck_timer.expires))) {
1899 /*
1900 * The timer should have fired, maybe it is
1901 * spinning right now on the lock.
1902 */
1903 goto next_queue;
1904 }
1905 /* remember how long until the timer fires */
1906 txq->frozen_expiry_remainder =
1907 txq->stuck_timer.expires - now;
1908 del_timer(&txq->stuck_timer);
1909 goto next_queue;
1910 }
1911
1912 /*
1913 * Wake a non-empty queue -> arm timer with the
1914 * remainder before it froze
1915 */
1916 mod_timer(&txq->stuck_timer,
1917 now + txq->frozen_expiry_remainder);
1918
1919next_queue:
1920 spin_unlock_bh(&txq->lock);
1921 }
1922}
1923
0cd58eaa
EG		 1924static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1925{
1926 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1927 int i;
1928
1929 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1930 struct iwl_txq *txq = &trans_pcie->txq[i];
1931
1932 if (i == trans_pcie->cmd_queue)
1933 continue;
1934
1935 spin_lock_bh(&txq->lock);
1936
1937 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1938 txq->block--;
1939 if (!txq->block) {
1940 iwl_write32(trans, HBUS_TARG_WRPTR,
1941 txq->q.write_ptr | (i << 8));
1942 }
1943 } else if (block) {
1944 txq->block++;
1945 }
1946
1947 spin_unlock_bh(&txq->lock);
1948 }
1949}
1950
5f178cd2
EG		 1951#define IWL_FLUSH_WAIT_MS 2000
1952
3cafdbe6 1953static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1954{
8ad71bef 1955 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1956 struct iwl_txq *txq;
5f178cd2
EG		 1957 struct iwl_queue *q;
1958 int cnt;
1959 unsigned long now = jiffies;
1c3fea82
EG		 1960 u32 scd_sram_addr;
1961 u8 buf[16];
5f178cd2
EG		 1962 int ret = 0;
1963
1964 /* waiting for all the tx frames complete might take a while */
035f7ff2 1965 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1966 u8 wr_ptr;
1967
9ba1947a 1968 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1969 continue;
3cafdbe6
EG		 1970 if (!test_bit(cnt, trans_pcie->queue_used))
1971 continue;
1972 if (!(BIT(cnt) & txq_bm))
1973 continue;
748fa67c
EG		 1974
1975 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1976 txq = &trans_pcie->txq[cnt];
5f178cd2 1977 q = &txq->q;
fa1a91fd
EG		 1978 wr_ptr = ACCESS_ONCE(q->write_ptr);
1979
1980 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1981 !time_after(jiffies,
1982 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1983 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1984
1985 if (WARN_ONCE(wr_ptr != write_ptr,
1986 "WR pointer moved while flushing %d -> %d\n",
1987 wr_ptr, write_ptr))
1988 return -ETIMEDOUT;
192185d6 1989 usleep_range(1000, 2000);
fa1a91fd 1990 }
5f178cd2
EG		 1991
1992 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1993 IWL_ERR(trans,
1994 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1995 ret = -ETIMEDOUT;
1996 break;
1997 }
748fa67c 1998 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1999 }
1c3fea82
EG		 2000
2001 if (!ret)
2002 return 0;
2003
2004 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
2005 txq->q.read_ptr, txq->q.write_ptr);
2006
2007 scd_sram_addr = trans_pcie->scd_base_addr +
2008 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
2009 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
2010
2011 iwl_print_hex_error(trans, buf, sizeof(buf));
2012
2013 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
2014 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
2015 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
2016
2017 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2018 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
2019 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2020 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2021 u32 tbl_dw =
2022 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
2023 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
2024
2025 if (cnt & 0x1)
2026 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
2027 else
2028 tbl_dw = tbl_dw & 0x0000FFFF;
2029
2030 IWL_ERR(trans,
2031 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
2032 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 2033 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
2034 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 2035 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
2036 }
2037
5f178cd2
EG		 2038 return ret;
2039}
2040
e139dc4a
LE		 2041static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2042 u32 mask, u32 value)
2043{
e56b04ef 2044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2045 unsigned long flags;
2046
e56b04ef 2047 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2048 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2049 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2050}
2051
c24c7f58 2052static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2053{
2054 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2055
2056 if (iwlwifi_mod_params.d0i3_disable)
2057 return;
2058
b3ff1270 2059 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2060
2061#ifdef CONFIG_PM
2062 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2063 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2064#endif /* CONFIG_PM */
7616f334
EP		 2065}
2066
c24c7f58 2067static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2068{
2069 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2070
2071 if (iwlwifi_mod_params.d0i3_disable)
2072 return;
2073
b3ff1270
LC		 2074 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2075 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2076
5d93f3a2
LC		 2077#ifdef CONFIG_PM
2078 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2079 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2080#endif /* CONFIG_PM */
7616f334
EP		 2081}
2082
ff620849
EG		 2083static const char *get_csr_string(int cmd)
2084{
d9fb6465 2085#define IWL_CMD(x) case x: return #x
ff620849
EG		 2086 switch (cmd) {
2087 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2088 IWL_CMD(CSR_INT_COALESCING);
2089 IWL_CMD(CSR_INT);
2090 IWL_CMD(CSR_INT_MASK);
2091 IWL_CMD(CSR_FH_INT_STATUS);
2092 IWL_CMD(CSR_GPIO_IN);
2093 IWL_CMD(CSR_RESET);
2094 IWL_CMD(CSR_GP_CNTRL);
2095 IWL_CMD(CSR_HW_REV);
2096 IWL_CMD(CSR_EEPROM_REG);
2097 IWL_CMD(CSR_EEPROM_GP);
2098 IWL_CMD(CSR_OTP_GP_REG);
2099 IWL_CMD(CSR_GIO_REG);
2100 IWL_CMD(CSR_GP_UCODE_REG);
2101 IWL_CMD(CSR_GP_DRIVER_REG);
2102 IWL_CMD(CSR_UCODE_DRV_GP1);
2103 IWL_CMD(CSR_UCODE_DRV_GP2);
2104 IWL_CMD(CSR_LED_REG);
2105 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2106 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2107 IWL_CMD(CSR_ANA_PLL_CFG);
2108 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2109 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2110 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2111 default:
2112 return "UNKNOWN";
2113 }
d9fb6465 2114#undef IWL_CMD
ff620849
EG		 2115}
2116
990aa6d7 2117void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2118{
2119 int i;
2120 static const u32 csr_tbl[] = {
2121 CSR_HW_IF_CONFIG_REG,
2122 CSR_INT_COALESCING,
2123 CSR_INT,
2124 CSR_INT_MASK,
2125 CSR_FH_INT_STATUS,
2126 CSR_GPIO_IN,
2127 CSR_RESET,
2128 CSR_GP_CNTRL,
2129 CSR_HW_REV,
2130 CSR_EEPROM_REG,
2131 CSR_EEPROM_GP,
2132 CSR_OTP_GP_REG,
2133 CSR_GIO_REG,
2134 CSR_GP_UCODE_REG,
2135 CSR_GP_DRIVER_REG,
2136 CSR_UCODE_DRV_GP1,
2137 CSR_UCODE_DRV_GP2,
2138 CSR_LED_REG,
2139 CSR_DRAM_INT_TBL_REG,
2140 CSR_GIO_CHICKEN_BITS,
2141 CSR_ANA_PLL_CFG,
a812cba9 2142 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2143 CSR_HW_REV_WA_REG,
2144 CSR_DBG_HPET_MEM_REG
2145 };
2146 IWL_ERR(trans, "CSR values:\n");
2147 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2148 "CSR_INT_PERIODIC_REG)\n");
2149 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2150 IWL_ERR(trans, " %25s: 0X%08x\n",
2151 get_csr_string(csr_tbl[i]),
1042db2a 2152 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2153 }
2154}
2155
87e5666c
EG		 2156#ifdef CONFIG_IWLWIFI_DEBUGFS
2157/* create and remove of files */
2158#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2159 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2160 &iwl_dbgfs_##name##_ops)) \
9da987ac 2161 goto err; \
87e5666c
EG		 2162} while (0)
2163
2164/* file operation */
87e5666c 2165#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2166static const struct file_operations iwl_dbgfs_##name##_ops = { \
2167 .read = iwl_dbgfs_##name##_read, \
234e3405 2168 .open = simple_open, \
87e5666c
EG		 2169 .llseek = generic_file_llseek, \
2170};
2171
16db88ba 2172#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2173static const struct file_operations iwl_dbgfs_##name##_ops = { \
2174 .write = iwl_dbgfs_##name##_write, \
234e3405 2175 .open = simple_open, \
16db88ba
EG		 2176 .llseek = generic_file_llseek, \
2177};
2178
87e5666c 2179#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2180static const struct file_operations iwl_dbgfs_##name##_ops = { \
2181 .write = iwl_dbgfs_##name##_write, \
2182 .read = iwl_dbgfs_##name##_read, \
234e3405 2183 .open = simple_open, \
87e5666c
EG		 2184 .llseek = generic_file_llseek, \
2185};
2186
87e5666c 2187static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2188 char __user *user_buf,
2189 size_t count, loff_t *ppos)
8ad71bef 2190{
5a878bf6 2191 struct iwl_trans *trans = file->private_data;
8ad71bef 2192 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2193 struct iwl_txq *txq;
87e5666c
EG		 2194 struct iwl_queue *q;
2195 char *buf;
2196 int pos = 0;
2197 int cnt;
2198 int ret;
1745e440
WYG		 2199 size_t bufsz;
2200
e0b8d405 2201 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2202
f9e75447 2203 if (!trans_pcie->txq)
87e5666c 2204 return -EAGAIN;
f9e75447 2205
87e5666c
EG		 2206 buf = kzalloc(bufsz, GFP_KERNEL);
2207 if (!buf)
2208 return -ENOMEM;
2209
035f7ff2 2210 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 2211 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 2212 q = &txq->q;
2213 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2214 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 2215 cnt, q->read_ptr, q->write_ptr,
9eae88fa 2216 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2217 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2218 txq->need_update, txq->frozen,
f40faf62 2219 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2220 }
2221 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2222 kfree(buf);
2223 return ret;
2224}
2225
2226static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2227 char __user *user_buf,
2228 size_t count, loff_t *ppos)
2229{
5a878bf6 2230 struct iwl_trans *trans = file->private_data;
20d3b647 2231 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2232 char *buf;
2233 int pos = 0, i, ret;
2234 size_t bufsz = sizeof(buf);
2235
2236 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2237
2238 if (!trans_pcie->rxq)
2239 return -EAGAIN;
2240
2241 buf = kzalloc(bufsz, GFP_KERNEL);
2242 if (!buf)
2243 return -ENOMEM;
2244
2245 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2246 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2247
2248 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2249 i);
2250 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2251 rxq->read);
2252 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2253 rxq->write);
2254 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2255 rxq->write_actual);
2256 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2257 rxq->need_update);
2258 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2259 rxq->free_count);
2260 if (rxq->rb_stts) {
2261 pos += scnprintf(buf + pos, bufsz - pos,
2262 "\tclosed_rb_num: %u\n",
2263 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2264 0x0FFF);
2265 } else {
2266 pos += scnprintf(buf + pos, bufsz - pos,
2267 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2268 }
87e5666c 2269 }
78485054
SS		 2270 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2271 kfree(buf);
2272
2273 return ret;
87e5666c
EG		 2274}
2275
1f7b6172
EG		 2276static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2277 char __user *user_buf,
20d3b647
JB		 2278 size_t count, loff_t *ppos)
2279{
1f7b6172 2280 struct iwl_trans *trans = file->private_data;
20d3b647 2281 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2282 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2283
2284 int pos = 0;
2285 char *buf;
2286 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2287 ssize_t ret;
2288
2289 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2290 if (!buf)
1f7b6172 2291 return -ENOMEM;
1f7b6172
EG		 2292
2293 pos += scnprintf(buf + pos, bufsz - pos,
2294 "Interrupt Statistics Report:\n");
2295
2296 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2297 isr_stats->hw);
2298 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2299 isr_stats->sw);
2300 if (isr_stats->sw || isr_stats->hw) {
2301 pos += scnprintf(buf + pos, bufsz - pos,
2302 "\tLast Restarting Code: 0x%X\n",
2303 isr_stats->err_code);
2304 }
2305#ifdef CONFIG_IWLWIFI_DEBUG
2306 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2307 isr_stats->sch);
2308 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2309 isr_stats->alive);
2310#endif
2311 pos += scnprintf(buf + pos, bufsz - pos,
2312 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2313
2314 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2315 isr_stats->ctkill);
2316
2317 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2318 isr_stats->wakeup);
2319
2320 pos += scnprintf(buf + pos, bufsz - pos,
2321 "Rx command responses:\t\t %u\n", isr_stats->rx);
2322
2323 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2324 isr_stats->tx);
2325
2326 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2327 isr_stats->unhandled);
2328
2329 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2330 kfree(buf);
2331 return ret;
2332}
2333
2334static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2335 const char __user *user_buf,
2336 size_t count, loff_t *ppos)
2337{
2338 struct iwl_trans *trans = file->private_data;
20d3b647 2339 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2340 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2341
2342 char buf[8];
2343 int buf_size;
2344 u32 reset_flag;
2345
2346 memset(buf, 0, sizeof(buf));
2347 buf_size = min(count, sizeof(buf) - 1);
2348 if (copy_from_user(buf, user_buf, buf_size))
2349 return -EFAULT;
2350 if (sscanf(buf, "%x", &reset_flag) != 1)
2351 return -EFAULT;
2352 if (reset_flag == 0)
2353 memset(isr_stats, 0, sizeof(*isr_stats));
2354
2355 return count;
2356}
2357
16db88ba 2358static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2359 const char __user *user_buf,
2360 size_t count, loff_t *ppos)
16db88ba
EG		 2361{
2362 struct iwl_trans *trans = file->private_data;
2363 char buf[8];
2364 int buf_size;
2365 int csr;
2366
2367 memset(buf, 0, sizeof(buf));
2368 buf_size = min(count, sizeof(buf) - 1);
2369 if (copy_from_user(buf, user_buf, buf_size))
2370 return -EFAULT;
2371 if (sscanf(buf, "%d", &csr) != 1)
2372 return -EFAULT;
2373
990aa6d7 2374 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2375
2376 return count;
2377}
2378
16db88ba 2379static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2380 char __user *user_buf,
2381 size_t count, loff_t *ppos)
16db88ba
EG		 2382{
2383 struct iwl_trans *trans = file->private_data;
94543a8d 2384 char *buf = NULL;
56c2477f 2385 ssize_t ret;
16db88ba 2386
56c2477f
JB		 2387 ret = iwl_dump_fh(trans, &buf);
2388 if (ret < 0)
2389 return ret;
2390 if (!buf)
2391 return -EINVAL;
2392 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2393 kfree(buf);
16db88ba
EG		 2394 return ret;
2395}
2396
1f7b6172 2397DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2398DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2399DEBUGFS_READ_FILE_OPS(rx_queue);
2400DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2401DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2402
f8a1edb7
JB		 2403/* Create the debugfs files and directories */
2404int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2405{
f8a1edb7
JB		 2406 struct dentry *dir = trans->dbgfs_dir;
2407
87e5666c
EG		 2408 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2409 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2410 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2411 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2412 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2413 return 0;
9da987ac
MV		 2414
2415err:
2416 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2417 return -ENOMEM;
87e5666c 2418}
aadede6e 2419#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2420
2421static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2422{
2423 u32 cmdlen = 0;
2424 int i;
2425
2426 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2427 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2428
2429 return cmdlen;
2430}
2431
bd7fc617
EG		 2432static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2433 struct iwl_fw_error_dump_data **data,
2434 int allocated_rb_nums)
2435{
2436 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2437 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2438 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2439 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2440 u32 i, r, j, rb_len = 0;
2441
2442 spin_lock(&rxq->lock);
2443
2444 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2445
2446 for (i = rxq->read, j = 0;
2447 i != r && j < allocated_rb_nums;
2448 i = (i + 1) & RX_QUEUE_MASK, j++) {
2449 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2450 struct iwl_fw_error_dump_rb *rb;
2451
2452 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2453 DMA_FROM_DEVICE);
2454
2455 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2456
2457 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2458 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2459 rb = (void *)(*data)->data;
2460 rb->index = cpu_to_le32(i);
2461 memcpy(rb->data, page_address(rxb->page), max_len);
2462 /* remap the page for the free benefit */
2463 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2464 max_len,
2465 DMA_FROM_DEVICE);
2466
2467 *data = iwl_fw_error_next_data(*data);
2468 }
2469
2470 spin_unlock(&rxq->lock);
2471
2472 return rb_len;
2473}
473ad712
EG		 2474#define IWL_CSR_TO_DUMP (0x250)
2475
2476static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2477 struct iwl_fw_error_dump_data **data)
2478{
2479 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2480 __le32 *val;
2481 int i;
2482
2483 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2484 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2485 val = (void *)(*data)->data;
2486
2487 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2488 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2489
2490 *data = iwl_fw_error_next_data(*data);
2491
2492 return csr_len;
2493}
2494
06d51e0d
LK		 2495static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2496 struct iwl_fw_error_dump_data **data)
2497{
2498 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2499 unsigned long flags;
2500 __le32 *val;
2501 int i;
2502
23ba9340 2503 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2504 return 0;
2505
2506 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2507 (*data)->len = cpu_to_le32(fh_regs_len);
2508 val = (void *)(*data)->data;
2509
2510 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2511 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2512
2513 iwl_trans_release_nic_access(trans, &flags);
2514
2515 *data = iwl_fw_error_next_data(*data);
2516
2517 return sizeof(**data) + fh_regs_len;
2518}
2519
cc79ef66
LK		 2520static u32
2521iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2522 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2523 u32 monitor_len)
2524{
2525 u32 buf_size_in_dwords = (monitor_len >> 2);
2526 u32 *buffer = (u32 *)fw_mon_data->data;
2527 unsigned long flags;
2528 u32 i;
2529
23ba9340 2530 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2531 return 0;
2532
14ef1b43 2533 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2534 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2535 buffer[i] = iwl_read_prph_no_grab(trans,
2536 MON_DMARB_RD_DATA_ADDR);
2537 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2538
2539 iwl_trans_release_nic_access(trans, &flags);
2540
2541 return monitor_len;
2542}
2543
36fb9017
OG		 2544static u32
2545iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2546 struct iwl_fw_error_dump_data **data,
2547 u32 monitor_len)
2548{
2549 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2550 u32 len = 0;
2551
2552 if ((trans_pcie->fw_mon_page &&
2553 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2554 trans->dbg_dest_tlv) {
2555 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2556 u32 base, write_ptr, wrap_cnt;
2557
2558 /* If there was a dest TLV - use the values from there */
2559 if (trans->dbg_dest_tlv) {
2560 write_ptr =
2561 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2562 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2563 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2564 } else {
2565 base = MON_BUFF_BASE_ADDR;
2566 write_ptr = MON_BUFF_WRPTR;
2567 wrap_cnt = MON_BUFF_CYCLE_CNT;
2568 }
2569
2570 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2571 fw_mon_data = (void *)(*data)->data;
2572 fw_mon_data->fw_mon_wr_ptr =
2573 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2574 fw_mon_data->fw_mon_cycle_cnt =
2575 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2576 fw_mon_data->fw_mon_base_ptr =
2577 cpu_to_le32(iwl_read_prph(trans, base));
2578
2579 len += sizeof(**data) + sizeof(*fw_mon_data);
2580 if (trans_pcie->fw_mon_page) {
2581 /*
2582 * The firmware is now asserted, it won't write anything
2583 * to the buffer. CPU can take ownership to fetch the
2584 * data. The buffer will be handed back to the device
2585 * before the firmware will be restarted.
2586 */
2587 dma_sync_single_for_cpu(trans->dev,
2588 trans_pcie->fw_mon_phys,
2589 trans_pcie->fw_mon_size,
2590 DMA_FROM_DEVICE);
2591 memcpy(fw_mon_data->data,
2592 page_address(trans_pcie->fw_mon_page),
2593 trans_pcie->fw_mon_size);
2594
2595 monitor_len = trans_pcie->fw_mon_size;
2596 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2597 /*
2598 * Update pointers to reflect actual values after
2599 * shifting
2600 */
2601 base = iwl_read_prph(trans, base) <<
2602 trans->dbg_dest_tlv->base_shift;
2603 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2604 monitor_len / sizeof(u32));
2605 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2606 monitor_len =
2607 iwl_trans_pci_dump_marbh_monitor(trans,
2608 fw_mon_data,
2609 monitor_len);
2610 } else {
2611 /* Didn't match anything - output no monitor data */
2612 monitor_len = 0;
2613 }
2614
2615 len += monitor_len;
2616 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2617 }
2618
2619 return len;
2620}
2621
2622static struct iwl_trans_dump_data
2623*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2624 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2625{
2626 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2627 struct iwl_fw_error_dump_data *data;
2628 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2629 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2630 struct iwl_trans_dump_data *dump_data;
bd7fc617 2631 u32 len, num_rbs;
99684ae3 2632 u32 monitor_len;
4d075007 2633 int i, ptr;
96a6497b
SS		 2634 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2635 !trans->cfg->mq_rx_supported;
4d075007 2636
473ad712
EG		 2637 /* transport dump header */
2638 len = sizeof(*dump_data);
2639
2640 /* host commands */
2641 len += sizeof(*data) +
c2d20201
EG		 2642 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2643
473ad712 2644 /* FW monitor */
99684ae3 2645 if (trans_pcie->fw_mon_page) {
c544e9c4 2646 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2647 trans_pcie->fw_mon_size;
2648 monitor_len = trans_pcie->fw_mon_size;
2649 } else if (trans->dbg_dest_tlv) {
2650 u32 base, end;
2651
2652 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2653 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2654
2655 base = iwl_read_prph(trans, base) <<
2656 trans->dbg_dest_tlv->base_shift;
2657 end = iwl_read_prph(trans, end) <<
2658 trans->dbg_dest_tlv->end_shift;
2659
2660 /* Make "end" point to the actual end */
cc79ef66
LK		 2661 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2662 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2663 end += (1 << trans->dbg_dest_tlv->end_shift);
2664 monitor_len = end - base;
2665 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2666 monitor_len;
2667 } else {
2668 monitor_len = 0;
2669 }
c2d20201 2670
36fb9017
OG		 2671 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2672 dump_data = vzalloc(len);
2673 if (!dump_data)
2674 return NULL;
2675
2676 data = (void *)dump_data->data;
2677 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2678 dump_data->len = len;
2679
2680 return dump_data;
2681 }
2682
2683 /* CSR registers */
2684 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2685
36fb9017
OG		 2686 /* FH registers */
2687 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2688
2689 if (dump_rbs) {
78485054
SS		 2690 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2691 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2692 /* RBs */
78485054 2693 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2694 & 0x0FFF;
78485054 2695 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2696 len += num_rbs * (sizeof(*data) +
2697 sizeof(struct iwl_fw_error_dump_rb) +
2698 (PAGE_SIZE << trans_pcie->rx_page_order));
2699 }
2700
48eb7b34
EG		 2701 dump_data = vzalloc(len);
2702 if (!dump_data)
2703 return NULL;
4d075007
JB		 2704
2705 len = 0;
48eb7b34 2706 data = (void *)dump_data->data;
4d075007
JB		 2707 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2708 txcmd = (void *)data->data;
2709 spin_lock_bh(&cmdq->lock);
2710 ptr = cmdq->q.write_ptr;
2711 for (i = 0; i < cmdq->q.n_window; i++) {
2712 u8 idx = get_cmd_index(&cmdq->q, ptr);
2713 u32 caplen, cmdlen;
2714
2715 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2716 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2717
2718 if (cmdlen) {
2719 len += sizeof(*txcmd) + caplen;
2720 txcmd->cmdlen = cpu_to_le32(cmdlen);
2721 txcmd->caplen = cpu_to_le32(caplen);
2722 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2723 txcmd = (void *)((u8 *)txcmd->data + caplen);
2724 }
2725
2726 ptr = iwl_queue_dec_wrap(ptr);
2727 }
2728 spin_unlock_bh(&cmdq->lock);
2729
2730 data->len = cpu_to_le32(len);
c2d20201 2731 len += sizeof(*data);
67c65f2c
EG		 2732 data = iwl_fw_error_next_data(data);
2733
473ad712 2734 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2735 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2736 if (dump_rbs)
2737 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2738
36fb9017 2739 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2740
48eb7b34
EG		 2741 dump_data->len = len;
2742
2743 return dump_data;
4d075007 2744}
87e5666c 2745
4cbb8e50
LC		 2746#ifdef CONFIG_PM_SLEEP
2747static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2748{
2749 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2750 return iwl_pci_fw_enter_d0i3(trans);
2751
2752 return 0;
2753}
2754
2755static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2756{
2757 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2758 iwl_pci_fw_exit_d0i3(trans);
2759}
2760#endif /* CONFIG_PM_SLEEP */
2761
d1ff5253 2762static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2763 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2764 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2765 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2766 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2767 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2768
ddaf5a5b
JB		 2769 .d3_suspend = iwl_trans_pcie_d3_suspend,
2770 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2771
4cbb8e50
LC		 2772#ifdef CONFIG_PM_SLEEP
2773 .suspend = iwl_trans_pcie_suspend,
2774 .resume = iwl_trans_pcie_resume,
2775#endif /* CONFIG_PM_SLEEP */
2776
f02831be 2777 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2778
e6bb4c9c 2779 .tx = iwl_trans_pcie_tx,
a0eaad71 2780 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2781
d0624be6 2782 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2783 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2784
42db09c1
LK		 2785 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2786
990aa6d7 2787 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2788 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
0cd58eaa 2789 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
5f178cd2 2790
03905495
EG		 2791 .write8 = iwl_trans_pcie_write8,
2792 .write32 = iwl_trans_pcie_write32,
2793 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2794 .read_prph = iwl_trans_pcie_read_prph,
2795 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2796 .read_mem = iwl_trans_pcie_read_mem,
2797 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2798 .configure = iwl_trans_pcie_configure,
47107e84 2799 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2800 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2801 .release_nic_access = iwl_trans_pcie_release_nic_access,
2802 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2803
7616f334
EP		 2804 .ref = iwl_trans_pcie_ref,
2805 .unref = iwl_trans_pcie_unref,
2806
4d075007 2807 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2808};
a42a1844 2809
87ce05a2 2810struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2811 const struct pci_device_id *ent,
2812 const struct iwl_cfg *cfg)
a42a1844 2813{
a42a1844
EG		 2814 struct iwl_trans_pcie *trans_pcie;
2815 struct iwl_trans *trans;
96a6497b 2816 int ret, addr_size;
a42a1844 2817
7b501d10
JB		 2818 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2819 &pdev->dev, cfg, &trans_ops_pcie, 0);
2820 if (!trans)
2821 return ERR_PTR(-ENOMEM);
a42a1844 2822
206eea78
JB		 2823 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2824
a42a1844
EG		 2825 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2826
a42a1844 2827 trans_pcie->trans = trans;
7b11488f 2828 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2829 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 2830 mutex_init(&trans_pcie->mutex);
13df1aab 2831 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2832 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2833 if (!trans_pcie->tso_hdr_page) {
2834 ret = -ENOMEM;
2835 goto out_no_pci;
2836 }
a42a1844 2837
af3f2f74
EG		 2838 ret = pci_enable_device(pdev);
2839 if (ret)
d819c6cf
JB		 2840 goto out_no_pci;
2841
f2532b04
EG		 2842 if (!cfg->base_params->pcie_l1_allowed) {
2843 /*
2844 * W/A - seems to solve weird behavior. We need to remove this
2845 * if we don't want to stay in L1 all the time. This wastes a
2846 * lot of power.
2847 */
2848 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2849 PCIE_LINK_STATE_L1 |
2850 PCIE_LINK_STATE_CLKPM);
2851 }
a42a1844 2852
96a6497b
SS		 2853 if (cfg->mq_rx_supported)
2854 addr_size = 64;
2855 else
2856 addr_size = 36;
2857
a42a1844
EG		 2858 pci_set_master(pdev);
2859
96a6497b 2860 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 2861 if (!ret)
96a6497b
SS		 2862 ret = pci_set_consistent_dma_mask(pdev,
2863 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 2864 if (ret) {
2865 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2866 if (!ret)
2867 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2868 DMA_BIT_MASK(32));
a42a1844 2869 /* both attempts failed: */
af3f2f74 2870 if (ret) {
6a4b09f8 2871 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2872 goto out_pci_disable_device;
2873 }
2874 }
2875
af3f2f74
EG		 2876 ret = pci_request_regions(pdev, DRV_NAME);
2877 if (ret) {
6a4b09f8 2878 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2879 goto out_pci_disable_device;
2880 }
2881
05f5b97e 2882 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2883 if (!trans_pcie->hw_base) {
6a4b09f8 2884 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
af3f2f74 2885 ret = -ENODEV;
a42a1844
EG		 2886 goto out_pci_release_regions;
2887 }
2888
a42a1844
EG		 2889 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2890 * PCI Tx retries from interfering with C3 CPU state */
2891 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2892
83f7a85f
EG		 2893 trans->dev = &pdev->dev;
2894 trans_pcie->pci_dev = pdev;
2895 iwl_disable_interrupts(trans);
2896
08079a49 2897 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2898 /*
2899 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2900 * changed, and now the revision step also includes bit 0-1 (no more
2901 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2902 * in the old format.
2903 */
7a42baa6
EH		 2904 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2905 unsigned long flags;
7a42baa6 2906
b513ee7f 2907 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2908 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2909
f9e5554c
EG		 2910 ret = iwl_pcie_prepare_card_hw(trans);
2911 if (ret) {
2912 IWL_WARN(trans, "Exit HW not ready\n");
2913 goto out_pci_disable_msi;
2914 }
2915
7a42baa6
EH		 2916 /*
2917 * in-order to recognize C step driver should read chip version
2918 * id located at the AUX bus MISC address space.
2919 */
2920 iwl_set_bit(trans, CSR_GP_CNTRL,
2921 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2922 udelay(2);
2923
2924 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2925 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2926 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2927 25000);
2928 if (ret < 0) {
2929 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2930 goto out_pci_disable_msi;
2931 }
2932
23ba9340 2933 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 2934 u32 hw_step;
2935
14ef1b43 2936 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 2937 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 2938 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2939 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 2940 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2941 if (hw_step == 0x3)
2942 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2943 (SILICON_C_STEP << 2);
2944 iwl_trans_release_nic_access(trans, &flags);
2945 }
2946 }
2947
1afb0ae4
HD		 2948 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
2949
2e5d4a8f 2950 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 2951 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2952 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2953 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2954
69a10b29 2955 /* Initialize the wait queue for commands */
f946b529 2956 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2957
4cbb8e50
LC		 2958 init_waitqueue_head(&trans_pcie->d0i3_waitq);
2959
2e5d4a8f
HD		 2960 if (trans_pcie->msix_enabled) {
2961 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
2962 goto out_pci_release_regions;
2963 } else {
2964 ret = iwl_pcie_alloc_ict(trans);
2965 if (ret)
2966 goto out_pci_disable_msi;
a8b691e6 2967
2e5d4a8f
HD		 2968 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2969 iwl_pcie_irq_handler,
2970 IRQF_SHARED, DRV_NAME, trans);
2971 if (ret) {
2972 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2973 goto out_free_ict;
2974 }
2975 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2976 }
83f7a85f 2977
b3ff1270
LC		 2978#ifdef CONFIG_IWLWIFI_PCIE_RTPM
2979 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2980#else
2981 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2982#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2983
a42a1844
EG		 2984 return trans;
2985
a8b691e6
JB		 2986out_free_ict:
2987 iwl_pcie_free_ict(trans);
59c647b6
EG		 2988out_pci_disable_msi:
2989 pci_disable_msi(pdev);
a42a1844
EG		 2990out_pci_release_regions:
2991 pci_release_regions(pdev);
2992out_pci_disable_device:
2993 pci_disable_device(pdev);
2994out_no_pci:
6eb5e529 2995 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 2996 iwl_trans_free(trans);
af3f2f74 2997 return ERR_PTR(ret);
a42a1844 2998}
Linux 6.x block layer and io_uring tree(s)