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iwlwifi: mvm: support rss queues configuration command
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 10 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 37 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
4d075007 83#include "iwl-fw-error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
c2d20201
EG		 91static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92{
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105}
106
96c285da 107static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 108{
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 110 struct page *page = NULL;
c2d20201 111 dma_addr_t phys;
96c285da 112 u32 size = 0;
c2d20201
EG		 113 u8 power;
114
96c285da
EG		 115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
c2d20201
EG		 127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
96c285da 135 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
553452e5 149 page = NULL;
c2d20201
EG		 150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
40a76905 158 if (WARN_ON_ONCE(!page))
c2d20201
EG		 159 return;
160
96c285da
EG		 161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
c2d20201
EG		 167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170}
171
a812cba9
AB		 172static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173{
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177}
178
179static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180{
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184}
185
ddaf5a5b 186static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 187{
66337b7c 188 if (trans->cfg->apmg_not_supported)
95411d04
AA		 189 return;
190
ddaf5a5b
JB		 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 199}
200
af634bee
EG		 201/* PCI registers */
202#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 203
7afe3705 204static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 205{
20d3b647 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 207 u16 lctl;
9180ac50 208 u16 cap;
af634bee 209
af634bee
EG		 210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
7afe3705 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 221 else
af634bee 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 230}
231
a6c684ee
EG		 232/*
233 * Start up NIC's basic functionality after it has been reset
7afe3705 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 235 * NOTE: This does not load uCode nor start the embedded processor
236 */
7afe3705 237static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 238{
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 268
7afe3705 269 iwl_pcie_apm_config(trans);
a6c684ee
EG		 270
271 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 272 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 273 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 274 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 275
276 /*
277 * Set "initialization complete" bit to move adapter from
278 * D0U* --> D0A* (powered-up active) state.
279 */
280 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
281
282 /*
283 * Wait for clock stabilization; once stabilized, access to
284 * device-internal resources is supported, e.g. iwl_write_prph()
285 * and accesses to uCode SRAM.
286 */
287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 290 if (ret < 0) {
291 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
292 goto out;
293 }
294
2d93aee1
EG		 295 if (trans->cfg->host_interrupt_operation_mode) {
296 /*
297 * This is a bit of an abuse - This is needed for 7260 / 3160
298 * only check host_interrupt_operation_mode even if this is
299 * not related to host_interrupt_operation_mode.
300 *
301 * Enable the oscillator to count wake up time for L1 exit. This
302 * consumes slightly more power (100uA) - but allows to be sure
303 * that we wake up from L1 on time.
304 *
305 * This looks weird: read twice the same register, discard the
306 * value, set a bit, and yet again, read that same register
307 * just to discard the value. But that's the way the hardware
308 * seems to like it.
309 */
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
313 iwl_read_prph(trans, OSC_CLK);
314 iwl_read_prph(trans, OSC_CLK);
315 }
316
a6c684ee
EG		 317 /*
318 * Enable DMA clock and wait for it to stabilize.
319 *
3073d8c0
EH		 320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
321 * bits do not disable clocks. This preserves any hardware
322 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 323 */
95411d04 324 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 325 iwl_write_prph(trans, APMG_CLK_EN_REG,
326 APMG_CLK_VAL_DMA_CLK_RQT);
327 udelay(20);
328
329 /* Disable L1-Active */
330 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
332
333 /* Clear the interrupt in APMG if the NIC is in RFKILL */
334 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
335 APMG_RTC_INT_STT_RFKILL);
336 }
889b1696 337
eb7ff77e 338 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 339
340out:
341 return ret;
342}
343
a812cba9
AB		 344/*
345 * Enable LP XTAL to avoid HW bug where device may consume much power if
346 * FW is not loaded after device reset. LP XTAL is disabled by default
347 * after device HW reset. Do it only if XTAL is fed by internal source.
348 * Configure device's "persistence" mode to avoid resetting XTAL again when
349 * SHRD_HW_RST occurs in S3.
350 */
351static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
352{
353 int ret;
354 u32 apmg_gp1_reg;
355 u32 apmg_xtal_cfg_reg;
356 u32 dl_cfg_reg;
357
358 /* Force XTAL ON */
359 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
360 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
361
362 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
363 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
364
365 udelay(10);
366
367 /*
368 * Set "initialization complete" bit to move adapter from
369 * D0U* --> D0A* (powered-up active) state.
370 */
371 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
372
373 /*
374 * Wait for clock stabilization; once stabilized, access to
375 * device-internal resources is possible.
376 */
377 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
379 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
380 25000);
381 if (WARN_ON(ret < 0)) {
382 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
383 /* Release XTAL ON request */
384 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
385 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
386 return;
387 }
388
389 /*
390 * Clear "disable persistence" to avoid LP XTAL resetting when
391 * SHRD_HW_RST is applied in S3.
392 */
393 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
394 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
395
396 /*
397 * Force APMG XTAL to be active to prevent its disabling by HW
398 * caused by APMG idle state.
399 */
400 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
401 SHR_APMG_XTAL_CFG_REG);
402 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
403 apmg_xtal_cfg_reg |
404 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
405
406 /*
407 * Reset entire device again - do controller reset (results in
408 * SHRD_HW_RST). Turn MAC off before proceeding.
409 */
410 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
411
412 udelay(10);
413
414 /* Enable LP XTAL by indirect access through CSR */
415 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
416 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
417 SHR_APMG_GP1_WF_XTAL_LP_EN |
418 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
419
420 /* Clear delay line clock power up */
421 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
422 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
423 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
424
425 /*
426 * Enable persistence mode to avoid LP XTAL resetting when
427 * SHRD_HW_RST is applied in S3.
428 */
429 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
430 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
431
432 /*
433 * Clear "initialization complete" bit to move adapter from
434 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
435 */
436 iwl_clear_bit(trans, CSR_GP_CNTRL,
437 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
438
439 /* Activates XTAL resources monitor */
440 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
441 CSR_MONITOR_XTAL_RESOURCES);
442
443 /* Release XTAL ON request */
444 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
445 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
446 udelay(10);
447
448 /* Release APMG XTAL */
449 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
450 apmg_xtal_cfg_reg &
451 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
452}
453
7afe3705 454static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 455{
456 int ret = 0;
457
458 /* stop device's busmaster DMA activity */
459 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
460
461 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 462 CSR_RESET_REG_FLAG_MASTER_DISABLED,
463 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 464 if (ret < 0)
cc56feb2
EG		 465 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
466
467 IWL_DEBUG_INFO(trans, "stop master\n");
468
469 return ret;
470}
471
b7aaeae4 472static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 473{
474 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
475
b7aaeae4
EG		 476 if (op_mode_leave) {
477 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
478 iwl_pcie_apm_init(trans);
479
480 /* inform ME that we are leaving */
481 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
482 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
483 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 484 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
485 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
486 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 487 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
488 CSR_HW_IF_CONFIG_REG_PREPARE |
489 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 490 mdelay(1);
491 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
492 CSR_RESET_LINK_PWR_MGMT_DISABLED);
493 }
b7aaeae4
EG		 494 mdelay(5);
495 }
496
eb7ff77e 497 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 498
499 /* Stop device's DMA activity */
7afe3705 500 iwl_pcie_apm_stop_master(trans);
cc56feb2 501
a812cba9
AB		 502 if (trans->cfg->lp_xtal_workaround) {
503 iwl_pcie_apm_lp_xtal_enable(trans);
504 return;
505 }
506
cc56feb2
EG		 507 /* Reset the entire device */
508 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
509
510 udelay(10);
511
512 /*
513 * Clear "initialization complete" bit to move adapter from
514 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
515 */
516 iwl_clear_bit(trans, CSR_GP_CNTRL,
517 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
518}
519
7afe3705 520static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 521{
7b11488f 522 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 523
524 /* nic_init */
7b70bd63 525 spin_lock(&trans_pcie->irq_lock);
7afe3705 526 iwl_pcie_apm_init(trans);
392f8b78 527
7b70bd63 528 spin_unlock(&trans_pcie->irq_lock);
392f8b78 529
95411d04 530 iwl_pcie_set_pwr(trans, false);
392f8b78 531
ecdb975c 532 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 533
534 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 535 iwl_pcie_rx_init(trans);
392f8b78
EG		 536
537 /* Allocate or reset and init all Tx and Command queues */
f02831be 538 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 539 return -ENOMEM;
540
035f7ff2 541 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 542 /* enable shadow regs in HW */
20d3b647 543 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 544 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 545 }
546
392f8b78
EG		 547 return 0;
548}
549
550#define HW_READY_TIMEOUT (50)
551
552/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 553static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 554{
555 int ret;
556
1042db2a 557 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 559
560 /* See if we got it */
1042db2a 561 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 562 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
563 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
564 HW_READY_TIMEOUT);
392f8b78 565
6a08f514
EG		 566 if (ret >= 0)
567 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
568
6d8f6eeb 569 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 570 return ret;
571}
572
573/* Note: returns standard 0/-ERROR code */
7afe3705 574static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 575{
576 int ret;
289e5501 577 int t = 0;
501fd989 578 int iter;
392f8b78 579
6d8f6eeb 580 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 581
7afe3705 582 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 583 /* If the card is ready, exit 0 */
392f8b78
EG		 584 if (ret >= 0)
585 return 0;
586
c9fdec9f
EG		 587 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
588 CSR_RESET_LINK_PWR_MGMT_DISABLED);
589 msleep(1);
590
501fd989
EG		 591 for (iter = 0; iter < 10; iter++) {
592 /* If HW is not ready, prepare the conditions to check again */
593 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
594 CSR_HW_IF_CONFIG_REG_PREPARE);
595
596 do {
597 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 598 if (ret >= 0)
599 return 0;
392f8b78 600
501fd989
EG		 601 usleep_range(200, 1000);
602 t += 200;
603 } while (t < 150000);
604 msleep(25);
605 }
392f8b78 606
7f2ac8fb 607 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 608
392f8b78
EG		 609 return ret;
610}
611
cf614297
EG		 612/*
613 * ucode
614 */
7afe3705 615static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 616 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 617{
13df1aab 618 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 619 int ret;
620
13df1aab 621 trans_pcie->ucode_write_complete = false;
cf614297
EG		 622
623 iwl_write_direct32(trans,
20d3b647
JB		 624 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
625 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 626
627 iwl_write_direct32(trans,
20d3b647
JB		 628 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
629 dst_addr);
cf614297
EG		 630
631 iwl_write_direct32(trans,
83f84d7b
JB		 632 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
633 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 634
635 iwl_write_direct32(trans,
20d3b647
JB		 636 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
637 (iwl_get_dma_hi_addr(phy_addr)
638 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 639
640 iwl_write_direct32(trans,
20d3b647
JB		 641 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
642 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
643 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
644 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 645
646 iwl_write_direct32(trans,
20d3b647
JB		 647 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
648 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
649 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
650 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 651
13df1aab
JB		 652 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
653 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 654 if (!ret) {
83f84d7b 655 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 656 return -ETIMEDOUT;
657 }
658
659 return 0;
660}
661
7afe3705 662static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 663 const struct fw_desc *section)
cf614297 664{
83f84d7b
JB		 665 u8 *v_addr;
666 dma_addr_t p_addr;
baa21e83 667 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 668 int ret = 0;
669
83f84d7b
JB		 670 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
671 section_num);
672
c571573a
EG		 673 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
674 GFP_KERNEL | __GFP_NOWARN);
675 if (!v_addr) {
676 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
677 chunk_sz = PAGE_SIZE;
678 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
679 &p_addr, GFP_KERNEL);
680 if (!v_addr)
681 return -ENOMEM;
682 }
83f84d7b 683
c571573a 684 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 685 u32 copy_size, dst_addr;
686 bool extended_addr = false;
83f84d7b 687
c571573a 688 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 689 dst_addr = section->offset + offset;
690
691 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
692 dst_addr <= IWL_FW_MEM_EXTENDED_END)
693 extended_addr = true;
694
695 if (extended_addr)
696 iwl_set_bits_prph(trans, LMPM_CHICK,
697 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 698
83f84d7b 699 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 700 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
701 copy_size);
702
703 if (extended_addr)
704 iwl_clear_bits_prph(trans, LMPM_CHICK,
705 LMPM_CHICK_EXTENDED_ADDR_SPACE);
706
83f84d7b
JB		 707 if (ret) {
708 IWL_ERR(trans,
709 "Could not load the [%d] uCode section\n",
710 section_num);
711 break;
6dfa8d01 712 }
83f84d7b
JB		 713 }
714
c571573a 715 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 716 return ret;
717}
718
16bc119b
EH		 719/*
720 * Driver Takes the ownership on secure machine before FW load
721 * and prevent race with the BT load.
722 * W/A for ROM bug. (should be remove in the next Si step)
723 */
724static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
725{
726 u32 val, loop = 1000;
727
1e167071
EH		 728 /*
729 * Check the RSA semaphore is accessible.
730 * If the HW isn't locked and the rsa semaphore isn't accessible,
731 * we are in trouble.
732 */
16bc119b
EH		 733 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
734 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 735 IWL_INFO(trans,
736 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 737 return 0;
738 }
739
740 /* take ownership on the AUX IF */
741 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
742 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
743
744 do {
745 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
746 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
747 if (val == 0x1) {
748 iwl_write_prph(trans, RSA_ENABLE, 0);
749 return 0;
750 }
751
752 udelay(10);
753 loop--;
754 } while (loop > 0);
755
756 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
757 return -EIO;
758}
759
5dd9c68a
EG		 760static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
761 const struct fw_img *image,
762 int cpu,
763 int *first_ucode_section)
e2d6f4e7
EH		 764{
765 int shift_param;
dcab8ecd
EH		 766 int i, ret = 0, sec_num = 0x1;
767 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 768
769 if (cpu == 1) {
770 shift_param = 0;
034846cf 771 *first_ucode_section = 0;
e2d6f4e7
EH		 772 } else {
773 shift_param = 16;
034846cf 774 (*first_ucode_section)++;
e2d6f4e7
EH		 775 }
776
034846cf
EH		 777 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
778 last_read_idx = i;
779
a6c4fb44
MG		 780 /*
781 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
782 * CPU1 to CPU2.
783 * PAGING_SEPARATOR_SECTION delimiter - separate between
784 * CPU2 non paged to CPU2 paging sec.
785 */
034846cf 786 if (!image->sec[i].data ||
a6c4fb44
MG		 787 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
788 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 789 IWL_DEBUG_FW(trans,
790 "Break since Data not valid or Empty section, sec = %d\n",
791 i);
189fa2fa 792 break;
034846cf
EH		 793 }
794
189fa2fa
EH		 795 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
796 if (ret)
797 return ret;
dcab8ecd
EH		 798
799 /* Notify the ucode of the loaded section number and status */
800 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
801 val = val | (sec_num << shift_param);
802 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
803 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 804 }
805
034846cf
EH		 806 *first_ucode_section = last_read_idx;
807
afb88917
EH		 808 if (cpu == 1)
809 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
810 else
811 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
812
189fa2fa
EH		 813 return 0;
814}
e2d6f4e7 815
189fa2fa
EH		 816static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
817 const struct fw_img *image,
034846cf
EH		 818 int cpu,
819 int *first_ucode_section)
189fa2fa
EH		 820{
821 int shift_param;
189fa2fa 822 int i, ret = 0;
034846cf 823 u32 last_read_idx = 0;
189fa2fa
EH		 824
825 if (cpu == 1) {
826 shift_param = 0;
034846cf 827 *first_ucode_section = 0;
189fa2fa
EH		 828 } else {
829 shift_param = 16;
034846cf 830 (*first_ucode_section)++;
189fa2fa
EH		 831 }
832
034846cf
EH		 833 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
834 last_read_idx = i;
835
a6c4fb44
MG		 836 /*
837 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
838 * CPU1 to CPU2.
839 * PAGING_SEPARATOR_SECTION delimiter - separate between
840 * CPU2 non paged to CPU2 paging sec.
841 */
034846cf 842 if (!image->sec[i].data ||
a6c4fb44
MG		 843 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
844 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 845 IWL_DEBUG_FW(trans,
846 "Break since Data not valid or Empty section, sec = %d\n",
847 i);
189fa2fa 848 break;
034846cf
EH		 849 }
850
189fa2fa
EH		 851 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
852 if (ret)
853 return ret;
e2d6f4e7
EH		 854 }
855
189fa2fa
EH		 856 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
857 iwl_set_bits_prph(trans,
858 CSR_UCODE_LOAD_STATUS_ADDR,
859 (LMPM_CPU_UCODE_LOADING_COMPLETED |
860 LMPM_CPU_HDRS_LOADING_COMPLETED |
861 LMPM_CPU_UCODE_LOADING_STARTED) <<
862 shift_param);
863
034846cf
EH		 864 *first_ucode_section = last_read_idx;
865
e2d6f4e7
EH		 866 return 0;
867}
868
09e350f7
LK		 869static void iwl_pcie_apply_destination(struct iwl_trans *trans)
870{
871 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
872 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
873 int i;
874
875 if (dest->version)
876 IWL_ERR(trans,
877 "DBG DEST version is %d - expect issues\n",
878 dest->version);
879
880 IWL_INFO(trans, "Applying debug destination %s\n",
881 get_fw_dbg_mode_string(dest->monitor_mode));
882
883 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 884 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 885 else
886 IWL_WARN(trans, "PCI should have external buffer debug\n");
887
888 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
889 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
890 u32 val = le32_to_cpu(dest->reg_ops[i].val);
891
892 switch (dest->reg_ops[i].op) {
893 case CSR_ASSIGN:
894 iwl_write32(trans, addr, val);
895 break;
896 case CSR_SETBIT:
897 iwl_set_bit(trans, addr, BIT(val));
898 break;
899 case CSR_CLEARBIT:
900 iwl_clear_bit(trans, addr, BIT(val));
901 break;
902 case PRPH_ASSIGN:
903 iwl_write_prph(trans, addr, val);
904 break;
905 case PRPH_SETBIT:
906 iwl_set_bits_prph(trans, addr, BIT(val));
907 break;
908 case PRPH_CLEARBIT:
909 iwl_clear_bits_prph(trans, addr, BIT(val));
910 break;
869f3b15
HD		 911 case PRPH_BLOCKBIT:
912 if (iwl_read_prph(trans, addr) & BIT(val)) {
913 IWL_ERR(trans,
914 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
915 val, addr);
916 goto monitor;
917 }
918 break;
09e350f7
LK		 919 default:
920 IWL_ERR(trans, "FW debug - unknown OP %d\n",
921 dest->reg_ops[i].op);
922 break;
923 }
924 }
925
869f3b15 926monitor:
09e350f7
LK		 927 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
928 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
929 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 930 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
931 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
932 (trans_pcie->fw_mon_phys +
933 trans_pcie->fw_mon_size - 256) >>
934 dest->end_shift);
935 else
936 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >>
939 dest->end_shift);
09e350f7
LK		 940 }
941}
942
7afe3705 943static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 944 const struct fw_img *image)
cf614297 945{
c2d20201 946 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 947 int ret = 0;
034846cf 948 int first_ucode_section;
cf614297 949
dcab8ecd 950 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 951 image->is_dual_cpus ? "Dual" : "Single");
952
dcab8ecd
EH		 953 /* load to FW the binary non secured sections of CPU1 */
954 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
955 if (ret)
956 return ret;
e2d6f4e7
EH		 957
958 if (image->is_dual_cpus) {
189fa2fa
EH		 959 /* set CPU2 header address */
960 iwl_write_prph(trans,
961 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
962 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 963
189fa2fa 964 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 965 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
966 &first_ucode_section);
189fa2fa
EH		 967 if (ret)
968 return ret;
e2d6f4e7 969 }
cf614297 970
c2d20201
EG		 971 /* supported for 7000 only for the moment */
972 if (iwlwifi_mod_params.fw_monitor &&
973 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 974 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 975
976 if (trans_pcie->fw_mon_size) {
977 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
978 trans_pcie->fw_mon_phys >> 4);
979 iwl_write_prph(trans, MON_BUFF_END_ADDR,
980 (trans_pcie->fw_mon_phys +
981 trans_pcie->fw_mon_size) >> 4);
982 }
09e350f7
LK		 983 } else if (trans->dbg_dest_tlv) {
984 iwl_pcie_apply_destination(trans);
c2d20201
EG		 985 }
986
e12ba844 987 /* release CPU reset */
5dd9c68a 988 iwl_write32(trans, CSR_RESET, 0);
e12ba844 989
dcab8ecd
EH		 990 return 0;
991}
189fa2fa 992
5dd9c68a
EG		 993static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
994 const struct fw_img *image)
dcab8ecd
EH		 995{
996 int ret = 0;
997 int first_ucode_section;
dcab8ecd
EH		 998
999 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000 image->is_dual_cpus ? "Dual" : "Single");
1001
a2227ce2
EG		 1002 if (trans->dbg_dest_tlv)
1003 iwl_pcie_apply_destination(trans);
1004
16bc119b
EH		 1005 /* TODO: remove in the next Si step */
1006 ret = iwl_pcie_rsa_race_bug_wa(trans);
1007 if (ret)
1008 return ret;
1009
dcab8ecd
EH		 1010 /* configure the ucode to be ready to get the secured image */
1011 /* release CPU reset */
1012 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1013
1014 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1015 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1016 &first_ucode_section);
dcab8ecd
EH		 1017 if (ret)
1018 return ret;
1019
1020 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1021 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1022 &first_ucode_section);
cf614297
EG		 1023}
1024
0692fe41 1025static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 1026 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 1027{
fa9f3281 1028 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1029 bool hw_rfkill;
fa9f3281
EG		 1030 int ret;
1031
1032 mutex_lock(&trans_pcie->mutex);
1033
1034 /* Someone called stop_device, don't try to start_fw */
1035 if (trans_pcie->is_down) {
1036 IWL_WARN(trans,
1037 "Can't start_fw since the HW hasn't been started\n");
1038 ret = EIO;
1039 goto out;
1040 }
392f8b78 1041
496bab39 1042 /* This may fail if AMT took ownership of the device */
7afe3705 1043 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 1044 IWL_WARN(trans, "Exit HW not ready\n");
fa9f3281
EG		 1045 ret = -EIO;
1046 goto out;
392f8b78
EG		 1047 }
1048
8c46bb70
EG		 1049 iwl_enable_rfkill_int(trans);
1050
392f8b78 1051 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 1052 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1053 if (hw_rfkill)
eb7ff77e 1054 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1055 else
eb7ff77e 1056 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1057 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
fa9f3281
EG		 1058 if (hw_rfkill && !run_in_rfkill) {
1059 ret = -ERFKILL;
1060 goto out;
1061 }
392f8b78 1062
1042db2a 1063 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1064
7afe3705 1065 ret = iwl_pcie_nic_init(trans);
392f8b78 1066 if (ret) {
6d8f6eeb 1067 IWL_ERR(trans, "Unable to init nic\n");
fa9f3281 1068 goto out;
392f8b78
EG		 1069 }
1070
1071 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1072 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1073 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1074 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1075
1076 /* clear (again), then enable host interrupts */
1042db2a 1077 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1078 iwl_enable_interrupts(trans);
392f8b78
EG		 1079
1080 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1081 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1082 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1083
cf614297 1084 /* Load the given image to the HW */
5dd9c68a 1085 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
fa9f3281 1086 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd 1087 else
fa9f3281
EG		 1088 ret = iwl_pcie_load_given_ucode(trans, fw);
1089
1090out:
1091 mutex_unlock(&trans_pcie->mutex);
1092 return ret;
b3c2ce13
EG		 1093}
1094
adca1235 1095static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1096{
990aa6d7 1097 iwl_pcie_reset_ict(trans);
f02831be 1098 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1099}
1100
fa9f3281 1101static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1102{
43e58856 1103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1104 bool hw_rfkill, was_hw_rfkill;
1105
fa9f3281
EG		 1106 lockdep_assert_held(&trans_pcie->mutex);
1107
1108 if (trans_pcie->is_down)
1109 return;
1110
1111 trans_pcie->is_down = true;
1112
3dc3374f 1113 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1114
43e58856 1115 /* tell the device to stop sending interrupts */
7b70bd63 1116 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1117 iwl_disable_interrupts(trans);
7b70bd63 1118 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1119
ab6cf8e8 1120 /* device going down, Stop using ICT table */
990aa6d7 1121 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1122
1123 /*
1124 * If a HW restart happens during firmware loading,
1125 * then the firmware loading might call this function
1126 * and later it might be called again due to the
1127 * restart. So don't process again if the device is
1128 * already dead.
1129 */
31b8b343
EG		 1130 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1131 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1132 iwl_pcie_tx_stop(trans);
9805c446 1133 iwl_pcie_rx_stop(trans);
6379103e 1134
ab6cf8e8 1135 /* Power-down device's busmaster DMA clocks */
95411d04 1136 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1137 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1138 APMG_CLK_VAL_DMA_CLK_RQT);
1139 udelay(5);
1140 }
ab6cf8e8
EG		 1141 }
1142
1143 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1144 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1145 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1146
1147 /* Stop the device, and put it in low power state */
b7aaeae4 1148 iwl_pcie_apm_stop(trans, false);
43e58856 1149
03d6c3b0
EG		 1150 /* stop and reset the on-board processor */
1151 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1152 udelay(20);
1153
1154 /*
1155 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1156 * This is a bug in certain verions of the hardware.
1157 * Certain devices also keep sending HW RF kill interrupt all
1158 * the time, unless the interrupt is ACKed even if the interrupt
1159 * should be masked. Re-ACK all the interrupts here.
43e58856 1160 */
7b70bd63 1161 spin_lock(&trans_pcie->irq_lock);
43e58856 1162 iwl_disable_interrupts(trans);
7b70bd63 1163 spin_unlock(&trans_pcie->irq_lock);
43e58856 1164
74fda971
DF		 1165
1166 /* clear all status bits */
eb7ff77e
AN		 1167 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1168 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1169 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1170 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1171
1172 /*
1173 * Even if we stop the HW, we still want the RF kill
1174 * interrupt
1175 */
1176 iwl_enable_rfkill_int(trans);
1177
1178 /*
1179 * Check again since the RF kill state may have changed while
1180 * all the interrupts were disabled, in this case we couldn't
1181 * receive the RF kill interrupt and update the state in the
1182 * op_mode.
3dc3374f
EG		 1183 * Don't call the op_mode if the rkfill state hasn't changed.
1184 * This allows the op_mode to call stop_device from the rfkill
1185 * notification without endless recursion. Under very rare
1186 * circumstances, we might have a small recursion if the rfkill
1187 * state changed exactly now while we were called from stop_device.
1188 * This is very unlikely but can happen and is supported.
a4082843
AN		 1189 */
1190 hw_rfkill = iwl_is_rfkill_set(trans);
1191 if (hw_rfkill)
eb7ff77e 1192 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1193 else
eb7ff77e 1194 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1195 if (hw_rfkill != was_hw_rfkill)
14cfca71 1196 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1197
1198 /* re-take ownership to prevent other users from stealing the deivce */
1199 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1200}
1201
fa9f3281
EG		 1202static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1203{
1204 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1205
1206 mutex_lock(&trans_pcie->mutex);
1207 _iwl_trans_pcie_stop_device(trans, low_power);
1208 mutex_unlock(&trans_pcie->mutex);
1209}
1210
14cfca71
JB		 1211void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1212{
fa9f3281
EG		 1213 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1214 IWL_TRANS_GET_PCIE_TRANS(trans);
1215
1216 lockdep_assert_held(&trans_pcie->mutex);
1217
14cfca71 1218 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1219 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1220}
1221
23ae6128
MG		 1222static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1223 bool reset)
2dd4f9f7 1224{
33b56af1
EG		 1225 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1226
23ae6128 1227 if (!reset) {
6dfb36c8
EP		 1228 /* Enable persistence mode to avoid reset */
1229 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1230 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1231 }
1232
2dd4f9f7 1233 iwl_disable_interrupts(trans);
debff618
JB		 1234
1235 /*
1236 * in testing mode, the host stays awake and the
1237 * hardware won't be reset (not even partially)
1238 */
1239 if (test)
1240 return;
1241
ddaf5a5b
JB		 1242 iwl_pcie_disable_ict(trans);
1243
33b56af1
EG		 1244 synchronize_irq(trans_pcie->pci_dev->irq);
1245
2dd4f9f7
JB		 1246 iwl_clear_bit(trans, CSR_GP_CNTRL,
1247 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1248 iwl_clear_bit(trans, CSR_GP_CNTRL,
1249 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1250
23ae6128 1251 if (reset) {
6dfb36c8
EP		 1252 /*
1253 * reset TX queues -- some of their registers reset during S3
1254 * so if we don't reset everything here the D3 image would try
1255 * to execute some invalid memory upon resume
1256 */
1257 iwl_trans_pcie_tx_reset(trans);
1258 }
ddaf5a5b
JB		 1259
1260 iwl_pcie_set_pwr(trans, true);
1261}
1262
1263static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1264 enum iwl_d3_status *status,
23ae6128 1265 bool test, bool reset)
ddaf5a5b
JB		 1266{
1267 u32 val;
1268 int ret;
1269
debff618
JB		 1270 if (test) {
1271 iwl_enable_interrupts(trans);
1272 *status = IWL_D3_STATUS_ALIVE;
1273 return 0;
1274 }
1275
ddaf5a5b
JB		 1276 /*
1277 * Also enables interrupts - none will happen as the device doesn't
1278 * know we're waking it up, only when the opmode actually tells it
1279 * after this call.
1280 */
1281 iwl_pcie_reset_ict(trans);
1282
1283 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1284 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1285
01e58a28
EG		 1286 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1287 udelay(2);
1288
ddaf5a5b
JB		 1289 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1290 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1291 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1292 25000);
7f2ac8fb 1293 if (ret < 0) {
ddaf5a5b
JB		 1294 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1295 return ret;
1296 }
1297
a3ead656
EG		 1298 iwl_pcie_set_pwr(trans, false);
1299
23ae6128 1300 if (!reset) {
6dfb36c8
EP		 1301 iwl_clear_bit(trans, CSR_GP_CNTRL,
1302 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1303 } else {
1304 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1305
6dfb36c8
EP		 1306 ret = iwl_pcie_rx_init(trans);
1307 if (ret) {
1308 IWL_ERR(trans,
1309 "Failed to resume the device (RX reset)\n");
1310 return ret;
1311 }
ddaf5a5b
JB		 1312 }
1313
a3ead656
EG		 1314 val = iwl_read32(trans, CSR_RESET);
1315 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1316 *status = IWL_D3_STATUS_RESET;
1317 else
1318 *status = IWL_D3_STATUS_ALIVE;
1319
ddaf5a5b 1320 return 0;
2dd4f9f7
JB		 1321}
1322
fa9f3281 1323static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1324{
fa9f3281 1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1326 bool hw_rfkill;
a8b691e6 1327 int err;
e6bb4c9c 1328
fa9f3281
EG		 1329 lockdep_assert_held(&trans_pcie->mutex);
1330
7afe3705 1331 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1332 if (err) {
d6f1c316 1333 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1334 return err;
ebb7678d 1335 }
a6c684ee 1336
2997494f 1337 /* Reset the entire device */
ce836c76 1338 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1339
1340 usleep_range(10, 15);
1341
7afe3705 1342 iwl_pcie_apm_init(trans);
a6c684ee 1343
226c02ca
EG		 1344 /* From now on, the op_mode will be kept updated about RF kill state */
1345 iwl_enable_rfkill_int(trans);
1346
fa9f3281
EG		 1347 /* Set is_down to false here so that...*/
1348 trans_pcie->is_down = false;
1349
8d425517 1350 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1351 if (hw_rfkill)
eb7ff77e 1352 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1353 else
eb7ff77e 1354 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1355 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1356 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1357
4cbb8e50
LC		 1358 /* Make sure we sync here, because we'll need full access later */
1359 if (low_power)
1360 pm_runtime_resume(trans->dev);
1361
a8b691e6 1362 return 0;
e6bb4c9c
EG		 1363}
1364
fa9f3281
EG		 1365static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1366{
1367 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1368 int ret;
1369
1370 mutex_lock(&trans_pcie->mutex);
1371 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1372 mutex_unlock(&trans_pcie->mutex);
1373
1374 return ret;
1375}
1376
a4082843 1377static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1378{
20d3b647 1379 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1380
fa9f3281
EG		 1381 mutex_lock(&trans_pcie->mutex);
1382
a4082843 1383 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1384 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1385 iwl_disable_interrupts(trans);
7b70bd63 1386 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1387
b7aaeae4 1388 iwl_pcie_apm_stop(trans, true);
cc56feb2 1389
7b70bd63 1390 spin_lock(&trans_pcie->irq_lock);
218733cf 1391 iwl_disable_interrupts(trans);
7b70bd63 1392 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1393
8d96bb61 1394 iwl_pcie_disable_ict(trans);
33b56af1 1395
fa9f3281 1396 mutex_unlock(&trans_pcie->mutex);
33b56af1
EG		 1397
1398 synchronize_irq(trans_pcie->pci_dev->irq);
cc56feb2
EG		 1399}
1400
03905495
EG		 1401static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1402{
05f5b97e 1403 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1404}
1405
1406static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1407{
05f5b97e 1408 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1409}
1410
1411static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1412{
05f5b97e 1413 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1414}
1415
6a06b6c1
EG		 1416static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1417{
f9477c17
AP		 1418 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1419 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1420 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1421}
1422
1423static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1424 u32 val)
1425{
1426 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1427 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1428 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1429}
1430
f14d6b39
JB		 1431static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1432{
1433 WARN_ON(1);
1434 return 0;
1435}
1436
c6f600fc 1437static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1438 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1439{
1440 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1441
1442 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1443 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1444 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1445 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1446 trans_pcie->n_no_reclaim_cmds = 0;
1447 else
1448 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1449 if (trans_pcie->n_no_reclaim_cmds)
1450 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1451 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1452
6c4fbcbc
EG		 1453 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1454 trans_pcie->rx_page_order =
1455 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1456
ab02165c 1457 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
046db346 1458 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1459 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1460 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1461
39bdb17e
SD		 1462 trans->command_groups = trans_cfg->command_groups;
1463 trans->command_groups_size = trans_cfg->command_groups_size;
1464
483f3ab1
EP		 1465 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1466 trans_pcie->ref_count = 1;
1467
f14d6b39
JB		 1468 /* Initialize NAPI here - it should be before registering to mac80211
1469 * in the opmode but after the HW struct is allocated.
1470 * As this function may be called again in some corner cases don't
1471 * do anything if NAPI was already initialized.
1472 */
1be5d8cc 1473 if (!trans_pcie->napi.poll) {
f14d6b39 1474 init_dummy_netdev(&trans_pcie->napi_dev);
1be5d8cc
JB		 1475 netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi,
1476 iwl_pcie_dummy_napi_poll, 64);
f14d6b39 1477 }
c6f600fc
MV		 1478}
1479
d1ff5253 1480void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1481{
20d3b647 1482 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1483 int i;
a42a1844 1484
b3ff1270
LC		 1485 /* TODO: check if this is really needed */
1486 pm_runtime_disable(trans->dev);
4cbb8e50 1487
0aa86df6 1488 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1489
f02831be 1490 iwl_pcie_tx_free(trans);
9805c446 1491 iwl_pcie_rx_free(trans);
6379103e 1492
a8b691e6
JB		 1493 free_irq(trans_pcie->pci_dev->irq, trans);
1494 iwl_pcie_free_ict(trans);
a42a1844
EG		 1495
1496 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1497 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1498 pci_release_regions(trans_pcie->pci_dev);
1499 pci_disable_device(trans_pcie->pci_dev);
1500
f14d6b39
JB		 1501 if (trans_pcie->napi.poll)
1502 netif_napi_del(&trans_pcie->napi);
1503
c2d20201
EG		 1504 iwl_pcie_free_fw_monitor(trans);
1505
6eb5e529
EG		 1506 for_each_possible_cpu(i) {
1507 struct iwl_tso_hdr_page *p =
1508 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1509
1510 if (p->page)
1511 __free_page(p->page);
1512 }
1513
1514 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 1515 iwl_trans_free(trans);
34c1b7ba
EG		 1516}
1517
47107e84
DF		 1518static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1519{
47107e84 1520 if (state)
eb7ff77e 1521 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1522 else
eb7ff77e 1523 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1524}
1525
23ba9340
EG		 1526static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1527 unsigned long *flags)
7a65d170
EG		 1528{
1529 int ret;
cfb4e624
JB		 1530 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1531
1532 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1533
fc8a350d 1534 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1535 goto out;
1536
7a65d170 1537 /* this bit wakes up the NIC */
e139dc4a
LE		 1538 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1539 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1540 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1541 udelay(2);
7a65d170
EG		 1542
1543 /*
1544 * These bits say the device is running, and should keep running for
1545 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1546 * but they do not indicate that embedded SRAM is restored yet;
1547 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1548 * to/from host DRAM when sleeping/waking for power-saving.
1549 * Each direction takes approximately 1/4 millisecond; with this
1550 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1551 * series of register accesses are expected (e.g. reading Event Log),
1552 * to keep device from sleeping.
1553 *
1554 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1555 * SRAM is okay/restored. We don't check that here because this call
1556 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1557 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1558 *
1559 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1560 * and do not save/restore SRAM when power cycling.
1561 */
1562 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1563 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1564 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1565 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1566 if (unlikely(ret < 0)) {
1567 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1568 WARN_ONCE(1,
1569 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1570 iwl_read32(trans, CSR_GP_CNTRL));
1571 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1572 return false;
7a65d170
EG		 1573 }
1574
b9439491 1575out:
e56b04ef
LE		 1576 /*
1577 * Fool sparse by faking we release the lock - sparse will
1578 * track nic_access anyway.
1579 */
cfb4e624 1580 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1581 return true;
1582}
1583
e56b04ef
LE		 1584static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1585 unsigned long *flags)
7a65d170 1586{
cfb4e624 1587 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1588
cfb4e624 1589 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1590
1591 /*
1592 * Fool sparse by faking we acquiring the lock - sparse will
1593 * track nic_access anyway.
1594 */
cfb4e624 1595 __acquire(&trans_pcie->reg_lock);
e56b04ef 1596
fc8a350d 1597 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1598 goto out;
1599
e139dc4a
LE		 1600 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1601 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1602 /*
1603 * Above we read the CSR_GP_CNTRL register, which will flush
1604 * any previous writes, but we need the write that clears the
1605 * MAC_ACCESS_REQ bit to be performed before any other writes
1606 * scheduled on different CPUs (after we drop reg_lock).
1607 */
1608 mmiowb();
b9439491 1609out:
cfb4e624 1610 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1611}
1612
4fd442db
EG		 1613static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1614 void *buf, int dwords)
1615{
1616 unsigned long flags;
1617 int offs, ret = 0;
1618 u32 *vals = buf;
1619
23ba9340 1620 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1621 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1622 for (offs = 0; offs < dwords; offs++)
1623 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1624 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1625 } else {
1626 ret = -EBUSY;
1627 }
4fd442db
EG		 1628 return ret;
1629}
1630
1631static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1632 const void *buf, int dwords)
4fd442db
EG		 1633{
1634 unsigned long flags;
1635 int offs, ret = 0;
bf0fd5da 1636 const u32 *vals = buf;
4fd442db 1637
23ba9340 1638 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1639 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1640 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1641 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1642 vals ? vals[offs] : 0);
e56b04ef 1643 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1644 } else {
1645 ret = -EBUSY;
1646 }
4fd442db
EG		 1647 return ret;
1648}
7a65d170 1649
e0b8d405
EG		 1650static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1651 unsigned long txqs,
1652 bool freeze)
1653{
1654 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1655 int queue;
1656
1657 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1658 struct iwl_txq *txq = &trans_pcie->txq[queue];
1659 unsigned long now;
1660
1661 spin_lock_bh(&txq->lock);
1662
1663 now = jiffies;
1664
1665 if (txq->frozen == freeze)
1666 goto next_queue;
1667
1668 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1669 freeze ? "Freezing" : "Waking", queue);
1670
1671 txq->frozen = freeze;
1672
1673 if (txq->q.read_ptr == txq->q.write_ptr)
1674 goto next_queue;
1675
1676 if (freeze) {
1677 if (unlikely(time_after(now,
1678 txq->stuck_timer.expires))) {
1679 /*
1680 * The timer should have fired, maybe it is
1681 * spinning right now on the lock.
1682 */
1683 goto next_queue;
1684 }
1685 /* remember how long until the timer fires */
1686 txq->frozen_expiry_remainder =
1687 txq->stuck_timer.expires - now;
1688 del_timer(&txq->stuck_timer);
1689 goto next_queue;
1690 }
1691
1692 /*
1693 * Wake a non-empty queue -> arm timer with the
1694 * remainder before it froze
1695 */
1696 mod_timer(&txq->stuck_timer,
1697 now + txq->frozen_expiry_remainder);
1698
1699next_queue:
1700 spin_unlock_bh(&txq->lock);
1701 }
1702}
1703
0cd58eaa
EG		 1704static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1705{
1706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1707 int i;
1708
1709 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1710 struct iwl_txq *txq = &trans_pcie->txq[i];
1711
1712 if (i == trans_pcie->cmd_queue)
1713 continue;
1714
1715 spin_lock_bh(&txq->lock);
1716
1717 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1718 txq->block--;
1719 if (!txq->block) {
1720 iwl_write32(trans, HBUS_TARG_WRPTR,
1721 txq->q.write_ptr | (i << 8));
1722 }
1723 } else if (block) {
1724 txq->block++;
1725 }
1726
1727 spin_unlock_bh(&txq->lock);
1728 }
1729}
1730
5f178cd2
EG		 1731#define IWL_FLUSH_WAIT_MS 2000
1732
3cafdbe6 1733static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1734{
8ad71bef 1735 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1736 struct iwl_txq *txq;
5f178cd2
EG		 1737 struct iwl_queue *q;
1738 int cnt;
1739 unsigned long now = jiffies;
1c3fea82
EG		 1740 u32 scd_sram_addr;
1741 u8 buf[16];
5f178cd2
EG		 1742 int ret = 0;
1743
1744 /* waiting for all the tx frames complete might take a while */
035f7ff2 1745 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1746 u8 wr_ptr;
1747
9ba1947a 1748 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1749 continue;
3cafdbe6
EG		 1750 if (!test_bit(cnt, trans_pcie->queue_used))
1751 continue;
1752 if (!(BIT(cnt) & txq_bm))
1753 continue;
748fa67c
EG		 1754
1755 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1756 txq = &trans_pcie->txq[cnt];
5f178cd2 1757 q = &txq->q;
fa1a91fd
EG		 1758 wr_ptr = ACCESS_ONCE(q->write_ptr);
1759
1760 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1761 !time_after(jiffies,
1762 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1763 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1764
1765 if (WARN_ONCE(wr_ptr != write_ptr,
1766 "WR pointer moved while flushing %d -> %d\n",
1767 wr_ptr, write_ptr))
1768 return -ETIMEDOUT;
5f178cd2 1769 msleep(1);
fa1a91fd 1770 }
5f178cd2
EG		 1771
1772 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1773 IWL_ERR(trans,
1774 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1775 ret = -ETIMEDOUT;
1776 break;
1777 }
748fa67c 1778 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1779 }
1c3fea82
EG		 1780
1781 if (!ret)
1782 return 0;
1783
1784 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1785 txq->q.read_ptr, txq->q.write_ptr);
1786
1787 scd_sram_addr = trans_pcie->scd_base_addr +
1788 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1789 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1790
1791 iwl_print_hex_error(trans, buf, sizeof(buf));
1792
1793 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1794 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1795 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1796
1797 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1798 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1799 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1800 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1801 u32 tbl_dw =
1802 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1803 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1804
1805 if (cnt & 0x1)
1806 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1807 else
1808 tbl_dw = tbl_dw & 0x0000FFFF;
1809
1810 IWL_ERR(trans,
1811 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1812 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1813 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1814 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1815 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1816 }
1817
5f178cd2
EG		 1818 return ret;
1819}
1820
e139dc4a
LE		 1821static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1822 u32 mask, u32 value)
1823{
e56b04ef 1824 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1825 unsigned long flags;
1826
e56b04ef 1827 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1828 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1829 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1830}
1831
7616f334
EP		 1832void iwl_trans_pcie_ref(struct iwl_trans *trans)
1833{
1834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1835 unsigned long flags;
1836
1837 if (iwlwifi_mod_params.d0i3_disable)
1838 return;
1839
1840 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1841 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1842 trans_pcie->ref_count++;
b3ff1270 1843 pm_runtime_get(&trans_pcie->pci_dev->dev);
7616f334
EP		 1844 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1845}
1846
1847void iwl_trans_pcie_unref(struct iwl_trans *trans)
1848{
1849 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1850 unsigned long flags;
1851
1852 if (iwlwifi_mod_params.d0i3_disable)
1853 return;
1854
1855 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1856 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1857 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1858 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1859 return;
1860 }
1861 trans_pcie->ref_count--;
4cbb8e50 1862
b3ff1270
LC		 1863 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
1864 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 1865
7616f334
EP		 1866 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1867}
1868
ff620849
EG		 1869static const char *get_csr_string(int cmd)
1870{
d9fb6465 1871#define IWL_CMD(x) case x: return #x
ff620849
EG		 1872 switch (cmd) {
1873 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1874 IWL_CMD(CSR_INT_COALESCING);
1875 IWL_CMD(CSR_INT);
1876 IWL_CMD(CSR_INT_MASK);
1877 IWL_CMD(CSR_FH_INT_STATUS);
1878 IWL_CMD(CSR_GPIO_IN);
1879 IWL_CMD(CSR_RESET);
1880 IWL_CMD(CSR_GP_CNTRL);
1881 IWL_CMD(CSR_HW_REV);
1882 IWL_CMD(CSR_EEPROM_REG);
1883 IWL_CMD(CSR_EEPROM_GP);
1884 IWL_CMD(CSR_OTP_GP_REG);
1885 IWL_CMD(CSR_GIO_REG);
1886 IWL_CMD(CSR_GP_UCODE_REG);
1887 IWL_CMD(CSR_GP_DRIVER_REG);
1888 IWL_CMD(CSR_UCODE_DRV_GP1);
1889 IWL_CMD(CSR_UCODE_DRV_GP2);
1890 IWL_CMD(CSR_LED_REG);
1891 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1892 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1893 IWL_CMD(CSR_ANA_PLL_CFG);
1894 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1895 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1896 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1897 default:
1898 return "UNKNOWN";
1899 }
d9fb6465 1900#undef IWL_CMD
ff620849
EG		 1901}
1902
990aa6d7 1903void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1904{
1905 int i;
1906 static const u32 csr_tbl[] = {
1907 CSR_HW_IF_CONFIG_REG,
1908 CSR_INT_COALESCING,
1909 CSR_INT,
1910 CSR_INT_MASK,
1911 CSR_FH_INT_STATUS,
1912 CSR_GPIO_IN,
1913 CSR_RESET,
1914 CSR_GP_CNTRL,
1915 CSR_HW_REV,
1916 CSR_EEPROM_REG,
1917 CSR_EEPROM_GP,
1918 CSR_OTP_GP_REG,
1919 CSR_GIO_REG,
1920 CSR_GP_UCODE_REG,
1921 CSR_GP_DRIVER_REG,
1922 CSR_UCODE_DRV_GP1,
1923 CSR_UCODE_DRV_GP2,
1924 CSR_LED_REG,
1925 CSR_DRAM_INT_TBL_REG,
1926 CSR_GIO_CHICKEN_BITS,
1927 CSR_ANA_PLL_CFG,
a812cba9 1928 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1929 CSR_HW_REV_WA_REG,
1930 CSR_DBG_HPET_MEM_REG
1931 };
1932 IWL_ERR(trans, "CSR values:\n");
1933 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1934 "CSR_INT_PERIODIC_REG)\n");
1935 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1936 IWL_ERR(trans, " %25s: 0X%08x\n",
1937 get_csr_string(csr_tbl[i]),
1042db2a 1938 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1939 }
1940}
1941
87e5666c
EG		 1942#ifdef CONFIG_IWLWIFI_DEBUGFS
1943/* create and remove of files */
1944#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1945 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1946 &iwl_dbgfs_##name##_ops)) \
9da987ac 1947 goto err; \
87e5666c
EG		 1948} while (0)
1949
1950/* file operation */
87e5666c 1951#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1952static const struct file_operations iwl_dbgfs_##name##_ops = { \
1953 .read = iwl_dbgfs_##name##_read, \
234e3405 1954 .open = simple_open, \
87e5666c
EG		 1955 .llseek = generic_file_llseek, \
1956};
1957
16db88ba 1958#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1959static const struct file_operations iwl_dbgfs_##name##_ops = { \
1960 .write = iwl_dbgfs_##name##_write, \
234e3405 1961 .open = simple_open, \
16db88ba
EG		 1962 .llseek = generic_file_llseek, \
1963};
1964
87e5666c 1965#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1966static const struct file_operations iwl_dbgfs_##name##_ops = { \
1967 .write = iwl_dbgfs_##name##_write, \
1968 .read = iwl_dbgfs_##name##_read, \
234e3405 1969 .open = simple_open, \
87e5666c
EG		 1970 .llseek = generic_file_llseek, \
1971};
1972
87e5666c 1973static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1974 char __user *user_buf,
1975 size_t count, loff_t *ppos)
8ad71bef 1976{
5a878bf6 1977 struct iwl_trans *trans = file->private_data;
8ad71bef 1978 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1979 struct iwl_txq *txq;
87e5666c
EG		 1980 struct iwl_queue *q;
1981 char *buf;
1982 int pos = 0;
1983 int cnt;
1984 int ret;
1745e440
WYG		 1985 size_t bufsz;
1986
e0b8d405 1987 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1988
f9e75447 1989 if (!trans_pcie->txq)
87e5666c 1990 return -EAGAIN;
f9e75447 1991
87e5666c
EG		 1992 buf = kzalloc(bufsz, GFP_KERNEL);
1993 if (!buf)
1994 return -ENOMEM;
1995
035f7ff2 1996 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1997 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1998 q = &txq->q;
1999 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2000 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 2001 cnt, q->read_ptr, q->write_ptr,
9eae88fa 2002 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2003 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2004 txq->need_update, txq->frozen,
f40faf62 2005 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2006 }
2007 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2008 kfree(buf);
2009 return ret;
2010}
2011
2012static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2013 char __user *user_buf,
2014 size_t count, loff_t *ppos)
2015{
5a878bf6 2016 struct iwl_trans *trans = file->private_data;
20d3b647 2017 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2018 char *buf;
2019 int pos = 0, i, ret;
2020 size_t bufsz = sizeof(buf);
2021
2022 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2023
2024 if (!trans_pcie->rxq)
2025 return -EAGAIN;
2026
2027 buf = kzalloc(bufsz, GFP_KERNEL);
2028 if (!buf)
2029 return -ENOMEM;
2030
2031 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2032 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2033
2034 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2035 i);
2036 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2037 rxq->read);
2038 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2039 rxq->write);
2040 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2041 rxq->write_actual);
2042 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2043 rxq->need_update);
2044 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2045 rxq->free_count);
2046 if (rxq->rb_stts) {
2047 pos += scnprintf(buf + pos, bufsz - pos,
2048 "\tclosed_rb_num: %u\n",
2049 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2050 0x0FFF);
2051 } else {
2052 pos += scnprintf(buf + pos, bufsz - pos,
2053 "\tclosed_rb_num: Not Allocated\n");
2054 }
87e5666c 2055 }
78485054
SS		 2056 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2057 kfree(buf);
2058
2059 return ret;
87e5666c
EG		 2060}
2061
1f7b6172
EG		 2062static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2063 char __user *user_buf,
20d3b647
JB		 2064 size_t count, loff_t *ppos)
2065{
1f7b6172 2066 struct iwl_trans *trans = file->private_data;
20d3b647 2067 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2068 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2069
2070 int pos = 0;
2071 char *buf;
2072 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2073 ssize_t ret;
2074
2075 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2076 if (!buf)
1f7b6172 2077 return -ENOMEM;
1f7b6172
EG		 2078
2079 pos += scnprintf(buf + pos, bufsz - pos,
2080 "Interrupt Statistics Report:\n");
2081
2082 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2083 isr_stats->hw);
2084 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2085 isr_stats->sw);
2086 if (isr_stats->sw || isr_stats->hw) {
2087 pos += scnprintf(buf + pos, bufsz - pos,
2088 "\tLast Restarting Code: 0x%X\n",
2089 isr_stats->err_code);
2090 }
2091#ifdef CONFIG_IWLWIFI_DEBUG
2092 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2093 isr_stats->sch);
2094 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2095 isr_stats->alive);
2096#endif
2097 pos += scnprintf(buf + pos, bufsz - pos,
2098 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2099
2100 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2101 isr_stats->ctkill);
2102
2103 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2104 isr_stats->wakeup);
2105
2106 pos += scnprintf(buf + pos, bufsz - pos,
2107 "Rx command responses:\t\t %u\n", isr_stats->rx);
2108
2109 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2110 isr_stats->tx);
2111
2112 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2113 isr_stats->unhandled);
2114
2115 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2116 kfree(buf);
2117 return ret;
2118}
2119
2120static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2121 const char __user *user_buf,
2122 size_t count, loff_t *ppos)
2123{
2124 struct iwl_trans *trans = file->private_data;
20d3b647 2125 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2126 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2127
2128 char buf[8];
2129 int buf_size;
2130 u32 reset_flag;
2131
2132 memset(buf, 0, sizeof(buf));
2133 buf_size = min(count, sizeof(buf) - 1);
2134 if (copy_from_user(buf, user_buf, buf_size))
2135 return -EFAULT;
2136 if (sscanf(buf, "%x", &reset_flag) != 1)
2137 return -EFAULT;
2138 if (reset_flag == 0)
2139 memset(isr_stats, 0, sizeof(*isr_stats));
2140
2141 return count;
2142}
2143
16db88ba 2144static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2145 const char __user *user_buf,
2146 size_t count, loff_t *ppos)
16db88ba
EG		 2147{
2148 struct iwl_trans *trans = file->private_data;
2149 char buf[8];
2150 int buf_size;
2151 int csr;
2152
2153 memset(buf, 0, sizeof(buf));
2154 buf_size = min(count, sizeof(buf) - 1);
2155 if (copy_from_user(buf, user_buf, buf_size))
2156 return -EFAULT;
2157 if (sscanf(buf, "%d", &csr) != 1)
2158 return -EFAULT;
2159
990aa6d7 2160 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2161
2162 return count;
2163}
2164
16db88ba 2165static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2166 char __user *user_buf,
2167 size_t count, loff_t *ppos)
16db88ba
EG		 2168{
2169 struct iwl_trans *trans = file->private_data;
94543a8d 2170 char *buf = NULL;
56c2477f 2171 ssize_t ret;
16db88ba 2172
56c2477f
JB		 2173 ret = iwl_dump_fh(trans, &buf);
2174 if (ret < 0)
2175 return ret;
2176 if (!buf)
2177 return -EINVAL;
2178 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2179 kfree(buf);
16db88ba
EG		 2180 return ret;
2181}
2182
1f7b6172 2183DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2184DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2185DEBUGFS_READ_FILE_OPS(rx_queue);
2186DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2187DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2188
f8a1edb7
JB		 2189/* Create the debugfs files and directories */
2190int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2191{
f8a1edb7
JB		 2192 struct dentry *dir = trans->dbgfs_dir;
2193
87e5666c
EG		 2194 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2195 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2196 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2197 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2198 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2199 return 0;
9da987ac
MV		 2200
2201err:
2202 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2203 return -ENOMEM;
87e5666c 2204}
aadede6e 2205#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2206
2207static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2208{
2209 u32 cmdlen = 0;
2210 int i;
2211
2212 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2213 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2214
2215 return cmdlen;
2216}
2217
bd7fc617
EG		 2218static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2219 struct iwl_fw_error_dump_data **data,
2220 int allocated_rb_nums)
2221{
2222 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2223 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2224 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2225 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2226 u32 i, r, j, rb_len = 0;
2227
2228 spin_lock(&rxq->lock);
2229
2230 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2231
2232 for (i = rxq->read, j = 0;
2233 i != r && j < allocated_rb_nums;
2234 i = (i + 1) & RX_QUEUE_MASK, j++) {
2235 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2236 struct iwl_fw_error_dump_rb *rb;
2237
2238 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2239 DMA_FROM_DEVICE);
2240
2241 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2242
2243 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2244 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2245 rb = (void *)(*data)->data;
2246 rb->index = cpu_to_le32(i);
2247 memcpy(rb->data, page_address(rxb->page), max_len);
2248 /* remap the page for the free benefit */
2249 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2250 max_len,
2251 DMA_FROM_DEVICE);
2252
2253 *data = iwl_fw_error_next_data(*data);
2254 }
2255
2256 spin_unlock(&rxq->lock);
2257
2258 return rb_len;
2259}
473ad712
EG		 2260#define IWL_CSR_TO_DUMP (0x250)
2261
2262static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2263 struct iwl_fw_error_dump_data **data)
2264{
2265 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2266 __le32 *val;
2267 int i;
2268
2269 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2270 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2271 val = (void *)(*data)->data;
2272
2273 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2274 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2275
2276 *data = iwl_fw_error_next_data(*data);
2277
2278 return csr_len;
2279}
2280
06d51e0d
LK		 2281static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2282 struct iwl_fw_error_dump_data **data)
2283{
2284 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2285 unsigned long flags;
2286 __le32 *val;
2287 int i;
2288
23ba9340 2289 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2290 return 0;
2291
2292 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2293 (*data)->len = cpu_to_le32(fh_regs_len);
2294 val = (void *)(*data)->data;
2295
2296 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2297 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2298
2299 iwl_trans_release_nic_access(trans, &flags);
2300
2301 *data = iwl_fw_error_next_data(*data);
2302
2303 return sizeof(**data) + fh_regs_len;
2304}
2305
cc79ef66
LK		 2306static u32
2307iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2308 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2309 u32 monitor_len)
2310{
2311 u32 buf_size_in_dwords = (monitor_len >> 2);
2312 u32 *buffer = (u32 *)fw_mon_data->data;
2313 unsigned long flags;
2314 u32 i;
2315
23ba9340 2316 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2317 return 0;
2318
14ef1b43 2319 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2320 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2321 buffer[i] = iwl_read_prph_no_grab(trans,
2322 MON_DMARB_RD_DATA_ADDR);
2323 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2324
2325 iwl_trans_release_nic_access(trans, &flags);
2326
2327 return monitor_len;
2328}
2329
36fb9017
OG		 2330static u32
2331iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2332 struct iwl_fw_error_dump_data **data,
2333 u32 monitor_len)
2334{
2335 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2336 u32 len = 0;
2337
2338 if ((trans_pcie->fw_mon_page &&
2339 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2340 trans->dbg_dest_tlv) {
2341 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2342 u32 base, write_ptr, wrap_cnt;
2343
2344 /* If there was a dest TLV - use the values from there */
2345 if (trans->dbg_dest_tlv) {
2346 write_ptr =
2347 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2348 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2349 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2350 } else {
2351 base = MON_BUFF_BASE_ADDR;
2352 write_ptr = MON_BUFF_WRPTR;
2353 wrap_cnt = MON_BUFF_CYCLE_CNT;
2354 }
2355
2356 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2357 fw_mon_data = (void *)(*data)->data;
2358 fw_mon_data->fw_mon_wr_ptr =
2359 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2360 fw_mon_data->fw_mon_cycle_cnt =
2361 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2362 fw_mon_data->fw_mon_base_ptr =
2363 cpu_to_le32(iwl_read_prph(trans, base));
2364
2365 len += sizeof(**data) + sizeof(*fw_mon_data);
2366 if (trans_pcie->fw_mon_page) {
2367 /*
2368 * The firmware is now asserted, it won't write anything
2369 * to the buffer. CPU can take ownership to fetch the
2370 * data. The buffer will be handed back to the device
2371 * before the firmware will be restarted.
2372 */
2373 dma_sync_single_for_cpu(trans->dev,
2374 trans_pcie->fw_mon_phys,
2375 trans_pcie->fw_mon_size,
2376 DMA_FROM_DEVICE);
2377 memcpy(fw_mon_data->data,
2378 page_address(trans_pcie->fw_mon_page),
2379 trans_pcie->fw_mon_size);
2380
2381 monitor_len = trans_pcie->fw_mon_size;
2382 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2383 /*
2384 * Update pointers to reflect actual values after
2385 * shifting
2386 */
2387 base = iwl_read_prph(trans, base) <<
2388 trans->dbg_dest_tlv->base_shift;
2389 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2390 monitor_len / sizeof(u32));
2391 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2392 monitor_len =
2393 iwl_trans_pci_dump_marbh_monitor(trans,
2394 fw_mon_data,
2395 monitor_len);
2396 } else {
2397 /* Didn't match anything - output no monitor data */
2398 monitor_len = 0;
2399 }
2400
2401 len += monitor_len;
2402 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2403 }
2404
2405 return len;
2406}
2407
2408static struct iwl_trans_dump_data
2409*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2410 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2411{
2412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2413 struct iwl_fw_error_dump_data *data;
2414 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2415 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2416 struct iwl_trans_dump_data *dump_data;
bd7fc617 2417 u32 len, num_rbs;
99684ae3 2418 u32 monitor_len;
4d075007 2419 int i, ptr;
96a6497b
SS		 2420 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2421 !trans->cfg->mq_rx_supported;
4d075007 2422
473ad712
EG		 2423 /* transport dump header */
2424 len = sizeof(*dump_data);
2425
2426 /* host commands */
2427 len += sizeof(*data) +
c2d20201
EG		 2428 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2429
473ad712 2430 /* FW monitor */
99684ae3 2431 if (trans_pcie->fw_mon_page) {
c544e9c4 2432 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2433 trans_pcie->fw_mon_size;
2434 monitor_len = trans_pcie->fw_mon_size;
2435 } else if (trans->dbg_dest_tlv) {
2436 u32 base, end;
2437
2438 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2439 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2440
2441 base = iwl_read_prph(trans, base) <<
2442 trans->dbg_dest_tlv->base_shift;
2443 end = iwl_read_prph(trans, end) <<
2444 trans->dbg_dest_tlv->end_shift;
2445
2446 /* Make "end" point to the actual end */
cc79ef66
LK		 2447 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2448 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2449 end += (1 << trans->dbg_dest_tlv->end_shift);
2450 monitor_len = end - base;
2451 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2452 monitor_len;
2453 } else {
2454 monitor_len = 0;
2455 }
c2d20201 2456
36fb9017
OG		 2457 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2458 dump_data = vzalloc(len);
2459 if (!dump_data)
2460 return NULL;
2461
2462 data = (void *)dump_data->data;
2463 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2464 dump_data->len = len;
2465
2466 return dump_data;
2467 }
2468
2469 /* CSR registers */
2470 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2471
36fb9017
OG		 2472 /* FH registers */
2473 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2474
2475 if (dump_rbs) {
78485054
SS		 2476 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2477 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2478 /* RBs */
78485054 2479 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2480 & 0x0FFF;
78485054 2481 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2482 len += num_rbs * (sizeof(*data) +
2483 sizeof(struct iwl_fw_error_dump_rb) +
2484 (PAGE_SIZE << trans_pcie->rx_page_order));
2485 }
2486
48eb7b34
EG		 2487 dump_data = vzalloc(len);
2488 if (!dump_data)
2489 return NULL;
4d075007
JB		 2490
2491 len = 0;
48eb7b34 2492 data = (void *)dump_data->data;
4d075007
JB		 2493 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2494 txcmd = (void *)data->data;
2495 spin_lock_bh(&cmdq->lock);
2496 ptr = cmdq->q.write_ptr;
2497 for (i = 0; i < cmdq->q.n_window; i++) {
2498 u8 idx = get_cmd_index(&cmdq->q, ptr);
2499 u32 caplen, cmdlen;
2500
2501 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2502 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2503
2504 if (cmdlen) {
2505 len += sizeof(*txcmd) + caplen;
2506 txcmd->cmdlen = cpu_to_le32(cmdlen);
2507 txcmd->caplen = cpu_to_le32(caplen);
2508 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2509 txcmd = (void *)((u8 *)txcmd->data + caplen);
2510 }
2511
2512 ptr = iwl_queue_dec_wrap(ptr);
2513 }
2514 spin_unlock_bh(&cmdq->lock);
2515
2516 data->len = cpu_to_le32(len);
c2d20201 2517 len += sizeof(*data);
67c65f2c
EG		 2518 data = iwl_fw_error_next_data(data);
2519
473ad712 2520 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2521 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2522 if (dump_rbs)
2523 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2524
36fb9017 2525 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2526
48eb7b34
EG		 2527 dump_data->len = len;
2528
2529 return dump_data;
4d075007 2530}
87e5666c 2531
4cbb8e50
LC		 2532#ifdef CONFIG_PM_SLEEP
2533static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2534{
2535 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2536 return iwl_pci_fw_enter_d0i3(trans);
2537
2538 return 0;
2539}
2540
2541static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2542{
2543 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2544 iwl_pci_fw_exit_d0i3(trans);
2545}
2546#endif /* CONFIG_PM_SLEEP */
2547
d1ff5253 2548static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2549 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2550 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2551 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2552 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2553 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2554
ddaf5a5b
JB		 2555 .d3_suspend = iwl_trans_pcie_d3_suspend,
2556 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2557
4cbb8e50
LC		 2558#ifdef CONFIG_PM_SLEEP
2559 .suspend = iwl_trans_pcie_suspend,
2560 .resume = iwl_trans_pcie_resume,
2561#endif /* CONFIG_PM_SLEEP */
2562
f02831be 2563 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2564
e6bb4c9c 2565 .tx = iwl_trans_pcie_tx,
a0eaad71 2566 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2567
d0624be6 2568 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2569 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2570
990aa6d7 2571 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2572 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
0cd58eaa 2573 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
5f178cd2 2574
03905495
EG		 2575 .write8 = iwl_trans_pcie_write8,
2576 .write32 = iwl_trans_pcie_write32,
2577 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2578 .read_prph = iwl_trans_pcie_read_prph,
2579 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2580 .read_mem = iwl_trans_pcie_read_mem,
2581 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2582 .configure = iwl_trans_pcie_configure,
47107e84 2583 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2584 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2585 .release_nic_access = iwl_trans_pcie_release_nic_access,
2586 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2587
7616f334
EP		 2588 .ref = iwl_trans_pcie_ref,
2589 .unref = iwl_trans_pcie_unref,
2590
4d075007 2591 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2592};
a42a1844 2593
87ce05a2 2594struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2595 const struct pci_device_id *ent,
2596 const struct iwl_cfg *cfg)
a42a1844 2597{
a42a1844
EG		 2598 struct iwl_trans_pcie *trans_pcie;
2599 struct iwl_trans *trans;
2600 u16 pci_cmd;
96a6497b 2601 int ret, addr_size;
a42a1844 2602
7b501d10
JB		 2603 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2604 &pdev->dev, cfg, &trans_ops_pcie, 0);
2605 if (!trans)
2606 return ERR_PTR(-ENOMEM);
a42a1844 2607
206eea78
JB		 2608 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2609
a42a1844
EG		 2610 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2611
a42a1844 2612 trans_pcie->trans = trans;
7b11488f 2613 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2614 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2615 spin_lock_init(&trans_pcie->ref_lock);
fa9f3281 2616 mutex_init(&trans_pcie->mutex);
13df1aab 2617 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2618 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2619 if (!trans_pcie->tso_hdr_page) {
2620 ret = -ENOMEM;
2621 goto out_no_pci;
2622 }
a42a1844 2623
af3f2f74
EG		 2624 ret = pci_enable_device(pdev);
2625 if (ret)
d819c6cf
JB		 2626 goto out_no_pci;
2627
f2532b04
EG		 2628 if (!cfg->base_params->pcie_l1_allowed) {
2629 /*
2630 * W/A - seems to solve weird behavior. We need to remove this
2631 * if we don't want to stay in L1 all the time. This wastes a
2632 * lot of power.
2633 */
2634 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2635 PCIE_LINK_STATE_L1 |
2636 PCIE_LINK_STATE_CLKPM);
2637 }
a42a1844 2638
96a6497b
SS		 2639 if (cfg->mq_rx_supported)
2640 addr_size = 64;
2641 else
2642 addr_size = 36;
2643
a42a1844
EG		 2644 pci_set_master(pdev);
2645
96a6497b 2646 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 2647 if (!ret)
96a6497b
SS		 2648 ret = pci_set_consistent_dma_mask(pdev,
2649 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 2650 if (ret) {
2651 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2652 if (!ret)
2653 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2654 DMA_BIT_MASK(32));
a42a1844 2655 /* both attempts failed: */
af3f2f74 2656 if (ret) {
6a4b09f8 2657 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2658 goto out_pci_disable_device;
2659 }
2660 }
2661
af3f2f74
EG		 2662 ret = pci_request_regions(pdev, DRV_NAME);
2663 if (ret) {
6a4b09f8 2664 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2665 goto out_pci_disable_device;
2666 }
2667
05f5b97e 2668 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2669 if (!trans_pcie->hw_base) {
6a4b09f8 2670 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
af3f2f74 2671 ret = -ENODEV;
a42a1844
EG		 2672 goto out_pci_release_regions;
2673 }
2674
a42a1844
EG		 2675 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2676 * PCI Tx retries from interfering with C3 CPU state */
2677 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2678
83f7a85f
EG		 2679 trans->dev = &pdev->dev;
2680 trans_pcie->pci_dev = pdev;
2681 iwl_disable_interrupts(trans);
2682
af3f2f74
EG		 2683 ret = pci_enable_msi(pdev);
2684 if (ret) {
2685 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
9f904b38
EG		 2686 /* enable rfkill interrupt: hw bug w/a */
2687 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2688 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2689 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2690 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2691 }
2692 }
a42a1844 2693
08079a49 2694 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2695 /*
2696 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2697 * changed, and now the revision step also includes bit 0-1 (no more
2698 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2699 * in the old format.
2700 */
7a42baa6
EH		 2701 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2702 unsigned long flags;
7a42baa6 2703
b513ee7f 2704 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2705 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2706
f9e5554c
EG		 2707 ret = iwl_pcie_prepare_card_hw(trans);
2708 if (ret) {
2709 IWL_WARN(trans, "Exit HW not ready\n");
2710 goto out_pci_disable_msi;
2711 }
2712
7a42baa6
EH		 2713 /*
2714 * in-order to recognize C step driver should read chip version
2715 * id located at the AUX bus MISC address space.
2716 */
2717 iwl_set_bit(trans, CSR_GP_CNTRL,
2718 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2719 udelay(2);
2720
2721 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2722 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2723 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2724 25000);
2725 if (ret < 0) {
2726 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2727 goto out_pci_disable_msi;
2728 }
2729
23ba9340 2730 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 2731 u32 hw_step;
2732
14ef1b43 2733 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 2734 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 2735 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2736 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 2737 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2738 if (hw_step == 0x3)
2739 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2740 (SILICON_C_STEP << 2);
2741 iwl_trans_release_nic_access(trans, &flags);
2742 }
2743 }
2744
99673ee5 2745 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2746 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2747 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2748
69a10b29 2749 /* Initialize the wait queue for commands */
f946b529 2750 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2751
4cbb8e50
LC		 2752 init_waitqueue_head(&trans_pcie->d0i3_waitq);
2753
af3f2f74
EG		 2754 ret = iwl_pcie_alloc_ict(trans);
2755 if (ret)
7b501d10 2756 goto out_pci_disable_msi;
a8b691e6 2757
af3f2f74 2758 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2759 iwl_pcie_irq_handler,
2760 IRQF_SHARED, DRV_NAME, trans);
af3f2f74 2761 if (ret) {
a8b691e6
JB		 2762 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2763 goto out_free_ict;
2764 }
2765
83f7a85f
EG		 2766 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2767
b3ff1270
LC		 2768#ifdef CONFIG_IWLWIFI_PCIE_RTPM
2769 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2770#else
2771 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2772#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2773
a42a1844
EG		 2774 return trans;
2775
a8b691e6
JB		 2776out_free_ict:
2777 iwl_pcie_free_ict(trans);
59c647b6
EG		 2778out_pci_disable_msi:
2779 pci_disable_msi(pdev);
a42a1844
EG		 2780out_pci_release_regions:
2781 pci_release_regions(pdev);
2782out_pci_disable_device:
2783 pci_disable_device(pdev);
2784out_no_pci:
6eb5e529 2785 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 2786 iwl_trans_free(trans);
af3f2f74 2787 return ERR_PTR(ret);
a42a1844 2788}
Linux 6.x block layer and io_uring tree(s)