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iwlwifi: pcie: rename L0S_ENABLED bit to L0S_DISABLED
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 11 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
c85eb619 22 * The full GNU General Public License is included in this distribution
410dc5aa 23 * in the file called COPYING.
c85eb619
EG		 24 *
25 * Contact Information:
cb2f8277 26 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
553452e5
LK		 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
ea695b7c 34 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
EG		 35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
a42a1844 64#include <linux/pci.h>
e6bb4c9c 65#include <linux/interrupt.h>
87e5666c 66#include <linux/debugfs.h>
cf614297 67#include <linux/sched.h>
6d8f6eeb
EG		 68#include <linux/bitops.h>
69#include <linux/gfp.h>
48eb7b34 70#include <linux/vmalloc.h>
49564a80 71#include <linux/module.h>
f7805b33 72#include <linux/wait.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
d962f9b1 80#include "fw/error-dump.h"
520f03ea 81#include "fw/dbg.h"
a89c72ff 82#include "fw/api/tx.h"
6468a01a 83#include "internal.h"
06d51e0d 84#include "iwl-fh.h"
0439bb62 85
fe45773b
AN		 86/* extended range in FW SRAM */
87#define IWL_FW_MEM_EXTENDED_START 0x40000
88#define IWL_FW_MEM_EXTENDED_END 0x57FFF
89
4290eaad 90void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad 91{
c4d3f2ee
LC		 92#define PCI_DUMP_SIZE 352
93#define PCI_MEM_DUMP_SIZE 64
94#define PCI_PARENT_DUMP_SIZE 524
95#define PREFIX_LEN 32
a6d24fad
RJ		 96 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
97 struct pci_dev *pdev = trans_pcie->pci_dev;
98 u32 i, pos, alloc_size, *ptr, *buf;
99 char *prefix;
100
101 if (trans_pcie->pcie_dbg_dumped_once)
102 return;
103
104 /* Should be a multiple of 4 */
105 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
c4d3f2ee
LC		 106 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
107 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
108
a6d24fad 109 /* Alloc a max size buffer */
c4d3f2ee
LC		 110 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
111 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
112 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
113 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
114
a6d24fad
RJ		 115 buf = kmalloc(alloc_size, GFP_ATOMIC);
116 if (!buf)
117 return;
118 prefix = (char *)buf + alloc_size - PREFIX_LEN;
119
120 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
121
122 /* Print wifi device registers */
123 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
124 IWL_ERR(trans, "iwlwifi device config registers:\n");
125 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
126 if (pci_read_config_dword(pdev, i, ptr))
127 goto err_read;
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
129
130 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
c4d3f2ee 131 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 132 *ptr = iwl_read32(trans, i);
133 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
134
135 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
136 if (pos) {
137 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
138 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
139 if (pci_read_config_dword(pdev, pos + i, ptr))
140 goto err_read;
141 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
142 32, 4, buf, i, 0);
143 }
144
145 /* Print parent device registers next */
146 if (!pdev->bus->self)
147 goto out;
148
149 pdev = pdev->bus->self;
150 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
151
152 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
153 pci_name(pdev));
c4d3f2ee 154 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 155 if (pci_read_config_dword(pdev, i, ptr))
156 goto err_read;
157 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
158
159 /* Print root port AER registers */
160 pos = 0;
161 pdev = pcie_find_root_port(pdev);
162 if (pdev)
163 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
164 if (pos) {
165 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
166 pci_name(pdev));
167 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
168 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
169 if (pci_read_config_dword(pdev, pos + i, ptr))
170 goto err_read;
171 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
172 4, buf, i, 0);
173 }
f3402d6d 174 goto out;
a6d24fad
RJ		 175
176err_read:
177 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
178 IWL_ERR(trans, "Read failed at 0x%X\n", i);
179out:
180 trans_pcie->pcie_dbg_dumped_once = 1;
181 kfree(buf);
182}
183
870c2a11
GBA		 184static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
185{
186 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
286ca8eb
LC		 187 iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
188 BIT(trans->trans_cfg->csr->flag_sw_reset));
870c2a11
GBA		 189 usleep_range(5000, 6000);
190}
191
c2d20201
EG		 192static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
193{
69f0e505 194 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 195
69f0e505
SM		 196 if (!fw_mon->size)
197 return;
198
199 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
200 fw_mon->physical);
201
202 fw_mon->block = NULL;
203 fw_mon->physical = 0;
204 fw_mon->size = 0;
c2d20201
EG		 205}
206
88964b2e
SS		 207static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
208 u8 max_power, u8 min_power)
c2d20201 209{
69f0e505
SM		 210 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
211 void *block = NULL;
212 dma_addr_t physical = 0;
96c285da 213 u32 size = 0;
c2d20201
EG		 214 u8 power;
215
69f0e505
SM		 216 if (fw_mon->size)
217 return;
218
88964b2e 219 for (power = max_power; power >= min_power; power--) {
c2d20201 220 size = BIT(power);
69f0e505
SM		 221 block = dma_alloc_coherent(trans->dev, size, &physical,
222 GFP_KERNEL | __GFP_NOWARN);
223 if (!block)
c2d20201
EG		 224 continue;
225
c2d20201 226 IWL_INFO(trans,
c5f97542
SM		 227 "Allocated 0x%08x bytes for firmware monitor.\n",
228 size);
c2d20201
EG		 229 break;
230 }
231
69f0e505 232 if (WARN_ON_ONCE(!block))
c2d20201
EG		 233 return;
234
96c285da
EG		 235 if (power != max_power)
236 IWL_ERR(trans,
237 "Sorry - debug buffer is only %luK while you requested %luK\n",
238 (unsigned long)BIT(power - 10),
239 (unsigned long)BIT(max_power - 10));
240
69f0e505
SM		 241 fw_mon->block = block;
242 fw_mon->physical = physical;
243 fw_mon->size = size;
88964b2e
SS		 244}
245
246void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
247{
248 if (!max_power) {
249 /* default max_power is maximum */
250 max_power = 26;
251 } else {
252 max_power += 11;
253 }
254
255 if (WARN(max_power > 26,
256 "External buffer size for monitor is too big %d, check the FW TLV\n",
257 max_power))
258 return;
259
69f0e505 260 if (trans->dbg.fw_mon.size)
88964b2e
SS		 261 return;
262
263 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
c2d20201
EG		 264}
265
a812cba9
AB		 266static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
267{
268 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
269 ((reg & 0x0000ffff) | (2 << 28)));
270 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
271}
272
273static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
274{
275 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
276 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
277 ((reg & 0x0000ffff) | (3 << 28)));
278}
279
ddaf5a5b 280static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 281{
66337b7c 282 if (trans->cfg->apmg_not_supported)
95411d04
AA		 283 return;
284
ddaf5a5b
JB		 285 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
286 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
287 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
288 ~APMG_PS_CTRL_MSK_PWR_SRC);
289 else
290 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
291 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
292 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 293}
294
af634bee
EG		 295/* PCI registers */
296#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 297
eda50cde 298void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 299{
20d3b647 300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 301 u16 lctl;
9180ac50 302 u16 cap;
af634bee 303
af634bee
EG		 304 /*
305 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
306 * Check if BIOS (or OS) enabled L1-ASPM on this device.
307 * If so (likely), disable L0S, so device moves directly L0->L1;
308 * costs negligible amount of power savings.
309 * If not (unlikely), enable L0S, so there is at least some
310 * power savings, even without L1.
311 */
7afe3705 312 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 313 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
3d1b28fd 314 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
9180ac50 315 else
3d1b28fd 316 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
438a0f0a 317 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 318
319 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
320 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 321 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
322 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
323 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 324}
325
a6c684ee
EG		 326/*
327 * Start up NIC's basic functionality after it has been reset
7afe3705 328 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 329 * NOTE: This does not load uCode nor start the embedded processor
330 */
7afe3705 331static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 332{
52b6e168
EG		 333 int ret;
334
a6c684ee
EG		 335 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
336
337 /*
338 * Use "set_bit" below rather than "write", to preserve any hardware
339 * bits already set by default after reset.
340 */
341
342 /* Disable L0S exit timer (platform NMI Work/Around) */
286ca8eb 343 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 344 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
345 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 346
347 /*
348 * Disable L0s without affecting L1;
349 * don't wait for ICH L0s (ICH bug W/A)
350 */
351 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 352 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 353
354 /* Set FH wait threshold to maximum (HW error during stress W/A) */
355 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
356
357 /*
358 * Enable HAP INTA (interrupt from management bus) to
359 * wake device's PCI Express link L1a -> L0s
360 */
361 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 362 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 363
7afe3705 364 iwl_pcie_apm_config(trans);
a6c684ee
EG		 365
366 /* Configure analog phase-lock-loop before activating to D0A */
286ca8eb 367 if (trans->trans_cfg->base_params->pll_cfg)
77d76931 368 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 369
7d34a7d7 370 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 371 if (ret)
52b6e168 372 return ret;
a6c684ee 373
2d93aee1
EG		 374 if (trans->cfg->host_interrupt_operation_mode) {
375 /*
376 * This is a bit of an abuse - This is needed for 7260 / 3160
377 * only check host_interrupt_operation_mode even if this is
378 * not related to host_interrupt_operation_mode.
379 *
380 * Enable the oscillator to count wake up time for L1 exit. This
381 * consumes slightly more power (100uA) - but allows to be sure
382 * that we wake up from L1 on time.
383 *
384 * This looks weird: read twice the same register, discard the
385 * value, set a bit, and yet again, read that same register
386 * just to discard the value. But that's the way the hardware
387 * seems to like it.
388 */
389 iwl_read_prph(trans, OSC_CLK);
390 iwl_read_prph(trans, OSC_CLK);
391 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
392 iwl_read_prph(trans, OSC_CLK);
393 iwl_read_prph(trans, OSC_CLK);
394 }
395
a6c684ee
EG		 396 /*
397 * Enable DMA clock and wait for it to stabilize.
398 *
3073d8c0
EH		 399 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
400 * bits do not disable clocks. This preserves any hardware
401 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 402 */
95411d04 403 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 404 iwl_write_prph(trans, APMG_CLK_EN_REG,
405 APMG_CLK_VAL_DMA_CLK_RQT);
406 udelay(20);
407
408 /* Disable L1-Active */
409 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
410 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
411
412 /* Clear the interrupt in APMG if the NIC is in RFKILL */
413 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
414 APMG_RTC_INT_STT_RFKILL);
415 }
889b1696 416
eb7ff77e 417 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 418
52b6e168 419 return 0;
a6c684ee
EG		 420}
421
a812cba9
AB		 422/*
423 * Enable LP XTAL to avoid HW bug where device may consume much power if
424 * FW is not loaded after device reset. LP XTAL is disabled by default
425 * after device HW reset. Do it only if XTAL is fed by internal source.
426 * Configure device's "persistence" mode to avoid resetting XTAL again when
427 * SHRD_HW_RST occurs in S3.
428 */
429static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
430{
431 int ret;
432 u32 apmg_gp1_reg;
433 u32 apmg_xtal_cfg_reg;
434 u32 dl_cfg_reg;
435
436 /* Force XTAL ON */
437 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
438 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
439
870c2a11 440 iwl_trans_pcie_sw_reset(trans);
a812cba9 441
7d34a7d7 442 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 443 if (WARN_ON(ret)) {
a812cba9
AB		 444 /* Release XTAL ON request */
445 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
446 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
447 return;
448 }
449
450 /*
451 * Clear "disable persistence" to avoid LP XTAL resetting when
452 * SHRD_HW_RST is applied in S3.
453 */
454 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
455 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
456
457 /*
458 * Force APMG XTAL to be active to prevent its disabling by HW
459 * caused by APMG idle state.
460 */
461 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
462 SHR_APMG_XTAL_CFG_REG);
463 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
464 apmg_xtal_cfg_reg |
465 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
466
870c2a11 467 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 468
469 /* Enable LP XTAL by indirect access through CSR */
470 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
471 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
472 SHR_APMG_GP1_WF_XTAL_LP_EN |
473 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
474
475 /* Clear delay line clock power up */
476 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
477 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
478 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
479
480 /*
481 * Enable persistence mode to avoid LP XTAL resetting when
482 * SHRD_HW_RST is applied in S3.
483 */
484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
486
487 /*
488 * Clear "initialization complete" bit to move adapter from
489 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
490 */
491 iwl_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 492 BIT(trans->trans_cfg->csr->flag_init_done));
a812cba9
AB		 493
494 /* Activates XTAL resources monitor */
495 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
496 CSR_MONITOR_XTAL_RESOURCES);
497
498 /* Release XTAL ON request */
499 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
500 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
501 udelay(10);
502
503 /* Release APMG XTAL */
504 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
505 apmg_xtal_cfg_reg &
506 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
507}
508
e8c8935e 509void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 510{
e8c8935e 511 int ret;
cc56feb2
EG		 512
513 /* stop device's busmaster DMA activity */
286ca8eb
LC		 514 iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
515 BIT(trans->trans_cfg->csr->flag_stop_master));
cc56feb2 516
286ca8eb
LC		 517 ret = iwl_poll_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
518 BIT(trans->trans_cfg->csr->flag_master_dis),
519 BIT(trans->trans_cfg->csr->flag_master_dis), 100);
7f2ac8fb 520 if (ret < 0)
cc56feb2
EG		 521 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
522
523 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 524}
525
b7aaeae4 526static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 527{
528 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
529
b7aaeae4
EG		 530 if (op_mode_leave) {
531 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
532 iwl_pcie_apm_init(trans);
533
534 /* inform ME that we are leaving */
286ca8eb 535 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
b7aaeae4
EG		 536 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
537 APMG_PCIDEV_STT_VAL_WAKE_ME);
286ca8eb 538 else if (trans->trans_cfg->device_family >=
79b6c8fe 539 IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 540 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
541 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 542 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
543 CSR_HW_IF_CONFIG_REG_PREPARE |
544 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 545 mdelay(1);
546 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
547 CSR_RESET_LINK_PWR_MGMT_DISABLED);
548 }
b7aaeae4
EG		 549 mdelay(5);
550 }
551
eb7ff77e 552 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 553
554 /* Stop device's DMA activity */
7afe3705 555 iwl_pcie_apm_stop_master(trans);
cc56feb2 556
a812cba9
AB		 557 if (trans->cfg->lp_xtal_workaround) {
558 iwl_pcie_apm_lp_xtal_enable(trans);
559 return;
560 }
561
870c2a11 562 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 563
564 /*
565 * Clear "initialization complete" bit to move adapter from
566 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
567 */
568 iwl_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 569 BIT(trans->trans_cfg->csr->flag_init_done));
cc56feb2
EG		 570}
571
7afe3705 572static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 573{
7b11488f 574 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 575 int ret;
392f8b78
EG		 576
577 /* nic_init */
7b70bd63 578 spin_lock(&trans_pcie->irq_lock);
52b6e168 579 ret = iwl_pcie_apm_init(trans);
7b70bd63 580 spin_unlock(&trans_pcie->irq_lock);
392f8b78 581
52b6e168
EG		 582 if (ret)
583 return ret;
584
95411d04 585 iwl_pcie_set_pwr(trans, false);
392f8b78 586
ecdb975c 587 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 588
589 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 590 iwl_pcie_rx_init(trans);
392f8b78
EG		 591
592 /* Allocate or reset and init all Tx and Command queues */
f02831be 593 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 594 return -ENOMEM;
595
286ca8eb 596 if (trans->trans_cfg->base_params->shadow_reg_enable) {
392f8b78 597 /* enable shadow regs in HW */
20d3b647 598 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 599 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 600 }
601
392f8b78
EG		 602 return 0;
603}
604
605#define HW_READY_TIMEOUT (50)
606
607/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 608static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 609{
610 int ret;
611
1042db2a 612 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 613 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 614
615 /* See if we got it */
1042db2a 616 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 617 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
618 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
619 HW_READY_TIMEOUT);
392f8b78 620
6a08f514
EG		 621 if (ret >= 0)
622 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
623
6d8f6eeb 624 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 625 return ret;
626}
627
628/* Note: returns standard 0/-ERROR code */
eda50cde 629int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 630{
631 int ret;
289e5501 632 int t = 0;
501fd989 633 int iter;
392f8b78 634
6d8f6eeb 635 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 636
7afe3705 637 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 638 /* If the card is ready, exit 0 */
392f8b78
EG		 639 if (ret >= 0)
640 return 0;
641
c9fdec9f
EG		 642 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
643 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 644 usleep_range(1000, 2000);
c9fdec9f 645
501fd989
EG		 646 for (iter = 0; iter < 10; iter++) {
647 /* If HW is not ready, prepare the conditions to check again */
648 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
649 CSR_HW_IF_CONFIG_REG_PREPARE);
650
651 do {
652 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 653 if (ret >= 0)
654 return 0;
392f8b78 655
501fd989
EG		 656 usleep_range(200, 1000);
657 t += 200;
658 } while (t < 150000);
659 msleep(25);
660 }
392f8b78 661
7f2ac8fb 662 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 663
392f8b78
EG		 664 return ret;
665}
666
cf614297
EG		 667/*
668 * ucode
669 */
564cdce7
SS		 670static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
671 u32 dst_addr, dma_addr_t phy_addr,
672 u32 byte_cnt)
cf614297 673{
bac842da
EG		 674 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
675 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
676
677 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
678 dst_addr);
679
680 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
681 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
682
683 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
684 (iwl_get_dma_hi_addr(phy_addr)
685 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
686
687 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
688 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
689 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
690 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
691
692 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
693 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
694 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
695 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 696}
697
564cdce7
SS		 698static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
699 u32 dst_addr, dma_addr_t phy_addr,
700 u32 byte_cnt)
701{
702 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
703 unsigned long flags;
704 int ret;
705
706 trans_pcie->ucode_write_complete = false;
707
708 if (!iwl_trans_grab_nic_access(trans, &flags))
709 return -EIO;
710
eda50cde
SS		 711 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
712 byte_cnt);
bac842da 713 iwl_trans_release_nic_access(trans, &flags);
cf614297 714
13df1aab
JB		 715 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
716 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 717 if (!ret) {
83f84d7b 718 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 719 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 720 return -ETIMEDOUT;
721 }
722
723 return 0;
724}
725
7afe3705 726static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 727 const struct fw_desc *section)
cf614297 728{
83f84d7b
JB		 729 u8 *v_addr;
730 dma_addr_t p_addr;
baa21e83 731 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 732 int ret = 0;
733
83f84d7b
JB		 734 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
735 section_num);
736
c571573a
EG		 737 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
738 GFP_KERNEL | __GFP_NOWARN);
739 if (!v_addr) {
740 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
741 chunk_sz = PAGE_SIZE;
742 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
743 &p_addr, GFP_KERNEL);
744 if (!v_addr)
745 return -ENOMEM;
746 }
83f84d7b 747
c571573a 748 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 749 u32 copy_size, dst_addr;
750 bool extended_addr = false;
83f84d7b 751
c571573a 752 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 753 dst_addr = section->offset + offset;
754
755 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
756 dst_addr <= IWL_FW_MEM_EXTENDED_END)
757 extended_addr = true;
758
759 if (extended_addr)
760 iwl_set_bits_prph(trans, LMPM_CHICK,
761 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 762
83f84d7b 763 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 764 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
765 copy_size);
766
767 if (extended_addr)
768 iwl_clear_bits_prph(trans, LMPM_CHICK,
769 LMPM_CHICK_EXTENDED_ADDR_SPACE);
770
83f84d7b
JB		 771 if (ret) {
772 IWL_ERR(trans,
773 "Could not load the [%d] uCode section\n",
774 section_num);
775 break;
6dfa8d01 776 }
83f84d7b
JB		 777 }
778
c571573a 779 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 780 return ret;
781}
782
5dd9c68a
EG		 783static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
784 const struct fw_img *image,
785 int cpu,
786 int *first_ucode_section)
e2d6f4e7
EH		 787{
788 int shift_param;
dcab8ecd
EH		 789 int i, ret = 0, sec_num = 0x1;
790 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 791
792 if (cpu == 1) {
793 shift_param = 0;
034846cf 794 *first_ucode_section = 0;
e2d6f4e7
EH		 795 } else {
796 shift_param = 16;
034846cf 797 (*first_ucode_section)++;
e2d6f4e7
EH		 798 }
799
eef187a7 800 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 801 last_read_idx = i;
802
a6c4fb44
MG		 803 /*
804 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
805 * CPU1 to CPU2.
806 * PAGING_SEPARATOR_SECTION delimiter - separate between
807 * CPU2 non paged to CPU2 paging sec.
808 */
034846cf 809 if (!image->sec[i].data ||
a6c4fb44
MG		 810 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
811 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 812 IWL_DEBUG_FW(trans,
813 "Break since Data not valid or Empty section, sec = %d\n",
814 i);
189fa2fa 815 break;
034846cf
EH		 816 }
817
189fa2fa
EH		 818 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
819 if (ret)
820 return ret;
dcab8ecd 821
d6a2c5c7 822 /* Notify ucode of loaded section number and status */
eda50cde
SS		 823 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
824 val = val | (sec_num << shift_param);
825 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
826
dcab8ecd 827 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 828 }
829
034846cf
EH		 830 *first_ucode_section = last_read_idx;
831
2aabdbdc
EG		 832 iwl_enable_interrupts(trans);
833
286ca8eb 834 if (trans->trans_cfg->use_tfh) {
d6a2c5c7
SS		 835 if (cpu == 1)
836 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
837 0xFFFF);
838 else
839 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
840 0xFFFFFFFF);
841 } else {
842 if (cpu == 1)
843 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
844 0xFFFF);
845 else
846 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
847 0xFFFFFFFF);
848 }
afb88917 849
189fa2fa
EH		 850 return 0;
851}
e2d6f4e7 852
189fa2fa
EH		 853static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
854 const struct fw_img *image,
034846cf
EH		 855 int cpu,
856 int *first_ucode_section)
189fa2fa 857{
189fa2fa 858 int i, ret = 0;
034846cf 859 u32 last_read_idx = 0;
189fa2fa 860
3ce4a038 861 if (cpu == 1)
034846cf 862 *first_ucode_section = 0;
3ce4a038 863 else
034846cf 864 (*first_ucode_section)++;
189fa2fa 865
eef187a7 866 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 867 last_read_idx = i;
868
a6c4fb44
MG		 869 /*
870 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
871 * CPU1 to CPU2.
872 * PAGING_SEPARATOR_SECTION delimiter - separate between
873 * CPU2 non paged to CPU2 paging sec.
874 */
034846cf 875 if (!image->sec[i].data ||
a6c4fb44
MG		 876 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
877 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 878 IWL_DEBUG_FW(trans,
879 "Break since Data not valid or Empty section, sec = %d\n",
880 i);
189fa2fa 881 break;
034846cf
EH		 882 }
883
189fa2fa
EH		 884 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
885 if (ret)
886 return ret;
e2d6f4e7
EH		 887 }
888
034846cf
EH		 889 *first_ucode_section = last_read_idx;
890
e2d6f4e7
EH		 891 return 0;
892}
893
593fae3e
SM		 894static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
895{
896 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
897 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
898 &trans->dbg.fw_mon_cfg[alloc_id];
899 struct iwl_dram_data *frag;
900
901 if (!iwl_trans_dbg_ini_valid(trans))
902 return;
903
904 if (le32_to_cpu(fw_mon_cfg->buf_location) ==
905 IWL_FW_INI_LOCATION_SRAM_PATH) {
906 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
907 /* set sram monitor by enabling bit 7 */
908 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
909 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
910
911 return;
912 }
913
914 if (le32_to_cpu(fw_mon_cfg->buf_location) !=
915 IWL_FW_INI_LOCATION_DRAM_PATH ||
916 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
917 return;
918
919 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
920
921 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
922 alloc_id);
923
924 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
925 frag->physical >> MON_BUFF_SHIFT_VER2);
926 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
927 (frag->physical + frag->size - 256) >>
928 MON_BUFF_SHIFT_VER2);
929}
930
c9be849d 931void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 932{
91c28b83 933 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
69f0e505 934 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
09e350f7
LK		 935 int i;
936
a1af4c48 937 if (iwl_trans_dbg_ini_valid(trans)) {
593fae3e 938 iwl_pcie_apply_destination_ini(trans);
7a14c23d
SS		 939 return;
940 }
941
09e350f7
LK		 942 IWL_INFO(trans, "Applying debug destination %s\n",
943 get_fw_dbg_mode_string(dest->monitor_mode));
944
945 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 946 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 947 else
948 IWL_WARN(trans, "PCI should have external buffer debug\n");
949
91c28b83 950 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
09e350f7
LK		 951 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
952 u32 val = le32_to_cpu(dest->reg_ops[i].val);
953
954 switch (dest->reg_ops[i].op) {
955 case CSR_ASSIGN:
956 iwl_write32(trans, addr, val);
957 break;
958 case CSR_SETBIT:
959 iwl_set_bit(trans, addr, BIT(val));
960 break;
961 case CSR_CLEARBIT:
962 iwl_clear_bit(trans, addr, BIT(val));
963 break;
964 case PRPH_ASSIGN:
965 iwl_write_prph(trans, addr, val);
966 break;
967 case PRPH_SETBIT:
968 iwl_set_bits_prph(trans, addr, BIT(val));
969 break;
970 case PRPH_CLEARBIT:
971 iwl_clear_bits_prph(trans, addr, BIT(val));
972 break;
869f3b15
HD		 973 case PRPH_BLOCKBIT:
974 if (iwl_read_prph(trans, addr) & BIT(val)) {
975 IWL_ERR(trans,
976 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
977 val, addr);
978 goto monitor;
979 }
980 break;
09e350f7
LK		 981 default:
982 IWL_ERR(trans, "FW debug - unknown OP %d\n",
983 dest->reg_ops[i].op);
984 break;
985 }
986 }
987
869f3b15 988monitor:
69f0e505 989 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
09e350f7 990 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
69f0e505 991 fw_mon->physical >> dest->base_shift);
286ca8eb 992 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 993 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 994 (fw_mon->physical + fw_mon->size -
995 256) >> dest->end_shift);
62d7476d
EG		 996 else
997 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 998 (fw_mon->physical + fw_mon->size) >>
999 dest->end_shift);
09e350f7
LK		 1000 }
1001}
1002
7afe3705 1003static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 1004 const struct fw_img *image)
cf614297 1005{
189fa2fa 1006 int ret = 0;
034846cf 1007 int first_ucode_section;
cf614297 1008
dcab8ecd 1009 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 1010 image->is_dual_cpus ? "Dual" : "Single");
1011
dcab8ecd
EH		 1012 /* load to FW the binary non secured sections of CPU1 */
1013 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1014 if (ret)
1015 return ret;
e2d6f4e7
EH		 1016
1017 if (image->is_dual_cpus) {
189fa2fa
EH		 1018 /* set CPU2 header address */
1019 iwl_write_prph(trans,
1020 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1021 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1022
189fa2fa 1023 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1024 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1025 &first_ucode_section);
189fa2fa
EH		 1026 if (ret)
1027 return ret;
e2d6f4e7 1028 }
cf614297 1029
c2d20201
EG		 1030 /* supported for 7000 only for the moment */
1031 if (iwlwifi_mod_params.fw_monitor &&
286ca8eb 1032 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
69f0e505 1033 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 1034
69f0e505
SM		 1035 iwl_pcie_alloc_fw_monitor(trans, 0);
1036 if (fw_mon->size) {
c2d20201 1037 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
69f0e505 1038 fw_mon->physical >> 4);
c2d20201 1039 iwl_write_prph(trans, MON_BUFF_END_ADDR,
69f0e505 1040 (fw_mon->physical + fw_mon->size) >> 4);
c2d20201 1041 }
7a14c23d 1042 } else if (iwl_pcie_dbg_on(trans)) {
09e350f7 1043 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1044 }
1045
2aabdbdc
EG		 1046 iwl_enable_interrupts(trans);
1047
e12ba844 1048 /* release CPU reset */
5dd9c68a 1049 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1050
dcab8ecd
EH		 1051 return 0;
1052}
189fa2fa 1053
5dd9c68a
EG		 1054static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1055 const struct fw_img *image)
dcab8ecd
EH		 1056{
1057 int ret = 0;
1058 int first_ucode_section;
dcab8ecd
EH		 1059
1060 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1061 image->is_dual_cpus ? "Dual" : "Single");
1062
7a14c23d 1063 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 1064 iwl_pcie_apply_destination(trans);
1065
82ea7966
SS		 1066 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1067 iwl_read_prph(trans, WFPM_GP2));
1068
1069 /*
1070 * Set default value. On resume reading the values that were
1071 * zeored can provide debug data on the resume flow.
1072 * This is for debugging only and has no functional impact.
1073 */
1074 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1075
dcab8ecd
EH		 1076 /* configure the ucode to be ready to get the secured image */
1077 /* release CPU reset */
1078 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1079
1080 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1081 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1082 &first_ucode_section);
dcab8ecd
EH		 1083 if (ret)
1084 return ret;
1085
1086 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1087 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1088 &first_ucode_section);
cf614297
EG		 1089}
1090
9ad8fd0b 1091bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1092{
326477e4 1093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1094 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1095 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1096 bool report;
727c02df 1097
326477e4
JB		 1098 if (hw_rfkill) {
1099 set_bit(STATUS_RFKILL_HW, &trans->status);
1100 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1101 } else {
1102 clear_bit(STATUS_RFKILL_HW, &trans->status);
1103 if (trans_pcie->opmode_down)
1104 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1105 }
1106
1107 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1108
326477e4
JB		 1109 if (prev != report)
1110 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1111
1112 return hw_rfkill;
1113}
1114
7ca00409
HD		 1115struct iwl_causes_list {
1116 u32 cause_num;
1117 u32 mask_reg;
1118 u8 addr;
1119};
1120
1121static struct iwl_causes_list causes_list[] = {
1122 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1123 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1124 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1125 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1126 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1127 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
ff911dca 1128 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12},
7ca00409
HD		 1129 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1130 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1131 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1132 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1133 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1134 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1135 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1136 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1137};
1138
1139static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1140{
1141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1142 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
3681021f
JB		 1143 int i, arr_size = ARRAY_SIZE(causes_list);
1144 struct iwl_causes_list *causes = causes_list;
7ca00409
HD		 1145
1146 /*
1147 * Access all non RX causes and map them to the default irq.
1148 * In case we are missing at least one interrupt vector,
1149 * the first interrupt vector will serve non-RX and FBQ causes.
1150 */
9b58419e 1151 for (i = 0; i < arr_size; i++) {
9b58419e
GBA		 1152 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1153 iwl_clear_bit(trans, causes[i].mask_reg,
1154 causes[i].cause_num);
7ca00409
HD		 1155 }
1156}
1157
1158static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1159{
1160 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1161 u32 offset =
1162 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1163 u32 val, idx;
1164
1165 /*
1166 * The first RX queue - fallback queue, which is designated for
1167 * management frame, command responses etc, is always mapped to the
1168 * first interrupt vector. The other RX queues are mapped to
1169 * the other (N - 2) interrupt vectors.
1170 */
1171 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1172 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1173 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1174 MSIX_FH_INT_CAUSES_Q(idx - offset));
1175 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1176 }
1177 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1178
1179 val = MSIX_FH_INT_CAUSES_Q(0);
1180 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1181 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1182 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1183
1184 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1185 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1186}
1187
77c09bc8 1188void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1189{
1190 struct iwl_trans *trans = trans_pcie->trans;
1191
1192 if (!trans_pcie->msix_enabled) {
286ca8eb 1193 if (trans->trans_cfg->mq_rx_supported &&
d7270d61 1194 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1195 iwl_write_umac_prph(trans, UREG_CHICK,
1196 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1197 return;
1198 }
d7270d61
HD		 1199 /*
1200 * The IVAR table needs to be configured again after reset,
1201 * but if the device is disabled, we can't write to
1202 * prph.
1203 */
1204 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1205 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1206
1207 /*
1208 * Each cause from the causes list above and the RX causes is
1209 * represented as a byte in the IVAR table. The first nibble
1210 * represents the bound interrupt vector of the cause, the second
1211 * represents no auto clear for this cause. This will be set if its
1212 * interrupt vector is bound to serve other causes.
1213 */
1214 iwl_pcie_map_rx_causes(trans);
1215
1216 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1217}
1218
1219static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1220{
1221 struct iwl_trans *trans = trans_pcie->trans;
1222
1223 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1224
83730058
HD		 1225 if (!trans_pcie->msix_enabled)
1226 return;
1227
1228 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1229 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1230 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1231 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1232}
1233
bab3cb92 1234static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1235{
43e58856 1236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1237
fa9f3281
EG		 1238 lockdep_assert_held(&trans_pcie->mutex);
1239
1240 if (trans_pcie->is_down)
1241 return;
1242
1243 trans_pcie->is_down = true;
1244
43e58856 1245 /* tell the device to stop sending interrupts */
ae2c30bf 1246 iwl_disable_interrupts(trans);
ae2c30bf 1247
ab6cf8e8 1248 /* device going down, Stop using ICT table */
990aa6d7 1249 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1250
1251 /*
1252 * If a HW restart happens during firmware loading,
1253 * then the firmware loading might call this function
1254 * and later it might be called again due to the
1255 * restart. So don't process again if the device is
1256 * already dead.
1257 */
31b8b343 1258 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1259 IWL_DEBUG_INFO(trans,
1260 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1261 iwl_pcie_tx_stop(trans);
9805c446 1262 iwl_pcie_rx_stop(trans);
6379103e 1263
ab6cf8e8 1264 /* Power-down device's busmaster DMA clocks */
95411d04 1265 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1266 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1267 APMG_CLK_VAL_DMA_CLK_RQT);
1268 udelay(5);
1269 }
ab6cf8e8
EG		 1270 }
1271
1272 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1273 iwl_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 1274 BIT(trans->trans_cfg->csr->flag_mac_access_req));
ab6cf8e8
EG		 1275
1276 /* Stop the device, and put it in low power state */
b7aaeae4 1277 iwl_pcie_apm_stop(trans, false);
43e58856 1278
870c2a11 1279 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1280
f4a1f04a
GBA		 1281 /*
1282 * Upon stop, the IVAR table gets erased, so msi-x won't
1283 * work. This causes a bug in RF-KILL flows, since the interrupt
1284 * that enables radio won't fire on the correct irq, and the
1285 * driver won't be able to handle the interrupt.
1286 * Configure the IVAR table again after reset.
1287 */
1288 iwl_pcie_conf_msix_hw(trans_pcie);
1289
03d6c3b0
EG		 1290 /*
1291 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1292 * This is a bug in certain verions of the hardware.
1293 * Certain devices also keep sending HW RF kill interrupt all
1294 * the time, unless the interrupt is ACKed even if the interrupt
1295 * should be masked. Re-ACK all the interrupts here.
43e58856 1296 */
43e58856 1297 iwl_disable_interrupts(trans);
43e58856 1298
74fda971 1299 /* clear all status bits */
eb7ff77e
AN		 1300 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1301 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1302 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1303
1304 /*
1305 * Even if we stop the HW, we still want the RF kill
1306 * interrupt
1307 */
1308 iwl_enable_rfkill_int(trans);
1309
a6bd005f 1310 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1311 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1312}
1313
eda50cde 1314void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1315{
1316 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1317
1318 if (trans_pcie->msix_enabled) {
1319 int i;
1320
496d83ca 1321 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1322 synchronize_irq(trans_pcie->msix_entries[i].vector);
1323 } else {
1324 synchronize_irq(trans_pcie->pci_dev->irq);
1325 }
1326}
1327
a6bd005f
EG		 1328static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1329 const struct fw_img *fw, bool run_in_rfkill)
1330{
1331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1332 bool hw_rfkill;
1333 int ret;
1334
1335 /* This may fail if AMT took ownership of the device */
1336 if (iwl_pcie_prepare_card_hw(trans)) {
1337 IWL_WARN(trans, "Exit HW not ready\n");
1338 ret = -EIO;
1339 goto out;
1340 }
1341
1342 iwl_enable_rfkill_int(trans);
1343
1344 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1345
1346 /*
1347 * We enabled the RF-Kill interrupt and the handler may very
1348 * well be running. Disable the interrupts to make sure no other
1349 * interrupt can be fired.
1350 */
1351 iwl_disable_interrupts(trans);
1352
1353 /* Make sure it finished running */
2e5d4a8f 1354 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1355
1356 mutex_lock(&trans_pcie->mutex);
1357
1358 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1359 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1360 if (hw_rfkill && !run_in_rfkill) {
1361 ret = -ERFKILL;
1362 goto out;
1363 }
1364
1365 /* Someone called stop_device, don't try to start_fw */
1366 if (trans_pcie->is_down) {
1367 IWL_WARN(trans,
1368 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1369 ret = -EIO;
a6bd005f
EG		 1370 goto out;
1371 }
1372
1373 /* make sure rfkill handshake bits are cleared */
1374 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1375 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1376 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1377
1378 /* clear (again), then enable host interrupts */
1379 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1380
1381 ret = iwl_pcie_nic_init(trans);
1382 if (ret) {
1383 IWL_ERR(trans, "Unable to init nic\n");
1384 goto out;
1385 }
1386
1387 /*
1388 * Now, we load the firmware and don't want to be interrupted, even
1389 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1390 * FH_TX interrupt which is needed to load the firmware). If the
1391 * RF-Kill switch is toggled, we will find out after having loaded
1392 * the firmware and return the proper value to the caller.
1393 */
1394 iwl_enable_fw_load_int(trans);
1395
1396 /* really make sure rfkill handshake bits are cleared */
1397 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1398 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1399
1400 /* Load the given image to the HW */
286ca8eb 1401 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1402 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1403 else
1404 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1405
1406 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1407 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1408 if (hw_rfkill && !run_in_rfkill)
1409 ret = -ERFKILL;
1410
1411out:
1412 mutex_unlock(&trans_pcie->mutex);
1413 return ret;
1414}
1415
1416static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1417{
1418 iwl_pcie_reset_ict(trans);
1419 iwl_pcie_tx_start(trans, scd_addr);
1420}
1421
326477e4
JB		 1422void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1423 bool was_in_rfkill)
1424{
1425 bool hw_rfkill;
1426
1427 /*
1428 * Check again since the RF kill state may have changed while
1429 * all the interrupts were disabled, in this case we couldn't
1430 * receive the RF kill interrupt and update the state in the
1431 * op_mode.
1432 * Don't call the op_mode if the rkfill state hasn't changed.
1433 * This allows the op_mode to call stop_device from the rfkill
1434 * notification without endless recursion. Under very rare
1435 * circumstances, we might have a small recursion if the rfkill
1436 * state changed exactly now while we were called from stop_device.
1437 * This is very unlikely but can happen and is supported.
1438 */
1439 hw_rfkill = iwl_is_rfkill_set(trans);
1440 if (hw_rfkill) {
1441 set_bit(STATUS_RFKILL_HW, &trans->status);
1442 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1443 } else {
1444 clear_bit(STATUS_RFKILL_HW, &trans->status);
1445 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1446 }
1447 if (hw_rfkill != was_in_rfkill)
1448 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1449}
1450
bab3cb92 1451static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
fa9f3281
EG		 1452{
1453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1454 bool was_in_rfkill;
fa9f3281
EG		 1455
1456 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1457 trans_pcie->opmode_down = true;
1458 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
bab3cb92 1459 _iwl_trans_pcie_stop_device(trans);
326477e4 1460 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1461 mutex_unlock(&trans_pcie->mutex);
1462}
1463
14cfca71
JB		 1464void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1465{
fa9f3281
EG		 1466 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1467 IWL_TRANS_GET_PCIE_TRANS(trans);
1468
1469 lockdep_assert_held(&trans_pcie->mutex);
1470
326477e4
JB		 1471 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1472 state ? "disabled" : "enabled");
77c09bc8 1473 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
286ca8eb 1474 if (trans->trans_cfg->gen2)
bab3cb92 1475 _iwl_trans_pcie_gen2_stop_device(trans);
77c09bc8 1476 else
bab3cb92 1477 _iwl_trans_pcie_stop_device(trans);
77c09bc8 1478 }
ab6cf8e8
EG		 1479}
1480
e5f3f215
HD		 1481void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1482 bool test, bool reset)
2dd4f9f7 1483{
2dd4f9f7 1484 iwl_disable_interrupts(trans);
debff618
JB		 1485
1486 /*
1487 * in testing mode, the host stays awake and the
1488 * hardware won't be reset (not even partially)
1489 */
1490 if (test)
1491 return;
1492
ddaf5a5b
JB		 1493 iwl_pcie_disable_ict(trans);
1494
2e5d4a8f 1495 iwl_pcie_synchronize_irqs(trans);
33b56af1 1496
2dd4f9f7 1497 iwl_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 1498 BIT(trans->trans_cfg->csr->flag_mac_access_req));
ddaf5a5b 1499 iwl_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 1500 BIT(trans->trans_cfg->csr->flag_init_done));
ddaf5a5b 1501
23ae6128 1502 if (reset) {
6dfb36c8
EP		 1503 /*
1504 * reset TX queues -- some of their registers reset during S3
1505 * so if we don't reset everything here the D3 image would try
1506 * to execute some invalid memory upon resume
1507 */
1508 iwl_trans_pcie_tx_reset(trans);
1509 }
ddaf5a5b
JB		 1510
1511 iwl_pcie_set_pwr(trans, true);
1512}
1513
e5f3f215
HD		 1514static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1515 bool reset)
1516{
1517 int ret;
1518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1519
1520 /*
1521 * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW.
1522 */
1523 if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
1524 /* Enable persistence mode to avoid reset */
1525 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1526 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1527 }
1528
1529 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1530 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1531 UREG_DOORBELL_TO_ISR6_SUSPEND);
1532
1533 ret = wait_event_timeout(trans_pcie->sx_waitq,
1534 trans_pcie->sx_complete, 2 * HZ);
1535 /*
1536 * Invalidate it toward resume.
1537 */
1538 trans_pcie->sx_complete = false;
1539
1540 if (!ret) {
1541 IWL_ERR(trans, "Timeout entering D3\n");
1542 return -ETIMEDOUT;
1543 }
1544 }
1545 iwl_pcie_d3_complete_suspend(trans, test, reset);
1546
1547 return 0;
1548}
1549
ddaf5a5b 1550static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1551 enum iwl_d3_status *status,
23ae6128 1552 bool test, bool reset)
ddaf5a5b 1553{
d7270d61 1554 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1555 u32 val;
1556 int ret;
1557
debff618
JB		 1558 if (test) {
1559 iwl_enable_interrupts(trans);
1560 *status = IWL_D3_STATUS_ALIVE;
e5f3f215 1561 goto out;
debff618
JB		 1562 }
1563
a8cbb46f 1564 iwl_set_bit(trans, CSR_GP_CNTRL,
286ca8eb 1565 BIT(trans->trans_cfg->csr->flag_mac_access_req));
ddaf5a5b 1566
7d34a7d7 1567 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 1568 if (ret)
ddaf5a5b 1569 return ret;
ddaf5a5b 1570
f98ad635
EG		 1571 /*
1572 * Reconfigure IVAR table in case of MSIX or reset ict table in
1573 * MSI mode since HW reset erased it.
1574 * Also enables interrupts - none will happen as
1575 * the device doesn't know we're waking it up, only when
1576 * the opmode actually tells it after this call.
1577 */
1578 iwl_pcie_conf_msix_hw(trans_pcie);
1579 if (!trans_pcie->msix_enabled)
1580 iwl_pcie_reset_ict(trans);
1581 iwl_enable_interrupts(trans);
1582
a3ead656
EG		 1583 iwl_pcie_set_pwr(trans, false);
1584
23ae6128 1585 if (!reset) {
6dfb36c8 1586 iwl_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 1587 BIT(trans->trans_cfg->csr->flag_mac_access_req));
6dfb36c8
EP		 1588 } else {
1589 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1590
6dfb36c8
EP		 1591 ret = iwl_pcie_rx_init(trans);
1592 if (ret) {
1593 IWL_ERR(trans,
1594 "Failed to resume the device (RX reset)\n");
1595 return ret;
1596 }
ddaf5a5b
JB		 1597 }
1598
82ea7966 1599 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1600 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1601
a3ead656
EG		 1602 val = iwl_read32(trans, CSR_RESET);
1603 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1604 *status = IWL_D3_STATUS_RESET;
1605 else
1606 *status = IWL_D3_STATUS_ALIVE;
1607
e5f3f215
HD		 1608out:
1609 if (*status == IWL_D3_STATUS_ALIVE &&
1610 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1611 trans_pcie->sx_complete = false;
1612 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1613 UREG_DOORBELL_TO_ISR6_RESUME);
1614
1615 ret = wait_event_timeout(trans_pcie->sx_waitq,
1616 trans_pcie->sx_complete, 2 * HZ);
1617 /*
1618 * Invalidate it toward next suspend.
1619 */
1620 trans_pcie->sx_complete = false;
1621
1622 if (!ret) {
1623 IWL_ERR(trans, "Timeout exiting D3\n");
1624 return -ETIMEDOUT;
1625 }
1626 }
ddaf5a5b 1627 return 0;
2dd4f9f7
JB		 1628}
1629
0c18714a
LC		 1630static void
1631iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1632 struct iwl_trans *trans,
1633 const struct iwl_cfg_trans_params *cfg_trans)
2e5d4a8f
HD		 1634{
1635 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1636 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1637 u16 pci_cmd;
2e5d4a8f 1638
0c18714a 1639 if (!cfg_trans->mq_rx_supported)
06f4b081
SS		 1640 goto enable_msi;
1641
ab1068d6 1642 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1643 for (i = 0; i < max_irqs; i++)
1644 trans_pcie->msix_entries[i].entry = i;
496d83ca 1645
06f4b081
SS		 1646 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1647 MSIX_MIN_INTERRUPT_VECTORS,
1648 max_irqs);
1649 if (num_irqs < 0) {
2e5d4a8f 1650 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1651 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1652 num_irqs);
1653 goto enable_msi;
1654 }
1655 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1656
06f4b081
SS		 1657 IWL_DEBUG_INFO(trans,
1658 "MSI-X enabled. %d interrupt vectors were allocated\n",
1659 num_irqs);
1660
1661 /*
1662 * In case the OS provides fewer interrupts than requested, different
1663 * causes will share the same interrupt vector as follows:
1664 * One interrupt less: non rx causes shared with FBQ.
1665 * Two interrupts less: non rx causes shared with FBQ and RSS.
1666 * More than two interrupts: we will use fewer RSS queues.
1667 */
ab1068d6 1668 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1669 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1670 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1671 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1672 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1673 trans_pcie->trans->num_rx_queues = num_irqs;
1674 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1675 } else {
1676 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1677 }
ab1068d6 1678 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1679
06f4b081
SS		 1680 trans_pcie->alloc_vecs = num_irqs;
1681 trans_pcie->msix_enabled = true;
1682 return;
1683
1684enable_msi:
1685 ret = pci_enable_msi(pdev);
1686 if (ret) {
1687 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1688 /* enable rfkill interrupt: hw bug w/a */
1689 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1690 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1691 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1692 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1693 }
1694 }
1695}
1696
7c8d91eb
HD		 1697static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1698{
1699 int iter_rx_q, i, ret, cpu, offset;
1700 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1701
1702 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1703 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1704 offset = 1 + i;
1705 for (; i < iter_rx_q ; i++) {
1706 /*
1707 * Get the cpu prior to the place to search
1708 * (i.e. return will be > i - 1).
1709 */
1710 cpu = cpumask_next(i - offset, cpu_online_mask);
1711 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1712 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1713 &trans_pcie->affinity_mask[i]);
1714 if (ret)
1715 IWL_ERR(trans_pcie->trans,
1716 "Failed to set affinity mask for IRQ %d\n",
1717 i);
1718 }
1719}
1720
2e5d4a8f
HD		 1721static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1722 struct iwl_trans_pcie *trans_pcie)
1723{
496d83ca 1724 int i;
2e5d4a8f 1725
496d83ca 1726 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1727 int ret;
5a41a86c 1728 struct msix_entry *msix_entry;
64fa3aff
SD		 1729 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1730
1731 if (!qname)
1732 return -ENOMEM;
5a41a86c
SD		 1733
1734 msix_entry = &trans_pcie->msix_entries[i];
1735 ret = devm_request_threaded_irq(&pdev->dev,
1736 msix_entry->vector,
1737 iwl_pcie_msix_isr,
1738 (i == trans_pcie->def_irq) ?
1739 iwl_pcie_irq_msix_handler :
1740 iwl_pcie_irq_rx_msix_handler,
1741 IRQF_SHARED,
64fa3aff 1742 qname,
5a41a86c 1743 msix_entry);
2e5d4a8f 1744 if (ret) {
2e5d4a8f
HD		 1745 IWL_ERR(trans_pcie->trans,
1746 "Error allocating IRQ %d\n", i);
5a41a86c 1747
2e5d4a8f
HD		 1748 return ret;
1749 }
1750 }
7c8d91eb 1751 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1752
1753 return 0;
1754}
1755
44f61b5c 1756static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
e6bb4c9c 1757{
44f61b5c 1758 u32 hpm, wprot;
fa9f3281 1759
286ca8eb 1760 switch (trans->trans_cfg->device_family) {
44f61b5c
SM		 1761 case IWL_DEVICE_FAMILY_9000:
1762 wprot = PREG_PRPH_WPROT_9000;
1763 break;
1764 case IWL_DEVICE_FAMILY_22000:
1765 wprot = PREG_PRPH_WPROT_22000;
1766 break;
1767 default:
1768 return 0;
ebb7678d 1769 }
a6c684ee 1770
ea695b7c 1771 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
8954e1eb 1772 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
44f61b5c 1773 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
ea695b7c 1774
44f61b5c 1775 if (wprot_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1776 IWL_ERR(trans,
1777 "Error, can not clear persistence bit\n");
1778 return -EPERM;
1779 }
ea695b7c
ST		 1780 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1781 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1782 }
1783
44f61b5c
SM		 1784 return 0;
1785}
1786
0df36b90
LC		 1787static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1788{
1789 int ret;
1790
1791 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1792 if (ret < 0)
1793 return ret;
1794
1795 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1796 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1797 udelay(20);
1798 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1799 HPM_HIPM_GEN_CFG_CR_PG_EN |
1800 HPM_HIPM_GEN_CFG_CR_SLP_EN);
1801 udelay(20);
1802 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1803 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1804
1805 iwl_trans_pcie_sw_reset(trans);
1806
1807 return 0;
1808}
1809
bab3cb92 1810static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
44f61b5c
SM		 1811{
1812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813 int err;
1814
1815 lockdep_assert_held(&trans_pcie->mutex);
1816
1817 err = iwl_pcie_prepare_card_hw(trans);
1818 if (err) {
1819 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1820 return err;
1821 }
1822
1823 err = iwl_trans_pcie_clear_persistence_bit(trans);
1824 if (err)
1825 return err;
1826
870c2a11 1827 iwl_trans_pcie_sw_reset(trans);
2997494f 1828
0df36b90
LC		 1829 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1830 trans->cfg->integrated) {
1831 err = iwl_pcie_gen2_force_power_gating(trans);
1832 if (err)
1833 return err;
1834 }
1835
52b6e168
EG		 1836 err = iwl_pcie_apm_init(trans);
1837 if (err)
1838 return err;
a6c684ee 1839
2e5d4a8f 1840 iwl_pcie_init_msix(trans_pcie);
83730058 1841
226c02ca
EG		 1842 /* From now on, the op_mode will be kept updated about RF kill state */
1843 iwl_enable_rfkill_int(trans);
1844
326477e4
JB		 1845 trans_pcie->opmode_down = false;
1846
fa9f3281
EG		 1847 /* Set is_down to false here so that...*/
1848 trans_pcie->is_down = false;
1849
727c02df 1850 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1851 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1852
a8b691e6 1853 return 0;
e6bb4c9c
EG		 1854}
1855
bab3cb92 1856static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
fa9f3281
EG		 1857{
1858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1859 int ret;
1860
1861 mutex_lock(&trans_pcie->mutex);
bab3cb92 1862 ret = _iwl_trans_pcie_start_hw(trans);
fa9f3281
EG		 1863 mutex_unlock(&trans_pcie->mutex);
1864
1865 return ret;
1866}
1867
a4082843 1868static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1869{
20d3b647 1870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1871
fa9f3281
EG		 1872 mutex_lock(&trans_pcie->mutex);
1873
a4082843 1874 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1875 iwl_disable_interrupts(trans);
ee7d737c 1876
b7aaeae4 1877 iwl_pcie_apm_stop(trans, true);
cc56feb2 1878
218733cf 1879 iwl_disable_interrupts(trans);
1df06bdc 1880
8d96bb61 1881 iwl_pcie_disable_ict(trans);
33b56af1 1882
fa9f3281 1883 mutex_unlock(&trans_pcie->mutex);
33b56af1 1884
2e5d4a8f 1885 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1886}
1887
03905495
EG		 1888static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1889{
05f5b97e 1890 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1891}
1892
1893static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1894{
05f5b97e 1895 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1896}
1897
1898static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1899{
05f5b97e 1900 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1901}
1902
84fb372c
SS		 1903static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1904{
3681021f 1905 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
84fb372c
SS		 1906 return 0x00FFFFFF;
1907 else
1908 return 0x000FFFFF;
1909}
1910
6a06b6c1
EG		 1911static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1912{
84fb372c
SS		 1913 u32 mask = iwl_trans_pcie_prph_msk(trans);
1914
f9477c17 1915 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1916 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1917 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1918}
1919
1920static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1921 u32 val)
1922{
84fb372c
SS		 1923 u32 mask = iwl_trans_pcie_prph_msk(trans);
1924
6a06b6c1 1925 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1926 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1927 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1928}
1929
c6f600fc 1930static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1931 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1932{
1933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1934
1935 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1936 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1937 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1938 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1939 trans_pcie->n_no_reclaim_cmds = 0;
1940 else
1941 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1942 if (trans_pcie->n_no_reclaim_cmds)
1943 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1944 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1945
6c4fbcbc
EG		 1946 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1947 trans_pcie->rx_page_order =
1948 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1949
046db346 1950 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1951 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1952 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1953
21cb3222
JB		 1954 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1955 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1956
39bdb17e
SD		 1957 trans->command_groups = trans_cfg->command_groups;
1958 trans->command_groups_size = trans_cfg->command_groups_size;
1959
f14d6b39
JB		 1960 /* Initialize NAPI here - it should be before registering to mac80211
1961 * in the opmode but after the HW struct is allocated.
1962 * As this function may be called again in some corner cases don't
1963 * do anything if NAPI was already initialized.
1964 */
bce97731 1965 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1966 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1967}
1968
d1ff5253 1969void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1970{
20d3b647 1971 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1972 int i;
a42a1844 1973
2e5d4a8f 1974 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1975
286ca8eb 1976 if (trans->trans_cfg->gen2)
13a3a390
SS		 1977 iwl_pcie_gen2_tx_free(trans);
1978 else
1979 iwl_pcie_tx_free(trans);
9805c446 1980 iwl_pcie_rx_free(trans);
6379103e 1981
10a54d81
LC		 1982 if (trans_pcie->rba.alloc_wq) {
1983 destroy_workqueue(trans_pcie->rba.alloc_wq);
1984 trans_pcie->rba.alloc_wq = NULL;
1985 }
1986
2e5d4a8f 1987 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1988 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1989 irq_set_affinity_hint(
1990 trans_pcie->msix_entries[i].vector,
1991 NULL);
7c8d91eb 1992 }
2e5d4a8f 1993
2e5d4a8f
HD		 1994 trans_pcie->msix_enabled = false;
1995 } else {
2e5d4a8f 1996 iwl_pcie_free_ict(trans);
2e5d4a8f 1997 }
a42a1844 1998
c2d20201
EG		 1999 iwl_pcie_free_fw_monitor(trans);
2000
6eb5e529
EG		 2001 for_each_possible_cpu(i) {
2002 struct iwl_tso_hdr_page *p =
2003 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
2004
2005 if (p->page)
2006 __free_page(p->page);
2007 }
2008
2009 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 2010 mutex_destroy(&trans_pcie->mutex);
7b501d10 2011 iwl_trans_free(trans);
34c1b7ba
EG		 2012}
2013
47107e84
DF		 2014static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2015{
47107e84 2016 if (state)
eb7ff77e 2017 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 2018 else
eb7ff77e 2019 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 2020}
2021
49564a80
LC		 2022struct iwl_trans_pcie_removal {
2023 struct pci_dev *pdev;
2024 struct work_struct work;
2025};
2026
2027static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2028{
2029 struct iwl_trans_pcie_removal *removal =
2030 container_of(wk, struct iwl_trans_pcie_removal, work);
2031 struct pci_dev *pdev = removal->pdev;
aba1e632 2032 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
49564a80
LC		 2033
2034 dev_err(&pdev->dev, "Device gone - attempting removal\n");
2035 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2036 pci_lock_rescan_remove();
2037 pci_dev_put(pdev);
2038 pci_stop_and_remove_bus_device(pdev);
2039 pci_unlock_rescan_remove();
2040
2041 kfree(removal);
2042 module_put(THIS_MODULE);
2043}
2044
23ba9340
EG		 2045static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2046 unsigned long *flags)
7a65d170
EG		 2047{
2048 int ret;
cfb4e624
JB		 2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2050
2051 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 2052
fc8a350d 2053 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2054 goto out;
2055
7a65d170 2056 /* this bit wakes up the NIC */
e139dc4a 2057 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
286ca8eb
LC		 2058 BIT(trans->trans_cfg->csr->flag_mac_access_req));
2059 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 2060 udelay(2);
7a65d170
EG		 2061
2062 /*
2063 * These bits say the device is running, and should keep running for
2064 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2065 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 2066 * HW with volatile SRAM must save/restore contents to/from
2067 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 2068 * Each direction takes approximately 1/4 millisecond; with this
2069 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2070 * series of register accesses are expected (e.g. reading Event Log),
2071 * to keep device from sleeping.
2072 *
2073 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2074 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 2075 * is just for hardware register access; but GP1 MAC_SLEEP
2076 * check is a good idea before accessing the SRAM of HW with
2077 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2078 *
2079 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2080 * and do not save/restore SRAM when power cycling.
2081 */
2082 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
286ca8eb
LC		 2083 BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
2084 (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
7a65d170
EG		 2085 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2086 if (unlikely(ret < 0)) {
49564a80
LC		 2087 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2088
23ba9340
EG		 2089 WARN_ONCE(1,
2090 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2091 cntrl);
2092
2093 iwl_trans_pcie_dump_regs(trans);
2094
2095 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2096 struct iwl_trans_pcie_removal *removal;
2097
f60c9e59 2098 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
49564a80
LC		 2099 goto err;
2100
2101 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2102
2103 /*
2104 * get a module reference to avoid doing this
2105 * while unloading anyway and to avoid
2106 * scheduling a work with code that's being
2107 * removed.
2108 */
2109 if (!try_module_get(THIS_MODULE)) {
2110 IWL_ERR(trans,
2111 "Module is being unloaded - abort\n");
2112 goto err;
2113 }
2114
2115 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2116 if (!removal) {
2117 module_put(THIS_MODULE);
2118 goto err;
2119 }
2120 /*
2121 * we don't need to clear this flag, because
2122 * the trans will be freed and reallocated.
2123 */
f60c9e59 2124 set_bit(STATUS_TRANS_DEAD, &trans->status);
49564a80
LC		 2125
2126 removal->pdev = to_pci_dev(trans->dev);
2127 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2128 pci_dev_get(removal->pdev);
2129 schedule_work(&removal->work);
2130 } else {
2131 iwl_write32(trans, CSR_RESET,
2132 CSR_RESET_REG_FLAG_FORCE_NMI);
2133 }
2134
2135err:
23ba9340
EG		 2136 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2137 return false;
7a65d170
EG		 2138 }
2139
b9439491 2140out:
e56b04ef
LE		 2141 /*
2142 * Fool sparse by faking we release the lock - sparse will
2143 * track nic_access anyway.
2144 */
cfb4e624 2145 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2146 return true;
2147}
2148
e56b04ef
LE		 2149static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2150 unsigned long *flags)
7a65d170 2151{
cfb4e624 2152 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2153
cfb4e624 2154 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2155
2156 /*
2157 * Fool sparse by faking we acquiring the lock - sparse will
2158 * track nic_access anyway.
2159 */
cfb4e624 2160 __acquire(&trans_pcie->reg_lock);
e56b04ef 2161
fc8a350d 2162 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2163 goto out;
2164
e139dc4a 2165 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
286ca8eb 2166 BIT(trans->trans_cfg->csr->flag_mac_access_req));
7a65d170
EG		 2167 /*
2168 * Above we read the CSR_GP_CNTRL register, which will flush
2169 * any previous writes, but we need the write that clears the
2170 * MAC_ACCESS_REQ bit to be performed before any other writes
2171 * scheduled on different CPUs (after we drop reg_lock).
2172 */
b9439491 2173out:
cfb4e624 2174 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2175}
2176
4fd442db
EG		 2177static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2178 void *buf, int dwords)
2179{
2180 unsigned long flags;
2181 int offs, ret = 0;
2182 u32 *vals = buf;
2183
23ba9340 2184 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2185 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2186 for (offs = 0; offs < dwords; offs++)
2187 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2188 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2189 } else {
2190 ret = -EBUSY;
2191 }
4fd442db
EG		 2192 return ret;
2193}
2194
2195static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2196 const void *buf, int dwords)
4fd442db
EG		 2197{
2198 unsigned long flags;
2199 int offs, ret = 0;
bf0fd5da 2200 const u32 *vals = buf;
4fd442db 2201
23ba9340 2202 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2203 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2204 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2205 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2206 vals ? vals[offs] : 0);
e56b04ef 2207 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2208 } else {
2209 ret = -EBUSY;
2210 }
4fd442db
EG		 2211 return ret;
2212}
7a65d170 2213
e0b8d405
EG		 2214static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2215 unsigned long txqs,
2216 bool freeze)
2217{
2218 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2219 int queue;
2220
2221 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2222 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2223 unsigned long now;
2224
2225 spin_lock_bh(&txq->lock);
2226
2227 now = jiffies;
2228
2229 if (txq->frozen == freeze)
2230 goto next_queue;
2231
2232 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2233 freeze ? "Freezing" : "Waking", queue);
2234
2235 txq->frozen = freeze;
2236
bb98ecd4 2237 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2238 goto next_queue;
2239
2240 if (freeze) {
2241 if (unlikely(time_after(now,
2242 txq->stuck_timer.expires))) {
2243 /*
2244 * The timer should have fired, maybe it is
2245 * spinning right now on the lock.
2246 */
2247 goto next_queue;
2248 }
2249 /* remember how long until the timer fires */
2250 txq->frozen_expiry_remainder =
2251 txq->stuck_timer.expires - now;
2252 del_timer(&txq->stuck_timer);
2253 goto next_queue;
2254 }
2255
2256 /*
2257 * Wake a non-empty queue -> arm timer with the
2258 * remainder before it froze
2259 */
2260 mod_timer(&txq->stuck_timer,
2261 now + txq->frozen_expiry_remainder);
2262
2263next_queue:
2264 spin_unlock_bh(&txq->lock);
2265 }
2266}
2267
0cd58eaa
EG		 2268static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2269{
2270 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2271 int i;
2272
286ca8eb 2273 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2274 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2275
2276 if (i == trans_pcie->cmd_queue)
2277 continue;
2278
2279 spin_lock_bh(&txq->lock);
2280
2281 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2282 txq->block--;
2283 if (!txq->block) {
2284 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2285 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2286 }
2287 } else if (block) {
2288 txq->block++;
2289 }
2290
2291 spin_unlock_bh(&txq->lock);
2292 }
2293}
2294
5f178cd2
EG		 2295#define IWL_FLUSH_WAIT_MS 2000
2296
38398efb
SS		 2297void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2298{
afb84431
EG		 2299 u32 txq_id = txq->id;
2300 u32 status;
2301 bool active;
2302 u8 fifo;
38398efb 2303
286ca8eb 2304 if (trans->trans_cfg->use_tfh) {
afb84431
EG		 2305 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2306 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2307 /* TODO: access new SCD registers and dump them */
2308 return;
38398efb 2309 }
afb84431
EG		 2310
2311 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2312 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2313 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2314
2315 IWL_ERR(trans,
2316 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2317 txq_id, active ? "" : "in", fifo,
2318 jiffies_to_msecs(txq->wd_timeout),
2319 txq->read_ptr, txq->write_ptr,
2320 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
286ca8eb
LC		 2321 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2322 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2323 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2324 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2325}
2326
92536c96
SS		 2327static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2328 struct iwl_trans_rxq_dma_data *data)
2329{
2330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2331
2332 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2333 return -EINVAL;
2334
2335 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2336 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2337 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2338 data->fr_bd_wid = 0;
2339
2340 return 0;
2341}
2342
d6d517b7 2343static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2344{
8ad71bef 2345 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2346 struct iwl_txq *txq;
5f178cd2 2347 unsigned long now = jiffies;
2ae48edc 2348 bool overflow_tx;
d6d517b7
SS		 2349 u8 wr_ptr;
2350
2b3fae66 2351 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2352 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2353 return -ENODEV;
2b3fae66 2354
d6d517b7
SS		 2355 if (!test_bit(txq_idx, trans_pcie->queue_used))
2356 return -EINVAL;
2357
2358 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2359 txq = trans_pcie->txq[txq_idx];
2ae48edc
SS		 2360
2361 spin_lock_bh(&txq->lock);
2362 overflow_tx = txq->overflow_tx ||
2363 !skb_queue_empty(&txq->overflow_q);
2364 spin_unlock_bh(&txq->lock);
2365
6aa7de05 2366 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2367
2ae48edc
SS		 2368 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2369 overflow_tx) &&
d6d517b7
SS		 2370 !time_after(jiffies,
2371 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2372 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2373
2ae48edc
SS		 2374 /*
2375 * If write pointer moved during the wait, warn only
2376 * if the TX came from op mode. In case TX came from
2377 * trans layer (overflow TX) don't warn.
2378 */
2379 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2380 "WR pointer moved while flushing %d -> %d\n",
2381 wr_ptr, write_ptr))
2382 return -ETIMEDOUT;
2ae48edc
SS		 2383 wr_ptr = write_ptr;
2384
d6d517b7 2385 usleep_range(1000, 2000);
2ae48edc
SS		 2386
2387 spin_lock_bh(&txq->lock);
2388 overflow_tx = txq->overflow_tx ||
2389 !skb_queue_empty(&txq->overflow_q);
2390 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2391 }
2392
2393 if (txq->read_ptr != txq->write_ptr) {
2394 IWL_ERR(trans,
2395 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2396 iwl_trans_pcie_log_scd_error(trans, txq);
2397 return -ETIMEDOUT;
2398 }
2399
2400 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2401
2402 return 0;
2403}
2404
2405static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2406{
2407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2408 int cnt;
5f178cd2
EG		 2409 int ret = 0;
2410
2411 /* waiting for all the tx frames complete might take a while */
79b6c8fe 2412 for (cnt = 0;
286ca8eb 2413 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2414 cnt++) {
fa1a91fd 2415
9ba1947a 2416 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2417 continue;
3cafdbe6
EG		 2418 if (!test_bit(cnt, trans_pcie->queue_used))
2419 continue;
2420 if (!(BIT(cnt) & txq_bm))
2421 continue;
748fa67c 2422
d6d517b7
SS		 2423 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2424 if (ret)
5f178cd2 2425 break;
5f178cd2 2426 }
1c3fea82 2427
5f178cd2
EG		 2428 return ret;
2429}
2430
e139dc4a
LE		 2431static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2432 u32 mask, u32 value)
2433{
e56b04ef 2434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2435 unsigned long flags;
2436
e56b04ef 2437 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2438 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2439 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2440}
2441
ff620849
EG		 2442static const char *get_csr_string(int cmd)
2443{
d9fb6465 2444#define IWL_CMD(x) case x: return #x
ff620849
EG		 2445 switch (cmd) {
2446 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2447 IWL_CMD(CSR_INT_COALESCING);
2448 IWL_CMD(CSR_INT);
2449 IWL_CMD(CSR_INT_MASK);
2450 IWL_CMD(CSR_FH_INT_STATUS);
2451 IWL_CMD(CSR_GPIO_IN);
2452 IWL_CMD(CSR_RESET);
2453 IWL_CMD(CSR_GP_CNTRL);
2454 IWL_CMD(CSR_HW_REV);
2455 IWL_CMD(CSR_EEPROM_REG);
2456 IWL_CMD(CSR_EEPROM_GP);
2457 IWL_CMD(CSR_OTP_GP_REG);
2458 IWL_CMD(CSR_GIO_REG);
2459 IWL_CMD(CSR_GP_UCODE_REG);
2460 IWL_CMD(CSR_GP_DRIVER_REG);
2461 IWL_CMD(CSR_UCODE_DRV_GP1);
2462 IWL_CMD(CSR_UCODE_DRV_GP2);
2463 IWL_CMD(CSR_LED_REG);
2464 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2465 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2466 IWL_CMD(CSR_ANA_PLL_CFG);
2467 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2468 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2469 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2470 default:
2471 return "UNKNOWN";
2472 }
d9fb6465 2473#undef IWL_CMD
ff620849
EG		 2474}
2475
990aa6d7 2476void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2477{
2478 int i;
2479 static const u32 csr_tbl[] = {
2480 CSR_HW_IF_CONFIG_REG,
2481 CSR_INT_COALESCING,
2482 CSR_INT,
2483 CSR_INT_MASK,
2484 CSR_FH_INT_STATUS,
2485 CSR_GPIO_IN,
2486 CSR_RESET,
2487 CSR_GP_CNTRL,
2488 CSR_HW_REV,
2489 CSR_EEPROM_REG,
2490 CSR_EEPROM_GP,
2491 CSR_OTP_GP_REG,
2492 CSR_GIO_REG,
2493 CSR_GP_UCODE_REG,
2494 CSR_GP_DRIVER_REG,
2495 CSR_UCODE_DRV_GP1,
2496 CSR_UCODE_DRV_GP2,
2497 CSR_LED_REG,
2498 CSR_DRAM_INT_TBL_REG,
2499 CSR_GIO_CHICKEN_BITS,
2500 CSR_ANA_PLL_CFG,
a812cba9 2501 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2502 CSR_HW_REV_WA_REG,
2503 CSR_DBG_HPET_MEM_REG
2504 };
2505 IWL_ERR(trans, "CSR values:\n");
2506 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2507 "CSR_INT_PERIODIC_REG)\n");
2508 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2509 IWL_ERR(trans, " %25s: 0X%08x\n",
2510 get_csr_string(csr_tbl[i]),
1042db2a 2511 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2512 }
2513}
2514
87e5666c
EG		 2515#ifdef CONFIG_IWLWIFI_DEBUGFS
2516/* create and remove of files */
2517#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
cf5d5663
GKH		 2518 debugfs_create_file(#name, mode, parent, trans, \
2519 &iwl_dbgfs_##name##_ops); \
87e5666c
EG		 2520} while (0)
2521
2522/* file operation */
87e5666c 2523#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2524static const struct file_operations iwl_dbgfs_##name##_ops = { \
2525 .read = iwl_dbgfs_##name##_read, \
234e3405 2526 .open = simple_open, \
87e5666c
EG		 2527 .llseek = generic_file_llseek, \
2528};
2529
16db88ba 2530#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2531static const struct file_operations iwl_dbgfs_##name##_ops = { \
2532 .write = iwl_dbgfs_##name##_write, \
234e3405 2533 .open = simple_open, \
16db88ba
EG		 2534 .llseek = generic_file_llseek, \
2535};
2536
87e5666c 2537#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2538static const struct file_operations iwl_dbgfs_##name##_ops = { \
2539 .write = iwl_dbgfs_##name##_write, \
2540 .read = iwl_dbgfs_##name##_read, \
234e3405 2541 .open = simple_open, \
87e5666c
EG		 2542 .llseek = generic_file_llseek, \
2543};
2544
87e5666c 2545static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2546 char __user *user_buf,
2547 size_t count, loff_t *ppos)
8ad71bef 2548{
5a878bf6 2549 struct iwl_trans *trans = file->private_data;
8ad71bef 2550 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2551 struct iwl_txq *txq;
87e5666c
EG		 2552 char *buf;
2553 int pos = 0;
2554 int cnt;
2555 int ret;
1745e440
WYG		 2556 size_t bufsz;
2557
79b6c8fe 2558 bufsz = sizeof(char) * 75 *
286ca8eb 2559 trans->trans_cfg->base_params->num_of_queues;
87e5666c 2560
b2a3b1c1 2561 if (!trans_pcie->txq_memory)
87e5666c 2562 return -EAGAIN;
f9e75447 2563
87e5666c
EG		 2564 buf = kzalloc(bufsz, GFP_KERNEL);
2565 if (!buf)
2566 return -ENOMEM;
2567
79b6c8fe 2568 for (cnt = 0;
286ca8eb 2569 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2570 cnt++) {
b2a3b1c1 2571 txq = trans_pcie->txq[cnt];
87e5666c 2572 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2573 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2574 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2575 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2576 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2577 txq->need_update, txq->frozen,
f40faf62 2578 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2579 }
2580 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2581 kfree(buf);
2582 return ret;
2583}
2584
2585static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2586 char __user *user_buf,
2587 size_t count, loff_t *ppos)
2588{
5a878bf6 2589 struct iwl_trans *trans = file->private_data;
20d3b647 2590 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2591 char *buf;
2592 int pos = 0, i, ret;
eb3dc36e 2593 size_t bufsz;
78485054
SS		 2594
2595 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2596
2597 if (!trans_pcie->rxq)
2598 return -EAGAIN;
2599
2600 buf = kzalloc(bufsz, GFP_KERNEL);
2601 if (!buf)
2602 return -ENOMEM;
2603
2604 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2605 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2606
2607 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2608 i);
2609 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2610 rxq->read);
2611 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2612 rxq->write);
2613 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2614 rxq->write_actual);
2615 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2616 rxq->need_update);
2617 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2618 rxq->free_count);
2619 if (rxq->rb_stts) {
0307c839
GBA		 2620 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2621 rxq));
78485054
SS		 2622 pos += scnprintf(buf + pos, bufsz - pos,
2623 "\tclosed_rb_num: %u\n",
0307c839 2624 r & 0x0FFF);
78485054
SS		 2625 } else {
2626 pos += scnprintf(buf + pos, bufsz - pos,
2627 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2628 }
87e5666c 2629 }
78485054
SS		 2630 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2631 kfree(buf);
2632
2633 return ret;
87e5666c
EG		 2634}
2635
1f7b6172
EG		 2636static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2637 char __user *user_buf,
20d3b647
JB		 2638 size_t count, loff_t *ppos)
2639{
1f7b6172 2640 struct iwl_trans *trans = file->private_data;
20d3b647 2641 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2642 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2643
2644 int pos = 0;
2645 char *buf;
2646 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2647 ssize_t ret;
2648
2649 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2650 if (!buf)
1f7b6172 2651 return -ENOMEM;
1f7b6172
EG		 2652
2653 pos += scnprintf(buf + pos, bufsz - pos,
2654 "Interrupt Statistics Report:\n");
2655
2656 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2657 isr_stats->hw);
2658 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2659 isr_stats->sw);
2660 if (isr_stats->sw || isr_stats->hw) {
2661 pos += scnprintf(buf + pos, bufsz - pos,
2662 "\tLast Restarting Code: 0x%X\n",
2663 isr_stats->err_code);
2664 }
2665#ifdef CONFIG_IWLWIFI_DEBUG
2666 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2667 isr_stats->sch);
2668 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2669 isr_stats->alive);
2670#endif
2671 pos += scnprintf(buf + pos, bufsz - pos,
2672 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2673
2674 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2675 isr_stats->ctkill);
2676
2677 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2678 isr_stats->wakeup);
2679
2680 pos += scnprintf(buf + pos, bufsz - pos,
2681 "Rx command responses:\t\t %u\n", isr_stats->rx);
2682
2683 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2684 isr_stats->tx);
2685
2686 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2687 isr_stats->unhandled);
2688
2689 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2690 kfree(buf);
2691 return ret;
2692}
2693
2694static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2695 const char __user *user_buf,
2696 size_t count, loff_t *ppos)
2697{
2698 struct iwl_trans *trans = file->private_data;
20d3b647 2699 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2700 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2701 u32 reset_flag;
078f1131 2702 int ret;
1f7b6172 2703
078f1131
JB		 2704 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2705 if (ret)
2706 return ret;
1f7b6172
EG		 2707 if (reset_flag == 0)
2708 memset(isr_stats, 0, sizeof(*isr_stats));
2709
2710 return count;
2711}
2712
16db88ba 2713static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2714 const char __user *user_buf,
2715 size_t count, loff_t *ppos)
16db88ba
EG		 2716{
2717 struct iwl_trans *trans = file->private_data;
16db88ba 2718
990aa6d7 2719 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2720
2721 return count;
2722}
2723
16db88ba 2724static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2725 char __user *user_buf,
2726 size_t count, loff_t *ppos)
16db88ba
EG		 2727{
2728 struct iwl_trans *trans = file->private_data;
94543a8d 2729 char *buf = NULL;
56c2477f 2730 ssize_t ret;
16db88ba 2731
56c2477f
JB		 2732 ret = iwl_dump_fh(trans, &buf);
2733 if (ret < 0)
2734 return ret;
2735 if (!buf)
2736 return -EINVAL;
2737 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2738 kfree(buf);
16db88ba
EG		 2739 return ret;
2740}
2741
fa4de7f7
JB		 2742static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2743 char __user *user_buf,
2744 size_t count, loff_t *ppos)
2745{
2746 struct iwl_trans *trans = file->private_data;
2747 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2748 char buf[100];
2749 int pos;
2750
2751 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2752 trans_pcie->debug_rfkill,
2753 !(iwl_read32(trans, CSR_GP_CNTRL) &
2754 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2755
2756 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2757}
2758
2759static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2760 const char __user *user_buf,
2761 size_t count, loff_t *ppos)
2762{
2763 struct iwl_trans *trans = file->private_data;
2764 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c5bf4fa1 2765 bool new_value;
fa4de7f7
JB		 2766 int ret;
2767
c5bf4fa1 2768 ret = kstrtobool_from_user(user_buf, count, &new_value);
fa4de7f7
JB		 2769 if (ret)
2770 return ret;
c5bf4fa1 2771 if (new_value == trans_pcie->debug_rfkill)
fa4de7f7
JB		 2772 return count;
2773 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
c5bf4fa1
JB		 2774 trans_pcie->debug_rfkill, new_value);
2775 trans_pcie->debug_rfkill = new_value;
fa4de7f7
JB		 2776 iwl_pcie_handle_rfkill_irq(trans);
2777
2778 return count;
2779}
2780
f7805b33
LC		 2781static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2782 struct file *file)
2783{
2784 struct iwl_trans *trans = inode->i_private;
2785 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2786
91c28b83
SM		 2787 if (!trans->dbg.dest_tlv ||
2788 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
f7805b33
LC		 2789 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2790 return -ENOENT;
2791 }
2792
2793 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2794 return -EBUSY;
2795
2796 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2797 return simple_open(inode, file);
2798}
2799
2800static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2801 struct file *file)
2802{
2803 struct iwl_trans_pcie *trans_pcie =
2804 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2805
2806 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2807 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2808 return 0;
2809}
2810
2811static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2812 void *buf, ssize_t *size,
2813 ssize_t *bytes_copied)
2814{
2815 int buf_size_left = count - *bytes_copied;
2816
2817 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2818 if (*size > buf_size_left)
2819 *size = buf_size_left;
2820
2821 *size -= copy_to_user(user_buf, buf, *size);
2822 *bytes_copied += *size;
2823
2824 if (buf_size_left == *size)
2825 return true;
2826 return false;
2827}
2828
2829static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2830 char __user *user_buf,
2831 size_t count, loff_t *ppos)
2832{
2833 struct iwl_trans *trans = file->private_data;
2834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
69f0e505 2835 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
f7805b33
LC		 2836 struct cont_rec *data = &trans_pcie->fw_mon_data;
2837 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2838 ssize_t size, bytes_copied = 0;
2839 bool b_full;
2840
91c28b83 2841 if (trans->dbg.dest_tlv) {
f7805b33 2842 write_ptr_addr =
91c28b83
SM		 2843 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2844 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
f7805b33
LC		 2845 } else {
2846 write_ptr_addr = MON_BUFF_WRPTR;
2847 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2848 }
2849
91c28b83 2850 if (unlikely(!trans->dbg.rec_on))
f7805b33
LC		 2851 return 0;
2852
2853 mutex_lock(&data->mutex);
2854 if (data->state ==
2855 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2856 mutex_unlock(&data->mutex);
2857 return 0;
2858 }
2859
2860 /* write_ptr position in bytes rather then DW */
2861 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2862 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2863
2864 if (data->prev_wrap_cnt == wrap_cnt) {
2865 size = write_ptr - data->prev_wr_ptr;
2866 curr_buf = cpu_addr + data->prev_wr_ptr;
2867 b_full = iwl_write_to_user_buf(user_buf, count,
2868 curr_buf, &size,
2869 &bytes_copied);
2870 data->prev_wr_ptr += size;
2871
2872 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2873 write_ptr < data->prev_wr_ptr) {
69f0e505 2874 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
f7805b33
LC		 2875 curr_buf = cpu_addr + data->prev_wr_ptr;
2876 b_full = iwl_write_to_user_buf(user_buf, count,
2877 curr_buf, &size,
2878 &bytes_copied);
2879 data->prev_wr_ptr += size;
2880
2881 if (!b_full) {
2882 size = write_ptr;
2883 b_full = iwl_write_to_user_buf(user_buf, count,
2884 cpu_addr, &size,
2885 &bytes_copied);
2886 data->prev_wr_ptr = size;
2887 data->prev_wrap_cnt++;
2888 }
2889 } else {
2890 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2891 write_ptr > data->prev_wr_ptr)
2892 IWL_WARN(trans,
2893 "write pointer passed previous write pointer, start copying from the beginning\n");
2894 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2895 data->prev_wr_ptr == 0))
2896 IWL_WARN(trans,
2897 "monitor data is out of sync, start copying from the beginning\n");
2898
2899 size = write_ptr;
2900 b_full = iwl_write_to_user_buf(user_buf, count,
2901 cpu_addr, &size,
2902 &bytes_copied);
2903 data->prev_wr_ptr = size;
2904 data->prev_wrap_cnt = wrap_cnt;
2905 }
2906
2907 mutex_unlock(&data->mutex);
2908
2909 return bytes_copied;
2910}
2911
1f7b6172 2912DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2913DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2914DEBUGFS_READ_FILE_OPS(rx_queue);
2915DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2916DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2917DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2918
f7805b33
LC		 2919static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2920 .read = iwl_dbgfs_monitor_data_read,
2921 .open = iwl_dbgfs_monitor_data_open,
2922 .release = iwl_dbgfs_monitor_data_release,
2923};
2924
f8a1edb7 2925/* Create the debugfs files and directories */
cf5d5663 2926void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2927{
f8a1edb7
JB		 2928 struct dentry *dir = trans->dbgfs_dir;
2929
2ef00c53
JP		 2930 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2931 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2932 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2933 DEBUGFS_ADD_FILE(csr, dir, 0200);
2934 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2935 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 2936 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
87e5666c 2937}
f7805b33
LC		 2938
2939static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2940{
2941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2942 struct cont_rec *data = &trans_pcie->fw_mon_data;
2943
2944 mutex_lock(&data->mutex);
2945 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2946 mutex_unlock(&data->mutex);
2947}
aadede6e 2948#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2949
6983ba69 2950static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2951{
3cd1980b 2952 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2953 u32 cmdlen = 0;
2954 int i;
2955
3cd1980b 2956 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2957 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2958
2959 return cmdlen;
2960}
2961
bd7fc617
EG		 2962static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2963 struct iwl_fw_error_dump_data **data,
2964 int allocated_rb_nums)
2965{
2966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2967 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2968 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2969 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2970 u32 i, r, j, rb_len = 0;
2971
2972 spin_lock(&rxq->lock);
2973
0307c839 2974 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2975
2976 for (i = rxq->read, j = 0;
2977 i != r && j < allocated_rb_nums;
2978 i = (i + 1) & RX_QUEUE_MASK, j++) {
2979 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2980 struct iwl_fw_error_dump_rb *rb;
2981
2982 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2983 DMA_FROM_DEVICE);
2984
2985 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2986
2987 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2988 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2989 rb = (void *)(*data)->data;
2990 rb->index = cpu_to_le32(i);
2991 memcpy(rb->data, page_address(rxb->page), max_len);
2992 /* remap the page for the free benefit */
2993 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2994 max_len,
2995 DMA_FROM_DEVICE);
2996
2997 *data = iwl_fw_error_next_data(*data);
2998 }
2999
3000 spin_unlock(&rxq->lock);
3001
3002 return rb_len;
3003}
473ad712
EG		 3004#define IWL_CSR_TO_DUMP (0x250)
3005
3006static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3007 struct iwl_fw_error_dump_data **data)
3008{
3009 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3010 __le32 *val;
3011 int i;
3012
3013 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3014 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3015 val = (void *)(*data)->data;
3016
3017 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3018 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3019
3020 *data = iwl_fw_error_next_data(*data);
3021
3022 return csr_len;
3023}
3024
06d51e0d
LK		 3025static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3026 struct iwl_fw_error_dump_data **data)
3027{
3028 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3029 unsigned long flags;
3030 __le32 *val;
3031 int i;
3032
23ba9340 3033 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 3034 return 0;
3035
3036 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3037 (*data)->len = cpu_to_le32(fh_regs_len);
3038 val = (void *)(*data)->data;
3039
286ca8eb 3040 if (!trans->trans_cfg->gen2)
723b45e2
LK		 3041 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3042 i += sizeof(u32))
3043 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3044 else
ea695b7c
ST		 3045 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3046 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 3047 i += sizeof(u32))
3048 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3049 i));
06d51e0d
LK		 3050
3051 iwl_trans_release_nic_access(trans, &flags);
3052
3053 *data = iwl_fw_error_next_data(*data);
3054
3055 return sizeof(**data) + fh_regs_len;
3056}
3057
cc79ef66
LK		 3058static u32
3059iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3060 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3061 u32 monitor_len)
3062{
3063 u32 buf_size_in_dwords = (monitor_len >> 2);
3064 u32 *buffer = (u32 *)fw_mon_data->data;
3065 unsigned long flags;
3066 u32 i;
3067
23ba9340 3068 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 3069 return 0;
3070
ea695b7c 3071 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 3072 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 3073 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3074 MON_DMARB_RD_DATA_ADDR);
3075 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 3076
3077 iwl_trans_release_nic_access(trans, &flags);
3078
3079 return monitor_len;
3080}
3081
7a14c23d
SS		 3082static void
3083iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3084 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3085{
c88580e1 3086 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
7a14c23d 3087
286ca8eb 3088 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3089 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3090 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3091 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3092 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
91c28b83
SM		 3093 } else if (trans->dbg.dest_tlv) {
3094 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3095 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3096 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
7a14c23d
SS		 3097 } else {
3098 base = MON_BUFF_BASE_ADDR;
3099 write_ptr = MON_BUFF_WRPTR;
3100 wrap_cnt = MON_BUFF_CYCLE_CNT;
3101 }
c88580e1
SM		 3102
3103 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3104 fw_mon_data->fw_mon_cycle_cnt =
3105 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3106 fw_mon_data->fw_mon_base_ptr =
3107 cpu_to_le32(iwl_read_prph(trans, base));
286ca8eb 3108 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3109 fw_mon_data->fw_mon_base_high_ptr =
3110 cpu_to_le32(iwl_read_prph(trans, base_high));
3111 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3112 }
3113 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3114}
3115
36fb9017
OG		 3116static u32
3117iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3118 struct iwl_fw_error_dump_data **data,
3119 u32 monitor_len)
3120{
69f0e505 3121 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
36fb9017
OG		 3122 u32 len = 0;
3123
91c28b83 3124 if (trans->dbg.dest_tlv ||
69f0e505 3125 (fw_mon->size &&
286ca8eb
LC		 3126 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3127 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
36fb9017 3128 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3129
3130 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3131 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3132
3133 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3134
3135 len += sizeof(**data) + sizeof(*fw_mon_data);
69f0e505
SM		 3136 if (fw_mon->size) {
3137 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3138 monitor_len = fw_mon->size;
91c28b83 3139 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3140 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3141 /*
3142 * Update pointers to reflect actual values after
3143 * shifting
3144 */
91c28b83 3145 if (trans->dbg.dest_tlv->version) {
fd527eb5
GBA		 3146 base = (iwl_read_prph(trans, base) &
3147 IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3148 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3149 base *= IWL_M2S_UNIT_SIZE;
3150 base += trans->cfg->smem_offset;
3151 } else {
3152 base = iwl_read_prph(trans, base) <<
91c28b83 3153 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3154 }
3155
36fb9017
OG		 3156 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3157 monitor_len / sizeof(u32));
91c28b83 3158 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
36fb9017
OG		 3159 monitor_len =
3160 iwl_trans_pci_dump_marbh_monitor(trans,
3161 fw_mon_data,
3162 monitor_len);
3163 } else {
3164 /* Didn't match anything - output no monitor data */
3165 monitor_len = 0;
3166 }
3167
3168 len += monitor_len;
3169 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3170 }
3171
3172 return len;
3173}
3174
93079fd5 3175static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3176{
69f0e505 3177 if (trans->dbg.fw_mon.size) {
da752717
SM		 3178 *len += sizeof(struct iwl_fw_error_dump_data) +
3179 sizeof(struct iwl_fw_error_dump_fw_mon) +
69f0e505
SM		 3180 trans->dbg.fw_mon.size;
3181 return trans->dbg.fw_mon.size;
91c28b83 3182 } else if (trans->dbg.dest_tlv) {
da752717 3183 u32 base, end, cfg_reg, monitor_len;
99684ae3 3184
91c28b83
SM		 3185 if (trans->dbg.dest_tlv->version == 1) {
3186 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
fd527eb5
GBA		 3187 cfg_reg = iwl_read_prph(trans, cfg_reg);
3188 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3189 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3190 base *= IWL_M2S_UNIT_SIZE;
3191 base += trans->cfg->smem_offset;
99684ae3 3192
fd527eb5
GBA		 3193 monitor_len =
3194 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
91c28b83 3195 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3196 monitor_len *= IWL_M2S_UNIT_SIZE;
3197 } else {
91c28b83
SM		 3198 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3199 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
99684ae3 3200
fd527eb5 3201 base = iwl_read_prph(trans, base) <<
91c28b83 3202 trans->dbg.dest_tlv->base_shift;
fd527eb5 3203 end = iwl_read_prph(trans, end) <<
91c28b83 3204 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3205
3206 /* Make "end" point to the actual end */
286ca8eb 3207 if (trans->trans_cfg->device_family >=
fd527eb5 3208 IWL_DEVICE_FAMILY_8000 ||
91c28b83
SM		 3209 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3210 end += (1 << trans->dbg.dest_tlv->end_shift);
fd527eb5
GBA		 3211 monitor_len = end - base;
3212 }
da752717
SM		 3213 *len += sizeof(struct iwl_fw_error_dump_data) +
3214 sizeof(struct iwl_fw_error_dump_fw_mon) +
3215 monitor_len;
3216 return monitor_len;
99684ae3 3217 }
da752717
SM		 3218 return 0;
3219}
3220
3221static struct iwl_trans_dump_data
3222*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
79f033f6 3223 u32 dump_mask)
da752717
SM		 3224{
3225 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3226 struct iwl_fw_error_dump_data *data;
3227 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3228 struct iwl_fw_error_dump_txcmd *txcmd;
3229 struct iwl_trans_dump_data *dump_data;
fefbf853 3230 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3231 int i, ptr;
3232 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
286ca8eb 3233 !trans->trans_cfg->mq_rx_supported &&
79f033f6
SS		 3234 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3235
3236 if (!dump_mask)
3237 return NULL;
da752717
SM		 3238
3239 /* transport dump header */
3240 len = sizeof(*dump_data);
3241
3242 /* host commands */
e4eee943 3243 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
8672aad3
SM		 3244 len += sizeof(*data) +
3245 cmdq->n_window * (sizeof(*txcmd) +
3246 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3247
3248 /* FW monitor */
fefbf853
SM		 3249 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3250 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3251
3252 /* CSR registers */
79f033f6 3253 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3254 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3255
36fb9017 3256 /* FH registers */
79f033f6 3257 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
286ca8eb 3258 if (trans->trans_cfg->gen2)
520f03ea 3259 len += sizeof(*data) +
ea695b7c
ST		 3260 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3261 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3262 else
3263 len += sizeof(*data) +
3264 (FH_MEM_UPPER_BOUND -
3265 FH_MEM_LOWER_BOUND);
3266 }
36fb9017
OG		 3267
3268 if (dump_rbs) {
78485054
SS		 3269 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3270 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3271 /* RBs */
0307c839
GBA		 3272 num_rbs =
3273 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3274 & 0x0FFF;
78485054 3275 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3276 len += num_rbs * (sizeof(*data) +
3277 sizeof(struct iwl_fw_error_dump_rb) +
3278 (PAGE_SIZE << trans_pcie->rx_page_order));
3279 }
3280
5538409b 3281 /* Paged memory for gen2 HW */
286ca8eb 3282 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3283 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3284 len += sizeof(*data) +
3285 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3286 trans->init_dram.paging[i].size;
5538409b 3287
48eb7b34
EG		 3288 dump_data = vzalloc(len);
3289 if (!dump_data)
3290 return NULL;
4d075007
JB		 3291
3292 len = 0;
48eb7b34 3293 data = (void *)dump_data->data;
520f03ea 3294
e4eee943 3295 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
520f03ea
SM		 3296 u16 tfd_size = trans_pcie->tfd_size;
3297
3298 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3299 txcmd = (void *)data->data;
3300 spin_lock_bh(&cmdq->lock);
3301 ptr = cmdq->write_ptr;
3302 for (i = 0; i < cmdq->n_window; i++) {
3303 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
08326a97 3304 u8 tfdidx;
520f03ea
SM		 3305 u32 caplen, cmdlen;
3306
08326a97
JB		 3307 if (trans->trans_cfg->use_tfh)
3308 tfdidx = idx;
3309 else
3310 tfdidx = ptr;
3311
520f03ea 3312 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
08326a97
JB		 3313 (u8 *)cmdq->tfds +
3314 tfd_size * tfdidx);
520f03ea
SM		 3315 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3316
3317 if (cmdlen) {
3318 len += sizeof(*txcmd) + caplen;
3319 txcmd->cmdlen = cpu_to_le32(cmdlen);
3320 txcmd->caplen = cpu_to_le32(caplen);
3321 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3322 caplen);
3323 txcmd = (void *)((u8 *)txcmd->data + caplen);
3324 }
3325
3326 ptr = iwl_queue_dec_wrap(trans, ptr);
4d075007 3327 }
520f03ea 3328 spin_unlock_bh(&cmdq->lock);
4d075007 3329
520f03ea
SM		 3330 data->len = cpu_to_le32(len);
3331 len += sizeof(*data);
3332 data = iwl_fw_error_next_data(data);
4d075007 3333 }
67c65f2c 3334
79f033f6 3335 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3336 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3337 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3338 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3339 if (dump_rbs)
3340 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3341
5538409b 3342 /* Paged memory for gen2 HW */
286ca8eb 3343 if (trans->trans_cfg->gen2 &&
79b6c8fe 3344 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3345 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3346 struct iwl_fw_error_dump_paging *paging;
505a00c0 3347 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3348
3349 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3350 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3351 paging = (void *)data->data;
3352 paging->index = cpu_to_le32(i);
5538409b 3353 memcpy(paging->data,
505a00c0 3354 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3355 data = iwl_fw_error_next_data(data);
3356
3357 len += sizeof(*data) + sizeof(*paging) + page_len;
3358 }
3359 }
79f033f6 3360 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3361 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3362
48eb7b34
EG		 3363 dump_data->len = len;
3364
3365 return dump_data;
4d075007 3366}
87e5666c 3367
4cbb8e50
LC		 3368#ifdef CONFIG_PM_SLEEP
3369static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3370{
4cbb8e50
LC		 3371 return 0;
3372}
3373
3374static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3375{
4cbb8e50
LC		 3376}
3377#endif /* CONFIG_PM_SLEEP */
3378
623e7766
SS		 3379#define IWL_TRANS_COMMON_OPS \
3380 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3381 .write8 = iwl_trans_pcie_write8, \
3382 .write32 = iwl_trans_pcie_write32, \
3383 .read32 = iwl_trans_pcie_read32, \
3384 .read_prph = iwl_trans_pcie_read_prph, \
3385 .write_prph = iwl_trans_pcie_write_prph, \
3386 .read_mem = iwl_trans_pcie_read_mem, \
3387 .write_mem = iwl_trans_pcie_write_mem, \
3388 .configure = iwl_trans_pcie_configure, \
3389 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3390 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3391 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3392 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3393 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
623e7766 3394 .dump_data = iwl_trans_pcie_dump_data, \
623e7766 3395 .d3_suspend = iwl_trans_pcie_d3_suspend, \
d1967ce6
SM		 3396 .d3_resume = iwl_trans_pcie_d3_resume, \
3397 .sync_nmi = iwl_trans_pcie_sync_nmi
623e7766
SS		 3398
3399#ifdef CONFIG_PM_SLEEP
3400#define IWL_TRANS_PM_OPS \
3401 .suspend = iwl_trans_pcie_suspend, \
3402 .resume = iwl_trans_pcie_resume,
3403#else
3404#define IWL_TRANS_PM_OPS
3405#endif /* CONFIG_PM_SLEEP */
3406
d1ff5253 3407static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3408 IWL_TRANS_COMMON_OPS,
3409 IWL_TRANS_PM_OPS
57a1dc89 3410 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3411 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3412 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3413 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3414
623e7766 3415 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3416
623e7766
SS		 3417 .tx = iwl_trans_pcie_tx,
3418 .reclaim = iwl_trans_pcie_reclaim,
3419
3420 .txq_disable = iwl_trans_pcie_txq_disable,
3421 .txq_enable = iwl_trans_pcie_txq_enable,
3422
3423 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3424
d6d517b7
SS		 3425 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3426
623e7766
SS		 3427 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3428 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3429#ifdef CONFIG_IWLWIFI_DEBUGFS
3430 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3431#endif
623e7766
SS		 3432};
3433
3434static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3435 IWL_TRANS_COMMON_OPS,
3436 IWL_TRANS_PM_OPS
3437 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3438 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3439 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3440 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3441
ca60da2e 3442 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3443
ab6c6445 3444 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3445 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3446
ba7136f3
AM		 3447 .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3448
6b35ff91
SS		 3449 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3450 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3451 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3452 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
f7805b33
LC		 3453#ifdef CONFIG_IWLWIFI_DEBUGFS
3454 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3455#endif
e6bb4c9c 3456};
a42a1844 3457
87ce05a2 3458struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
7e8258c0
LC		 3459 const struct pci_device_id *ent,
3460 const struct iwl_cfg_trans_params *cfg_trans)
a42a1844 3461{
a42a1844
EG		 3462 struct iwl_trans_pcie *trans_pcie;
3463 struct iwl_trans *trans;
a89c72ff
JB		 3464 int ret, addr_size, txcmd_size, txcmd_align;
3465 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3466
3467 if (!cfg_trans->gen2) {
3468 ops = &trans_ops_pcie;
3469 txcmd_size = sizeof(struct iwl_tx_cmd);
3470 txcmd_align = sizeof(void *);
3471 } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) {
3472 txcmd_size = sizeof(struct iwl_tx_cmd_gen2);
3473 txcmd_align = 64;
3474 } else {
3475 txcmd_size = sizeof(struct iwl_tx_cmd_gen3);
3476 txcmd_align = 128;
3477 }
3478
3479 txcmd_size += sizeof(struct iwl_cmd_header);
3480 txcmd_size += 36; /* biggest possible 802.11 header */
3481
3482 /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */
3483 if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align))
3484 return ERR_PTR(-EINVAL);
a42a1844 3485
5a41a86c
SD		 3486 ret = pcim_enable_device(pdev);
3487 if (ret)
3488 return ERR_PTR(ret);
3489
a89c72ff
JB		 3490 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3491 txcmd_size, txcmd_align);
7b501d10
JB		 3492 if (!trans)
3493 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3494
3495 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3496
a42a1844 3497 trans_pcie->trans = trans;
326477e4 3498 trans_pcie->opmode_down = true;
7b11488f 3499 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3500 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3501 mutex_init(&trans_pcie->mutex);
13df1aab 3502 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
8188a18e
JB		 3503
3504 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3505 WQ_HIGHPRI | WQ_UNBOUND, 1);
3506 if (!trans_pcie->rba.alloc_wq) {
3507 ret = -ENOMEM;
3508 goto out_free_trans;
3509 }
3510 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3511
6eb5e529
EG		 3512 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3513 if (!trans_pcie->tso_hdr_page) {
3514 ret = -ENOMEM;
3515 goto out_no_pci;
3516 }
c5bf4fa1 3517 trans_pcie->debug_rfkill = -1;
d819c6cf 3518
7e8258c0 3519 if (!cfg_trans->base_params->pcie_l1_allowed) {
f2532b04
EG		 3520 /*
3521 * W/A - seems to solve weird behavior. We need to remove this
3522 * if we don't want to stay in L1 all the time. This wastes a
3523 * lot of power.
3524 */
3525 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3526 PCIE_LINK_STATE_L1 |
3527 PCIE_LINK_STATE_CLKPM);
3528 }
a42a1844 3529
9416560e
GBA		 3530 trans_pcie->def_rx_queue = 0;
3531
7e8258c0 3532 if (cfg_trans->use_tfh) {
2c6262b7 3533 addr_size = 64;
3cd1980b 3534 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3535 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3536 } else {
2c6262b7 3537 addr_size = 36;
3cd1980b 3538 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3539 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3540 }
3cd1980b
SS		 3541 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3542
a42a1844
EG		 3543 pci_set_master(pdev);
3544
96a6497b 3545 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3546 if (!ret)
96a6497b
SS		 3547 ret = pci_set_consistent_dma_mask(pdev,
3548 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3549 if (ret) {
3550 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3551 if (!ret)
3552 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3553 DMA_BIT_MASK(32));
a42a1844 3554 /* both attempts failed: */
af3f2f74 3555 if (ret) {
6a4b09f8 3556 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3557 goto out_no_pci;
a42a1844
EG		 3558 }
3559 }
3560
5a41a86c 3561 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3562 if (ret) {
5a41a86c
SD		 3563 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3564 goto out_no_pci;
a42a1844
EG		 3565 }
3566
5a41a86c 3567 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3568 if (!trans_pcie->hw_base) {
5a41a86c 3569 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3570 ret = -ENODEV;
5a41a86c 3571 goto out_no_pci;
a42a1844
EG		 3572 }
3573
a42a1844
EG		 3574 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3575 * PCI Tx retries from interfering with C3 CPU state */
3576 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3577
83f7a85f
EG		 3578 trans_pcie->pci_dev = pdev;
3579 iwl_disable_interrupts(trans);
3580
08079a49 3581 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3582 if (trans->hw_rev == 0xffffffff) {
3583 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3584 ret = -EIO;
3585 goto out_no_pci;
3586 }
3587
b513ee7f
LK		 3588 /*
3589 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3590 * changed, and now the revision step also includes bit 0-1 (no more
3591 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3592 * in the old format.
3593 */
7e8258c0 3594 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
b513ee7f 3595 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3596 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3597
f9e5554c
EG		 3598 ret = iwl_pcie_prepare_card_hw(trans);
3599 if (ret) {
3600 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3601 goto out_no_pci;
f9e5554c
EG		 3602 }
3603
7a42baa6
EH		 3604 /*
3605 * in-order to recognize C step driver should read chip version
3606 * id located at the AUX bus MISC address space.
3607 */
7e8258c0 3608 ret = iwl_finish_nic_init(trans, cfg_trans);
c96b5eec 3609 if (ret)
5a41a86c 3610 goto out_no_pci;
7a42baa6 3611
7a42baa6
EH		 3612 }
3613
99be6166
LC		 3614 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3615
7e8258c0 3616 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
99673ee5 3617 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3618 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3619 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3620
69a10b29 3621 /* Initialize the wait queue for commands */
f946b529 3622 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3623
e5f3f215
HD		 3624 init_waitqueue_head(&trans_pcie->sx_waitq);
3625
2e5d4a8f 3626 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3627 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3628 if (ret)
5a41a86c 3629 goto out_no_pci;
2e5d4a8f
HD		 3630 } else {
3631 ret = iwl_pcie_alloc_ict(trans);
3632 if (ret)
5a41a86c 3633 goto out_no_pci;
a8b691e6 3634
5a41a86c
SD		 3635 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3636 iwl_pcie_isr,
3637 iwl_pcie_irq_handler,
3638 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3639 if (ret) {
3640 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3641 goto out_free_ict;
3642 }
3643 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3644 }
83f7a85f 3645
f7805b33
LC		 3646#ifdef CONFIG_IWLWIFI_DEBUGFS
3647 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3648 mutex_init(&trans_pcie->fw_mon_data.mutex);
3649#endif
3650
a9248de4
SM		 3651 iwl_dbg_tlv_init(trans);
3652
a42a1844
EG		 3653 return trans;
3654
a8b691e6
JB		 3655out_free_ict:
3656 iwl_pcie_free_ict(trans);
a42a1844 3657out_no_pci:
6eb5e529 3658 free_percpu(trans_pcie->tso_hdr_page);
8188a18e
JB		 3659 destroy_workqueue(trans_pcie->rba.alloc_wq);
3660out_free_trans:
7b501d10 3661 iwl_trans_free(trans);
af3f2f74 3662 return ERR_PTR(ret);
a42a1844 3663}
b8a7547d 3664
d1967ce6 3665void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
b8a7547d 3666{
1c6bca6d 3667 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
b8a7547d 3668 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
e4eee943 3669 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
1c6bca6d
SM		 3670 u32 inta_addr, sw_err_bit;
3671
3672 if (trans_pcie->msix_enabled) {
3673 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3674 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3675 } else {
3676 inta_addr = CSR_INT;
3677 sw_err_bit = CSR_INT_BIT_SW_ERR;
3678 }
b8a7547d 3679
e4eee943
SM		 3680 /* if the interrupts were already disabled, there is no point in
3681 * calling iwl_disable_interrupts
3682 */
3683 if (interrupts_enabled)
3684 iwl_disable_interrupts(trans);
3685
b8a7547d
SM		 3686 iwl_force_nmi(trans);
3687 while (time_after(timeout, jiffies)) {
1c6bca6d 3688 u32 inta_hw = iwl_read32(trans, inta_addr);
b8a7547d
SM		 3689
3690 /* Error detected by uCode */
1c6bca6d 3691 if (inta_hw & sw_err_bit) {
b8a7547d 3692 /* Clear causes register */
1c6bca6d 3693 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
b8a7547d
SM		 3694 break;
3695 }
3696
3697 mdelay(1);
3698 }
e4eee943
SM		 3699
3700 /* enable interrupts only if there were already enabled before this
3701 * function to avoid a case were the driver enable interrupts before
3702 * proper configurations were made
3703 */
3704 if (interrupts_enabled)
3705 iwl_enable_interrupts(trans);
3706
b8a7547d
SM		 3707 iwl_trans_fw_error(trans);
3708}
Linux 6.x block layer and io_uring tree(s)