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iwlwifi: mvm: fix typo in CTDP_CMD_OPERATION_REPORT description
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
4d075007 83#include "iwl-fw-error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
c2d20201
EG		 91static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92{
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105}
106
96c285da 107static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 108{
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 110 struct page *page = NULL;
c2d20201 111 dma_addr_t phys;
96c285da 112 u32 size = 0;
c2d20201
EG		 113 u8 power;
114
96c285da
EG		 115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
c2d20201
EG		 127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
96c285da 135 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
553452e5 149 page = NULL;
c2d20201
EG		 150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
40a76905 158 if (WARN_ON_ONCE(!page))
c2d20201
EG		 159 return;
160
96c285da
EG		 161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
c2d20201
EG		 167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170}
171
a812cba9
AB		 172static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173{
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177}
178
179static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180{
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184}
185
ddaf5a5b 186static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 187{
66337b7c 188 if (trans->cfg->apmg_not_supported)
95411d04
AA		 189 return;
190
ddaf5a5b
JB		 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 199}
200
af634bee
EG		 201/* PCI registers */
202#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 203
eda50cde 204void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 205{
20d3b647 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 207 u16 lctl;
9180ac50 208 u16 cap;
af634bee 209
af634bee
EG		 210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
7afe3705 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 221 else
af634bee 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 227 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 230}
231
a6c684ee
EG		 232/*
233 * Start up NIC's basic functionality after it has been reset
7afe3705 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 235 * NOTE: This does not load uCode nor start the embedded processor
236 */
7afe3705 237static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 238{
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
6e584873 248 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 268
7afe3705 269 iwl_pcie_apm_config(trans);
a6c684ee
EG		 270
271 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 363 usleep_range(1000, 2000);
a812cba9
AB		 364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 409 usleep_range(1000, 2000);
a812cba9
AB		 410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
e8c8935e 451void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 452{
e8c8935e 453 int ret;
cc56feb2
EG		 454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 465}
466
b7aaeae4 467static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 468{
469 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
470
b7aaeae4
EG		 471 if (op_mode_leave) {
472 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
473 iwl_pcie_apm_init(trans);
474
475 /* inform ME that we are leaving */
476 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
477 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
478 APMG_PCIDEV_STT_VAL_WAKE_ME);
6e584873 479 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 480 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
481 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
483 CSR_HW_IF_CONFIG_REG_PREPARE |
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 485 mdelay(1);
486 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
487 CSR_RESET_LINK_PWR_MGMT_DISABLED);
488 }
b7aaeae4
EG		 489 mdelay(5);
490 }
491
eb7ff77e 492 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 493
494 /* Stop device's DMA activity */
7afe3705 495 iwl_pcie_apm_stop_master(trans);
cc56feb2 496
a812cba9
AB		 497 if (trans->cfg->lp_xtal_workaround) {
498 iwl_pcie_apm_lp_xtal_enable(trans);
499 return;
500 }
501
cc56feb2
EG		 502 /* Reset the entire device */
503 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 504 usleep_range(1000, 2000);
cc56feb2
EG		 505
506 /*
507 * Clear "initialization complete" bit to move adapter from
508 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
509 */
510 iwl_clear_bit(trans, CSR_GP_CNTRL,
511 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
512}
513
7afe3705 514static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 515{
7b11488f 516 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 517
518 /* nic_init */
7b70bd63 519 spin_lock(&trans_pcie->irq_lock);
7afe3705 520 iwl_pcie_apm_init(trans);
392f8b78 521
7b70bd63 522 spin_unlock(&trans_pcie->irq_lock);
392f8b78 523
95411d04 524 iwl_pcie_set_pwr(trans, false);
392f8b78 525
ecdb975c 526 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 527
528 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 529 iwl_pcie_rx_init(trans);
392f8b78
EG		 530
531 /* Allocate or reset and init all Tx and Command queues */
f02831be 532 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 533 return -ENOMEM;
534
035f7ff2 535 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 536 /* enable shadow regs in HW */
20d3b647 537 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 538 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 539 }
540
392f8b78
EG		 541 return 0;
542}
543
544#define HW_READY_TIMEOUT (50)
545
546/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 547static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 548{
549 int ret;
550
1042db2a 551 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 552 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 553
554 /* See if we got it */
1042db2a 555 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 556 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
557 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
558 HW_READY_TIMEOUT);
392f8b78 559
6a08f514
EG		 560 if (ret >= 0)
561 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
562
6d8f6eeb 563 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 564 return ret;
565}
566
567/* Note: returns standard 0/-ERROR code */
eda50cde 568int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 569{
570 int ret;
289e5501 571 int t = 0;
501fd989 572 int iter;
392f8b78 573
6d8f6eeb 574 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 575
7afe3705 576 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 577 /* If the card is ready, exit 0 */
392f8b78
EG		 578 if (ret >= 0)
579 return 0;
580
c9fdec9f
EG		 581 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
582 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 583 usleep_range(1000, 2000);
c9fdec9f 584
501fd989
EG		 585 for (iter = 0; iter < 10; iter++) {
586 /* If HW is not ready, prepare the conditions to check again */
587 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
588 CSR_HW_IF_CONFIG_REG_PREPARE);
589
590 do {
591 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 592 if (ret >= 0)
593 return 0;
392f8b78 594
501fd989
EG		 595 usleep_range(200, 1000);
596 t += 200;
597 } while (t < 150000);
598 msleep(25);
599 }
392f8b78 600
7f2ac8fb 601 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 602
392f8b78
EG		 603 return ret;
604}
605
cf614297
EG		 606/*
607 * ucode
608 */
564cdce7
SS		 609static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
610 u32 dst_addr, dma_addr_t phy_addr,
611 u32 byte_cnt)
cf614297 612{
bac842da
EG		 613 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
614 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
615
616 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
617 dst_addr);
618
619 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
620 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
621
622 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
623 (iwl_get_dma_hi_addr(phy_addr)
624 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
625
626 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
627 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
628 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
629 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
630
631 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
632 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
633 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
634 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 635}
636
564cdce7
SS		 637static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
638 u32 dst_addr, dma_addr_t phy_addr,
639 u32 byte_cnt)
640{
641 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
642 unsigned long flags;
643 int ret;
644
645 trans_pcie->ucode_write_complete = false;
646
647 if (!iwl_trans_grab_nic_access(trans, &flags))
648 return -EIO;
649
eda50cde
SS		 650 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
651 byte_cnt);
bac842da 652 iwl_trans_release_nic_access(trans, &flags);
cf614297 653
13df1aab
JB		 654 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
655 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 656 if (!ret) {
83f84d7b 657 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 658 return -ETIMEDOUT;
659 }
660
661 return 0;
662}
663
7afe3705 664static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 665 const struct fw_desc *section)
cf614297 666{
83f84d7b
JB		 667 u8 *v_addr;
668 dma_addr_t p_addr;
baa21e83 669 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 670 int ret = 0;
671
83f84d7b
JB		 672 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
673 section_num);
674
c571573a
EG		 675 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
676 GFP_KERNEL | __GFP_NOWARN);
677 if (!v_addr) {
678 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
679 chunk_sz = PAGE_SIZE;
680 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
681 &p_addr, GFP_KERNEL);
682 if (!v_addr)
683 return -ENOMEM;
684 }
83f84d7b 685
c571573a 686 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 687 u32 copy_size, dst_addr;
688 bool extended_addr = false;
83f84d7b 689
c571573a 690 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 691 dst_addr = section->offset + offset;
692
693 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
694 dst_addr <= IWL_FW_MEM_EXTENDED_END)
695 extended_addr = true;
696
697 if (extended_addr)
698 iwl_set_bits_prph(trans, LMPM_CHICK,
699 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 700
83f84d7b 701 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 702 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
703 copy_size);
704
705 if (extended_addr)
706 iwl_clear_bits_prph(trans, LMPM_CHICK,
707 LMPM_CHICK_EXTENDED_ADDR_SPACE);
708
83f84d7b
JB		 709 if (ret) {
710 IWL_ERR(trans,
711 "Could not load the [%d] uCode section\n",
712 section_num);
713 break;
6dfa8d01 714 }
83f84d7b
JB		 715 }
716
c571573a 717 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 718 return ret;
719}
720
5dd9c68a
EG		 721static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
722 const struct fw_img *image,
723 int cpu,
724 int *first_ucode_section)
e2d6f4e7
EH		 725{
726 int shift_param;
dcab8ecd
EH		 727 int i, ret = 0, sec_num = 0x1;
728 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 729
730 if (cpu == 1) {
731 shift_param = 0;
034846cf 732 *first_ucode_section = 0;
e2d6f4e7
EH		 733 } else {
734 shift_param = 16;
034846cf 735 (*first_ucode_section)++;
e2d6f4e7
EH		 736 }
737
eef187a7 738 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 739 last_read_idx = i;
740
a6c4fb44
MG		 741 /*
742 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
743 * CPU1 to CPU2.
744 * PAGING_SEPARATOR_SECTION delimiter - separate between
745 * CPU2 non paged to CPU2 paging sec.
746 */
034846cf 747 if (!image->sec[i].data ||
a6c4fb44
MG		 748 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
749 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 750 IWL_DEBUG_FW(trans,
751 "Break since Data not valid or Empty section, sec = %d\n",
752 i);
189fa2fa 753 break;
034846cf
EH		 754 }
755
189fa2fa
EH		 756 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
757 if (ret)
758 return ret;
dcab8ecd 759
d6a2c5c7 760 /* Notify ucode of loaded section number and status */
eda50cde
SS		 761 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
762 val = val | (sec_num << shift_param);
763 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
764
dcab8ecd 765 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 766 }
767
034846cf
EH		 768 *first_ucode_section = last_read_idx;
769
2aabdbdc
EG		 770 iwl_enable_interrupts(trans);
771
d6a2c5c7
SS		 772 if (trans->cfg->use_tfh) {
773 if (cpu == 1)
774 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
775 0xFFFF);
776 else
777 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
778 0xFFFFFFFF);
779 } else {
780 if (cpu == 1)
781 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
782 0xFFFF);
783 else
784 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
785 0xFFFFFFFF);
786 }
afb88917 787
189fa2fa
EH		 788 return 0;
789}
e2d6f4e7 790
189fa2fa
EH		 791static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
792 const struct fw_img *image,
034846cf
EH		 793 int cpu,
794 int *first_ucode_section)
189fa2fa 795{
189fa2fa 796 int i, ret = 0;
034846cf 797 u32 last_read_idx = 0;
189fa2fa 798
3ce4a038 799 if (cpu == 1)
034846cf 800 *first_ucode_section = 0;
3ce4a038 801 else
034846cf 802 (*first_ucode_section)++;
189fa2fa 803
eef187a7 804 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 805 last_read_idx = i;
806
a6c4fb44
MG		 807 /*
808 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
809 * CPU1 to CPU2.
810 * PAGING_SEPARATOR_SECTION delimiter - separate between
811 * CPU2 non paged to CPU2 paging sec.
812 */
034846cf 813 if (!image->sec[i].data ||
a6c4fb44
MG		 814 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
815 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 816 IWL_DEBUG_FW(trans,
817 "Break since Data not valid or Empty section, sec = %d\n",
818 i);
189fa2fa 819 break;
034846cf
EH		 820 }
821
189fa2fa
EH		 822 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
823 if (ret)
824 return ret;
e2d6f4e7
EH		 825 }
826
034846cf
EH		 827 *first_ucode_section = last_read_idx;
828
e2d6f4e7
EH		 829 return 0;
830}
831
c9be849d 832void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7
LK		 833{
834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
835 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
836 int i;
837
838 if (dest->version)
839 IWL_ERR(trans,
840 "DBG DEST version is %d - expect issues\n",
841 dest->version);
842
843 IWL_INFO(trans, "Applying debug destination %s\n",
844 get_fw_dbg_mode_string(dest->monitor_mode));
845
846 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 847 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 848 else
849 IWL_WARN(trans, "PCI should have external buffer debug\n");
850
851 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
852 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
853 u32 val = le32_to_cpu(dest->reg_ops[i].val);
854
855 switch (dest->reg_ops[i].op) {
856 case CSR_ASSIGN:
857 iwl_write32(trans, addr, val);
858 break;
859 case CSR_SETBIT:
860 iwl_set_bit(trans, addr, BIT(val));
861 break;
862 case CSR_CLEARBIT:
863 iwl_clear_bit(trans, addr, BIT(val));
864 break;
865 case PRPH_ASSIGN:
866 iwl_write_prph(trans, addr, val);
867 break;
868 case PRPH_SETBIT:
869 iwl_set_bits_prph(trans, addr, BIT(val));
870 break;
871 case PRPH_CLEARBIT:
872 iwl_clear_bits_prph(trans, addr, BIT(val));
873 break;
869f3b15
HD		 874 case PRPH_BLOCKBIT:
875 if (iwl_read_prph(trans, addr) & BIT(val)) {
876 IWL_ERR(trans,
877 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
878 val, addr);
879 goto monitor;
880 }
881 break;
09e350f7
LK		 882 default:
883 IWL_ERR(trans, "FW debug - unknown OP %d\n",
884 dest->reg_ops[i].op);
885 break;
886 }
887 }
888
869f3b15 889monitor:
09e350f7
LK		 890 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
891 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
892 trans_pcie->fw_mon_phys >> dest->base_shift);
6e584873 893 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d
EG		 894 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
895 (trans_pcie->fw_mon_phys +
896 trans_pcie->fw_mon_size - 256) >>
897 dest->end_shift);
898 else
899 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
900 (trans_pcie->fw_mon_phys +
901 trans_pcie->fw_mon_size) >>
902 dest->end_shift);
09e350f7
LK		 903 }
904}
905
7afe3705 906static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 907 const struct fw_img *image)
cf614297 908{
c2d20201 909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 910 int ret = 0;
034846cf 911 int first_ucode_section;
cf614297 912
dcab8ecd 913 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 914 image->is_dual_cpus ? "Dual" : "Single");
915
dcab8ecd
EH		 916 /* load to FW the binary non secured sections of CPU1 */
917 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
918 if (ret)
919 return ret;
e2d6f4e7
EH		 920
921 if (image->is_dual_cpus) {
189fa2fa
EH		 922 /* set CPU2 header address */
923 iwl_write_prph(trans,
924 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
925 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 926
189fa2fa 927 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 928 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
929 &first_ucode_section);
189fa2fa
EH		 930 if (ret)
931 return ret;
e2d6f4e7 932 }
cf614297 933
c2d20201
EG		 934 /* supported for 7000 only for the moment */
935 if (iwlwifi_mod_params.fw_monitor &&
936 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 937 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 938
939 if (trans_pcie->fw_mon_size) {
940 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
941 trans_pcie->fw_mon_phys >> 4);
942 iwl_write_prph(trans, MON_BUFF_END_ADDR,
943 (trans_pcie->fw_mon_phys +
944 trans_pcie->fw_mon_size) >> 4);
945 }
09e350f7
LK		 946 } else if (trans->dbg_dest_tlv) {
947 iwl_pcie_apply_destination(trans);
c2d20201
EG		 948 }
949
2aabdbdc
EG		 950 iwl_enable_interrupts(trans);
951
e12ba844 952 /* release CPU reset */
5dd9c68a 953 iwl_write32(trans, CSR_RESET, 0);
e12ba844 954
dcab8ecd
EH		 955 return 0;
956}
189fa2fa 957
5dd9c68a
EG		 958static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
959 const struct fw_img *image)
dcab8ecd
EH		 960{
961 int ret = 0;
962 int first_ucode_section;
dcab8ecd
EH		 963
964 IWL_DEBUG_FW(trans, "working with %s CPU\n",
965 image->is_dual_cpus ? "Dual" : "Single");
966
a2227ce2
EG		 967 if (trans->dbg_dest_tlv)
968 iwl_pcie_apply_destination(trans);
969
82ea7966
SS		 970 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
971 iwl_read_prph(trans, WFPM_GP2));
972
973 /*
974 * Set default value. On resume reading the values that were
975 * zeored can provide debug data on the resume flow.
976 * This is for debugging only and has no functional impact.
977 */
978 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
979
dcab8ecd
EH		 980 /* configure the ucode to be ready to get the secured image */
981 /* release CPU reset */
982 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
983
984 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 985 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
986 &first_ucode_section);
dcab8ecd
EH		 987 if (ret)
988 return ret;
989
990 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 991 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
992 &first_ucode_section);
cf614297
EG		 993}
994
eda50cde 995bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 996{
326477e4 997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 998 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 999 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1000 bool report;
727c02df 1001
326477e4
JB		 1002 if (hw_rfkill) {
1003 set_bit(STATUS_RFKILL_HW, &trans->status);
1004 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1005 } else {
1006 clear_bit(STATUS_RFKILL_HW, &trans->status);
1007 if (trans_pcie->opmode_down)
1008 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1009 }
1010
1011 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1012
326477e4
JB		 1013 if (prev != report)
1014 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1015
1016 return hw_rfkill;
1017}
1018
7ca00409
HD		 1019struct iwl_causes_list {
1020 u32 cause_num;
1021 u32 mask_reg;
1022 u8 addr;
1023};
1024
1025static struct iwl_causes_list causes_list[] = {
1026 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1027 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1028 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1029 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1030 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1031 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1032 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1033 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1034 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1035 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1036 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1037 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1038 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1039 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1040};
1041
1042static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1043{
1044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1045 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1046 int i;
1047
1048 /*
1049 * Access all non RX causes and map them to the default irq.
1050 * In case we are missing at least one interrupt vector,
1051 * the first interrupt vector will serve non-RX and FBQ causes.
1052 */
1053 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1054 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1055 iwl_clear_bit(trans, causes_list[i].mask_reg,
1056 causes_list[i].cause_num);
1057 }
1058}
1059
1060static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1061{
1062 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1063 u32 offset =
1064 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1065 u32 val, idx;
1066
1067 /*
1068 * The first RX queue - fallback queue, which is designated for
1069 * management frame, command responses etc, is always mapped to the
1070 * first interrupt vector. The other RX queues are mapped to
1071 * the other (N - 2) interrupt vectors.
1072 */
1073 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1074 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1075 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1076 MSIX_FH_INT_CAUSES_Q(idx - offset));
1077 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1078 }
1079 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1080
1081 val = MSIX_FH_INT_CAUSES_Q(0);
1082 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1083 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1084 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1085
1086 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1087 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1088}
1089
77c09bc8 1090void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1091{
1092 struct iwl_trans *trans = trans_pcie->trans;
1093
1094 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1095 if (trans->cfg->mq_rx_supported &&
1096 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1097 iwl_write_prph(trans, UREG_CHICK,
1098 UREG_CHICK_MSI_ENABLE);
1099 return;
1100 }
d7270d61
HD		 1101 /*
1102 * The IVAR table needs to be configured again after reset,
1103 * but if the device is disabled, we can't write to
1104 * prph.
1105 */
1106 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1107 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1108
1109 /*
1110 * Each cause from the causes list above and the RX causes is
1111 * represented as a byte in the IVAR table. The first nibble
1112 * represents the bound interrupt vector of the cause, the second
1113 * represents no auto clear for this cause. This will be set if its
1114 * interrupt vector is bound to serve other causes.
1115 */
1116 iwl_pcie_map_rx_causes(trans);
1117
1118 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1119}
1120
1121static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1122{
1123 struct iwl_trans *trans = trans_pcie->trans;
1124
1125 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1126
83730058
HD		 1127 if (!trans_pcie->msix_enabled)
1128 return;
1129
1130 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1131 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1132 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1133 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1134}
1135
fa9f3281 1136static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1137{
43e58856 1138 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1139
fa9f3281
EG		 1140 lockdep_assert_held(&trans_pcie->mutex);
1141
1142 if (trans_pcie->is_down)
1143 return;
1144
1145 trans_pcie->is_down = true;
1146
43e58856 1147 /* tell the device to stop sending interrupts */
ae2c30bf 1148 iwl_disable_interrupts(trans);
ae2c30bf 1149
ab6cf8e8 1150 /* device going down, Stop using ICT table */
990aa6d7 1151 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1152
1153 /*
1154 * If a HW restart happens during firmware loading,
1155 * then the firmware loading might call this function
1156 * and later it might be called again due to the
1157 * restart. So don't process again if the device is
1158 * already dead.
1159 */
31b8b343 1160 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1161 IWL_DEBUG_INFO(trans,
1162 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1163 iwl_pcie_tx_stop(trans);
9805c446 1164 iwl_pcie_rx_stop(trans);
6379103e 1165
ab6cf8e8 1166 /* Power-down device's busmaster DMA clocks */
95411d04 1167 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1168 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1169 APMG_CLK_VAL_DMA_CLK_RQT);
1170 udelay(5);
1171 }
ab6cf8e8
EG		 1172 }
1173
1174 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1175 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1176 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1177
1178 /* Stop the device, and put it in low power state */
b7aaeae4 1179 iwl_pcie_apm_stop(trans, false);
43e58856 1180
03d6c3b0
EG		 1181 /* stop and reset the on-board processor */
1182 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1183 usleep_range(1000, 2000);
03d6c3b0 1184
f4a1f04a
GBA		 1185 /*
1186 * Upon stop, the IVAR table gets erased, so msi-x won't
1187 * work. This causes a bug in RF-KILL flows, since the interrupt
1188 * that enables radio won't fire on the correct irq, and the
1189 * driver won't be able to handle the interrupt.
1190 * Configure the IVAR table again after reset.
1191 */
1192 iwl_pcie_conf_msix_hw(trans_pcie);
1193
03d6c3b0
EG		 1194 /*
1195 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1196 * This is a bug in certain verions of the hardware.
1197 * Certain devices also keep sending HW RF kill interrupt all
1198 * the time, unless the interrupt is ACKed even if the interrupt
1199 * should be masked. Re-ACK all the interrupts here.
43e58856 1200 */
43e58856 1201 iwl_disable_interrupts(trans);
43e58856 1202
74fda971 1203 /* clear all status bits */
eb7ff77e
AN		 1204 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1205 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1206 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1207
1208 /*
1209 * Even if we stop the HW, we still want the RF kill
1210 * interrupt
1211 */
1212 iwl_enable_rfkill_int(trans);
1213
a6bd005f 1214 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1215 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1216}
1217
eda50cde 1218void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1219{
1220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1221
1222 if (trans_pcie->msix_enabled) {
1223 int i;
1224
496d83ca 1225 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1226 synchronize_irq(trans_pcie->msix_entries[i].vector);
1227 } else {
1228 synchronize_irq(trans_pcie->pci_dev->irq);
1229 }
1230}
1231
a6bd005f
EG		 1232static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1233 const struct fw_img *fw, bool run_in_rfkill)
1234{
1235 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1236 bool hw_rfkill;
1237 int ret;
1238
1239 /* This may fail if AMT took ownership of the device */
1240 if (iwl_pcie_prepare_card_hw(trans)) {
1241 IWL_WARN(trans, "Exit HW not ready\n");
1242 ret = -EIO;
1243 goto out;
1244 }
1245
1246 iwl_enable_rfkill_int(trans);
1247
1248 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1249
1250 /*
1251 * We enabled the RF-Kill interrupt and the handler may very
1252 * well be running. Disable the interrupts to make sure no other
1253 * interrupt can be fired.
1254 */
1255 iwl_disable_interrupts(trans);
1256
1257 /* Make sure it finished running */
2e5d4a8f 1258 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1259
1260 mutex_lock(&trans_pcie->mutex);
1261
1262 /* If platform's RF_KILL switch is NOT set to KILL */
727c02df 1263 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1264 if (hw_rfkill && !run_in_rfkill) {
1265 ret = -ERFKILL;
1266 goto out;
1267 }
1268
1269 /* Someone called stop_device, don't try to start_fw */
1270 if (trans_pcie->is_down) {
1271 IWL_WARN(trans,
1272 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1273 ret = -EIO;
a6bd005f
EG		 1274 goto out;
1275 }
1276
1277 /* make sure rfkill handshake bits are cleared */
1278 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1279 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1280 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1281
1282 /* clear (again), then enable host interrupts */
1283 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1284
1285 ret = iwl_pcie_nic_init(trans);
1286 if (ret) {
1287 IWL_ERR(trans, "Unable to init nic\n");
1288 goto out;
1289 }
1290
1291 /*
1292 * Now, we load the firmware and don't want to be interrupted, even
1293 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1294 * FH_TX interrupt which is needed to load the firmware). If the
1295 * RF-Kill switch is toggled, we will find out after having loaded
1296 * the firmware and return the proper value to the caller.
1297 */
1298 iwl_enable_fw_load_int(trans);
1299
1300 /* really make sure rfkill handshake bits are cleared */
1301 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1302 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1303
1304 /* Load the given image to the HW */
6e584873 1305 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1306 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1307 else
1308 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1309
1310 /* re-check RF-Kill state since we may have missed the interrupt */
727c02df 1311 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1312 if (hw_rfkill && !run_in_rfkill)
1313 ret = -ERFKILL;
1314
1315out:
1316 mutex_unlock(&trans_pcie->mutex);
1317 return ret;
1318}
1319
1320static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1321{
1322 iwl_pcie_reset_ict(trans);
1323 iwl_pcie_tx_start(trans, scd_addr);
1324}
1325
326477e4
JB		 1326void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1327 bool was_in_rfkill)
1328{
1329 bool hw_rfkill;
1330
1331 /*
1332 * Check again since the RF kill state may have changed while
1333 * all the interrupts were disabled, in this case we couldn't
1334 * receive the RF kill interrupt and update the state in the
1335 * op_mode.
1336 * Don't call the op_mode if the rkfill state hasn't changed.
1337 * This allows the op_mode to call stop_device from the rfkill
1338 * notification without endless recursion. Under very rare
1339 * circumstances, we might have a small recursion if the rfkill
1340 * state changed exactly now while we were called from stop_device.
1341 * This is very unlikely but can happen and is supported.
1342 */
1343 hw_rfkill = iwl_is_rfkill_set(trans);
1344 if (hw_rfkill) {
1345 set_bit(STATUS_RFKILL_HW, &trans->status);
1346 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1347 } else {
1348 clear_bit(STATUS_RFKILL_HW, &trans->status);
1349 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1350 }
1351 if (hw_rfkill != was_in_rfkill)
1352 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1353}
1354
fa9f3281
EG		 1355static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1356{
1357 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1358 bool was_in_rfkill;
fa9f3281
EG		 1359
1360 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1361 trans_pcie->opmode_down = true;
1362 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
fa9f3281 1363 _iwl_trans_pcie_stop_device(trans, low_power);
326477e4 1364 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1365 mutex_unlock(&trans_pcie->mutex);
1366}
1367
14cfca71
JB		 1368void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1369{
fa9f3281
EG		 1370 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1371 IWL_TRANS_GET_PCIE_TRANS(trans);
1372
1373 lockdep_assert_held(&trans_pcie->mutex);
1374
326477e4
JB		 1375 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1376 state ? "disabled" : "enabled");
77c09bc8
SS		 1377 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1378 if (trans->cfg->gen2)
1379 _iwl_trans_pcie_gen2_stop_device(trans, true);
1380 else
1381 _iwl_trans_pcie_stop_device(trans, true);
1382 }
ab6cf8e8
EG		 1383}
1384
23ae6128
MG		 1385static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1386 bool reset)
2dd4f9f7 1387{
23ae6128 1388 if (!reset) {
6dfb36c8
EP		 1389 /* Enable persistence mode to avoid reset */
1390 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1391 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1392 }
1393
2dd4f9f7 1394 iwl_disable_interrupts(trans);
debff618
JB		 1395
1396 /*
1397 * in testing mode, the host stays awake and the
1398 * hardware won't be reset (not even partially)
1399 */
1400 if (test)
1401 return;
1402
ddaf5a5b
JB		 1403 iwl_pcie_disable_ict(trans);
1404
2e5d4a8f 1405 iwl_pcie_synchronize_irqs(trans);
33b56af1 1406
2dd4f9f7
JB		 1407 iwl_clear_bit(trans, CSR_GP_CNTRL,
1408 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1409 iwl_clear_bit(trans, CSR_GP_CNTRL,
1410 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1411
1316d595
SS		 1412 iwl_pcie_enable_rx_wake(trans, false);
1413
23ae6128 1414 if (reset) {
6dfb36c8
EP		 1415 /*
1416 * reset TX queues -- some of their registers reset during S3
1417 * so if we don't reset everything here the D3 image would try
1418 * to execute some invalid memory upon resume
1419 */
1420 iwl_trans_pcie_tx_reset(trans);
1421 }
ddaf5a5b
JB		 1422
1423 iwl_pcie_set_pwr(trans, true);
1424}
1425
1426static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1427 enum iwl_d3_status *status,
23ae6128 1428 bool test, bool reset)
ddaf5a5b 1429{
d7270d61 1430 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1431 u32 val;
1432 int ret;
1433
debff618
JB		 1434 if (test) {
1435 iwl_enable_interrupts(trans);
1436 *status = IWL_D3_STATUS_ALIVE;
1437 return 0;
1438 }
1439
1316d595
SS		 1440 iwl_pcie_enable_rx_wake(trans, true);
1441
ddaf5a5b 1442 /*
d7270d61
HD		 1443 * Reconfigure IVAR table in case of MSIX or reset ict table in
1444 * MSI mode since HW reset erased it.
1445 * Also enables interrupts - none will happen as
1446 * the device doesn't know we're waking it up, only when
1447 * the opmode actually tells it after this call.
ddaf5a5b 1448 */
d7270d61
HD		 1449 iwl_pcie_conf_msix_hw(trans_pcie);
1450 if (!trans_pcie->msix_enabled)
1451 iwl_pcie_reset_ict(trans);
18dcb9a9 1452 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1453
1454 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1455 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1456
6e584873 1457 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28
EG		 1458 udelay(2);
1459
ddaf5a5b
JB		 1460 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1461 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1462 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1463 25000);
7f2ac8fb 1464 if (ret < 0) {
ddaf5a5b
JB		 1465 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1466 return ret;
1467 }
1468
a3ead656
EG		 1469 iwl_pcie_set_pwr(trans, false);
1470
23ae6128 1471 if (!reset) {
6dfb36c8
EP		 1472 iwl_clear_bit(trans, CSR_GP_CNTRL,
1473 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1474 } else {
1475 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1476
6dfb36c8
EP		 1477 ret = iwl_pcie_rx_init(trans);
1478 if (ret) {
1479 IWL_ERR(trans,
1480 "Failed to resume the device (RX reset)\n");
1481 return ret;
1482 }
ddaf5a5b
JB		 1483 }
1484
82ea7966
SS		 1485 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1486 iwl_read_prph(trans, WFPM_GP2));
1487
a3ead656
EG		 1488 val = iwl_read32(trans, CSR_RESET);
1489 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1490 *status = IWL_D3_STATUS_RESET;
1491 else
1492 *status = IWL_D3_STATUS_ALIVE;
1493
ddaf5a5b 1494 return 0;
2dd4f9f7
JB		 1495}
1496
2e5d4a8f
HD		 1497static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1498 struct iwl_trans *trans)
1499{
1500 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9fb064df 1501 int max_irqs, num_irqs, i, ret, nr_online_cpus;
2e5d4a8f 1502 u16 pci_cmd;
2e5d4a8f 1503
06f4b081
SS		 1504 if (!trans->cfg->mq_rx_supported)
1505 goto enable_msi;
1506
9fb064df
HD		 1507 nr_online_cpus = num_online_cpus();
1508 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1509 for (i = 0; i < max_irqs; i++)
1510 trans_pcie->msix_entries[i].entry = i;
496d83ca 1511
06f4b081
SS		 1512 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1513 MSIX_MIN_INTERRUPT_VECTORS,
1514 max_irqs);
1515 if (num_irqs < 0) {
2e5d4a8f 1516 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1517 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1518 num_irqs);
1519 goto enable_msi;
1520 }
1521 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1522
06f4b081
SS		 1523 IWL_DEBUG_INFO(trans,
1524 "MSI-X enabled. %d interrupt vectors were allocated\n",
1525 num_irqs);
1526
1527 /*
1528 * In case the OS provides fewer interrupts than requested, different
1529 * causes will share the same interrupt vector as follows:
1530 * One interrupt less: non rx causes shared with FBQ.
1531 * Two interrupts less: non rx causes shared with FBQ and RSS.
1532 * More than two interrupts: we will use fewer RSS queues.
1533 */
9fb064df 1534 if (num_irqs <= nr_online_cpus) {
06f4b081
SS		 1535 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1536 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1537 IWL_SHARED_IRQ_FIRST_RSS;
9fb064df 1538 } else if (num_irqs == nr_online_cpus + 1) {
06f4b081
SS		 1539 trans_pcie->trans->num_rx_queues = num_irqs;
1540 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1541 } else {
1542 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f
HD		 1543 }
1544
06f4b081
SS		 1545 trans_pcie->alloc_vecs = num_irqs;
1546 trans_pcie->msix_enabled = true;
1547 return;
1548
1549enable_msi:
1550 ret = pci_enable_msi(pdev);
1551 if (ret) {
1552 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1553 /* enable rfkill interrupt: hw bug w/a */
1554 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1555 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1556 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1557 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1558 }
1559 }
1560}
1561
7c8d91eb
HD		 1562static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1563{
1564 int iter_rx_q, i, ret, cpu, offset;
1565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1566
1567 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1568 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1569 offset = 1 + i;
1570 for (; i < iter_rx_q ; i++) {
1571 /*
1572 * Get the cpu prior to the place to search
1573 * (i.e. return will be > i - 1).
1574 */
1575 cpu = cpumask_next(i - offset, cpu_online_mask);
1576 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1577 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1578 &trans_pcie->affinity_mask[i]);
1579 if (ret)
1580 IWL_ERR(trans_pcie->trans,
1581 "Failed to set affinity mask for IRQ %d\n",
1582 i);
1583 }
1584}
1585
64fa3aff
SD		 1586static const char *queue_name(struct device *dev,
1587 struct iwl_trans_pcie *trans_p, int i)
1588{
1589 if (trans_p->shared_vec_mask) {
1590 int vec = trans_p->shared_vec_mask &
1591 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1592
1593 if (i == 0)
1594 return DRV_NAME ": shared IRQ";
1595
1596 return devm_kasprintf(dev, GFP_KERNEL,
1597 DRV_NAME ": queue %d", i + vec);
1598 }
1599 if (i == 0)
1600 return DRV_NAME ": default queue";
1601
1602 if (i == trans_p->alloc_vecs - 1)
1603 return DRV_NAME ": exception";
1604
1605 return devm_kasprintf(dev, GFP_KERNEL,
1606 DRV_NAME ": queue %d", i);
1607}
1608
2e5d4a8f
HD		 1609static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1610 struct iwl_trans_pcie *trans_pcie)
1611{
496d83ca 1612 int i;
2e5d4a8f 1613
496d83ca 1614 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1615 int ret;
5a41a86c 1616 struct msix_entry *msix_entry;
64fa3aff
SD		 1617 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1618
1619 if (!qname)
1620 return -ENOMEM;
5a41a86c
SD		 1621
1622 msix_entry = &trans_pcie->msix_entries[i];
1623 ret = devm_request_threaded_irq(&pdev->dev,
1624 msix_entry->vector,
1625 iwl_pcie_msix_isr,
1626 (i == trans_pcie->def_irq) ?
1627 iwl_pcie_irq_msix_handler :
1628 iwl_pcie_irq_rx_msix_handler,
1629 IRQF_SHARED,
64fa3aff 1630 qname,
5a41a86c 1631 msix_entry);
2e5d4a8f 1632 if (ret) {
2e5d4a8f
HD		 1633 IWL_ERR(trans_pcie->trans,
1634 "Error allocating IRQ %d\n", i);
5a41a86c 1635
2e5d4a8f
HD		 1636 return ret;
1637 }
1638 }
7c8d91eb 1639 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1640
1641 return 0;
1642}
1643
fa9f3281 1644static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1645{
fa9f3281 1646 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1647 int err;
e6bb4c9c 1648
fa9f3281
EG		 1649 lockdep_assert_held(&trans_pcie->mutex);
1650
7afe3705 1651 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1652 if (err) {
d6f1c316 1653 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1654 return err;
ebb7678d 1655 }
a6c684ee 1656
2997494f 1657 /* Reset the entire device */
ce836c76 1658 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1659 usleep_range(1000, 2000);
2997494f 1660
7afe3705 1661 iwl_pcie_apm_init(trans);
a6c684ee 1662
2e5d4a8f 1663 iwl_pcie_init_msix(trans_pcie);
83730058 1664
226c02ca
EG		 1665 /* From now on, the op_mode will be kept updated about RF kill state */
1666 iwl_enable_rfkill_int(trans);
1667
326477e4
JB		 1668 trans_pcie->opmode_down = false;
1669
fa9f3281
EG		 1670 /* Set is_down to false here so that...*/
1671 trans_pcie->is_down = false;
1672
727c02df
SS		 1673 /* ...rfkill can call stop_device and set it false if needed */
1674 iwl_trans_check_hw_rf_kill(trans);
d48e2074 1675
4cbb8e50
LC		 1676 /* Make sure we sync here, because we'll need full access later */
1677 if (low_power)
1678 pm_runtime_resume(trans->dev);
1679
a8b691e6 1680 return 0;
e6bb4c9c
EG		 1681}
1682
fa9f3281
EG		 1683static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1684{
1685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1686 int ret;
1687
1688 mutex_lock(&trans_pcie->mutex);
1689 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1690 mutex_unlock(&trans_pcie->mutex);
1691
1692 return ret;
1693}
1694
a4082843 1695static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1696{
20d3b647 1697 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1698
fa9f3281
EG		 1699 mutex_lock(&trans_pcie->mutex);
1700
a4082843 1701 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1702 iwl_disable_interrupts(trans);
ee7d737c 1703
b7aaeae4 1704 iwl_pcie_apm_stop(trans, true);
cc56feb2 1705
218733cf 1706 iwl_disable_interrupts(trans);
1df06bdc 1707
8d96bb61 1708 iwl_pcie_disable_ict(trans);
33b56af1 1709
fa9f3281 1710 mutex_unlock(&trans_pcie->mutex);
33b56af1 1711
2e5d4a8f 1712 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1713}
1714
03905495
EG		 1715static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1716{
05f5b97e 1717 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1718}
1719
1720static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1721{
05f5b97e 1722 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1723}
1724
1725static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1726{
05f5b97e 1727 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1728}
1729
6a06b6c1
EG		 1730static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1731{
f9477c17
AP		 1732 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1733 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1734 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1735}
1736
1737static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1738 u32 val)
1739{
1740 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1741 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1742 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1743}
1744
c6f600fc 1745static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1746 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1747{
1748 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1749
1750 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1751 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1752 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1753 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1754 trans_pcie->n_no_reclaim_cmds = 0;
1755 else
1756 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1757 if (trans_pcie->n_no_reclaim_cmds)
1758 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1759 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1760
6c4fbcbc
EG		 1761 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1762 trans_pcie->rx_page_order =
1763 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1764
046db346 1765 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1766 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1767 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1768
21cb3222
JB		 1769 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1770 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1771
39bdb17e
SD		 1772 trans->command_groups = trans_cfg->command_groups;
1773 trans->command_groups_size = trans_cfg->command_groups_size;
1774
f14d6b39
JB		 1775 /* Initialize NAPI here - it should be before registering to mac80211
1776 * in the opmode but after the HW struct is allocated.
1777 * As this function may be called again in some corner cases don't
1778 * do anything if NAPI was already initialized.
1779 */
bce97731 1780 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1781 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1782}
1783
d1ff5253 1784void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1785{
20d3b647 1786 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1787 int i;
a42a1844 1788
2e5d4a8f 1789 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1790
13a3a390
SS		 1791 if (trans->cfg->gen2)
1792 iwl_pcie_gen2_tx_free(trans);
1793 else
1794 iwl_pcie_tx_free(trans);
9805c446 1795 iwl_pcie_rx_free(trans);
6379103e 1796
2e5d4a8f 1797 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1798 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1799 irq_set_affinity_hint(
1800 trans_pcie->msix_entries[i].vector,
1801 NULL);
7c8d91eb 1802 }
2e5d4a8f 1803
2e5d4a8f
HD		 1804 trans_pcie->msix_enabled = false;
1805 } else {
2e5d4a8f 1806 iwl_pcie_free_ict(trans);
2e5d4a8f 1807 }
a42a1844 1808
c2d20201
EG		 1809 iwl_pcie_free_fw_monitor(trans);
1810
6eb5e529
EG		 1811 for_each_possible_cpu(i) {
1812 struct iwl_tso_hdr_page *p =
1813 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1814
1815 if (p->page)
1816 __free_page(p->page);
1817 }
1818
1819 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1820 mutex_destroy(&trans_pcie->mutex);
7b501d10 1821 iwl_trans_free(trans);
34c1b7ba
EG		 1822}
1823
47107e84
DF		 1824static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1825{
47107e84 1826 if (state)
eb7ff77e 1827 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1828 else
eb7ff77e 1829 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1830}
1831
23ba9340
EG		 1832static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1833 unsigned long *flags)
7a65d170
EG		 1834{
1835 int ret;
cfb4e624
JB		 1836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1837
1838 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1839
fc8a350d 1840 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1841 goto out;
1842
7a65d170 1843 /* this bit wakes up the NIC */
e139dc4a
LE		 1844 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1845 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6e584873 1846 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 1847 udelay(2);
7a65d170
EG		 1848
1849 /*
1850 * These bits say the device is running, and should keep running for
1851 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1852 * but they do not indicate that embedded SRAM is restored yet;
1853 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1854 * to/from host DRAM when sleeping/waking for power-saving.
1855 * Each direction takes approximately 1/4 millisecond; with this
1856 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1857 * series of register accesses are expected (e.g. reading Event Log),
1858 * to keep device from sleeping.
1859 *
1860 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1861 * SRAM is okay/restored. We don't check that here because this call
1862 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1863 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1864 *
1865 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1866 * and do not save/restore SRAM when power cycling.
1867 */
1868 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1869 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1870 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1871 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1872 if (unlikely(ret < 0)) {
1873 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1874 WARN_ONCE(1,
1875 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1876 iwl_read32(trans, CSR_GP_CNTRL));
1877 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1878 return false;
7a65d170
EG		 1879 }
1880
b9439491 1881out:
e56b04ef
LE		 1882 /*
1883 * Fool sparse by faking we release the lock - sparse will
1884 * track nic_access anyway.
1885 */
cfb4e624 1886 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1887 return true;
1888}
1889
e56b04ef
LE		 1890static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1891 unsigned long *flags)
7a65d170 1892{
cfb4e624 1893 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1894
cfb4e624 1895 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1896
1897 /*
1898 * Fool sparse by faking we acquiring the lock - sparse will
1899 * track nic_access anyway.
1900 */
cfb4e624 1901 __acquire(&trans_pcie->reg_lock);
e56b04ef 1902
fc8a350d 1903 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1904 goto out;
1905
e139dc4a
LE		 1906 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1907 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1908 /*
1909 * Above we read the CSR_GP_CNTRL register, which will flush
1910 * any previous writes, but we need the write that clears the
1911 * MAC_ACCESS_REQ bit to be performed before any other writes
1912 * scheduled on different CPUs (after we drop reg_lock).
1913 */
1914 mmiowb();
b9439491 1915out:
cfb4e624 1916 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1917}
1918
4fd442db
EG		 1919static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1920 void *buf, int dwords)
1921{
1922 unsigned long flags;
1923 int offs, ret = 0;
1924 u32 *vals = buf;
1925
23ba9340 1926 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1927 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1928 for (offs = 0; offs < dwords; offs++)
1929 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1930 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1931 } else {
1932 ret = -EBUSY;
1933 }
4fd442db
EG		 1934 return ret;
1935}
1936
1937static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1938 const void *buf, int dwords)
4fd442db
EG		 1939{
1940 unsigned long flags;
1941 int offs, ret = 0;
bf0fd5da 1942 const u32 *vals = buf;
4fd442db 1943
23ba9340 1944 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1945 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1946 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1947 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1948 vals ? vals[offs] : 0);
e56b04ef 1949 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1950 } else {
1951 ret = -EBUSY;
1952 }
4fd442db
EG		 1953 return ret;
1954}
7a65d170 1955
e0b8d405
EG		 1956static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1957 unsigned long txqs,
1958 bool freeze)
1959{
1960 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1961 int queue;
1962
1963 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 1964 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 1965 unsigned long now;
1966
1967 spin_lock_bh(&txq->lock);
1968
1969 now = jiffies;
1970
1971 if (txq->frozen == freeze)
1972 goto next_queue;
1973
1974 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1975 freeze ? "Freezing" : "Waking", queue);
1976
1977 txq->frozen = freeze;
1978
bb98ecd4 1979 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 1980 goto next_queue;
1981
1982 if (freeze) {
1983 if (unlikely(time_after(now,
1984 txq->stuck_timer.expires))) {
1985 /*
1986 * The timer should have fired, maybe it is
1987 * spinning right now on the lock.
1988 */
1989 goto next_queue;
1990 }
1991 /* remember how long until the timer fires */
1992 txq->frozen_expiry_remainder =
1993 txq->stuck_timer.expires - now;
1994 del_timer(&txq->stuck_timer);
1995 goto next_queue;
1996 }
1997
1998 /*
1999 * Wake a non-empty queue -> arm timer with the
2000 * remainder before it froze
2001 */
2002 mod_timer(&txq->stuck_timer,
2003 now + txq->frozen_expiry_remainder);
2004
2005next_queue:
2006 spin_unlock_bh(&txq->lock);
2007 }
2008}
2009
0cd58eaa
EG		 2010static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2011{
2012 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2013 int i;
2014
2015 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2016 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2017
2018 if (i == trans_pcie->cmd_queue)
2019 continue;
2020
2021 spin_lock_bh(&txq->lock);
2022
2023 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2024 txq->block--;
2025 if (!txq->block) {
2026 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2027 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2028 }
2029 } else if (block) {
2030 txq->block++;
2031 }
2032
2033 spin_unlock_bh(&txq->lock);
2034 }
2035}
2036
5f178cd2
EG		 2037#define IWL_FLUSH_WAIT_MS 2000
2038
38398efb
SS		 2039void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2040{
afb84431
EG		 2041 u32 txq_id = txq->id;
2042 u32 status;
2043 bool active;
2044 u8 fifo;
38398efb 2045
afb84431
EG		 2046 if (trans->cfg->use_tfh) {
2047 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2048 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2049 /* TODO: access new SCD registers and dump them */
2050 return;
38398efb 2051 }
afb84431
EG		 2052
2053 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2054 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2055 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2056
2057 IWL_ERR(trans,
2058 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2059 txq_id, active ? "" : "in", fifo,
2060 jiffies_to_msecs(txq->wd_timeout),
2061 txq->read_ptr, txq->write_ptr,
2062 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2063 (TFD_QUEUE_SIZE_MAX - 1),
2064 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2065 (TFD_QUEUE_SIZE_MAX - 1),
2066 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2067}
2068
d6d517b7 2069static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2070{
8ad71bef 2071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2072 struct iwl_txq *txq;
5f178cd2 2073 unsigned long now = jiffies;
d6d517b7
SS		 2074 u8 wr_ptr;
2075
2076 if (!test_bit(txq_idx, trans_pcie->queue_used))
2077 return -EINVAL;
2078
2079 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2080 txq = trans_pcie->txq[txq_idx];
2081 wr_ptr = ACCESS_ONCE(txq->write_ptr);
2082
2083 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2084 !time_after(jiffies,
2085 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2086 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2087
2088 if (WARN_ONCE(wr_ptr != write_ptr,
2089 "WR pointer moved while flushing %d -> %d\n",
2090 wr_ptr, write_ptr))
2091 return -ETIMEDOUT;
2092 usleep_range(1000, 2000);
2093 }
2094
2095 if (txq->read_ptr != txq->write_ptr) {
2096 IWL_ERR(trans,
2097 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2098 iwl_trans_pcie_log_scd_error(trans, txq);
2099 return -ETIMEDOUT;
2100 }
2101
2102 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2103
2104 return 0;
2105}
2106
2107static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2108{
2109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2110 int cnt;
5f178cd2
EG		 2111 int ret = 0;
2112
2113 /* waiting for all the tx frames complete might take a while */
035f7ff2 2114 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd 2115
9ba1947a 2116 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2117 continue;
3cafdbe6
EG		 2118 if (!test_bit(cnt, trans_pcie->queue_used))
2119 continue;
2120 if (!(BIT(cnt) & txq_bm))
2121 continue;
748fa67c 2122
d6d517b7
SS		 2123 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2124 if (ret)
5f178cd2 2125 break;
5f178cd2 2126 }
1c3fea82 2127
5f178cd2
EG		 2128 return ret;
2129}
2130
e139dc4a
LE		 2131static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2132 u32 mask, u32 value)
2133{
e56b04ef 2134 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2135 unsigned long flags;
2136
e56b04ef 2137 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2138 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2139 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2140}
2141
c24c7f58 2142static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2143{
2144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2145
2146 if (iwlwifi_mod_params.d0i3_disable)
2147 return;
2148
b3ff1270 2149 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2150
2151#ifdef CONFIG_PM
2152 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2153 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2154#endif /* CONFIG_PM */
7616f334
EP		 2155}
2156
c24c7f58 2157static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2158{
2159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2160
2161 if (iwlwifi_mod_params.d0i3_disable)
2162 return;
2163
b3ff1270
LC		 2164 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2165 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2166
5d93f3a2
LC		 2167#ifdef CONFIG_PM
2168 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2169 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2170#endif /* CONFIG_PM */
7616f334
EP		 2171}
2172
ff620849
EG		 2173static const char *get_csr_string(int cmd)
2174{
d9fb6465 2175#define IWL_CMD(x) case x: return #x
ff620849
EG		 2176 switch (cmd) {
2177 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2178 IWL_CMD(CSR_INT_COALESCING);
2179 IWL_CMD(CSR_INT);
2180 IWL_CMD(CSR_INT_MASK);
2181 IWL_CMD(CSR_FH_INT_STATUS);
2182 IWL_CMD(CSR_GPIO_IN);
2183 IWL_CMD(CSR_RESET);
2184 IWL_CMD(CSR_GP_CNTRL);
2185 IWL_CMD(CSR_HW_REV);
2186 IWL_CMD(CSR_EEPROM_REG);
2187 IWL_CMD(CSR_EEPROM_GP);
2188 IWL_CMD(CSR_OTP_GP_REG);
2189 IWL_CMD(CSR_GIO_REG);
2190 IWL_CMD(CSR_GP_UCODE_REG);
2191 IWL_CMD(CSR_GP_DRIVER_REG);
2192 IWL_CMD(CSR_UCODE_DRV_GP1);
2193 IWL_CMD(CSR_UCODE_DRV_GP2);
2194 IWL_CMD(CSR_LED_REG);
2195 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2196 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2197 IWL_CMD(CSR_ANA_PLL_CFG);
2198 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2199 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2200 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2201 default:
2202 return "UNKNOWN";
2203 }
d9fb6465 2204#undef IWL_CMD
ff620849
EG		 2205}
2206
990aa6d7 2207void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2208{
2209 int i;
2210 static const u32 csr_tbl[] = {
2211 CSR_HW_IF_CONFIG_REG,
2212 CSR_INT_COALESCING,
2213 CSR_INT,
2214 CSR_INT_MASK,
2215 CSR_FH_INT_STATUS,
2216 CSR_GPIO_IN,
2217 CSR_RESET,
2218 CSR_GP_CNTRL,
2219 CSR_HW_REV,
2220 CSR_EEPROM_REG,
2221 CSR_EEPROM_GP,
2222 CSR_OTP_GP_REG,
2223 CSR_GIO_REG,
2224 CSR_GP_UCODE_REG,
2225 CSR_GP_DRIVER_REG,
2226 CSR_UCODE_DRV_GP1,
2227 CSR_UCODE_DRV_GP2,
2228 CSR_LED_REG,
2229 CSR_DRAM_INT_TBL_REG,
2230 CSR_GIO_CHICKEN_BITS,
2231 CSR_ANA_PLL_CFG,
a812cba9 2232 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2233 CSR_HW_REV_WA_REG,
2234 CSR_DBG_HPET_MEM_REG
2235 };
2236 IWL_ERR(trans, "CSR values:\n");
2237 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2238 "CSR_INT_PERIODIC_REG)\n");
2239 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2240 IWL_ERR(trans, " %25s: 0X%08x\n",
2241 get_csr_string(csr_tbl[i]),
1042db2a 2242 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2243 }
2244}
2245
87e5666c
EG		 2246#ifdef CONFIG_IWLWIFI_DEBUGFS
2247/* create and remove of files */
2248#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2249 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2250 &iwl_dbgfs_##name##_ops)) \
9da987ac 2251 goto err; \
87e5666c
EG		 2252} while (0)
2253
2254/* file operation */
87e5666c 2255#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2256static const struct file_operations iwl_dbgfs_##name##_ops = { \
2257 .read = iwl_dbgfs_##name##_read, \
234e3405 2258 .open = simple_open, \
87e5666c
EG		 2259 .llseek = generic_file_llseek, \
2260};
2261
16db88ba 2262#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2263static const struct file_operations iwl_dbgfs_##name##_ops = { \
2264 .write = iwl_dbgfs_##name##_write, \
234e3405 2265 .open = simple_open, \
16db88ba
EG		 2266 .llseek = generic_file_llseek, \
2267};
2268
87e5666c 2269#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2270static const struct file_operations iwl_dbgfs_##name##_ops = { \
2271 .write = iwl_dbgfs_##name##_write, \
2272 .read = iwl_dbgfs_##name##_read, \
234e3405 2273 .open = simple_open, \
87e5666c
EG		 2274 .llseek = generic_file_llseek, \
2275};
2276
87e5666c 2277static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2278 char __user *user_buf,
2279 size_t count, loff_t *ppos)
8ad71bef 2280{
5a878bf6 2281 struct iwl_trans *trans = file->private_data;
8ad71bef 2282 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2283 struct iwl_txq *txq;
87e5666c
EG		 2284 char *buf;
2285 int pos = 0;
2286 int cnt;
2287 int ret;
1745e440
WYG		 2288 size_t bufsz;
2289
e0b8d405 2290 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2291
b2a3b1c1 2292 if (!trans_pcie->txq_memory)
87e5666c 2293 return -EAGAIN;
f9e75447 2294
87e5666c
EG		 2295 buf = kzalloc(bufsz, GFP_KERNEL);
2296 if (!buf)
2297 return -ENOMEM;
2298
035f7ff2 2299 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2300 txq = trans_pcie->txq[cnt];
87e5666c 2301 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2302 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2303 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2304 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2305 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2306 txq->need_update, txq->frozen,
f40faf62 2307 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2308 }
2309 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2310 kfree(buf);
2311 return ret;
2312}
2313
2314static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2315 char __user *user_buf,
2316 size_t count, loff_t *ppos)
2317{
5a878bf6 2318 struct iwl_trans *trans = file->private_data;
20d3b647 2319 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2320 char *buf;
2321 int pos = 0, i, ret;
2322 size_t bufsz = sizeof(buf);
2323
2324 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2325
2326 if (!trans_pcie->rxq)
2327 return -EAGAIN;
2328
2329 buf = kzalloc(bufsz, GFP_KERNEL);
2330 if (!buf)
2331 return -ENOMEM;
2332
2333 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2334 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2335
2336 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2337 i);
2338 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2339 rxq->read);
2340 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2341 rxq->write);
2342 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2343 rxq->write_actual);
2344 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2345 rxq->need_update);
2346 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2347 rxq->free_count);
2348 if (rxq->rb_stts) {
2349 pos += scnprintf(buf + pos, bufsz - pos,
2350 "\tclosed_rb_num: %u\n",
2351 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2352 0x0FFF);
2353 } else {
2354 pos += scnprintf(buf + pos, bufsz - pos,
2355 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2356 }
87e5666c 2357 }
78485054
SS		 2358 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2359 kfree(buf);
2360
2361 return ret;
87e5666c
EG		 2362}
2363
1f7b6172
EG		 2364static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2365 char __user *user_buf,
20d3b647
JB		 2366 size_t count, loff_t *ppos)
2367{
1f7b6172 2368 struct iwl_trans *trans = file->private_data;
20d3b647 2369 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2370 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2371
2372 int pos = 0;
2373 char *buf;
2374 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2375 ssize_t ret;
2376
2377 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2378 if (!buf)
1f7b6172 2379 return -ENOMEM;
1f7b6172
EG		 2380
2381 pos += scnprintf(buf + pos, bufsz - pos,
2382 "Interrupt Statistics Report:\n");
2383
2384 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2385 isr_stats->hw);
2386 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2387 isr_stats->sw);
2388 if (isr_stats->sw || isr_stats->hw) {
2389 pos += scnprintf(buf + pos, bufsz - pos,
2390 "\tLast Restarting Code: 0x%X\n",
2391 isr_stats->err_code);
2392 }
2393#ifdef CONFIG_IWLWIFI_DEBUG
2394 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2395 isr_stats->sch);
2396 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2397 isr_stats->alive);
2398#endif
2399 pos += scnprintf(buf + pos, bufsz - pos,
2400 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2401
2402 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2403 isr_stats->ctkill);
2404
2405 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2406 isr_stats->wakeup);
2407
2408 pos += scnprintf(buf + pos, bufsz - pos,
2409 "Rx command responses:\t\t %u\n", isr_stats->rx);
2410
2411 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2412 isr_stats->tx);
2413
2414 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2415 isr_stats->unhandled);
2416
2417 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2418 kfree(buf);
2419 return ret;
2420}
2421
2422static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2423 const char __user *user_buf,
2424 size_t count, loff_t *ppos)
2425{
2426 struct iwl_trans *trans = file->private_data;
20d3b647 2427 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2428 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2429 u32 reset_flag;
078f1131 2430 int ret;
1f7b6172 2431
078f1131
JB		 2432 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2433 if (ret)
2434 return ret;
1f7b6172
EG		 2435 if (reset_flag == 0)
2436 memset(isr_stats, 0, sizeof(*isr_stats));
2437
2438 return count;
2439}
2440
16db88ba 2441static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2442 const char __user *user_buf,
2443 size_t count, loff_t *ppos)
16db88ba
EG		 2444{
2445 struct iwl_trans *trans = file->private_data;
16db88ba 2446
990aa6d7 2447 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2448
2449 return count;
2450}
2451
16db88ba 2452static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2453 char __user *user_buf,
2454 size_t count, loff_t *ppos)
16db88ba
EG		 2455{
2456 struct iwl_trans *trans = file->private_data;
94543a8d 2457 char *buf = NULL;
56c2477f 2458 ssize_t ret;
16db88ba 2459
56c2477f
JB		 2460 ret = iwl_dump_fh(trans, &buf);
2461 if (ret < 0)
2462 return ret;
2463 if (!buf)
2464 return -EINVAL;
2465 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2466 kfree(buf);
16db88ba
EG		 2467 return ret;
2468}
2469
fa4de7f7
JB		 2470static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2471 char __user *user_buf,
2472 size_t count, loff_t *ppos)
2473{
2474 struct iwl_trans *trans = file->private_data;
2475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2476 char buf[100];
2477 int pos;
2478
2479 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2480 trans_pcie->debug_rfkill,
2481 !(iwl_read32(trans, CSR_GP_CNTRL) &
2482 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2483
2484 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2485}
2486
2487static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2488 const char __user *user_buf,
2489 size_t count, loff_t *ppos)
2490{
2491 struct iwl_trans *trans = file->private_data;
2492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2493 bool old = trans_pcie->debug_rfkill;
2494 int ret;
2495
2496 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2497 if (ret)
2498 return ret;
2499 if (old == trans_pcie->debug_rfkill)
2500 return count;
2501 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2502 old, trans_pcie->debug_rfkill);
2503 iwl_pcie_handle_rfkill_irq(trans);
2504
2505 return count;
2506}
2507
1f7b6172 2508DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2509DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2510DEBUGFS_READ_FILE_OPS(rx_queue);
2511DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2512DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2513DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2514
f8a1edb7
JB		 2515/* Create the debugfs files and directories */
2516int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2517{
f8a1edb7
JB		 2518 struct dentry *dir = trans->dbgfs_dir;
2519
87e5666c
EG		 2520 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2521 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2522 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2523 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2524 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
fa4de7f7 2525 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
87e5666c 2526 return 0;
9da987ac
MV		 2527
2528err:
2529 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2530 return -ENOMEM;
87e5666c 2531}
aadede6e 2532#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2533
6983ba69 2534static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2535{
3cd1980b 2536 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2537 u32 cmdlen = 0;
2538 int i;
2539
3cd1980b 2540 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2541 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2542
2543 return cmdlen;
2544}
2545
bd7fc617
EG		 2546static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2547 struct iwl_fw_error_dump_data **data,
2548 int allocated_rb_nums)
2549{
2550 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2551 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2552 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2553 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2554 u32 i, r, j, rb_len = 0;
2555
2556 spin_lock(&rxq->lock);
2557
2558 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2559
2560 for (i = rxq->read, j = 0;
2561 i != r && j < allocated_rb_nums;
2562 i = (i + 1) & RX_QUEUE_MASK, j++) {
2563 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2564 struct iwl_fw_error_dump_rb *rb;
2565
2566 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2567 DMA_FROM_DEVICE);
2568
2569 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2570
2571 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2572 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2573 rb = (void *)(*data)->data;
2574 rb->index = cpu_to_le32(i);
2575 memcpy(rb->data, page_address(rxb->page), max_len);
2576 /* remap the page for the free benefit */
2577 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2578 max_len,
2579 DMA_FROM_DEVICE);
2580
2581 *data = iwl_fw_error_next_data(*data);
2582 }
2583
2584 spin_unlock(&rxq->lock);
2585
2586 return rb_len;
2587}
473ad712
EG		 2588#define IWL_CSR_TO_DUMP (0x250)
2589
2590static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2591 struct iwl_fw_error_dump_data **data)
2592{
2593 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2594 __le32 *val;
2595 int i;
2596
2597 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2598 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2599 val = (void *)(*data)->data;
2600
2601 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2602 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2603
2604 *data = iwl_fw_error_next_data(*data);
2605
2606 return csr_len;
2607}
2608
06d51e0d
LK		 2609static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2610 struct iwl_fw_error_dump_data **data)
2611{
2612 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2613 unsigned long flags;
2614 __le32 *val;
2615 int i;
2616
23ba9340 2617 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2618 return 0;
2619
2620 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2621 (*data)->len = cpu_to_le32(fh_regs_len);
2622 val = (void *)(*data)->data;
2623
723b45e2
LK		 2624 if (!trans->cfg->gen2)
2625 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2626 i += sizeof(u32))
2627 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2628 else
2629 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2630 i += sizeof(u32))
2631 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2632 i));
06d51e0d
LK		 2633
2634 iwl_trans_release_nic_access(trans, &flags);
2635
2636 *data = iwl_fw_error_next_data(*data);
2637
2638 return sizeof(**data) + fh_regs_len;
2639}
2640
cc79ef66
LK		 2641static u32
2642iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2643 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2644 u32 monitor_len)
2645{
2646 u32 buf_size_in_dwords = (monitor_len >> 2);
2647 u32 *buffer = (u32 *)fw_mon_data->data;
2648 unsigned long flags;
2649 u32 i;
2650
23ba9340 2651 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2652 return 0;
2653
14ef1b43 2654 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2655 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2656 buffer[i] = iwl_read_prph_no_grab(trans,
2657 MON_DMARB_RD_DATA_ADDR);
2658 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2659
2660 iwl_trans_release_nic_access(trans, &flags);
2661
2662 return monitor_len;
2663}
2664
36fb9017
OG		 2665static u32
2666iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2667 struct iwl_fw_error_dump_data **data,
2668 u32 monitor_len)
2669{
2670 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2671 u32 len = 0;
2672
2673 if ((trans_pcie->fw_mon_page &&
2674 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2675 trans->dbg_dest_tlv) {
2676 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2677 u32 base, write_ptr, wrap_cnt;
2678
2679 /* If there was a dest TLV - use the values from there */
2680 if (trans->dbg_dest_tlv) {
2681 write_ptr =
2682 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2683 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2684 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2685 } else {
2686 base = MON_BUFF_BASE_ADDR;
2687 write_ptr = MON_BUFF_WRPTR;
2688 wrap_cnt = MON_BUFF_CYCLE_CNT;
2689 }
2690
2691 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2692 fw_mon_data = (void *)(*data)->data;
2693 fw_mon_data->fw_mon_wr_ptr =
2694 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2695 fw_mon_data->fw_mon_cycle_cnt =
2696 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2697 fw_mon_data->fw_mon_base_ptr =
2698 cpu_to_le32(iwl_read_prph(trans, base));
2699
2700 len += sizeof(**data) + sizeof(*fw_mon_data);
2701 if (trans_pcie->fw_mon_page) {
2702 /*
2703 * The firmware is now asserted, it won't write anything
2704 * to the buffer. CPU can take ownership to fetch the
2705 * data. The buffer will be handed back to the device
2706 * before the firmware will be restarted.
2707 */
2708 dma_sync_single_for_cpu(trans->dev,
2709 trans_pcie->fw_mon_phys,
2710 trans_pcie->fw_mon_size,
2711 DMA_FROM_DEVICE);
2712 memcpy(fw_mon_data->data,
2713 page_address(trans_pcie->fw_mon_page),
2714 trans_pcie->fw_mon_size);
2715
2716 monitor_len = trans_pcie->fw_mon_size;
2717 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2718 /*
2719 * Update pointers to reflect actual values after
2720 * shifting
2721 */
2722 base = iwl_read_prph(trans, base) <<
2723 trans->dbg_dest_tlv->base_shift;
2724 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2725 monitor_len / sizeof(u32));
2726 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2727 monitor_len =
2728 iwl_trans_pci_dump_marbh_monitor(trans,
2729 fw_mon_data,
2730 monitor_len);
2731 } else {
2732 /* Didn't match anything - output no monitor data */
2733 monitor_len = 0;
2734 }
2735
2736 len += monitor_len;
2737 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2738 }
2739
2740 return len;
2741}
2742
2743static struct iwl_trans_dump_data
2744*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2745 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2746{
2747 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2748 struct iwl_fw_error_dump_data *data;
b2a3b1c1 2749 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
4d075007 2750 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2751 struct iwl_trans_dump_data *dump_data;
bd7fc617 2752 u32 len, num_rbs;
99684ae3 2753 u32 monitor_len;
4d075007 2754 int i, ptr;
96a6497b
SS		 2755 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2756 !trans->cfg->mq_rx_supported;
4d075007 2757
473ad712
EG		 2758 /* transport dump header */
2759 len = sizeof(*dump_data);
2760
2761 /* host commands */
2762 len += sizeof(*data) +
bb98ecd4 2763 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2764
473ad712 2765 /* FW monitor */
99684ae3 2766 if (trans_pcie->fw_mon_page) {
c544e9c4 2767 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2768 trans_pcie->fw_mon_size;
2769 monitor_len = trans_pcie->fw_mon_size;
2770 } else if (trans->dbg_dest_tlv) {
2771 u32 base, end;
2772
2773 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2774 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2775
2776 base = iwl_read_prph(trans, base) <<
2777 trans->dbg_dest_tlv->base_shift;
2778 end = iwl_read_prph(trans, end) <<
2779 trans->dbg_dest_tlv->end_shift;
2780
2781 /* Make "end" point to the actual end */
6e584873 2782 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 ||
cc79ef66 2783 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2784 end += (1 << trans->dbg_dest_tlv->end_shift);
2785 monitor_len = end - base;
2786 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2787 monitor_len;
2788 } else {
2789 monitor_len = 0;
2790 }
c2d20201 2791
36fb9017
OG		 2792 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2793 dump_data = vzalloc(len);
2794 if (!dump_data)
2795 return NULL;
2796
2797 data = (void *)dump_data->data;
2798 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2799 dump_data->len = len;
2800
2801 return dump_data;
2802 }
2803
2804 /* CSR registers */
2805 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2806
36fb9017 2807 /* FH registers */
723b45e2
LK		 2808 if (trans->cfg->gen2)
2809 len += sizeof(*data) +
2810 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2811 else
2812 len += sizeof(*data) +
2813 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
36fb9017
OG		 2814
2815 if (dump_rbs) {
78485054
SS		 2816 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2817 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2818 /* RBs */
78485054 2819 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2820 & 0x0FFF;
78485054 2821 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2822 len += num_rbs * (sizeof(*data) +
2823 sizeof(struct iwl_fw_error_dump_rb) +
2824 (PAGE_SIZE << trans_pcie->rx_page_order));
2825 }
2826
5538409b
LK		 2827 /* Paged memory for gen2 HW */
2828 if (trans->cfg->gen2)
2829 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2830 len += sizeof(*data) +
2831 sizeof(struct iwl_fw_error_dump_paging) +
2832 trans_pcie->init_dram.paging[i].size;
2833
48eb7b34
EG		 2834 dump_data = vzalloc(len);
2835 if (!dump_data)
2836 return NULL;
4d075007
JB		 2837
2838 len = 0;
48eb7b34 2839 data = (void *)dump_data->data;
4d075007
JB		 2840 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2841 txcmd = (void *)data->data;
2842 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 2843 ptr = cmdq->write_ptr;
2844 for (i = 0; i < cmdq->n_window; i++) {
2845 u8 idx = get_cmd_index(cmdq, ptr);
4d075007
JB		 2846 u32 caplen, cmdlen;
2847
6983ba69
SS		 2848 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2849 trans_pcie->tfd_size * ptr);
4d075007
JB		 2850 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2851
2852 if (cmdlen) {
2853 len += sizeof(*txcmd) + caplen;
2854 txcmd->cmdlen = cpu_to_le32(cmdlen);
2855 txcmd->caplen = cpu_to_le32(caplen);
2856 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2857 txcmd = (void *)((u8 *)txcmd->data + caplen);
2858 }
2859
2860 ptr = iwl_queue_dec_wrap(ptr);
2861 }
2862 spin_unlock_bh(&cmdq->lock);
2863
2864 data->len = cpu_to_le32(len);
c2d20201 2865 len += sizeof(*data);
67c65f2c
EG		 2866 data = iwl_fw_error_next_data(data);
2867
473ad712 2868 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2869 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2870 if (dump_rbs)
2871 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2872
5538409b
LK		 2873 /* Paged memory for gen2 HW */
2874 if (trans->cfg->gen2) {
2875 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2876 struct iwl_fw_error_dump_paging *paging;
2877 dma_addr_t addr =
2878 trans_pcie->init_dram.paging[i].physical;
2879 u32 page_len = trans_pcie->init_dram.paging[i].size;
2880
2881 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2882 data->len = cpu_to_le32(sizeof(*paging) + page_len);
2883 paging = (void *)data->data;
2884 paging->index = cpu_to_le32(i);
2885 dma_sync_single_for_cpu(trans->dev, addr, page_len,
2886 DMA_BIDIRECTIONAL);
2887 memcpy(paging->data,
2888 trans_pcie->init_dram.paging[i].block, page_len);
2889 data = iwl_fw_error_next_data(data);
2890
2891 len += sizeof(*data) + sizeof(*paging) + page_len;
2892 }
2893 }
2894
36fb9017 2895 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2896
48eb7b34
EG		 2897 dump_data->len = len;
2898
2899 return dump_data;
4d075007 2900}
87e5666c 2901
4cbb8e50
LC		 2902#ifdef CONFIG_PM_SLEEP
2903static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2904{
e4c49c49
LC		 2905 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2906 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 2907 return iwl_pci_fw_enter_d0i3(trans);
2908
2909 return 0;
2910}
2911
2912static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2913{
e4c49c49
LC		 2914 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2915 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 2916 iwl_pci_fw_exit_d0i3(trans);
2917}
2918#endif /* CONFIG_PM_SLEEP */
2919
623e7766
SS		 2920#define IWL_TRANS_COMMON_OPS \
2921 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
2922 .write8 = iwl_trans_pcie_write8, \
2923 .write32 = iwl_trans_pcie_write32, \
2924 .read32 = iwl_trans_pcie_read32, \
2925 .read_prph = iwl_trans_pcie_read_prph, \
2926 .write_prph = iwl_trans_pcie_write_prph, \
2927 .read_mem = iwl_trans_pcie_read_mem, \
2928 .write_mem = iwl_trans_pcie_write_mem, \
2929 .configure = iwl_trans_pcie_configure, \
2930 .set_pmi = iwl_trans_pcie_set_pmi, \
2931 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
2932 .release_nic_access = iwl_trans_pcie_release_nic_access, \
2933 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
2934 .ref = iwl_trans_pcie_ref, \
2935 .unref = iwl_trans_pcie_unref, \
2936 .dump_data = iwl_trans_pcie_dump_data, \
623e7766
SS		 2937 .d3_suspend = iwl_trans_pcie_d3_suspend, \
2938 .d3_resume = iwl_trans_pcie_d3_resume
2939
2940#ifdef CONFIG_PM_SLEEP
2941#define IWL_TRANS_PM_OPS \
2942 .suspend = iwl_trans_pcie_suspend, \
2943 .resume = iwl_trans_pcie_resume,
2944#else
2945#define IWL_TRANS_PM_OPS
2946#endif /* CONFIG_PM_SLEEP */
2947
d1ff5253 2948static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 2949 IWL_TRANS_COMMON_OPS,
2950 IWL_TRANS_PM_OPS
57a1dc89 2951 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 2952 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2953 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2954 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2955
623e7766 2956 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 2957
623e7766
SS		 2958 .tx = iwl_trans_pcie_tx,
2959 .reclaim = iwl_trans_pcie_reclaim,
2960
2961 .txq_disable = iwl_trans_pcie_txq_disable,
2962 .txq_enable = iwl_trans_pcie_txq_enable,
2963
2964 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2965
d6d517b7
SS		 2966 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
2967
623e7766
SS		 2968 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2969 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2970};
2971
2972static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
2973 IWL_TRANS_COMMON_OPS,
2974 IWL_TRANS_PM_OPS
2975 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 2976 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
2977 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 2978 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 2979
ca60da2e 2980 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 2981
ab6c6445 2982 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 2983 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2984
6b35ff91
SS		 2985 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
2986 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 2987 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
e6bb4c9c 2988};
a42a1844 2989
87ce05a2 2990struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2991 const struct pci_device_id *ent,
2992 const struct iwl_cfg *cfg)
a42a1844 2993{
a42a1844
EG		 2994 struct iwl_trans_pcie *trans_pcie;
2995 struct iwl_trans *trans;
96a6497b 2996 int ret, addr_size;
a42a1844 2997
5a41a86c
SD		 2998 ret = pcim_enable_device(pdev);
2999 if (ret)
3000 return ERR_PTR(ret);
3001
623e7766
SS		 3002 if (cfg->gen2)
3003 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3004 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3005 else
3006 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3007 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 3008 if (!trans)
3009 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3010
3011 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3012
a42a1844 3013 trans_pcie->trans = trans;
326477e4 3014 trans_pcie->opmode_down = true;
7b11488f 3015 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3016 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3017 mutex_init(&trans_pcie->mutex);
13df1aab 3018 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 3019 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3020 if (!trans_pcie->tso_hdr_page) {
3021 ret = -ENOMEM;
3022 goto out_no_pci;
3023 }
a42a1844 3024
d819c6cf 3025
f2532b04
EG		 3026 if (!cfg->base_params->pcie_l1_allowed) {
3027 /*
3028 * W/A - seems to solve weird behavior. We need to remove this
3029 * if we don't want to stay in L1 all the time. This wastes a
3030 * lot of power.
3031 */
3032 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3033 PCIE_LINK_STATE_L1 |
3034 PCIE_LINK_STATE_CLKPM);
3035 }
a42a1844 3036
6983ba69 3037 if (cfg->use_tfh) {
2c6262b7 3038 addr_size = 64;
3cd1980b 3039 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3040 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3041 } else {
2c6262b7 3042 addr_size = 36;
3cd1980b 3043 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3044 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3045 }
3cd1980b
SS		 3046 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3047
a42a1844
EG		 3048 pci_set_master(pdev);
3049
96a6497b 3050 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3051 if (!ret)
96a6497b
SS		 3052 ret = pci_set_consistent_dma_mask(pdev,
3053 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3054 if (ret) {
3055 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3056 if (!ret)
3057 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3058 DMA_BIT_MASK(32));
a42a1844 3059 /* both attempts failed: */
af3f2f74 3060 if (ret) {
6a4b09f8 3061 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3062 goto out_no_pci;
a42a1844
EG		 3063 }
3064 }
3065
5a41a86c 3066 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3067 if (ret) {
5a41a86c
SD		 3068 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3069 goto out_no_pci;
a42a1844
EG		 3070 }
3071
5a41a86c 3072 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3073 if (!trans_pcie->hw_base) {
5a41a86c 3074 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3075 ret = -ENODEV;
5a41a86c 3076 goto out_no_pci;
a42a1844
EG		 3077 }
3078
a42a1844
EG		 3079 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3080 * PCI Tx retries from interfering with C3 CPU state */
3081 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3082
83f7a85f
EG		 3083 trans_pcie->pci_dev = pdev;
3084 iwl_disable_interrupts(trans);
3085
08079a49 3086 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3087 /*
3088 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3089 * changed, and now the revision step also includes bit 0-1 (no more
3090 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3091 * in the old format.
3092 */
6e584873 3093 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
7a42baa6 3094 unsigned long flags;
7a42baa6 3095
b513ee7f 3096 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3097 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3098
f9e5554c
EG		 3099 ret = iwl_pcie_prepare_card_hw(trans);
3100 if (ret) {
3101 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3102 goto out_no_pci;
f9e5554c
EG		 3103 }
3104
7a42baa6
EH		 3105 /*
3106 * in-order to recognize C step driver should read chip version
3107 * id located at the AUX bus MISC address space.
3108 */
3109 iwl_set_bit(trans, CSR_GP_CNTRL,
3110 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3111 udelay(2);
3112
3113 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3114 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3115 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3116 25000);
3117 if (ret < 0) {
3118 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3119 goto out_no_pci;
7a42baa6
EH		 3120 }
3121
23ba9340 3122 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3123 u32 hw_step;
3124
14ef1b43 3125 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3126 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3127 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3128 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3129 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3130 if (hw_step == 0x3)
3131 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3132 (SILICON_C_STEP << 2);
3133 iwl_trans_release_nic_access(trans, &flags);
3134 }
3135 }
3136
1afb0ae4
HD		 3137 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3138
2e5d4a8f 3139 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3140 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3141 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3142 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3143
69a10b29 3144 /* Initialize the wait queue for commands */
f946b529 3145 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3146
4cbb8e50
LC		 3147 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3148
2e5d4a8f
HD		 3149 if (trans_pcie->msix_enabled) {
3150 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
5a41a86c 3151 goto out_no_pci;
2e5d4a8f
HD		 3152 } else {
3153 ret = iwl_pcie_alloc_ict(trans);
3154 if (ret)
5a41a86c 3155 goto out_no_pci;
a8b691e6 3156
5a41a86c
SD		 3157 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3158 iwl_pcie_isr,
3159 iwl_pcie_irq_handler,
3160 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3161 if (ret) {
3162 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3163 goto out_free_ict;
3164 }
3165 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3166 }
83f7a85f 3167
b3ff1270
LC		 3168#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3169 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3170#else
3171 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3172#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3173
a42a1844
EG		 3174 return trans;
3175
a8b691e6
JB		 3176out_free_ict:
3177 iwl_pcie_free_ict(trans);
a42a1844 3178out_no_pci:
6eb5e529 3179 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3180 iwl_trans_free(trans);
af3f2f74 3181 return ERR_PTR(ret);
a42a1844 3182}
Linux 6.x block layer and io_uring tree(s)