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iwlwifi: mvm: remove the read_nvm from iwl_run_init_mvm_ucode
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5 8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
771db3a1 10 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
c85eb619 21 * The full GNU General Public License is included in this distribution
410dc5aa 22 * in the file called COPYING.
c85eb619
EG		 23 *
24 * Contact Information:
cb2f8277 25 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 * BSD LICENSE
29 *
553452e5 30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
771db3a1 32 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
c85eb619
EG		 33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 *
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
44 * distribution.
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 *
61 *****************************************************************************/
a42a1844 62#include <linux/pci.h>
e6bb4c9c 63#include <linux/interrupt.h>
87e5666c 64#include <linux/debugfs.h>
cf614297 65#include <linux/sched.h>
6d8f6eeb
EG		 66#include <linux/bitops.h>
67#include <linux/gfp.h>
48eb7b34 68#include <linux/vmalloc.h>
49564a80 69#include <linux/module.h>
f7805b33 70#include <linux/wait.h>
df67a1be 71#include <linux/seq_file.h>
e6bb4c9c 72
82575102 73#include "iwl-drv.h"
c85eb619 74#include "iwl-trans.h"
522376d2
EG		 75#include "iwl-csr.h"
76#include "iwl-prph.h"
cb6bb128 77#include "iwl-scd.h"
7a10e3e4 78#include "iwl-agn-hw.h"
d962f9b1 79#include "fw/error-dump.h"
520f03ea 80#include "fw/dbg.h"
a89c72ff 81#include "fw/api/tx.h"
6468a01a 82#include "internal.h"
06d51e0d 83#include "iwl-fh.h"
6654cd4e 84#include "iwl-context-info-gen3.h"
0439bb62 85
fe45773b
AN		 86/* extended range in FW SRAM */
87#define IWL_FW_MEM_EXTENDED_START 0x40000
88#define IWL_FW_MEM_EXTENDED_END 0x57FFF
89
4290eaad 90void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad 91{
c4d3f2ee
LC		 92#define PCI_DUMP_SIZE 352
93#define PCI_MEM_DUMP_SIZE 64
94#define PCI_PARENT_DUMP_SIZE 524
95#define PREFIX_LEN 32
a6d24fad
RJ		 96 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
97 struct pci_dev *pdev = trans_pcie->pci_dev;
98 u32 i, pos, alloc_size, *ptr, *buf;
99 char *prefix;
100
101 if (trans_pcie->pcie_dbg_dumped_once)
102 return;
103
104 /* Should be a multiple of 4 */
105 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
c4d3f2ee
LC		 106 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
107 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
108
a6d24fad 109 /* Alloc a max size buffer */
c4d3f2ee
LC		 110 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
111 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
112 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
113 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
114
a6d24fad
RJ		 115 buf = kmalloc(alloc_size, GFP_ATOMIC);
116 if (!buf)
117 return;
118 prefix = (char *)buf + alloc_size - PREFIX_LEN;
119
120 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
121
122 /* Print wifi device registers */
123 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
124 IWL_ERR(trans, "iwlwifi device config registers:\n");
125 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
126 if (pci_read_config_dword(pdev, i, ptr))
127 goto err_read;
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
129
130 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
c4d3f2ee 131 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 132 *ptr = iwl_read32(trans, i);
133 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
134
135 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
136 if (pos) {
137 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
138 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
139 if (pci_read_config_dword(pdev, pos + i, ptr))
140 goto err_read;
141 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
142 32, 4, buf, i, 0);
143 }
144
145 /* Print parent device registers next */
146 if (!pdev->bus->self)
147 goto out;
148
149 pdev = pdev->bus->self;
150 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
151
152 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
153 pci_name(pdev));
c4d3f2ee 154 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 155 if (pci_read_config_dword(pdev, i, ptr))
156 goto err_read;
157 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
158
159 /* Print root port AER registers */
160 pos = 0;
161 pdev = pcie_find_root_port(pdev);
162 if (pdev)
163 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
164 if (pos) {
165 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
166 pci_name(pdev));
167 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
168 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
169 if (pci_read_config_dword(pdev, pos + i, ptr))
170 goto err_read;
171 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
172 4, buf, i, 0);
173 }
f3402d6d 174 goto out;
a6d24fad
RJ		 175
176err_read:
177 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
178 IWL_ERR(trans, "Read failed at 0x%X\n", i);
179out:
180 trans_pcie->pcie_dbg_dumped_once = 1;
181 kfree(buf);
182}
183
870c2a11
GBA		 184static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
185{
186 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
6dece0e9 187 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
870c2a11
GBA		 188 usleep_range(5000, 6000);
189}
190
c2d20201
EG		 191static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
192{
69f0e505 193 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 194
69f0e505
SM		 195 if (!fw_mon->size)
196 return;
197
198 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
199 fw_mon->physical);
200
201 fw_mon->block = NULL;
202 fw_mon->physical = 0;
203 fw_mon->size = 0;
c2d20201
EG		 204}
205
88964b2e
SS		 206static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
207 u8 max_power, u8 min_power)
c2d20201 208{
69f0e505
SM		 209 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
210 void *block = NULL;
211 dma_addr_t physical = 0;
96c285da 212 u32 size = 0;
c2d20201
EG		 213 u8 power;
214
69f0e505
SM		 215 if (fw_mon->size)
216 return;
217
88964b2e 218 for (power = max_power; power >= min_power; power--) {
c2d20201 219 size = BIT(power);
69f0e505
SM		 220 block = dma_alloc_coherent(trans->dev, size, &physical,
221 GFP_KERNEL | __GFP_NOWARN);
222 if (!block)
c2d20201
EG		 223 continue;
224
c2d20201 225 IWL_INFO(trans,
c5f97542
SM		 226 "Allocated 0x%08x bytes for firmware monitor.\n",
227 size);
c2d20201
EG		 228 break;
229 }
230
69f0e505 231 if (WARN_ON_ONCE(!block))
c2d20201
EG		 232 return;
233
96c285da
EG		 234 if (power != max_power)
235 IWL_ERR(trans,
236 "Sorry - debug buffer is only %luK while you requested %luK\n",
237 (unsigned long)BIT(power - 10),
238 (unsigned long)BIT(max_power - 10));
239
69f0e505
SM		 240 fw_mon->block = block;
241 fw_mon->physical = physical;
242 fw_mon->size = size;
88964b2e
SS		 243}
244
245void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
246{
247 if (!max_power) {
248 /* default max_power is maximum */
249 max_power = 26;
250 } else {
251 max_power += 11;
252 }
253
254 if (WARN(max_power > 26,
255 "External buffer size for monitor is too big %d, check the FW TLV\n",
256 max_power))
257 return;
258
69f0e505 259 if (trans->dbg.fw_mon.size)
88964b2e
SS		 260 return;
261
262 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
c2d20201
EG		 263}
264
a812cba9
AB		 265static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
266{
267 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
268 ((reg & 0x0000ffff) | (2 << 28)));
269 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
270}
271
272static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
273{
274 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
275 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
276 ((reg & 0x0000ffff) | (3 << 28)));
277}
278
ddaf5a5b 279static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 280{
66337b7c 281 if (trans->cfg->apmg_not_supported)
95411d04
AA		 282 return;
283
ddaf5a5b
JB		 284 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
285 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
286 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
287 ~APMG_PS_CTRL_MSK_PWR_SRC);
288 else
289 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
290 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
291 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 292}
293
af634bee
EG		 294/* PCI registers */
295#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 296
eda50cde 297void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 298{
20d3b647 299 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 300 u16 lctl;
9180ac50 301 u16 cap;
af634bee 302
af634bee 303 /*
cc894b85
LC		 304 * L0S states have been found to be unstable with our devices
305 * and in newer hardware they are not officially supported at
306 * all, so we must always set the L0S_DISABLED bit.
af634bee 307 */
cc894b85
LC		 308 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
309
7afe3705 310 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
438a0f0a 311 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 312
313 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
314 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 315 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
316 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
317 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 318}
319
a6c684ee
EG		 320/*
321 * Start up NIC's basic functionality after it has been reset
7afe3705 322 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 323 * NOTE: This does not load uCode nor start the embedded processor
324 */
7afe3705 325static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 326{
52b6e168
EG		 327 int ret;
328
a6c684ee
EG		 329 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
330
331 /*
332 * Use "set_bit" below rather than "write", to preserve any hardware
333 * bits already set by default after reset.
334 */
335
336 /* Disable L0S exit timer (platform NMI Work/Around) */
286ca8eb 337 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 338 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
339 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 340
341 /*
342 * Disable L0s without affecting L1;
343 * don't wait for ICH L0s (ICH bug W/A)
344 */
345 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 346 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 347
348 /* Set FH wait threshold to maximum (HW error during stress W/A) */
349 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
350
351 /*
352 * Enable HAP INTA (interrupt from management bus) to
353 * wake device's PCI Express link L1a -> L0s
354 */
355 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 356 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 357
7afe3705 358 iwl_pcie_apm_config(trans);
a6c684ee
EG		 359
360 /* Configure analog phase-lock-loop before activating to D0A */
286ca8eb 361 if (trans->trans_cfg->base_params->pll_cfg)
77d76931 362 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 363
7d34a7d7 364 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 365 if (ret)
52b6e168 366 return ret;
a6c684ee 367
2d93aee1
EG		 368 if (trans->cfg->host_interrupt_operation_mode) {
369 /*
370 * This is a bit of an abuse - This is needed for 7260 / 3160
371 * only check host_interrupt_operation_mode even if this is
372 * not related to host_interrupt_operation_mode.
373 *
374 * Enable the oscillator to count wake up time for L1 exit. This
375 * consumes slightly more power (100uA) - but allows to be sure
376 * that we wake up from L1 on time.
377 *
378 * This looks weird: read twice the same register, discard the
379 * value, set a bit, and yet again, read that same register
380 * just to discard the value. But that's the way the hardware
381 * seems to like it.
382 */
383 iwl_read_prph(trans, OSC_CLK);
384 iwl_read_prph(trans, OSC_CLK);
385 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
386 iwl_read_prph(trans, OSC_CLK);
387 iwl_read_prph(trans, OSC_CLK);
388 }
389
a6c684ee
EG		 390 /*
391 * Enable DMA clock and wait for it to stabilize.
392 *
3073d8c0
EH		 393 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
394 * bits do not disable clocks. This preserves any hardware
395 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 396 */
95411d04 397 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 398 iwl_write_prph(trans, APMG_CLK_EN_REG,
399 APMG_CLK_VAL_DMA_CLK_RQT);
400 udelay(20);
401
402 /* Disable L1-Active */
403 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
404 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
405
406 /* Clear the interrupt in APMG if the NIC is in RFKILL */
407 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
408 APMG_RTC_INT_STT_RFKILL);
409 }
889b1696 410
eb7ff77e 411 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 412
52b6e168 413 return 0;
a6c684ee
EG		 414}
415
a812cba9
AB		 416/*
417 * Enable LP XTAL to avoid HW bug where device may consume much power if
418 * FW is not loaded after device reset. LP XTAL is disabled by default
419 * after device HW reset. Do it only if XTAL is fed by internal source.
420 * Configure device's "persistence" mode to avoid resetting XTAL again when
421 * SHRD_HW_RST occurs in S3.
422 */
423static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
424{
425 int ret;
426 u32 apmg_gp1_reg;
427 u32 apmg_xtal_cfg_reg;
428 u32 dl_cfg_reg;
429
430 /* Force XTAL ON */
431 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
432 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
433
870c2a11 434 iwl_trans_pcie_sw_reset(trans);
a812cba9 435
7d34a7d7 436 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 437 if (WARN_ON(ret)) {
a812cba9
AB		 438 /* Release XTAL ON request */
439 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
440 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
441 return;
442 }
443
444 /*
445 * Clear "disable persistence" to avoid LP XTAL resetting when
446 * SHRD_HW_RST is applied in S3.
447 */
448 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
449 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
450
451 /*
452 * Force APMG XTAL to be active to prevent its disabling by HW
453 * caused by APMG idle state.
454 */
455 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
456 SHR_APMG_XTAL_CFG_REG);
457 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
458 apmg_xtal_cfg_reg |
459 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
460
870c2a11 461 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 462
463 /* Enable LP XTAL by indirect access through CSR */
464 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
465 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
466 SHR_APMG_GP1_WF_XTAL_LP_EN |
467 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
468
469 /* Clear delay line clock power up */
470 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
471 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
472 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
473
474 /*
475 * Enable persistence mode to avoid LP XTAL resetting when
476 * SHRD_HW_RST is applied in S3.
477 */
478 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
479 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
480
481 /*
482 * Clear "initialization complete" bit to move adapter from
483 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
484 */
6dece0e9 485 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
a812cba9
AB		 486
487 /* Activates XTAL resources monitor */
488 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
489 CSR_MONITOR_XTAL_RESOURCES);
490
491 /* Release XTAL ON request */
492 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
493 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
494 udelay(10);
495
496 /* Release APMG XTAL */
497 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
498 apmg_xtal_cfg_reg &
499 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
500}
501
e8c8935e 502void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 503{
e8c8935e 504 int ret;
cc56feb2
EG		 505
506 /* stop device's busmaster DMA activity */
6dece0e9 507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
cc56feb2 508
6dece0e9
LC		 509 ret = iwl_poll_bit(trans, CSR_RESET,
510 CSR_RESET_REG_FLAG_MASTER_DISABLED,
511 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 512 if (ret < 0)
cc56feb2
EG		 513 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
514
515 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 516}
517
b7aaeae4 518static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 519{
520 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
521
b7aaeae4
EG		 522 if (op_mode_leave) {
523 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
524 iwl_pcie_apm_init(trans);
525
526 /* inform ME that we are leaving */
286ca8eb 527 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
b7aaeae4
EG		 528 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
529 APMG_PCIDEV_STT_VAL_WAKE_ME);
286ca8eb 530 else if (trans->trans_cfg->device_family >=
79b6c8fe 531 IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 532 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
533 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 534 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
535 CSR_HW_IF_CONFIG_REG_PREPARE |
536 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 537 mdelay(1);
538 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
539 CSR_RESET_LINK_PWR_MGMT_DISABLED);
540 }
b7aaeae4
EG		 541 mdelay(5);
542 }
543
eb7ff77e 544 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 545
546 /* Stop device's DMA activity */
7afe3705 547 iwl_pcie_apm_stop_master(trans);
cc56feb2 548
a812cba9
AB		 549 if (trans->cfg->lp_xtal_workaround) {
550 iwl_pcie_apm_lp_xtal_enable(trans);
551 return;
552 }
553
870c2a11 554 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 555
556 /*
557 * Clear "initialization complete" bit to move adapter from
558 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
559 */
6dece0e9 560 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
cc56feb2
EG		 561}
562
7afe3705 563static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 564{
7b11488f 565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 566 int ret;
392f8b78
EG		 567
568 /* nic_init */
7b70bd63 569 spin_lock(&trans_pcie->irq_lock);
52b6e168 570 ret = iwl_pcie_apm_init(trans);
7b70bd63 571 spin_unlock(&trans_pcie->irq_lock);
392f8b78 572
52b6e168
EG		 573 if (ret)
574 return ret;
575
95411d04 576 iwl_pcie_set_pwr(trans, false);
392f8b78 577
ecdb975c 578 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 579
580 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 581 iwl_pcie_rx_init(trans);
392f8b78
EG		 582
583 /* Allocate or reset and init all Tx and Command queues */
f02831be 584 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 585 return -ENOMEM;
586
286ca8eb 587 if (trans->trans_cfg->base_params->shadow_reg_enable) {
392f8b78 588 /* enable shadow regs in HW */
20d3b647 589 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 590 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 591 }
592
392f8b78
EG		 593 return 0;
594}
595
596#define HW_READY_TIMEOUT (50)
597
598/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 599static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 600{
601 int ret;
602
1042db2a 603 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 604 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 605
606 /* See if we got it */
1042db2a 607 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 608 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
610 HW_READY_TIMEOUT);
392f8b78 611
6a08f514
EG		 612 if (ret >= 0)
613 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
614
6d8f6eeb 615 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 616 return ret;
617}
618
619/* Note: returns standard 0/-ERROR code */
eda50cde 620int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 621{
622 int ret;
289e5501 623 int t = 0;
501fd989 624 int iter;
392f8b78 625
6d8f6eeb 626 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 627
7afe3705 628 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 629 /* If the card is ready, exit 0 */
392f8b78
EG		 630 if (ret >= 0)
631 return 0;
632
c9fdec9f
EG		 633 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
634 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 635 usleep_range(1000, 2000);
c9fdec9f 636
501fd989
EG		 637 for (iter = 0; iter < 10; iter++) {
638 /* If HW is not ready, prepare the conditions to check again */
639 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
640 CSR_HW_IF_CONFIG_REG_PREPARE);
641
642 do {
643 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 644 if (ret >= 0)
645 return 0;
392f8b78 646
501fd989
EG		 647 usleep_range(200, 1000);
648 t += 200;
649 } while (t < 150000);
650 msleep(25);
651 }
392f8b78 652
7f2ac8fb 653 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 654
392f8b78
EG		 655 return ret;
656}
657
cf614297
EG		 658/*
659 * ucode
660 */
564cdce7
SS		 661static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
662 u32 dst_addr, dma_addr_t phy_addr,
663 u32 byte_cnt)
cf614297 664{
bac842da
EG		 665 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
666 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
667
668 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
669 dst_addr);
670
671 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
672 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
673
674 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
675 (iwl_get_dma_hi_addr(phy_addr)
676 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
677
678 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
679 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
680 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
681 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
682
683 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
684 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
686 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 687}
688
564cdce7
SS		 689static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
690 u32 dst_addr, dma_addr_t phy_addr,
691 u32 byte_cnt)
692{
693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
694 unsigned long flags;
695 int ret;
696
697 trans_pcie->ucode_write_complete = false;
698
699 if (!iwl_trans_grab_nic_access(trans, &flags))
700 return -EIO;
701
eda50cde
SS		 702 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
703 byte_cnt);
bac842da 704 iwl_trans_release_nic_access(trans, &flags);
cf614297 705
13df1aab
JB		 706 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
707 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 708 if (!ret) {
83f84d7b 709 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 710 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 711 return -ETIMEDOUT;
712 }
713
714 return 0;
715}
716
7afe3705 717static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 718 const struct fw_desc *section)
cf614297 719{
83f84d7b
JB		 720 u8 *v_addr;
721 dma_addr_t p_addr;
baa21e83 722 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 723 int ret = 0;
724
83f84d7b
JB		 725 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
726 section_num);
727
c571573a
EG		 728 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
729 GFP_KERNEL | __GFP_NOWARN);
730 if (!v_addr) {
731 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
732 chunk_sz = PAGE_SIZE;
733 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
734 &p_addr, GFP_KERNEL);
735 if (!v_addr)
736 return -ENOMEM;
737 }
83f84d7b 738
c571573a 739 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 740 u32 copy_size, dst_addr;
741 bool extended_addr = false;
83f84d7b 742
c571573a 743 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 744 dst_addr = section->offset + offset;
745
746 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
747 dst_addr <= IWL_FW_MEM_EXTENDED_END)
748 extended_addr = true;
749
750 if (extended_addr)
751 iwl_set_bits_prph(trans, LMPM_CHICK,
752 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 753
83f84d7b 754 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 755 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
756 copy_size);
757
758 if (extended_addr)
759 iwl_clear_bits_prph(trans, LMPM_CHICK,
760 LMPM_CHICK_EXTENDED_ADDR_SPACE);
761
83f84d7b
JB		 762 if (ret) {
763 IWL_ERR(trans,
764 "Could not load the [%d] uCode section\n",
765 section_num);
766 break;
6dfa8d01 767 }
83f84d7b
JB		 768 }
769
c571573a 770 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 771 return ret;
772}
773
5dd9c68a
EG		 774static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
775 const struct fw_img *image,
776 int cpu,
777 int *first_ucode_section)
e2d6f4e7
EH		 778{
779 int shift_param;
dcab8ecd
EH		 780 int i, ret = 0, sec_num = 0x1;
781 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 782
783 if (cpu == 1) {
784 shift_param = 0;
034846cf 785 *first_ucode_section = 0;
e2d6f4e7
EH		 786 } else {
787 shift_param = 16;
034846cf 788 (*first_ucode_section)++;
e2d6f4e7
EH		 789 }
790
eef187a7 791 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 792 last_read_idx = i;
793
a6c4fb44
MG		 794 /*
795 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
796 * CPU1 to CPU2.
797 * PAGING_SEPARATOR_SECTION delimiter - separate between
798 * CPU2 non paged to CPU2 paging sec.
799 */
034846cf 800 if (!image->sec[i].data ||
a6c4fb44
MG		 801 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
802 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 803 IWL_DEBUG_FW(trans,
804 "Break since Data not valid or Empty section, sec = %d\n",
805 i);
189fa2fa 806 break;
034846cf
EH		 807 }
808
189fa2fa
EH		 809 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
810 if (ret)
811 return ret;
dcab8ecd 812
d6a2c5c7 813 /* Notify ucode of loaded section number and status */
eda50cde
SS		 814 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
815 val = val | (sec_num << shift_param);
816 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
817
dcab8ecd 818 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 819 }
820
034846cf
EH		 821 *first_ucode_section = last_read_idx;
822
2aabdbdc
EG		 823 iwl_enable_interrupts(trans);
824
286ca8eb 825 if (trans->trans_cfg->use_tfh) {
d6a2c5c7
SS		 826 if (cpu == 1)
827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
828 0xFFFF);
829 else
830 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
831 0xFFFFFFFF);
832 } else {
833 if (cpu == 1)
834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
835 0xFFFF);
836 else
837 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
838 0xFFFFFFFF);
839 }
afb88917 840
189fa2fa
EH		 841 return 0;
842}
e2d6f4e7 843
189fa2fa
EH		 844static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
845 const struct fw_img *image,
034846cf
EH		 846 int cpu,
847 int *first_ucode_section)
189fa2fa 848{
189fa2fa 849 int i, ret = 0;
034846cf 850 u32 last_read_idx = 0;
189fa2fa 851
3ce4a038 852 if (cpu == 1)
034846cf 853 *first_ucode_section = 0;
3ce4a038 854 else
034846cf 855 (*first_ucode_section)++;
189fa2fa 856
eef187a7 857 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 858 last_read_idx = i;
859
a6c4fb44
MG		 860 /*
861 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
862 * CPU1 to CPU2.
863 * PAGING_SEPARATOR_SECTION delimiter - separate between
864 * CPU2 non paged to CPU2 paging sec.
865 */
034846cf 866 if (!image->sec[i].data ||
a6c4fb44
MG		 867 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
868 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 869 IWL_DEBUG_FW(trans,
870 "Break since Data not valid or Empty section, sec = %d\n",
871 i);
189fa2fa 872 break;
034846cf
EH		 873 }
874
189fa2fa
EH		 875 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
876 if (ret)
877 return ret;
e2d6f4e7
EH		 878 }
879
034846cf
EH		 880 *first_ucode_section = last_read_idx;
881
e2d6f4e7
EH		 882 return 0;
883}
884
593fae3e
SM		 885static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
886{
887 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
888 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
889 &trans->dbg.fw_mon_cfg[alloc_id];
890 struct iwl_dram_data *frag;
891
892 if (!iwl_trans_dbg_ini_valid(trans))
893 return;
894
895 if (le32_to_cpu(fw_mon_cfg->buf_location) ==
896 IWL_FW_INI_LOCATION_SRAM_PATH) {
897 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
898 /* set sram monitor by enabling bit 7 */
899 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
900 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
901
902 return;
903 }
904
905 if (le32_to_cpu(fw_mon_cfg->buf_location) !=
906 IWL_FW_INI_LOCATION_DRAM_PATH ||
907 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
908 return;
909
910 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
911
912 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
913 alloc_id);
914
915 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
916 frag->physical >> MON_BUFF_SHIFT_VER2);
917 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
918 (frag->physical + frag->size - 256) >>
919 MON_BUFF_SHIFT_VER2);
920}
921
c9be849d 922void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 923{
91c28b83 924 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
69f0e505 925 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
09e350f7
LK		 926 int i;
927
a1af4c48 928 if (iwl_trans_dbg_ini_valid(trans)) {
593fae3e 929 iwl_pcie_apply_destination_ini(trans);
7a14c23d
SS		 930 return;
931 }
932
09e350f7
LK		 933 IWL_INFO(trans, "Applying debug destination %s\n",
934 get_fw_dbg_mode_string(dest->monitor_mode));
935
936 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 937 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 938 else
939 IWL_WARN(trans, "PCI should have external buffer debug\n");
940
91c28b83 941 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
09e350f7
LK		 942 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
943 u32 val = le32_to_cpu(dest->reg_ops[i].val);
944
945 switch (dest->reg_ops[i].op) {
946 case CSR_ASSIGN:
947 iwl_write32(trans, addr, val);
948 break;
949 case CSR_SETBIT:
950 iwl_set_bit(trans, addr, BIT(val));
951 break;
952 case CSR_CLEARBIT:
953 iwl_clear_bit(trans, addr, BIT(val));
954 break;
955 case PRPH_ASSIGN:
956 iwl_write_prph(trans, addr, val);
957 break;
958 case PRPH_SETBIT:
959 iwl_set_bits_prph(trans, addr, BIT(val));
960 break;
961 case PRPH_CLEARBIT:
962 iwl_clear_bits_prph(trans, addr, BIT(val));
963 break;
869f3b15
HD		 964 case PRPH_BLOCKBIT:
965 if (iwl_read_prph(trans, addr) & BIT(val)) {
966 IWL_ERR(trans,
967 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
968 val, addr);
969 goto monitor;
970 }
971 break;
09e350f7
LK		 972 default:
973 IWL_ERR(trans, "FW debug - unknown OP %d\n",
974 dest->reg_ops[i].op);
975 break;
976 }
977 }
978
869f3b15 979monitor:
69f0e505 980 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
09e350f7 981 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
69f0e505 982 fw_mon->physical >> dest->base_shift);
286ca8eb 983 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 984 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 985 (fw_mon->physical + fw_mon->size -
986 256) >> dest->end_shift);
62d7476d
EG		 987 else
988 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 989 (fw_mon->physical + fw_mon->size) >>
990 dest->end_shift);
09e350f7
LK		 991 }
992}
993
7afe3705 994static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 995 const struct fw_img *image)
cf614297 996{
189fa2fa 997 int ret = 0;
034846cf 998 int first_ucode_section;
cf614297 999
dcab8ecd 1000 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 1001 image->is_dual_cpus ? "Dual" : "Single");
1002
dcab8ecd
EH		 1003 /* load to FW the binary non secured sections of CPU1 */
1004 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1005 if (ret)
1006 return ret;
e2d6f4e7
EH		 1007
1008 if (image->is_dual_cpus) {
189fa2fa
EH		 1009 /* set CPU2 header address */
1010 iwl_write_prph(trans,
1011 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1012 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1013
189fa2fa 1014 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1015 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1016 &first_ucode_section);
189fa2fa
EH		 1017 if (ret)
1018 return ret;
e2d6f4e7 1019 }
cf614297 1020
9efab1ad 1021 if (iwl_pcie_dbg_on(trans))
09e350f7 1022 iwl_pcie_apply_destination(trans);
c2d20201 1023
2aabdbdc
EG		 1024 iwl_enable_interrupts(trans);
1025
e12ba844 1026 /* release CPU reset */
5dd9c68a 1027 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1028
dcab8ecd
EH		 1029 return 0;
1030}
189fa2fa 1031
5dd9c68a
EG		 1032static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1033 const struct fw_img *image)
dcab8ecd
EH		 1034{
1035 int ret = 0;
1036 int first_ucode_section;
dcab8ecd
EH		 1037
1038 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1039 image->is_dual_cpus ? "Dual" : "Single");
1040
7a14c23d 1041 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 1042 iwl_pcie_apply_destination(trans);
1043
82ea7966
SS		 1044 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1045 iwl_read_prph(trans, WFPM_GP2));
1046
1047 /*
1048 * Set default value. On resume reading the values that were
1049 * zeored can provide debug data on the resume flow.
1050 * This is for debugging only and has no functional impact.
1051 */
1052 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1053
dcab8ecd
EH		 1054 /* configure the ucode to be ready to get the secured image */
1055 /* release CPU reset */
1056 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1057
1058 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1059 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1060 &first_ucode_section);
dcab8ecd
EH		 1061 if (ret)
1062 return ret;
1063
1064 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1065 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1066 &first_ucode_section);
cf614297
EG		 1067}
1068
9ad8fd0b 1069bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1070{
326477e4 1071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1072 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1073 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1074 bool report;
727c02df 1075
326477e4
JB		 1076 if (hw_rfkill) {
1077 set_bit(STATUS_RFKILL_HW, &trans->status);
1078 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1079 } else {
1080 clear_bit(STATUS_RFKILL_HW, &trans->status);
1081 if (trans_pcie->opmode_down)
1082 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083 }
1084
1085 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1086
326477e4
JB		 1087 if (prev != report)
1088 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1089
1090 return hw_rfkill;
1091}
1092
7ca00409
HD		 1093struct iwl_causes_list {
1094 u32 cause_num;
1095 u32 mask_reg;
1096 u8 addr;
1097};
1098
1099static struct iwl_causes_list causes_list[] = {
1100 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1101 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1102 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1103 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1104 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1105 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
ff911dca 1106 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12},
7ca00409
HD		 1107 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1108 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1109 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1110 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1111 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1112 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1113 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1114 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1115};
1116
1117static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1118{
1119 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1120 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
3681021f
JB		 1121 int i, arr_size = ARRAY_SIZE(causes_list);
1122 struct iwl_causes_list *causes = causes_list;
7ca00409
HD		 1123
1124 /*
1125 * Access all non RX causes and map them to the default irq.
1126 * In case we are missing at least one interrupt vector,
1127 * the first interrupt vector will serve non-RX and FBQ causes.
1128 */
9b58419e 1129 for (i = 0; i < arr_size; i++) {
9b58419e
GBA		 1130 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1131 iwl_clear_bit(trans, causes[i].mask_reg,
1132 causes[i].cause_num);
7ca00409
HD		 1133 }
1134}
1135
1136static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1137{
1138 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1139 u32 offset =
1140 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1141 u32 val, idx;
1142
1143 /*
1144 * The first RX queue - fallback queue, which is designated for
1145 * management frame, command responses etc, is always mapped to the
1146 * first interrupt vector. The other RX queues are mapped to
1147 * the other (N - 2) interrupt vectors.
1148 */
1149 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1150 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1151 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1152 MSIX_FH_INT_CAUSES_Q(idx - offset));
1153 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1154 }
1155 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1156
1157 val = MSIX_FH_INT_CAUSES_Q(0);
1158 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1159 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1160 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1161
1162 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1163 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1164}
1165
77c09bc8 1166void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1167{
1168 struct iwl_trans *trans = trans_pcie->trans;
1169
1170 if (!trans_pcie->msix_enabled) {
286ca8eb 1171 if (trans->trans_cfg->mq_rx_supported &&
d7270d61 1172 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1173 iwl_write_umac_prph(trans, UREG_CHICK,
1174 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1175 return;
1176 }
d7270d61
HD		 1177 /*
1178 * The IVAR table needs to be configured again after reset,
1179 * but if the device is disabled, we can't write to
1180 * prph.
1181 */
1182 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1183 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1184
1185 /*
1186 * Each cause from the causes list above and the RX causes is
1187 * represented as a byte in the IVAR table. The first nibble
1188 * represents the bound interrupt vector of the cause, the second
1189 * represents no auto clear for this cause. This will be set if its
1190 * interrupt vector is bound to serve other causes.
1191 */
1192 iwl_pcie_map_rx_causes(trans);
1193
1194 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1195}
1196
1197static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1198{
1199 struct iwl_trans *trans = trans_pcie->trans;
1200
1201 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1202
83730058
HD		 1203 if (!trans_pcie->msix_enabled)
1204 return;
1205
1206 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1207 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1208 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1209 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1210}
1211
bab3cb92 1212static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1213{
43e58856 1214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1215
fa9f3281
EG		 1216 lockdep_assert_held(&trans_pcie->mutex);
1217
1218 if (trans_pcie->is_down)
1219 return;
1220
1221 trans_pcie->is_down = true;
1222
43e58856 1223 /* tell the device to stop sending interrupts */
ae2c30bf 1224 iwl_disable_interrupts(trans);
ae2c30bf 1225
ab6cf8e8 1226 /* device going down, Stop using ICT table */
990aa6d7 1227 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1228
1229 /*
1230 * If a HW restart happens during firmware loading,
1231 * then the firmware loading might call this function
1232 * and later it might be called again due to the
1233 * restart. So don't process again if the device is
1234 * already dead.
1235 */
31b8b343 1236 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1237 IWL_DEBUG_INFO(trans,
1238 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1239 iwl_pcie_tx_stop(trans);
9805c446 1240 iwl_pcie_rx_stop(trans);
6379103e 1241
ab6cf8e8 1242 /* Power-down device's busmaster DMA clocks */
95411d04 1243 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1244 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1245 APMG_CLK_VAL_DMA_CLK_RQT);
1246 udelay(5);
1247 }
ab6cf8e8
EG		 1248 }
1249
1250 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1251 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1252 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1253
1254 /* Stop the device, and put it in low power state */
b7aaeae4 1255 iwl_pcie_apm_stop(trans, false);
43e58856 1256
870c2a11 1257 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1258
f4a1f04a
GBA		 1259 /*
1260 * Upon stop, the IVAR table gets erased, so msi-x won't
1261 * work. This causes a bug in RF-KILL flows, since the interrupt
1262 * that enables radio won't fire on the correct irq, and the
1263 * driver won't be able to handle the interrupt.
1264 * Configure the IVAR table again after reset.
1265 */
1266 iwl_pcie_conf_msix_hw(trans_pcie);
1267
03d6c3b0
EG		 1268 /*
1269 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1270 * This is a bug in certain verions of the hardware.
1271 * Certain devices also keep sending HW RF kill interrupt all
1272 * the time, unless the interrupt is ACKed even if the interrupt
1273 * should be masked. Re-ACK all the interrupts here.
43e58856 1274 */
43e58856 1275 iwl_disable_interrupts(trans);
43e58856 1276
74fda971 1277 /* clear all status bits */
eb7ff77e
AN		 1278 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1279 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1280 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1281
1282 /*
1283 * Even if we stop the HW, we still want the RF kill
1284 * interrupt
1285 */
1286 iwl_enable_rfkill_int(trans);
1287
a6bd005f 1288 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1289 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1290}
1291
eda50cde 1292void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1293{
1294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1295
1296 if (trans_pcie->msix_enabled) {
1297 int i;
1298
496d83ca 1299 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1300 synchronize_irq(trans_pcie->msix_entries[i].vector);
1301 } else {
1302 synchronize_irq(trans_pcie->pci_dev->irq);
1303 }
1304}
1305
a6bd005f
EG		 1306static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1307 const struct fw_img *fw, bool run_in_rfkill)
1308{
1309 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1310 bool hw_rfkill;
1311 int ret;
1312
1313 /* This may fail if AMT took ownership of the device */
1314 if (iwl_pcie_prepare_card_hw(trans)) {
1315 IWL_WARN(trans, "Exit HW not ready\n");
1316 ret = -EIO;
1317 goto out;
1318 }
1319
1320 iwl_enable_rfkill_int(trans);
1321
1322 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1323
1324 /*
1325 * We enabled the RF-Kill interrupt and the handler may very
1326 * well be running. Disable the interrupts to make sure no other
1327 * interrupt can be fired.
1328 */
1329 iwl_disable_interrupts(trans);
1330
1331 /* Make sure it finished running */
2e5d4a8f 1332 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1333
1334 mutex_lock(&trans_pcie->mutex);
1335
1336 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1337 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1338 if (hw_rfkill && !run_in_rfkill) {
1339 ret = -ERFKILL;
1340 goto out;
1341 }
1342
1343 /* Someone called stop_device, don't try to start_fw */
1344 if (trans_pcie->is_down) {
1345 IWL_WARN(trans,
1346 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1347 ret = -EIO;
a6bd005f
EG		 1348 goto out;
1349 }
1350
1351 /* make sure rfkill handshake bits are cleared */
1352 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1353 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1354 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1355
1356 /* clear (again), then enable host interrupts */
1357 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1358
1359 ret = iwl_pcie_nic_init(trans);
1360 if (ret) {
1361 IWL_ERR(trans, "Unable to init nic\n");
1362 goto out;
1363 }
1364
1365 /*
1366 * Now, we load the firmware and don't want to be interrupted, even
1367 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1368 * FH_TX interrupt which is needed to load the firmware). If the
1369 * RF-Kill switch is toggled, we will find out after having loaded
1370 * the firmware and return the proper value to the caller.
1371 */
1372 iwl_enable_fw_load_int(trans);
1373
1374 /* really make sure rfkill handshake bits are cleared */
1375 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1376 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1377
1378 /* Load the given image to the HW */
286ca8eb 1379 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1380 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1381 else
1382 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1383
1384 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1385 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1386 if (hw_rfkill && !run_in_rfkill)
1387 ret = -ERFKILL;
1388
1389out:
1390 mutex_unlock(&trans_pcie->mutex);
1391 return ret;
1392}
1393
1394static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1395{
1396 iwl_pcie_reset_ict(trans);
1397 iwl_pcie_tx_start(trans, scd_addr);
1398}
1399
326477e4
JB		 1400void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1401 bool was_in_rfkill)
1402{
1403 bool hw_rfkill;
1404
1405 /*
1406 * Check again since the RF kill state may have changed while
1407 * all the interrupts were disabled, in this case we couldn't
1408 * receive the RF kill interrupt and update the state in the
1409 * op_mode.
1410 * Don't call the op_mode if the rkfill state hasn't changed.
1411 * This allows the op_mode to call stop_device from the rfkill
1412 * notification without endless recursion. Under very rare
1413 * circumstances, we might have a small recursion if the rfkill
1414 * state changed exactly now while we were called from stop_device.
1415 * This is very unlikely but can happen and is supported.
1416 */
1417 hw_rfkill = iwl_is_rfkill_set(trans);
1418 if (hw_rfkill) {
1419 set_bit(STATUS_RFKILL_HW, &trans->status);
1420 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1421 } else {
1422 clear_bit(STATUS_RFKILL_HW, &trans->status);
1423 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1424 }
1425 if (hw_rfkill != was_in_rfkill)
1426 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1427}
1428
bab3cb92 1429static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
fa9f3281
EG		 1430{
1431 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1432 bool was_in_rfkill;
fa9f3281
EG		 1433
1434 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1435 trans_pcie->opmode_down = true;
1436 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
bab3cb92 1437 _iwl_trans_pcie_stop_device(trans);
326477e4 1438 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1439 mutex_unlock(&trans_pcie->mutex);
1440}
1441
14cfca71
JB		 1442void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1443{
fa9f3281
EG		 1444 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1445 IWL_TRANS_GET_PCIE_TRANS(trans);
1446
1447 lockdep_assert_held(&trans_pcie->mutex);
1448
326477e4
JB		 1449 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1450 state ? "disabled" : "enabled");
77c09bc8 1451 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
286ca8eb 1452 if (trans->trans_cfg->gen2)
bab3cb92 1453 _iwl_trans_pcie_gen2_stop_device(trans);
77c09bc8 1454 else
bab3cb92 1455 _iwl_trans_pcie_stop_device(trans);
77c09bc8 1456 }
ab6cf8e8
EG		 1457}
1458
e5f3f215
HD		 1459void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1460 bool test, bool reset)
2dd4f9f7 1461{
2dd4f9f7 1462 iwl_disable_interrupts(trans);
debff618
JB		 1463
1464 /*
1465 * in testing mode, the host stays awake and the
1466 * hardware won't be reset (not even partially)
1467 */
1468 if (test)
1469 return;
1470
ddaf5a5b
JB		 1471 iwl_pcie_disable_ict(trans);
1472
2e5d4a8f 1473 iwl_pcie_synchronize_irqs(trans);
33b56af1 1474
2dd4f9f7 1475 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 1476 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1477 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
ddaf5a5b 1478
23ae6128 1479 if (reset) {
6dfb36c8
EP		 1480 /*
1481 * reset TX queues -- some of their registers reset during S3
1482 * so if we don't reset everything here the D3 image would try
1483 * to execute some invalid memory upon resume
1484 */
1485 iwl_trans_pcie_tx_reset(trans);
1486 }
ddaf5a5b
JB		 1487
1488 iwl_pcie_set_pwr(trans, true);
1489}
1490
e5f3f215
HD		 1491static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1492 bool reset)
1493{
1494 int ret;
1495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1496
771db3a1 1497 if (!reset)
e5f3f215
HD		 1498 /* Enable persistence mode to avoid reset */
1499 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1500 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
e5f3f215
HD		 1501
1502 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1503 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1504 UREG_DOORBELL_TO_ISR6_SUSPEND);
1505
1506 ret = wait_event_timeout(trans_pcie->sx_waitq,
1507 trans_pcie->sx_complete, 2 * HZ);
1508 /*
1509 * Invalidate it toward resume.
1510 */
1511 trans_pcie->sx_complete = false;
1512
1513 if (!ret) {
1514 IWL_ERR(trans, "Timeout entering D3\n");
1515 return -ETIMEDOUT;
1516 }
1517 }
1518 iwl_pcie_d3_complete_suspend(trans, test, reset);
1519
1520 return 0;
1521}
1522
ddaf5a5b 1523static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1524 enum iwl_d3_status *status,
23ae6128 1525 bool test, bool reset)
ddaf5a5b 1526{
d7270d61 1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1528 u32 val;
1529 int ret;
1530
debff618
JB		 1531 if (test) {
1532 iwl_enable_interrupts(trans);
1533 *status = IWL_D3_STATUS_ALIVE;
e5f3f215 1534 goto out;
debff618
JB		 1535 }
1536
a8cbb46f 1537 iwl_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 1538 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b 1539
7d34a7d7 1540 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 1541 if (ret)
ddaf5a5b 1542 return ret;
ddaf5a5b 1543
f98ad635
EG		 1544 /*
1545 * Reconfigure IVAR table in case of MSIX or reset ict table in
1546 * MSI mode since HW reset erased it.
1547 * Also enables interrupts - none will happen as
1548 * the device doesn't know we're waking it up, only when
1549 * the opmode actually tells it after this call.
1550 */
1551 iwl_pcie_conf_msix_hw(trans_pcie);
1552 if (!trans_pcie->msix_enabled)
1553 iwl_pcie_reset_ict(trans);
1554 iwl_enable_interrupts(trans);
1555
a3ead656
EG		 1556 iwl_pcie_set_pwr(trans, false);
1557
23ae6128 1558 if (!reset) {
6dfb36c8 1559 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1560 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6dfb36c8
EP		 1561 } else {
1562 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1563
6dfb36c8
EP		 1564 ret = iwl_pcie_rx_init(trans);
1565 if (ret) {
1566 IWL_ERR(trans,
1567 "Failed to resume the device (RX reset)\n");
1568 return ret;
1569 }
ddaf5a5b
JB		 1570 }
1571
82ea7966 1572 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1573 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1574
a3ead656
EG		 1575 val = iwl_read32(trans, CSR_RESET);
1576 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1577 *status = IWL_D3_STATUS_RESET;
1578 else
1579 *status = IWL_D3_STATUS_ALIVE;
1580
e5f3f215
HD		 1581out:
1582 if (*status == IWL_D3_STATUS_ALIVE &&
1583 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1584 trans_pcie->sx_complete = false;
1585 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1586 UREG_DOORBELL_TO_ISR6_RESUME);
1587
1588 ret = wait_event_timeout(trans_pcie->sx_waitq,
1589 trans_pcie->sx_complete, 2 * HZ);
1590 /*
1591 * Invalidate it toward next suspend.
1592 */
1593 trans_pcie->sx_complete = false;
1594
1595 if (!ret) {
1596 IWL_ERR(trans, "Timeout exiting D3\n");
1597 return -ETIMEDOUT;
1598 }
1599 }
ddaf5a5b 1600 return 0;
2dd4f9f7
JB		 1601}
1602
0c18714a
LC		 1603static void
1604iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1605 struct iwl_trans *trans,
1606 const struct iwl_cfg_trans_params *cfg_trans)
2e5d4a8f
HD		 1607{
1608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1609 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1610 u16 pci_cmd;
0cd38f4d 1611 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
2e5d4a8f 1612
0c18714a 1613 if (!cfg_trans->mq_rx_supported)
06f4b081
SS		 1614 goto enable_msi;
1615
0cd38f4d
MG		 1616 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1617 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1618
1619 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
06f4b081
SS		 1620 for (i = 0; i < max_irqs; i++)
1621 trans_pcie->msix_entries[i].entry = i;
496d83ca 1622
06f4b081
SS		 1623 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1624 MSIX_MIN_INTERRUPT_VECTORS,
1625 max_irqs);
1626 if (num_irqs < 0) {
2e5d4a8f 1627 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1628 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1629 num_irqs);
1630 goto enable_msi;
1631 }
1632 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1633
06f4b081
SS		 1634 IWL_DEBUG_INFO(trans,
1635 "MSI-X enabled. %d interrupt vectors were allocated\n",
1636 num_irqs);
1637
1638 /*
1639 * In case the OS provides fewer interrupts than requested, different
1640 * causes will share the same interrupt vector as follows:
1641 * One interrupt less: non rx causes shared with FBQ.
1642 * Two interrupts less: non rx causes shared with FBQ and RSS.
1643 * More than two interrupts: we will use fewer RSS queues.
1644 */
ab1068d6 1645 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1646 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1647 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1648 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1649 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1650 trans_pcie->trans->num_rx_queues = num_irqs;
1651 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1652 } else {
1653 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1654 }
ab1068d6 1655 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1656
06f4b081
SS		 1657 trans_pcie->alloc_vecs = num_irqs;
1658 trans_pcie->msix_enabled = true;
1659 return;
1660
1661enable_msi:
1662 ret = pci_enable_msi(pdev);
1663 if (ret) {
1664 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1665 /* enable rfkill interrupt: hw bug w/a */
1666 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1667 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1668 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1669 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1670 }
1671 }
1672}
1673
7c8d91eb
HD		 1674static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1675{
1676 int iter_rx_q, i, ret, cpu, offset;
1677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1678
1679 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1680 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1681 offset = 1 + i;
1682 for (; i < iter_rx_q ; i++) {
1683 /*
1684 * Get the cpu prior to the place to search
1685 * (i.e. return will be > i - 1).
1686 */
1687 cpu = cpumask_next(i - offset, cpu_online_mask);
1688 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1689 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1690 &trans_pcie->affinity_mask[i]);
1691 if (ret)
1692 IWL_ERR(trans_pcie->trans,
1693 "Failed to set affinity mask for IRQ %d\n",
1694 i);
1695 }
1696}
1697
2e5d4a8f
HD		 1698static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1699 struct iwl_trans_pcie *trans_pcie)
1700{
496d83ca 1701 int i;
2e5d4a8f 1702
496d83ca 1703 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1704 int ret;
5a41a86c 1705 struct msix_entry *msix_entry;
64fa3aff
SD		 1706 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1707
1708 if (!qname)
1709 return -ENOMEM;
5a41a86c
SD		 1710
1711 msix_entry = &trans_pcie->msix_entries[i];
1712 ret = devm_request_threaded_irq(&pdev->dev,
1713 msix_entry->vector,
1714 iwl_pcie_msix_isr,
1715 (i == trans_pcie->def_irq) ?
1716 iwl_pcie_irq_msix_handler :
1717 iwl_pcie_irq_rx_msix_handler,
1718 IRQF_SHARED,
64fa3aff 1719 qname,
5a41a86c 1720 msix_entry);
2e5d4a8f 1721 if (ret) {
2e5d4a8f
HD		 1722 IWL_ERR(trans_pcie->trans,
1723 "Error allocating IRQ %d\n", i);
5a41a86c 1724
2e5d4a8f
HD		 1725 return ret;
1726 }
1727 }
7c8d91eb 1728 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1729
1730 return 0;
1731}
1732
44f61b5c 1733static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
e6bb4c9c 1734{
44f61b5c 1735 u32 hpm, wprot;
fa9f3281 1736
286ca8eb 1737 switch (trans->trans_cfg->device_family) {
44f61b5c
SM		 1738 case IWL_DEVICE_FAMILY_9000:
1739 wprot = PREG_PRPH_WPROT_9000;
1740 break;
1741 case IWL_DEVICE_FAMILY_22000:
1742 wprot = PREG_PRPH_WPROT_22000;
1743 break;
1744 default:
1745 return 0;
ebb7678d 1746 }
a6c684ee 1747
ea695b7c 1748 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
8954e1eb 1749 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
44f61b5c 1750 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
ea695b7c 1751
44f61b5c 1752 if (wprot_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1753 IWL_ERR(trans,
1754 "Error, can not clear persistence bit\n");
1755 return -EPERM;
1756 }
ea695b7c
ST		 1757 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1758 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1759 }
1760
44f61b5c
SM		 1761 return 0;
1762}
1763
0df36b90
LC		 1764static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1765{
1766 int ret;
1767
1768 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1769 if (ret < 0)
1770 return ret;
1771
1772 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1773 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1774 udelay(20);
1775 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1776 HPM_HIPM_GEN_CFG_CR_PG_EN |
1777 HPM_HIPM_GEN_CFG_CR_SLP_EN);
1778 udelay(20);
1779 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1780 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1781
1782 iwl_trans_pcie_sw_reset(trans);
1783
1784 return 0;
1785}
1786
bab3cb92 1787static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
44f61b5c
SM		 1788{
1789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1790 int err;
1791
1792 lockdep_assert_held(&trans_pcie->mutex);
1793
1794 err = iwl_pcie_prepare_card_hw(trans);
1795 if (err) {
1796 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1797 return err;
1798 }
1799
1800 err = iwl_trans_pcie_clear_persistence_bit(trans);
1801 if (err)
1802 return err;
1803
870c2a11 1804 iwl_trans_pcie_sw_reset(trans);
2997494f 1805
0df36b90 1806 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
7897dfa2 1807 trans->trans_cfg->integrated) {
0df36b90
LC		 1808 err = iwl_pcie_gen2_force_power_gating(trans);
1809 if (err)
1810 return err;
1811 }
1812
52b6e168
EG		 1813 err = iwl_pcie_apm_init(trans);
1814 if (err)
1815 return err;
a6c684ee 1816
2e5d4a8f 1817 iwl_pcie_init_msix(trans_pcie);
83730058 1818
226c02ca
EG		 1819 /* From now on, the op_mode will be kept updated about RF kill state */
1820 iwl_enable_rfkill_int(trans);
1821
326477e4
JB		 1822 trans_pcie->opmode_down = false;
1823
fa9f3281
EG		 1824 /* Set is_down to false here so that...*/
1825 trans_pcie->is_down = false;
1826
727c02df 1827 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1828 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1829
a8b691e6 1830 return 0;
e6bb4c9c
EG		 1831}
1832
bab3cb92 1833static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
fa9f3281
EG		 1834{
1835 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1836 int ret;
1837
1838 mutex_lock(&trans_pcie->mutex);
bab3cb92 1839 ret = _iwl_trans_pcie_start_hw(trans);
fa9f3281
EG		 1840 mutex_unlock(&trans_pcie->mutex);
1841
1842 return ret;
1843}
1844
a4082843 1845static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1846{
20d3b647 1847 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1848
fa9f3281
EG		 1849 mutex_lock(&trans_pcie->mutex);
1850
a4082843 1851 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1852 iwl_disable_interrupts(trans);
ee7d737c 1853
b7aaeae4 1854 iwl_pcie_apm_stop(trans, true);
cc56feb2 1855
218733cf 1856 iwl_disable_interrupts(trans);
1df06bdc 1857
8d96bb61 1858 iwl_pcie_disable_ict(trans);
33b56af1 1859
fa9f3281 1860 mutex_unlock(&trans_pcie->mutex);
33b56af1 1861
2e5d4a8f 1862 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1863}
1864
03905495
EG		 1865static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1866{
05f5b97e 1867 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1868}
1869
1870static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1871{
05f5b97e 1872 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1873}
1874
1875static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1876{
05f5b97e 1877 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1878}
1879
84fb372c
SS		 1880static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1881{
3681021f 1882 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
84fb372c
SS		 1883 return 0x00FFFFFF;
1884 else
1885 return 0x000FFFFF;
1886}
1887
6a06b6c1
EG		 1888static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1889{
84fb372c
SS		 1890 u32 mask = iwl_trans_pcie_prph_msk(trans);
1891
f9477c17 1892 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1893 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1894 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1895}
1896
1897static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1898 u32 val)
1899{
84fb372c
SS		 1900 u32 mask = iwl_trans_pcie_prph_msk(trans);
1901
6a06b6c1 1902 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1903 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1904 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1905}
1906
c6f600fc 1907static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1908 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1909{
1910 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1911
4f4822b7
MG		 1912 trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1913 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1914 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
22852fad
MG		 1915 trans->txqs.page_offs = trans_cfg->cb_data_offs;
1916 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1917
d663ee73
JB		 1918 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1919 trans_pcie->n_no_reclaim_cmds = 0;
1920 else
1921 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1922 if (trans_pcie->n_no_reclaim_cmds)
1923 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1924 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1925
6c4fbcbc
EG		 1926 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1927 trans_pcie->rx_page_order =
1928 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
80084e35
JB		 1929 trans_pcie->rx_buf_bytes =
1930 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
cfdc20ef
JB		 1931 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1932 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1933 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
7c5ba4a8 1934
8e3b79f8 1935 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1936 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1937 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1938
39bdb17e
SD		 1939 trans->command_groups = trans_cfg->command_groups;
1940 trans->command_groups_size = trans_cfg->command_groups_size;
1941
f14d6b39
JB		 1942 /* Initialize NAPI here - it should be before registering to mac80211
1943 * in the opmode but after the HW struct is allocated.
1944 * As this function may be called again in some corner cases don't
1945 * do anything if NAPI was already initialized.
1946 */
bce97731 1947 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1948 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1949}
1950
d1ff5253 1951void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1952{
20d3b647 1953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1954 int i;
a42a1844 1955
2e5d4a8f 1956 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1957
286ca8eb 1958 if (trans->trans_cfg->gen2)
0cd1ad2d 1959 iwl_txq_gen2_tx_free(trans);
13a3a390
SS		 1960 else
1961 iwl_pcie_tx_free(trans);
9805c446 1962 iwl_pcie_rx_free(trans);
6379103e 1963
10a54d81
LC		 1964 if (trans_pcie->rba.alloc_wq) {
1965 destroy_workqueue(trans_pcie->rba.alloc_wq);
1966 trans_pcie->rba.alloc_wq = NULL;
1967 }
1968
2e5d4a8f 1969 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1970 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1971 irq_set_affinity_hint(
1972 trans_pcie->msix_entries[i].vector,
1973 NULL);
7c8d91eb 1974 }
2e5d4a8f 1975
2e5d4a8f
HD		 1976 trans_pcie->msix_enabled = false;
1977 } else {
2e5d4a8f 1978 iwl_pcie_free_ict(trans);
2e5d4a8f 1979 }
a42a1844 1980
c2d20201
EG		 1981 iwl_pcie_free_fw_monitor(trans);
1982
69725928
LC		 1983 if (trans_pcie->pnvm_dram.size)
1984 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
1985 trans_pcie->pnvm_dram.block,
1986 trans_pcie->pnvm_dram.physical);
1987
a2a57a35 1988 mutex_destroy(&trans_pcie->mutex);
7b501d10 1989 iwl_trans_free(trans);
34c1b7ba
EG		 1990}
1991
47107e84
DF		 1992static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1993{
47107e84 1994 if (state)
eb7ff77e 1995 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1996 else
eb7ff77e 1997 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1998}
1999
49564a80
LC		 2000struct iwl_trans_pcie_removal {
2001 struct pci_dev *pdev;
2002 struct work_struct work;
2003};
2004
2005static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2006{
2007 struct iwl_trans_pcie_removal *removal =
2008 container_of(wk, struct iwl_trans_pcie_removal, work);
2009 struct pci_dev *pdev = removal->pdev;
aba1e632 2010 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
49564a80
LC		 2011
2012 dev_err(&pdev->dev, "Device gone - attempting removal\n");
2013 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2014 pci_lock_rescan_remove();
2015 pci_dev_put(pdev);
2016 pci_stop_and_remove_bus_device(pdev);
2017 pci_unlock_rescan_remove();
2018
2019 kfree(removal);
2020 module_put(THIS_MODULE);
2021}
2022
23ba9340
EG		 2023static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2024 unsigned long *flags)
7a65d170
EG		 2025{
2026 int ret;
cfb4e624
JB		 2027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2028
2029 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 2030
fc8a350d 2031 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2032 goto out;
2033
7a65d170 2034 /* this bit wakes up the NIC */
e139dc4a 2035 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 2036 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
286ca8eb 2037 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 2038 udelay(2);
7a65d170
EG		 2039
2040 /*
2041 * These bits say the device is running, and should keep running for
2042 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2043 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 2044 * HW with volatile SRAM must save/restore contents to/from
2045 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 2046 * Each direction takes approximately 1/4 millisecond; with this
2047 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2048 * series of register accesses are expected (e.g. reading Event Log),
2049 * to keep device from sleeping.
2050 *
2051 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2052 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 2053 * is just for hardware register access; but GP1 MAC_SLEEP
2054 * check is a good idea before accessing the SRAM of HW with
2055 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2056 *
2057 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2058 * and do not save/restore SRAM when power cycling.
2059 */
2060 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 2061 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2062 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
7a65d170
EG		 2063 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2064 if (unlikely(ret < 0)) {
49564a80
LC		 2065 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2066
23ba9340
EG		 2067 WARN_ONCE(1,
2068 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2069 cntrl);
2070
2071 iwl_trans_pcie_dump_regs(trans);
2072
2073 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2074 struct iwl_trans_pcie_removal *removal;
2075
f60c9e59 2076 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
49564a80
LC		 2077 goto err;
2078
2079 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2080
2081 /*
2082 * get a module reference to avoid doing this
2083 * while unloading anyway and to avoid
2084 * scheduling a work with code that's being
2085 * removed.
2086 */
2087 if (!try_module_get(THIS_MODULE)) {
2088 IWL_ERR(trans,
2089 "Module is being unloaded - abort\n");
2090 goto err;
2091 }
2092
2093 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2094 if (!removal) {
2095 module_put(THIS_MODULE);
2096 goto err;
2097 }
2098 /*
2099 * we don't need to clear this flag, because
2100 * the trans will be freed and reallocated.
2101 */
f60c9e59 2102 set_bit(STATUS_TRANS_DEAD, &trans->status);
49564a80
LC		 2103
2104 removal->pdev = to_pci_dev(trans->dev);
2105 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2106 pci_dev_get(removal->pdev);
2107 schedule_work(&removal->work);
2108 } else {
2109 iwl_write32(trans, CSR_RESET,
2110 CSR_RESET_REG_FLAG_FORCE_NMI);
2111 }
2112
2113err:
23ba9340
EG		 2114 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2115 return false;
7a65d170
EG		 2116 }
2117
b9439491 2118out:
e56b04ef
LE		 2119 /*
2120 * Fool sparse by faking we release the lock - sparse will
2121 * track nic_access anyway.
2122 */
cfb4e624 2123 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2124 return true;
2125}
2126
e56b04ef
LE		 2127static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2128 unsigned long *flags)
7a65d170 2129{
cfb4e624 2130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2131
cfb4e624 2132 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2133
2134 /*
2135 * Fool sparse by faking we acquiring the lock - sparse will
2136 * track nic_access anyway.
2137 */
cfb4e624 2138 __acquire(&trans_pcie->reg_lock);
e56b04ef 2139
fc8a350d 2140 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2141 goto out;
2142
e139dc4a 2143 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 2144 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2145 /*
2146 * Above we read the CSR_GP_CNTRL register, which will flush
2147 * any previous writes, but we need the write that clears the
2148 * MAC_ACCESS_REQ bit to be performed before any other writes
2149 * scheduled on different CPUs (after we drop reg_lock).
2150 */
b9439491 2151out:
cfb4e624 2152 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2153}
2154
4fd442db
EG		 2155static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2156 void *buf, int dwords)
2157{
2158 unsigned long flags;
04516706 2159 int offs = 0;
4fd442db
EG		 2160 u32 *vals = buf;
2161
04516706
JB		 2162 while (offs < dwords) {
2163 /* limit the time we spin here under lock to 1/2s */
2164 ktime_t timeout = ktime_add_us(ktime_get(), 500 * USEC_PER_MSEC);
2165
2166 if (iwl_trans_grab_nic_access(trans, &flags)) {
2167 iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2168 addr + 4 * offs);
2169
2170 while (offs < dwords) {
2171 vals[offs] = iwl_read32(trans,
2172 HBUS_TARG_MEM_RDAT);
2173 offs++;
2174
2175 /* calling ktime_get is expensive so
2176 * do it once in 128 reads
2177 */
2178 if (offs % 128 == 0 && ktime_after(ktime_get(),
2179 timeout))
2180 break;
2181 }
2182 iwl_trans_release_nic_access(trans, &flags);
2183 } else {
2184 return -EBUSY;
2185 }
4fd442db 2186 }
04516706
JB		 2187
2188 return 0;
4fd442db
EG		 2189}
2190
2191static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2192 const void *buf, int dwords)
4fd442db
EG		 2193{
2194 unsigned long flags;
2195 int offs, ret = 0;
bf0fd5da 2196 const u32 *vals = buf;
4fd442db 2197
23ba9340 2198 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2199 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2200 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2201 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2202 vals ? vals[offs] : 0);
e56b04ef 2203 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2204 } else {
2205 ret = -EBUSY;
2206 }
4fd442db
EG		 2207 return ret;
2208}
7a65d170 2209
7f1fe1d4
LC		 2210static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2211 u32 *val)
2212{
2213 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2214 ofs, val);
2215}
2216
0cd58eaa
EG		 2217static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2218{
0cd58eaa
EG		 2219 int i;
2220
286ca8eb 2221 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
4f4822b7 2222 struct iwl_txq *txq = trans->txqs.txq[i];
0cd58eaa 2223
4f4822b7 2224 if (i == trans->txqs.cmd.q_id)
0cd58eaa
EG		 2225 continue;
2226
2227 spin_lock_bh(&txq->lock);
2228
2229 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2230 txq->block--;
2231 if (!txq->block) {
2232 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2233 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2234 }
2235 } else if (block) {
2236 txq->block++;
2237 }
2238
2239 spin_unlock_bh(&txq->lock);
2240 }
2241}
2242
5f178cd2
EG		 2243#define IWL_FLUSH_WAIT_MS 2000
2244
92536c96
SS		 2245static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2246 struct iwl_trans_rxq_dma_data *data)
2247{
2248 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2249
2250 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2251 return -EINVAL;
2252
2253 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2254 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2255 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2256 data->fr_bd_wid = 0;
2257
2258 return 0;
2259}
2260
d6d517b7 2261static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2262{
990aa6d7 2263 struct iwl_txq *txq;
5f178cd2 2264 unsigned long now = jiffies;
2ae48edc 2265 bool overflow_tx;
d6d517b7
SS		 2266 u8 wr_ptr;
2267
2b3fae66 2268 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2269 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2270 return -ENODEV;
2b3fae66 2271
4f4822b7 2272 if (!test_bit(txq_idx, trans->txqs.queue_used))
d6d517b7
SS		 2273 return -EINVAL;
2274
2275 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
4f4822b7 2276 txq = trans->txqs.txq[txq_idx];
2ae48edc
SS		 2277
2278 spin_lock_bh(&txq->lock);
2279 overflow_tx = txq->overflow_tx ||
2280 !skb_queue_empty(&txq->overflow_q);
2281 spin_unlock_bh(&txq->lock);
2282
6aa7de05 2283 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2284
2ae48edc
SS		 2285 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2286 overflow_tx) &&
d6d517b7
SS		 2287 !time_after(jiffies,
2288 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2289 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2290
2ae48edc
SS		 2291 /*
2292 * If write pointer moved during the wait, warn only
2293 * if the TX came from op mode. In case TX came from
2294 * trans layer (overflow TX) don't warn.
2295 */
2296 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2297 "WR pointer moved while flushing %d -> %d\n",
2298 wr_ptr, write_ptr))
2299 return -ETIMEDOUT;
2ae48edc
SS		 2300 wr_ptr = write_ptr;
2301
d6d517b7 2302 usleep_range(1000, 2000);
2ae48edc
SS		 2303
2304 spin_lock_bh(&txq->lock);
2305 overflow_tx = txq->overflow_tx ||
2306 !skb_queue_empty(&txq->overflow_q);
2307 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2308 }
2309
2310 if (txq->read_ptr != txq->write_ptr) {
2311 IWL_ERR(trans,
2312 "fail to flush all tx fifo queues Q %d\n", txq_idx);
0cd1ad2d 2313 iwl_txq_log_scd_error(trans, txq);
d6d517b7
SS		 2314 return -ETIMEDOUT;
2315 }
2316
2317 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2318
2319 return 0;
2320}
2321
2322static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2323{
d6d517b7 2324 int cnt;
5f178cd2
EG		 2325 int ret = 0;
2326
2327 /* waiting for all the tx frames complete might take a while */
79b6c8fe 2328 for (cnt = 0;
286ca8eb 2329 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2330 cnt++) {
fa1a91fd 2331
4f4822b7 2332 if (cnt == trans->txqs.cmd.q_id)
5f178cd2 2333 continue;
4f4822b7 2334 if (!test_bit(cnt, trans->txqs.queue_used))
3cafdbe6
EG		 2335 continue;
2336 if (!(BIT(cnt) & txq_bm))
2337 continue;
748fa67c 2338
d6d517b7
SS		 2339 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2340 if (ret)
5f178cd2 2341 break;
5f178cd2 2342 }
1c3fea82 2343
5f178cd2
EG		 2344 return ret;
2345}
2346
e139dc4a
LE		 2347static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2348 u32 mask, u32 value)
2349{
e56b04ef 2350 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2351 unsigned long flags;
2352
e56b04ef 2353 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2354 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2355 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2356}
2357
ff620849
EG		 2358static const char *get_csr_string(int cmd)
2359{
d9fb6465 2360#define IWL_CMD(x) case x: return #x
ff620849
EG		 2361 switch (cmd) {
2362 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2363 IWL_CMD(CSR_INT_COALESCING);
2364 IWL_CMD(CSR_INT);
2365 IWL_CMD(CSR_INT_MASK);
2366 IWL_CMD(CSR_FH_INT_STATUS);
2367 IWL_CMD(CSR_GPIO_IN);
2368 IWL_CMD(CSR_RESET);
2369 IWL_CMD(CSR_GP_CNTRL);
2370 IWL_CMD(CSR_HW_REV);
2371 IWL_CMD(CSR_EEPROM_REG);
2372 IWL_CMD(CSR_EEPROM_GP);
2373 IWL_CMD(CSR_OTP_GP_REG);
2374 IWL_CMD(CSR_GIO_REG);
2375 IWL_CMD(CSR_GP_UCODE_REG);
2376 IWL_CMD(CSR_GP_DRIVER_REG);
2377 IWL_CMD(CSR_UCODE_DRV_GP1);
2378 IWL_CMD(CSR_UCODE_DRV_GP2);
2379 IWL_CMD(CSR_LED_REG);
2380 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2381 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2382 IWL_CMD(CSR_ANA_PLL_CFG);
2383 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2384 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2385 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2386 default:
2387 return "UNKNOWN";
2388 }
d9fb6465 2389#undef IWL_CMD
ff620849
EG		 2390}
2391
990aa6d7 2392void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2393{
2394 int i;
2395 static const u32 csr_tbl[] = {
2396 CSR_HW_IF_CONFIG_REG,
2397 CSR_INT_COALESCING,
2398 CSR_INT,
2399 CSR_INT_MASK,
2400 CSR_FH_INT_STATUS,
2401 CSR_GPIO_IN,
2402 CSR_RESET,
2403 CSR_GP_CNTRL,
2404 CSR_HW_REV,
2405 CSR_EEPROM_REG,
2406 CSR_EEPROM_GP,
2407 CSR_OTP_GP_REG,
2408 CSR_GIO_REG,
2409 CSR_GP_UCODE_REG,
2410 CSR_GP_DRIVER_REG,
2411 CSR_UCODE_DRV_GP1,
2412 CSR_UCODE_DRV_GP2,
2413 CSR_LED_REG,
2414 CSR_DRAM_INT_TBL_REG,
2415 CSR_GIO_CHICKEN_BITS,
2416 CSR_ANA_PLL_CFG,
a812cba9 2417 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2418 CSR_HW_REV_WA_REG,
2419 CSR_DBG_HPET_MEM_REG
2420 };
2421 IWL_ERR(trans, "CSR values:\n");
2422 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2423 "CSR_INT_PERIODIC_REG)\n");
2424 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2425 IWL_ERR(trans, " %25s: 0X%08x\n",
2426 get_csr_string(csr_tbl[i]),
1042db2a 2427 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2428 }
2429}
2430
87e5666c
EG		 2431#ifdef CONFIG_IWLWIFI_DEBUGFS
2432/* create and remove of files */
2433#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
cf5d5663
GKH		 2434 debugfs_create_file(#name, mode, parent, trans, \
2435 &iwl_dbgfs_##name##_ops); \
87e5666c
EG		 2436} while (0)
2437
2438/* file operation */
87e5666c 2439#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2440static const struct file_operations iwl_dbgfs_##name##_ops = { \
2441 .read = iwl_dbgfs_##name##_read, \
234e3405 2442 .open = simple_open, \
87e5666c
EG		 2443 .llseek = generic_file_llseek, \
2444};
2445
16db88ba 2446#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2447static const struct file_operations iwl_dbgfs_##name##_ops = { \
2448 .write = iwl_dbgfs_##name##_write, \
234e3405 2449 .open = simple_open, \
16db88ba
EG		 2450 .llseek = generic_file_llseek, \
2451};
2452
87e5666c 2453#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2454static const struct file_operations iwl_dbgfs_##name##_ops = { \
2455 .write = iwl_dbgfs_##name##_write, \
2456 .read = iwl_dbgfs_##name##_read, \
234e3405 2457 .open = simple_open, \
87e5666c
EG		 2458 .llseek = generic_file_llseek, \
2459};
2460
df67a1be
JB		 2461struct iwl_dbgfs_tx_queue_priv {
2462 struct iwl_trans *trans;
2463};
2464
2465struct iwl_dbgfs_tx_queue_state {
2466 loff_t pos;
2467};
2468
2469static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
8ad71bef 2470{
df67a1be
JB		 2471 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2472 struct iwl_dbgfs_tx_queue_state *state;
2473
2474 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2475 return NULL;
2476
2477 state = kmalloc(sizeof(*state), GFP_KERNEL);
2478 if (!state)
2479 return NULL;
2480 state->pos = *pos;
2481 return state;
2482}
2483
2484static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2485 void *v, loff_t *pos)
2486{
2487 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2488 struct iwl_dbgfs_tx_queue_state *state = v;
2489
2490 *pos = ++state->pos;
2491
2492 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2493 return NULL;
2494
2495 return state;
2496}
2497
2498static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2499{
2500 kfree(v);
2501}
2502
2503static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2504{
2505 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2506 struct iwl_dbgfs_tx_queue_state *state = v;
2507 struct iwl_trans *trans = priv->trans;
4f4822b7 2508 struct iwl_txq *txq = trans->txqs.txq[state->pos];
df67a1be
JB		 2509
2510 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2511 (unsigned int)state->pos,
4f4822b7
MG		 2512 !!test_bit(state->pos, trans->txqs.queue_used),
2513 !!test_bit(state->pos, trans->txqs.queue_stopped));
df67a1be
JB		 2514 if (txq)
2515 seq_printf(seq,
95a9e44f 2516 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
df67a1be 2517 txq->read_ptr, txq->write_ptr,
95a9e44f
JB		 2518 txq->need_update, txq->frozen,
2519 txq->n_window, txq->ampdu);
df67a1be
JB		 2520 else
2521 seq_puts(seq, "(unallocated)");
1745e440 2522
4f4822b7 2523 if (state->pos == trans->txqs.cmd.q_id)
df67a1be
JB		 2524 seq_puts(seq, " (HCMD)");
2525 seq_puts(seq, "\n");
87e5666c 2526
df67a1be
JB		 2527 return 0;
2528}
f9e75447 2529
df67a1be
JB		 2530static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2531 .start = iwl_dbgfs_tx_queue_seq_start,
2532 .next = iwl_dbgfs_tx_queue_seq_next,
2533 .stop = iwl_dbgfs_tx_queue_seq_stop,
2534 .show = iwl_dbgfs_tx_queue_seq_show,
2535};
2536
2537static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2538{
2539 struct iwl_dbgfs_tx_queue_priv *priv;
2540
2541 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2542 sizeof(*priv));
2543
2544 if (!priv)
87e5666c
EG		 2545 return -ENOMEM;
2546
df67a1be
JB		 2547 priv->trans = inode->i_private;
2548 return 0;
87e5666c
EG		 2549}
2550
2551static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2552 char __user *user_buf,
2553 size_t count, loff_t *ppos)
2554{
5a878bf6 2555 struct iwl_trans *trans = file->private_data;
20d3b647 2556 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2557 char *buf;
2558 int pos = 0, i, ret;
eb3dc36e 2559 size_t bufsz;
78485054
SS		 2560
2561 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2562
2563 if (!trans_pcie->rxq)
2564 return -EAGAIN;
2565
2566 buf = kzalloc(bufsz, GFP_KERNEL);
2567 if (!buf)
2568 return -ENOMEM;
2569
2570 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2571 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2572
2573 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2574 i);
2575 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2576 rxq->read);
2577 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2578 rxq->write);
2579 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2580 rxq->write_actual);
2581 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2582 rxq->need_update);
2583 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2584 rxq->free_count);
2585 if (rxq->rb_stts) {
0307c839
GBA		 2586 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2587 rxq));
78485054
SS		 2588 pos += scnprintf(buf + pos, bufsz - pos,
2589 "\tclosed_rb_num: %u\n",
0307c839 2590 r & 0x0FFF);
78485054
SS		 2591 } else {
2592 pos += scnprintf(buf + pos, bufsz - pos,
2593 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2594 }
87e5666c 2595 }
78485054
SS		 2596 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2597 kfree(buf);
2598
2599 return ret;
87e5666c
EG		 2600}
2601
1f7b6172
EG		 2602static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2603 char __user *user_buf,
20d3b647
JB		 2604 size_t count, loff_t *ppos)
2605{
1f7b6172 2606 struct iwl_trans *trans = file->private_data;
20d3b647 2607 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2608 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2609
2610 int pos = 0;
2611 char *buf;
2612 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2613 ssize_t ret;
2614
2615 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2616 if (!buf)
1f7b6172 2617 return -ENOMEM;
1f7b6172
EG		 2618
2619 pos += scnprintf(buf + pos, bufsz - pos,
2620 "Interrupt Statistics Report:\n");
2621
2622 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2623 isr_stats->hw);
2624 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2625 isr_stats->sw);
2626 if (isr_stats->sw || isr_stats->hw) {
2627 pos += scnprintf(buf + pos, bufsz - pos,
2628 "\tLast Restarting Code: 0x%X\n",
2629 isr_stats->err_code);
2630 }
2631#ifdef CONFIG_IWLWIFI_DEBUG
2632 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2633 isr_stats->sch);
2634 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2635 isr_stats->alive);
2636#endif
2637 pos += scnprintf(buf + pos, bufsz - pos,
2638 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2639
2640 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2641 isr_stats->ctkill);
2642
2643 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2644 isr_stats->wakeup);
2645
2646 pos += scnprintf(buf + pos, bufsz - pos,
2647 "Rx command responses:\t\t %u\n", isr_stats->rx);
2648
2649 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2650 isr_stats->tx);
2651
2652 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2653 isr_stats->unhandled);
2654
2655 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2656 kfree(buf);
2657 return ret;
2658}
2659
2660static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2661 const char __user *user_buf,
2662 size_t count, loff_t *ppos)
2663{
2664 struct iwl_trans *trans = file->private_data;
20d3b647 2665 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2666 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2667 u32 reset_flag;
078f1131 2668 int ret;
1f7b6172 2669
078f1131
JB		 2670 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2671 if (ret)
2672 return ret;
1f7b6172
EG		 2673 if (reset_flag == 0)
2674 memset(isr_stats, 0, sizeof(*isr_stats));
2675
2676 return count;
2677}
2678
16db88ba 2679static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2680 const char __user *user_buf,
2681 size_t count, loff_t *ppos)
16db88ba
EG		 2682{
2683 struct iwl_trans *trans = file->private_data;
16db88ba 2684
990aa6d7 2685 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2686
2687 return count;
2688}
2689
16db88ba 2690static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2691 char __user *user_buf,
2692 size_t count, loff_t *ppos)
16db88ba
EG		 2693{
2694 struct iwl_trans *trans = file->private_data;
94543a8d 2695 char *buf = NULL;
56c2477f 2696 ssize_t ret;
16db88ba 2697
56c2477f
JB		 2698 ret = iwl_dump_fh(trans, &buf);
2699 if (ret < 0)
2700 return ret;
2701 if (!buf)
2702 return -EINVAL;
2703 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2704 kfree(buf);
16db88ba
EG		 2705 return ret;
2706}
2707
fa4de7f7
JB		 2708static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2709 char __user *user_buf,
2710 size_t count, loff_t *ppos)
2711{
2712 struct iwl_trans *trans = file->private_data;
2713 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2714 char buf[100];
2715 int pos;
2716
2717 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2718 trans_pcie->debug_rfkill,
2719 !(iwl_read32(trans, CSR_GP_CNTRL) &
2720 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2721
2722 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2723}
2724
2725static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2726 const char __user *user_buf,
2727 size_t count, loff_t *ppos)
2728{
2729 struct iwl_trans *trans = file->private_data;
2730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c5bf4fa1 2731 bool new_value;
fa4de7f7
JB		 2732 int ret;
2733
c5bf4fa1 2734 ret = kstrtobool_from_user(user_buf, count, &new_value);
fa4de7f7
JB		 2735 if (ret)
2736 return ret;
c5bf4fa1 2737 if (new_value == trans_pcie->debug_rfkill)
fa4de7f7
JB		 2738 return count;
2739 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
c5bf4fa1
JB		 2740 trans_pcie->debug_rfkill, new_value);
2741 trans_pcie->debug_rfkill = new_value;
fa4de7f7
JB		 2742 iwl_pcie_handle_rfkill_irq(trans);
2743
2744 return count;
2745}
2746
f7805b33
LC		 2747static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2748 struct file *file)
2749{
2750 struct iwl_trans *trans = inode->i_private;
2751 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2752
91c28b83
SM		 2753 if (!trans->dbg.dest_tlv ||
2754 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
f7805b33
LC		 2755 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2756 return -ENOENT;
2757 }
2758
2759 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2760 return -EBUSY;
2761
2762 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2763 return simple_open(inode, file);
2764}
2765
2766static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2767 struct file *file)
2768{
2769 struct iwl_trans_pcie *trans_pcie =
2770 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2771
2772 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2773 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2774 return 0;
2775}
2776
2777static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2778 void *buf, ssize_t *size,
2779 ssize_t *bytes_copied)
2780{
2781 int buf_size_left = count - *bytes_copied;
2782
2783 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2784 if (*size > buf_size_left)
2785 *size = buf_size_left;
2786
2787 *size -= copy_to_user(user_buf, buf, *size);
2788 *bytes_copied += *size;
2789
2790 if (buf_size_left == *size)
2791 return true;
2792 return false;
2793}
2794
2795static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2796 char __user *user_buf,
2797 size_t count, loff_t *ppos)
2798{
2799 struct iwl_trans *trans = file->private_data;
2800 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
69f0e505 2801 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
f7805b33
LC		 2802 struct cont_rec *data = &trans_pcie->fw_mon_data;
2803 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2804 ssize_t size, bytes_copied = 0;
2805 bool b_full;
2806
91c28b83 2807 if (trans->dbg.dest_tlv) {
f7805b33 2808 write_ptr_addr =
91c28b83
SM		 2809 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2810 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
f7805b33
LC		 2811 } else {
2812 write_ptr_addr = MON_BUFF_WRPTR;
2813 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2814 }
2815
91c28b83 2816 if (unlikely(!trans->dbg.rec_on))
f7805b33
LC		 2817 return 0;
2818
2819 mutex_lock(&data->mutex);
2820 if (data->state ==
2821 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2822 mutex_unlock(&data->mutex);
2823 return 0;
2824 }
2825
2826 /* write_ptr position in bytes rather then DW */
2827 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2828 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2829
2830 if (data->prev_wrap_cnt == wrap_cnt) {
2831 size = write_ptr - data->prev_wr_ptr;
2832 curr_buf = cpu_addr + data->prev_wr_ptr;
2833 b_full = iwl_write_to_user_buf(user_buf, count,
2834 curr_buf, &size,
2835 &bytes_copied);
2836 data->prev_wr_ptr += size;
2837
2838 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2839 write_ptr < data->prev_wr_ptr) {
69f0e505 2840 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
f7805b33
LC		 2841 curr_buf = cpu_addr + data->prev_wr_ptr;
2842 b_full = iwl_write_to_user_buf(user_buf, count,
2843 curr_buf, &size,
2844 &bytes_copied);
2845 data->prev_wr_ptr += size;
2846
2847 if (!b_full) {
2848 size = write_ptr;
2849 b_full = iwl_write_to_user_buf(user_buf, count,
2850 cpu_addr, &size,
2851 &bytes_copied);
2852 data->prev_wr_ptr = size;
2853 data->prev_wrap_cnt++;
2854 }
2855 } else {
2856 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2857 write_ptr > data->prev_wr_ptr)
2858 IWL_WARN(trans,
2859 "write pointer passed previous write pointer, start copying from the beginning\n");
2860 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2861 data->prev_wr_ptr == 0))
2862 IWL_WARN(trans,
2863 "monitor data is out of sync, start copying from the beginning\n");
2864
2865 size = write_ptr;
2866 b_full = iwl_write_to_user_buf(user_buf, count,
2867 cpu_addr, &size,
2868 &bytes_copied);
2869 data->prev_wr_ptr = size;
2870 data->prev_wrap_cnt = wrap_cnt;
2871 }
2872
2873 mutex_unlock(&data->mutex);
2874
2875 return bytes_copied;
2876}
2877
1f7b6172 2878DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2879DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c 2880DEBUGFS_READ_FILE_OPS(rx_queue);
16db88ba 2881DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2882DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
df67a1be
JB		 2883static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2884 .owner = THIS_MODULE,
2885 .open = iwl_dbgfs_tx_queue_open,
2886 .read = seq_read,
2887 .llseek = seq_lseek,
2888 .release = seq_release_private,
2889};
87e5666c 2890
f7805b33
LC		 2891static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2892 .read = iwl_dbgfs_monitor_data_read,
2893 .open = iwl_dbgfs_monitor_data_open,
2894 .release = iwl_dbgfs_monitor_data_release,
2895};
2896
f8a1edb7 2897/* Create the debugfs files and directories */
cf5d5663 2898void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2899{
f8a1edb7
JB		 2900 struct dentry *dir = trans->dbgfs_dir;
2901
2ef00c53
JP		 2902 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2903 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2904 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2905 DEBUGFS_ADD_FILE(csr, dir, 0200);
2906 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2907 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 2908 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
87e5666c 2909}
f7805b33
LC		 2910
2911static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2912{
2913 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2914 struct cont_rec *data = &trans_pcie->fw_mon_data;
2915
2916 mutex_lock(&data->mutex);
2917 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2918 mutex_unlock(&data->mutex);
2919}
aadede6e 2920#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2921
6983ba69 2922static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007
JB		 2923{
2924 u32 cmdlen = 0;
2925 int i;
2926
885375d0 2927 for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
0179bfff 2928 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2929
2930 return cmdlen;
2931}
2932
bd7fc617
EG		 2933static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2934 struct iwl_fw_error_dump_data **data,
2935 int allocated_rb_nums)
2936{
2937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
80084e35 2938 int max_len = trans_pcie->rx_buf_bytes;
78485054
SS		 2939 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2940 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2941 u32 i, r, j, rb_len = 0;
2942
2943 spin_lock(&rxq->lock);
2944
0307c839 2945 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2946
2947 for (i = rxq->read, j = 0;
2948 i != r && j < allocated_rb_nums;
2949 i = (i + 1) & RX_QUEUE_MASK, j++) {
2950 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2951 struct iwl_fw_error_dump_rb *rb;
2952
2953 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2954 DMA_FROM_DEVICE);
2955
2956 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2957
2958 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2959 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2960 rb = (void *)(*data)->data;
2961 rb->index = cpu_to_le32(i);
2962 memcpy(rb->data, page_address(rxb->page), max_len);
2963 /* remap the page for the free benefit */
cfdc20ef
JB		 2964 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
2965 rxb->offset, max_len,
2966 DMA_FROM_DEVICE);
bd7fc617
EG		 2967
2968 *data = iwl_fw_error_next_data(*data);
2969 }
2970
2971 spin_unlock(&rxq->lock);
2972
2973 return rb_len;
2974}
473ad712
EG		 2975#define IWL_CSR_TO_DUMP (0x250)
2976
2977static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2978 struct iwl_fw_error_dump_data **data)
2979{
2980 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2981 __le32 *val;
2982 int i;
2983
2984 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2985 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2986 val = (void *)(*data)->data;
2987
2988 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2989 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2990
2991 *data = iwl_fw_error_next_data(*data);
2992
2993 return csr_len;
2994}
2995
06d51e0d
LK		 2996static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2997 struct iwl_fw_error_dump_data **data)
2998{
2999 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3000 unsigned long flags;
3001 __le32 *val;
3002 int i;
3003
23ba9340 3004 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 3005 return 0;
3006
3007 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3008 (*data)->len = cpu_to_le32(fh_regs_len);
3009 val = (void *)(*data)->data;
3010
286ca8eb 3011 if (!trans->trans_cfg->gen2)
723b45e2
LK		 3012 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3013 i += sizeof(u32))
3014 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3015 else
ea695b7c
ST		 3016 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3017 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 3018 i += sizeof(u32))
3019 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3020 i));
06d51e0d
LK		 3021
3022 iwl_trans_release_nic_access(trans, &flags);
3023
3024 *data = iwl_fw_error_next_data(*data);
3025
3026 return sizeof(**data) + fh_regs_len;
3027}
3028
cc79ef66
LK		 3029static u32
3030iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3031 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3032 u32 monitor_len)
3033{
3034 u32 buf_size_in_dwords = (monitor_len >> 2);
3035 u32 *buffer = (u32 *)fw_mon_data->data;
3036 unsigned long flags;
3037 u32 i;
3038
23ba9340 3039 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 3040 return 0;
3041
ea695b7c 3042 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 3043 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 3044 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3045 MON_DMARB_RD_DATA_ADDR);
3046 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 3047
3048 iwl_trans_release_nic_access(trans, &flags);
3049
3050 return monitor_len;
3051}
3052
7a14c23d
SS		 3053static void
3054iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3055 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3056{
c88580e1 3057 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
7a14c23d 3058
286ca8eb 3059 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3060 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3061 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3062 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3063 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
91c28b83
SM		 3064 } else if (trans->dbg.dest_tlv) {
3065 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3066 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3067 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
7a14c23d
SS		 3068 } else {
3069 base = MON_BUFF_BASE_ADDR;
3070 write_ptr = MON_BUFF_WRPTR;
3071 wrap_cnt = MON_BUFF_CYCLE_CNT;
3072 }
c88580e1
SM		 3073
3074 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3075 fw_mon_data->fw_mon_cycle_cnt =
3076 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3077 fw_mon_data->fw_mon_base_ptr =
3078 cpu_to_le32(iwl_read_prph(trans, base));
286ca8eb 3079 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3080 fw_mon_data->fw_mon_base_high_ptr =
3081 cpu_to_le32(iwl_read_prph(trans, base_high));
3082 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
cc598782
RS		 3083 /* convert wrtPtr to DWs, to align with all HWs */
3084 write_ptr_val >>= 2;
c88580e1
SM		 3085 }
3086 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3087}
3088
36fb9017
OG		 3089static u32
3090iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3091 struct iwl_fw_error_dump_data **data,
3092 u32 monitor_len)
3093{
69f0e505 3094 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
36fb9017
OG		 3095 u32 len = 0;
3096
91c28b83 3097 if (trans->dbg.dest_tlv ||
69f0e505 3098 (fw_mon->size &&
286ca8eb
LC		 3099 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3100 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
36fb9017 3101 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3102
3103 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3104 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3105
3106 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3107
3108 len += sizeof(**data) + sizeof(*fw_mon_data);
69f0e505
SM		 3109 if (fw_mon->size) {
3110 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3111 monitor_len = fw_mon->size;
91c28b83 3112 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3113 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3114 /*
3115 * Update pointers to reflect actual values after
3116 * shifting
3117 */
91c28b83 3118 if (trans->dbg.dest_tlv->version) {
fd527eb5
GBA		 3119 base = (iwl_read_prph(trans, base) &
3120 IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3121 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3122 base *= IWL_M2S_UNIT_SIZE;
3123 base += trans->cfg->smem_offset;
3124 } else {
3125 base = iwl_read_prph(trans, base) <<
91c28b83 3126 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3127 }
3128
36fb9017
OG		 3129 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3130 monitor_len / sizeof(u32));
91c28b83 3131 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
36fb9017
OG		 3132 monitor_len =
3133 iwl_trans_pci_dump_marbh_monitor(trans,
3134 fw_mon_data,
3135 monitor_len);
3136 } else {
3137 /* Didn't match anything - output no monitor data */
3138 monitor_len = 0;
3139 }
3140
3141 len += monitor_len;
3142 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3143 }
3144
3145 return len;
3146}
3147
93079fd5 3148static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3149{
69f0e505 3150 if (trans->dbg.fw_mon.size) {
da752717
SM		 3151 *len += sizeof(struct iwl_fw_error_dump_data) +
3152 sizeof(struct iwl_fw_error_dump_fw_mon) +
69f0e505
SM		 3153 trans->dbg.fw_mon.size;
3154 return trans->dbg.fw_mon.size;
91c28b83 3155 } else if (trans->dbg.dest_tlv) {
da752717 3156 u32 base, end, cfg_reg, monitor_len;
99684ae3 3157
91c28b83
SM		 3158 if (trans->dbg.dest_tlv->version == 1) {
3159 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
fd527eb5
GBA		 3160 cfg_reg = iwl_read_prph(trans, cfg_reg);
3161 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3162 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3163 base *= IWL_M2S_UNIT_SIZE;
3164 base += trans->cfg->smem_offset;
99684ae3 3165
fd527eb5
GBA		 3166 monitor_len =
3167 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
91c28b83 3168 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3169 monitor_len *= IWL_M2S_UNIT_SIZE;
3170 } else {
91c28b83
SM		 3171 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3172 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
99684ae3 3173
fd527eb5 3174 base = iwl_read_prph(trans, base) <<
91c28b83 3175 trans->dbg.dest_tlv->base_shift;
fd527eb5 3176 end = iwl_read_prph(trans, end) <<
91c28b83 3177 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3178
3179 /* Make "end" point to the actual end */
286ca8eb 3180 if (trans->trans_cfg->device_family >=
fd527eb5 3181 IWL_DEVICE_FAMILY_8000 ||
91c28b83
SM		 3182 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3183 end += (1 << trans->dbg.dest_tlv->end_shift);
fd527eb5
GBA		 3184 monitor_len = end - base;
3185 }
da752717
SM		 3186 *len += sizeof(struct iwl_fw_error_dump_data) +
3187 sizeof(struct iwl_fw_error_dump_fw_mon) +
3188 monitor_len;
3189 return monitor_len;
99684ae3 3190 }
da752717
SM		 3191 return 0;
3192}
3193
3194static struct iwl_trans_dump_data
3195*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
79f033f6 3196 u32 dump_mask)
da752717
SM		 3197{
3198 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3199 struct iwl_fw_error_dump_data *data;
4f4822b7 3200 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
da752717
SM		 3201 struct iwl_fw_error_dump_txcmd *txcmd;
3202 struct iwl_trans_dump_data *dump_data;
fefbf853 3203 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3204 int i, ptr;
3205 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
286ca8eb 3206 !trans->trans_cfg->mq_rx_supported &&
79f033f6
SS		 3207 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3208
3209 if (!dump_mask)
3210 return NULL;
da752717
SM		 3211
3212 /* transport dump header */
3213 len = sizeof(*dump_data);
3214
3215 /* host commands */
e4eee943 3216 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
8672aad3
SM		 3217 len += sizeof(*data) +
3218 cmdq->n_window * (sizeof(*txcmd) +
3219 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3220
3221 /* FW monitor */
fefbf853
SM		 3222 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3223 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3224
3225 /* CSR registers */
79f033f6 3226 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3227 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3228
36fb9017 3229 /* FH registers */
79f033f6 3230 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
286ca8eb 3231 if (trans->trans_cfg->gen2)
520f03ea 3232 len += sizeof(*data) +
ea695b7c
ST		 3233 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3234 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3235 else
3236 len += sizeof(*data) +
3237 (FH_MEM_UPPER_BOUND -
3238 FH_MEM_LOWER_BOUND);
3239 }
36fb9017
OG		 3240
3241 if (dump_rbs) {
78485054
SS		 3242 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3243 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3244 /* RBs */
0307c839
GBA		 3245 num_rbs =
3246 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3247 & 0x0FFF;
78485054 3248 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3249 len += num_rbs * (sizeof(*data) +
3250 sizeof(struct iwl_fw_error_dump_rb) +
3251 (PAGE_SIZE << trans_pcie->rx_page_order));
3252 }
3253
5538409b 3254 /* Paged memory for gen2 HW */
286ca8eb 3255 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3256 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3257 len += sizeof(*data) +
3258 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3259 trans->init_dram.paging[i].size;
5538409b 3260
48eb7b34
EG		 3261 dump_data = vzalloc(len);
3262 if (!dump_data)
3263 return NULL;
4d075007
JB		 3264
3265 len = 0;
48eb7b34 3266 data = (void *)dump_data->data;
520f03ea 3267
e4eee943 3268 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
885375d0 3269 u16 tfd_size = trans->txqs.tfd.size;
520f03ea
SM		 3270
3271 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3272 txcmd = (void *)data->data;
3273 spin_lock_bh(&cmdq->lock);
3274 ptr = cmdq->write_ptr;
3275 for (i = 0; i < cmdq->n_window; i++) {
0cd1ad2d 3276 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
08326a97 3277 u8 tfdidx;
520f03ea
SM		 3278 u32 caplen, cmdlen;
3279
08326a97
JB		 3280 if (trans->trans_cfg->use_tfh)
3281 tfdidx = idx;
3282 else
3283 tfdidx = ptr;
3284
520f03ea 3285 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
08326a97
JB		 3286 (u8 *)cmdq->tfds +
3287 tfd_size * tfdidx);
520f03ea
SM		 3288 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3289
3290 if (cmdlen) {
3291 len += sizeof(*txcmd) + caplen;
3292 txcmd->cmdlen = cpu_to_le32(cmdlen);
3293 txcmd->caplen = cpu_to_le32(caplen);
3294 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3295 caplen);
3296 txcmd = (void *)((u8 *)txcmd->data + caplen);
3297 }
3298
0cd1ad2d 3299 ptr = iwl_txq_dec_wrap(trans, ptr);
4d075007 3300 }
520f03ea 3301 spin_unlock_bh(&cmdq->lock);
4d075007 3302
520f03ea
SM		 3303 data->len = cpu_to_le32(len);
3304 len += sizeof(*data);
3305 data = iwl_fw_error_next_data(data);
4d075007 3306 }
67c65f2c 3307
79f033f6 3308 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3309 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3310 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3311 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3312 if (dump_rbs)
3313 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3314
5538409b 3315 /* Paged memory for gen2 HW */
286ca8eb 3316 if (trans->trans_cfg->gen2 &&
79b6c8fe 3317 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3318 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3319 struct iwl_fw_error_dump_paging *paging;
505a00c0 3320 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3321
3322 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3323 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3324 paging = (void *)data->data;
3325 paging->index = cpu_to_le32(i);
5538409b 3326 memcpy(paging->data,
505a00c0 3327 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3328 data = iwl_fw_error_next_data(data);
3329
3330 len += sizeof(*data) + sizeof(*paging) + page_len;
3331 }
3332 }
79f033f6 3333 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3334 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3335
48eb7b34
EG		 3336 dump_data->len = len;
3337
3338 return dump_data;
4d075007 3339}
87e5666c 3340
4cbb8e50
LC		 3341#ifdef CONFIG_PM_SLEEP
3342static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3343{
4cbb8e50
LC		 3344 return 0;
3345}
3346
3347static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3348{
4cbb8e50
LC		 3349}
3350#endif /* CONFIG_PM_SLEEP */
3351
623e7766
SS		 3352#define IWL_TRANS_COMMON_OPS \
3353 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3354 .write8 = iwl_trans_pcie_write8, \
3355 .write32 = iwl_trans_pcie_write32, \
3356 .read32 = iwl_trans_pcie_read32, \
3357 .read_prph = iwl_trans_pcie_read_prph, \
3358 .write_prph = iwl_trans_pcie_write_prph, \
3359 .read_mem = iwl_trans_pcie_read_mem, \
3360 .write_mem = iwl_trans_pcie_write_mem, \
7f1fe1d4 3361 .read_config32 = iwl_trans_pcie_read_config32, \
623e7766
SS		 3362 .configure = iwl_trans_pcie_configure, \
3363 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3364 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3365 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3366 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3367 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
623e7766 3368 .dump_data = iwl_trans_pcie_dump_data, \
623e7766 3369 .d3_suspend = iwl_trans_pcie_d3_suspend, \
d1967ce6
SM		 3370 .d3_resume = iwl_trans_pcie_d3_resume, \
3371 .sync_nmi = iwl_trans_pcie_sync_nmi
623e7766
SS		 3372
3373#ifdef CONFIG_PM_SLEEP
3374#define IWL_TRANS_PM_OPS \
3375 .suspend = iwl_trans_pcie_suspend, \
3376 .resume = iwl_trans_pcie_resume,
3377#else
3378#define IWL_TRANS_PM_OPS
3379#endif /* CONFIG_PM_SLEEP */
3380
d1ff5253 3381static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3382 IWL_TRANS_COMMON_OPS,
3383 IWL_TRANS_PM_OPS
57a1dc89 3384 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3385 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3386 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3387 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3388
623e7766 3389 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3390
623e7766 3391 .tx = iwl_trans_pcie_tx,
a4450980 3392 .reclaim = iwl_txq_reclaim,
623e7766
SS		 3393
3394 .txq_disable = iwl_trans_pcie_txq_disable,
3395 .txq_enable = iwl_trans_pcie_txq_enable,
3396
3397 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3398
d6d517b7
SS		 3399 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3400
a4450980 3401 .freeze_txq_timer = iwl_trans_txq_freeze_timer,
623e7766 3402 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3403#ifdef CONFIG_IWLWIFI_DEBUGFS
3404 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3405#endif
623e7766
SS		 3406};
3407
3408static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3409 IWL_TRANS_COMMON_OPS,
3410 IWL_TRANS_PM_OPS
3411 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3412 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3413 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3414 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3415
ca60da2e 3416 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3417
0cd1ad2d 3418 .tx = iwl_txq_gen2_tx,
a4450980 3419 .reclaim = iwl_txq_reclaim,
34c1b7ba 3420
a4450980 3421 .set_q_ptrs = iwl_txq_set_q_ptrs,
ba7136f3 3422
0cd1ad2d
MG		 3423 .txq_alloc = iwl_txq_dyn_alloc,
3424 .txq_free = iwl_txq_dyn_free,
d6d517b7 3425 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3426 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
6654cd4e 3427 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
f7805b33
LC		 3428#ifdef CONFIG_IWLWIFI_DEBUGFS
3429 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3430#endif
e6bb4c9c 3431};
a42a1844 3432
87ce05a2 3433struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
7e8258c0
LC		 3434 const struct pci_device_id *ent,
3435 const struct iwl_cfg_trans_params *cfg_trans)
a42a1844 3436{
a42a1844
EG		 3437 struct iwl_trans_pcie *trans_pcie;
3438 struct iwl_trans *trans;
fda1bd0d 3439 int ret, addr_size;
a89c72ff
JB		 3440 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3441
fda1bd0d 3442 if (!cfg_trans->gen2)
a89c72ff 3443 ops = &trans_ops_pcie;
a42a1844 3444
5a41a86c
SD		 3445 ret = pcim_enable_device(pdev);
3446 if (ret)
3447 return ERR_PTR(ret);
3448
a89c72ff 3449 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
fda1bd0d 3450 cfg_trans);
7b501d10
JB		 3451 if (!trans)
3452 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3453
3454 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3455
a42a1844 3456 trans_pcie->trans = trans;
326477e4 3457 trans_pcie->opmode_down = true;
7b11488f 3458 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3459 spin_lock_init(&trans_pcie->reg_lock);
cfdc20ef 3460 spin_lock_init(&trans_pcie->alloc_page_lock);
fa9f3281 3461 mutex_init(&trans_pcie->mutex);
13df1aab 3462 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
8188a18e
JB		 3463
3464 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3465 WQ_HIGHPRI | WQ_UNBOUND, 1);
3466 if (!trans_pcie->rba.alloc_wq) {
3467 ret = -ENOMEM;
3468 goto out_free_trans;
3469 }
3470 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3471
c5bf4fa1 3472 trans_pcie->debug_rfkill = -1;
d819c6cf 3473
7e8258c0 3474 if (!cfg_trans->base_params->pcie_l1_allowed) {
f2532b04
EG		 3475 /*
3476 * W/A - seems to solve weird behavior. We need to remove this
3477 * if we don't want to stay in L1 all the time. This wastes a
3478 * lot of power.
3479 */
3480 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3481 PCIE_LINK_STATE_L1 |
3482 PCIE_LINK_STATE_CLKPM);
3483 }
a42a1844 3484
9416560e
GBA		 3485 trans_pcie->def_rx_queue = 0;
3486
a42a1844
EG		 3487 pci_set_master(pdev);
3488
885375d0 3489 addr_size = trans->txqs.tfd.addr_size;
96a6497b 3490 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3491 if (!ret)
96a6497b
SS		 3492 ret = pci_set_consistent_dma_mask(pdev,
3493 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3494 if (ret) {
3495 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3496 if (!ret)
3497 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3498 DMA_BIT_MASK(32));
a42a1844 3499 /* both attempts failed: */
af3f2f74 3500 if (ret) {
6a4b09f8 3501 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3502 goto out_no_pci;
a42a1844
EG		 3503 }
3504 }
3505
5a41a86c 3506 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3507 if (ret) {
5a41a86c
SD		 3508 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3509 goto out_no_pci;
a42a1844
EG		 3510 }
3511
5a41a86c 3512 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3513 if (!trans_pcie->hw_base) {
5a41a86c 3514 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3515 ret = -ENODEV;
5a41a86c 3516 goto out_no_pci;
a42a1844
EG		 3517 }
3518
a42a1844
EG		 3519 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3520 * PCI Tx retries from interfering with C3 CPU state */
3521 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3522
83f7a85f
EG		 3523 trans_pcie->pci_dev = pdev;
3524 iwl_disable_interrupts(trans);
3525
08079a49 3526 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3527 if (trans->hw_rev == 0xffffffff) {
3528 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3529 ret = -EIO;
3530 goto out_no_pci;
3531 }
3532
b513ee7f
LK		 3533 /*
3534 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3535 * changed, and now the revision step also includes bit 0-1 (no more
3536 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3537 * in the old format.
3538 */
7e8258c0 3539 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
b513ee7f 3540 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3541 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3542
f9e5554c
EG		 3543 ret = iwl_pcie_prepare_card_hw(trans);
3544 if (ret) {
3545 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3546 goto out_no_pci;
f9e5554c
EG		 3547 }
3548
7a42baa6
EH		 3549 /*
3550 * in-order to recognize C step driver should read chip version
3551 * id located at the AUX bus MISC address space.
3552 */
7e8258c0 3553 ret = iwl_finish_nic_init(trans, cfg_trans);
c96b5eec 3554 if (ret)
5a41a86c 3555 goto out_no_pci;
7a42baa6 3556
7a42baa6
EH		 3557 }
3558
99be6166
LC		 3559 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3560
7e8258c0 3561 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
99673ee5 3562 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3563 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3564 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3565
69a10b29 3566 /* Initialize the wait queue for commands */
f946b529 3567 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3568
e5f3f215
HD		 3569 init_waitqueue_head(&trans_pcie->sx_waitq);
3570
c239feec 3571
2e5d4a8f 3572 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3573 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3574 if (ret)
5a41a86c 3575 goto out_no_pci;
2e5d4a8f
HD		 3576 } else {
3577 ret = iwl_pcie_alloc_ict(trans);
3578 if (ret)
5a41a86c 3579 goto out_no_pci;
a8b691e6 3580
5a41a86c
SD		 3581 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3582 iwl_pcie_isr,
3583 iwl_pcie_irq_handler,
3584 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3585 if (ret) {
3586 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3587 goto out_free_ict;
3588 }
3589 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3590 }
83f7a85f 3591
f7805b33
LC		 3592#ifdef CONFIG_IWLWIFI_DEBUGFS
3593 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3594 mutex_init(&trans_pcie->fw_mon_data.mutex);
3595#endif
3596
a9248de4
SM		 3597 iwl_dbg_tlv_init(trans);
3598
a42a1844
EG		 3599 return trans;
3600
a8b691e6
JB		 3601out_free_ict:
3602 iwl_pcie_free_ict(trans);
a42a1844 3603out_no_pci:
8188a18e
JB		 3604 destroy_workqueue(trans_pcie->rba.alloc_wq);
3605out_free_trans:
7b501d10 3606 iwl_trans_free(trans);
af3f2f74 3607 return ERR_PTR(ret);
a42a1844 3608}
b8a7547d 3609
d1967ce6 3610void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
b8a7547d 3611{
1c6bca6d 3612 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
b8a7547d 3613 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
e4eee943 3614 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
1c6bca6d
SM		 3615 u32 inta_addr, sw_err_bit;
3616
3617 if (trans_pcie->msix_enabled) {
3618 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3619 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3620 } else {
3621 inta_addr = CSR_INT;
3622 sw_err_bit = CSR_INT_BIT_SW_ERR;
3623 }
b8a7547d 3624
e4eee943
SM		 3625 /* if the interrupts were already disabled, there is no point in
3626 * calling iwl_disable_interrupts
3627 */
3628 if (interrupts_enabled)
3629 iwl_disable_interrupts(trans);
3630
b8a7547d
SM		 3631 iwl_force_nmi(trans);
3632 while (time_after(timeout, jiffies)) {
1c6bca6d 3633 u32 inta_hw = iwl_read32(trans, inta_addr);
b8a7547d
SM		 3634
3635 /* Error detected by uCode */
1c6bca6d 3636 if (inta_hw & sw_err_bit) {
b8a7547d 3637 /* Clear causes register */
1c6bca6d 3638 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
b8a7547d
SM		 3639 break;
3640 }
3641
3642 mdelay(1);
3643 }
e4eee943
SM		 3644
3645 /* enable interrupts only if there were already enabled before this
3646 * function to avoid a case were the driver enable interrupts before
3647 * proper configurations were made
3648 */
3649 if (interrupts_enabled)
3650 iwl_enable_interrupts(trans);
3651
b8a7547d
SM		 3652 iwl_trans_fw_error(trans);
3653}
Linux 6.x block layer and io_uring tree(s)