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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
553452e5 LK |
8 | * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. |
9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
afb84431 | 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
ea695b7c | 11 | * Copyright(c) 2018 - 2019 Intel Corporation |
c85eb619 EG |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of version 2 of the GNU General Public License as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
c85eb619 | 22 | * The full GNU General Public License is included in this distribution |
410dc5aa | 23 | * in the file called COPYING. |
c85eb619 EG |
24 | * |
25 | * Contact Information: | |
cb2f8277 | 26 | * Intel Linux Wireless <linuxwifi@intel.com> |
c85eb619 EG |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | * BSD LICENSE | |
30 | * | |
553452e5 LK |
31 | * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. |
32 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
afb84431 | 33 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
ea695b7c | 34 | * Copyright(c) 2018 - 2019 Intel Corporation |
c85eb619 EG |
35 | * All rights reserved. |
36 | * | |
37 | * Redistribution and use in source and binary forms, with or without | |
38 | * modification, are permitted provided that the following conditions | |
39 | * are met: | |
40 | * | |
41 | * * Redistributions of source code must retain the above copyright | |
42 | * notice, this list of conditions and the following disclaimer. | |
43 | * * Redistributions in binary form must reproduce the above copyright | |
44 | * notice, this list of conditions and the following disclaimer in | |
45 | * the documentation and/or other materials provided with the | |
46 | * distribution. | |
47 | * * Neither the name Intel Corporation nor the names of its | |
48 | * contributors may be used to endorse or promote products derived | |
49 | * from this software without specific prior written permission. | |
50 | * | |
51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
52 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
53 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
54 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
55 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
56 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
57 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
58 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
59 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
60 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
61 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
62 | * | |
63 | *****************************************************************************/ | |
a42a1844 EG |
64 | #include <linux/pci.h> |
65 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 66 | #include <linux/interrupt.h> |
87e5666c | 67 | #include <linux/debugfs.h> |
cf614297 | 68 | #include <linux/sched.h> |
6d8f6eeb EG |
69 | #include <linux/bitops.h> |
70 | #include <linux/gfp.h> | |
48eb7b34 | 71 | #include <linux/vmalloc.h> |
b3ff1270 | 72 | #include <linux/pm_runtime.h> |
49564a80 | 73 | #include <linux/module.h> |
f7805b33 | 74 | #include <linux/wait.h> |
e6bb4c9c | 75 | |
82575102 | 76 | #include "iwl-drv.h" |
c85eb619 | 77 | #include "iwl-trans.h" |
522376d2 EG |
78 | #include "iwl-csr.h" |
79 | #include "iwl-prph.h" | |
cb6bb128 | 80 | #include "iwl-scd.h" |
7a10e3e4 | 81 | #include "iwl-agn-hw.h" |
d962f9b1 | 82 | #include "fw/error-dump.h" |
520f03ea | 83 | #include "fw/dbg.h" |
6468a01a | 84 | #include "internal.h" |
06d51e0d | 85 | #include "iwl-fh.h" |
0439bb62 | 86 | |
fe45773b AN |
87 | /* extended range in FW SRAM */ |
88 | #define IWL_FW_MEM_EXTENDED_START 0x40000 | |
89 | #define IWL_FW_MEM_EXTENDED_END 0x57FFF | |
90 | ||
4290eaad | 91 | void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) |
a6d24fad RJ |
92 | { |
93 | #define PCI_DUMP_SIZE 64 | |
94 | #define PREFIX_LEN 32 | |
95 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
96 | struct pci_dev *pdev = trans_pcie->pci_dev; | |
97 | u32 i, pos, alloc_size, *ptr, *buf; | |
98 | char *prefix; | |
99 | ||
100 | if (trans_pcie->pcie_dbg_dumped_once) | |
101 | return; | |
102 | ||
103 | /* Should be a multiple of 4 */ | |
104 | BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); | |
105 | /* Alloc a max size buffer */ | |
106 | if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) | |
107 | alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; | |
108 | else | |
109 | alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; | |
110 | buf = kmalloc(alloc_size, GFP_ATOMIC); | |
111 | if (!buf) | |
112 | return; | |
113 | prefix = (char *)buf + alloc_size - PREFIX_LEN; | |
114 | ||
115 | IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); | |
116 | ||
117 | /* Print wifi device registers */ | |
118 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); | |
119 | IWL_ERR(trans, "iwlwifi device config registers:\n"); | |
120 | for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) | |
121 | if (pci_read_config_dword(pdev, i, ptr)) | |
122 | goto err_read; | |
123 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
124 | ||
125 | IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); | |
126 | for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) | |
127 | *ptr = iwl_read32(trans, i); | |
128 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
129 | ||
130 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); | |
131 | if (pos) { | |
132 | IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); | |
133 | for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) | |
134 | if (pci_read_config_dword(pdev, pos + i, ptr)) | |
135 | goto err_read; | |
136 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, | |
137 | 32, 4, buf, i, 0); | |
138 | } | |
139 | ||
140 | /* Print parent device registers next */ | |
141 | if (!pdev->bus->self) | |
142 | goto out; | |
143 | ||
144 | pdev = pdev->bus->self; | |
145 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); | |
146 | ||
147 | IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", | |
148 | pci_name(pdev)); | |
149 | for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) | |
150 | if (pci_read_config_dword(pdev, i, ptr)) | |
151 | goto err_read; | |
152 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
153 | ||
154 | /* Print root port AER registers */ | |
155 | pos = 0; | |
156 | pdev = pcie_find_root_port(pdev); | |
157 | if (pdev) | |
158 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); | |
159 | if (pos) { | |
160 | IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", | |
161 | pci_name(pdev)); | |
162 | sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); | |
163 | for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) | |
164 | if (pci_read_config_dword(pdev, pos + i, ptr)) | |
165 | goto err_read; | |
166 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, | |
167 | 4, buf, i, 0); | |
168 | } | |
f3402d6d | 169 | goto out; |
a6d24fad RJ |
170 | |
171 | err_read: | |
172 | print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); | |
173 | IWL_ERR(trans, "Read failed at 0x%X\n", i); | |
174 | out: | |
175 | trans_pcie->pcie_dbg_dumped_once = 1; | |
176 | kfree(buf); | |
177 | } | |
178 | ||
870c2a11 GBA |
179 | static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) |
180 | { | |
181 | /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ | |
a8cbb46f GBA |
182 | iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, |
183 | BIT(trans->cfg->csr->flag_sw_reset)); | |
870c2a11 GBA |
184 | usleep_range(5000, 6000); |
185 | } | |
186 | ||
c2d20201 EG |
187 | static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) |
188 | { | |
88964b2e | 189 | int i; |
c2d20201 | 190 | |
88964b2e SS |
191 | for (i = 0; i < trans->num_blocks; i++) { |
192 | dma_free_coherent(trans->dev, trans->fw_mon[i].size, | |
193 | trans->fw_mon[i].block, | |
194 | trans->fw_mon[i].physical); | |
195 | trans->fw_mon[i].block = NULL; | |
196 | trans->fw_mon[i].physical = 0; | |
197 | trans->fw_mon[i].size = 0; | |
198 | trans->num_blocks--; | |
199 | } | |
c2d20201 EG |
200 | } |
201 | ||
88964b2e SS |
202 | static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, |
203 | u8 max_power, u8 min_power) | |
c2d20201 | 204 | { |
c5f97542 | 205 | void *cpu_addr = NULL; |
88964b2e | 206 | dma_addr_t phys = 0; |
96c285da | 207 | u32 size = 0; |
c2d20201 EG |
208 | u8 power; |
209 | ||
88964b2e | 210 | for (power = max_power; power >= min_power; power--) { |
c2d20201 | 211 | size = BIT(power); |
c5f97542 SM |
212 | cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, |
213 | GFP_KERNEL | __GFP_NOWARN | | |
214 | __GFP_ZERO | __GFP_COMP); | |
215 | if (!cpu_addr) | |
c2d20201 EG |
216 | continue; |
217 | ||
c2d20201 | 218 | IWL_INFO(trans, |
c5f97542 SM |
219 | "Allocated 0x%08x bytes for firmware monitor.\n", |
220 | size); | |
c2d20201 EG |
221 | break; |
222 | } | |
223 | ||
c5f97542 | 224 | if (WARN_ON_ONCE(!cpu_addr)) |
c2d20201 EG |
225 | return; |
226 | ||
96c285da EG |
227 | if (power != max_power) |
228 | IWL_ERR(trans, | |
229 | "Sorry - debug buffer is only %luK while you requested %luK\n", | |
230 | (unsigned long)BIT(power - 10), | |
231 | (unsigned long)BIT(max_power - 10)); | |
232 | ||
88964b2e SS |
233 | trans->fw_mon[trans->num_blocks].block = cpu_addr; |
234 | trans->fw_mon[trans->num_blocks].physical = phys; | |
235 | trans->fw_mon[trans->num_blocks].size = size; | |
236 | trans->num_blocks++; | |
237 | } | |
238 | ||
239 | void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) | |
240 | { | |
241 | if (!max_power) { | |
242 | /* default max_power is maximum */ | |
243 | max_power = 26; | |
244 | } else { | |
245 | max_power += 11; | |
246 | } | |
247 | ||
248 | if (WARN(max_power > 26, | |
249 | "External buffer size for monitor is too big %d, check the FW TLV\n", | |
250 | max_power)) | |
251 | return; | |
252 | ||
253 | /* | |
254 | * This function allocats the default fw monitor. | |
255 | * The optional additional ones will be allocated in runtime | |
256 | */ | |
257 | if (trans->num_blocks) | |
258 | return; | |
259 | ||
260 | iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); | |
c2d20201 EG |
261 | } |
262 | ||
a812cba9 AB |
263 | static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) |
264 | { | |
265 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
266 | ((reg & 0x0000ffff) | (2 << 28))); | |
267 | return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); | |
268 | } | |
269 | ||
270 | static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) | |
271 | { | |
272 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); | |
273 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
274 | ((reg & 0x0000ffff) | (3 << 28))); | |
275 | } | |
276 | ||
ddaf5a5b | 277 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 278 | { |
66337b7c | 279 | if (trans->cfg->apmg_not_supported) |
95411d04 AA |
280 | return; |
281 | ||
ddaf5a5b JB |
282 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
283 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
284 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
285 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
286 | else | |
287 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
288 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
289 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
290 | } |
291 | ||
af634bee EG |
292 | /* PCI registers */ |
293 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 294 | |
eda50cde | 295 | void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 296 | { |
20d3b647 | 297 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 298 | u16 lctl; |
9180ac50 | 299 | u16 cap; |
af634bee | 300 | |
af634bee EG |
301 | /* |
302 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
303 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
304 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
305 | * costs negligible amount of power savings. | |
306 | * If not (unlikely), enable L0S, so there is at least some | |
307 | * power savings, even without L1. | |
308 | */ | |
7afe3705 | 309 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
9180ac50 | 310 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) |
af634bee | 311 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
9180ac50 | 312 | else |
af634bee | 313 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
438a0f0a | 314 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
9180ac50 EG |
315 | |
316 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); | |
317 | trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; | |
d74a61fc LC |
318 | IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", |
319 | (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", | |
320 | trans->ltr_enabled ? "En" : "Dis"); | |
af634bee EG |
321 | } |
322 | ||
a6c684ee EG |
323 | /* |
324 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 325 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
326 | * NOTE: This does not load uCode nor start the embedded processor |
327 | */ | |
7afe3705 | 328 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee | 329 | { |
52b6e168 EG |
330 | int ret; |
331 | ||
a6c684ee EG |
332 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); |
333 | ||
334 | /* | |
335 | * Use "set_bit" below rather than "write", to preserve any hardware | |
336 | * bits already set by default after reset. | |
337 | */ | |
338 | ||
339 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
6e584873 | 340 | if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) |
e4a9f8ce EH |
341 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, |
342 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
a6c684ee EG |
343 | |
344 | /* | |
345 | * Disable L0s without affecting L1; | |
346 | * don't wait for ICH L0s (ICH bug W/A) | |
347 | */ | |
348 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 349 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
350 | |
351 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
352 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
353 | ||
354 | /* | |
355 | * Enable HAP INTA (interrupt from management bus) to | |
356 | * wake device's PCI Express link L1a -> L0s | |
357 | */ | |
358 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 359 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 360 | |
7afe3705 | 361 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
362 | |
363 | /* Configure analog phase-lock-loop before activating to D0A */ | |
77d76931 JB |
364 | if (trans->cfg->base_params->pll_cfg) |
365 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
a6c684ee | 366 | |
c96b5eec JB |
367 | ret = iwl_finish_nic_init(trans); |
368 | if (ret) | |
52b6e168 | 369 | return ret; |
a6c684ee | 370 | |
2d93aee1 EG |
371 | if (trans->cfg->host_interrupt_operation_mode) { |
372 | /* | |
373 | * This is a bit of an abuse - This is needed for 7260 / 3160 | |
374 | * only check host_interrupt_operation_mode even if this is | |
375 | * not related to host_interrupt_operation_mode. | |
376 | * | |
377 | * Enable the oscillator to count wake up time for L1 exit. This | |
378 | * consumes slightly more power (100uA) - but allows to be sure | |
379 | * that we wake up from L1 on time. | |
380 | * | |
381 | * This looks weird: read twice the same register, discard the | |
382 | * value, set a bit, and yet again, read that same register | |
383 | * just to discard the value. But that's the way the hardware | |
384 | * seems to like it. | |
385 | */ | |
386 | iwl_read_prph(trans, OSC_CLK); | |
387 | iwl_read_prph(trans, OSC_CLK); | |
388 | iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); | |
389 | iwl_read_prph(trans, OSC_CLK); | |
390 | iwl_read_prph(trans, OSC_CLK); | |
391 | } | |
392 | ||
a6c684ee EG |
393 | /* |
394 | * Enable DMA clock and wait for it to stabilize. | |
395 | * | |
3073d8c0 EH |
396 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" |
397 | * bits do not disable clocks. This preserves any hardware | |
398 | * bits already set by default in "CLK_CTRL_REG" after reset. | |
a6c684ee | 399 | */ |
95411d04 | 400 | if (!trans->cfg->apmg_not_supported) { |
3073d8c0 EH |
401 | iwl_write_prph(trans, APMG_CLK_EN_REG, |
402 | APMG_CLK_VAL_DMA_CLK_RQT); | |
403 | udelay(20); | |
404 | ||
405 | /* Disable L1-Active */ | |
406 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
407 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
408 | ||
409 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ | |
410 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, | |
411 | APMG_RTC_INT_STT_RFKILL); | |
412 | } | |
889b1696 | 413 | |
eb7ff77e | 414 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee | 415 | |
52b6e168 | 416 | return 0; |
a6c684ee EG |
417 | } |
418 | ||
a812cba9 AB |
419 | /* |
420 | * Enable LP XTAL to avoid HW bug where device may consume much power if | |
421 | * FW is not loaded after device reset. LP XTAL is disabled by default | |
422 | * after device HW reset. Do it only if XTAL is fed by internal source. | |
423 | * Configure device's "persistence" mode to avoid resetting XTAL again when | |
424 | * SHRD_HW_RST occurs in S3. | |
425 | */ | |
426 | static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) | |
427 | { | |
428 | int ret; | |
429 | u32 apmg_gp1_reg; | |
430 | u32 apmg_xtal_cfg_reg; | |
431 | u32 dl_cfg_reg; | |
432 | ||
433 | /* Force XTAL ON */ | |
434 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
435 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
436 | ||
870c2a11 | 437 | iwl_trans_pcie_sw_reset(trans); |
a812cba9 | 438 | |
c96b5eec JB |
439 | ret = iwl_finish_nic_init(trans); |
440 | if (WARN_ON(ret)) { | |
a812cba9 AB |
441 | /* Release XTAL ON request */ |
442 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
443 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
444 | return; | |
445 | } | |
446 | ||
447 | /* | |
448 | * Clear "disable persistence" to avoid LP XTAL resetting when | |
449 | * SHRD_HW_RST is applied in S3. | |
450 | */ | |
451 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
452 | APMG_PCIDEV_STT_VAL_PERSIST_DIS); | |
453 | ||
454 | /* | |
455 | * Force APMG XTAL to be active to prevent its disabling by HW | |
456 | * caused by APMG idle state. | |
457 | */ | |
458 | apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, | |
459 | SHR_APMG_XTAL_CFG_REG); | |
460 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
461 | apmg_xtal_cfg_reg | | |
462 | SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
463 | ||
870c2a11 | 464 | iwl_trans_pcie_sw_reset(trans); |
a812cba9 AB |
465 | |
466 | /* Enable LP XTAL by indirect access through CSR */ | |
467 | apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); | |
468 | iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | | |
469 | SHR_APMG_GP1_WF_XTAL_LP_EN | | |
470 | SHR_APMG_GP1_CHICKEN_BIT_SELECT); | |
471 | ||
472 | /* Clear delay line clock power up */ | |
473 | dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); | |
474 | iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & | |
475 | ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); | |
476 | ||
477 | /* | |
478 | * Enable persistence mode to avoid LP XTAL resetting when | |
479 | * SHRD_HW_RST is applied in S3. | |
480 | */ | |
481 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
482 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
483 | ||
484 | /* | |
485 | * Clear "initialization complete" bit to move adapter from | |
486 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
487 | */ | |
488 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
a8cbb46f | 489 | BIT(trans->cfg->csr->flag_init_done)); |
a812cba9 AB |
490 | |
491 | /* Activates XTAL resources monitor */ | |
492 | __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, | |
493 | CSR_MONITOR_XTAL_RESOURCES); | |
494 | ||
495 | /* Release XTAL ON request */ | |
496 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
497 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
498 | udelay(10); | |
499 | ||
500 | /* Release APMG XTAL */ | |
501 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
502 | apmg_xtal_cfg_reg & | |
503 | ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
504 | } | |
505 | ||
e8c8935e | 506 | void iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 | 507 | { |
e8c8935e | 508 | int ret; |
cc56feb2 EG |
509 | |
510 | /* stop device's busmaster DMA activity */ | |
a8cbb46f GBA |
511 | iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, |
512 | BIT(trans->cfg->csr->flag_stop_master)); | |
cc56feb2 | 513 | |
a8cbb46f GBA |
514 | ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, |
515 | BIT(trans->cfg->csr->flag_master_dis), | |
516 | BIT(trans->cfg->csr->flag_master_dis), 100); | |
7f2ac8fb | 517 | if (ret < 0) |
cc56feb2 EG |
518 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); |
519 | ||
520 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
cc56feb2 EG |
521 | } |
522 | ||
b7aaeae4 | 523 | static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) |
cc56feb2 EG |
524 | { |
525 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
526 | ||
b7aaeae4 EG |
527 | if (op_mode_leave) { |
528 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
529 | iwl_pcie_apm_init(trans); | |
530 | ||
531 | /* inform ME that we are leaving */ | |
532 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) | |
533 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
534 | APMG_PCIDEV_STT_VAL_WAKE_ME); | |
6e584873 | 535 | else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { |
c9fdec9f EG |
536 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
537 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
b7aaeae4 EG |
538 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
539 | CSR_HW_IF_CONFIG_REG_PREPARE | | |
540 | CSR_HW_IF_CONFIG_REG_ENABLE_PME); | |
c9fdec9f EG |
541 | mdelay(1); |
542 | iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, | |
543 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
544 | } | |
b7aaeae4 EG |
545 | mdelay(5); |
546 | } | |
547 | ||
eb7ff77e | 548 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
549 | |
550 | /* Stop device's DMA activity */ | |
7afe3705 | 551 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 | 552 | |
a812cba9 AB |
553 | if (trans->cfg->lp_xtal_workaround) { |
554 | iwl_pcie_apm_lp_xtal_enable(trans); | |
555 | return; | |
556 | } | |
557 | ||
870c2a11 | 558 | iwl_trans_pcie_sw_reset(trans); |
cc56feb2 EG |
559 | |
560 | /* | |
561 | * Clear "initialization complete" bit to move adapter from | |
562 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
563 | */ | |
564 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
a8cbb46f | 565 | BIT(trans->cfg->csr->flag_init_done)); |
cc56feb2 EG |
566 | } |
567 | ||
7afe3705 | 568 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 569 | { |
7b11488f | 570 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
52b6e168 | 571 | int ret; |
392f8b78 EG |
572 | |
573 | /* nic_init */ | |
7b70bd63 | 574 | spin_lock(&trans_pcie->irq_lock); |
52b6e168 | 575 | ret = iwl_pcie_apm_init(trans); |
7b70bd63 | 576 | spin_unlock(&trans_pcie->irq_lock); |
392f8b78 | 577 | |
52b6e168 EG |
578 | if (ret) |
579 | return ret; | |
580 | ||
95411d04 | 581 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 582 | |
ecdb975c | 583 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
584 | |
585 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 586 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
587 | |
588 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 589 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
590 | return -ENOMEM; |
591 | ||
035f7ff2 | 592 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 593 | /* enable shadow regs in HW */ |
20d3b647 | 594 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 595 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
596 | } |
597 | ||
392f8b78 EG |
598 | return 0; |
599 | } | |
600 | ||
601 | #define HW_READY_TIMEOUT (50) | |
602 | ||
603 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 604 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
605 | { |
606 | int ret; | |
607 | ||
1042db2a | 608 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 609 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
610 | |
611 | /* See if we got it */ | |
1042db2a | 612 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
613 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
614 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
615 | HW_READY_TIMEOUT); | |
392f8b78 | 616 | |
6a08f514 EG |
617 | if (ret >= 0) |
618 | iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); | |
619 | ||
6d8f6eeb | 620 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
621 | return ret; |
622 | } | |
623 | ||
624 | /* Note: returns standard 0/-ERROR code */ | |
eda50cde | 625 | int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
626 | { |
627 | int ret; | |
289e5501 | 628 | int t = 0; |
501fd989 | 629 | int iter; |
392f8b78 | 630 | |
6d8f6eeb | 631 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 632 | |
7afe3705 | 633 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 634 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
635 | if (ret >= 0) |
636 | return 0; | |
637 | ||
c9fdec9f EG |
638 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
639 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
192185d6 | 640 | usleep_range(1000, 2000); |
c9fdec9f | 641 | |
501fd989 EG |
642 | for (iter = 0; iter < 10; iter++) { |
643 | /* If HW is not ready, prepare the conditions to check again */ | |
644 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
645 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
646 | ||
647 | do { | |
648 | ret = iwl_pcie_set_hw_ready(trans); | |
03a19cbb EG |
649 | if (ret >= 0) |
650 | return 0; | |
392f8b78 | 651 | |
501fd989 EG |
652 | usleep_range(200, 1000); |
653 | t += 200; | |
654 | } while (t < 150000); | |
655 | msleep(25); | |
656 | } | |
392f8b78 | 657 | |
7f2ac8fb | 658 | IWL_ERR(trans, "Couldn't prepare the card\n"); |
392f8b78 | 659 | |
392f8b78 EG |
660 | return ret; |
661 | } | |
662 | ||
cf614297 EG |
663 | /* |
664 | * ucode | |
665 | */ | |
564cdce7 SS |
666 | static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, |
667 | u32 dst_addr, dma_addr_t phy_addr, | |
668 | u32 byte_cnt) | |
cf614297 | 669 | { |
bac842da EG |
670 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
671 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
672 | ||
673 | iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), | |
674 | dst_addr); | |
675 | ||
676 | iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
677 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
678 | ||
679 | iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), | |
680 | (iwl_get_dma_hi_addr(phy_addr) | |
681 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
682 | ||
683 | iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
684 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | | |
685 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | | |
686 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
687 | ||
688 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
689 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
690 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
691 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
564cdce7 SS |
692 | } |
693 | ||
564cdce7 SS |
694 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, |
695 | u32 dst_addr, dma_addr_t phy_addr, | |
696 | u32 byte_cnt) | |
697 | { | |
698 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
699 | unsigned long flags; | |
700 | int ret; | |
701 | ||
702 | trans_pcie->ucode_write_complete = false; | |
703 | ||
704 | if (!iwl_trans_grab_nic_access(trans, &flags)) | |
705 | return -EIO; | |
706 | ||
eda50cde SS |
707 | iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, |
708 | byte_cnt); | |
bac842da | 709 | iwl_trans_release_nic_access(trans, &flags); |
cf614297 | 710 | |
13df1aab JB |
711 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
712 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 713 | if (!ret) { |
83f84d7b | 714 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
fb12777a | 715 | iwl_trans_pcie_dump_regs(trans); |
cf614297 EG |
716 | return -ETIMEDOUT; |
717 | } | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
7afe3705 | 722 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 723 | const struct fw_desc *section) |
cf614297 | 724 | { |
83f84d7b JB |
725 | u8 *v_addr; |
726 | dma_addr_t p_addr; | |
baa21e83 | 727 | u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); |
cf614297 EG |
728 | int ret = 0; |
729 | ||
83f84d7b JB |
730 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
731 | section_num); | |
732 | ||
c571573a EG |
733 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
734 | GFP_KERNEL | __GFP_NOWARN); | |
735 | if (!v_addr) { | |
736 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
737 | chunk_sz = PAGE_SIZE; | |
738 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
739 | &p_addr, GFP_KERNEL); | |
740 | if (!v_addr) | |
741 | return -ENOMEM; | |
742 | } | |
83f84d7b | 743 | |
c571573a | 744 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
fe45773b AN |
745 | u32 copy_size, dst_addr; |
746 | bool extended_addr = false; | |
83f84d7b | 747 | |
c571573a | 748 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
fe45773b AN |
749 | dst_addr = section->offset + offset; |
750 | ||
751 | if (dst_addr >= IWL_FW_MEM_EXTENDED_START && | |
752 | dst_addr <= IWL_FW_MEM_EXTENDED_END) | |
753 | extended_addr = true; | |
754 | ||
755 | if (extended_addr) | |
756 | iwl_set_bits_prph(trans, LMPM_CHICK, | |
757 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
cf614297 | 758 | |
83f84d7b | 759 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
fe45773b AN |
760 | ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, |
761 | copy_size); | |
762 | ||
763 | if (extended_addr) | |
764 | iwl_clear_bits_prph(trans, LMPM_CHICK, | |
765 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
766 | ||
83f84d7b JB |
767 | if (ret) { |
768 | IWL_ERR(trans, | |
769 | "Could not load the [%d] uCode section\n", | |
770 | section_num); | |
771 | break; | |
6dfa8d01 | 772 | } |
83f84d7b JB |
773 | } |
774 | ||
c571573a | 775 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
776 | return ret; |
777 | } | |
778 | ||
5dd9c68a EG |
779 | static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, |
780 | const struct fw_img *image, | |
781 | int cpu, | |
782 | int *first_ucode_section) | |
e2d6f4e7 EH |
783 | { |
784 | int shift_param; | |
dcab8ecd EH |
785 | int i, ret = 0, sec_num = 0x1; |
786 | u32 val, last_read_idx = 0; | |
e2d6f4e7 EH |
787 | |
788 | if (cpu == 1) { | |
789 | shift_param = 0; | |
034846cf | 790 | *first_ucode_section = 0; |
e2d6f4e7 EH |
791 | } else { |
792 | shift_param = 16; | |
034846cf | 793 | (*first_ucode_section)++; |
e2d6f4e7 EH |
794 | } |
795 | ||
eef187a7 | 796 | for (i = *first_ucode_section; i < image->num_sec; i++) { |
034846cf EH |
797 | last_read_idx = i; |
798 | ||
a6c4fb44 MG |
799 | /* |
800 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between | |
801 | * CPU1 to CPU2. | |
802 | * PAGING_SEPARATOR_SECTION delimiter - separate between | |
803 | * CPU2 non paged to CPU2 paging sec. | |
804 | */ | |
034846cf | 805 | if (!image->sec[i].data || |
a6c4fb44 MG |
806 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
807 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { | |
034846cf EH |
808 | IWL_DEBUG_FW(trans, |
809 | "Break since Data not valid or Empty section, sec = %d\n", | |
810 | i); | |
189fa2fa | 811 | break; |
034846cf EH |
812 | } |
813 | ||
189fa2fa EH |
814 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
815 | if (ret) | |
816 | return ret; | |
dcab8ecd | 817 | |
d6a2c5c7 | 818 | /* Notify ucode of loaded section number and status */ |
eda50cde SS |
819 | val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); |
820 | val = val | (sec_num << shift_param); | |
821 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); | |
822 | ||
dcab8ecd | 823 | sec_num = (sec_num << 1) | 0x1; |
e2d6f4e7 EH |
824 | } |
825 | ||
034846cf EH |
826 | *first_ucode_section = last_read_idx; |
827 | ||
2aabdbdc EG |
828 | iwl_enable_interrupts(trans); |
829 | ||
d6a2c5c7 SS |
830 | if (trans->cfg->use_tfh) { |
831 | if (cpu == 1) | |
832 | iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, | |
833 | 0xFFFF); | |
834 | else | |
835 | iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, | |
836 | 0xFFFFFFFF); | |
837 | } else { | |
838 | if (cpu == 1) | |
839 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, | |
840 | 0xFFFF); | |
841 | else | |
842 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, | |
843 | 0xFFFFFFFF); | |
844 | } | |
afb88917 | 845 | |
189fa2fa EH |
846 | return 0; |
847 | } | |
e2d6f4e7 | 848 | |
189fa2fa EH |
849 | static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, |
850 | const struct fw_img *image, | |
034846cf EH |
851 | int cpu, |
852 | int *first_ucode_section) | |
189fa2fa | 853 | { |
189fa2fa | 854 | int i, ret = 0; |
034846cf | 855 | u32 last_read_idx = 0; |
189fa2fa | 856 | |
3ce4a038 | 857 | if (cpu == 1) |
034846cf | 858 | *first_ucode_section = 0; |
3ce4a038 | 859 | else |
034846cf | 860 | (*first_ucode_section)++; |
189fa2fa | 861 | |
eef187a7 | 862 | for (i = *first_ucode_section; i < image->num_sec; i++) { |
034846cf EH |
863 | last_read_idx = i; |
864 | ||
a6c4fb44 MG |
865 | /* |
866 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between | |
867 | * CPU1 to CPU2. | |
868 | * PAGING_SEPARATOR_SECTION delimiter - separate between | |
869 | * CPU2 non paged to CPU2 paging sec. | |
870 | */ | |
034846cf | 871 | if (!image->sec[i].data || |
a6c4fb44 MG |
872 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
873 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { | |
034846cf EH |
874 | IWL_DEBUG_FW(trans, |
875 | "Break since Data not valid or Empty section, sec = %d\n", | |
876 | i); | |
189fa2fa | 877 | break; |
034846cf EH |
878 | } |
879 | ||
189fa2fa EH |
880 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
881 | if (ret) | |
882 | return ret; | |
e2d6f4e7 EH |
883 | } |
884 | ||
034846cf EH |
885 | *first_ucode_section = last_read_idx; |
886 | ||
e2d6f4e7 EH |
887 | return 0; |
888 | } | |
889 | ||
c9be849d | 890 | void iwl_pcie_apply_destination(struct iwl_trans *trans) |
09e350f7 | 891 | { |
fd527eb5 | 892 | const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; |
09e350f7 LK |
893 | int i; |
894 | ||
7a14c23d SS |
895 | if (trans->ini_valid) { |
896 | if (!trans->num_blocks) | |
897 | return; | |
898 | ||
53032e6e SM |
899 | IWL_DEBUG_FW(trans, |
900 | "WRT: applying DRAM buffer[0] destination\n"); | |
ea695b7c ST |
901 | iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, |
902 | trans->fw_mon[0].physical >> | |
903 | MON_BUFF_SHIFT_VER2); | |
904 | iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, | |
905 | (trans->fw_mon[0].physical + | |
906 | trans->fw_mon[0].size - 256) >> | |
907 | MON_BUFF_SHIFT_VER2); | |
7a14c23d SS |
908 | return; |
909 | } | |
910 | ||
09e350f7 LK |
911 | IWL_INFO(trans, "Applying debug destination %s\n", |
912 | get_fw_dbg_mode_string(dest->monitor_mode)); | |
913 | ||
914 | if (dest->monitor_mode == EXTERNAL_MODE) | |
96c285da | 915 | iwl_pcie_alloc_fw_monitor(trans, dest->size_power); |
09e350f7 LK |
916 | else |
917 | IWL_WARN(trans, "PCI should have external buffer debug\n"); | |
918 | ||
17b809c9 | 919 | for (i = 0; i < trans->dbg_n_dest_reg; i++) { |
09e350f7 LK |
920 | u32 addr = le32_to_cpu(dest->reg_ops[i].addr); |
921 | u32 val = le32_to_cpu(dest->reg_ops[i].val); | |
922 | ||
923 | switch (dest->reg_ops[i].op) { | |
924 | case CSR_ASSIGN: | |
925 | iwl_write32(trans, addr, val); | |
926 | break; | |
927 | case CSR_SETBIT: | |
928 | iwl_set_bit(trans, addr, BIT(val)); | |
929 | break; | |
930 | case CSR_CLEARBIT: | |
931 | iwl_clear_bit(trans, addr, BIT(val)); | |
932 | break; | |
933 | case PRPH_ASSIGN: | |
934 | iwl_write_prph(trans, addr, val); | |
935 | break; | |
936 | case PRPH_SETBIT: | |
937 | iwl_set_bits_prph(trans, addr, BIT(val)); | |
938 | break; | |
939 | case PRPH_CLEARBIT: | |
940 | iwl_clear_bits_prph(trans, addr, BIT(val)); | |
941 | break; | |
869f3b15 HD |
942 | case PRPH_BLOCKBIT: |
943 | if (iwl_read_prph(trans, addr) & BIT(val)) { | |
944 | IWL_ERR(trans, | |
945 | "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", | |
946 | val, addr); | |
947 | goto monitor; | |
948 | } | |
949 | break; | |
09e350f7 LK |
950 | default: |
951 | IWL_ERR(trans, "FW debug - unknown OP %d\n", | |
952 | dest->reg_ops[i].op); | |
953 | break; | |
954 | } | |
955 | } | |
956 | ||
869f3b15 | 957 | monitor: |
88964b2e | 958 | if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) { |
09e350f7 | 959 | iwl_write_prph(trans, le32_to_cpu(dest->base_reg), |
88964b2e | 960 | trans->fw_mon[0].physical >> dest->base_shift); |
6e584873 | 961 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
62d7476d | 962 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), |
88964b2e SS |
963 | (trans->fw_mon[0].physical + |
964 | trans->fw_mon[0].size - 256) >> | |
62d7476d EG |
965 | dest->end_shift); |
966 | else | |
967 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), | |
88964b2e SS |
968 | (trans->fw_mon[0].physical + |
969 | trans->fw_mon[0].size) >> | |
62d7476d | 970 | dest->end_shift); |
09e350f7 LK |
971 | } |
972 | } | |
973 | ||
7afe3705 | 974 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 975 | const struct fw_img *image) |
cf614297 | 976 | { |
189fa2fa | 977 | int ret = 0; |
034846cf | 978 | int first_ucode_section; |
cf614297 | 979 | |
dcab8ecd | 980 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
e2d6f4e7 EH |
981 | image->is_dual_cpus ? "Dual" : "Single"); |
982 | ||
dcab8ecd EH |
983 | /* load to FW the binary non secured sections of CPU1 */ |
984 | ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); | |
985 | if (ret) | |
986 | return ret; | |
e2d6f4e7 EH |
987 | |
988 | if (image->is_dual_cpus) { | |
189fa2fa EH |
989 | /* set CPU2 header address */ |
990 | iwl_write_prph(trans, | |
991 | LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, | |
992 | LMPM_SECURE_CPU2_HDR_MEM_SPACE); | |
e2d6f4e7 | 993 | |
189fa2fa | 994 | /* load to FW the binary sections of CPU2 */ |
dcab8ecd EH |
995 | ret = iwl_pcie_load_cpu_sections(trans, image, 2, |
996 | &first_ucode_section); | |
189fa2fa EH |
997 | if (ret) |
998 | return ret; | |
e2d6f4e7 | 999 | } |
cf614297 | 1000 | |
c2d20201 EG |
1001 | /* supported for 7000 only for the moment */ |
1002 | if (iwlwifi_mod_params.fw_monitor && | |
1003 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { | |
96c285da | 1004 | iwl_pcie_alloc_fw_monitor(trans, 0); |
c2d20201 | 1005 | |
88964b2e | 1006 | if (trans->fw_mon[0].size) { |
c2d20201 | 1007 | iwl_write_prph(trans, MON_BUFF_BASE_ADDR, |
88964b2e | 1008 | trans->fw_mon[0].physical >> 4); |
c2d20201 | 1009 | iwl_write_prph(trans, MON_BUFF_END_ADDR, |
88964b2e SS |
1010 | (trans->fw_mon[0].physical + |
1011 | trans->fw_mon[0].size) >> 4); | |
c2d20201 | 1012 | } |
7a14c23d | 1013 | } else if (iwl_pcie_dbg_on(trans)) { |
09e350f7 | 1014 | iwl_pcie_apply_destination(trans); |
c2d20201 EG |
1015 | } |
1016 | ||
2aabdbdc EG |
1017 | iwl_enable_interrupts(trans); |
1018 | ||
e12ba844 | 1019 | /* release CPU reset */ |
5dd9c68a | 1020 | iwl_write32(trans, CSR_RESET, 0); |
e12ba844 | 1021 | |
dcab8ecd EH |
1022 | return 0; |
1023 | } | |
189fa2fa | 1024 | |
5dd9c68a EG |
1025 | static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, |
1026 | const struct fw_img *image) | |
dcab8ecd EH |
1027 | { |
1028 | int ret = 0; | |
1029 | int first_ucode_section; | |
dcab8ecd EH |
1030 | |
1031 | IWL_DEBUG_FW(trans, "working with %s CPU\n", | |
1032 | image->is_dual_cpus ? "Dual" : "Single"); | |
1033 | ||
7a14c23d | 1034 | if (iwl_pcie_dbg_on(trans)) |
a2227ce2 EG |
1035 | iwl_pcie_apply_destination(trans); |
1036 | ||
82ea7966 SS |
1037 | IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", |
1038 | iwl_read_prph(trans, WFPM_GP2)); | |
1039 | ||
1040 | /* | |
1041 | * Set default value. On resume reading the values that were | |
1042 | * zeored can provide debug data on the resume flow. | |
1043 | * This is for debugging only and has no functional impact. | |
1044 | */ | |
1045 | iwl_write_prph(trans, WFPM_GP2, 0x01010101); | |
1046 | ||
dcab8ecd EH |
1047 | /* configure the ucode to be ready to get the secured image */ |
1048 | /* release CPU reset */ | |
1049 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); | |
1050 | ||
1051 | /* load to FW the binary Secured sections of CPU1 */ | |
5dd9c68a EG |
1052 | ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, |
1053 | &first_ucode_section); | |
dcab8ecd EH |
1054 | if (ret) |
1055 | return ret; | |
1056 | ||
1057 | /* load to FW the binary sections of CPU2 */ | |
47dbab26 EG |
1058 | return iwl_pcie_load_cpu_sections_8000(trans, image, 2, |
1059 | &first_ucode_section); | |
cf614297 EG |
1060 | } |
1061 | ||
9ad8fd0b | 1062 | bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) |
727c02df | 1063 | { |
326477e4 | 1064 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
727c02df | 1065 | bool hw_rfkill = iwl_is_rfkill_set(trans); |
326477e4 JB |
1066 | bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); |
1067 | bool report; | |
727c02df | 1068 | |
326477e4 JB |
1069 | if (hw_rfkill) { |
1070 | set_bit(STATUS_RFKILL_HW, &trans->status); | |
1071 | set_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1072 | } else { | |
1073 | clear_bit(STATUS_RFKILL_HW, &trans->status); | |
1074 | if (trans_pcie->opmode_down) | |
1075 | clear_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1076 | } | |
1077 | ||
1078 | report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
727c02df | 1079 | |
326477e4 JB |
1080 | if (prev != report) |
1081 | iwl_trans_pcie_rf_kill(trans, report); | |
727c02df SS |
1082 | |
1083 | return hw_rfkill; | |
1084 | } | |
1085 | ||
7ca00409 HD |
1086 | struct iwl_causes_list { |
1087 | u32 cause_num; | |
1088 | u32 mask_reg; | |
1089 | u8 addr; | |
1090 | }; | |
1091 | ||
1092 | static struct iwl_causes_list causes_list[] = { | |
1093 | {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, | |
1094 | {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, | |
1095 | {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, | |
1096 | {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, | |
1097 | {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, | |
1098 | {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, | |
ff911dca | 1099 | {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, |
7ca00409 HD |
1100 | {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, |
1101 | {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, | |
1102 | {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, | |
1103 | {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, | |
1104 | {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, | |
1105 | {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, | |
1106 | {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, | |
1107 | {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, | |
1108 | }; | |
1109 | ||
9b58419e GBA |
1110 | static struct iwl_causes_list causes_list_v2[] = { |
1111 | {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, | |
1112 | {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, | |
1113 | {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, | |
1114 | {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, | |
1115 | {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, | |
1116 | {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, | |
1117 | {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, | |
1118 | {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, | |
1119 | {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, | |
1120 | {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, | |
1121 | {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, | |
1122 | {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, | |
1123 | {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, | |
1124 | {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, | |
1125 | }; | |
1126 | ||
7ca00409 HD |
1127 | static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) |
1128 | { | |
1129 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1130 | int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; | |
9b58419e | 1131 | int i, arr_size = |
ff911dca | 1132 | (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? |
9b58419e | 1133 | ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); |
7ca00409 HD |
1134 | |
1135 | /* | |
1136 | * Access all non RX causes and map them to the default irq. | |
1137 | * In case we are missing at least one interrupt vector, | |
1138 | * the first interrupt vector will serve non-RX and FBQ causes. | |
1139 | */ | |
9b58419e GBA |
1140 | for (i = 0; i < arr_size; i++) { |
1141 | struct iwl_causes_list *causes = | |
ff911dca | 1142 | (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? |
9b58419e GBA |
1143 | causes_list : causes_list_v2; |
1144 | ||
1145 | iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); | |
1146 | iwl_clear_bit(trans, causes[i].mask_reg, | |
1147 | causes[i].cause_num); | |
7ca00409 HD |
1148 | } |
1149 | } | |
1150 | ||
1151 | static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) | |
1152 | { | |
1153 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1154 | u32 offset = | |
1155 | trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; | |
1156 | u32 val, idx; | |
1157 | ||
1158 | /* | |
1159 | * The first RX queue - fallback queue, which is designated for | |
1160 | * management frame, command responses etc, is always mapped to the | |
1161 | * first interrupt vector. The other RX queues are mapped to | |
1162 | * the other (N - 2) interrupt vectors. | |
1163 | */ | |
1164 | val = BIT(MSIX_FH_INT_CAUSES_Q(0)); | |
1165 | for (idx = 1; idx < trans->num_rx_queues; idx++) { | |
1166 | iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), | |
1167 | MSIX_FH_INT_CAUSES_Q(idx - offset)); | |
1168 | val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); | |
1169 | } | |
1170 | iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); | |
1171 | ||
1172 | val = MSIX_FH_INT_CAUSES_Q(0); | |
1173 | if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) | |
1174 | val |= MSIX_NON_AUTO_CLEAR_CAUSE; | |
1175 | iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); | |
1176 | ||
1177 | if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) | |
1178 | iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); | |
1179 | } | |
1180 | ||
77c09bc8 | 1181 | void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) |
7ca00409 HD |
1182 | { |
1183 | struct iwl_trans *trans = trans_pcie->trans; | |
1184 | ||
1185 | if (!trans_pcie->msix_enabled) { | |
d7270d61 HD |
1186 | if (trans->cfg->mq_rx_supported && |
1187 | test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
ea695b7c ST |
1188 | iwl_write_umac_prph(trans, UREG_CHICK, |
1189 | UREG_CHICK_MSI_ENABLE); | |
7ca00409 HD |
1190 | return; |
1191 | } | |
d7270d61 HD |
1192 | /* |
1193 | * The IVAR table needs to be configured again after reset, | |
1194 | * but if the device is disabled, we can't write to | |
1195 | * prph. | |
1196 | */ | |
1197 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
ea695b7c | 1198 | iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); |
7ca00409 HD |
1199 | |
1200 | /* | |
1201 | * Each cause from the causes list above and the RX causes is | |
1202 | * represented as a byte in the IVAR table. The first nibble | |
1203 | * represents the bound interrupt vector of the cause, the second | |
1204 | * represents no auto clear for this cause. This will be set if its | |
1205 | * interrupt vector is bound to serve other causes. | |
1206 | */ | |
1207 | iwl_pcie_map_rx_causes(trans); | |
1208 | ||
1209 | iwl_pcie_map_non_rx_causes(trans); | |
83730058 HD |
1210 | } |
1211 | ||
1212 | static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) | |
1213 | { | |
1214 | struct iwl_trans *trans = trans_pcie->trans; | |
1215 | ||
1216 | iwl_pcie_conf_msix_hw(trans_pcie); | |
7ca00409 | 1217 | |
83730058 HD |
1218 | if (!trans_pcie->msix_enabled) |
1219 | return; | |
1220 | ||
1221 | trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); | |
7ca00409 | 1222 | trans_pcie->fh_mask = trans_pcie->fh_init_mask; |
83730058 | 1223 | trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); |
7ca00409 HD |
1224 | trans_pcie->hw_mask = trans_pcie->hw_init_mask; |
1225 | } | |
1226 | ||
fa9f3281 | 1227 | static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) |
ae2c30bf | 1228 | { |
43e58856 | 1229 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3dc3374f | 1230 | |
fa9f3281 EG |
1231 | lockdep_assert_held(&trans_pcie->mutex); |
1232 | ||
1233 | if (trans_pcie->is_down) | |
1234 | return; | |
1235 | ||
1236 | trans_pcie->is_down = true; | |
1237 | ||
0232d2cd | 1238 | /* Stop dbgc before stopping device */ |
5cfe79c8 | 1239 | _iwl_fw_dbg_stop_recording(trans, NULL); |
0232d2cd | 1240 | |
43e58856 | 1241 | /* tell the device to stop sending interrupts */ |
ae2c30bf | 1242 | iwl_disable_interrupts(trans); |
ae2c30bf | 1243 | |
ab6cf8e8 | 1244 | /* device going down, Stop using ICT table */ |
990aa6d7 | 1245 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
1246 | |
1247 | /* | |
1248 | * If a HW restart happens during firmware loading, | |
1249 | * then the firmware loading might call this function | |
1250 | * and later it might be called again due to the | |
1251 | * restart. So don't process again if the device is | |
1252 | * already dead. | |
1253 | */ | |
31b8b343 | 1254 | if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
a6bd005f EG |
1255 | IWL_DEBUG_INFO(trans, |
1256 | "DEVICE_ENABLED bit was set and is now cleared\n"); | |
f02831be | 1257 | iwl_pcie_tx_stop(trans); |
9805c446 | 1258 | iwl_pcie_rx_stop(trans); |
6379103e | 1259 | |
ab6cf8e8 | 1260 | /* Power-down device's busmaster DMA clocks */ |
95411d04 | 1261 | if (!trans->cfg->apmg_not_supported) { |
1aa02b5a AA |
1262 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
1263 | APMG_CLK_VAL_DMA_CLK_RQT); | |
1264 | udelay(5); | |
1265 | } | |
ab6cf8e8 EG |
1266 | } |
1267 | ||
1268 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1269 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
a8cbb46f | 1270 | BIT(trans->cfg->csr->flag_mac_access_req)); |
ab6cf8e8 EG |
1271 | |
1272 | /* Stop the device, and put it in low power state */ | |
b7aaeae4 | 1273 | iwl_pcie_apm_stop(trans, false); |
43e58856 | 1274 | |
870c2a11 | 1275 | iwl_trans_pcie_sw_reset(trans); |
03d6c3b0 | 1276 | |
f4a1f04a GBA |
1277 | /* |
1278 | * Upon stop, the IVAR table gets erased, so msi-x won't | |
1279 | * work. This causes a bug in RF-KILL flows, since the interrupt | |
1280 | * that enables radio won't fire on the correct irq, and the | |
1281 | * driver won't be able to handle the interrupt. | |
1282 | * Configure the IVAR table again after reset. | |
1283 | */ | |
1284 | iwl_pcie_conf_msix_hw(trans_pcie); | |
1285 | ||
03d6c3b0 EG |
1286 | /* |
1287 | * Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1288 | * This is a bug in certain verions of the hardware. | |
1289 | * Certain devices also keep sending HW RF kill interrupt all | |
1290 | * the time, unless the interrupt is ACKed even if the interrupt | |
1291 | * should be masked. Re-ACK all the interrupts here. | |
43e58856 | 1292 | */ |
43e58856 | 1293 | iwl_disable_interrupts(trans); |
43e58856 | 1294 | |
74fda971 | 1295 | /* clear all status bits */ |
eb7ff77e AN |
1296 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
1297 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
eb7ff77e | 1298 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
a4082843 AN |
1299 | |
1300 | /* | |
1301 | * Even if we stop the HW, we still want the RF kill | |
1302 | * interrupt | |
1303 | */ | |
1304 | iwl_enable_rfkill_int(trans); | |
1305 | ||
a6bd005f | 1306 | /* re-take ownership to prevent other users from stealing the device */ |
655e5cf0 | 1307 | iwl_pcie_prepare_card_hw(trans); |
14cfca71 JB |
1308 | } |
1309 | ||
eda50cde | 1310 | void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) |
2e5d4a8f HD |
1311 | { |
1312 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1313 | ||
1314 | if (trans_pcie->msix_enabled) { | |
1315 | int i; | |
1316 | ||
496d83ca | 1317 | for (i = 0; i < trans_pcie->alloc_vecs; i++) |
2e5d4a8f HD |
1318 | synchronize_irq(trans_pcie->msix_entries[i].vector); |
1319 | } else { | |
1320 | synchronize_irq(trans_pcie->pci_dev->irq); | |
1321 | } | |
1322 | } | |
1323 | ||
a6bd005f EG |
1324 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
1325 | const struct fw_img *fw, bool run_in_rfkill) | |
1326 | { | |
1327 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1328 | bool hw_rfkill; | |
1329 | int ret; | |
1330 | ||
1331 | /* This may fail if AMT took ownership of the device */ | |
1332 | if (iwl_pcie_prepare_card_hw(trans)) { | |
1333 | IWL_WARN(trans, "Exit HW not ready\n"); | |
1334 | ret = -EIO; | |
1335 | goto out; | |
1336 | } | |
1337 | ||
1338 | iwl_enable_rfkill_int(trans); | |
1339 | ||
1340 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
1341 | ||
1342 | /* | |
1343 | * We enabled the RF-Kill interrupt and the handler may very | |
1344 | * well be running. Disable the interrupts to make sure no other | |
1345 | * interrupt can be fired. | |
1346 | */ | |
1347 | iwl_disable_interrupts(trans); | |
1348 | ||
1349 | /* Make sure it finished running */ | |
2e5d4a8f | 1350 | iwl_pcie_synchronize_irqs(trans); |
a6bd005f EG |
1351 | |
1352 | mutex_lock(&trans_pcie->mutex); | |
1353 | ||
1354 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
9ad8fd0b | 1355 | hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); |
a6bd005f EG |
1356 | if (hw_rfkill && !run_in_rfkill) { |
1357 | ret = -ERFKILL; | |
1358 | goto out; | |
1359 | } | |
1360 | ||
1361 | /* Someone called stop_device, don't try to start_fw */ | |
1362 | if (trans_pcie->is_down) { | |
1363 | IWL_WARN(trans, | |
1364 | "Can't start_fw since the HW hasn't been started\n"); | |
20aa99bb | 1365 | ret = -EIO; |
a6bd005f EG |
1366 | goto out; |
1367 | } | |
1368 | ||
1369 | /* make sure rfkill handshake bits are cleared */ | |
1370 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1371 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
1372 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | |
1373 | ||
1374 | /* clear (again), then enable host interrupts */ | |
1375 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
1376 | ||
1377 | ret = iwl_pcie_nic_init(trans); | |
1378 | if (ret) { | |
1379 | IWL_ERR(trans, "Unable to init nic\n"); | |
1380 | goto out; | |
1381 | } | |
1382 | ||
1383 | /* | |
1384 | * Now, we load the firmware and don't want to be interrupted, even | |
1385 | * by the RF-Kill interrupt (hence mask all the interrupt besides the | |
1386 | * FH_TX interrupt which is needed to load the firmware). If the | |
1387 | * RF-Kill switch is toggled, we will find out after having loaded | |
1388 | * the firmware and return the proper value to the caller. | |
1389 | */ | |
1390 | iwl_enable_fw_load_int(trans); | |
1391 | ||
1392 | /* really make sure rfkill handshake bits are cleared */ | |
1393 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1394 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1395 | ||
1396 | /* Load the given image to the HW */ | |
6e584873 | 1397 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
a6bd005f EG |
1398 | ret = iwl_pcie_load_given_ucode_8000(trans, fw); |
1399 | else | |
1400 | ret = iwl_pcie_load_given_ucode(trans, fw); | |
a6bd005f EG |
1401 | |
1402 | /* re-check RF-Kill state since we may have missed the interrupt */ | |
9ad8fd0b | 1403 | hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); |
a6bd005f EG |
1404 | if (hw_rfkill && !run_in_rfkill) |
1405 | ret = -ERFKILL; | |
1406 | ||
1407 | out: | |
1408 | mutex_unlock(&trans_pcie->mutex); | |
1409 | return ret; | |
1410 | } | |
1411 | ||
1412 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) | |
1413 | { | |
1414 | iwl_pcie_reset_ict(trans); | |
1415 | iwl_pcie_tx_start(trans, scd_addr); | |
1416 | } | |
1417 | ||
326477e4 JB |
1418 | void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, |
1419 | bool was_in_rfkill) | |
1420 | { | |
1421 | bool hw_rfkill; | |
1422 | ||
1423 | /* | |
1424 | * Check again since the RF kill state may have changed while | |
1425 | * all the interrupts were disabled, in this case we couldn't | |
1426 | * receive the RF kill interrupt and update the state in the | |
1427 | * op_mode. | |
1428 | * Don't call the op_mode if the rkfill state hasn't changed. | |
1429 | * This allows the op_mode to call stop_device from the rfkill | |
1430 | * notification without endless recursion. Under very rare | |
1431 | * circumstances, we might have a small recursion if the rfkill | |
1432 | * state changed exactly now while we were called from stop_device. | |
1433 | * This is very unlikely but can happen and is supported. | |
1434 | */ | |
1435 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1436 | if (hw_rfkill) { | |
1437 | set_bit(STATUS_RFKILL_HW, &trans->status); | |
1438 | set_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1439 | } else { | |
1440 | clear_bit(STATUS_RFKILL_HW, &trans->status); | |
1441 | clear_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
1442 | } | |
1443 | if (hw_rfkill != was_in_rfkill) | |
1444 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); | |
1445 | } | |
1446 | ||
fa9f3281 EG |
1447 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) |
1448 | { | |
1449 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
326477e4 | 1450 | bool was_in_rfkill; |
fa9f3281 EG |
1451 | |
1452 | mutex_lock(&trans_pcie->mutex); | |
326477e4 JB |
1453 | trans_pcie->opmode_down = true; |
1454 | was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); | |
fa9f3281 | 1455 | _iwl_trans_pcie_stop_device(trans, low_power); |
326477e4 | 1456 | iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); |
fa9f3281 EG |
1457 | mutex_unlock(&trans_pcie->mutex); |
1458 | } | |
1459 | ||
14cfca71 JB |
1460 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) |
1461 | { | |
fa9f3281 EG |
1462 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1463 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1464 | ||
1465 | lockdep_assert_held(&trans_pcie->mutex); | |
1466 | ||
326477e4 JB |
1467 | IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", |
1468 | state ? "disabled" : "enabled"); | |
77c09bc8 SS |
1469 | if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { |
1470 | if (trans->cfg->gen2) | |
1471 | _iwl_trans_pcie_gen2_stop_device(trans, true); | |
1472 | else | |
1473 | _iwl_trans_pcie_stop_device(trans, true); | |
1474 | } | |
ab6cf8e8 EG |
1475 | } |
1476 | ||
23ae6128 MG |
1477 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, |
1478 | bool reset) | |
2dd4f9f7 | 1479 | { |
23ae6128 | 1480 | if (!reset) { |
6dfb36c8 EP |
1481 | /* Enable persistence mode to avoid reset */ |
1482 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
1483 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
1484 | } | |
1485 | ||
2dd4f9f7 | 1486 | iwl_disable_interrupts(trans); |
debff618 JB |
1487 | |
1488 | /* | |
1489 | * in testing mode, the host stays awake and the | |
1490 | * hardware won't be reset (not even partially) | |
1491 | */ | |
1492 | if (test) | |
1493 | return; | |
1494 | ||
ddaf5a5b JB |
1495 | iwl_pcie_disable_ict(trans); |
1496 | ||
2e5d4a8f | 1497 | iwl_pcie_synchronize_irqs(trans); |
33b56af1 | 1498 | |
2dd4f9f7 | 1499 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
a8cbb46f | 1500 | BIT(trans->cfg->csr->flag_mac_access_req)); |
ddaf5a5b | 1501 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
a8cbb46f | 1502 | BIT(trans->cfg->csr->flag_init_done)); |
ddaf5a5b | 1503 | |
23ae6128 | 1504 | if (reset) { |
6dfb36c8 EP |
1505 | /* |
1506 | * reset TX queues -- some of their registers reset during S3 | |
1507 | * so if we don't reset everything here the D3 image would try | |
1508 | * to execute some invalid memory upon resume | |
1509 | */ | |
1510 | iwl_trans_pcie_tx_reset(trans); | |
1511 | } | |
ddaf5a5b JB |
1512 | |
1513 | iwl_pcie_set_pwr(trans, true); | |
1514 | } | |
1515 | ||
1516 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 | 1517 | enum iwl_d3_status *status, |
23ae6128 | 1518 | bool test, bool reset) |
ddaf5a5b | 1519 | { |
d7270d61 | 1520 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ddaf5a5b JB |
1521 | u32 val; |
1522 | int ret; | |
1523 | ||
debff618 JB |
1524 | if (test) { |
1525 | iwl_enable_interrupts(trans); | |
1526 | *status = IWL_D3_STATUS_ALIVE; | |
1527 | return 0; | |
1528 | } | |
1529 | ||
a8cbb46f GBA |
1530 | iwl_set_bit(trans, CSR_GP_CNTRL, |
1531 | BIT(trans->cfg->csr->flag_mac_access_req)); | |
ddaf5a5b | 1532 | |
c96b5eec JB |
1533 | ret = iwl_finish_nic_init(trans); |
1534 | if (ret) | |
ddaf5a5b | 1535 | return ret; |
ddaf5a5b | 1536 | |
f98ad635 EG |
1537 | /* |
1538 | * Reconfigure IVAR table in case of MSIX or reset ict table in | |
1539 | * MSI mode since HW reset erased it. | |
1540 | * Also enables interrupts - none will happen as | |
1541 | * the device doesn't know we're waking it up, only when | |
1542 | * the opmode actually tells it after this call. | |
1543 | */ | |
1544 | iwl_pcie_conf_msix_hw(trans_pcie); | |
1545 | if (!trans_pcie->msix_enabled) | |
1546 | iwl_pcie_reset_ict(trans); | |
1547 | iwl_enable_interrupts(trans); | |
1548 | ||
a3ead656 EG |
1549 | iwl_pcie_set_pwr(trans, false); |
1550 | ||
23ae6128 | 1551 | if (!reset) { |
6dfb36c8 | 1552 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
a8cbb46f | 1553 | BIT(trans->cfg->csr->flag_mac_access_req)); |
6dfb36c8 EP |
1554 | } else { |
1555 | iwl_trans_pcie_tx_reset(trans); | |
ddaf5a5b | 1556 | |
6dfb36c8 EP |
1557 | ret = iwl_pcie_rx_init(trans); |
1558 | if (ret) { | |
1559 | IWL_ERR(trans, | |
1560 | "Failed to resume the device (RX reset)\n"); | |
1561 | return ret; | |
1562 | } | |
ddaf5a5b JB |
1563 | } |
1564 | ||
82ea7966 | 1565 | IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", |
ea695b7c | 1566 | iwl_read_umac_prph(trans, WFPM_GP2)); |
82ea7966 | 1567 | |
a3ead656 EG |
1568 | val = iwl_read32(trans, CSR_RESET); |
1569 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) | |
1570 | *status = IWL_D3_STATUS_RESET; | |
1571 | else | |
1572 | *status = IWL_D3_STATUS_ALIVE; | |
1573 | ||
ddaf5a5b | 1574 | return 0; |
2dd4f9f7 JB |
1575 | } |
1576 | ||
2e5d4a8f HD |
1577 | static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, |
1578 | struct iwl_trans *trans) | |
1579 | { | |
1580 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
ab1068d6 | 1581 | int max_irqs, num_irqs, i, ret; |
2e5d4a8f | 1582 | u16 pci_cmd; |
2e5d4a8f | 1583 | |
06f4b081 SS |
1584 | if (!trans->cfg->mq_rx_supported) |
1585 | goto enable_msi; | |
1586 | ||
ab1068d6 | 1587 | max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); |
06f4b081 SS |
1588 | for (i = 0; i < max_irqs; i++) |
1589 | trans_pcie->msix_entries[i].entry = i; | |
496d83ca | 1590 | |
06f4b081 SS |
1591 | num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, |
1592 | MSIX_MIN_INTERRUPT_VECTORS, | |
1593 | max_irqs); | |
1594 | if (num_irqs < 0) { | |
2e5d4a8f | 1595 | IWL_DEBUG_INFO(trans, |
06f4b081 SS |
1596 | "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", |
1597 | num_irqs); | |
1598 | goto enable_msi; | |
1599 | } | |
1600 | trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; | |
496d83ca | 1601 | |
06f4b081 SS |
1602 | IWL_DEBUG_INFO(trans, |
1603 | "MSI-X enabled. %d interrupt vectors were allocated\n", | |
1604 | num_irqs); | |
1605 | ||
1606 | /* | |
1607 | * In case the OS provides fewer interrupts than requested, different | |
1608 | * causes will share the same interrupt vector as follows: | |
1609 | * One interrupt less: non rx causes shared with FBQ. | |
1610 | * Two interrupts less: non rx causes shared with FBQ and RSS. | |
1611 | * More than two interrupts: we will use fewer RSS queues. | |
1612 | */ | |
ab1068d6 | 1613 | if (num_irqs <= max_irqs - 2) { |
06f4b081 SS |
1614 | trans_pcie->trans->num_rx_queues = num_irqs + 1; |
1615 | trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | | |
1616 | IWL_SHARED_IRQ_FIRST_RSS; | |
ab1068d6 | 1617 | } else if (num_irqs == max_irqs - 1) { |
06f4b081 SS |
1618 | trans_pcie->trans->num_rx_queues = num_irqs; |
1619 | trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; | |
1620 | } else { | |
1621 | trans_pcie->trans->num_rx_queues = num_irqs - 1; | |
2e5d4a8f | 1622 | } |
ab1068d6 | 1623 | WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); |
2e5d4a8f | 1624 | |
06f4b081 SS |
1625 | trans_pcie->alloc_vecs = num_irqs; |
1626 | trans_pcie->msix_enabled = true; | |
1627 | return; | |
1628 | ||
1629 | enable_msi: | |
1630 | ret = pci_enable_msi(pdev); | |
1631 | if (ret) { | |
1632 | dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); | |
2e5d4a8f HD |
1633 | /* enable rfkill interrupt: hw bug w/a */ |
1634 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1635 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1636 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1637 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1638 | } | |
1639 | } | |
1640 | } | |
1641 | ||
7c8d91eb HD |
1642 | static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) |
1643 | { | |
1644 | int iter_rx_q, i, ret, cpu, offset; | |
1645 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1646 | ||
1647 | i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; | |
1648 | iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; | |
1649 | offset = 1 + i; | |
1650 | for (; i < iter_rx_q ; i++) { | |
1651 | /* | |
1652 | * Get the cpu prior to the place to search | |
1653 | * (i.e. return will be > i - 1). | |
1654 | */ | |
1655 | cpu = cpumask_next(i - offset, cpu_online_mask); | |
1656 | cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); | |
1657 | ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, | |
1658 | &trans_pcie->affinity_mask[i]); | |
1659 | if (ret) | |
1660 | IWL_ERR(trans_pcie->trans, | |
1661 | "Failed to set affinity mask for IRQ %d\n", | |
1662 | i); | |
1663 | } | |
1664 | } | |
1665 | ||
2e5d4a8f HD |
1666 | static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, |
1667 | struct iwl_trans_pcie *trans_pcie) | |
1668 | { | |
496d83ca | 1669 | int i; |
2e5d4a8f | 1670 | |
496d83ca | 1671 | for (i = 0; i < trans_pcie->alloc_vecs; i++) { |
2e5d4a8f | 1672 | int ret; |
5a41a86c | 1673 | struct msix_entry *msix_entry; |
64fa3aff SD |
1674 | const char *qname = queue_name(&pdev->dev, trans_pcie, i); |
1675 | ||
1676 | if (!qname) | |
1677 | return -ENOMEM; | |
5a41a86c SD |
1678 | |
1679 | msix_entry = &trans_pcie->msix_entries[i]; | |
1680 | ret = devm_request_threaded_irq(&pdev->dev, | |
1681 | msix_entry->vector, | |
1682 | iwl_pcie_msix_isr, | |
1683 | (i == trans_pcie->def_irq) ? | |
1684 | iwl_pcie_irq_msix_handler : | |
1685 | iwl_pcie_irq_rx_msix_handler, | |
1686 | IRQF_SHARED, | |
64fa3aff | 1687 | qname, |
5a41a86c | 1688 | msix_entry); |
2e5d4a8f | 1689 | if (ret) { |
2e5d4a8f HD |
1690 | IWL_ERR(trans_pcie->trans, |
1691 | "Error allocating IRQ %d\n", i); | |
5a41a86c | 1692 | |
2e5d4a8f HD |
1693 | return ret; |
1694 | } | |
1695 | } | |
7c8d91eb | 1696 | iwl_pcie_irq_set_affinity(trans_pcie->trans); |
2e5d4a8f HD |
1697 | |
1698 | return 0; | |
1699 | } | |
1700 | ||
fa9f3281 | 1701 | static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) |
e6bb4c9c | 1702 | { |
fa9f3281 | 1703 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8954e1eb | 1704 | u32 hpm; |
a8b691e6 | 1705 | int err; |
e6bb4c9c | 1706 | |
fa9f3281 EG |
1707 | lockdep_assert_held(&trans_pcie->mutex); |
1708 | ||
7afe3705 | 1709 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 1710 | if (err) { |
d6f1c316 | 1711 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 1712 | return err; |
ebb7678d | 1713 | } |
a6c684ee | 1714 | |
ea695b7c | 1715 | hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); |
8954e1eb | 1716 | if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { |
ea695b7c ST |
1717 | int wfpm_val = iwl_read_umac_prph_no_grab(trans, |
1718 | PREG_PRPH_WPROT_0); | |
1719 | ||
1720 | if (wfpm_val & PREG_WFPM_ACCESS) { | |
8954e1eb SM |
1721 | IWL_ERR(trans, |
1722 | "Error, can not clear persistence bit\n"); | |
1723 | return -EPERM; | |
1724 | } | |
ea695b7c ST |
1725 | iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, |
1726 | hpm & ~PERSISTENCE_BIT); | |
8954e1eb SM |
1727 | } |
1728 | ||
870c2a11 | 1729 | iwl_trans_pcie_sw_reset(trans); |
2997494f | 1730 | |
52b6e168 EG |
1731 | err = iwl_pcie_apm_init(trans); |
1732 | if (err) | |
1733 | return err; | |
a6c684ee | 1734 | |
2e5d4a8f | 1735 | iwl_pcie_init_msix(trans_pcie); |
83730058 | 1736 | |
226c02ca EG |
1737 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1738 | iwl_enable_rfkill_int(trans); | |
1739 | ||
326477e4 JB |
1740 | trans_pcie->opmode_down = false; |
1741 | ||
fa9f3281 EG |
1742 | /* Set is_down to false here so that...*/ |
1743 | trans_pcie->is_down = false; | |
1744 | ||
727c02df | 1745 | /* ...rfkill can call stop_device and set it false if needed */ |
9ad8fd0b | 1746 | iwl_pcie_check_hw_rf_kill(trans); |
d48e2074 | 1747 | |
4cbb8e50 LC |
1748 | /* Make sure we sync here, because we'll need full access later */ |
1749 | if (low_power) | |
1750 | pm_runtime_resume(trans->dev); | |
1751 | ||
a8b691e6 | 1752 | return 0; |
e6bb4c9c EG |
1753 | } |
1754 | ||
fa9f3281 EG |
1755 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) |
1756 | { | |
1757 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1758 | int ret; | |
1759 | ||
1760 | mutex_lock(&trans_pcie->mutex); | |
1761 | ret = _iwl_trans_pcie_start_hw(trans, low_power); | |
1762 | mutex_unlock(&trans_pcie->mutex); | |
1763 | ||
1764 | return ret; | |
1765 | } | |
1766 | ||
a4082843 | 1767 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 1768 | { |
20d3b647 | 1769 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1770 | |
fa9f3281 EG |
1771 | mutex_lock(&trans_pcie->mutex); |
1772 | ||
a4082843 | 1773 | /* disable interrupts - don't enable HW RF kill interrupt */ |
ee7d737c | 1774 | iwl_disable_interrupts(trans); |
ee7d737c | 1775 | |
b7aaeae4 | 1776 | iwl_pcie_apm_stop(trans, true); |
cc56feb2 | 1777 | |
218733cf | 1778 | iwl_disable_interrupts(trans); |
1df06bdc | 1779 | |
8d96bb61 | 1780 | iwl_pcie_disable_ict(trans); |
33b56af1 | 1781 | |
fa9f3281 | 1782 | mutex_unlock(&trans_pcie->mutex); |
33b56af1 | 1783 | |
2e5d4a8f | 1784 | iwl_pcie_synchronize_irqs(trans); |
cc56feb2 EG |
1785 | } |
1786 | ||
03905495 EG |
1787 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1788 | { | |
05f5b97e | 1789 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1790 | } |
1791 | ||
1792 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1793 | { | |
05f5b97e | 1794 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1795 | } |
1796 | ||
1797 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1798 | { | |
05f5b97e | 1799 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1800 | } |
1801 | ||
84fb372c SS |
1802 | static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) |
1803 | { | |
1804 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) | |
1805 | return 0x00FFFFFF; | |
1806 | else | |
1807 | return 0x000FFFFF; | |
1808 | } | |
1809 | ||
6a06b6c1 EG |
1810 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
1811 | { | |
84fb372c SS |
1812 | u32 mask = iwl_trans_pcie_prph_msk(trans); |
1813 | ||
f9477c17 | 1814 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
84fb372c | 1815 | ((reg & mask) | (3 << 24))); |
6a06b6c1 EG |
1816 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
1817 | } | |
1818 | ||
1819 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
1820 | u32 val) | |
1821 | { | |
84fb372c SS |
1822 | u32 mask = iwl_trans_pcie_prph_msk(trans); |
1823 | ||
6a06b6c1 | 1824 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, |
84fb372c | 1825 | ((addr & mask) | (3 << 24))); |
6a06b6c1 EG |
1826 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
1827 | } | |
1828 | ||
c6f600fc | 1829 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1830 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1831 | { |
1832 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1833 | ||
1834 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 1835 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
4cf677fd | 1836 | trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; |
d663ee73 JB |
1837 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1838 | trans_pcie->n_no_reclaim_cmds = 0; | |
1839 | else | |
1840 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1841 | if (trans_pcie->n_no_reclaim_cmds) | |
1842 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1843 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 1844 | |
6c4fbcbc EG |
1845 | trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; |
1846 | trans_pcie->rx_page_order = | |
1847 | iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); | |
7c5ba4a8 | 1848 | |
046db346 | 1849 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
3a736bcb | 1850 | trans_pcie->scd_set_active = trans_cfg->scd_set_active; |
41837ca9 | 1851 | trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; |
f14d6b39 | 1852 | |
21cb3222 JB |
1853 | trans_pcie->page_offs = trans_cfg->cb_data_offs; |
1854 | trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); | |
1855 | ||
39bdb17e SD |
1856 | trans->command_groups = trans_cfg->command_groups; |
1857 | trans->command_groups_size = trans_cfg->command_groups_size; | |
1858 | ||
f14d6b39 JB |
1859 | /* Initialize NAPI here - it should be before registering to mac80211 |
1860 | * in the opmode but after the HW struct is allocated. | |
1861 | * As this function may be called again in some corner cases don't | |
1862 | * do anything if NAPI was already initialized. | |
1863 | */ | |
bce97731 | 1864 | if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) |
f14d6b39 | 1865 | init_dummy_netdev(&trans_pcie->napi_dev); |
c6f600fc MV |
1866 | } |
1867 | ||
d1ff5253 | 1868 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1869 | { |
20d3b647 | 1870 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
6eb5e529 | 1871 | int i; |
a42a1844 | 1872 | |
2e5d4a8f | 1873 | iwl_pcie_synchronize_irqs(trans); |
0aa86df6 | 1874 | |
13a3a390 SS |
1875 | if (trans->cfg->gen2) |
1876 | iwl_pcie_gen2_tx_free(trans); | |
1877 | else | |
1878 | iwl_pcie_tx_free(trans); | |
9805c446 | 1879 | iwl_pcie_rx_free(trans); |
6379103e | 1880 | |
10a54d81 LC |
1881 | if (trans_pcie->rba.alloc_wq) { |
1882 | destroy_workqueue(trans_pcie->rba.alloc_wq); | |
1883 | trans_pcie->rba.alloc_wq = NULL; | |
1884 | } | |
1885 | ||
2e5d4a8f | 1886 | if (trans_pcie->msix_enabled) { |
7c8d91eb HD |
1887 | for (i = 0; i < trans_pcie->alloc_vecs; i++) { |
1888 | irq_set_affinity_hint( | |
1889 | trans_pcie->msix_entries[i].vector, | |
1890 | NULL); | |
7c8d91eb | 1891 | } |
2e5d4a8f | 1892 | |
2e5d4a8f HD |
1893 | trans_pcie->msix_enabled = false; |
1894 | } else { | |
2e5d4a8f | 1895 | iwl_pcie_free_ict(trans); |
2e5d4a8f | 1896 | } |
a42a1844 | 1897 | |
c2d20201 EG |
1898 | iwl_pcie_free_fw_monitor(trans); |
1899 | ||
6eb5e529 EG |
1900 | for_each_possible_cpu(i) { |
1901 | struct iwl_tso_hdr_page *p = | |
1902 | per_cpu_ptr(trans_pcie->tso_hdr_page, i); | |
1903 | ||
1904 | if (p->page) | |
1905 | __free_page(p->page); | |
1906 | } | |
1907 | ||
1908 | free_percpu(trans_pcie->tso_hdr_page); | |
a2a57a35 | 1909 | mutex_destroy(&trans_pcie->mutex); |
7b501d10 | 1910 | iwl_trans_free(trans); |
34c1b7ba EG |
1911 | } |
1912 | ||
47107e84 DF |
1913 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1914 | { | |
47107e84 | 1915 | if (state) |
eb7ff77e | 1916 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 1917 | else |
eb7ff77e | 1918 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
1919 | } |
1920 | ||
49564a80 LC |
1921 | struct iwl_trans_pcie_removal { |
1922 | struct pci_dev *pdev; | |
1923 | struct work_struct work; | |
1924 | }; | |
1925 | ||
1926 | static void iwl_trans_pcie_removal_wk(struct work_struct *wk) | |
1927 | { | |
1928 | struct iwl_trans_pcie_removal *removal = | |
1929 | container_of(wk, struct iwl_trans_pcie_removal, work); | |
1930 | struct pci_dev *pdev = removal->pdev; | |
aba1e632 | 1931 | static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; |
49564a80 LC |
1932 | |
1933 | dev_err(&pdev->dev, "Device gone - attempting removal\n"); | |
1934 | kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); | |
1935 | pci_lock_rescan_remove(); | |
1936 | pci_dev_put(pdev); | |
1937 | pci_stop_and_remove_bus_device(pdev); | |
1938 | pci_unlock_rescan_remove(); | |
1939 | ||
1940 | kfree(removal); | |
1941 | module_put(THIS_MODULE); | |
1942 | } | |
1943 | ||
23ba9340 EG |
1944 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, |
1945 | unsigned long *flags) | |
7a65d170 EG |
1946 | { |
1947 | int ret; | |
cfb4e624 JB |
1948 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1949 | ||
1950 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 | 1951 | |
fc8a350d | 1952 | if (trans_pcie->cmd_hold_nic_awake) |
b9439491 EG |
1953 | goto out; |
1954 | ||
7a65d170 | 1955 | /* this bit wakes up the NIC */ |
e139dc4a | 1956 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
a8cbb46f | 1957 | BIT(trans->cfg->csr->flag_mac_access_req)); |
6e584873 | 1958 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
01e58a28 | 1959 | udelay(2); |
7a65d170 EG |
1960 | |
1961 | /* | |
1962 | * These bits say the device is running, and should keep running for | |
1963 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
1964 | * but they do not indicate that embedded SRAM is restored yet; | |
fb70d49f LC |
1965 | * HW with volatile SRAM must save/restore contents to/from |
1966 | * host DRAM when sleeping/waking for power-saving. | |
7a65d170 EG |
1967 | * Each direction takes approximately 1/4 millisecond; with this |
1968 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
1969 | * series of register accesses are expected (e.g. reading Event Log), | |
1970 | * to keep device from sleeping. | |
1971 | * | |
1972 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
1973 | * SRAM is okay/restored. We don't check that here because this call | |
fb70d49f LC |
1974 | * is just for hardware register access; but GP1 MAC_SLEEP |
1975 | * check is a good idea before accessing the SRAM of HW with | |
1976 | * volatile SRAM (e.g. reading Event Log). | |
7a65d170 EG |
1977 | * |
1978 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
1979 | * and do not save/restore SRAM when power cycling. | |
1980 | */ | |
1981 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
a8cbb46f GBA |
1982 | BIT(trans->cfg->csr->flag_val_mac_access_en), |
1983 | (BIT(trans->cfg->csr->flag_mac_clock_ready) | | |
7a65d170 EG |
1984 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); |
1985 | if (unlikely(ret < 0)) { | |
49564a80 LC |
1986 | u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); |
1987 | ||
23ba9340 EG |
1988 | WARN_ONCE(1, |
1989 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
49564a80 LC |
1990 | cntrl); |
1991 | ||
1992 | iwl_trans_pcie_dump_regs(trans); | |
1993 | ||
1994 | if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { | |
1995 | struct iwl_trans_pcie_removal *removal; | |
1996 | ||
f60c9e59 | 1997 | if (test_bit(STATUS_TRANS_DEAD, &trans->status)) |
49564a80 LC |
1998 | goto err; |
1999 | ||
2000 | IWL_ERR(trans, "Device gone - scheduling removal!\n"); | |
2001 | ||
2002 | /* | |
2003 | * get a module reference to avoid doing this | |
2004 | * while unloading anyway and to avoid | |
2005 | * scheduling a work with code that's being | |
2006 | * removed. | |
2007 | */ | |
2008 | if (!try_module_get(THIS_MODULE)) { | |
2009 | IWL_ERR(trans, | |
2010 | "Module is being unloaded - abort\n"); | |
2011 | goto err; | |
2012 | } | |
2013 | ||
2014 | removal = kzalloc(sizeof(*removal), GFP_ATOMIC); | |
2015 | if (!removal) { | |
2016 | module_put(THIS_MODULE); | |
2017 | goto err; | |
2018 | } | |
2019 | /* | |
2020 | * we don't need to clear this flag, because | |
2021 | * the trans will be freed and reallocated. | |
2022 | */ | |
f60c9e59 | 2023 | set_bit(STATUS_TRANS_DEAD, &trans->status); |
49564a80 LC |
2024 | |
2025 | removal->pdev = to_pci_dev(trans->dev); | |
2026 | INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); | |
2027 | pci_dev_get(removal->pdev); | |
2028 | schedule_work(&removal->work); | |
2029 | } else { | |
2030 | iwl_write32(trans, CSR_RESET, | |
2031 | CSR_RESET_REG_FLAG_FORCE_NMI); | |
2032 | } | |
2033 | ||
2034 | err: | |
23ba9340 EG |
2035 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
2036 | return false; | |
7a65d170 EG |
2037 | } |
2038 | ||
b9439491 | 2039 | out: |
e56b04ef LE |
2040 | /* |
2041 | * Fool sparse by faking we release the lock - sparse will | |
2042 | * track nic_access anyway. | |
2043 | */ | |
cfb4e624 | 2044 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
2045 | return true; |
2046 | } | |
2047 | ||
e56b04ef LE |
2048 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
2049 | unsigned long *flags) | |
7a65d170 | 2050 | { |
cfb4e624 | 2051 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 2052 | |
cfb4e624 | 2053 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
2054 | |
2055 | /* | |
2056 | * Fool sparse by faking we acquiring the lock - sparse will | |
2057 | * track nic_access anyway. | |
2058 | */ | |
cfb4e624 | 2059 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 2060 | |
fc8a350d | 2061 | if (trans_pcie->cmd_hold_nic_awake) |
b9439491 EG |
2062 | goto out; |
2063 | ||
e139dc4a | 2064 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
a8cbb46f | 2065 | BIT(trans->cfg->csr->flag_mac_access_req)); |
7a65d170 EG |
2066 | /* |
2067 | * Above we read the CSR_GP_CNTRL register, which will flush | |
2068 | * any previous writes, but we need the write that clears the | |
2069 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
2070 | * scheduled on different CPUs (after we drop reg_lock). | |
2071 | */ | |
2072 | mmiowb(); | |
b9439491 | 2073 | out: |
cfb4e624 | 2074 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
2075 | } |
2076 | ||
4fd442db EG |
2077 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
2078 | void *buf, int dwords) | |
2079 | { | |
2080 | unsigned long flags; | |
2081 | int offs, ret = 0; | |
2082 | u32 *vals = buf; | |
2083 | ||
23ba9340 | 2084 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
4fd442db EG |
2085 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
2086 | for (offs = 0; offs < dwords; offs++) | |
2087 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 2088 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
2089 | } else { |
2090 | ret = -EBUSY; | |
2091 | } | |
4fd442db EG |
2092 | return ret; |
2093 | } | |
2094 | ||
2095 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 2096 | const void *buf, int dwords) |
4fd442db EG |
2097 | { |
2098 | unsigned long flags; | |
2099 | int offs, ret = 0; | |
bf0fd5da | 2100 | const u32 *vals = buf; |
4fd442db | 2101 | |
23ba9340 | 2102 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
4fd442db EG |
2103 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
2104 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
2105 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
2106 | vals ? vals[offs] : 0); | |
e56b04ef | 2107 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
2108 | } else { |
2109 | ret = -EBUSY; | |
2110 | } | |
4fd442db EG |
2111 | return ret; |
2112 | } | |
7a65d170 | 2113 | |
e0b8d405 EG |
2114 | static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, |
2115 | unsigned long txqs, | |
2116 | bool freeze) | |
2117 | { | |
2118 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2119 | int queue; | |
2120 | ||
2121 | for_each_set_bit(queue, &txqs, BITS_PER_LONG) { | |
b2a3b1c1 | 2122 | struct iwl_txq *txq = trans_pcie->txq[queue]; |
e0b8d405 EG |
2123 | unsigned long now; |
2124 | ||
2125 | spin_lock_bh(&txq->lock); | |
2126 | ||
2127 | now = jiffies; | |
2128 | ||
2129 | if (txq->frozen == freeze) | |
2130 | goto next_queue; | |
2131 | ||
2132 | IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", | |
2133 | freeze ? "Freezing" : "Waking", queue); | |
2134 | ||
2135 | txq->frozen = freeze; | |
2136 | ||
bb98ecd4 | 2137 | if (txq->read_ptr == txq->write_ptr) |
e0b8d405 EG |
2138 | goto next_queue; |
2139 | ||
2140 | if (freeze) { | |
2141 | if (unlikely(time_after(now, | |
2142 | txq->stuck_timer.expires))) { | |
2143 | /* | |
2144 | * The timer should have fired, maybe it is | |
2145 | * spinning right now on the lock. | |
2146 | */ | |
2147 | goto next_queue; | |
2148 | } | |
2149 | /* remember how long until the timer fires */ | |
2150 | txq->frozen_expiry_remainder = | |
2151 | txq->stuck_timer.expires - now; | |
2152 | del_timer(&txq->stuck_timer); | |
2153 | goto next_queue; | |
2154 | } | |
2155 | ||
2156 | /* | |
2157 | * Wake a non-empty queue -> arm timer with the | |
2158 | * remainder before it froze | |
2159 | */ | |
2160 | mod_timer(&txq->stuck_timer, | |
2161 | now + txq->frozen_expiry_remainder); | |
2162 | ||
2163 | next_queue: | |
2164 | spin_unlock_bh(&txq->lock); | |
2165 | } | |
2166 | } | |
2167 | ||
0cd58eaa EG |
2168 | static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) |
2169 | { | |
2170 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2171 | int i; | |
2172 | ||
2173 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
b2a3b1c1 | 2174 | struct iwl_txq *txq = trans_pcie->txq[i]; |
0cd58eaa EG |
2175 | |
2176 | if (i == trans_pcie->cmd_queue) | |
2177 | continue; | |
2178 | ||
2179 | spin_lock_bh(&txq->lock); | |
2180 | ||
2181 | if (!block && !(WARN_ON_ONCE(!txq->block))) { | |
2182 | txq->block--; | |
2183 | if (!txq->block) { | |
2184 | iwl_write32(trans, HBUS_TARG_WRPTR, | |
bb98ecd4 | 2185 | txq->write_ptr | (i << 8)); |
0cd58eaa EG |
2186 | } |
2187 | } else if (block) { | |
2188 | txq->block++; | |
2189 | } | |
2190 | ||
2191 | spin_unlock_bh(&txq->lock); | |
2192 | } | |
2193 | } | |
2194 | ||
5f178cd2 EG |
2195 | #define IWL_FLUSH_WAIT_MS 2000 |
2196 | ||
38398efb SS |
2197 | void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) |
2198 | { | |
afb84431 EG |
2199 | u32 txq_id = txq->id; |
2200 | u32 status; | |
2201 | bool active; | |
2202 | u8 fifo; | |
38398efb | 2203 | |
afb84431 EG |
2204 | if (trans->cfg->use_tfh) { |
2205 | IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, | |
2206 | txq->read_ptr, txq->write_ptr); | |
ae79785f SS |
2207 | /* TODO: access new SCD registers and dump them */ |
2208 | return; | |
38398efb | 2209 | } |
afb84431 EG |
2210 | |
2211 | status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); | |
2212 | fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
2213 | active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
2214 | ||
2215 | IWL_ERR(trans, | |
2216 | "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", | |
2217 | txq_id, active ? "" : "in", fifo, | |
2218 | jiffies_to_msecs(txq->wd_timeout), | |
2219 | txq->read_ptr, txq->write_ptr, | |
2220 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & | |
7b3e42ea | 2221 | (trans->cfg->base_params->max_tfd_queue_size - 1), |
afb84431 | 2222 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & |
7b3e42ea | 2223 | (trans->cfg->base_params->max_tfd_queue_size - 1), |
afb84431 | 2224 | iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); |
38398efb SS |
2225 | } |
2226 | ||
92536c96 SS |
2227 | static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, |
2228 | struct iwl_trans_rxq_dma_data *data) | |
2229 | { | |
2230 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2231 | ||
2232 | if (queue >= trans->num_rx_queues || !trans_pcie->rxq) | |
2233 | return -EINVAL; | |
2234 | ||
2235 | data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; | |
2236 | data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; | |
2237 | data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; | |
2238 | data->fr_bd_wid = 0; | |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | ||
d6d517b7 | 2243 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) |
5f178cd2 | 2244 | { |
8ad71bef | 2245 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 2246 | struct iwl_txq *txq; |
5f178cd2 | 2247 | unsigned long now = jiffies; |
2ae48edc | 2248 | bool overflow_tx; |
d6d517b7 SS |
2249 | u8 wr_ptr; |
2250 | ||
2b3fae66 | 2251 | /* Make sure the NIC is still alive in the bus */ |
f60c9e59 EG |
2252 | if (test_bit(STATUS_TRANS_DEAD, &trans->status)) |
2253 | return -ENODEV; | |
2b3fae66 | 2254 | |
d6d517b7 SS |
2255 | if (!test_bit(txq_idx, trans_pcie->queue_used)) |
2256 | return -EINVAL; | |
2257 | ||
2258 | IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); | |
2259 | txq = trans_pcie->txq[txq_idx]; | |
2ae48edc SS |
2260 | |
2261 | spin_lock_bh(&txq->lock); | |
2262 | overflow_tx = txq->overflow_tx || | |
2263 | !skb_queue_empty(&txq->overflow_q); | |
2264 | spin_unlock_bh(&txq->lock); | |
2265 | ||
6aa7de05 | 2266 | wr_ptr = READ_ONCE(txq->write_ptr); |
d6d517b7 | 2267 | |
2ae48edc SS |
2268 | while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || |
2269 | overflow_tx) && | |
d6d517b7 SS |
2270 | !time_after(jiffies, |
2271 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { | |
6aa7de05 | 2272 | u8 write_ptr = READ_ONCE(txq->write_ptr); |
d6d517b7 | 2273 | |
2ae48edc SS |
2274 | /* |
2275 | * If write pointer moved during the wait, warn only | |
2276 | * if the TX came from op mode. In case TX came from | |
2277 | * trans layer (overflow TX) don't warn. | |
2278 | */ | |
2279 | if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, | |
d6d517b7 SS |
2280 | "WR pointer moved while flushing %d -> %d\n", |
2281 | wr_ptr, write_ptr)) | |
2282 | return -ETIMEDOUT; | |
2ae48edc SS |
2283 | wr_ptr = write_ptr; |
2284 | ||
d6d517b7 | 2285 | usleep_range(1000, 2000); |
2ae48edc SS |
2286 | |
2287 | spin_lock_bh(&txq->lock); | |
2288 | overflow_tx = txq->overflow_tx || | |
2289 | !skb_queue_empty(&txq->overflow_q); | |
2290 | spin_unlock_bh(&txq->lock); | |
d6d517b7 SS |
2291 | } |
2292 | ||
2293 | if (txq->read_ptr != txq->write_ptr) { | |
2294 | IWL_ERR(trans, | |
2295 | "fail to flush all tx fifo queues Q %d\n", txq_idx); | |
2296 | iwl_trans_pcie_log_scd_error(trans, txq); | |
2297 | return -ETIMEDOUT; | |
2298 | } | |
2299 | ||
2300 | IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); | |
2301 | ||
2302 | return 0; | |
2303 | } | |
2304 | ||
2305 | static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) | |
2306 | { | |
2307 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2308 | int cnt; | |
5f178cd2 EG |
2309 | int ret = 0; |
2310 | ||
2311 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 2312 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
fa1a91fd | 2313 | |
9ba1947a | 2314 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 2315 | continue; |
3cafdbe6 EG |
2316 | if (!test_bit(cnt, trans_pcie->queue_used)) |
2317 | continue; | |
2318 | if (!(BIT(cnt) & txq_bm)) | |
2319 | continue; | |
748fa67c | 2320 | |
d6d517b7 SS |
2321 | ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); |
2322 | if (ret) | |
5f178cd2 | 2323 | break; |
5f178cd2 | 2324 | } |
1c3fea82 | 2325 | |
5f178cd2 EG |
2326 | return ret; |
2327 | } | |
2328 | ||
e139dc4a LE |
2329 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
2330 | u32 mask, u32 value) | |
2331 | { | |
e56b04ef | 2332 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
2333 | unsigned long flags; |
2334 | ||
e56b04ef | 2335 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 2336 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 2337 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
2338 | } |
2339 | ||
c24c7f58 | 2340 | static void iwl_trans_pcie_ref(struct iwl_trans *trans) |
7616f334 EP |
2341 | { |
2342 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
7616f334 EP |
2343 | |
2344 | if (iwlwifi_mod_params.d0i3_disable) | |
2345 | return; | |
2346 | ||
b3ff1270 | 2347 | pm_runtime_get(&trans_pcie->pci_dev->dev); |
5d93f3a2 LC |
2348 | |
2349 | #ifdef CONFIG_PM | |
2350 | IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", | |
2351 | atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); | |
2352 | #endif /* CONFIG_PM */ | |
7616f334 EP |
2353 | } |
2354 | ||
c24c7f58 | 2355 | static void iwl_trans_pcie_unref(struct iwl_trans *trans) |
7616f334 EP |
2356 | { |
2357 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
7616f334 EP |
2358 | |
2359 | if (iwlwifi_mod_params.d0i3_disable) | |
2360 | return; | |
2361 | ||
b3ff1270 LC |
2362 | pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); |
2363 | pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); | |
b3ff1270 | 2364 | |
5d93f3a2 LC |
2365 | #ifdef CONFIG_PM |
2366 | IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", | |
2367 | atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); | |
2368 | #endif /* CONFIG_PM */ | |
7616f334 EP |
2369 | } |
2370 | ||
ff620849 EG |
2371 | static const char *get_csr_string(int cmd) |
2372 | { | |
d9fb6465 | 2373 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
2374 | switch (cmd) { |
2375 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
2376 | IWL_CMD(CSR_INT_COALESCING); | |
2377 | IWL_CMD(CSR_INT); | |
2378 | IWL_CMD(CSR_INT_MASK); | |
2379 | IWL_CMD(CSR_FH_INT_STATUS); | |
2380 | IWL_CMD(CSR_GPIO_IN); | |
2381 | IWL_CMD(CSR_RESET); | |
2382 | IWL_CMD(CSR_GP_CNTRL); | |
2383 | IWL_CMD(CSR_HW_REV); | |
2384 | IWL_CMD(CSR_EEPROM_REG); | |
2385 | IWL_CMD(CSR_EEPROM_GP); | |
2386 | IWL_CMD(CSR_OTP_GP_REG); | |
2387 | IWL_CMD(CSR_GIO_REG); | |
2388 | IWL_CMD(CSR_GP_UCODE_REG); | |
2389 | IWL_CMD(CSR_GP_DRIVER_REG); | |
2390 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
2391 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
2392 | IWL_CMD(CSR_LED_REG); | |
2393 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
2394 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
2395 | IWL_CMD(CSR_ANA_PLL_CFG); | |
2396 | IWL_CMD(CSR_HW_REV_WA_REG); | |
a812cba9 | 2397 | IWL_CMD(CSR_MONITOR_STATUS_REG); |
ff620849 EG |
2398 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
2399 | default: | |
2400 | return "UNKNOWN"; | |
2401 | } | |
d9fb6465 | 2402 | #undef IWL_CMD |
ff620849 EG |
2403 | } |
2404 | ||
990aa6d7 | 2405 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
2406 | { |
2407 | int i; | |
2408 | static const u32 csr_tbl[] = { | |
2409 | CSR_HW_IF_CONFIG_REG, | |
2410 | CSR_INT_COALESCING, | |
2411 | CSR_INT, | |
2412 | CSR_INT_MASK, | |
2413 | CSR_FH_INT_STATUS, | |
2414 | CSR_GPIO_IN, | |
2415 | CSR_RESET, | |
2416 | CSR_GP_CNTRL, | |
2417 | CSR_HW_REV, | |
2418 | CSR_EEPROM_REG, | |
2419 | CSR_EEPROM_GP, | |
2420 | CSR_OTP_GP_REG, | |
2421 | CSR_GIO_REG, | |
2422 | CSR_GP_UCODE_REG, | |
2423 | CSR_GP_DRIVER_REG, | |
2424 | CSR_UCODE_DRV_GP1, | |
2425 | CSR_UCODE_DRV_GP2, | |
2426 | CSR_LED_REG, | |
2427 | CSR_DRAM_INT_TBL_REG, | |
2428 | CSR_GIO_CHICKEN_BITS, | |
2429 | CSR_ANA_PLL_CFG, | |
a812cba9 | 2430 | CSR_MONITOR_STATUS_REG, |
ff620849 EG |
2431 | CSR_HW_REV_WA_REG, |
2432 | CSR_DBG_HPET_MEM_REG | |
2433 | }; | |
2434 | IWL_ERR(trans, "CSR values:\n"); | |
2435 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
2436 | "CSR_INT_PERIODIC_REG)\n"); | |
2437 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
2438 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
2439 | get_csr_string(csr_tbl[i]), | |
1042db2a | 2440 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
2441 | } |
2442 | } | |
2443 | ||
87e5666c EG |
2444 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
2445 | /* create and remove of files */ | |
2446 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
cf5d5663 GKH |
2447 | debugfs_create_file(#name, mode, parent, trans, \ |
2448 | &iwl_dbgfs_##name##_ops); \ | |
87e5666c EG |
2449 | } while (0) |
2450 | ||
2451 | /* file operation */ | |
87e5666c | 2452 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
2453 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2454 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 2455 | .open = simple_open, \ |
87e5666c EG |
2456 | .llseek = generic_file_llseek, \ |
2457 | }; | |
2458 | ||
16db88ba | 2459 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
2460 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2461 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 2462 | .open = simple_open, \ |
16db88ba EG |
2463 | .llseek = generic_file_llseek, \ |
2464 | }; | |
2465 | ||
87e5666c | 2466 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
2467 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2468 | .write = iwl_dbgfs_##name##_write, \ | |
2469 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 2470 | .open = simple_open, \ |
87e5666c EG |
2471 | .llseek = generic_file_llseek, \ |
2472 | }; | |
2473 | ||
87e5666c | 2474 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
2475 | char __user *user_buf, |
2476 | size_t count, loff_t *ppos) | |
8ad71bef | 2477 | { |
5a878bf6 | 2478 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 2479 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 2480 | struct iwl_txq *txq; |
87e5666c EG |
2481 | char *buf; |
2482 | int pos = 0; | |
2483 | int cnt; | |
2484 | int ret; | |
1745e440 WYG |
2485 | size_t bufsz; |
2486 | ||
e0b8d405 | 2487 | bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; |
87e5666c | 2488 | |
b2a3b1c1 | 2489 | if (!trans_pcie->txq_memory) |
87e5666c | 2490 | return -EAGAIN; |
f9e75447 | 2491 | |
87e5666c EG |
2492 | buf = kzalloc(bufsz, GFP_KERNEL); |
2493 | if (!buf) | |
2494 | return -ENOMEM; | |
2495 | ||
035f7ff2 | 2496 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
b2a3b1c1 | 2497 | txq = trans_pcie->txq[cnt]; |
87e5666c | 2498 | pos += scnprintf(buf + pos, bufsz - pos, |
e0b8d405 | 2499 | "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", |
bb98ecd4 | 2500 | cnt, txq->read_ptr, txq->write_ptr, |
9eae88fa | 2501 | !!test_bit(cnt, trans_pcie->queue_used), |
f40faf62 | 2502 | !!test_bit(cnt, trans_pcie->queue_stopped), |
e0b8d405 | 2503 | txq->need_update, txq->frozen, |
f40faf62 | 2504 | (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); |
87e5666c EG |
2505 | } |
2506 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2507 | kfree(buf); | |
2508 | return ret; | |
2509 | } | |
2510 | ||
2511 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
2512 | char __user *user_buf, |
2513 | size_t count, loff_t *ppos) | |
2514 | { | |
5a878bf6 | 2515 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 2516 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
78485054 SS |
2517 | char *buf; |
2518 | int pos = 0, i, ret; | |
2519 | size_t bufsz = sizeof(buf); | |
2520 | ||
2521 | bufsz = sizeof(char) * 121 * trans->num_rx_queues; | |
2522 | ||
2523 | if (!trans_pcie->rxq) | |
2524 | return -EAGAIN; | |
2525 | ||
2526 | buf = kzalloc(bufsz, GFP_KERNEL); | |
2527 | if (!buf) | |
2528 | return -ENOMEM; | |
2529 | ||
2530 | for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { | |
2531 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
2532 | ||
2533 | pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", | |
2534 | i); | |
2535 | pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", | |
2536 | rxq->read); | |
2537 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", | |
2538 | rxq->write); | |
2539 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", | |
2540 | rxq->write_actual); | |
2541 | pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", | |
2542 | rxq->need_update); | |
2543 | pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", | |
2544 | rxq->free_count); | |
2545 | if (rxq->rb_stts) { | |
0307c839 GBA |
2546 | u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, |
2547 | rxq)); | |
78485054 SS |
2548 | pos += scnprintf(buf + pos, bufsz - pos, |
2549 | "\tclosed_rb_num: %u\n", | |
0307c839 | 2550 | r & 0x0FFF); |
78485054 SS |
2551 | } else { |
2552 | pos += scnprintf(buf + pos, bufsz - pos, | |
2553 | "\tclosed_rb_num: Not Allocated\n"); | |
60c0a88f | 2554 | } |
87e5666c | 2555 | } |
78485054 SS |
2556 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
2557 | kfree(buf); | |
2558 | ||
2559 | return ret; | |
87e5666c EG |
2560 | } |
2561 | ||
1f7b6172 EG |
2562 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
2563 | char __user *user_buf, | |
20d3b647 JB |
2564 | size_t count, loff_t *ppos) |
2565 | { | |
1f7b6172 | 2566 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 2567 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
2568 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
2569 | ||
2570 | int pos = 0; | |
2571 | char *buf; | |
2572 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
2573 | ssize_t ret; | |
2574 | ||
2575 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 2576 | if (!buf) |
1f7b6172 | 2577 | return -ENOMEM; |
1f7b6172 EG |
2578 | |
2579 | pos += scnprintf(buf + pos, bufsz - pos, | |
2580 | "Interrupt Statistics Report:\n"); | |
2581 | ||
2582 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
2583 | isr_stats->hw); | |
2584 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
2585 | isr_stats->sw); | |
2586 | if (isr_stats->sw || isr_stats->hw) { | |
2587 | pos += scnprintf(buf + pos, bufsz - pos, | |
2588 | "\tLast Restarting Code: 0x%X\n", | |
2589 | isr_stats->err_code); | |
2590 | } | |
2591 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2592 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
2593 | isr_stats->sch); | |
2594 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
2595 | isr_stats->alive); | |
2596 | #endif | |
2597 | pos += scnprintf(buf + pos, bufsz - pos, | |
2598 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
2599 | ||
2600 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
2601 | isr_stats->ctkill); | |
2602 | ||
2603 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
2604 | isr_stats->wakeup); | |
2605 | ||
2606 | pos += scnprintf(buf + pos, bufsz - pos, | |
2607 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
2608 | ||
2609 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
2610 | isr_stats->tx); | |
2611 | ||
2612 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
2613 | isr_stats->unhandled); | |
2614 | ||
2615 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2616 | kfree(buf); | |
2617 | return ret; | |
2618 | } | |
2619 | ||
2620 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
2621 | const char __user *user_buf, | |
2622 | size_t count, loff_t *ppos) | |
2623 | { | |
2624 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 2625 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 | 2626 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1f7b6172 | 2627 | u32 reset_flag; |
078f1131 | 2628 | int ret; |
1f7b6172 | 2629 | |
078f1131 JB |
2630 | ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); |
2631 | if (ret) | |
2632 | return ret; | |
1f7b6172 EG |
2633 | if (reset_flag == 0) |
2634 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
2635 | ||
2636 | return count; | |
2637 | } | |
2638 | ||
16db88ba | 2639 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
2640 | const char __user *user_buf, |
2641 | size_t count, loff_t *ppos) | |
16db88ba EG |
2642 | { |
2643 | struct iwl_trans *trans = file->private_data; | |
16db88ba | 2644 | |
990aa6d7 | 2645 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
2646 | |
2647 | return count; | |
2648 | } | |
2649 | ||
16db88ba | 2650 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
2651 | char __user *user_buf, |
2652 | size_t count, loff_t *ppos) | |
16db88ba EG |
2653 | { |
2654 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 2655 | char *buf = NULL; |
56c2477f | 2656 | ssize_t ret; |
16db88ba | 2657 | |
56c2477f JB |
2658 | ret = iwl_dump_fh(trans, &buf); |
2659 | if (ret < 0) | |
2660 | return ret; | |
2661 | if (!buf) | |
2662 | return -EINVAL; | |
2663 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); | |
2664 | kfree(buf); | |
16db88ba EG |
2665 | return ret; |
2666 | } | |
2667 | ||
fa4de7f7 JB |
2668 | static ssize_t iwl_dbgfs_rfkill_read(struct file *file, |
2669 | char __user *user_buf, | |
2670 | size_t count, loff_t *ppos) | |
2671 | { | |
2672 | struct iwl_trans *trans = file->private_data; | |
2673 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2674 | char buf[100]; | |
2675 | int pos; | |
2676 | ||
2677 | pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", | |
2678 | trans_pcie->debug_rfkill, | |
2679 | !(iwl_read32(trans, CSR_GP_CNTRL) & | |
2680 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); | |
2681 | ||
2682 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2683 | } | |
2684 | ||
2685 | static ssize_t iwl_dbgfs_rfkill_write(struct file *file, | |
2686 | const char __user *user_buf, | |
2687 | size_t count, loff_t *ppos) | |
2688 | { | |
2689 | struct iwl_trans *trans = file->private_data; | |
2690 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2691 | bool old = trans_pcie->debug_rfkill; | |
2692 | int ret; | |
2693 | ||
2694 | ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); | |
2695 | if (ret) | |
2696 | return ret; | |
2697 | if (old == trans_pcie->debug_rfkill) | |
2698 | return count; | |
2699 | IWL_WARN(trans, "changing debug rfkill %d->%d\n", | |
2700 | old, trans_pcie->debug_rfkill); | |
2701 | iwl_pcie_handle_rfkill_irq(trans); | |
2702 | ||
2703 | return count; | |
2704 | } | |
2705 | ||
f7805b33 LC |
2706 | static int iwl_dbgfs_monitor_data_open(struct inode *inode, |
2707 | struct file *file) | |
2708 | { | |
2709 | struct iwl_trans *trans = inode->i_private; | |
2710 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2711 | ||
2712 | if (!trans->dbg_dest_tlv || | |
2713 | trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) { | |
2714 | IWL_ERR(trans, "Debug destination is not set to DRAM\n"); | |
2715 | return -ENOENT; | |
2716 | } | |
2717 | ||
2718 | if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) | |
2719 | return -EBUSY; | |
2720 | ||
2721 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; | |
2722 | return simple_open(inode, file); | |
2723 | } | |
2724 | ||
2725 | static int iwl_dbgfs_monitor_data_release(struct inode *inode, | |
2726 | struct file *file) | |
2727 | { | |
2728 | struct iwl_trans_pcie *trans_pcie = | |
2729 | IWL_TRANS_GET_PCIE_TRANS(inode->i_private); | |
2730 | ||
2731 | if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) | |
2732 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; | |
2733 | return 0; | |
2734 | } | |
2735 | ||
2736 | static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, | |
2737 | void *buf, ssize_t *size, | |
2738 | ssize_t *bytes_copied) | |
2739 | { | |
2740 | int buf_size_left = count - *bytes_copied; | |
2741 | ||
2742 | buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); | |
2743 | if (*size > buf_size_left) | |
2744 | *size = buf_size_left; | |
2745 | ||
2746 | *size -= copy_to_user(user_buf, buf, *size); | |
2747 | *bytes_copied += *size; | |
2748 | ||
2749 | if (buf_size_left == *size) | |
2750 | return true; | |
2751 | return false; | |
2752 | } | |
2753 | ||
2754 | static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, | |
2755 | char __user *user_buf, | |
2756 | size_t count, loff_t *ppos) | |
2757 | { | |
2758 | struct iwl_trans *trans = file->private_data; | |
2759 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2760 | void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf; | |
2761 | struct cont_rec *data = &trans_pcie->fw_mon_data; | |
2762 | u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; | |
2763 | ssize_t size, bytes_copied = 0; | |
2764 | bool b_full; | |
2765 | ||
2766 | if (trans->dbg_dest_tlv) { | |
2767 | write_ptr_addr = | |
2768 | le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); | |
2769 | wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); | |
2770 | } else { | |
2771 | write_ptr_addr = MON_BUFF_WRPTR; | |
2772 | wrap_cnt_addr = MON_BUFF_CYCLE_CNT; | |
2773 | } | |
2774 | ||
2775 | if (unlikely(!trans->dbg_rec_on)) | |
2776 | return 0; | |
2777 | ||
2778 | mutex_lock(&data->mutex); | |
2779 | if (data->state == | |
2780 | IWL_FW_MON_DBGFS_STATE_DISABLED) { | |
2781 | mutex_unlock(&data->mutex); | |
2782 | return 0; | |
2783 | } | |
2784 | ||
2785 | /* write_ptr position in bytes rather then DW */ | |
2786 | write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); | |
2787 | wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); | |
2788 | ||
2789 | if (data->prev_wrap_cnt == wrap_cnt) { | |
2790 | size = write_ptr - data->prev_wr_ptr; | |
2791 | curr_buf = cpu_addr + data->prev_wr_ptr; | |
2792 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2793 | curr_buf, &size, | |
2794 | &bytes_copied); | |
2795 | data->prev_wr_ptr += size; | |
2796 | ||
2797 | } else if (data->prev_wrap_cnt == wrap_cnt - 1 && | |
2798 | write_ptr < data->prev_wr_ptr) { | |
2799 | size = trans->fw_mon[0].size - data->prev_wr_ptr; | |
2800 | curr_buf = cpu_addr + data->prev_wr_ptr; | |
2801 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2802 | curr_buf, &size, | |
2803 | &bytes_copied); | |
2804 | data->prev_wr_ptr += size; | |
2805 | ||
2806 | if (!b_full) { | |
2807 | size = write_ptr; | |
2808 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2809 | cpu_addr, &size, | |
2810 | &bytes_copied); | |
2811 | data->prev_wr_ptr = size; | |
2812 | data->prev_wrap_cnt++; | |
2813 | } | |
2814 | } else { | |
2815 | if (data->prev_wrap_cnt == wrap_cnt - 1 && | |
2816 | write_ptr > data->prev_wr_ptr) | |
2817 | IWL_WARN(trans, | |
2818 | "write pointer passed previous write pointer, start copying from the beginning\n"); | |
2819 | else if (!unlikely(data->prev_wrap_cnt == 0 && | |
2820 | data->prev_wr_ptr == 0)) | |
2821 | IWL_WARN(trans, | |
2822 | "monitor data is out of sync, start copying from the beginning\n"); | |
2823 | ||
2824 | size = write_ptr; | |
2825 | b_full = iwl_write_to_user_buf(user_buf, count, | |
2826 | cpu_addr, &size, | |
2827 | &bytes_copied); | |
2828 | data->prev_wr_ptr = size; | |
2829 | data->prev_wrap_cnt = wrap_cnt; | |
2830 | } | |
2831 | ||
2832 | mutex_unlock(&data->mutex); | |
2833 | ||
2834 | return bytes_copied; | |
2835 | } | |
2836 | ||
1f7b6172 | 2837 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2838 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2839 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2840 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2841 | DEBUGFS_WRITE_FILE_OPS(csr); |
fa4de7f7 | 2842 | DEBUGFS_READ_WRITE_FILE_OPS(rfkill); |
87e5666c | 2843 | |
f7805b33 LC |
2844 | static const struct file_operations iwl_dbgfs_monitor_data_ops = { |
2845 | .read = iwl_dbgfs_monitor_data_read, | |
2846 | .open = iwl_dbgfs_monitor_data_open, | |
2847 | .release = iwl_dbgfs_monitor_data_release, | |
2848 | }; | |
2849 | ||
f8a1edb7 | 2850 | /* Create the debugfs files and directories */ |
cf5d5663 | 2851 | void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) |
87e5666c | 2852 | { |
f8a1edb7 JB |
2853 | struct dentry *dir = trans->dbgfs_dir; |
2854 | ||
2ef00c53 JP |
2855 | DEBUGFS_ADD_FILE(rx_queue, dir, 0400); |
2856 | DEBUGFS_ADD_FILE(tx_queue, dir, 0400); | |
2857 | DEBUGFS_ADD_FILE(interrupt, dir, 0600); | |
2858 | DEBUGFS_ADD_FILE(csr, dir, 0200); | |
2859 | DEBUGFS_ADD_FILE(fh_reg, dir, 0400); | |
2860 | DEBUGFS_ADD_FILE(rfkill, dir, 0600); | |
f7805b33 | 2861 | DEBUGFS_ADD_FILE(monitor_data, dir, 0400); |
87e5666c | 2862 | } |
f7805b33 LC |
2863 | |
2864 | static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) | |
2865 | { | |
2866 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2867 | struct cont_rec *data = &trans_pcie->fw_mon_data; | |
2868 | ||
2869 | mutex_lock(&data->mutex); | |
2870 | data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; | |
2871 | mutex_unlock(&data->mutex); | |
2872 | } | |
aadede6e | 2873 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
4d075007 | 2874 | |
6983ba69 | 2875 | static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) |
4d075007 | 2876 | { |
3cd1980b | 2877 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4d075007 JB |
2878 | u32 cmdlen = 0; |
2879 | int i; | |
2880 | ||
3cd1980b | 2881 | for (i = 0; i < trans_pcie->max_tbs; i++) |
6983ba69 | 2882 | cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); |
4d075007 JB |
2883 | |
2884 | return cmdlen; | |
2885 | } | |
2886 | ||
bd7fc617 EG |
2887 | static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, |
2888 | struct iwl_fw_error_dump_data **data, | |
2889 | int allocated_rb_nums) | |
2890 | { | |
2891 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2892 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; | |
78485054 SS |
2893 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
2894 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; | |
bd7fc617 EG |
2895 | u32 i, r, j, rb_len = 0; |
2896 | ||
2897 | spin_lock(&rxq->lock); | |
2898 | ||
0307c839 | 2899 | r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; |
bd7fc617 EG |
2900 | |
2901 | for (i = rxq->read, j = 0; | |
2902 | i != r && j < allocated_rb_nums; | |
2903 | i = (i + 1) & RX_QUEUE_MASK, j++) { | |
2904 | struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; | |
2905 | struct iwl_fw_error_dump_rb *rb; | |
2906 | ||
2907 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, | |
2908 | DMA_FROM_DEVICE); | |
2909 | ||
2910 | rb_len += sizeof(**data) + sizeof(*rb) + max_len; | |
2911 | ||
2912 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); | |
2913 | (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); | |
2914 | rb = (void *)(*data)->data; | |
2915 | rb->index = cpu_to_le32(i); | |
2916 | memcpy(rb->data, page_address(rxb->page), max_len); | |
2917 | /* remap the page for the free benefit */ | |
2918 | rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, | |
2919 | max_len, | |
2920 | DMA_FROM_DEVICE); | |
2921 | ||
2922 | *data = iwl_fw_error_next_data(*data); | |
2923 | } | |
2924 | ||
2925 | spin_unlock(&rxq->lock); | |
2926 | ||
2927 | return rb_len; | |
2928 | } | |
473ad712 EG |
2929 | #define IWL_CSR_TO_DUMP (0x250) |
2930 | ||
2931 | static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, | |
2932 | struct iwl_fw_error_dump_data **data) | |
2933 | { | |
2934 | u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; | |
2935 | __le32 *val; | |
2936 | int i; | |
2937 | ||
2938 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); | |
2939 | (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); | |
2940 | val = (void *)(*data)->data; | |
2941 | ||
2942 | for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) | |
2943 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2944 | ||
2945 | *data = iwl_fw_error_next_data(*data); | |
2946 | ||
2947 | return csr_len; | |
2948 | } | |
2949 | ||
06d51e0d LK |
2950 | static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, |
2951 | struct iwl_fw_error_dump_data **data) | |
2952 | { | |
2953 | u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; | |
2954 | unsigned long flags; | |
2955 | __le32 *val; | |
2956 | int i; | |
2957 | ||
23ba9340 | 2958 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
06d51e0d LK |
2959 | return 0; |
2960 | ||
2961 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); | |
2962 | (*data)->len = cpu_to_le32(fh_regs_len); | |
2963 | val = (void *)(*data)->data; | |
2964 | ||
723b45e2 LK |
2965 | if (!trans->cfg->gen2) |
2966 | for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; | |
2967 | i += sizeof(u32)) | |
2968 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2969 | else | |
ea695b7c ST |
2970 | for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); |
2971 | i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); | |
723b45e2 LK |
2972 | i += sizeof(u32)) |
2973 | *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, | |
2974 | i)); | |
06d51e0d LK |
2975 | |
2976 | iwl_trans_release_nic_access(trans, &flags); | |
2977 | ||
2978 | *data = iwl_fw_error_next_data(*data); | |
2979 | ||
2980 | return sizeof(**data) + fh_regs_len; | |
2981 | } | |
2982 | ||
cc79ef66 LK |
2983 | static u32 |
2984 | iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, | |
2985 | struct iwl_fw_error_dump_fw_mon *fw_mon_data, | |
2986 | u32 monitor_len) | |
2987 | { | |
2988 | u32 buf_size_in_dwords = (monitor_len >> 2); | |
2989 | u32 *buffer = (u32 *)fw_mon_data->data; | |
2990 | unsigned long flags; | |
2991 | u32 i; | |
2992 | ||
23ba9340 | 2993 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
cc79ef66 LK |
2994 | return 0; |
2995 | ||
ea695b7c | 2996 | iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); |
cc79ef66 | 2997 | for (i = 0; i < buf_size_in_dwords; i++) |
ea695b7c ST |
2998 | buffer[i] = iwl_read_umac_prph_no_grab(trans, |
2999 | MON_DMARB_RD_DATA_ADDR); | |
3000 | iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); | |
cc79ef66 LK |
3001 | |
3002 | iwl_trans_release_nic_access(trans, &flags); | |
3003 | ||
3004 | return monitor_len; | |
3005 | } | |
3006 | ||
7a14c23d SS |
3007 | static void |
3008 | iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, | |
3009 | struct iwl_fw_error_dump_fw_mon *fw_mon_data) | |
3010 | { | |
c88580e1 | 3011 | u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; |
7a14c23d | 3012 | |
c88580e1 SM |
3013 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { |
3014 | base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; | |
3015 | base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; | |
3016 | write_ptr = DBGC_CUR_DBGBUF_STATUS; | |
3017 | wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; | |
3018 | } else if (trans->ini_valid) { | |
ea695b7c ST |
3019 | base = iwl_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2); |
3020 | write_ptr = iwl_umac_prph(trans, MON_BUFF_WRPTR_VER2); | |
3021 | wrap_cnt = iwl_umac_prph(trans, MON_BUFF_CYCLE_CNT_VER2); | |
7a14c23d SS |
3022 | } else if (trans->dbg_dest_tlv) { |
3023 | write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); | |
3024 | wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); | |
3025 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
3026 | } else { | |
3027 | base = MON_BUFF_BASE_ADDR; | |
3028 | write_ptr = MON_BUFF_WRPTR; | |
3029 | wrap_cnt = MON_BUFF_CYCLE_CNT; | |
3030 | } | |
c88580e1 SM |
3031 | |
3032 | write_ptr_val = iwl_read_prph(trans, write_ptr); | |
7a14c23d SS |
3033 | fw_mon_data->fw_mon_cycle_cnt = |
3034 | cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); | |
3035 | fw_mon_data->fw_mon_base_ptr = | |
3036 | cpu_to_le32(iwl_read_prph(trans, base)); | |
c88580e1 SM |
3037 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { |
3038 | fw_mon_data->fw_mon_base_high_ptr = | |
3039 | cpu_to_le32(iwl_read_prph(trans, base_high)); | |
3040 | write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; | |
3041 | } | |
3042 | fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); | |
7a14c23d SS |
3043 | } |
3044 | ||
36fb9017 OG |
3045 | static u32 |
3046 | iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, | |
3047 | struct iwl_fw_error_dump_data **data, | |
3048 | u32 monitor_len) | |
3049 | { | |
36fb9017 OG |
3050 | u32 len = 0; |
3051 | ||
88964b2e | 3052 | if ((trans->num_blocks && |
c88580e1 SM |
3053 | (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 || |
3054 | trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210 || | |
3055 | trans->ini_valid)) || | |
3056 | (trans->dbg_dest_tlv && !trans->ini_valid)) { | |
36fb9017 | 3057 | struct iwl_fw_error_dump_fw_mon *fw_mon_data; |
36fb9017 OG |
3058 | |
3059 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); | |
3060 | fw_mon_data = (void *)(*data)->data; | |
7a14c23d SS |
3061 | |
3062 | iwl_trans_pcie_dump_pointers(trans, fw_mon_data); | |
36fb9017 OG |
3063 | |
3064 | len += sizeof(**data) + sizeof(*fw_mon_data); | |
88964b2e | 3065 | if (trans->num_blocks) { |
36fb9017 | 3066 | memcpy(fw_mon_data->data, |
88964b2e SS |
3067 | trans->fw_mon[0].block, |
3068 | trans->fw_mon[0].size); | |
36fb9017 | 3069 | |
88964b2e | 3070 | monitor_len = trans->fw_mon[0].size; |
36fb9017 | 3071 | } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { |
7a14c23d | 3072 | u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); |
36fb9017 OG |
3073 | /* |
3074 | * Update pointers to reflect actual values after | |
3075 | * shifting | |
3076 | */ | |
fd527eb5 GBA |
3077 | if (trans->dbg_dest_tlv->version) { |
3078 | base = (iwl_read_prph(trans, base) & | |
3079 | IWL_LDBG_M2S_BUF_BA_MSK) << | |
3080 | trans->dbg_dest_tlv->base_shift; | |
3081 | base *= IWL_M2S_UNIT_SIZE; | |
3082 | base += trans->cfg->smem_offset; | |
3083 | } else { | |
3084 | base = iwl_read_prph(trans, base) << | |
3085 | trans->dbg_dest_tlv->base_shift; | |
3086 | } | |
3087 | ||
36fb9017 OG |
3088 | iwl_trans_read_mem(trans, base, fw_mon_data->data, |
3089 | monitor_len / sizeof(u32)); | |
3090 | } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { | |
3091 | monitor_len = | |
3092 | iwl_trans_pci_dump_marbh_monitor(trans, | |
3093 | fw_mon_data, | |
3094 | monitor_len); | |
3095 | } else { | |
3096 | /* Didn't match anything - output no monitor data */ | |
3097 | monitor_len = 0; | |
3098 | } | |
3099 | ||
3100 | len += monitor_len; | |
3101 | (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); | |
3102 | } | |
3103 | ||
3104 | return len; | |
3105 | } | |
3106 | ||
93079fd5 | 3107 | static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) |
4d075007 | 3108 | { |
88964b2e | 3109 | if (trans->num_blocks) { |
da752717 SM |
3110 | *len += sizeof(struct iwl_fw_error_dump_data) + |
3111 | sizeof(struct iwl_fw_error_dump_fw_mon) + | |
88964b2e SS |
3112 | trans->fw_mon[0].size; |
3113 | return trans->fw_mon[0].size; | |
99684ae3 | 3114 | } else if (trans->dbg_dest_tlv) { |
da752717 | 3115 | u32 base, end, cfg_reg, monitor_len; |
99684ae3 | 3116 | |
fd527eb5 GBA |
3117 | if (trans->dbg_dest_tlv->version == 1) { |
3118 | cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
3119 | cfg_reg = iwl_read_prph(trans, cfg_reg); | |
3120 | base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << | |
3121 | trans->dbg_dest_tlv->base_shift; | |
3122 | base *= IWL_M2S_UNIT_SIZE; | |
3123 | base += trans->cfg->smem_offset; | |
99684ae3 | 3124 | |
fd527eb5 GBA |
3125 | monitor_len = |
3126 | (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> | |
3127 | trans->dbg_dest_tlv->end_shift; | |
3128 | monitor_len *= IWL_M2S_UNIT_SIZE; | |
3129 | } else { | |
3130 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
3131 | end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); | |
99684ae3 | 3132 | |
fd527eb5 GBA |
3133 | base = iwl_read_prph(trans, base) << |
3134 | trans->dbg_dest_tlv->base_shift; | |
3135 | end = iwl_read_prph(trans, end) << | |
3136 | trans->dbg_dest_tlv->end_shift; | |
3137 | ||
3138 | /* Make "end" point to the actual end */ | |
3139 | if (trans->cfg->device_family >= | |
3140 | IWL_DEVICE_FAMILY_8000 || | |
3141 | trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) | |
3142 | end += (1 << trans->dbg_dest_tlv->end_shift); | |
3143 | monitor_len = end - base; | |
3144 | } | |
da752717 SM |
3145 | *len += sizeof(struct iwl_fw_error_dump_data) + |
3146 | sizeof(struct iwl_fw_error_dump_fw_mon) + | |
3147 | monitor_len; | |
3148 | return monitor_len; | |
99684ae3 | 3149 | } |
da752717 SM |
3150 | return 0; |
3151 | } | |
3152 | ||
3153 | static struct iwl_trans_dump_data | |
3154 | *iwl_trans_pcie_dump_data(struct iwl_trans *trans, | |
79f033f6 | 3155 | u32 dump_mask) |
da752717 SM |
3156 | { |
3157 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
3158 | struct iwl_fw_error_dump_data *data; | |
3159 | struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; | |
3160 | struct iwl_fw_error_dump_txcmd *txcmd; | |
3161 | struct iwl_trans_dump_data *dump_data; | |
fefbf853 | 3162 | u32 len, num_rbs = 0, monitor_len = 0; |
da752717 SM |
3163 | int i, ptr; |
3164 | bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && | |
3165 | !trans->cfg->mq_rx_supported && | |
79f033f6 SS |
3166 | dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); |
3167 | ||
3168 | if (!dump_mask) | |
3169 | return NULL; | |
da752717 SM |
3170 | |
3171 | /* transport dump header */ | |
3172 | len = sizeof(*dump_data); | |
3173 | ||
3174 | /* host commands */ | |
8672aad3 SM |
3175 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) |
3176 | len += sizeof(*data) + | |
3177 | cmdq->n_window * (sizeof(*txcmd) + | |
3178 | TFD_MAX_PAYLOAD_SIZE); | |
da752717 SM |
3179 | |
3180 | /* FW monitor */ | |
fefbf853 SM |
3181 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) |
3182 | monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); | |
36fb9017 OG |
3183 | |
3184 | /* CSR registers */ | |
79f033f6 | 3185 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) |
520f03ea | 3186 | len += sizeof(*data) + IWL_CSR_TO_DUMP; |
36fb9017 | 3187 | |
36fb9017 | 3188 | /* FH registers */ |
79f033f6 | 3189 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { |
520f03ea SM |
3190 | if (trans->cfg->gen2) |
3191 | len += sizeof(*data) + | |
ea695b7c ST |
3192 | (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - |
3193 | iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); | |
520f03ea SM |
3194 | else |
3195 | len += sizeof(*data) + | |
3196 | (FH_MEM_UPPER_BOUND - | |
3197 | FH_MEM_LOWER_BOUND); | |
3198 | } | |
36fb9017 OG |
3199 | |
3200 | if (dump_rbs) { | |
78485054 SS |
3201 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
3202 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; | |
36fb9017 | 3203 | /* RBs */ |
0307c839 GBA |
3204 | num_rbs = |
3205 | le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) | |
3206 | & 0x0FFF; | |
78485054 | 3207 | num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; |
36fb9017 OG |
3208 | len += num_rbs * (sizeof(*data) + |
3209 | sizeof(struct iwl_fw_error_dump_rb) + | |
3210 | (PAGE_SIZE << trans_pcie->rx_page_order)); | |
3211 | } | |
3212 | ||
5538409b | 3213 | /* Paged memory for gen2 HW */ |
79f033f6 | 3214 | if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) |
505a00c0 | 3215 | for (i = 0; i < trans->init_dram.paging_cnt; i++) |
5538409b LK |
3216 | len += sizeof(*data) + |
3217 | sizeof(struct iwl_fw_error_dump_paging) + | |
505a00c0 | 3218 | trans->init_dram.paging[i].size; |
5538409b | 3219 | |
48eb7b34 EG |
3220 | dump_data = vzalloc(len); |
3221 | if (!dump_data) | |
3222 | return NULL; | |
4d075007 JB |
3223 | |
3224 | len = 0; | |
48eb7b34 | 3225 | data = (void *)dump_data->data; |
520f03ea | 3226 | |
79f033f6 | 3227 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) { |
520f03ea SM |
3228 | u16 tfd_size = trans_pcie->tfd_size; |
3229 | ||
3230 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); | |
3231 | txcmd = (void *)data->data; | |
3232 | spin_lock_bh(&cmdq->lock); | |
3233 | ptr = cmdq->write_ptr; | |
3234 | for (i = 0; i < cmdq->n_window; i++) { | |
3235 | u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); | |
3236 | u32 caplen, cmdlen; | |
3237 | ||
3238 | cmdlen = iwl_trans_pcie_get_cmdlen(trans, | |
3239 | cmdq->tfds + | |
3240 | tfd_size * ptr); | |
3241 | caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); | |
3242 | ||
3243 | if (cmdlen) { | |
3244 | len += sizeof(*txcmd) + caplen; | |
3245 | txcmd->cmdlen = cpu_to_le32(cmdlen); | |
3246 | txcmd->caplen = cpu_to_le32(caplen); | |
3247 | memcpy(txcmd->data, cmdq->entries[idx].cmd, | |
3248 | caplen); | |
3249 | txcmd = (void *)((u8 *)txcmd->data + caplen); | |
3250 | } | |
3251 | ||
3252 | ptr = iwl_queue_dec_wrap(trans, ptr); | |
4d075007 | 3253 | } |
520f03ea | 3254 | spin_unlock_bh(&cmdq->lock); |
4d075007 | 3255 | |
520f03ea SM |
3256 | data->len = cpu_to_le32(len); |
3257 | len += sizeof(*data); | |
3258 | data = iwl_fw_error_next_data(data); | |
4d075007 | 3259 | } |
67c65f2c | 3260 | |
79f033f6 | 3261 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) |
520f03ea | 3262 | len += iwl_trans_pcie_dump_csr(trans, &data); |
79f033f6 | 3263 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) |
520f03ea | 3264 | len += iwl_trans_pcie_fh_regs_dump(trans, &data); |
bd7fc617 EG |
3265 | if (dump_rbs) |
3266 | len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); | |
c2d20201 | 3267 | |
5538409b | 3268 | /* Paged memory for gen2 HW */ |
79f033f6 | 3269 | if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { |
505a00c0 | 3270 | for (i = 0; i < trans->init_dram.paging_cnt; i++) { |
5538409b | 3271 | struct iwl_fw_error_dump_paging *paging; |
505a00c0 | 3272 | u32 page_len = trans->init_dram.paging[i].size; |
5538409b LK |
3273 | |
3274 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); | |
3275 | data->len = cpu_to_le32(sizeof(*paging) + page_len); | |
3276 | paging = (void *)data->data; | |
3277 | paging->index = cpu_to_le32(i); | |
5538409b | 3278 | memcpy(paging->data, |
505a00c0 | 3279 | trans->init_dram.paging[i].block, page_len); |
5538409b LK |
3280 | data = iwl_fw_error_next_data(data); |
3281 | ||
3282 | len += sizeof(*data) + sizeof(*paging) + page_len; | |
3283 | } | |
3284 | } | |
79f033f6 | 3285 | if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) |
520f03ea | 3286 | len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); |
c2d20201 | 3287 | |
48eb7b34 EG |
3288 | dump_data->len = len; |
3289 | ||
3290 | return dump_data; | |
4d075007 | 3291 | } |
87e5666c | 3292 | |
4cbb8e50 LC |
3293 | #ifdef CONFIG_PM_SLEEP |
3294 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) | |
3295 | { | |
e4c49c49 LC |
3296 | if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && |
3297 | (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) | |
4cbb8e50 LC |
3298 | return iwl_pci_fw_enter_d0i3(trans); |
3299 | ||
3300 | return 0; | |
3301 | } | |
3302 | ||
3303 | static void iwl_trans_pcie_resume(struct iwl_trans *trans) | |
3304 | { | |
e4c49c49 LC |
3305 | if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && |
3306 | (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) | |
4cbb8e50 LC |
3307 | iwl_pci_fw_exit_d0i3(trans); |
3308 | } | |
3309 | #endif /* CONFIG_PM_SLEEP */ | |
3310 | ||
623e7766 SS |
3311 | #define IWL_TRANS_COMMON_OPS \ |
3312 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ | |
3313 | .write8 = iwl_trans_pcie_write8, \ | |
3314 | .write32 = iwl_trans_pcie_write32, \ | |
3315 | .read32 = iwl_trans_pcie_read32, \ | |
3316 | .read_prph = iwl_trans_pcie_read_prph, \ | |
3317 | .write_prph = iwl_trans_pcie_write_prph, \ | |
3318 | .read_mem = iwl_trans_pcie_read_mem, \ | |
3319 | .write_mem = iwl_trans_pcie_write_mem, \ | |
3320 | .configure = iwl_trans_pcie_configure, \ | |
3321 | .set_pmi = iwl_trans_pcie_set_pmi, \ | |
870c2a11 | 3322 | .sw_reset = iwl_trans_pcie_sw_reset, \ |
623e7766 SS |
3323 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ |
3324 | .release_nic_access = iwl_trans_pcie_release_nic_access, \ | |
3325 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ | |
3326 | .ref = iwl_trans_pcie_ref, \ | |
3327 | .unref = iwl_trans_pcie_unref, \ | |
3328 | .dump_data = iwl_trans_pcie_dump_data, \ | |
623e7766 | 3329 | .d3_suspend = iwl_trans_pcie_d3_suspend, \ |
d1967ce6 SM |
3330 | .d3_resume = iwl_trans_pcie_d3_resume, \ |
3331 | .sync_nmi = iwl_trans_pcie_sync_nmi | |
623e7766 SS |
3332 | |
3333 | #ifdef CONFIG_PM_SLEEP | |
3334 | #define IWL_TRANS_PM_OPS \ | |
3335 | .suspend = iwl_trans_pcie_suspend, \ | |
3336 | .resume = iwl_trans_pcie_resume, | |
3337 | #else | |
3338 | #define IWL_TRANS_PM_OPS | |
3339 | #endif /* CONFIG_PM_SLEEP */ | |
3340 | ||
d1ff5253 | 3341 | static const struct iwl_trans_ops trans_ops_pcie = { |
623e7766 SS |
3342 | IWL_TRANS_COMMON_OPS, |
3343 | IWL_TRANS_PM_OPS | |
57a1dc89 | 3344 | .start_hw = iwl_trans_pcie_start_hw, |
ed6a3803 | 3345 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 3346 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 3347 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 3348 | |
623e7766 | 3349 | .send_cmd = iwl_trans_pcie_send_hcmd, |
2dd4f9f7 | 3350 | |
623e7766 SS |
3351 | .tx = iwl_trans_pcie_tx, |
3352 | .reclaim = iwl_trans_pcie_reclaim, | |
3353 | ||
3354 | .txq_disable = iwl_trans_pcie_txq_disable, | |
3355 | .txq_enable = iwl_trans_pcie_txq_enable, | |
3356 | ||
3357 | .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, | |
3358 | ||
d6d517b7 SS |
3359 | .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, |
3360 | ||
623e7766 SS |
3361 | .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, |
3362 | .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, | |
f7805b33 LC |
3363 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3364 | .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, | |
3365 | #endif | |
623e7766 SS |
3366 | }; |
3367 | ||
3368 | static const struct iwl_trans_ops trans_ops_pcie_gen2 = { | |
3369 | IWL_TRANS_COMMON_OPS, | |
3370 | IWL_TRANS_PM_OPS | |
3371 | .start_hw = iwl_trans_pcie_start_hw, | |
eda50cde SS |
3372 | .fw_alive = iwl_trans_pcie_gen2_fw_alive, |
3373 | .start_fw = iwl_trans_pcie_gen2_start_fw, | |
77c09bc8 | 3374 | .stop_device = iwl_trans_pcie_gen2_stop_device, |
4cbb8e50 | 3375 | |
ca60da2e | 3376 | .send_cmd = iwl_trans_pcie_gen2_send_hcmd, |
c85eb619 | 3377 | |
ab6c6445 | 3378 | .tx = iwl_trans_pcie_gen2_tx, |
a0eaad71 | 3379 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 3380 | |
6b35ff91 SS |
3381 | .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, |
3382 | .txq_free = iwl_trans_pcie_dyn_txq_free, | |
d6d517b7 | 3383 | .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, |
92536c96 | 3384 | .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, |
f7805b33 LC |
3385 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3386 | .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, | |
3387 | #endif | |
e6bb4c9c | 3388 | }; |
a42a1844 | 3389 | |
87ce05a2 | 3390 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
3391 | const struct pci_device_id *ent, |
3392 | const struct iwl_cfg *cfg) | |
a42a1844 | 3393 | { |
a42a1844 EG |
3394 | struct iwl_trans_pcie *trans_pcie; |
3395 | struct iwl_trans *trans; | |
96a6497b | 3396 | int ret, addr_size; |
a42a1844 | 3397 | |
5a41a86c SD |
3398 | ret = pcim_enable_device(pdev); |
3399 | if (ret) | |
3400 | return ERR_PTR(ret); | |
3401 | ||
623e7766 SS |
3402 | if (cfg->gen2) |
3403 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), | |
3404 | &pdev->dev, cfg, &trans_ops_pcie_gen2); | |
3405 | else | |
3406 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), | |
3407 | &pdev->dev, cfg, &trans_ops_pcie); | |
7b501d10 JB |
3408 | if (!trans) |
3409 | return ERR_PTR(-ENOMEM); | |
a42a1844 EG |
3410 | |
3411 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
3412 | ||
a42a1844 | 3413 | trans_pcie->trans = trans; |
326477e4 | 3414 | trans_pcie->opmode_down = true; |
7b11488f | 3415 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 3416 | spin_lock_init(&trans_pcie->reg_lock); |
fa9f3281 | 3417 | mutex_init(&trans_pcie->mutex); |
13df1aab | 3418 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
6eb5e529 EG |
3419 | trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); |
3420 | if (!trans_pcie->tso_hdr_page) { | |
3421 | ret = -ENOMEM; | |
3422 | goto out_no_pci; | |
3423 | } | |
a42a1844 | 3424 | |
d819c6cf | 3425 | |
f2532b04 EG |
3426 | if (!cfg->base_params->pcie_l1_allowed) { |
3427 | /* | |
3428 | * W/A - seems to solve weird behavior. We need to remove this | |
3429 | * if we don't want to stay in L1 all the time. This wastes a | |
3430 | * lot of power. | |
3431 | */ | |
3432 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
3433 | PCIE_LINK_STATE_L1 | | |
3434 | PCIE_LINK_STATE_CLKPM); | |
3435 | } | |
a42a1844 | 3436 | |
9416560e GBA |
3437 | trans_pcie->def_rx_queue = 0; |
3438 | ||
6983ba69 | 3439 | if (cfg->use_tfh) { |
2c6262b7 | 3440 | addr_size = 64; |
3cd1980b | 3441 | trans_pcie->max_tbs = IWL_TFH_NUM_TBS; |
8352e62a | 3442 | trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); |
6983ba69 | 3443 | } else { |
2c6262b7 | 3444 | addr_size = 36; |
3cd1980b | 3445 | trans_pcie->max_tbs = IWL_NUM_OF_TBS; |
6983ba69 SS |
3446 | trans_pcie->tfd_size = sizeof(struct iwl_tfd); |
3447 | } | |
3cd1980b SS |
3448 | trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); |
3449 | ||
a42a1844 EG |
3450 | pci_set_master(pdev); |
3451 | ||
96a6497b | 3452 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); |
af3f2f74 | 3453 | if (!ret) |
96a6497b SS |
3454 | ret = pci_set_consistent_dma_mask(pdev, |
3455 | DMA_BIT_MASK(addr_size)); | |
af3f2f74 EG |
3456 | if (ret) { |
3457 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
3458 | if (!ret) | |
3459 | ret = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 3460 | DMA_BIT_MASK(32)); |
a42a1844 | 3461 | /* both attempts failed: */ |
af3f2f74 | 3462 | if (ret) { |
6a4b09f8 | 3463 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
5a41a86c | 3464 | goto out_no_pci; |
a42a1844 EG |
3465 | } |
3466 | } | |
3467 | ||
5a41a86c | 3468 | ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); |
af3f2f74 | 3469 | if (ret) { |
5a41a86c SD |
3470 | dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); |
3471 | goto out_no_pci; | |
a42a1844 EG |
3472 | } |
3473 | ||
5a41a86c | 3474 | trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; |
a42a1844 | 3475 | if (!trans_pcie->hw_base) { |
5a41a86c | 3476 | dev_err(&pdev->dev, "pcim_iomap_table failed\n"); |
af3f2f74 | 3477 | ret = -ENODEV; |
5a41a86c | 3478 | goto out_no_pci; |
a42a1844 EG |
3479 | } |
3480 | ||
a42a1844 EG |
3481 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3482 | * PCI Tx retries from interfering with C3 CPU state */ | |
3483 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3484 | ||
83f7a85f EG |
3485 | trans_pcie->pci_dev = pdev; |
3486 | iwl_disable_interrupts(trans); | |
3487 | ||
08079a49 | 3488 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
9a098a89 RJ |
3489 | if (trans->hw_rev == 0xffffffff) { |
3490 | dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); | |
3491 | ret = -EIO; | |
3492 | goto out_no_pci; | |
3493 | } | |
3494 | ||
b513ee7f LK |
3495 | /* |
3496 | * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have | |
3497 | * changed, and now the revision step also includes bit 0-1 (no more | |
3498 | * "dash" value). To keep hw_rev backwards compatible - we'll store it | |
3499 | * in the old format. | |
3500 | */ | |
6e584873 | 3501 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { |
7a42baa6 | 3502 | unsigned long flags; |
7a42baa6 | 3503 | |
b513ee7f | 3504 | trans->hw_rev = (trans->hw_rev & 0xfff0) | |
1fc0e221 | 3505 | (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); |
b513ee7f | 3506 | |
f9e5554c EG |
3507 | ret = iwl_pcie_prepare_card_hw(trans); |
3508 | if (ret) { | |
3509 | IWL_WARN(trans, "Exit HW not ready\n"); | |
5a41a86c | 3510 | goto out_no_pci; |
f9e5554c EG |
3511 | } |
3512 | ||
7a42baa6 EH |
3513 | /* |
3514 | * in-order to recognize C step driver should read chip version | |
3515 | * id located at the AUX bus MISC address space. | |
3516 | */ | |
c96b5eec JB |
3517 | ret = iwl_finish_nic_init(trans); |
3518 | if (ret) | |
5a41a86c | 3519 | goto out_no_pci; |
7a42baa6 | 3520 | |
23ba9340 | 3521 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
7a42baa6 EH |
3522 | u32 hw_step; |
3523 | ||
ea695b7c ST |
3524 | hw_step = iwl_read_umac_prph_no_grab(trans, |
3525 | WFPM_CTRL_REG); | |
7a42baa6 | 3526 | hw_step |= ENABLE_WFPM; |
ea695b7c ST |
3527 | iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG, |
3528 | hw_step); | |
14ef1b43 | 3529 | hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); |
7a42baa6 EH |
3530 | hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; |
3531 | if (hw_step == 0x3) | |
3532 | trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | | |
3533 | (SILICON_C_STEP << 2); | |
3534 | iwl_trans_release_nic_access(trans, &flags); | |
3535 | } | |
3536 | } | |
3537 | ||
99be6166 LC |
3538 | IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); |
3539 | ||
f6586b69 | 3540 | #if IS_ENABLED(CONFIG_IWLMVM) |
1afb0ae4 | 3541 | trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); |
33708052 | 3542 | |
ff911dca ST |
3543 | if (cfg == &iwlax210_2ax_cfg_so_hr_a0) { |
3544 | if (trans->hw_rev == CSR_HW_REV_TYPE_TY) { | |
3545 | trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0; | |
3546 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == | |
3547 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { | |
3548 | trans->cfg = &iwlax210_2ax_cfg_so_jf_a0; | |
3549 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == | |
3550 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) { | |
3551 | trans->cfg = &iwlax210_2ax_cfg_so_gf_a0; | |
5bd757a6 ST |
3552 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == |
3553 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF4)) { | |
3554 | trans->cfg = &iwlax210_2ax_cfg_so_gf4_a0; | |
ff911dca | 3555 | } |
085486de | 3556 | } else if (cfg == &iwl_ax101_cfg_qu_hr) { |
b1bbc1a6 | 3557 | if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == |
debec2f2 LC |
3558 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && |
3559 | trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) { | |
3560 | trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; | |
3561 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == | |
b1bbc1a6 | 3562 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { |
085486de | 3563 | trans->cfg = &iwl_ax101_cfg_qu_hr; |
b1bbc1a6 LC |
3564 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == |
3565 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { | |
3566 | trans->cfg = &iwl22000_2ax_cfg_jf; | |
3567 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == | |
3568 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { | |
3569 | IWL_ERR(trans, "RF ID HRCDB is not supported\n"); | |
3570 | ret = -EINVAL; | |
3571 | goto out_no_pci; | |
3572 | } else { | |
3573 | IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", | |
3574 | CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); | |
3575 | ret = -EINVAL; | |
3576 | goto out_no_pci; | |
3577 | } | |
3578 | } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == | |
8093bb6d | 3579 | CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && |
0d5bad14 | 3580 | (trans->cfg != &iwl_ax200_cfg_cc || |
99be6166 | 3581 | trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0)) { |
f6586b69 TP |
3582 | u32 hw_status; |
3583 | ||
3584 | hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); | |
33708052 LC |
3585 | if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) |
3586 | /* | |
3587 | * b step fw is the same for physical card and fpga | |
3588 | */ | |
3589 | trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; | |
3590 | else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && | |
3591 | CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { | |
3592 | trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; | |
3593 | } else { | |
3594 | /* | |
3595 | * a step no FPGA | |
3596 | */ | |
2f7a3863 | 3597 | trans->cfg = &iwl22000_2ac_cfg_hr; |
33708052 | 3598 | } |
f6586b69 TP |
3599 | } |
3600 | #endif | |
1afb0ae4 | 3601 | |
2e5d4a8f | 3602 | iwl_pcie_set_interrupt_capa(pdev, trans); |
99673ee5 | 3603 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
3604 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
3605 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 3606 | |
69a10b29 | 3607 | /* Initialize the wait queue for commands */ |
f946b529 | 3608 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 3609 | |
4cbb8e50 LC |
3610 | init_waitqueue_head(&trans_pcie->d0i3_waitq); |
3611 | ||
2e5d4a8f | 3612 | if (trans_pcie->msix_enabled) { |
2388bd7b DC |
3613 | ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); |
3614 | if (ret) | |
5a41a86c | 3615 | goto out_no_pci; |
2e5d4a8f HD |
3616 | } else { |
3617 | ret = iwl_pcie_alloc_ict(trans); | |
3618 | if (ret) | |
5a41a86c | 3619 | goto out_no_pci; |
a8b691e6 | 3620 | |
5a41a86c SD |
3621 | ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, |
3622 | iwl_pcie_isr, | |
3623 | iwl_pcie_irq_handler, | |
3624 | IRQF_SHARED, DRV_NAME, trans); | |
2e5d4a8f HD |
3625 | if (ret) { |
3626 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); | |
3627 | goto out_free_ict; | |
3628 | } | |
3629 | trans_pcie->inta_mask = CSR_INI_SET_MASK; | |
3630 | } | |
83f7a85f | 3631 | |
10a54d81 LC |
3632 | trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", |
3633 | WQ_HIGHPRI | WQ_UNBOUND, 1); | |
3634 | INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); | |
3635 | ||
b3ff1270 LC |
3636 | #ifdef CONFIG_IWLWIFI_PCIE_RTPM |
3637 | trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; | |
3638 | #else | |
3639 | trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; | |
3640 | #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ | |
3641 | ||
f7805b33 LC |
3642 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3643 | trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; | |
3644 | mutex_init(&trans_pcie->fw_mon_data.mutex); | |
3645 | #endif | |
3646 | ||
a42a1844 EG |
3647 | return trans; |
3648 | ||
a8b691e6 JB |
3649 | out_free_ict: |
3650 | iwl_pcie_free_ict(trans); | |
a42a1844 | 3651 | out_no_pci: |
6eb5e529 | 3652 | free_percpu(trans_pcie->tso_hdr_page); |
7b501d10 | 3653 | iwl_trans_free(trans); |
af3f2f74 | 3654 | return ERR_PTR(ret); |
a42a1844 | 3655 | } |
b8a7547d | 3656 | |
d1967ce6 | 3657 | void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) |
b8a7547d SM |
3658 | { |
3659 | unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; | |
3660 | ||
3661 | iwl_disable_interrupts(trans); | |
3662 | iwl_force_nmi(trans); | |
3663 | while (time_after(timeout, jiffies)) { | |
3664 | u32 inta_hw = iwl_read32(trans, | |
3665 | CSR_MSIX_HW_INT_CAUSES_AD); | |
3666 | ||
3667 | /* Error detected by uCode */ | |
3668 | if (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) { | |
3669 | /* Clear causes register */ | |
3670 | iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, | |
3671 | inta_hw & | |
3672 | MSIX_HW_INT_CAUSES_REG_SW_ERR); | |
3673 | break; | |
3674 | } | |
3675 | ||
3676 | mdelay(1); | |
3677 | } | |
3678 | iwl_enable_interrupts(trans); | |
3679 | iwl_trans_fw_error(trans); | |
3680 | } |