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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
553452e5 LK |
8 | * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. |
9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
62d7476d | 10 | * Copyright(c) 2016 Intel Deutschland GmbH |
c85eb619 EG |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
24 | * USA | |
25 | * | |
26 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 27 | * in the file called COPYING. |
c85eb619 EG |
28 | * |
29 | * Contact Information: | |
cb2f8277 | 30 | * Intel Linux Wireless <linuxwifi@intel.com> |
c85eb619 EG |
31 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
32 | * | |
33 | * BSD LICENSE | |
34 | * | |
553452e5 LK |
35 | * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. |
36 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
62d7476d | 37 | * Copyright(c) 2016 Intel Deutschland GmbH |
c85eb619 EG |
38 | * All rights reserved. |
39 | * | |
40 | * Redistribution and use in source and binary forms, with or without | |
41 | * modification, are permitted provided that the following conditions | |
42 | * are met: | |
43 | * | |
44 | * * Redistributions of source code must retain the above copyright | |
45 | * notice, this list of conditions and the following disclaimer. | |
46 | * * Redistributions in binary form must reproduce the above copyright | |
47 | * notice, this list of conditions and the following disclaimer in | |
48 | * the documentation and/or other materials provided with the | |
49 | * distribution. | |
50 | * * Neither the name Intel Corporation nor the names of its | |
51 | * contributors may be used to endorse or promote products derived | |
52 | * from this software without specific prior written permission. | |
53 | * | |
54 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
55 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
56 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
57 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
58 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
59 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
60 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
61 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
62 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
63 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
64 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
65 | * | |
66 | *****************************************************************************/ | |
a42a1844 EG |
67 | #include <linux/pci.h> |
68 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 69 | #include <linux/interrupt.h> |
87e5666c | 70 | #include <linux/debugfs.h> |
cf614297 | 71 | #include <linux/sched.h> |
6d8f6eeb EG |
72 | #include <linux/bitops.h> |
73 | #include <linux/gfp.h> | |
48eb7b34 | 74 | #include <linux/vmalloc.h> |
b3ff1270 | 75 | #include <linux/pm_runtime.h> |
e6bb4c9c | 76 | |
82575102 | 77 | #include "iwl-drv.h" |
c85eb619 | 78 | #include "iwl-trans.h" |
522376d2 EG |
79 | #include "iwl-csr.h" |
80 | #include "iwl-prph.h" | |
cb6bb128 | 81 | #include "iwl-scd.h" |
7a10e3e4 | 82 | #include "iwl-agn-hw.h" |
4d075007 | 83 | #include "iwl-fw-error-dump.h" |
6468a01a | 84 | #include "internal.h" |
06d51e0d | 85 | #include "iwl-fh.h" |
0439bb62 | 86 | |
fe45773b AN |
87 | /* extended range in FW SRAM */ |
88 | #define IWL_FW_MEM_EXTENDED_START 0x40000 | |
89 | #define IWL_FW_MEM_EXTENDED_END 0x57FFF | |
90 | ||
c2d20201 EG |
91 | static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) |
92 | { | |
93 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
94 | ||
95 | if (!trans_pcie->fw_mon_page) | |
96 | return; | |
97 | ||
98 | dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, | |
99 | trans_pcie->fw_mon_size, DMA_FROM_DEVICE); | |
100 | __free_pages(trans_pcie->fw_mon_page, | |
101 | get_order(trans_pcie->fw_mon_size)); | |
102 | trans_pcie->fw_mon_page = NULL; | |
103 | trans_pcie->fw_mon_phys = 0; | |
104 | trans_pcie->fw_mon_size = 0; | |
105 | } | |
106 | ||
96c285da | 107 | static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) |
c2d20201 EG |
108 | { |
109 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
553452e5 | 110 | struct page *page = NULL; |
c2d20201 | 111 | dma_addr_t phys; |
96c285da | 112 | u32 size = 0; |
c2d20201 EG |
113 | u8 power; |
114 | ||
96c285da EG |
115 | if (!max_power) { |
116 | /* default max_power is maximum */ | |
117 | max_power = 26; | |
118 | } else { | |
119 | max_power += 11; | |
120 | } | |
121 | ||
122 | if (WARN(max_power > 26, | |
123 | "External buffer size for monitor is too big %d, check the FW TLV\n", | |
124 | max_power)) | |
125 | return; | |
126 | ||
c2d20201 EG |
127 | if (trans_pcie->fw_mon_page) { |
128 | dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, | |
129 | trans_pcie->fw_mon_size, | |
130 | DMA_FROM_DEVICE); | |
131 | return; | |
132 | } | |
133 | ||
134 | phys = 0; | |
96c285da | 135 | for (power = max_power; power >= 11; power--) { |
c2d20201 EG |
136 | int order; |
137 | ||
138 | size = BIT(power); | |
139 | order = get_order(size); | |
140 | page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, | |
141 | order); | |
142 | if (!page) | |
143 | continue; | |
144 | ||
145 | phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, | |
146 | DMA_FROM_DEVICE); | |
147 | if (dma_mapping_error(trans->dev, phys)) { | |
148 | __free_pages(page, order); | |
553452e5 | 149 | page = NULL; |
c2d20201 EG |
150 | continue; |
151 | } | |
152 | IWL_INFO(trans, | |
153 | "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", | |
154 | size, order); | |
155 | break; | |
156 | } | |
157 | ||
40a76905 | 158 | if (WARN_ON_ONCE(!page)) |
c2d20201 EG |
159 | return; |
160 | ||
96c285da EG |
161 | if (power != max_power) |
162 | IWL_ERR(trans, | |
163 | "Sorry - debug buffer is only %luK while you requested %luK\n", | |
164 | (unsigned long)BIT(power - 10), | |
165 | (unsigned long)BIT(max_power - 10)); | |
166 | ||
c2d20201 EG |
167 | trans_pcie->fw_mon_page = page; |
168 | trans_pcie->fw_mon_phys = phys; | |
169 | trans_pcie->fw_mon_size = size; | |
170 | } | |
171 | ||
a812cba9 AB |
172 | static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) |
173 | { | |
174 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
175 | ((reg & 0x0000ffff) | (2 << 28))); | |
176 | return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); | |
177 | } | |
178 | ||
179 | static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) | |
180 | { | |
181 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); | |
182 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
183 | ((reg & 0x0000ffff) | (3 << 28))); | |
184 | } | |
185 | ||
ddaf5a5b | 186 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 187 | { |
66337b7c | 188 | if (trans->cfg->apmg_not_supported) |
95411d04 AA |
189 | return; |
190 | ||
ddaf5a5b JB |
191 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
192 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
193 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
194 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
195 | else | |
196 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
197 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
198 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
199 | } |
200 | ||
af634bee EG |
201 | /* PCI registers */ |
202 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 203 | |
7afe3705 | 204 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 205 | { |
20d3b647 | 206 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 207 | u16 lctl; |
9180ac50 | 208 | u16 cap; |
af634bee | 209 | |
af634bee EG |
210 | /* |
211 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
212 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
213 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
214 | * costs negligible amount of power savings. | |
215 | * If not (unlikely), enable L0S, so there is at least some | |
216 | * power savings, even without L1. | |
217 | */ | |
7afe3705 | 218 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
9180ac50 | 219 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) |
af634bee | 220 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
9180ac50 | 221 | else |
af634bee | 222 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
438a0f0a | 223 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
9180ac50 EG |
224 | |
225 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); | |
226 | trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; | |
227 | dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", | |
228 | (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", | |
229 | trans->ltr_enabled ? "En" : "Dis"); | |
af634bee EG |
230 | } |
231 | ||
a6c684ee EG |
232 | /* |
233 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 234 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
235 | * NOTE: This does not load uCode nor start the embedded processor |
236 | */ | |
7afe3705 | 237 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee EG |
238 | { |
239 | int ret = 0; | |
240 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
241 | ||
242 | /* | |
243 | * Use "set_bit" below rather than "write", to preserve any hardware | |
244 | * bits already set by default after reset. | |
245 | */ | |
246 | ||
247 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
e4a9f8ce EH |
248 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
249 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
250 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
a6c684ee EG |
251 | |
252 | /* | |
253 | * Disable L0s without affecting L1; | |
254 | * don't wait for ICH L0s (ICH bug W/A) | |
255 | */ | |
256 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 257 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
258 | |
259 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
260 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
261 | ||
262 | /* | |
263 | * Enable HAP INTA (interrupt from management bus) to | |
264 | * wake device's PCI Express link L1a -> L0s | |
265 | */ | |
266 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 267 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 268 | |
7afe3705 | 269 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
270 | |
271 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 272 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 273 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 274 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
275 | |
276 | /* | |
277 | * Set "initialization complete" bit to move adapter from | |
278 | * D0U* --> D0A* (powered-up active) state. | |
279 | */ | |
280 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
281 | ||
282 | /* | |
283 | * Wait for clock stabilization; once stabilized, access to | |
284 | * device-internal resources is supported, e.g. iwl_write_prph() | |
285 | * and accesses to uCode SRAM. | |
286 | */ | |
287 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
288 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
289 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
290 | if (ret < 0) { |
291 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
292 | goto out; | |
293 | } | |
294 | ||
2d93aee1 EG |
295 | if (trans->cfg->host_interrupt_operation_mode) { |
296 | /* | |
297 | * This is a bit of an abuse - This is needed for 7260 / 3160 | |
298 | * only check host_interrupt_operation_mode even if this is | |
299 | * not related to host_interrupt_operation_mode. | |
300 | * | |
301 | * Enable the oscillator to count wake up time for L1 exit. This | |
302 | * consumes slightly more power (100uA) - but allows to be sure | |
303 | * that we wake up from L1 on time. | |
304 | * | |
305 | * This looks weird: read twice the same register, discard the | |
306 | * value, set a bit, and yet again, read that same register | |
307 | * just to discard the value. But that's the way the hardware | |
308 | * seems to like it. | |
309 | */ | |
310 | iwl_read_prph(trans, OSC_CLK); | |
311 | iwl_read_prph(trans, OSC_CLK); | |
312 | iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); | |
313 | iwl_read_prph(trans, OSC_CLK); | |
314 | iwl_read_prph(trans, OSC_CLK); | |
315 | } | |
316 | ||
a6c684ee EG |
317 | /* |
318 | * Enable DMA clock and wait for it to stabilize. | |
319 | * | |
3073d8c0 EH |
320 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" |
321 | * bits do not disable clocks. This preserves any hardware | |
322 | * bits already set by default in "CLK_CTRL_REG" after reset. | |
a6c684ee | 323 | */ |
95411d04 | 324 | if (!trans->cfg->apmg_not_supported) { |
3073d8c0 EH |
325 | iwl_write_prph(trans, APMG_CLK_EN_REG, |
326 | APMG_CLK_VAL_DMA_CLK_RQT); | |
327 | udelay(20); | |
328 | ||
329 | /* Disable L1-Active */ | |
330 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
331 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
332 | ||
333 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ | |
334 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, | |
335 | APMG_RTC_INT_STT_RFKILL); | |
336 | } | |
889b1696 | 337 | |
eb7ff77e | 338 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee EG |
339 | |
340 | out: | |
341 | return ret; | |
342 | } | |
343 | ||
a812cba9 AB |
344 | /* |
345 | * Enable LP XTAL to avoid HW bug where device may consume much power if | |
346 | * FW is not loaded after device reset. LP XTAL is disabled by default | |
347 | * after device HW reset. Do it only if XTAL is fed by internal source. | |
348 | * Configure device's "persistence" mode to avoid resetting XTAL again when | |
349 | * SHRD_HW_RST occurs in S3. | |
350 | */ | |
351 | static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) | |
352 | { | |
353 | int ret; | |
354 | u32 apmg_gp1_reg; | |
355 | u32 apmg_xtal_cfg_reg; | |
356 | u32 dl_cfg_reg; | |
357 | ||
358 | /* Force XTAL ON */ | |
359 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
360 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
361 | ||
362 | /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ | |
363 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
364 | ||
365 | udelay(10); | |
366 | ||
367 | /* | |
368 | * Set "initialization complete" bit to move adapter from | |
369 | * D0U* --> D0A* (powered-up active) state. | |
370 | */ | |
371 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
372 | ||
373 | /* | |
374 | * Wait for clock stabilization; once stabilized, access to | |
375 | * device-internal resources is possible. | |
376 | */ | |
377 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
378 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
379 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
380 | 25000); | |
381 | if (WARN_ON(ret < 0)) { | |
382 | IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); | |
383 | /* Release XTAL ON request */ | |
384 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
385 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
386 | return; | |
387 | } | |
388 | ||
389 | /* | |
390 | * Clear "disable persistence" to avoid LP XTAL resetting when | |
391 | * SHRD_HW_RST is applied in S3. | |
392 | */ | |
393 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
394 | APMG_PCIDEV_STT_VAL_PERSIST_DIS); | |
395 | ||
396 | /* | |
397 | * Force APMG XTAL to be active to prevent its disabling by HW | |
398 | * caused by APMG idle state. | |
399 | */ | |
400 | apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, | |
401 | SHR_APMG_XTAL_CFG_REG); | |
402 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
403 | apmg_xtal_cfg_reg | | |
404 | SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
405 | ||
406 | /* | |
407 | * Reset entire device again - do controller reset (results in | |
408 | * SHRD_HW_RST). Turn MAC off before proceeding. | |
409 | */ | |
410 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
411 | ||
412 | udelay(10); | |
413 | ||
414 | /* Enable LP XTAL by indirect access through CSR */ | |
415 | apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); | |
416 | iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | | |
417 | SHR_APMG_GP1_WF_XTAL_LP_EN | | |
418 | SHR_APMG_GP1_CHICKEN_BIT_SELECT); | |
419 | ||
420 | /* Clear delay line clock power up */ | |
421 | dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); | |
422 | iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & | |
423 | ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); | |
424 | ||
425 | /* | |
426 | * Enable persistence mode to avoid LP XTAL resetting when | |
427 | * SHRD_HW_RST is applied in S3. | |
428 | */ | |
429 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
430 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
431 | ||
432 | /* | |
433 | * Clear "initialization complete" bit to move adapter from | |
434 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
435 | */ | |
436 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
437 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
438 | ||
439 | /* Activates XTAL resources monitor */ | |
440 | __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, | |
441 | CSR_MONITOR_XTAL_RESOURCES); | |
442 | ||
443 | /* Release XTAL ON request */ | |
444 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
445 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
446 | udelay(10); | |
447 | ||
448 | /* Release APMG XTAL */ | |
449 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
450 | apmg_xtal_cfg_reg & | |
451 | ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
452 | } | |
453 | ||
7afe3705 | 454 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
455 | { |
456 | int ret = 0; | |
457 | ||
458 | /* stop device's busmaster DMA activity */ | |
459 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
460 | ||
461 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
462 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
463 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
7f2ac8fb | 464 | if (ret < 0) |
cc56feb2 EG |
465 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); |
466 | ||
467 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
468 | ||
469 | return ret; | |
470 | } | |
471 | ||
b7aaeae4 | 472 | static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) |
cc56feb2 EG |
473 | { |
474 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
475 | ||
b7aaeae4 EG |
476 | if (op_mode_leave) { |
477 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
478 | iwl_pcie_apm_init(trans); | |
479 | ||
480 | /* inform ME that we are leaving */ | |
481 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) | |
482 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
483 | APMG_PCIDEV_STT_VAL_WAKE_ME); | |
c9fdec9f EG |
484 | else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { |
485 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, | |
486 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
b7aaeae4 EG |
487 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
488 | CSR_HW_IF_CONFIG_REG_PREPARE | | |
489 | CSR_HW_IF_CONFIG_REG_ENABLE_PME); | |
c9fdec9f EG |
490 | mdelay(1); |
491 | iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, | |
492 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
493 | } | |
b7aaeae4 EG |
494 | mdelay(5); |
495 | } | |
496 | ||
eb7ff77e | 497 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
498 | |
499 | /* Stop device's DMA activity */ | |
7afe3705 | 500 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 | 501 | |
a812cba9 AB |
502 | if (trans->cfg->lp_xtal_workaround) { |
503 | iwl_pcie_apm_lp_xtal_enable(trans); | |
504 | return; | |
505 | } | |
506 | ||
cc56feb2 EG |
507 | /* Reset the entire device */ |
508 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
509 | ||
510 | udelay(10); | |
511 | ||
512 | /* | |
513 | * Clear "initialization complete" bit to move adapter from | |
514 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
515 | */ | |
516 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
517 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
518 | } | |
519 | ||
7afe3705 | 520 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 521 | { |
7b11488f | 522 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
523 | |
524 | /* nic_init */ | |
7b70bd63 | 525 | spin_lock(&trans_pcie->irq_lock); |
7afe3705 | 526 | iwl_pcie_apm_init(trans); |
392f8b78 | 527 | |
7b70bd63 | 528 | spin_unlock(&trans_pcie->irq_lock); |
392f8b78 | 529 | |
95411d04 | 530 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 531 | |
ecdb975c | 532 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
533 | |
534 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 535 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
536 | |
537 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 538 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
539 | return -ENOMEM; |
540 | ||
035f7ff2 | 541 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 542 | /* enable shadow regs in HW */ |
20d3b647 | 543 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 544 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
545 | } |
546 | ||
392f8b78 EG |
547 | return 0; |
548 | } | |
549 | ||
550 | #define HW_READY_TIMEOUT (50) | |
551 | ||
552 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 553 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
554 | { |
555 | int ret; | |
556 | ||
1042db2a | 557 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 558 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
559 | |
560 | /* See if we got it */ | |
1042db2a | 561 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
562 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
563 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
564 | HW_READY_TIMEOUT); | |
392f8b78 | 565 | |
6a08f514 EG |
566 | if (ret >= 0) |
567 | iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); | |
568 | ||
6d8f6eeb | 569 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
570 | return ret; |
571 | } | |
572 | ||
573 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 574 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
575 | { |
576 | int ret; | |
289e5501 | 577 | int t = 0; |
501fd989 | 578 | int iter; |
392f8b78 | 579 | |
6d8f6eeb | 580 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 581 | |
7afe3705 | 582 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 583 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
584 | if (ret >= 0) |
585 | return 0; | |
586 | ||
c9fdec9f EG |
587 | iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, |
588 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
589 | msleep(1); | |
590 | ||
501fd989 EG |
591 | for (iter = 0; iter < 10; iter++) { |
592 | /* If HW is not ready, prepare the conditions to check again */ | |
593 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
594 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
595 | ||
596 | do { | |
597 | ret = iwl_pcie_set_hw_ready(trans); | |
03a19cbb EG |
598 | if (ret >= 0) |
599 | return 0; | |
392f8b78 | 600 | |
501fd989 EG |
601 | usleep_range(200, 1000); |
602 | t += 200; | |
603 | } while (t < 150000); | |
604 | msleep(25); | |
605 | } | |
392f8b78 | 606 | |
7f2ac8fb | 607 | IWL_ERR(trans, "Couldn't prepare the card\n"); |
392f8b78 | 608 | |
392f8b78 EG |
609 | return ret; |
610 | } | |
611 | ||
cf614297 EG |
612 | /* |
613 | * ucode | |
614 | */ | |
7afe3705 | 615 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 616 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 617 | { |
13df1aab | 618 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
bac842da | 619 | unsigned long flags; |
cf614297 EG |
620 | int ret; |
621 | ||
13df1aab | 622 | trans_pcie->ucode_write_complete = false; |
cf614297 | 623 | |
bac842da EG |
624 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
625 | return -EIO; | |
626 | ||
627 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
628 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
629 | ||
630 | iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), | |
631 | dst_addr); | |
632 | ||
633 | iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
634 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
635 | ||
636 | iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), | |
637 | (iwl_get_dma_hi_addr(phy_addr) | |
638 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
639 | ||
640 | iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
641 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | | |
642 | BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | | |
643 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
644 | ||
645 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
646 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
647 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
648 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
649 | ||
650 | iwl_trans_release_nic_access(trans, &flags); | |
cf614297 | 651 | |
13df1aab JB |
652 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
653 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 654 | if (!ret) { |
83f84d7b | 655 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
656 | return -ETIMEDOUT; |
657 | } | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
7afe3705 | 662 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 663 | const struct fw_desc *section) |
cf614297 | 664 | { |
83f84d7b JB |
665 | u8 *v_addr; |
666 | dma_addr_t p_addr; | |
baa21e83 | 667 | u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); |
cf614297 EG |
668 | int ret = 0; |
669 | ||
83f84d7b JB |
670 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
671 | section_num); | |
672 | ||
c571573a EG |
673 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
674 | GFP_KERNEL | __GFP_NOWARN); | |
675 | if (!v_addr) { | |
676 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
677 | chunk_sz = PAGE_SIZE; | |
678 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
679 | &p_addr, GFP_KERNEL); | |
680 | if (!v_addr) | |
681 | return -ENOMEM; | |
682 | } | |
83f84d7b | 683 | |
c571573a | 684 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
fe45773b AN |
685 | u32 copy_size, dst_addr; |
686 | bool extended_addr = false; | |
83f84d7b | 687 | |
c571573a | 688 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
fe45773b AN |
689 | dst_addr = section->offset + offset; |
690 | ||
691 | if (dst_addr >= IWL_FW_MEM_EXTENDED_START && | |
692 | dst_addr <= IWL_FW_MEM_EXTENDED_END) | |
693 | extended_addr = true; | |
694 | ||
695 | if (extended_addr) | |
696 | iwl_set_bits_prph(trans, LMPM_CHICK, | |
697 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
cf614297 | 698 | |
83f84d7b | 699 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
fe45773b AN |
700 | ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, |
701 | copy_size); | |
702 | ||
703 | if (extended_addr) | |
704 | iwl_clear_bits_prph(trans, LMPM_CHICK, | |
705 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
706 | ||
83f84d7b JB |
707 | if (ret) { |
708 | IWL_ERR(trans, | |
709 | "Could not load the [%d] uCode section\n", | |
710 | section_num); | |
711 | break; | |
6dfa8d01 | 712 | } |
83f84d7b JB |
713 | } |
714 | ||
c571573a | 715 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
716 | return ret; |
717 | } | |
718 | ||
16bc119b EH |
719 | /* |
720 | * Driver Takes the ownership on secure machine before FW load | |
721 | * and prevent race with the BT load. | |
722 | * W/A for ROM bug. (should be remove in the next Si step) | |
723 | */ | |
724 | static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) | |
725 | { | |
726 | u32 val, loop = 1000; | |
727 | ||
1e167071 EH |
728 | /* |
729 | * Check the RSA semaphore is accessible. | |
730 | * If the HW isn't locked and the rsa semaphore isn't accessible, | |
731 | * we are in trouble. | |
732 | */ | |
16bc119b EH |
733 | val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); |
734 | if (val & (BIT(1) | BIT(17))) { | |
1e167071 EH |
735 | IWL_INFO(trans, |
736 | "can't access the RSA semaphore it is write protected\n"); | |
16bc119b EH |
737 | return 0; |
738 | } | |
739 | ||
740 | /* take ownership on the AUX IF */ | |
741 | iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); | |
742 | iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); | |
743 | ||
744 | do { | |
745 | iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); | |
746 | val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); | |
747 | if (val == 0x1) { | |
748 | iwl_write_prph(trans, RSA_ENABLE, 0); | |
749 | return 0; | |
750 | } | |
751 | ||
752 | udelay(10); | |
753 | loop--; | |
754 | } while (loop > 0); | |
755 | ||
756 | IWL_ERR(trans, "Failed to take ownership on secure machine\n"); | |
757 | return -EIO; | |
758 | } | |
759 | ||
5dd9c68a EG |
760 | static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, |
761 | const struct fw_img *image, | |
762 | int cpu, | |
763 | int *first_ucode_section) | |
e2d6f4e7 EH |
764 | { |
765 | int shift_param; | |
dcab8ecd EH |
766 | int i, ret = 0, sec_num = 0x1; |
767 | u32 val, last_read_idx = 0; | |
e2d6f4e7 EH |
768 | |
769 | if (cpu == 1) { | |
770 | shift_param = 0; | |
034846cf | 771 | *first_ucode_section = 0; |
e2d6f4e7 EH |
772 | } else { |
773 | shift_param = 16; | |
034846cf | 774 | (*first_ucode_section)++; |
e2d6f4e7 EH |
775 | } |
776 | ||
034846cf EH |
777 | for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { |
778 | last_read_idx = i; | |
779 | ||
a6c4fb44 MG |
780 | /* |
781 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between | |
782 | * CPU1 to CPU2. | |
783 | * PAGING_SEPARATOR_SECTION delimiter - separate between | |
784 | * CPU2 non paged to CPU2 paging sec. | |
785 | */ | |
034846cf | 786 | if (!image->sec[i].data || |
a6c4fb44 MG |
787 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
788 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { | |
034846cf EH |
789 | IWL_DEBUG_FW(trans, |
790 | "Break since Data not valid or Empty section, sec = %d\n", | |
791 | i); | |
189fa2fa | 792 | break; |
034846cf EH |
793 | } |
794 | ||
189fa2fa EH |
795 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
796 | if (ret) | |
797 | return ret; | |
dcab8ecd EH |
798 | |
799 | /* Notify the ucode of the loaded section number and status */ | |
800 | val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); | |
801 | val = val | (sec_num << shift_param); | |
802 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); | |
803 | sec_num = (sec_num << 1) | 0x1; | |
e2d6f4e7 EH |
804 | } |
805 | ||
034846cf EH |
806 | *first_ucode_section = last_read_idx; |
807 | ||
afb88917 EH |
808 | if (cpu == 1) |
809 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); | |
810 | else | |
811 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); | |
812 | ||
189fa2fa EH |
813 | return 0; |
814 | } | |
e2d6f4e7 | 815 | |
189fa2fa EH |
816 | static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, |
817 | const struct fw_img *image, | |
034846cf EH |
818 | int cpu, |
819 | int *first_ucode_section) | |
189fa2fa EH |
820 | { |
821 | int shift_param; | |
189fa2fa | 822 | int i, ret = 0; |
034846cf | 823 | u32 last_read_idx = 0; |
189fa2fa EH |
824 | |
825 | if (cpu == 1) { | |
826 | shift_param = 0; | |
034846cf | 827 | *first_ucode_section = 0; |
189fa2fa EH |
828 | } else { |
829 | shift_param = 16; | |
034846cf | 830 | (*first_ucode_section)++; |
189fa2fa EH |
831 | } |
832 | ||
034846cf EH |
833 | for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { |
834 | last_read_idx = i; | |
835 | ||
a6c4fb44 MG |
836 | /* |
837 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between | |
838 | * CPU1 to CPU2. | |
839 | * PAGING_SEPARATOR_SECTION delimiter - separate between | |
840 | * CPU2 non paged to CPU2 paging sec. | |
841 | */ | |
034846cf | 842 | if (!image->sec[i].data || |
a6c4fb44 MG |
843 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || |
844 | image->sec[i].offset == PAGING_SEPARATOR_SECTION) { | |
034846cf EH |
845 | IWL_DEBUG_FW(trans, |
846 | "Break since Data not valid or Empty section, sec = %d\n", | |
847 | i); | |
189fa2fa | 848 | break; |
034846cf EH |
849 | } |
850 | ||
189fa2fa EH |
851 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
852 | if (ret) | |
853 | return ret; | |
e2d6f4e7 EH |
854 | } |
855 | ||
189fa2fa EH |
856 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
857 | iwl_set_bits_prph(trans, | |
858 | CSR_UCODE_LOAD_STATUS_ADDR, | |
859 | (LMPM_CPU_UCODE_LOADING_COMPLETED | | |
860 | LMPM_CPU_HDRS_LOADING_COMPLETED | | |
861 | LMPM_CPU_UCODE_LOADING_STARTED) << | |
862 | shift_param); | |
863 | ||
034846cf EH |
864 | *first_ucode_section = last_read_idx; |
865 | ||
e2d6f4e7 EH |
866 | return 0; |
867 | } | |
868 | ||
09e350f7 LK |
869 | static void iwl_pcie_apply_destination(struct iwl_trans *trans) |
870 | { | |
871 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
872 | const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; | |
873 | int i; | |
874 | ||
875 | if (dest->version) | |
876 | IWL_ERR(trans, | |
877 | "DBG DEST version is %d - expect issues\n", | |
878 | dest->version); | |
879 | ||
880 | IWL_INFO(trans, "Applying debug destination %s\n", | |
881 | get_fw_dbg_mode_string(dest->monitor_mode)); | |
882 | ||
883 | if (dest->monitor_mode == EXTERNAL_MODE) | |
96c285da | 884 | iwl_pcie_alloc_fw_monitor(trans, dest->size_power); |
09e350f7 LK |
885 | else |
886 | IWL_WARN(trans, "PCI should have external buffer debug\n"); | |
887 | ||
888 | for (i = 0; i < trans->dbg_dest_reg_num; i++) { | |
889 | u32 addr = le32_to_cpu(dest->reg_ops[i].addr); | |
890 | u32 val = le32_to_cpu(dest->reg_ops[i].val); | |
891 | ||
892 | switch (dest->reg_ops[i].op) { | |
893 | case CSR_ASSIGN: | |
894 | iwl_write32(trans, addr, val); | |
895 | break; | |
896 | case CSR_SETBIT: | |
897 | iwl_set_bit(trans, addr, BIT(val)); | |
898 | break; | |
899 | case CSR_CLEARBIT: | |
900 | iwl_clear_bit(trans, addr, BIT(val)); | |
901 | break; | |
902 | case PRPH_ASSIGN: | |
903 | iwl_write_prph(trans, addr, val); | |
904 | break; | |
905 | case PRPH_SETBIT: | |
906 | iwl_set_bits_prph(trans, addr, BIT(val)); | |
907 | break; | |
908 | case PRPH_CLEARBIT: | |
909 | iwl_clear_bits_prph(trans, addr, BIT(val)); | |
910 | break; | |
869f3b15 HD |
911 | case PRPH_BLOCKBIT: |
912 | if (iwl_read_prph(trans, addr) & BIT(val)) { | |
913 | IWL_ERR(trans, | |
914 | "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", | |
915 | val, addr); | |
916 | goto monitor; | |
917 | } | |
918 | break; | |
09e350f7 LK |
919 | default: |
920 | IWL_ERR(trans, "FW debug - unknown OP %d\n", | |
921 | dest->reg_ops[i].op); | |
922 | break; | |
923 | } | |
924 | } | |
925 | ||
869f3b15 | 926 | monitor: |
09e350f7 LK |
927 | if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { |
928 | iwl_write_prph(trans, le32_to_cpu(dest->base_reg), | |
929 | trans_pcie->fw_mon_phys >> dest->base_shift); | |
62d7476d EG |
930 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
931 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), | |
932 | (trans_pcie->fw_mon_phys + | |
933 | trans_pcie->fw_mon_size - 256) >> | |
934 | dest->end_shift); | |
935 | else | |
936 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), | |
937 | (trans_pcie->fw_mon_phys + | |
938 | trans_pcie->fw_mon_size) >> | |
939 | dest->end_shift); | |
09e350f7 LK |
940 | } |
941 | } | |
942 | ||
7afe3705 | 943 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 944 | const struct fw_img *image) |
cf614297 | 945 | { |
c2d20201 | 946 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
189fa2fa | 947 | int ret = 0; |
034846cf | 948 | int first_ucode_section; |
cf614297 | 949 | |
dcab8ecd | 950 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
e2d6f4e7 EH |
951 | image->is_dual_cpus ? "Dual" : "Single"); |
952 | ||
dcab8ecd EH |
953 | /* load to FW the binary non secured sections of CPU1 */ |
954 | ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); | |
955 | if (ret) | |
956 | return ret; | |
e2d6f4e7 EH |
957 | |
958 | if (image->is_dual_cpus) { | |
189fa2fa EH |
959 | /* set CPU2 header address */ |
960 | iwl_write_prph(trans, | |
961 | LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, | |
962 | LMPM_SECURE_CPU2_HDR_MEM_SPACE); | |
e2d6f4e7 | 963 | |
189fa2fa | 964 | /* load to FW the binary sections of CPU2 */ |
dcab8ecd EH |
965 | ret = iwl_pcie_load_cpu_sections(trans, image, 2, |
966 | &first_ucode_section); | |
189fa2fa EH |
967 | if (ret) |
968 | return ret; | |
e2d6f4e7 | 969 | } |
cf614297 | 970 | |
c2d20201 EG |
971 | /* supported for 7000 only for the moment */ |
972 | if (iwlwifi_mod_params.fw_monitor && | |
973 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { | |
96c285da | 974 | iwl_pcie_alloc_fw_monitor(trans, 0); |
c2d20201 EG |
975 | |
976 | if (trans_pcie->fw_mon_size) { | |
977 | iwl_write_prph(trans, MON_BUFF_BASE_ADDR, | |
978 | trans_pcie->fw_mon_phys >> 4); | |
979 | iwl_write_prph(trans, MON_BUFF_END_ADDR, | |
980 | (trans_pcie->fw_mon_phys + | |
981 | trans_pcie->fw_mon_size) >> 4); | |
982 | } | |
09e350f7 LK |
983 | } else if (trans->dbg_dest_tlv) { |
984 | iwl_pcie_apply_destination(trans); | |
c2d20201 EG |
985 | } |
986 | ||
e12ba844 | 987 | /* release CPU reset */ |
5dd9c68a | 988 | iwl_write32(trans, CSR_RESET, 0); |
e12ba844 | 989 | |
dcab8ecd EH |
990 | return 0; |
991 | } | |
189fa2fa | 992 | |
5dd9c68a EG |
993 | static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, |
994 | const struct fw_img *image) | |
dcab8ecd EH |
995 | { |
996 | int ret = 0; | |
997 | int first_ucode_section; | |
dcab8ecd EH |
998 | |
999 | IWL_DEBUG_FW(trans, "working with %s CPU\n", | |
1000 | image->is_dual_cpus ? "Dual" : "Single"); | |
1001 | ||
a2227ce2 EG |
1002 | if (trans->dbg_dest_tlv) |
1003 | iwl_pcie_apply_destination(trans); | |
1004 | ||
16bc119b EH |
1005 | /* TODO: remove in the next Si step */ |
1006 | ret = iwl_pcie_rsa_race_bug_wa(trans); | |
1007 | if (ret) | |
1008 | return ret; | |
1009 | ||
dcab8ecd EH |
1010 | /* configure the ucode to be ready to get the secured image */ |
1011 | /* release CPU reset */ | |
1012 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); | |
1013 | ||
1014 | /* load to FW the binary Secured sections of CPU1 */ | |
5dd9c68a EG |
1015 | ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, |
1016 | &first_ucode_section); | |
dcab8ecd EH |
1017 | if (ret) |
1018 | return ret; | |
1019 | ||
1020 | /* load to FW the binary sections of CPU2 */ | |
47dbab26 EG |
1021 | return iwl_pcie_load_cpu_sections_8000(trans, image, 2, |
1022 | &first_ucode_section); | |
cf614297 EG |
1023 | } |
1024 | ||
fa9f3281 | 1025 | static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) |
ae2c30bf | 1026 | { |
43e58856 | 1027 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3dc3374f EG |
1028 | bool hw_rfkill, was_hw_rfkill; |
1029 | ||
fa9f3281 EG |
1030 | lockdep_assert_held(&trans_pcie->mutex); |
1031 | ||
1032 | if (trans_pcie->is_down) | |
1033 | return; | |
1034 | ||
1035 | trans_pcie->is_down = true; | |
1036 | ||
3dc3374f | 1037 | was_hw_rfkill = iwl_is_rfkill_set(trans); |
ae2c30bf | 1038 | |
43e58856 | 1039 | /* tell the device to stop sending interrupts */ |
7b70bd63 | 1040 | spin_lock(&trans_pcie->irq_lock); |
ae2c30bf | 1041 | iwl_disable_interrupts(trans); |
7b70bd63 | 1042 | spin_unlock(&trans_pcie->irq_lock); |
ae2c30bf | 1043 | |
ab6cf8e8 | 1044 | /* device going down, Stop using ICT table */ |
990aa6d7 | 1045 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
1046 | |
1047 | /* | |
1048 | * If a HW restart happens during firmware loading, | |
1049 | * then the firmware loading might call this function | |
1050 | * and later it might be called again due to the | |
1051 | * restart. So don't process again if the device is | |
1052 | * already dead. | |
1053 | */ | |
31b8b343 | 1054 | if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
a6bd005f EG |
1055 | IWL_DEBUG_INFO(trans, |
1056 | "DEVICE_ENABLED bit was set and is now cleared\n"); | |
f02831be | 1057 | iwl_pcie_tx_stop(trans); |
9805c446 | 1058 | iwl_pcie_rx_stop(trans); |
6379103e | 1059 | |
ab6cf8e8 | 1060 | /* Power-down device's busmaster DMA clocks */ |
95411d04 | 1061 | if (!trans->cfg->apmg_not_supported) { |
1aa02b5a AA |
1062 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
1063 | APMG_CLK_VAL_DMA_CLK_RQT); | |
1064 | udelay(5); | |
1065 | } | |
ab6cf8e8 EG |
1066 | } |
1067 | ||
1068 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1069 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 1070 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1071 | |
1072 | /* Stop the device, and put it in low power state */ | |
b7aaeae4 | 1073 | iwl_pcie_apm_stop(trans, false); |
43e58856 | 1074 | |
03d6c3b0 EG |
1075 | /* stop and reset the on-board processor */ |
1076 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
1077 | udelay(20); | |
1078 | ||
1079 | /* | |
1080 | * Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1081 | * This is a bug in certain verions of the hardware. | |
1082 | * Certain devices also keep sending HW RF kill interrupt all | |
1083 | * the time, unless the interrupt is ACKed even if the interrupt | |
1084 | * should be masked. Re-ACK all the interrupts here. | |
43e58856 | 1085 | */ |
7b70bd63 | 1086 | spin_lock(&trans_pcie->irq_lock); |
43e58856 | 1087 | iwl_disable_interrupts(trans); |
7b70bd63 | 1088 | spin_unlock(&trans_pcie->irq_lock); |
43e58856 | 1089 | |
74fda971 | 1090 | /* clear all status bits */ |
eb7ff77e AN |
1091 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
1092 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
eb7ff77e AN |
1093 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
1094 | clear_bit(STATUS_RFKILL, &trans->status); | |
a4082843 AN |
1095 | |
1096 | /* | |
1097 | * Even if we stop the HW, we still want the RF kill | |
1098 | * interrupt | |
1099 | */ | |
1100 | iwl_enable_rfkill_int(trans); | |
1101 | ||
1102 | /* | |
1103 | * Check again since the RF kill state may have changed while | |
1104 | * all the interrupts were disabled, in this case we couldn't | |
1105 | * receive the RF kill interrupt and update the state in the | |
1106 | * op_mode. | |
3dc3374f EG |
1107 | * Don't call the op_mode if the rkfill state hasn't changed. |
1108 | * This allows the op_mode to call stop_device from the rfkill | |
1109 | * notification without endless recursion. Under very rare | |
1110 | * circumstances, we might have a small recursion if the rfkill | |
1111 | * state changed exactly now while we were called from stop_device. | |
1112 | * This is very unlikely but can happen and is supported. | |
a4082843 AN |
1113 | */ |
1114 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1115 | if (hw_rfkill) | |
eb7ff77e | 1116 | set_bit(STATUS_RFKILL, &trans->status); |
a4082843 | 1117 | else |
eb7ff77e | 1118 | clear_bit(STATUS_RFKILL, &trans->status); |
3dc3374f | 1119 | if (hw_rfkill != was_hw_rfkill) |
14cfca71 | 1120 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
655e5cf0 | 1121 | |
a6bd005f | 1122 | /* re-take ownership to prevent other users from stealing the device */ |
655e5cf0 | 1123 | iwl_pcie_prepare_card_hw(trans); |
14cfca71 JB |
1124 | } |
1125 | ||
2e5d4a8f HD |
1126 | static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) |
1127 | { | |
1128 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1129 | ||
1130 | if (trans_pcie->msix_enabled) { | |
1131 | int i; | |
1132 | ||
1133 | for (i = 0; i < trans_pcie->allocated_vector; i++) | |
1134 | synchronize_irq(trans_pcie->msix_entries[i].vector); | |
1135 | } else { | |
1136 | synchronize_irq(trans_pcie->pci_dev->irq); | |
1137 | } | |
1138 | } | |
1139 | ||
a6bd005f EG |
1140 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
1141 | const struct fw_img *fw, bool run_in_rfkill) | |
1142 | { | |
1143 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1144 | bool hw_rfkill; | |
1145 | int ret; | |
1146 | ||
1147 | /* This may fail if AMT took ownership of the device */ | |
1148 | if (iwl_pcie_prepare_card_hw(trans)) { | |
1149 | IWL_WARN(trans, "Exit HW not ready\n"); | |
1150 | ret = -EIO; | |
1151 | goto out; | |
1152 | } | |
1153 | ||
1154 | iwl_enable_rfkill_int(trans); | |
1155 | ||
1156 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
1157 | ||
1158 | /* | |
1159 | * We enabled the RF-Kill interrupt and the handler may very | |
1160 | * well be running. Disable the interrupts to make sure no other | |
1161 | * interrupt can be fired. | |
1162 | */ | |
1163 | iwl_disable_interrupts(trans); | |
1164 | ||
1165 | /* Make sure it finished running */ | |
2e5d4a8f | 1166 | iwl_pcie_synchronize_irqs(trans); |
a6bd005f EG |
1167 | |
1168 | mutex_lock(&trans_pcie->mutex); | |
1169 | ||
1170 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
1171 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1172 | if (hw_rfkill) | |
1173 | set_bit(STATUS_RFKILL, &trans->status); | |
1174 | else | |
1175 | clear_bit(STATUS_RFKILL, &trans->status); | |
1176 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); | |
1177 | if (hw_rfkill && !run_in_rfkill) { | |
1178 | ret = -ERFKILL; | |
1179 | goto out; | |
1180 | } | |
1181 | ||
1182 | /* Someone called stop_device, don't try to start_fw */ | |
1183 | if (trans_pcie->is_down) { | |
1184 | IWL_WARN(trans, | |
1185 | "Can't start_fw since the HW hasn't been started\n"); | |
20aa99bb | 1186 | ret = -EIO; |
a6bd005f EG |
1187 | goto out; |
1188 | } | |
1189 | ||
1190 | /* make sure rfkill handshake bits are cleared */ | |
1191 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1192 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
1193 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | |
1194 | ||
1195 | /* clear (again), then enable host interrupts */ | |
1196 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
1197 | ||
1198 | ret = iwl_pcie_nic_init(trans); | |
1199 | if (ret) { | |
1200 | IWL_ERR(trans, "Unable to init nic\n"); | |
1201 | goto out; | |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * Now, we load the firmware and don't want to be interrupted, even | |
1206 | * by the RF-Kill interrupt (hence mask all the interrupt besides the | |
1207 | * FH_TX interrupt which is needed to load the firmware). If the | |
1208 | * RF-Kill switch is toggled, we will find out after having loaded | |
1209 | * the firmware and return the proper value to the caller. | |
1210 | */ | |
1211 | iwl_enable_fw_load_int(trans); | |
1212 | ||
1213 | /* really make sure rfkill handshake bits are cleared */ | |
1214 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1215 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1216 | ||
1217 | /* Load the given image to the HW */ | |
1218 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) | |
1219 | ret = iwl_pcie_load_given_ucode_8000(trans, fw); | |
1220 | else | |
1221 | ret = iwl_pcie_load_given_ucode(trans, fw); | |
1222 | iwl_enable_interrupts(trans); | |
1223 | ||
1224 | /* re-check RF-Kill state since we may have missed the interrupt */ | |
1225 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1226 | if (hw_rfkill) | |
1227 | set_bit(STATUS_RFKILL, &trans->status); | |
1228 | else | |
1229 | clear_bit(STATUS_RFKILL, &trans->status); | |
1230 | ||
1231 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); | |
1232 | if (hw_rfkill && !run_in_rfkill) | |
1233 | ret = -ERFKILL; | |
1234 | ||
1235 | out: | |
1236 | mutex_unlock(&trans_pcie->mutex); | |
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) | |
1241 | { | |
1242 | iwl_pcie_reset_ict(trans); | |
1243 | iwl_pcie_tx_start(trans, scd_addr); | |
1244 | } | |
1245 | ||
fa9f3281 EG |
1246 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) |
1247 | { | |
1248 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1249 | ||
1250 | mutex_lock(&trans_pcie->mutex); | |
1251 | _iwl_trans_pcie_stop_device(trans, low_power); | |
1252 | mutex_unlock(&trans_pcie->mutex); | |
1253 | } | |
1254 | ||
14cfca71 JB |
1255 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) |
1256 | { | |
fa9f3281 EG |
1257 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1258 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1259 | ||
1260 | lockdep_assert_held(&trans_pcie->mutex); | |
1261 | ||
14cfca71 | 1262 | if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) |
fa9f3281 | 1263 | _iwl_trans_pcie_stop_device(trans, true); |
ab6cf8e8 EG |
1264 | } |
1265 | ||
23ae6128 MG |
1266 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, |
1267 | bool reset) | |
2dd4f9f7 | 1268 | { |
23ae6128 | 1269 | if (!reset) { |
6dfb36c8 EP |
1270 | /* Enable persistence mode to avoid reset */ |
1271 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
1272 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
1273 | } | |
1274 | ||
2dd4f9f7 | 1275 | iwl_disable_interrupts(trans); |
debff618 JB |
1276 | |
1277 | /* | |
1278 | * in testing mode, the host stays awake and the | |
1279 | * hardware won't be reset (not even partially) | |
1280 | */ | |
1281 | if (test) | |
1282 | return; | |
1283 | ||
ddaf5a5b JB |
1284 | iwl_pcie_disable_ict(trans); |
1285 | ||
2e5d4a8f | 1286 | iwl_pcie_synchronize_irqs(trans); |
33b56af1 | 1287 | |
2dd4f9f7 JB |
1288 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1289 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
1290 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1291 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1292 | ||
23ae6128 | 1293 | if (reset) { |
6dfb36c8 EP |
1294 | /* |
1295 | * reset TX queues -- some of their registers reset during S3 | |
1296 | * so if we don't reset everything here the D3 image would try | |
1297 | * to execute some invalid memory upon resume | |
1298 | */ | |
1299 | iwl_trans_pcie_tx_reset(trans); | |
1300 | } | |
ddaf5a5b JB |
1301 | |
1302 | iwl_pcie_set_pwr(trans, true); | |
1303 | } | |
1304 | ||
1305 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 | 1306 | enum iwl_d3_status *status, |
23ae6128 | 1307 | bool test, bool reset) |
ddaf5a5b JB |
1308 | { |
1309 | u32 val; | |
1310 | int ret; | |
1311 | ||
debff618 JB |
1312 | if (test) { |
1313 | iwl_enable_interrupts(trans); | |
1314 | *status = IWL_D3_STATUS_ALIVE; | |
1315 | return 0; | |
1316 | } | |
1317 | ||
ddaf5a5b JB |
1318 | /* |
1319 | * Also enables interrupts - none will happen as the device doesn't | |
1320 | * know we're waking it up, only when the opmode actually tells it | |
1321 | * after this call. | |
1322 | */ | |
1323 | iwl_pcie_reset_ict(trans); | |
18dcb9a9 | 1324 | iwl_enable_interrupts(trans); |
ddaf5a5b JB |
1325 | |
1326 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1327 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1328 | ||
01e58a28 EG |
1329 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1330 | udelay(2); | |
1331 | ||
ddaf5a5b JB |
1332 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, |
1333 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1334 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1335 | 25000); | |
7f2ac8fb | 1336 | if (ret < 0) { |
ddaf5a5b JB |
1337 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); |
1338 | return ret; | |
1339 | } | |
1340 | ||
a3ead656 EG |
1341 | iwl_pcie_set_pwr(trans, false); |
1342 | ||
23ae6128 | 1343 | if (!reset) { |
6dfb36c8 EP |
1344 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1345 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1346 | } else { | |
1347 | iwl_trans_pcie_tx_reset(trans); | |
ddaf5a5b | 1348 | |
6dfb36c8 EP |
1349 | ret = iwl_pcie_rx_init(trans); |
1350 | if (ret) { | |
1351 | IWL_ERR(trans, | |
1352 | "Failed to resume the device (RX reset)\n"); | |
1353 | return ret; | |
1354 | } | |
ddaf5a5b JB |
1355 | } |
1356 | ||
a3ead656 EG |
1357 | val = iwl_read32(trans, CSR_RESET); |
1358 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) | |
1359 | *status = IWL_D3_STATUS_RESET; | |
1360 | else | |
1361 | *status = IWL_D3_STATUS_ALIVE; | |
1362 | ||
ddaf5a5b | 1363 | return 0; |
2dd4f9f7 JB |
1364 | } |
1365 | ||
2e5d4a8f HD |
1366 | struct iwl_causes_list { |
1367 | u32 cause_num; | |
1368 | u32 mask_reg; | |
1369 | u8 addr; | |
1370 | }; | |
1371 | ||
1372 | static struct iwl_causes_list causes_list[] = { | |
1373 | {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, | |
1374 | {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, | |
1375 | {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, | |
1376 | {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, | |
1377 | {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, | |
1378 | {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, | |
1379 | {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, | |
1380 | {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, | |
1381 | {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, | |
1382 | {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, | |
1383 | {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, | |
1384 | {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, | |
1385 | {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, | |
1386 | {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, | |
1387 | }; | |
1388 | ||
1389 | static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) | |
1390 | { | |
1391 | u32 val, max_rx_vector, i; | |
1392 | struct iwl_trans *trans = trans_pcie->trans; | |
1393 | ||
1394 | max_rx_vector = trans_pcie->allocated_vector - 1; | |
1395 | ||
1396 | if (!trans_pcie->msix_enabled) | |
1397 | return; | |
1398 | ||
1399 | iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); | |
1400 | ||
1401 | /* | |
1402 | * Each cause from the list above and the RX causes is represented as | |
1403 | * a byte in the IVAR table. We access the first (N - 1) bytes and map | |
1404 | * them to the (N - 1) vectors so these vectors will be used as rx | |
1405 | * vectors. Then access all non rx causes and map them to the | |
1406 | * default queue (N'th queue). | |
1407 | */ | |
1408 | for (i = 0; i < max_rx_vector; i++) { | |
1409 | iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i)); | |
1410 | iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD, | |
1411 | BIT(MSIX_FH_INT_CAUSES_Q(i))); | |
1412 | } | |
1413 | ||
1414 | for (i = 0; i < ARRAY_SIZE(causes_list); i++) { | |
1415 | val = trans_pcie->default_irq_num | | |
1416 | MSIX_NON_AUTO_CLEAR_CAUSE; | |
1417 | iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); | |
1418 | iwl_clear_bit(trans, causes_list[i].mask_reg, | |
1419 | causes_list[i].cause_num); | |
1420 | } | |
1421 | trans_pcie->fh_init_mask = | |
1422 | ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); | |
1423 | trans_pcie->fh_mask = trans_pcie->fh_init_mask; | |
1424 | trans_pcie->hw_init_mask = | |
1425 | ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); | |
1426 | trans_pcie->hw_mask = trans_pcie->hw_init_mask; | |
1427 | } | |
1428 | ||
1429 | static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, | |
1430 | struct iwl_trans *trans) | |
1431 | { | |
1432 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1433 | u16 pci_cmd; | |
1434 | int max_vector; | |
1435 | int ret, i; | |
1436 | ||
1437 | if (trans->cfg->mq_rx_supported) { | |
1438 | max_vector = min_t(u32, (num_possible_cpus() + 1), | |
1439 | IWL_MAX_RX_HW_QUEUES); | |
1440 | for (i = 0; i < max_vector; i++) | |
1441 | trans_pcie->msix_entries[i].entry = i; | |
1442 | ||
1443 | ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries, | |
1444 | MSIX_MIN_INTERRUPT_VECTORS, | |
1445 | max_vector); | |
1446 | if (ret > 1) { | |
1447 | IWL_DEBUG_INFO(trans, | |
1448 | "Enable MSI-X allocate %d interrupt vector\n", | |
1449 | ret); | |
1450 | trans_pcie->allocated_vector = ret; | |
1451 | trans_pcie->default_irq_num = | |
1452 | trans_pcie->allocated_vector - 1; | |
1453 | trans_pcie->trans->num_rx_queues = | |
1454 | trans_pcie->allocated_vector - 1; | |
1455 | trans_pcie->msix_enabled = true; | |
1456 | ||
1457 | return; | |
1458 | } | |
1459 | IWL_DEBUG_INFO(trans, | |
1460 | "ret = %d %s move to msi mode\n", ret, | |
1461 | (ret == 1) ? | |
1462 | "can't allocate more than 1 interrupt vector" : | |
1463 | "failed to enable msi-x mode"); | |
1464 | pci_disable_msix(pdev); | |
1465 | } | |
1466 | ||
1467 | ret = pci_enable_msi(pdev); | |
1468 | if (ret) { | |
6ed5e4d6 | 1469 | dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); |
2e5d4a8f HD |
1470 | /* enable rfkill interrupt: hw bug w/a */ |
1471 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1472 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1473 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1474 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1475 | } | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, | |
1480 | struct iwl_trans_pcie *trans_pcie) | |
1481 | { | |
1482 | int i, last_vector; | |
1483 | ||
1484 | last_vector = trans_pcie->trans->num_rx_queues; | |
1485 | ||
1486 | for (i = 0; i < trans_pcie->allocated_vector; i++) { | |
1487 | int ret; | |
1488 | ||
1489 | ret = request_threaded_irq(trans_pcie->msix_entries[i].vector, | |
1490 | iwl_pcie_msix_isr, | |
1491 | (i == last_vector) ? | |
1492 | iwl_pcie_irq_msix_handler : | |
1493 | iwl_pcie_irq_rx_msix_handler, | |
1494 | IRQF_SHARED, | |
1495 | DRV_NAME, | |
1496 | &trans_pcie->msix_entries[i]); | |
1497 | if (ret) { | |
1498 | int j; | |
1499 | ||
1500 | IWL_ERR(trans_pcie->trans, | |
1501 | "Error allocating IRQ %d\n", i); | |
1502 | for (j = 0; j < i; j++) | |
1503 | free_irq(trans_pcie->msix_entries[i].vector, | |
1504 | &trans_pcie->msix_entries[i]); | |
1505 | pci_disable_msix(pdev); | |
1506 | return ret; | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
fa9f3281 | 1513 | static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) |
e6bb4c9c | 1514 | { |
fa9f3281 | 1515 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c9eec95c | 1516 | bool hw_rfkill; |
a8b691e6 | 1517 | int err; |
e6bb4c9c | 1518 | |
fa9f3281 EG |
1519 | lockdep_assert_held(&trans_pcie->mutex); |
1520 | ||
7afe3705 | 1521 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 1522 | if (err) { |
d6f1c316 | 1523 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 1524 | return err; |
ebb7678d | 1525 | } |
a6c684ee | 1526 | |
2997494f | 1527 | /* Reset the entire device */ |
ce836c76 | 1528 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
2997494f EG |
1529 | |
1530 | usleep_range(10, 15); | |
1531 | ||
7afe3705 | 1532 | iwl_pcie_apm_init(trans); |
a6c684ee | 1533 | |
2e5d4a8f | 1534 | iwl_pcie_init_msix(trans_pcie); |
226c02ca EG |
1535 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1536 | iwl_enable_rfkill_int(trans); | |
1537 | ||
fa9f3281 EG |
1538 | /* Set is_down to false here so that...*/ |
1539 | trans_pcie->is_down = false; | |
1540 | ||
8d425517 | 1541 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 1542 | if (hw_rfkill) |
eb7ff77e | 1543 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 1544 | else |
eb7ff77e | 1545 | clear_bit(STATUS_RFKILL, &trans->status); |
fa9f3281 | 1546 | /* ... rfkill can call stop_device and set it false if needed */ |
14cfca71 | 1547 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
d48e2074 | 1548 | |
4cbb8e50 LC |
1549 | /* Make sure we sync here, because we'll need full access later */ |
1550 | if (low_power) | |
1551 | pm_runtime_resume(trans->dev); | |
1552 | ||
a8b691e6 | 1553 | return 0; |
e6bb4c9c EG |
1554 | } |
1555 | ||
fa9f3281 EG |
1556 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) |
1557 | { | |
1558 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1559 | int ret; | |
1560 | ||
1561 | mutex_lock(&trans_pcie->mutex); | |
1562 | ret = _iwl_trans_pcie_start_hw(trans, low_power); | |
1563 | mutex_unlock(&trans_pcie->mutex); | |
1564 | ||
1565 | return ret; | |
1566 | } | |
1567 | ||
a4082843 | 1568 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 1569 | { |
20d3b647 | 1570 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1571 | |
fa9f3281 EG |
1572 | mutex_lock(&trans_pcie->mutex); |
1573 | ||
a4082843 | 1574 | /* disable interrupts - don't enable HW RF kill interrupt */ |
7b70bd63 | 1575 | spin_lock(&trans_pcie->irq_lock); |
ee7d737c | 1576 | iwl_disable_interrupts(trans); |
7b70bd63 | 1577 | spin_unlock(&trans_pcie->irq_lock); |
ee7d737c | 1578 | |
b7aaeae4 | 1579 | iwl_pcie_apm_stop(trans, true); |
cc56feb2 | 1580 | |
7b70bd63 | 1581 | spin_lock(&trans_pcie->irq_lock); |
218733cf | 1582 | iwl_disable_interrupts(trans); |
7b70bd63 | 1583 | spin_unlock(&trans_pcie->irq_lock); |
1df06bdc | 1584 | |
8d96bb61 | 1585 | iwl_pcie_disable_ict(trans); |
33b56af1 | 1586 | |
fa9f3281 | 1587 | mutex_unlock(&trans_pcie->mutex); |
33b56af1 | 1588 | |
2e5d4a8f | 1589 | iwl_pcie_synchronize_irqs(trans); |
cc56feb2 EG |
1590 | } |
1591 | ||
03905495 EG |
1592 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1593 | { | |
05f5b97e | 1594 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1595 | } |
1596 | ||
1597 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1598 | { | |
05f5b97e | 1599 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1600 | } |
1601 | ||
1602 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1603 | { | |
05f5b97e | 1604 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1605 | } |
1606 | ||
6a06b6c1 EG |
1607 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
1608 | { | |
f9477c17 AP |
1609 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
1610 | ((reg & 0x000FFFFF) | (3 << 24))); | |
6a06b6c1 EG |
1611 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
1612 | } | |
1613 | ||
1614 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
1615 | u32 val) | |
1616 | { | |
1617 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
f9477c17 | 1618 | ((addr & 0x000FFFFF) | (3 << 24))); |
6a06b6c1 EG |
1619 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
1620 | } | |
1621 | ||
c6f600fc | 1622 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1623 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1624 | { |
1625 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1626 | ||
1627 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 1628 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
4cf677fd | 1629 | trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; |
d663ee73 JB |
1630 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1631 | trans_pcie->n_no_reclaim_cmds = 0; | |
1632 | else | |
1633 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1634 | if (trans_pcie->n_no_reclaim_cmds) | |
1635 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1636 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 1637 | |
6c4fbcbc EG |
1638 | trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; |
1639 | trans_pcie->rx_page_order = | |
1640 | iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); | |
7c5ba4a8 | 1641 | |
ab02165c | 1642 | trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header; |
046db346 | 1643 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
3a736bcb | 1644 | trans_pcie->scd_set_active = trans_cfg->scd_set_active; |
41837ca9 | 1645 | trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; |
f14d6b39 | 1646 | |
39bdb17e SD |
1647 | trans->command_groups = trans_cfg->command_groups; |
1648 | trans->command_groups_size = trans_cfg->command_groups_size; | |
1649 | ||
f14d6b39 JB |
1650 | /* Initialize NAPI here - it should be before registering to mac80211 |
1651 | * in the opmode but after the HW struct is allocated. | |
1652 | * As this function may be called again in some corner cases don't | |
1653 | * do anything if NAPI was already initialized. | |
1654 | */ | |
bce97731 | 1655 | if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) |
f14d6b39 | 1656 | init_dummy_netdev(&trans_pcie->napi_dev); |
c6f600fc MV |
1657 | } |
1658 | ||
d1ff5253 | 1659 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1660 | { |
20d3b647 | 1661 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
6eb5e529 | 1662 | int i; |
a42a1844 | 1663 | |
2e5d4a8f | 1664 | iwl_pcie_synchronize_irqs(trans); |
0aa86df6 | 1665 | |
f02831be | 1666 | iwl_pcie_tx_free(trans); |
9805c446 | 1667 | iwl_pcie_rx_free(trans); |
6379103e | 1668 | |
2e5d4a8f HD |
1669 | if (trans_pcie->msix_enabled) { |
1670 | for (i = 0; i < trans_pcie->allocated_vector; i++) | |
1671 | free_irq(trans_pcie->msix_entries[i].vector, | |
1672 | &trans_pcie->msix_entries[i]); | |
1673 | ||
1674 | pci_disable_msix(trans_pcie->pci_dev); | |
1675 | trans_pcie->msix_enabled = false; | |
1676 | } else { | |
1677 | free_irq(trans_pcie->pci_dev->irq, trans); | |
a42a1844 | 1678 | |
2e5d4a8f HD |
1679 | iwl_pcie_free_ict(trans); |
1680 | ||
1681 | pci_disable_msi(trans_pcie->pci_dev); | |
1682 | } | |
05f5b97e | 1683 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
1684 | pci_release_regions(trans_pcie->pci_dev); |
1685 | pci_disable_device(trans_pcie->pci_dev); | |
1686 | ||
c2d20201 EG |
1687 | iwl_pcie_free_fw_monitor(trans); |
1688 | ||
6eb5e529 EG |
1689 | for_each_possible_cpu(i) { |
1690 | struct iwl_tso_hdr_page *p = | |
1691 | per_cpu_ptr(trans_pcie->tso_hdr_page, i); | |
1692 | ||
1693 | if (p->page) | |
1694 | __free_page(p->page); | |
1695 | } | |
1696 | ||
1697 | free_percpu(trans_pcie->tso_hdr_page); | |
a2a57a35 | 1698 | mutex_destroy(&trans_pcie->mutex); |
7b501d10 | 1699 | iwl_trans_free(trans); |
34c1b7ba EG |
1700 | } |
1701 | ||
47107e84 DF |
1702 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1703 | { | |
47107e84 | 1704 | if (state) |
eb7ff77e | 1705 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 1706 | else |
eb7ff77e | 1707 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
1708 | } |
1709 | ||
23ba9340 EG |
1710 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, |
1711 | unsigned long *flags) | |
7a65d170 EG |
1712 | { |
1713 | int ret; | |
cfb4e624 JB |
1714 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1715 | ||
1716 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 | 1717 | |
fc8a350d | 1718 | if (trans_pcie->cmd_hold_nic_awake) |
b9439491 EG |
1719 | goto out; |
1720 | ||
7a65d170 | 1721 | /* this bit wakes up the NIC */ |
e139dc4a LE |
1722 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1723 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
01e58a28 EG |
1724 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1725 | udelay(2); | |
7a65d170 EG |
1726 | |
1727 | /* | |
1728 | * These bits say the device is running, and should keep running for | |
1729 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
1730 | * but they do not indicate that embedded SRAM is restored yet; | |
1731 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
1732 | * to/from host DRAM when sleeping/waking for power-saving. | |
1733 | * Each direction takes approximately 1/4 millisecond; with this | |
1734 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
1735 | * series of register accesses are expected (e.g. reading Event Log), | |
1736 | * to keep device from sleeping. | |
1737 | * | |
1738 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
1739 | * SRAM is okay/restored. We don't check that here because this call | |
1740 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
1741 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
1742 | * | |
1743 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
1744 | * and do not save/restore SRAM when power cycling. | |
1745 | */ | |
1746 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1747 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1748 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1749 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
1750 | if (unlikely(ret < 0)) { | |
1751 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
23ba9340 EG |
1752 | WARN_ONCE(1, |
1753 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
1754 | iwl_read32(trans, CSR_GP_CNTRL)); | |
1755 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); | |
1756 | return false; | |
7a65d170 EG |
1757 | } |
1758 | ||
b9439491 | 1759 | out: |
e56b04ef LE |
1760 | /* |
1761 | * Fool sparse by faking we release the lock - sparse will | |
1762 | * track nic_access anyway. | |
1763 | */ | |
cfb4e624 | 1764 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
1765 | return true; |
1766 | } | |
1767 | ||
e56b04ef LE |
1768 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
1769 | unsigned long *flags) | |
7a65d170 | 1770 | { |
cfb4e624 | 1771 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 1772 | |
cfb4e624 | 1773 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
1774 | |
1775 | /* | |
1776 | * Fool sparse by faking we acquiring the lock - sparse will | |
1777 | * track nic_access anyway. | |
1778 | */ | |
cfb4e624 | 1779 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 1780 | |
fc8a350d | 1781 | if (trans_pcie->cmd_hold_nic_awake) |
b9439491 EG |
1782 | goto out; |
1783 | ||
e139dc4a LE |
1784 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
1785 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
1786 | /* |
1787 | * Above we read the CSR_GP_CNTRL register, which will flush | |
1788 | * any previous writes, but we need the write that clears the | |
1789 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
1790 | * scheduled on different CPUs (after we drop reg_lock). | |
1791 | */ | |
1792 | mmiowb(); | |
b9439491 | 1793 | out: |
cfb4e624 | 1794 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
1795 | } |
1796 | ||
4fd442db EG |
1797 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
1798 | void *buf, int dwords) | |
1799 | { | |
1800 | unsigned long flags; | |
1801 | int offs, ret = 0; | |
1802 | u32 *vals = buf; | |
1803 | ||
23ba9340 | 1804 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
4fd442db EG |
1805 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
1806 | for (offs = 0; offs < dwords; offs++) | |
1807 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 1808 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1809 | } else { |
1810 | ret = -EBUSY; | |
1811 | } | |
4fd442db EG |
1812 | return ret; |
1813 | } | |
1814 | ||
1815 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1816 | const void *buf, int dwords) |
4fd442db EG |
1817 | { |
1818 | unsigned long flags; | |
1819 | int offs, ret = 0; | |
bf0fd5da | 1820 | const u32 *vals = buf; |
4fd442db | 1821 | |
23ba9340 | 1822 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
4fd442db EG |
1823 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
1824 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
1825 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
1826 | vals ? vals[offs] : 0); | |
e56b04ef | 1827 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1828 | } else { |
1829 | ret = -EBUSY; | |
1830 | } | |
4fd442db EG |
1831 | return ret; |
1832 | } | |
7a65d170 | 1833 | |
e0b8d405 EG |
1834 | static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, |
1835 | unsigned long txqs, | |
1836 | bool freeze) | |
1837 | { | |
1838 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1839 | int queue; | |
1840 | ||
1841 | for_each_set_bit(queue, &txqs, BITS_PER_LONG) { | |
1842 | struct iwl_txq *txq = &trans_pcie->txq[queue]; | |
1843 | unsigned long now; | |
1844 | ||
1845 | spin_lock_bh(&txq->lock); | |
1846 | ||
1847 | now = jiffies; | |
1848 | ||
1849 | if (txq->frozen == freeze) | |
1850 | goto next_queue; | |
1851 | ||
1852 | IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", | |
1853 | freeze ? "Freezing" : "Waking", queue); | |
1854 | ||
1855 | txq->frozen = freeze; | |
1856 | ||
1857 | if (txq->q.read_ptr == txq->q.write_ptr) | |
1858 | goto next_queue; | |
1859 | ||
1860 | if (freeze) { | |
1861 | if (unlikely(time_after(now, | |
1862 | txq->stuck_timer.expires))) { | |
1863 | /* | |
1864 | * The timer should have fired, maybe it is | |
1865 | * spinning right now on the lock. | |
1866 | */ | |
1867 | goto next_queue; | |
1868 | } | |
1869 | /* remember how long until the timer fires */ | |
1870 | txq->frozen_expiry_remainder = | |
1871 | txq->stuck_timer.expires - now; | |
1872 | del_timer(&txq->stuck_timer); | |
1873 | goto next_queue; | |
1874 | } | |
1875 | ||
1876 | /* | |
1877 | * Wake a non-empty queue -> arm timer with the | |
1878 | * remainder before it froze | |
1879 | */ | |
1880 | mod_timer(&txq->stuck_timer, | |
1881 | now + txq->frozen_expiry_remainder); | |
1882 | ||
1883 | next_queue: | |
1884 | spin_unlock_bh(&txq->lock); | |
1885 | } | |
1886 | } | |
1887 | ||
0cd58eaa EG |
1888 | static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) |
1889 | { | |
1890 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1891 | int i; | |
1892 | ||
1893 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
1894 | struct iwl_txq *txq = &trans_pcie->txq[i]; | |
1895 | ||
1896 | if (i == trans_pcie->cmd_queue) | |
1897 | continue; | |
1898 | ||
1899 | spin_lock_bh(&txq->lock); | |
1900 | ||
1901 | if (!block && !(WARN_ON_ONCE(!txq->block))) { | |
1902 | txq->block--; | |
1903 | if (!txq->block) { | |
1904 | iwl_write32(trans, HBUS_TARG_WRPTR, | |
1905 | txq->q.write_ptr | (i << 8)); | |
1906 | } | |
1907 | } else if (block) { | |
1908 | txq->block++; | |
1909 | } | |
1910 | ||
1911 | spin_unlock_bh(&txq->lock); | |
1912 | } | |
1913 | } | |
1914 | ||
5f178cd2 EG |
1915 | #define IWL_FLUSH_WAIT_MS 2000 |
1916 | ||
3cafdbe6 | 1917 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) |
5f178cd2 | 1918 | { |
8ad71bef | 1919 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1920 | struct iwl_txq *txq; |
5f178cd2 EG |
1921 | struct iwl_queue *q; |
1922 | int cnt; | |
1923 | unsigned long now = jiffies; | |
1c3fea82 EG |
1924 | u32 scd_sram_addr; |
1925 | u8 buf[16]; | |
5f178cd2 EG |
1926 | int ret = 0; |
1927 | ||
1928 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1929 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
fa1a91fd EG |
1930 | u8 wr_ptr; |
1931 | ||
9ba1947a | 1932 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1933 | continue; |
3cafdbe6 EG |
1934 | if (!test_bit(cnt, trans_pcie->queue_used)) |
1935 | continue; | |
1936 | if (!(BIT(cnt) & txq_bm)) | |
1937 | continue; | |
748fa67c EG |
1938 | |
1939 | IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); | |
8ad71bef | 1940 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 | 1941 | q = &txq->q; |
fa1a91fd EG |
1942 | wr_ptr = ACCESS_ONCE(q->write_ptr); |
1943 | ||
1944 | while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && | |
1945 | !time_after(jiffies, | |
1946 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { | |
1947 | u8 write_ptr = ACCESS_ONCE(q->write_ptr); | |
1948 | ||
1949 | if (WARN_ONCE(wr_ptr != write_ptr, | |
1950 | "WR pointer moved while flushing %d -> %d\n", | |
1951 | wr_ptr, write_ptr)) | |
1952 | return -ETIMEDOUT; | |
5f178cd2 | 1953 | msleep(1); |
fa1a91fd | 1954 | } |
5f178cd2 EG |
1955 | |
1956 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
1957 | IWL_ERR(trans, |
1958 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
1959 | ret = -ETIMEDOUT; |
1960 | break; | |
1961 | } | |
748fa67c | 1962 | IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); |
5f178cd2 | 1963 | } |
1c3fea82 EG |
1964 | |
1965 | if (!ret) | |
1966 | return 0; | |
1967 | ||
1968 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
1969 | txq->q.read_ptr, txq->q.write_ptr); | |
1970 | ||
1971 | scd_sram_addr = trans_pcie->scd_base_addr + | |
1972 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
1973 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
1974 | ||
1975 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
1976 | ||
1977 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
1978 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
1979 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
1980 | ||
1981 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1982 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
1983 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
1984 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
1985 | u32 tbl_dw = | |
1986 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
1987 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
1988 | ||
1989 | if (cnt & 0x1) | |
1990 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
1991 | else | |
1992 | tbl_dw = tbl_dw & 0x0000FFFF; | |
1993 | ||
1994 | IWL_ERR(trans, | |
1995 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
1996 | cnt, active ? "" : "in", fifo, tbl_dw, | |
83f32a4b JB |
1997 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & |
1998 | (TFD_QUEUE_SIZE_MAX - 1), | |
1c3fea82 EG |
1999 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); |
2000 | } | |
2001 | ||
5f178cd2 EG |
2002 | return ret; |
2003 | } | |
2004 | ||
e139dc4a LE |
2005 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
2006 | u32 mask, u32 value) | |
2007 | { | |
e56b04ef | 2008 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
2009 | unsigned long flags; |
2010 | ||
e56b04ef | 2011 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 2012 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 2013 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
2014 | } |
2015 | ||
7616f334 EP |
2016 | void iwl_trans_pcie_ref(struct iwl_trans *trans) |
2017 | { | |
2018 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
7616f334 EP |
2019 | |
2020 | if (iwlwifi_mod_params.d0i3_disable) | |
2021 | return; | |
2022 | ||
b3ff1270 | 2023 | pm_runtime_get(&trans_pcie->pci_dev->dev); |
5d93f3a2 LC |
2024 | |
2025 | #ifdef CONFIG_PM | |
2026 | IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", | |
2027 | atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); | |
2028 | #endif /* CONFIG_PM */ | |
7616f334 EP |
2029 | } |
2030 | ||
2031 | void iwl_trans_pcie_unref(struct iwl_trans *trans) | |
2032 | { | |
2033 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
7616f334 EP |
2034 | |
2035 | if (iwlwifi_mod_params.d0i3_disable) | |
2036 | return; | |
2037 | ||
b3ff1270 LC |
2038 | pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); |
2039 | pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); | |
b3ff1270 | 2040 | |
5d93f3a2 LC |
2041 | #ifdef CONFIG_PM |
2042 | IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", | |
2043 | atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); | |
2044 | #endif /* CONFIG_PM */ | |
7616f334 EP |
2045 | } |
2046 | ||
ff620849 EG |
2047 | static const char *get_csr_string(int cmd) |
2048 | { | |
d9fb6465 | 2049 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
2050 | switch (cmd) { |
2051 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
2052 | IWL_CMD(CSR_INT_COALESCING); | |
2053 | IWL_CMD(CSR_INT); | |
2054 | IWL_CMD(CSR_INT_MASK); | |
2055 | IWL_CMD(CSR_FH_INT_STATUS); | |
2056 | IWL_CMD(CSR_GPIO_IN); | |
2057 | IWL_CMD(CSR_RESET); | |
2058 | IWL_CMD(CSR_GP_CNTRL); | |
2059 | IWL_CMD(CSR_HW_REV); | |
2060 | IWL_CMD(CSR_EEPROM_REG); | |
2061 | IWL_CMD(CSR_EEPROM_GP); | |
2062 | IWL_CMD(CSR_OTP_GP_REG); | |
2063 | IWL_CMD(CSR_GIO_REG); | |
2064 | IWL_CMD(CSR_GP_UCODE_REG); | |
2065 | IWL_CMD(CSR_GP_DRIVER_REG); | |
2066 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
2067 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
2068 | IWL_CMD(CSR_LED_REG); | |
2069 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
2070 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
2071 | IWL_CMD(CSR_ANA_PLL_CFG); | |
2072 | IWL_CMD(CSR_HW_REV_WA_REG); | |
a812cba9 | 2073 | IWL_CMD(CSR_MONITOR_STATUS_REG); |
ff620849 EG |
2074 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
2075 | default: | |
2076 | return "UNKNOWN"; | |
2077 | } | |
d9fb6465 | 2078 | #undef IWL_CMD |
ff620849 EG |
2079 | } |
2080 | ||
990aa6d7 | 2081 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
2082 | { |
2083 | int i; | |
2084 | static const u32 csr_tbl[] = { | |
2085 | CSR_HW_IF_CONFIG_REG, | |
2086 | CSR_INT_COALESCING, | |
2087 | CSR_INT, | |
2088 | CSR_INT_MASK, | |
2089 | CSR_FH_INT_STATUS, | |
2090 | CSR_GPIO_IN, | |
2091 | CSR_RESET, | |
2092 | CSR_GP_CNTRL, | |
2093 | CSR_HW_REV, | |
2094 | CSR_EEPROM_REG, | |
2095 | CSR_EEPROM_GP, | |
2096 | CSR_OTP_GP_REG, | |
2097 | CSR_GIO_REG, | |
2098 | CSR_GP_UCODE_REG, | |
2099 | CSR_GP_DRIVER_REG, | |
2100 | CSR_UCODE_DRV_GP1, | |
2101 | CSR_UCODE_DRV_GP2, | |
2102 | CSR_LED_REG, | |
2103 | CSR_DRAM_INT_TBL_REG, | |
2104 | CSR_GIO_CHICKEN_BITS, | |
2105 | CSR_ANA_PLL_CFG, | |
a812cba9 | 2106 | CSR_MONITOR_STATUS_REG, |
ff620849 EG |
2107 | CSR_HW_REV_WA_REG, |
2108 | CSR_DBG_HPET_MEM_REG | |
2109 | }; | |
2110 | IWL_ERR(trans, "CSR values:\n"); | |
2111 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
2112 | "CSR_INT_PERIODIC_REG)\n"); | |
2113 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
2114 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
2115 | get_csr_string(csr_tbl[i]), | |
1042db2a | 2116 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
2117 | } |
2118 | } | |
2119 | ||
87e5666c EG |
2120 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
2121 | /* create and remove of files */ | |
2122 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 2123 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 2124 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 2125 | goto err; \ |
87e5666c EG |
2126 | } while (0) |
2127 | ||
2128 | /* file operation */ | |
87e5666c | 2129 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
2130 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2131 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 2132 | .open = simple_open, \ |
87e5666c EG |
2133 | .llseek = generic_file_llseek, \ |
2134 | }; | |
2135 | ||
16db88ba | 2136 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
2137 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2138 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 2139 | .open = simple_open, \ |
16db88ba EG |
2140 | .llseek = generic_file_llseek, \ |
2141 | }; | |
2142 | ||
87e5666c | 2143 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
2144 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
2145 | .write = iwl_dbgfs_##name##_write, \ | |
2146 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 2147 | .open = simple_open, \ |
87e5666c EG |
2148 | .llseek = generic_file_llseek, \ |
2149 | }; | |
2150 | ||
87e5666c | 2151 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
2152 | char __user *user_buf, |
2153 | size_t count, loff_t *ppos) | |
8ad71bef | 2154 | { |
5a878bf6 | 2155 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 2156 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 2157 | struct iwl_txq *txq; |
87e5666c EG |
2158 | struct iwl_queue *q; |
2159 | char *buf; | |
2160 | int pos = 0; | |
2161 | int cnt; | |
2162 | int ret; | |
1745e440 WYG |
2163 | size_t bufsz; |
2164 | ||
e0b8d405 | 2165 | bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; |
87e5666c | 2166 | |
f9e75447 | 2167 | if (!trans_pcie->txq) |
87e5666c | 2168 | return -EAGAIN; |
f9e75447 | 2169 | |
87e5666c EG |
2170 | buf = kzalloc(bufsz, GFP_KERNEL); |
2171 | if (!buf) | |
2172 | return -ENOMEM; | |
2173 | ||
035f7ff2 | 2174 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 2175 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
2176 | q = &txq->q; |
2177 | pos += scnprintf(buf + pos, bufsz - pos, | |
e0b8d405 | 2178 | "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", |
87e5666c | 2179 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa | 2180 | !!test_bit(cnt, trans_pcie->queue_used), |
f40faf62 | 2181 | !!test_bit(cnt, trans_pcie->queue_stopped), |
e0b8d405 | 2182 | txq->need_update, txq->frozen, |
f40faf62 | 2183 | (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); |
87e5666c EG |
2184 | } |
2185 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2186 | kfree(buf); | |
2187 | return ret; | |
2188 | } | |
2189 | ||
2190 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
2191 | char __user *user_buf, |
2192 | size_t count, loff_t *ppos) | |
2193 | { | |
5a878bf6 | 2194 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 2195 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
78485054 SS |
2196 | char *buf; |
2197 | int pos = 0, i, ret; | |
2198 | size_t bufsz = sizeof(buf); | |
2199 | ||
2200 | bufsz = sizeof(char) * 121 * trans->num_rx_queues; | |
2201 | ||
2202 | if (!trans_pcie->rxq) | |
2203 | return -EAGAIN; | |
2204 | ||
2205 | buf = kzalloc(bufsz, GFP_KERNEL); | |
2206 | if (!buf) | |
2207 | return -ENOMEM; | |
2208 | ||
2209 | for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { | |
2210 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
2211 | ||
2212 | pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", | |
2213 | i); | |
2214 | pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", | |
2215 | rxq->read); | |
2216 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", | |
2217 | rxq->write); | |
2218 | pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", | |
2219 | rxq->write_actual); | |
2220 | pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", | |
2221 | rxq->need_update); | |
2222 | pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", | |
2223 | rxq->free_count); | |
2224 | if (rxq->rb_stts) { | |
2225 | pos += scnprintf(buf + pos, bufsz - pos, | |
2226 | "\tclosed_rb_num: %u\n", | |
2227 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & | |
2228 | 0x0FFF); | |
2229 | } else { | |
2230 | pos += scnprintf(buf + pos, bufsz - pos, | |
2231 | "\tclosed_rb_num: Not Allocated\n"); | |
60c0a88f | 2232 | } |
87e5666c | 2233 | } |
78485054 SS |
2234 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
2235 | kfree(buf); | |
2236 | ||
2237 | return ret; | |
87e5666c EG |
2238 | } |
2239 | ||
1f7b6172 EG |
2240 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
2241 | char __user *user_buf, | |
20d3b647 JB |
2242 | size_t count, loff_t *ppos) |
2243 | { | |
1f7b6172 | 2244 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 2245 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
2246 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
2247 | ||
2248 | int pos = 0; | |
2249 | char *buf; | |
2250 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
2251 | ssize_t ret; | |
2252 | ||
2253 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 2254 | if (!buf) |
1f7b6172 | 2255 | return -ENOMEM; |
1f7b6172 EG |
2256 | |
2257 | pos += scnprintf(buf + pos, bufsz - pos, | |
2258 | "Interrupt Statistics Report:\n"); | |
2259 | ||
2260 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
2261 | isr_stats->hw); | |
2262 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
2263 | isr_stats->sw); | |
2264 | if (isr_stats->sw || isr_stats->hw) { | |
2265 | pos += scnprintf(buf + pos, bufsz - pos, | |
2266 | "\tLast Restarting Code: 0x%X\n", | |
2267 | isr_stats->err_code); | |
2268 | } | |
2269 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2270 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
2271 | isr_stats->sch); | |
2272 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
2273 | isr_stats->alive); | |
2274 | #endif | |
2275 | pos += scnprintf(buf + pos, bufsz - pos, | |
2276 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
2277 | ||
2278 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
2279 | isr_stats->ctkill); | |
2280 | ||
2281 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
2282 | isr_stats->wakeup); | |
2283 | ||
2284 | pos += scnprintf(buf + pos, bufsz - pos, | |
2285 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
2286 | ||
2287 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
2288 | isr_stats->tx); | |
2289 | ||
2290 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
2291 | isr_stats->unhandled); | |
2292 | ||
2293 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2294 | kfree(buf); | |
2295 | return ret; | |
2296 | } | |
2297 | ||
2298 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
2299 | const char __user *user_buf, | |
2300 | size_t count, loff_t *ppos) | |
2301 | { | |
2302 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 2303 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
2304 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
2305 | ||
2306 | char buf[8]; | |
2307 | int buf_size; | |
2308 | u32 reset_flag; | |
2309 | ||
2310 | memset(buf, 0, sizeof(buf)); | |
2311 | buf_size = min(count, sizeof(buf) - 1); | |
2312 | if (copy_from_user(buf, user_buf, buf_size)) | |
2313 | return -EFAULT; | |
2314 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
2315 | return -EFAULT; | |
2316 | if (reset_flag == 0) | |
2317 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
2318 | ||
2319 | return count; | |
2320 | } | |
2321 | ||
16db88ba | 2322 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
2323 | const char __user *user_buf, |
2324 | size_t count, loff_t *ppos) | |
16db88ba EG |
2325 | { |
2326 | struct iwl_trans *trans = file->private_data; | |
2327 | char buf[8]; | |
2328 | int buf_size; | |
2329 | int csr; | |
2330 | ||
2331 | memset(buf, 0, sizeof(buf)); | |
2332 | buf_size = min(count, sizeof(buf) - 1); | |
2333 | if (copy_from_user(buf, user_buf, buf_size)) | |
2334 | return -EFAULT; | |
2335 | if (sscanf(buf, "%d", &csr) != 1) | |
2336 | return -EFAULT; | |
2337 | ||
990aa6d7 | 2338 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
2339 | |
2340 | return count; | |
2341 | } | |
2342 | ||
16db88ba | 2343 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
2344 | char __user *user_buf, |
2345 | size_t count, loff_t *ppos) | |
16db88ba EG |
2346 | { |
2347 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 2348 | char *buf = NULL; |
56c2477f | 2349 | ssize_t ret; |
16db88ba | 2350 | |
56c2477f JB |
2351 | ret = iwl_dump_fh(trans, &buf); |
2352 | if (ret < 0) | |
2353 | return ret; | |
2354 | if (!buf) | |
2355 | return -EINVAL; | |
2356 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); | |
2357 | kfree(buf); | |
16db88ba EG |
2358 | return ret; |
2359 | } | |
2360 | ||
1f7b6172 | 2361 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2362 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2363 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2364 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2365 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c | 2366 | |
f8a1edb7 JB |
2367 | /* Create the debugfs files and directories */ |
2368 | int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) | |
87e5666c | 2369 | { |
f8a1edb7 JB |
2370 | struct dentry *dir = trans->dbgfs_dir; |
2371 | ||
87e5666c EG |
2372 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
2373 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 2374 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
2375 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
2376 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c | 2377 | return 0; |
9da987ac MV |
2378 | |
2379 | err: | |
2380 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
2381 | return -ENOMEM; | |
87e5666c | 2382 | } |
aadede6e | 2383 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
4d075007 JB |
2384 | |
2385 | static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) | |
2386 | { | |
2387 | u32 cmdlen = 0; | |
2388 | int i; | |
2389 | ||
2390 | for (i = 0; i < IWL_NUM_OF_TBS; i++) | |
2391 | cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); | |
2392 | ||
2393 | return cmdlen; | |
2394 | } | |
2395 | ||
bd7fc617 EG |
2396 | static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, |
2397 | struct iwl_fw_error_dump_data **data, | |
2398 | int allocated_rb_nums) | |
2399 | { | |
2400 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2401 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; | |
78485054 SS |
2402 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
2403 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; | |
bd7fc617 EG |
2404 | u32 i, r, j, rb_len = 0; |
2405 | ||
2406 | spin_lock(&rxq->lock); | |
2407 | ||
2408 | r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; | |
2409 | ||
2410 | for (i = rxq->read, j = 0; | |
2411 | i != r && j < allocated_rb_nums; | |
2412 | i = (i + 1) & RX_QUEUE_MASK, j++) { | |
2413 | struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; | |
2414 | struct iwl_fw_error_dump_rb *rb; | |
2415 | ||
2416 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, | |
2417 | DMA_FROM_DEVICE); | |
2418 | ||
2419 | rb_len += sizeof(**data) + sizeof(*rb) + max_len; | |
2420 | ||
2421 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); | |
2422 | (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); | |
2423 | rb = (void *)(*data)->data; | |
2424 | rb->index = cpu_to_le32(i); | |
2425 | memcpy(rb->data, page_address(rxb->page), max_len); | |
2426 | /* remap the page for the free benefit */ | |
2427 | rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, | |
2428 | max_len, | |
2429 | DMA_FROM_DEVICE); | |
2430 | ||
2431 | *data = iwl_fw_error_next_data(*data); | |
2432 | } | |
2433 | ||
2434 | spin_unlock(&rxq->lock); | |
2435 | ||
2436 | return rb_len; | |
2437 | } | |
473ad712 EG |
2438 | #define IWL_CSR_TO_DUMP (0x250) |
2439 | ||
2440 | static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, | |
2441 | struct iwl_fw_error_dump_data **data) | |
2442 | { | |
2443 | u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; | |
2444 | __le32 *val; | |
2445 | int i; | |
2446 | ||
2447 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); | |
2448 | (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); | |
2449 | val = (void *)(*data)->data; | |
2450 | ||
2451 | for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) | |
2452 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2453 | ||
2454 | *data = iwl_fw_error_next_data(*data); | |
2455 | ||
2456 | return csr_len; | |
2457 | } | |
2458 | ||
06d51e0d LK |
2459 | static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, |
2460 | struct iwl_fw_error_dump_data **data) | |
2461 | { | |
2462 | u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; | |
2463 | unsigned long flags; | |
2464 | __le32 *val; | |
2465 | int i; | |
2466 | ||
23ba9340 | 2467 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
06d51e0d LK |
2468 | return 0; |
2469 | ||
2470 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); | |
2471 | (*data)->len = cpu_to_le32(fh_regs_len); | |
2472 | val = (void *)(*data)->data; | |
2473 | ||
2474 | for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) | |
2475 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2476 | ||
2477 | iwl_trans_release_nic_access(trans, &flags); | |
2478 | ||
2479 | *data = iwl_fw_error_next_data(*data); | |
2480 | ||
2481 | return sizeof(**data) + fh_regs_len; | |
2482 | } | |
2483 | ||
cc79ef66 LK |
2484 | static u32 |
2485 | iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, | |
2486 | struct iwl_fw_error_dump_fw_mon *fw_mon_data, | |
2487 | u32 monitor_len) | |
2488 | { | |
2489 | u32 buf_size_in_dwords = (monitor_len >> 2); | |
2490 | u32 *buffer = (u32 *)fw_mon_data->data; | |
2491 | unsigned long flags; | |
2492 | u32 i; | |
2493 | ||
23ba9340 | 2494 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
cc79ef66 LK |
2495 | return 0; |
2496 | ||
14ef1b43 | 2497 | iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); |
cc79ef66 | 2498 | for (i = 0; i < buf_size_in_dwords; i++) |
14ef1b43 GBA |
2499 | buffer[i] = iwl_read_prph_no_grab(trans, |
2500 | MON_DMARB_RD_DATA_ADDR); | |
2501 | iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); | |
cc79ef66 LK |
2502 | |
2503 | iwl_trans_release_nic_access(trans, &flags); | |
2504 | ||
2505 | return monitor_len; | |
2506 | } | |
2507 | ||
36fb9017 OG |
2508 | static u32 |
2509 | iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, | |
2510 | struct iwl_fw_error_dump_data **data, | |
2511 | u32 monitor_len) | |
2512 | { | |
2513 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2514 | u32 len = 0; | |
2515 | ||
2516 | if ((trans_pcie->fw_mon_page && | |
2517 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || | |
2518 | trans->dbg_dest_tlv) { | |
2519 | struct iwl_fw_error_dump_fw_mon *fw_mon_data; | |
2520 | u32 base, write_ptr, wrap_cnt; | |
2521 | ||
2522 | /* If there was a dest TLV - use the values from there */ | |
2523 | if (trans->dbg_dest_tlv) { | |
2524 | write_ptr = | |
2525 | le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); | |
2526 | wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); | |
2527 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
2528 | } else { | |
2529 | base = MON_BUFF_BASE_ADDR; | |
2530 | write_ptr = MON_BUFF_WRPTR; | |
2531 | wrap_cnt = MON_BUFF_CYCLE_CNT; | |
2532 | } | |
2533 | ||
2534 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); | |
2535 | fw_mon_data = (void *)(*data)->data; | |
2536 | fw_mon_data->fw_mon_wr_ptr = | |
2537 | cpu_to_le32(iwl_read_prph(trans, write_ptr)); | |
2538 | fw_mon_data->fw_mon_cycle_cnt = | |
2539 | cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); | |
2540 | fw_mon_data->fw_mon_base_ptr = | |
2541 | cpu_to_le32(iwl_read_prph(trans, base)); | |
2542 | ||
2543 | len += sizeof(**data) + sizeof(*fw_mon_data); | |
2544 | if (trans_pcie->fw_mon_page) { | |
2545 | /* | |
2546 | * The firmware is now asserted, it won't write anything | |
2547 | * to the buffer. CPU can take ownership to fetch the | |
2548 | * data. The buffer will be handed back to the device | |
2549 | * before the firmware will be restarted. | |
2550 | */ | |
2551 | dma_sync_single_for_cpu(trans->dev, | |
2552 | trans_pcie->fw_mon_phys, | |
2553 | trans_pcie->fw_mon_size, | |
2554 | DMA_FROM_DEVICE); | |
2555 | memcpy(fw_mon_data->data, | |
2556 | page_address(trans_pcie->fw_mon_page), | |
2557 | trans_pcie->fw_mon_size); | |
2558 | ||
2559 | monitor_len = trans_pcie->fw_mon_size; | |
2560 | } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { | |
2561 | /* | |
2562 | * Update pointers to reflect actual values after | |
2563 | * shifting | |
2564 | */ | |
2565 | base = iwl_read_prph(trans, base) << | |
2566 | trans->dbg_dest_tlv->base_shift; | |
2567 | iwl_trans_read_mem(trans, base, fw_mon_data->data, | |
2568 | monitor_len / sizeof(u32)); | |
2569 | } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { | |
2570 | monitor_len = | |
2571 | iwl_trans_pci_dump_marbh_monitor(trans, | |
2572 | fw_mon_data, | |
2573 | monitor_len); | |
2574 | } else { | |
2575 | /* Didn't match anything - output no monitor data */ | |
2576 | monitor_len = 0; | |
2577 | } | |
2578 | ||
2579 | len += monitor_len; | |
2580 | (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); | |
2581 | } | |
2582 | ||
2583 | return len; | |
2584 | } | |
2585 | ||
2586 | static struct iwl_trans_dump_data | |
2587 | *iwl_trans_pcie_dump_data(struct iwl_trans *trans, | |
a80c7a69 | 2588 | const struct iwl_fw_dbg_trigger_tlv *trigger) |
4d075007 JB |
2589 | { |
2590 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2591 | struct iwl_fw_error_dump_data *data; | |
2592 | struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; | |
2593 | struct iwl_fw_error_dump_txcmd *txcmd; | |
48eb7b34 | 2594 | struct iwl_trans_dump_data *dump_data; |
bd7fc617 | 2595 | u32 len, num_rbs; |
99684ae3 | 2596 | u32 monitor_len; |
4d075007 | 2597 | int i, ptr; |
96a6497b SS |
2598 | bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && |
2599 | !trans->cfg->mq_rx_supported; | |
4d075007 | 2600 | |
473ad712 EG |
2601 | /* transport dump header */ |
2602 | len = sizeof(*dump_data); | |
2603 | ||
2604 | /* host commands */ | |
2605 | len += sizeof(*data) + | |
c2d20201 EG |
2606 | cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); |
2607 | ||
473ad712 | 2608 | /* FW monitor */ |
99684ae3 | 2609 | if (trans_pcie->fw_mon_page) { |
c544e9c4 | 2610 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + |
99684ae3 LK |
2611 | trans_pcie->fw_mon_size; |
2612 | monitor_len = trans_pcie->fw_mon_size; | |
2613 | } else if (trans->dbg_dest_tlv) { | |
2614 | u32 base, end; | |
2615 | ||
2616 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
2617 | end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); | |
2618 | ||
2619 | base = iwl_read_prph(trans, base) << | |
2620 | trans->dbg_dest_tlv->base_shift; | |
2621 | end = iwl_read_prph(trans, end) << | |
2622 | trans->dbg_dest_tlv->end_shift; | |
2623 | ||
2624 | /* Make "end" point to the actual end */ | |
cc79ef66 LK |
2625 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || |
2626 | trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) | |
99684ae3 LK |
2627 | end += (1 << trans->dbg_dest_tlv->end_shift); |
2628 | monitor_len = end - base; | |
2629 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + | |
2630 | monitor_len; | |
2631 | } else { | |
2632 | monitor_len = 0; | |
2633 | } | |
c2d20201 | 2634 | |
36fb9017 OG |
2635 | if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { |
2636 | dump_data = vzalloc(len); | |
2637 | if (!dump_data) | |
2638 | return NULL; | |
2639 | ||
2640 | data = (void *)dump_data->data; | |
2641 | len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); | |
2642 | dump_data->len = len; | |
2643 | ||
2644 | return dump_data; | |
2645 | } | |
2646 | ||
2647 | /* CSR registers */ | |
2648 | len += sizeof(*data) + IWL_CSR_TO_DUMP; | |
2649 | ||
36fb9017 OG |
2650 | /* FH registers */ |
2651 | len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); | |
2652 | ||
2653 | if (dump_rbs) { | |
78485054 SS |
2654 | /* Dump RBs is supported only for pre-9000 devices (1 queue) */ |
2655 | struct iwl_rxq *rxq = &trans_pcie->rxq[0]; | |
36fb9017 | 2656 | /* RBs */ |
78485054 | 2657 | num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) |
36fb9017 | 2658 | & 0x0FFF; |
78485054 | 2659 | num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; |
36fb9017 OG |
2660 | len += num_rbs * (sizeof(*data) + |
2661 | sizeof(struct iwl_fw_error_dump_rb) + | |
2662 | (PAGE_SIZE << trans_pcie->rx_page_order)); | |
2663 | } | |
2664 | ||
48eb7b34 EG |
2665 | dump_data = vzalloc(len); |
2666 | if (!dump_data) | |
2667 | return NULL; | |
4d075007 JB |
2668 | |
2669 | len = 0; | |
48eb7b34 | 2670 | data = (void *)dump_data->data; |
4d075007 JB |
2671 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); |
2672 | txcmd = (void *)data->data; | |
2673 | spin_lock_bh(&cmdq->lock); | |
2674 | ptr = cmdq->q.write_ptr; | |
2675 | for (i = 0; i < cmdq->q.n_window; i++) { | |
2676 | u8 idx = get_cmd_index(&cmdq->q, ptr); | |
2677 | u32 caplen, cmdlen; | |
2678 | ||
2679 | cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); | |
2680 | caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); | |
2681 | ||
2682 | if (cmdlen) { | |
2683 | len += sizeof(*txcmd) + caplen; | |
2684 | txcmd->cmdlen = cpu_to_le32(cmdlen); | |
2685 | txcmd->caplen = cpu_to_le32(caplen); | |
2686 | memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); | |
2687 | txcmd = (void *)((u8 *)txcmd->data + caplen); | |
2688 | } | |
2689 | ||
2690 | ptr = iwl_queue_dec_wrap(ptr); | |
2691 | } | |
2692 | spin_unlock_bh(&cmdq->lock); | |
2693 | ||
2694 | data->len = cpu_to_le32(len); | |
c2d20201 | 2695 | len += sizeof(*data); |
67c65f2c EG |
2696 | data = iwl_fw_error_next_data(data); |
2697 | ||
473ad712 | 2698 | len += iwl_trans_pcie_dump_csr(trans, &data); |
06d51e0d | 2699 | len += iwl_trans_pcie_fh_regs_dump(trans, &data); |
bd7fc617 EG |
2700 | if (dump_rbs) |
2701 | len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); | |
c2d20201 | 2702 | |
36fb9017 | 2703 | len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); |
c2d20201 | 2704 | |
48eb7b34 EG |
2705 | dump_data->len = len; |
2706 | ||
2707 | return dump_data; | |
4d075007 | 2708 | } |
87e5666c | 2709 | |
4cbb8e50 LC |
2710 | #ifdef CONFIG_PM_SLEEP |
2711 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) | |
2712 | { | |
2713 | if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) | |
2714 | return iwl_pci_fw_enter_d0i3(trans); | |
2715 | ||
2716 | return 0; | |
2717 | } | |
2718 | ||
2719 | static void iwl_trans_pcie_resume(struct iwl_trans *trans) | |
2720 | { | |
2721 | if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) | |
2722 | iwl_pci_fw_exit_d0i3(trans); | |
2723 | } | |
2724 | #endif /* CONFIG_PM_SLEEP */ | |
2725 | ||
d1ff5253 | 2726 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2727 | .start_hw = iwl_trans_pcie_start_hw, |
a4082843 | 2728 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, |
ed6a3803 | 2729 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2730 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2731 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2732 | |
ddaf5a5b JB |
2733 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
2734 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 2735 | |
4cbb8e50 LC |
2736 | #ifdef CONFIG_PM_SLEEP |
2737 | .suspend = iwl_trans_pcie_suspend, | |
2738 | .resume = iwl_trans_pcie_resume, | |
2739 | #endif /* CONFIG_PM_SLEEP */ | |
2740 | ||
f02831be | 2741 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 2742 | |
e6bb4c9c | 2743 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2744 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2745 | |
d0624be6 | 2746 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 2747 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 2748 | |
990aa6d7 | 2749 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
e0b8d405 | 2750 | .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, |
0cd58eaa | 2751 | .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, |
5f178cd2 | 2752 | |
03905495 EG |
2753 | .write8 = iwl_trans_pcie_write8, |
2754 | .write32 = iwl_trans_pcie_write32, | |
2755 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
2756 | .read_prph = iwl_trans_pcie_read_prph, |
2757 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
2758 | .read_mem = iwl_trans_pcie_read_mem, |
2759 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 2760 | .configure = iwl_trans_pcie_configure, |
47107e84 | 2761 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 2762 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
2763 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
2764 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
4d075007 | 2765 | |
7616f334 EP |
2766 | .ref = iwl_trans_pcie_ref, |
2767 | .unref = iwl_trans_pcie_unref, | |
2768 | ||
4d075007 | 2769 | .dump_data = iwl_trans_pcie_dump_data, |
e6bb4c9c | 2770 | }; |
a42a1844 | 2771 | |
87ce05a2 | 2772 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
2773 | const struct pci_device_id *ent, |
2774 | const struct iwl_cfg *cfg) | |
a42a1844 | 2775 | { |
a42a1844 EG |
2776 | struct iwl_trans_pcie *trans_pcie; |
2777 | struct iwl_trans *trans; | |
96a6497b | 2778 | int ret, addr_size; |
a42a1844 | 2779 | |
7b501d10 JB |
2780 | trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), |
2781 | &pdev->dev, cfg, &trans_ops_pcie, 0); | |
2782 | if (!trans) | |
2783 | return ERR_PTR(-ENOMEM); | |
a42a1844 | 2784 | |
206eea78 JB |
2785 | trans->max_skb_frags = IWL_PCIE_MAX_FRAGS; |
2786 | ||
a42a1844 EG |
2787 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
2788 | ||
a42a1844 | 2789 | trans_pcie->trans = trans; |
7b11488f | 2790 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 2791 | spin_lock_init(&trans_pcie->reg_lock); |
fa9f3281 | 2792 | mutex_init(&trans_pcie->mutex); |
13df1aab | 2793 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
6eb5e529 EG |
2794 | trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); |
2795 | if (!trans_pcie->tso_hdr_page) { | |
2796 | ret = -ENOMEM; | |
2797 | goto out_no_pci; | |
2798 | } | |
a42a1844 | 2799 | |
af3f2f74 EG |
2800 | ret = pci_enable_device(pdev); |
2801 | if (ret) | |
d819c6cf JB |
2802 | goto out_no_pci; |
2803 | ||
f2532b04 EG |
2804 | if (!cfg->base_params->pcie_l1_allowed) { |
2805 | /* | |
2806 | * W/A - seems to solve weird behavior. We need to remove this | |
2807 | * if we don't want to stay in L1 all the time. This wastes a | |
2808 | * lot of power. | |
2809 | */ | |
2810 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
2811 | PCIE_LINK_STATE_L1 | | |
2812 | PCIE_LINK_STATE_CLKPM); | |
2813 | } | |
a42a1844 | 2814 | |
96a6497b SS |
2815 | if (cfg->mq_rx_supported) |
2816 | addr_size = 64; | |
2817 | else | |
2818 | addr_size = 36; | |
2819 | ||
a42a1844 EG |
2820 | pci_set_master(pdev); |
2821 | ||
96a6497b | 2822 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); |
af3f2f74 | 2823 | if (!ret) |
96a6497b SS |
2824 | ret = pci_set_consistent_dma_mask(pdev, |
2825 | DMA_BIT_MASK(addr_size)); | |
af3f2f74 EG |
2826 | if (ret) { |
2827 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2828 | if (!ret) | |
2829 | ret = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 2830 | DMA_BIT_MASK(32)); |
a42a1844 | 2831 | /* both attempts failed: */ |
af3f2f74 | 2832 | if (ret) { |
6a4b09f8 | 2833 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
2834 | goto out_pci_disable_device; |
2835 | } | |
2836 | } | |
2837 | ||
af3f2f74 EG |
2838 | ret = pci_request_regions(pdev, DRV_NAME); |
2839 | if (ret) { | |
6a4b09f8 | 2840 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
2841 | goto out_pci_disable_device; |
2842 | } | |
2843 | ||
05f5b97e | 2844 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 2845 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 2846 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
af3f2f74 | 2847 | ret = -ENODEV; |
a42a1844 EG |
2848 | goto out_pci_release_regions; |
2849 | } | |
2850 | ||
a42a1844 EG |
2851 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
2852 | * PCI Tx retries from interfering with C3 CPU state */ | |
2853 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2854 | ||
83f7a85f EG |
2855 | trans->dev = &pdev->dev; |
2856 | trans_pcie->pci_dev = pdev; | |
2857 | iwl_disable_interrupts(trans); | |
2858 | ||
08079a49 | 2859 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
b513ee7f LK |
2860 | /* |
2861 | * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have | |
2862 | * changed, and now the revision step also includes bit 0-1 (no more | |
2863 | * "dash" value). To keep hw_rev backwards compatible - we'll store it | |
2864 | * in the old format. | |
2865 | */ | |
7a42baa6 EH |
2866 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { |
2867 | unsigned long flags; | |
7a42baa6 | 2868 | |
b513ee7f | 2869 | trans->hw_rev = (trans->hw_rev & 0xfff0) | |
1fc0e221 | 2870 | (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); |
b513ee7f | 2871 | |
f9e5554c EG |
2872 | ret = iwl_pcie_prepare_card_hw(trans); |
2873 | if (ret) { | |
2874 | IWL_WARN(trans, "Exit HW not ready\n"); | |
2875 | goto out_pci_disable_msi; | |
2876 | } | |
2877 | ||
7a42baa6 EH |
2878 | /* |
2879 | * in-order to recognize C step driver should read chip version | |
2880 | * id located at the AUX bus MISC address space. | |
2881 | */ | |
2882 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
2883 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
2884 | udelay(2); | |
2885 | ||
2886 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
2887 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
2888 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
2889 | 25000); | |
2890 | if (ret < 0) { | |
2891 | IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); | |
2892 | goto out_pci_disable_msi; | |
2893 | } | |
2894 | ||
23ba9340 | 2895 | if (iwl_trans_grab_nic_access(trans, &flags)) { |
7a42baa6 EH |
2896 | u32 hw_step; |
2897 | ||
14ef1b43 | 2898 | hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); |
7a42baa6 | 2899 | hw_step |= ENABLE_WFPM; |
14ef1b43 GBA |
2900 | iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); |
2901 | hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); | |
7a42baa6 EH |
2902 | hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; |
2903 | if (hw_step == 0x3) | |
2904 | trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | | |
2905 | (SILICON_C_STEP << 2); | |
2906 | iwl_trans_release_nic_access(trans, &flags); | |
2907 | } | |
2908 | } | |
2909 | ||
2e5d4a8f | 2910 | iwl_pcie_set_interrupt_capa(pdev, trans); |
99673ee5 | 2911 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2912 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2913 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 2914 | |
69a10b29 | 2915 | /* Initialize the wait queue for commands */ |
f946b529 | 2916 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 2917 | |
4cbb8e50 LC |
2918 | init_waitqueue_head(&trans_pcie->d0i3_waitq); |
2919 | ||
2e5d4a8f HD |
2920 | if (trans_pcie->msix_enabled) { |
2921 | if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) | |
2922 | goto out_pci_release_regions; | |
2923 | } else { | |
2924 | ret = iwl_pcie_alloc_ict(trans); | |
2925 | if (ret) | |
2926 | goto out_pci_disable_msi; | |
a8b691e6 | 2927 | |
2e5d4a8f HD |
2928 | ret = request_threaded_irq(pdev->irq, iwl_pcie_isr, |
2929 | iwl_pcie_irq_handler, | |
2930 | IRQF_SHARED, DRV_NAME, trans); | |
2931 | if (ret) { | |
2932 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); | |
2933 | goto out_free_ict; | |
2934 | } | |
2935 | trans_pcie->inta_mask = CSR_INI_SET_MASK; | |
2936 | } | |
83f7a85f | 2937 | |
b3ff1270 LC |
2938 | #ifdef CONFIG_IWLWIFI_PCIE_RTPM |
2939 | trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; | |
2940 | #else | |
2941 | trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; | |
2942 | #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ | |
2943 | ||
a42a1844 EG |
2944 | return trans; |
2945 | ||
a8b691e6 JB |
2946 | out_free_ict: |
2947 | iwl_pcie_free_ict(trans); | |
59c647b6 EG |
2948 | out_pci_disable_msi: |
2949 | pci_disable_msi(pdev); | |
a42a1844 EG |
2950 | out_pci_release_regions: |
2951 | pci_release_regions(pdev); | |
2952 | out_pci_disable_device: | |
2953 | pci_disable_device(pdev); | |
2954 | out_no_pci: | |
6eb5e529 | 2955 | free_percpu(trans_pcie->tso_hdr_page); |
7b501d10 | 2956 | iwl_trans_free(trans); |
af3f2f74 | 2957 | return ERR_PTR(ret); |
a42a1844 | 2958 | } |