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iwlwifi: mvm: support new reduce tx power FW API.
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
a8cbb46f 11 * Copyright(c) 2018 Intel Corporation
c85eb619
EG		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * USA
26 *
27 * The full GNU General Public License is included in this distribution
410dc5aa 28 * in the file called COPYING.
c85eb619
EG		 29 *
30 * Contact Information:
cb2f8277 31 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *
34 * BSD LICENSE
35 *
553452e5
LK		 36 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
37 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 38 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
a8cbb46f 39 * Copyright(c) 2018 Intel Corporation
c85eb619
EG		 40 * All rights reserved.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
44 * are met:
45 *
46 * * Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * * Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in
50 * the documentation and/or other materials provided with the
51 * distribution.
52 * * Neither the name Intel Corporation nor the names of its
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
55 *
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
57 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
59 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
60 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
62 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 *
68 *****************************************************************************/
a42a1844
EG		 69#include <linux/pci.h>
70#include <linux/pci-aspm.h>
e6bb4c9c 71#include <linux/interrupt.h>
87e5666c 72#include <linux/debugfs.h>
cf614297 73#include <linux/sched.h>
6d8f6eeb
EG		 74#include <linux/bitops.h>
75#include <linux/gfp.h>
48eb7b34 76#include <linux/vmalloc.h>
b3ff1270 77#include <linux/pm_runtime.h>
49564a80 78#include <linux/module.h>
e6bb4c9c 79
82575102 80#include "iwl-drv.h"
c85eb619 81#include "iwl-trans.h"
522376d2
EG		 82#include "iwl-csr.h"
83#include "iwl-prph.h"
cb6bb128 84#include "iwl-scd.h"
7a10e3e4 85#include "iwl-agn-hw.h"
d962f9b1 86#include "fw/error-dump.h"
520f03ea 87#include "fw/dbg.h"
6468a01a 88#include "internal.h"
06d51e0d 89#include "iwl-fh.h"
0439bb62 90
fe45773b
AN		 91/* extended range in FW SRAM */
92#define IWL_FW_MEM_EXTENDED_START 0x40000
93#define IWL_FW_MEM_EXTENDED_END 0x57FFF
94
4290eaad 95void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad
RJ		 96{
97#define PCI_DUMP_SIZE 64
98#define PREFIX_LEN 32
99 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
100 struct pci_dev *pdev = trans_pcie->pci_dev;
101 u32 i, pos, alloc_size, *ptr, *buf;
102 char *prefix;
103
104 if (trans_pcie->pcie_dbg_dumped_once)
105 return;
106
107 /* Should be a multiple of 4 */
108 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
109 /* Alloc a max size buffer */
110 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
111 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
112 else
113 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
114 buf = kmalloc(alloc_size, GFP_ATOMIC);
115 if (!buf)
116 return;
117 prefix = (char *)buf + alloc_size - PREFIX_LEN;
118
119 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
120
121 /* Print wifi device registers */
122 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
123 IWL_ERR(trans, "iwlwifi device config registers:\n");
124 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
125 if (pci_read_config_dword(pdev, i, ptr))
126 goto err_read;
127 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
128
129 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
130 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
131 *ptr = iwl_read32(trans, i);
132 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
133
134 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
135 if (pos) {
136 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
137 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
138 if (pci_read_config_dword(pdev, pos + i, ptr))
139 goto err_read;
140 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
141 32, 4, buf, i, 0);
142 }
143
144 /* Print parent device registers next */
145 if (!pdev->bus->self)
146 goto out;
147
148 pdev = pdev->bus->self;
149 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
150
151 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
152 pci_name(pdev));
153 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
154 if (pci_read_config_dword(pdev, i, ptr))
155 goto err_read;
156 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
157
158 /* Print root port AER registers */
159 pos = 0;
160 pdev = pcie_find_root_port(pdev);
161 if (pdev)
162 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
163 if (pos) {
164 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
165 pci_name(pdev));
166 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
167 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
168 if (pci_read_config_dword(pdev, pos + i, ptr))
169 goto err_read;
170 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
171 4, buf, i, 0);
172 }
f3402d6d 173 goto out;
a6d24fad
RJ		 174
175err_read:
176 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
177 IWL_ERR(trans, "Read failed at 0x%X\n", i);
178out:
179 trans_pcie->pcie_dbg_dumped_once = 1;
180 kfree(buf);
181}
182
870c2a11
GBA		 183static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
184{
185 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
a8cbb46f
GBA		 186 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
187 BIT(trans->cfg->csr->flag_sw_reset));
870c2a11
GBA		 188 usleep_range(5000, 6000);
189}
190
c2d20201
EG		 191static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
192{
193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
194
195 if (!trans_pcie->fw_mon_page)
196 return;
197
198 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
199 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
200 __free_pages(trans_pcie->fw_mon_page,
201 get_order(trans_pcie->fw_mon_size));
202 trans_pcie->fw_mon_page = NULL;
203 trans_pcie->fw_mon_phys = 0;
204 trans_pcie->fw_mon_size = 0;
205}
206
9f358c17 207void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 208{
209 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 210 struct page *page = NULL;
c2d20201 211 dma_addr_t phys;
96c285da 212 u32 size = 0;
c2d20201
EG		 213 u8 power;
214
96c285da
EG		 215 if (!max_power) {
216 /* default max_power is maximum */
217 max_power = 26;
218 } else {
219 max_power += 11;
220 }
221
222 if (WARN(max_power > 26,
223 "External buffer size for monitor is too big %d, check the FW TLV\n",
224 max_power))
225 return;
226
c2d20201
EG		 227 if (trans_pcie->fw_mon_page) {
228 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
229 trans_pcie->fw_mon_size,
230 DMA_FROM_DEVICE);
231 return;
232 }
233
234 phys = 0;
96c285da 235 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 236 int order;
237
238 size = BIT(power);
239 order = get_order(size);
240 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
241 order);
242 if (!page)
243 continue;
244
245 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
246 DMA_FROM_DEVICE);
247 if (dma_mapping_error(trans->dev, phys)) {
248 __free_pages(page, order);
553452e5 249 page = NULL;
c2d20201
EG		 250 continue;
251 }
252 IWL_INFO(trans,
253 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
254 size, order);
255 break;
256 }
257
40a76905 258 if (WARN_ON_ONCE(!page))
c2d20201
EG		 259 return;
260
96c285da
EG		 261 if (power != max_power)
262 IWL_ERR(trans,
263 "Sorry - debug buffer is only %luK while you requested %luK\n",
264 (unsigned long)BIT(power - 10),
265 (unsigned long)BIT(max_power - 10));
266
c2d20201
EG		 267 trans_pcie->fw_mon_page = page;
268 trans_pcie->fw_mon_phys = phys;
269 trans_pcie->fw_mon_size = size;
270}
271
a812cba9
AB		 272static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
273{
274 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
275 ((reg & 0x0000ffff) | (2 << 28)));
276 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
277}
278
279static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
280{
281 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
282 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
283 ((reg & 0x0000ffff) | (3 << 28)));
284}
285
ddaf5a5b 286static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 287{
66337b7c 288 if (trans->cfg->apmg_not_supported)
95411d04
AA		 289 return;
290
ddaf5a5b
JB		 291 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
292 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
293 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
294 ~APMG_PS_CTRL_MSK_PWR_SRC);
295 else
296 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
297 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
298 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 299}
300
af634bee
EG		 301/* PCI registers */
302#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 303
eda50cde 304void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 305{
20d3b647 306 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 307 u16 lctl;
9180ac50 308 u16 cap;
af634bee 309
af634bee
EG		 310 /*
311 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
312 * Check if BIOS (or OS) enabled L1-ASPM on this device.
313 * If so (likely), disable L0S, so device moves directly L0->L1;
314 * costs negligible amount of power savings.
315 * If not (unlikely), enable L0S, so there is at least some
316 * power savings, even without L1.
317 */
7afe3705 318 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 319 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 320 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 321 else
af634bee 322 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 323 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 324
325 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
326 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 327 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
328 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
329 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 330}
331
a6c684ee
EG		 332/*
333 * Start up NIC's basic functionality after it has been reset
7afe3705 334 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 335 * NOTE: This does not load uCode nor start the embedded processor
336 */
7afe3705 337static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 338{
52b6e168
EG		 339 int ret;
340
a6c684ee
EG		 341 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
342
343 /*
344 * Use "set_bit" below rather than "write", to preserve any hardware
345 * bits already set by default after reset.
346 */
347
348 /* Disable L0S exit timer (platform NMI Work/Around) */
6e584873 349 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 350 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
351 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 352
353 /*
354 * Disable L0s without affecting L1;
355 * don't wait for ICH L0s (ICH bug W/A)
356 */
357 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 358 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 359
360 /* Set FH wait threshold to maximum (HW error during stress W/A) */
361 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
362
363 /*
364 * Enable HAP INTA (interrupt from management bus) to
365 * wake device's PCI Express link L1a -> L0s
366 */
367 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 368 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 369
7afe3705 370 iwl_pcie_apm_config(trans);
a6c684ee
EG		 371
372 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 373 if (trans->cfg->base_params->pll_cfg)
374 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 375
376 /*
377 * Set "initialization complete" bit to move adapter from
378 * D0U* --> D0A* (powered-up active) state.
379 */
a8cbb46f
GBA		 380 iwl_set_bit(trans, CSR_GP_CNTRL,
381 BIT(trans->cfg->csr->flag_init_done));
a6c684ee
EG		 382
383 /*
384 * Wait for clock stabilization; once stabilized, access to
385 * device-internal resources is supported, e.g. iwl_write_prph()
386 * and accesses to uCode SRAM.
387 */
388 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 389 BIT(trans->cfg->csr->flag_mac_clock_ready),
390 BIT(trans->cfg->csr->flag_mac_clock_ready),
391 25000);
a6c684ee 392 if (ret < 0) {
52b6e168
EG		 393 IWL_ERR(trans, "Failed to init the card\n");
394 return ret;
a6c684ee
EG		 395 }
396
2d93aee1
EG		 397 if (trans->cfg->host_interrupt_operation_mode) {
398 /*
399 * This is a bit of an abuse - This is needed for 7260 / 3160
400 * only check host_interrupt_operation_mode even if this is
401 * not related to host_interrupt_operation_mode.
402 *
403 * Enable the oscillator to count wake up time for L1 exit. This
404 * consumes slightly more power (100uA) - but allows to be sure
405 * that we wake up from L1 on time.
406 *
407 * This looks weird: read twice the same register, discard the
408 * value, set a bit, and yet again, read that same register
409 * just to discard the value. But that's the way the hardware
410 * seems to like it.
411 */
412 iwl_read_prph(trans, OSC_CLK);
413 iwl_read_prph(trans, OSC_CLK);
414 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
415 iwl_read_prph(trans, OSC_CLK);
416 iwl_read_prph(trans, OSC_CLK);
417 }
418
a6c684ee
EG		 419 /*
420 * Enable DMA clock and wait for it to stabilize.
421 *
3073d8c0
EH		 422 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
423 * bits do not disable clocks. This preserves any hardware
424 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 425 */
95411d04 426 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 427 iwl_write_prph(trans, APMG_CLK_EN_REG,
428 APMG_CLK_VAL_DMA_CLK_RQT);
429 udelay(20);
430
431 /* Disable L1-Active */
432 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
433 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
434
435 /* Clear the interrupt in APMG if the NIC is in RFKILL */
436 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
437 APMG_RTC_INT_STT_RFKILL);
438 }
889b1696 439
eb7ff77e 440 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 441
52b6e168 442 return 0;
a6c684ee
EG		 443}
444
a812cba9
AB		 445/*
446 * Enable LP XTAL to avoid HW bug where device may consume much power if
447 * FW is not loaded after device reset. LP XTAL is disabled by default
448 * after device HW reset. Do it only if XTAL is fed by internal source.
449 * Configure device's "persistence" mode to avoid resetting XTAL again when
450 * SHRD_HW_RST occurs in S3.
451 */
452static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
453{
454 int ret;
455 u32 apmg_gp1_reg;
456 u32 apmg_xtal_cfg_reg;
457 u32 dl_cfg_reg;
458
459 /* Force XTAL ON */
460 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
461 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
462
870c2a11 463 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 464
465 /*
466 * Set "initialization complete" bit to move adapter from
467 * D0U* --> D0A* (powered-up active) state.
468 */
a8cbb46f
GBA		 469 iwl_set_bit(trans, CSR_GP_CNTRL,
470 BIT(trans->cfg->csr->flag_init_done));
a812cba9
AB		 471
472 /*
473 * Wait for clock stabilization; once stabilized, access to
474 * device-internal resources is possible.
475 */
476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 477 BIT(trans->cfg->csr->flag_mac_clock_ready),
478 BIT(trans->cfg->csr->flag_mac_clock_ready),
a812cba9
AB		 479 25000);
480 if (WARN_ON(ret < 0)) {
481 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
482 /* Release XTAL ON request */
483 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
484 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
485 return;
486 }
487
488 /*
489 * Clear "disable persistence" to avoid LP XTAL resetting when
490 * SHRD_HW_RST is applied in S3.
491 */
492 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
493 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
494
495 /*
496 * Force APMG XTAL to be active to prevent its disabling by HW
497 * caused by APMG idle state.
498 */
499 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
500 SHR_APMG_XTAL_CFG_REG);
501 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
502 apmg_xtal_cfg_reg |
503 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
504
870c2a11 505 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 506
507 /* Enable LP XTAL by indirect access through CSR */
508 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
509 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
510 SHR_APMG_GP1_WF_XTAL_LP_EN |
511 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
512
513 /* Clear delay line clock power up */
514 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
515 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
516 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
517
518 /*
519 * Enable persistence mode to avoid LP XTAL resetting when
520 * SHRD_HW_RST is applied in S3.
521 */
522 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
523 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
524
525 /*
526 * Clear "initialization complete" bit to move adapter from
527 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
528 */
529 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 530 BIT(trans->cfg->csr->flag_init_done));
a812cba9
AB		 531
532 /* Activates XTAL resources monitor */
533 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
534 CSR_MONITOR_XTAL_RESOURCES);
535
536 /* Release XTAL ON request */
537 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
538 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
539 udelay(10);
540
541 /* Release APMG XTAL */
542 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
543 apmg_xtal_cfg_reg &
544 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
545}
546
e8c8935e 547void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 548{
e8c8935e 549 int ret;
cc56feb2
EG		 550
551 /* stop device's busmaster DMA activity */
a8cbb46f
GBA		 552 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
553 BIT(trans->cfg->csr->flag_stop_master));
cc56feb2 554
a8cbb46f
GBA		 555 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
556 BIT(trans->cfg->csr->flag_master_dis),
557 BIT(trans->cfg->csr->flag_master_dis), 100);
7f2ac8fb 558 if (ret < 0)
cc56feb2
EG		 559 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
560
561 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 562}
563
b7aaeae4 564static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 565{
566 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
567
b7aaeae4
EG		 568 if (op_mode_leave) {
569 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
570 iwl_pcie_apm_init(trans);
571
572 /* inform ME that we are leaving */
573 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
574 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
575 APMG_PCIDEV_STT_VAL_WAKE_ME);
6e584873 576 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 577 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
578 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 579 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
580 CSR_HW_IF_CONFIG_REG_PREPARE |
581 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 582 mdelay(1);
583 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
585 }
b7aaeae4
EG		 586 mdelay(5);
587 }
588
eb7ff77e 589 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 590
591 /* Stop device's DMA activity */
7afe3705 592 iwl_pcie_apm_stop_master(trans);
cc56feb2 593
a812cba9
AB		 594 if (trans->cfg->lp_xtal_workaround) {
595 iwl_pcie_apm_lp_xtal_enable(trans);
596 return;
597 }
598
870c2a11 599 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 600
601 /*
602 * Clear "initialization complete" bit to move adapter from
603 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
604 */
605 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 606 BIT(trans->cfg->csr->flag_init_done));
cc56feb2
EG		 607}
608
7afe3705 609static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 610{
7b11488f 611 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 612 int ret;
392f8b78
EG		 613
614 /* nic_init */
7b70bd63 615 spin_lock(&trans_pcie->irq_lock);
52b6e168 616 ret = iwl_pcie_apm_init(trans);
7b70bd63 617 spin_unlock(&trans_pcie->irq_lock);
392f8b78 618
52b6e168
EG		 619 if (ret)
620 return ret;
621
95411d04 622 iwl_pcie_set_pwr(trans, false);
392f8b78 623
ecdb975c 624 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 625
626 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 627 iwl_pcie_rx_init(trans);
392f8b78
EG		 628
629 /* Allocate or reset and init all Tx and Command queues */
f02831be 630 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 631 return -ENOMEM;
632
035f7ff2 633 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 634 /* enable shadow regs in HW */
20d3b647 635 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 636 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 637 }
638
392f8b78
EG		 639 return 0;
640}
641
642#define HW_READY_TIMEOUT (50)
643
644/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 645static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 646{
647 int ret;
648
1042db2a 649 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 650 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 651
652 /* See if we got it */
1042db2a 653 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 654 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
655 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
656 HW_READY_TIMEOUT);
392f8b78 657
6a08f514
EG		 658 if (ret >= 0)
659 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
660
6d8f6eeb 661 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 662 return ret;
663}
664
665/* Note: returns standard 0/-ERROR code */
eda50cde 666int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 667{
668 int ret;
289e5501 669 int t = 0;
501fd989 670 int iter;
392f8b78 671
6d8f6eeb 672 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 673
7afe3705 674 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 675 /* If the card is ready, exit 0 */
392f8b78
EG		 676 if (ret >= 0)
677 return 0;
678
c9fdec9f
EG		 679 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
680 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 681 usleep_range(1000, 2000);
c9fdec9f 682
501fd989
EG		 683 for (iter = 0; iter < 10; iter++) {
684 /* If HW is not ready, prepare the conditions to check again */
685 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
686 CSR_HW_IF_CONFIG_REG_PREPARE);
687
688 do {
689 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 690 if (ret >= 0)
691 return 0;
392f8b78 692
501fd989
EG		 693 usleep_range(200, 1000);
694 t += 200;
695 } while (t < 150000);
696 msleep(25);
697 }
392f8b78 698
7f2ac8fb 699 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 700
392f8b78
EG		 701 return ret;
702}
703
cf614297
EG		 704/*
705 * ucode
706 */
564cdce7
SS		 707static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
708 u32 dst_addr, dma_addr_t phy_addr,
709 u32 byte_cnt)
cf614297 710{
bac842da
EG		 711 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
712 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
713
714 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
715 dst_addr);
716
717 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
718 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
719
720 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
721 (iwl_get_dma_hi_addr(phy_addr)
722 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
723
724 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
725 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
726 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
727 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
728
729 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
730 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
731 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
732 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 733}
734
564cdce7
SS		 735static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
736 u32 dst_addr, dma_addr_t phy_addr,
737 u32 byte_cnt)
738{
739 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
740 unsigned long flags;
741 int ret;
742
743 trans_pcie->ucode_write_complete = false;
744
745 if (!iwl_trans_grab_nic_access(trans, &flags))
746 return -EIO;
747
eda50cde
SS		 748 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
749 byte_cnt);
bac842da 750 iwl_trans_release_nic_access(trans, &flags);
cf614297 751
13df1aab
JB		 752 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
753 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 754 if (!ret) {
83f84d7b 755 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 756 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 757 return -ETIMEDOUT;
758 }
759
760 return 0;
761}
762
7afe3705 763static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 764 const struct fw_desc *section)
cf614297 765{
83f84d7b
JB		 766 u8 *v_addr;
767 dma_addr_t p_addr;
baa21e83 768 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 769 int ret = 0;
770
83f84d7b
JB		 771 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
772 section_num);
773
c571573a
EG		 774 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
775 GFP_KERNEL | __GFP_NOWARN);
776 if (!v_addr) {
777 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
778 chunk_sz = PAGE_SIZE;
779 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
780 &p_addr, GFP_KERNEL);
781 if (!v_addr)
782 return -ENOMEM;
783 }
83f84d7b 784
c571573a 785 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 786 u32 copy_size, dst_addr;
787 bool extended_addr = false;
83f84d7b 788
c571573a 789 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 790 dst_addr = section->offset + offset;
791
792 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
793 dst_addr <= IWL_FW_MEM_EXTENDED_END)
794 extended_addr = true;
795
796 if (extended_addr)
797 iwl_set_bits_prph(trans, LMPM_CHICK,
798 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 799
83f84d7b 800 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 801 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
802 copy_size);
803
804 if (extended_addr)
805 iwl_clear_bits_prph(trans, LMPM_CHICK,
806 LMPM_CHICK_EXTENDED_ADDR_SPACE);
807
83f84d7b
JB		 808 if (ret) {
809 IWL_ERR(trans,
810 "Could not load the [%d] uCode section\n",
811 section_num);
812 break;
6dfa8d01 813 }
83f84d7b
JB		 814 }
815
c571573a 816 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 817 return ret;
818}
819
5dd9c68a
EG		 820static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
821 const struct fw_img *image,
822 int cpu,
823 int *first_ucode_section)
e2d6f4e7
EH		 824{
825 int shift_param;
dcab8ecd
EH		 826 int i, ret = 0, sec_num = 0x1;
827 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 828
829 if (cpu == 1) {
830 shift_param = 0;
034846cf 831 *first_ucode_section = 0;
e2d6f4e7
EH		 832 } else {
833 shift_param = 16;
034846cf 834 (*first_ucode_section)++;
e2d6f4e7
EH		 835 }
836
eef187a7 837 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 838 last_read_idx = i;
839
a6c4fb44
MG		 840 /*
841 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
842 * CPU1 to CPU2.
843 * PAGING_SEPARATOR_SECTION delimiter - separate between
844 * CPU2 non paged to CPU2 paging sec.
845 */
034846cf 846 if (!image->sec[i].data ||
a6c4fb44
MG		 847 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
848 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 849 IWL_DEBUG_FW(trans,
850 "Break since Data not valid or Empty section, sec = %d\n",
851 i);
189fa2fa 852 break;
034846cf
EH		 853 }
854
189fa2fa
EH		 855 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
856 if (ret)
857 return ret;
dcab8ecd 858
d6a2c5c7 859 /* Notify ucode of loaded section number and status */
eda50cde
SS		 860 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
861 val = val | (sec_num << shift_param);
862 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
863
dcab8ecd 864 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 865 }
866
034846cf
EH		 867 *first_ucode_section = last_read_idx;
868
2aabdbdc
EG		 869 iwl_enable_interrupts(trans);
870
d6a2c5c7
SS		 871 if (trans->cfg->use_tfh) {
872 if (cpu == 1)
873 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
874 0xFFFF);
875 else
876 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
877 0xFFFFFFFF);
878 } else {
879 if (cpu == 1)
880 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
881 0xFFFF);
882 else
883 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
884 0xFFFFFFFF);
885 }
afb88917 886
189fa2fa
EH		 887 return 0;
888}
e2d6f4e7 889
189fa2fa
EH		 890static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
891 const struct fw_img *image,
034846cf
EH		 892 int cpu,
893 int *first_ucode_section)
189fa2fa 894{
189fa2fa 895 int i, ret = 0;
034846cf 896 u32 last_read_idx = 0;
189fa2fa 897
3ce4a038 898 if (cpu == 1)
034846cf 899 *first_ucode_section = 0;
3ce4a038 900 else
034846cf 901 (*first_ucode_section)++;
189fa2fa 902
eef187a7 903 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 904 last_read_idx = i;
905
a6c4fb44
MG		 906 /*
907 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
908 * CPU1 to CPU2.
909 * PAGING_SEPARATOR_SECTION delimiter - separate between
910 * CPU2 non paged to CPU2 paging sec.
911 */
034846cf 912 if (!image->sec[i].data ||
a6c4fb44
MG		 913 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
914 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 915 IWL_DEBUG_FW(trans,
916 "Break since Data not valid or Empty section, sec = %d\n",
917 i);
189fa2fa 918 break;
034846cf
EH		 919 }
920
189fa2fa
EH		 921 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
922 if (ret)
923 return ret;
e2d6f4e7
EH		 924 }
925
034846cf
EH		 926 *first_ucode_section = last_read_idx;
927
e2d6f4e7
EH		 928 return 0;
929}
930
c9be849d 931void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7
LK		 932{
933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
fd527eb5 934 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
09e350f7
LK		 935 int i;
936
09e350f7
LK		 937 IWL_INFO(trans, "Applying debug destination %s\n",
938 get_fw_dbg_mode_string(dest->monitor_mode));
939
940 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 941 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 942 else
943 IWL_WARN(trans, "PCI should have external buffer debug\n");
944
945 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
946 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
947 u32 val = le32_to_cpu(dest->reg_ops[i].val);
948
949 switch (dest->reg_ops[i].op) {
950 case CSR_ASSIGN:
951 iwl_write32(trans, addr, val);
952 break;
953 case CSR_SETBIT:
954 iwl_set_bit(trans, addr, BIT(val));
955 break;
956 case CSR_CLEARBIT:
957 iwl_clear_bit(trans, addr, BIT(val));
958 break;
959 case PRPH_ASSIGN:
960 iwl_write_prph(trans, addr, val);
961 break;
962 case PRPH_SETBIT:
963 iwl_set_bits_prph(trans, addr, BIT(val));
964 break;
965 case PRPH_CLEARBIT:
966 iwl_clear_bits_prph(trans, addr, BIT(val));
967 break;
869f3b15
HD		 968 case PRPH_BLOCKBIT:
969 if (iwl_read_prph(trans, addr) & BIT(val)) {
970 IWL_ERR(trans,
971 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
972 val, addr);
973 goto monitor;
974 }
975 break;
09e350f7
LK		 976 default:
977 IWL_ERR(trans, "FW debug - unknown OP %d\n",
978 dest->reg_ops[i].op);
979 break;
980 }
981 }
982
869f3b15 983monitor:
09e350f7
LK		 984 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
985 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
986 trans_pcie->fw_mon_phys >> dest->base_shift);
6e584873 987 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d
EG		 988 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
989 (trans_pcie->fw_mon_phys +
990 trans_pcie->fw_mon_size - 256) >>
991 dest->end_shift);
992 else
993 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
994 (trans_pcie->fw_mon_phys +
995 trans_pcie->fw_mon_size) >>
996 dest->end_shift);
09e350f7
LK		 997 }
998}
999
7afe3705 1000static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 1001 const struct fw_img *image)
cf614297 1002{
c2d20201 1003 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 1004 int ret = 0;
034846cf 1005 int first_ucode_section;
cf614297 1006
dcab8ecd 1007 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 1008 image->is_dual_cpus ? "Dual" : "Single");
1009
dcab8ecd
EH		 1010 /* load to FW the binary non secured sections of CPU1 */
1011 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1012 if (ret)
1013 return ret;
e2d6f4e7
EH		 1014
1015 if (image->is_dual_cpus) {
189fa2fa
EH		 1016 /* set CPU2 header address */
1017 iwl_write_prph(trans,
1018 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1019 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1020
189fa2fa 1021 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1022 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1023 &first_ucode_section);
189fa2fa
EH		 1024 if (ret)
1025 return ret;
e2d6f4e7 1026 }
cf614297 1027
c2d20201
EG		 1028 /* supported for 7000 only for the moment */
1029 if (iwlwifi_mod_params.fw_monitor &&
1030 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1031 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1032
1033 if (trans_pcie->fw_mon_size) {
1034 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1035 trans_pcie->fw_mon_phys >> 4);
1036 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1037 (trans_pcie->fw_mon_phys +
1038 trans_pcie->fw_mon_size) >> 4);
1039 }
09e350f7
LK		 1040 } else if (trans->dbg_dest_tlv) {
1041 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1042 }
1043
2aabdbdc
EG		 1044 iwl_enable_interrupts(trans);
1045
e12ba844 1046 /* release CPU reset */
5dd9c68a 1047 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1048
dcab8ecd
EH		 1049 return 0;
1050}
189fa2fa 1051
5dd9c68a
EG		 1052static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1053 const struct fw_img *image)
dcab8ecd
EH		 1054{
1055 int ret = 0;
1056 int first_ucode_section;
dcab8ecd
EH		 1057
1058 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1059 image->is_dual_cpus ? "Dual" : "Single");
1060
a2227ce2
EG		 1061 if (trans->dbg_dest_tlv)
1062 iwl_pcie_apply_destination(trans);
1063
82ea7966
SS		 1064 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1065 iwl_read_prph(trans, WFPM_GP2));
1066
1067 /*
1068 * Set default value. On resume reading the values that were
1069 * zeored can provide debug data on the resume flow.
1070 * This is for debugging only and has no functional impact.
1071 */
1072 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1073
dcab8ecd
EH		 1074 /* configure the ucode to be ready to get the secured image */
1075 /* release CPU reset */
1076 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1077
1078 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1079 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1080 &first_ucode_section);
dcab8ecd
EH		 1081 if (ret)
1082 return ret;
1083
1084 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1085 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1086 &first_ucode_section);
cf614297
EG		 1087}
1088
9ad8fd0b 1089bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1090{
326477e4 1091 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1092 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1093 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1094 bool report;
727c02df 1095
326477e4
JB		 1096 if (hw_rfkill) {
1097 set_bit(STATUS_RFKILL_HW, &trans->status);
1098 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1099 } else {
1100 clear_bit(STATUS_RFKILL_HW, &trans->status);
1101 if (trans_pcie->opmode_down)
1102 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1103 }
1104
1105 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1106
326477e4
JB		 1107 if (prev != report)
1108 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1109
1110 return hw_rfkill;
1111}
1112
7ca00409
HD		 1113struct iwl_causes_list {
1114 u32 cause_num;
1115 u32 mask_reg;
1116 u8 addr;
1117};
1118
1119static struct iwl_causes_list causes_list[] = {
1120 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1121 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1122 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1123 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1124 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1125 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1126 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1127 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1128 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1129 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1130 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1131 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1132 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1133 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1134};
1135
9b58419e
GBA		 1136static struct iwl_causes_list causes_list_v2[] = {
1137 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1138 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1139 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1140 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1141 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1142 {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1143 {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15},
1144 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1145 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1146 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1147 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1148 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1149 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1150 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1151};
1152
7ca00409
HD		 1153static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1154{
1155 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1156 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
9b58419e
GBA		 1157 int i, arr_size =
1158 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1159 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
7ca00409
HD		 1160
1161 /*
1162 * Access all non RX causes and map them to the default irq.
1163 * In case we are missing at least one interrupt vector,
1164 * the first interrupt vector will serve non-RX and FBQ causes.
1165 */
9b58419e
GBA		 1166 for (i = 0; i < arr_size; i++) {
1167 struct iwl_causes_list *causes =
1168 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1169 causes_list : causes_list_v2;
1170
1171 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1172 iwl_clear_bit(trans, causes[i].mask_reg,
1173 causes[i].cause_num);
7ca00409
HD		 1174 }
1175}
1176
1177static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1178{
1179 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1180 u32 offset =
1181 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1182 u32 val, idx;
1183
1184 /*
1185 * The first RX queue - fallback queue, which is designated for
1186 * management frame, command responses etc, is always mapped to the
1187 * first interrupt vector. The other RX queues are mapped to
1188 * the other (N - 2) interrupt vectors.
1189 */
1190 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1191 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1192 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1193 MSIX_FH_INT_CAUSES_Q(idx - offset));
1194 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1195 }
1196 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1197
1198 val = MSIX_FH_INT_CAUSES_Q(0);
1199 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1200 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1201 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1202
1203 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1204 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1205}
1206
77c09bc8 1207void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1208{
1209 struct iwl_trans *trans = trans_pcie->trans;
1210
1211 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1212 if (trans->cfg->mq_rx_supported &&
1213 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1214 iwl_write_prph(trans, UREG_CHICK,
1215 UREG_CHICK_MSI_ENABLE);
1216 return;
1217 }
d7270d61
HD		 1218 /*
1219 * The IVAR table needs to be configured again after reset,
1220 * but if the device is disabled, we can't write to
1221 * prph.
1222 */
1223 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1224 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1225
1226 /*
1227 * Each cause from the causes list above and the RX causes is
1228 * represented as a byte in the IVAR table. The first nibble
1229 * represents the bound interrupt vector of the cause, the second
1230 * represents no auto clear for this cause. This will be set if its
1231 * interrupt vector is bound to serve other causes.
1232 */
1233 iwl_pcie_map_rx_causes(trans);
1234
1235 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1236}
1237
1238static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1239{
1240 struct iwl_trans *trans = trans_pcie->trans;
1241
1242 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1243
83730058
HD		 1244 if (!trans_pcie->msix_enabled)
1245 return;
1246
1247 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1248 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1249 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1250 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1251}
1252
fa9f3281 1253static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1254{
43e58856 1255 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1256
fa9f3281
EG		 1257 lockdep_assert_held(&trans_pcie->mutex);
1258
1259 if (trans_pcie->is_down)
1260 return;
1261
1262 trans_pcie->is_down = true;
1263
0232d2cd
SS		 1264 /* Stop dbgc before stopping device */
1265 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1266 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1267 } else {
1268 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1269 udelay(100);
1270 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1271 }
1272
43e58856 1273 /* tell the device to stop sending interrupts */
ae2c30bf 1274 iwl_disable_interrupts(trans);
ae2c30bf 1275
ab6cf8e8 1276 /* device going down, Stop using ICT table */
990aa6d7 1277 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1278
1279 /*
1280 * If a HW restart happens during firmware loading,
1281 * then the firmware loading might call this function
1282 * and later it might be called again due to the
1283 * restart. So don't process again if the device is
1284 * already dead.
1285 */
31b8b343 1286 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1287 IWL_DEBUG_INFO(trans,
1288 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1289 iwl_pcie_tx_stop(trans);
9805c446 1290 iwl_pcie_rx_stop(trans);
6379103e 1291
ab6cf8e8 1292 /* Power-down device's busmaster DMA clocks */
95411d04 1293 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1294 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1295 APMG_CLK_VAL_DMA_CLK_RQT);
1296 udelay(5);
1297 }
ab6cf8e8
EG		 1298 }
1299
1300 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1301 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1302 BIT(trans->cfg->csr->flag_mac_access_req));
ab6cf8e8
EG		 1303
1304 /* Stop the device, and put it in low power state */
b7aaeae4 1305 iwl_pcie_apm_stop(trans, false);
43e58856 1306
870c2a11 1307 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1308
f4a1f04a
GBA		 1309 /*
1310 * Upon stop, the IVAR table gets erased, so msi-x won't
1311 * work. This causes a bug in RF-KILL flows, since the interrupt
1312 * that enables radio won't fire on the correct irq, and the
1313 * driver won't be able to handle the interrupt.
1314 * Configure the IVAR table again after reset.
1315 */
1316 iwl_pcie_conf_msix_hw(trans_pcie);
1317
03d6c3b0
EG		 1318 /*
1319 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1320 * This is a bug in certain verions of the hardware.
1321 * Certain devices also keep sending HW RF kill interrupt all
1322 * the time, unless the interrupt is ACKed even if the interrupt
1323 * should be masked. Re-ACK all the interrupts here.
43e58856 1324 */
43e58856 1325 iwl_disable_interrupts(trans);
43e58856 1326
74fda971 1327 /* clear all status bits */
eb7ff77e
AN		 1328 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1329 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1330 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1331
1332 /*
1333 * Even if we stop the HW, we still want the RF kill
1334 * interrupt
1335 */
1336 iwl_enable_rfkill_int(trans);
1337
a6bd005f 1338 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1339 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1340}
1341
eda50cde 1342void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1343{
1344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1345
1346 if (trans_pcie->msix_enabled) {
1347 int i;
1348
496d83ca 1349 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1350 synchronize_irq(trans_pcie->msix_entries[i].vector);
1351 } else {
1352 synchronize_irq(trans_pcie->pci_dev->irq);
1353 }
1354}
1355
a6bd005f
EG		 1356static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1357 const struct fw_img *fw, bool run_in_rfkill)
1358{
1359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1360 bool hw_rfkill;
1361 int ret;
1362
1363 /* This may fail if AMT took ownership of the device */
1364 if (iwl_pcie_prepare_card_hw(trans)) {
1365 IWL_WARN(trans, "Exit HW not ready\n");
1366 ret = -EIO;
1367 goto out;
1368 }
1369
1370 iwl_enable_rfkill_int(trans);
1371
1372 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1373
1374 /*
1375 * We enabled the RF-Kill interrupt and the handler may very
1376 * well be running. Disable the interrupts to make sure no other
1377 * interrupt can be fired.
1378 */
1379 iwl_disable_interrupts(trans);
1380
1381 /* Make sure it finished running */
2e5d4a8f 1382 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1383
1384 mutex_lock(&trans_pcie->mutex);
1385
1386 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1387 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1388 if (hw_rfkill && !run_in_rfkill) {
1389 ret = -ERFKILL;
1390 goto out;
1391 }
1392
1393 /* Someone called stop_device, don't try to start_fw */
1394 if (trans_pcie->is_down) {
1395 IWL_WARN(trans,
1396 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1397 ret = -EIO;
a6bd005f
EG		 1398 goto out;
1399 }
1400
1401 /* make sure rfkill handshake bits are cleared */
1402 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1403 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1404 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1405
1406 /* clear (again), then enable host interrupts */
1407 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1408
1409 ret = iwl_pcie_nic_init(trans);
1410 if (ret) {
1411 IWL_ERR(trans, "Unable to init nic\n");
1412 goto out;
1413 }
1414
1415 /*
1416 * Now, we load the firmware and don't want to be interrupted, even
1417 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1418 * FH_TX interrupt which is needed to load the firmware). If the
1419 * RF-Kill switch is toggled, we will find out after having loaded
1420 * the firmware and return the proper value to the caller.
1421 */
1422 iwl_enable_fw_load_int(trans);
1423
1424 /* really make sure rfkill handshake bits are cleared */
1425 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1426 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1427
1428 /* Load the given image to the HW */
6e584873 1429 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1430 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1431 else
1432 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1433
1434 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1435 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1436 if (hw_rfkill && !run_in_rfkill)
1437 ret = -ERFKILL;
1438
1439out:
1440 mutex_unlock(&trans_pcie->mutex);
1441 return ret;
1442}
1443
1444static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1445{
1446 iwl_pcie_reset_ict(trans);
1447 iwl_pcie_tx_start(trans, scd_addr);
1448}
1449
326477e4
JB		 1450void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1451 bool was_in_rfkill)
1452{
1453 bool hw_rfkill;
1454
1455 /*
1456 * Check again since the RF kill state may have changed while
1457 * all the interrupts were disabled, in this case we couldn't
1458 * receive the RF kill interrupt and update the state in the
1459 * op_mode.
1460 * Don't call the op_mode if the rkfill state hasn't changed.
1461 * This allows the op_mode to call stop_device from the rfkill
1462 * notification without endless recursion. Under very rare
1463 * circumstances, we might have a small recursion if the rfkill
1464 * state changed exactly now while we were called from stop_device.
1465 * This is very unlikely but can happen and is supported.
1466 */
1467 hw_rfkill = iwl_is_rfkill_set(trans);
1468 if (hw_rfkill) {
1469 set_bit(STATUS_RFKILL_HW, &trans->status);
1470 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1471 } else {
1472 clear_bit(STATUS_RFKILL_HW, &trans->status);
1473 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1474 }
1475 if (hw_rfkill != was_in_rfkill)
1476 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1477}
1478
fa9f3281
EG		 1479static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1480{
1481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1482 bool was_in_rfkill;
fa9f3281
EG		 1483
1484 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1485 trans_pcie->opmode_down = true;
1486 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
fa9f3281 1487 _iwl_trans_pcie_stop_device(trans, low_power);
326477e4 1488 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1489 mutex_unlock(&trans_pcie->mutex);
1490}
1491
14cfca71
JB		 1492void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1493{
fa9f3281
EG		 1494 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1495 IWL_TRANS_GET_PCIE_TRANS(trans);
1496
1497 lockdep_assert_held(&trans_pcie->mutex);
1498
326477e4
JB		 1499 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1500 state ? "disabled" : "enabled");
77c09bc8
SS		 1501 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1502 if (trans->cfg->gen2)
1503 _iwl_trans_pcie_gen2_stop_device(trans, true);
1504 else
1505 _iwl_trans_pcie_stop_device(trans, true);
1506 }
ab6cf8e8
EG		 1507}
1508
23ae6128
MG		 1509static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1510 bool reset)
2dd4f9f7 1511{
23ae6128 1512 if (!reset) {
6dfb36c8
EP		 1513 /* Enable persistence mode to avoid reset */
1514 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1515 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1516 }
1517
2dd4f9f7 1518 iwl_disable_interrupts(trans);
debff618
JB		 1519
1520 /*
1521 * in testing mode, the host stays awake and the
1522 * hardware won't be reset (not even partially)
1523 */
1524 if (test)
1525 return;
1526
ddaf5a5b
JB		 1527 iwl_pcie_disable_ict(trans);
1528
2e5d4a8f 1529 iwl_pcie_synchronize_irqs(trans);
33b56af1 1530
2dd4f9f7 1531 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1532 BIT(trans->cfg->csr->flag_mac_access_req));
ddaf5a5b 1533 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1534 BIT(trans->cfg->csr->flag_init_done));
ddaf5a5b 1535
1316d595
SS		 1536 iwl_pcie_enable_rx_wake(trans, false);
1537
23ae6128 1538 if (reset) {
6dfb36c8
EP		 1539 /*
1540 * reset TX queues -- some of their registers reset during S3
1541 * so if we don't reset everything here the D3 image would try
1542 * to execute some invalid memory upon resume
1543 */
1544 iwl_trans_pcie_tx_reset(trans);
1545 }
ddaf5a5b
JB		 1546
1547 iwl_pcie_set_pwr(trans, true);
1548}
1549
1550static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1551 enum iwl_d3_status *status,
23ae6128 1552 bool test, bool reset)
ddaf5a5b 1553{
d7270d61 1554 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1555 u32 val;
1556 int ret;
1557
debff618
JB		 1558 if (test) {
1559 iwl_enable_interrupts(trans);
1560 *status = IWL_D3_STATUS_ALIVE;
1561 return 0;
1562 }
1563
1316d595
SS		 1564 iwl_pcie_enable_rx_wake(trans, true);
1565
a8cbb46f
GBA		 1566 iwl_set_bit(trans, CSR_GP_CNTRL,
1567 BIT(trans->cfg->csr->flag_mac_access_req));
1568 iwl_set_bit(trans, CSR_GP_CNTRL,
1569 BIT(trans->cfg->csr->flag_init_done));
ddaf5a5b 1570
6e584873 1571 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28
EG		 1572 udelay(2);
1573
ddaf5a5b 1574 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 1575 BIT(trans->cfg->csr->flag_mac_clock_ready),
1576 BIT(trans->cfg->csr->flag_mac_clock_ready),
ddaf5a5b 1577 25000);
7f2ac8fb 1578 if (ret < 0) {
ddaf5a5b
JB		 1579 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1580 return ret;
1581 }
1582
f98ad635
EG		 1583 /*
1584 * Reconfigure IVAR table in case of MSIX or reset ict table in
1585 * MSI mode since HW reset erased it.
1586 * Also enables interrupts - none will happen as
1587 * the device doesn't know we're waking it up, only when
1588 * the opmode actually tells it after this call.
1589 */
1590 iwl_pcie_conf_msix_hw(trans_pcie);
1591 if (!trans_pcie->msix_enabled)
1592 iwl_pcie_reset_ict(trans);
1593 iwl_enable_interrupts(trans);
1594
a3ead656
EG		 1595 iwl_pcie_set_pwr(trans, false);
1596
23ae6128 1597 if (!reset) {
6dfb36c8 1598 iwl_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1599 BIT(trans->cfg->csr->flag_mac_access_req));
6dfb36c8
EP		 1600 } else {
1601 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1602
6dfb36c8
EP		 1603 ret = iwl_pcie_rx_init(trans);
1604 if (ret) {
1605 IWL_ERR(trans,
1606 "Failed to resume the device (RX reset)\n");
1607 return ret;
1608 }
ddaf5a5b
JB		 1609 }
1610
82ea7966
SS		 1611 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1612 iwl_read_prph(trans, WFPM_GP2));
1613
a3ead656
EG		 1614 val = iwl_read32(trans, CSR_RESET);
1615 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1616 *status = IWL_D3_STATUS_RESET;
1617 else
1618 *status = IWL_D3_STATUS_ALIVE;
1619
ddaf5a5b 1620 return 0;
2dd4f9f7
JB		 1621}
1622
2e5d4a8f
HD		 1623static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1624 struct iwl_trans *trans)
1625{
1626 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1627 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1628 u16 pci_cmd;
2e5d4a8f 1629
06f4b081
SS		 1630 if (!trans->cfg->mq_rx_supported)
1631 goto enable_msi;
1632
ab1068d6 1633 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1634 for (i = 0; i < max_irqs; i++)
1635 trans_pcie->msix_entries[i].entry = i;
496d83ca 1636
06f4b081
SS		 1637 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1638 MSIX_MIN_INTERRUPT_VECTORS,
1639 max_irqs);
1640 if (num_irqs < 0) {
2e5d4a8f 1641 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1642 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1643 num_irqs);
1644 goto enable_msi;
1645 }
1646 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1647
06f4b081
SS		 1648 IWL_DEBUG_INFO(trans,
1649 "MSI-X enabled. %d interrupt vectors were allocated\n",
1650 num_irqs);
1651
1652 /*
1653 * In case the OS provides fewer interrupts than requested, different
1654 * causes will share the same interrupt vector as follows:
1655 * One interrupt less: non rx causes shared with FBQ.
1656 * Two interrupts less: non rx causes shared with FBQ and RSS.
1657 * More than two interrupts: we will use fewer RSS queues.
1658 */
ab1068d6 1659 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1660 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1661 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1662 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1663 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1664 trans_pcie->trans->num_rx_queues = num_irqs;
1665 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1666 } else {
1667 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1668 }
ab1068d6 1669 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1670
06f4b081
SS		 1671 trans_pcie->alloc_vecs = num_irqs;
1672 trans_pcie->msix_enabled = true;
1673 return;
1674
1675enable_msi:
1676 ret = pci_enable_msi(pdev);
1677 if (ret) {
1678 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1679 /* enable rfkill interrupt: hw bug w/a */
1680 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1681 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1682 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1683 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1684 }
1685 }
1686}
1687
7c8d91eb
HD		 1688static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1689{
1690 int iter_rx_q, i, ret, cpu, offset;
1691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1692
1693 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1694 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1695 offset = 1 + i;
1696 for (; i < iter_rx_q ; i++) {
1697 /*
1698 * Get the cpu prior to the place to search
1699 * (i.e. return will be > i - 1).
1700 */
1701 cpu = cpumask_next(i - offset, cpu_online_mask);
1702 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1703 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1704 &trans_pcie->affinity_mask[i]);
1705 if (ret)
1706 IWL_ERR(trans_pcie->trans,
1707 "Failed to set affinity mask for IRQ %d\n",
1708 i);
1709 }
1710}
1711
2e5d4a8f
HD		 1712static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1713 struct iwl_trans_pcie *trans_pcie)
1714{
496d83ca 1715 int i;
2e5d4a8f 1716
496d83ca 1717 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1718 int ret;
5a41a86c 1719 struct msix_entry *msix_entry;
64fa3aff
SD		 1720 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1721
1722 if (!qname)
1723 return -ENOMEM;
5a41a86c
SD		 1724
1725 msix_entry = &trans_pcie->msix_entries[i];
1726 ret = devm_request_threaded_irq(&pdev->dev,
1727 msix_entry->vector,
1728 iwl_pcie_msix_isr,
1729 (i == trans_pcie->def_irq) ?
1730 iwl_pcie_irq_msix_handler :
1731 iwl_pcie_irq_rx_msix_handler,
1732 IRQF_SHARED,
64fa3aff 1733 qname,
5a41a86c 1734 msix_entry);
2e5d4a8f 1735 if (ret) {
2e5d4a8f
HD		 1736 IWL_ERR(trans_pcie->trans,
1737 "Error allocating IRQ %d\n", i);
5a41a86c 1738
2e5d4a8f
HD		 1739 return ret;
1740 }
1741 }
7c8d91eb 1742 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1743
1744 return 0;
1745}
1746
fa9f3281 1747static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1748{
fa9f3281 1749 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1750 int err;
e6bb4c9c 1751
fa9f3281
EG		 1752 lockdep_assert_held(&trans_pcie->mutex);
1753
7afe3705 1754 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1755 if (err) {
d6f1c316 1756 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1757 return err;
ebb7678d 1758 }
a6c684ee 1759
870c2a11 1760 iwl_trans_pcie_sw_reset(trans);
2997494f 1761
52b6e168
EG		 1762 err = iwl_pcie_apm_init(trans);
1763 if (err)
1764 return err;
a6c684ee 1765
2e5d4a8f 1766 iwl_pcie_init_msix(trans_pcie);
83730058 1767
226c02ca
EG		 1768 /* From now on, the op_mode will be kept updated about RF kill state */
1769 iwl_enable_rfkill_int(trans);
1770
326477e4
JB		 1771 trans_pcie->opmode_down = false;
1772
fa9f3281
EG		 1773 /* Set is_down to false here so that...*/
1774 trans_pcie->is_down = false;
1775
727c02df 1776 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1777 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1778
4cbb8e50
LC		 1779 /* Make sure we sync here, because we'll need full access later */
1780 if (low_power)
1781 pm_runtime_resume(trans->dev);
1782
a8b691e6 1783 return 0;
e6bb4c9c
EG		 1784}
1785
fa9f3281
EG		 1786static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1787{
1788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1789 int ret;
1790
1791 mutex_lock(&trans_pcie->mutex);
1792 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1793 mutex_unlock(&trans_pcie->mutex);
1794
1795 return ret;
1796}
1797
a4082843 1798static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1799{
20d3b647 1800 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1801
fa9f3281
EG		 1802 mutex_lock(&trans_pcie->mutex);
1803
a4082843 1804 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1805 iwl_disable_interrupts(trans);
ee7d737c 1806
b7aaeae4 1807 iwl_pcie_apm_stop(trans, true);
cc56feb2 1808
218733cf 1809 iwl_disable_interrupts(trans);
1df06bdc 1810
8d96bb61 1811 iwl_pcie_disable_ict(trans);
33b56af1 1812
fa9f3281 1813 mutex_unlock(&trans_pcie->mutex);
33b56af1 1814
2e5d4a8f 1815 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1816}
1817
03905495
EG		 1818static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1819{
05f5b97e 1820 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1821}
1822
1823static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1824{
05f5b97e 1825 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1826}
1827
1828static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1829{
05f5b97e 1830 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1831}
1832
6a06b6c1
EG		 1833static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1834{
f9477c17
AP		 1835 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1836 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1837 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1838}
1839
1840static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1841 u32 val)
1842{
1843 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1844 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1845 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1846}
1847
c6f600fc 1848static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1849 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1850{
1851 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1852
1853 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1854 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1855 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1856 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1857 trans_pcie->n_no_reclaim_cmds = 0;
1858 else
1859 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1860 if (trans_pcie->n_no_reclaim_cmds)
1861 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1862 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1863
6c4fbcbc
EG		 1864 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1865 trans_pcie->rx_page_order =
1866 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1867
046db346 1868 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1869 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1870 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1871
21cb3222
JB		 1872 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1873 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1874
39bdb17e
SD		 1875 trans->command_groups = trans_cfg->command_groups;
1876 trans->command_groups_size = trans_cfg->command_groups_size;
1877
f14d6b39
JB		 1878 /* Initialize NAPI here - it should be before registering to mac80211
1879 * in the opmode but after the HW struct is allocated.
1880 * As this function may be called again in some corner cases don't
1881 * do anything if NAPI was already initialized.
1882 */
bce97731 1883 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1884 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1885}
1886
d1ff5253 1887void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1888{
20d3b647 1889 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1890 int i;
a42a1844 1891
2e5d4a8f 1892 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1893
13a3a390
SS		 1894 if (trans->cfg->gen2)
1895 iwl_pcie_gen2_tx_free(trans);
1896 else
1897 iwl_pcie_tx_free(trans);
9805c446 1898 iwl_pcie_rx_free(trans);
6379103e 1899
10a54d81
LC		 1900 if (trans_pcie->rba.alloc_wq) {
1901 destroy_workqueue(trans_pcie->rba.alloc_wq);
1902 trans_pcie->rba.alloc_wq = NULL;
1903 }
1904
2e5d4a8f 1905 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1906 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1907 irq_set_affinity_hint(
1908 trans_pcie->msix_entries[i].vector,
1909 NULL);
7c8d91eb 1910 }
2e5d4a8f 1911
2e5d4a8f
HD		 1912 trans_pcie->msix_enabled = false;
1913 } else {
2e5d4a8f 1914 iwl_pcie_free_ict(trans);
2e5d4a8f 1915 }
a42a1844 1916
c2d20201
EG		 1917 iwl_pcie_free_fw_monitor(trans);
1918
6eb5e529
EG		 1919 for_each_possible_cpu(i) {
1920 struct iwl_tso_hdr_page *p =
1921 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1922
1923 if (p->page)
1924 __free_page(p->page);
1925 }
1926
1927 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1928 mutex_destroy(&trans_pcie->mutex);
7b501d10 1929 iwl_trans_free(trans);
34c1b7ba
EG		 1930}
1931
47107e84
DF		 1932static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1933{
47107e84 1934 if (state)
eb7ff77e 1935 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1936 else
eb7ff77e 1937 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1938}
1939
49564a80
LC		 1940struct iwl_trans_pcie_removal {
1941 struct pci_dev *pdev;
1942 struct work_struct work;
1943};
1944
1945static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1946{
1947 struct iwl_trans_pcie_removal *removal =
1948 container_of(wk, struct iwl_trans_pcie_removal, work);
1949 struct pci_dev *pdev = removal->pdev;
1950 char *prop[] = {"EVENT=INACCESSIBLE", NULL};
1951
1952 dev_err(&pdev->dev, "Device gone - attempting removal\n");
1953 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1954 pci_lock_rescan_remove();
1955 pci_dev_put(pdev);
1956 pci_stop_and_remove_bus_device(pdev);
1957 pci_unlock_rescan_remove();
1958
1959 kfree(removal);
1960 module_put(THIS_MODULE);
1961}
1962
23ba9340
EG		 1963static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1964 unsigned long *flags)
7a65d170
EG		 1965{
1966 int ret;
cfb4e624
JB		 1967 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1968
1969 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1970
fc8a350d 1971 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1972 goto out;
1973
7a65d170 1974 /* this bit wakes up the NIC */
e139dc4a 1975 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
a8cbb46f 1976 BIT(trans->cfg->csr->flag_mac_access_req));
6e584873 1977 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 1978 udelay(2);
7a65d170
EG		 1979
1980 /*
1981 * These bits say the device is running, and should keep running for
1982 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1983 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 1984 * HW with volatile SRAM must save/restore contents to/from
1985 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 1986 * Each direction takes approximately 1/4 millisecond; with this
1987 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1988 * series of register accesses are expected (e.g. reading Event Log),
1989 * to keep device from sleeping.
1990 *
1991 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1992 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 1993 * is just for hardware register access; but GP1 MAC_SLEEP
1994 * check is a good idea before accessing the SRAM of HW with
1995 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 1996 *
1997 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1998 * and do not save/restore SRAM when power cycling.
1999 */
2000 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 2001 BIT(trans->cfg->csr->flag_val_mac_access_en),
2002 (BIT(trans->cfg->csr->flag_mac_clock_ready) |
7a65d170
EG		 2003 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2004 if (unlikely(ret < 0)) {
49564a80
LC		 2005 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2006
23ba9340
EG		 2007 WARN_ONCE(1,
2008 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2009 cntrl);
2010
2011 iwl_trans_pcie_dump_regs(trans);
2012
2013 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2014 struct iwl_trans_pcie_removal *removal;
2015
2016 if (trans_pcie->scheduled_for_removal)
2017 goto err;
2018
2019 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2020
2021 /*
2022 * get a module reference to avoid doing this
2023 * while unloading anyway and to avoid
2024 * scheduling a work with code that's being
2025 * removed.
2026 */
2027 if (!try_module_get(THIS_MODULE)) {
2028 IWL_ERR(trans,
2029 "Module is being unloaded - abort\n");
2030 goto err;
2031 }
2032
2033 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2034 if (!removal) {
2035 module_put(THIS_MODULE);
2036 goto err;
2037 }
2038 /*
2039 * we don't need to clear this flag, because
2040 * the trans will be freed and reallocated.
2041 */
2042 trans_pcie->scheduled_for_removal = true;
2043
2044 removal->pdev = to_pci_dev(trans->dev);
2045 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2046 pci_dev_get(removal->pdev);
2047 schedule_work(&removal->work);
2048 } else {
2049 iwl_write32(trans, CSR_RESET,
2050 CSR_RESET_REG_FLAG_FORCE_NMI);
2051 }
2052
2053err:
23ba9340
EG		 2054 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2055 return false;
7a65d170
EG		 2056 }
2057
b9439491 2058out:
e56b04ef
LE		 2059 /*
2060 * Fool sparse by faking we release the lock - sparse will
2061 * track nic_access anyway.
2062 */
cfb4e624 2063 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2064 return true;
2065}
2066
e56b04ef
LE		 2067static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2068 unsigned long *flags)
7a65d170 2069{
cfb4e624 2070 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2071
cfb4e624 2072 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2073
2074 /*
2075 * Fool sparse by faking we acquiring the lock - sparse will
2076 * track nic_access anyway.
2077 */
cfb4e624 2078 __acquire(&trans_pcie->reg_lock);
e56b04ef 2079
fc8a350d 2080 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2081 goto out;
2082
e139dc4a 2083 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
a8cbb46f 2084 BIT(trans->cfg->csr->flag_mac_access_req));
7a65d170
EG		 2085 /*
2086 * Above we read the CSR_GP_CNTRL register, which will flush
2087 * any previous writes, but we need the write that clears the
2088 * MAC_ACCESS_REQ bit to be performed before any other writes
2089 * scheduled on different CPUs (after we drop reg_lock).
2090 */
2091 mmiowb();
b9439491 2092out:
cfb4e624 2093 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 2094}
2095
4fd442db
EG		 2096static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2097 void *buf, int dwords)
2098{
2099 unsigned long flags;
2100 int offs, ret = 0;
2101 u32 *vals = buf;
2102
23ba9340 2103 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2104 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2105 for (offs = 0; offs < dwords; offs++)
2106 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 2107 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2108 } else {
2109 ret = -EBUSY;
2110 }
4fd442db
EG		 2111 return ret;
2112}
2113
2114static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2115 const void *buf, int dwords)
4fd442db
EG		 2116{
2117 unsigned long flags;
2118 int offs, ret = 0;
bf0fd5da 2119 const u32 *vals = buf;
4fd442db 2120
23ba9340 2121 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2122 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2123 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2124 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2125 vals ? vals[offs] : 0);
e56b04ef 2126 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2127 } else {
2128 ret = -EBUSY;
2129 }
4fd442db
EG		 2130 return ret;
2131}
7a65d170 2132
e0b8d405
EG		 2133static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2134 unsigned long txqs,
2135 bool freeze)
2136{
2137 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2138 int queue;
2139
2140 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 2141 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 2142 unsigned long now;
2143
2144 spin_lock_bh(&txq->lock);
2145
2146 now = jiffies;
2147
2148 if (txq->frozen == freeze)
2149 goto next_queue;
2150
2151 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2152 freeze ? "Freezing" : "Waking", queue);
2153
2154 txq->frozen = freeze;
2155
bb98ecd4 2156 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2157 goto next_queue;
2158
2159 if (freeze) {
2160 if (unlikely(time_after(now,
2161 txq->stuck_timer.expires))) {
2162 /*
2163 * The timer should have fired, maybe it is
2164 * spinning right now on the lock.
2165 */
2166 goto next_queue;
2167 }
2168 /* remember how long until the timer fires */
2169 txq->frozen_expiry_remainder =
2170 txq->stuck_timer.expires - now;
2171 del_timer(&txq->stuck_timer);
2172 goto next_queue;
2173 }
2174
2175 /*
2176 * Wake a non-empty queue -> arm timer with the
2177 * remainder before it froze
2178 */
2179 mod_timer(&txq->stuck_timer,
2180 now + txq->frozen_expiry_remainder);
2181
2182next_queue:
2183 spin_unlock_bh(&txq->lock);
2184 }
2185}
2186
0cd58eaa
EG		 2187static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2188{
2189 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2190 int i;
2191
2192 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 2193 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 2194
2195 if (i == trans_pcie->cmd_queue)
2196 continue;
2197
2198 spin_lock_bh(&txq->lock);
2199
2200 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2201 txq->block--;
2202 if (!txq->block) {
2203 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2204 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2205 }
2206 } else if (block) {
2207 txq->block++;
2208 }
2209
2210 spin_unlock_bh(&txq->lock);
2211 }
2212}
2213
5f178cd2
EG		 2214#define IWL_FLUSH_WAIT_MS 2000
2215
38398efb
SS		 2216void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2217{
afb84431
EG		 2218 u32 txq_id = txq->id;
2219 u32 status;
2220 bool active;
2221 u8 fifo;
38398efb 2222
afb84431
EG		 2223 if (trans->cfg->use_tfh) {
2224 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2225 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2226 /* TODO: access new SCD registers and dump them */
2227 return;
38398efb 2228 }
afb84431
EG		 2229
2230 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2231 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2232 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2233
2234 IWL_ERR(trans,
2235 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2236 txq_id, active ? "" : "in", fifo,
2237 jiffies_to_msecs(txq->wd_timeout),
2238 txq->read_ptr, txq->write_ptr,
2239 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
7b3e42ea 2240 (trans->cfg->base_params->max_tfd_queue_size - 1),
afb84431 2241 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
7b3e42ea 2242 (trans->cfg->base_params->max_tfd_queue_size - 1),
afb84431 2243 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2244}
2245
92536c96
SS		 2246static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2247 struct iwl_trans_rxq_dma_data *data)
2248{
2249 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2250
2251 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2252 return -EINVAL;
2253
2254 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2255 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2256 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2257 data->fr_bd_wid = 0;
2258
2259 return 0;
2260}
2261
d6d517b7 2262static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2263{
8ad71bef 2264 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2265 struct iwl_txq *txq;
5f178cd2 2266 unsigned long now = jiffies;
d6d517b7
SS		 2267 u8 wr_ptr;
2268
2269 if (!test_bit(txq_idx, trans_pcie->queue_used))
2270 return -EINVAL;
2271
2272 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2273 txq = trans_pcie->txq[txq_idx];
6aa7de05 2274 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2275
6aa7de05 2276 while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
d6d517b7
SS		 2277 !time_after(jiffies,
2278 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2279 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7
SS		 2280
2281 if (WARN_ONCE(wr_ptr != write_ptr,
2282 "WR pointer moved while flushing %d -> %d\n",
2283 wr_ptr, write_ptr))
2284 return -ETIMEDOUT;
2285 usleep_range(1000, 2000);
2286 }
2287
2288 if (txq->read_ptr != txq->write_ptr) {
2289 IWL_ERR(trans,
2290 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2291 iwl_trans_pcie_log_scd_error(trans, txq);
2292 return -ETIMEDOUT;
2293 }
2294
2295 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2296
2297 return 0;
2298}
2299
2300static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2301{
2302 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2303 int cnt;
5f178cd2
EG		 2304 int ret = 0;
2305
2306 /* waiting for all the tx frames complete might take a while */
035f7ff2 2307 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd 2308
9ba1947a 2309 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2310 continue;
3cafdbe6
EG		 2311 if (!test_bit(cnt, trans_pcie->queue_used))
2312 continue;
2313 if (!(BIT(cnt) & txq_bm))
2314 continue;
748fa67c 2315
d6d517b7
SS		 2316 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2317 if (ret)
5f178cd2 2318 break;
5f178cd2 2319 }
1c3fea82 2320
5f178cd2
EG		 2321 return ret;
2322}
2323
e139dc4a
LE		 2324static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2325 u32 mask, u32 value)
2326{
e56b04ef 2327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2328 unsigned long flags;
2329
e56b04ef 2330 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2331 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2332 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2333}
2334
c24c7f58 2335static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2336{
2337 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2338
2339 if (iwlwifi_mod_params.d0i3_disable)
2340 return;
2341
b3ff1270 2342 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2343
2344#ifdef CONFIG_PM
2345 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2346 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2347#endif /* CONFIG_PM */
7616f334
EP		 2348}
2349
c24c7f58 2350static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2351{
2352 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2353
2354 if (iwlwifi_mod_params.d0i3_disable)
2355 return;
2356
b3ff1270
LC		 2357 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2358 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2359
5d93f3a2
LC		 2360#ifdef CONFIG_PM
2361 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2362 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2363#endif /* CONFIG_PM */
7616f334
EP		 2364}
2365
ff620849
EG		 2366static const char *get_csr_string(int cmd)
2367{
d9fb6465 2368#define IWL_CMD(x) case x: return #x
ff620849
EG		 2369 switch (cmd) {
2370 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2371 IWL_CMD(CSR_INT_COALESCING);
2372 IWL_CMD(CSR_INT);
2373 IWL_CMD(CSR_INT_MASK);
2374 IWL_CMD(CSR_FH_INT_STATUS);
2375 IWL_CMD(CSR_GPIO_IN);
2376 IWL_CMD(CSR_RESET);
2377 IWL_CMD(CSR_GP_CNTRL);
2378 IWL_CMD(CSR_HW_REV);
2379 IWL_CMD(CSR_EEPROM_REG);
2380 IWL_CMD(CSR_EEPROM_GP);
2381 IWL_CMD(CSR_OTP_GP_REG);
2382 IWL_CMD(CSR_GIO_REG);
2383 IWL_CMD(CSR_GP_UCODE_REG);
2384 IWL_CMD(CSR_GP_DRIVER_REG);
2385 IWL_CMD(CSR_UCODE_DRV_GP1);
2386 IWL_CMD(CSR_UCODE_DRV_GP2);
2387 IWL_CMD(CSR_LED_REG);
2388 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2389 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2390 IWL_CMD(CSR_ANA_PLL_CFG);
2391 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2392 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2393 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2394 default:
2395 return "UNKNOWN";
2396 }
d9fb6465 2397#undef IWL_CMD
ff620849
EG		 2398}
2399
990aa6d7 2400void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2401{
2402 int i;
2403 static const u32 csr_tbl[] = {
2404 CSR_HW_IF_CONFIG_REG,
2405 CSR_INT_COALESCING,
2406 CSR_INT,
2407 CSR_INT_MASK,
2408 CSR_FH_INT_STATUS,
2409 CSR_GPIO_IN,
2410 CSR_RESET,
2411 CSR_GP_CNTRL,
2412 CSR_HW_REV,
2413 CSR_EEPROM_REG,
2414 CSR_EEPROM_GP,
2415 CSR_OTP_GP_REG,
2416 CSR_GIO_REG,
2417 CSR_GP_UCODE_REG,
2418 CSR_GP_DRIVER_REG,
2419 CSR_UCODE_DRV_GP1,
2420 CSR_UCODE_DRV_GP2,
2421 CSR_LED_REG,
2422 CSR_DRAM_INT_TBL_REG,
2423 CSR_GIO_CHICKEN_BITS,
2424 CSR_ANA_PLL_CFG,
a812cba9 2425 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2426 CSR_HW_REV_WA_REG,
2427 CSR_DBG_HPET_MEM_REG
2428 };
2429 IWL_ERR(trans, "CSR values:\n");
2430 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2431 "CSR_INT_PERIODIC_REG)\n");
2432 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2433 IWL_ERR(trans, " %25s: 0X%08x\n",
2434 get_csr_string(csr_tbl[i]),
1042db2a 2435 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2436 }
2437}
2438
87e5666c
EG		 2439#ifdef CONFIG_IWLWIFI_DEBUGFS
2440/* create and remove of files */
2441#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2442 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2443 &iwl_dbgfs_##name##_ops)) \
9da987ac 2444 goto err; \
87e5666c
EG		 2445} while (0)
2446
2447/* file operation */
87e5666c 2448#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2449static const struct file_operations iwl_dbgfs_##name##_ops = { \
2450 .read = iwl_dbgfs_##name##_read, \
234e3405 2451 .open = simple_open, \
87e5666c
EG		 2452 .llseek = generic_file_llseek, \
2453};
2454
16db88ba 2455#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2456static const struct file_operations iwl_dbgfs_##name##_ops = { \
2457 .write = iwl_dbgfs_##name##_write, \
234e3405 2458 .open = simple_open, \
16db88ba
EG		 2459 .llseek = generic_file_llseek, \
2460};
2461
87e5666c 2462#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2463static const struct file_operations iwl_dbgfs_##name##_ops = { \
2464 .write = iwl_dbgfs_##name##_write, \
2465 .read = iwl_dbgfs_##name##_read, \
234e3405 2466 .open = simple_open, \
87e5666c
EG		 2467 .llseek = generic_file_llseek, \
2468};
2469
87e5666c 2470static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2471 char __user *user_buf,
2472 size_t count, loff_t *ppos)
8ad71bef 2473{
5a878bf6 2474 struct iwl_trans *trans = file->private_data;
8ad71bef 2475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2476 struct iwl_txq *txq;
87e5666c
EG		 2477 char *buf;
2478 int pos = 0;
2479 int cnt;
2480 int ret;
1745e440
WYG		 2481 size_t bufsz;
2482
e0b8d405 2483 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2484
b2a3b1c1 2485 if (!trans_pcie->txq_memory)
87e5666c 2486 return -EAGAIN;
f9e75447 2487
87e5666c
EG		 2488 buf = kzalloc(bufsz, GFP_KERNEL);
2489 if (!buf)
2490 return -ENOMEM;
2491
035f7ff2 2492 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2493 txq = trans_pcie->txq[cnt];
87e5666c 2494 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2495 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2496 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2497 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2498 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2499 txq->need_update, txq->frozen,
f40faf62 2500 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2501 }
2502 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2503 kfree(buf);
2504 return ret;
2505}
2506
2507static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2508 char __user *user_buf,
2509 size_t count, loff_t *ppos)
2510{
5a878bf6 2511 struct iwl_trans *trans = file->private_data;
20d3b647 2512 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2513 char *buf;
2514 int pos = 0, i, ret;
2515 size_t bufsz = sizeof(buf);
2516
2517 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2518
2519 if (!trans_pcie->rxq)
2520 return -EAGAIN;
2521
2522 buf = kzalloc(bufsz, GFP_KERNEL);
2523 if (!buf)
2524 return -ENOMEM;
2525
2526 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2527 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2528
2529 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2530 i);
2531 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2532 rxq->read);
2533 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2534 rxq->write);
2535 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2536 rxq->write_actual);
2537 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2538 rxq->need_update);
2539 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2540 rxq->free_count);
2541 if (rxq->rb_stts) {
0307c839
GBA		 2542 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2543 rxq));
78485054
SS		 2544 pos += scnprintf(buf + pos, bufsz - pos,
2545 "\tclosed_rb_num: %u\n",
0307c839 2546 r & 0x0FFF);
78485054
SS		 2547 } else {
2548 pos += scnprintf(buf + pos, bufsz - pos,
2549 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2550 }
87e5666c 2551 }
78485054
SS		 2552 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2553 kfree(buf);
2554
2555 return ret;
87e5666c
EG		 2556}
2557
1f7b6172
EG		 2558static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2559 char __user *user_buf,
20d3b647
JB		 2560 size_t count, loff_t *ppos)
2561{
1f7b6172 2562 struct iwl_trans *trans = file->private_data;
20d3b647 2563 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2564 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2565
2566 int pos = 0;
2567 char *buf;
2568 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2569 ssize_t ret;
2570
2571 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2572 if (!buf)
1f7b6172 2573 return -ENOMEM;
1f7b6172
EG		 2574
2575 pos += scnprintf(buf + pos, bufsz - pos,
2576 "Interrupt Statistics Report:\n");
2577
2578 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2579 isr_stats->hw);
2580 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2581 isr_stats->sw);
2582 if (isr_stats->sw || isr_stats->hw) {
2583 pos += scnprintf(buf + pos, bufsz - pos,
2584 "\tLast Restarting Code: 0x%X\n",
2585 isr_stats->err_code);
2586 }
2587#ifdef CONFIG_IWLWIFI_DEBUG
2588 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2589 isr_stats->sch);
2590 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2591 isr_stats->alive);
2592#endif
2593 pos += scnprintf(buf + pos, bufsz - pos,
2594 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2595
2596 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2597 isr_stats->ctkill);
2598
2599 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2600 isr_stats->wakeup);
2601
2602 pos += scnprintf(buf + pos, bufsz - pos,
2603 "Rx command responses:\t\t %u\n", isr_stats->rx);
2604
2605 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2606 isr_stats->tx);
2607
2608 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2609 isr_stats->unhandled);
2610
2611 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2612 kfree(buf);
2613 return ret;
2614}
2615
2616static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2617 const char __user *user_buf,
2618 size_t count, loff_t *ppos)
2619{
2620 struct iwl_trans *trans = file->private_data;
20d3b647 2621 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2622 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2623 u32 reset_flag;
078f1131 2624 int ret;
1f7b6172 2625
078f1131
JB		 2626 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2627 if (ret)
2628 return ret;
1f7b6172
EG		 2629 if (reset_flag == 0)
2630 memset(isr_stats, 0, sizeof(*isr_stats));
2631
2632 return count;
2633}
2634
16db88ba 2635static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2636 const char __user *user_buf,
2637 size_t count, loff_t *ppos)
16db88ba
EG		 2638{
2639 struct iwl_trans *trans = file->private_data;
16db88ba 2640
990aa6d7 2641 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2642
2643 return count;
2644}
2645
16db88ba 2646static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2647 char __user *user_buf,
2648 size_t count, loff_t *ppos)
16db88ba
EG		 2649{
2650 struct iwl_trans *trans = file->private_data;
94543a8d 2651 char *buf = NULL;
56c2477f 2652 ssize_t ret;
16db88ba 2653
56c2477f
JB		 2654 ret = iwl_dump_fh(trans, &buf);
2655 if (ret < 0)
2656 return ret;
2657 if (!buf)
2658 return -EINVAL;
2659 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2660 kfree(buf);
16db88ba
EG		 2661 return ret;
2662}
2663
fa4de7f7
JB		 2664static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2665 char __user *user_buf,
2666 size_t count, loff_t *ppos)
2667{
2668 struct iwl_trans *trans = file->private_data;
2669 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2670 char buf[100];
2671 int pos;
2672
2673 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2674 trans_pcie->debug_rfkill,
2675 !(iwl_read32(trans, CSR_GP_CNTRL) &
2676 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2677
2678 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2679}
2680
2681static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2682 const char __user *user_buf,
2683 size_t count, loff_t *ppos)
2684{
2685 struct iwl_trans *trans = file->private_data;
2686 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2687 bool old = trans_pcie->debug_rfkill;
2688 int ret;
2689
2690 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2691 if (ret)
2692 return ret;
2693 if (old == trans_pcie->debug_rfkill)
2694 return count;
2695 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2696 old, trans_pcie->debug_rfkill);
2697 iwl_pcie_handle_rfkill_irq(trans);
2698
2699 return count;
2700}
2701
1f7b6172 2702DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2703DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2704DEBUGFS_READ_FILE_OPS(rx_queue);
2705DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2706DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2707DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
87e5666c 2708
f8a1edb7
JB		 2709/* Create the debugfs files and directories */
2710int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2711{
f8a1edb7
JB		 2712 struct dentry *dir = trans->dbgfs_dir;
2713
2ef00c53
JP		 2714 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2715 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2716 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2717 DEBUGFS_ADD_FILE(csr, dir, 0200);
2718 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2719 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
87e5666c 2720 return 0;
9da987ac
MV		 2721
2722err:
2723 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2724 return -ENOMEM;
87e5666c 2725}
aadede6e 2726#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2727
6983ba69 2728static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2729{
3cd1980b 2730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2731 u32 cmdlen = 0;
2732 int i;
2733
3cd1980b 2734 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2735 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2736
2737 return cmdlen;
2738}
2739
bd7fc617
EG		 2740static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2741 struct iwl_fw_error_dump_data **data,
2742 int allocated_rb_nums)
2743{
2744 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2745 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2746 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2747 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2748 u32 i, r, j, rb_len = 0;
2749
2750 spin_lock(&rxq->lock);
2751
0307c839 2752 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2753
2754 for (i = rxq->read, j = 0;
2755 i != r && j < allocated_rb_nums;
2756 i = (i + 1) & RX_QUEUE_MASK, j++) {
2757 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2758 struct iwl_fw_error_dump_rb *rb;
2759
2760 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2761 DMA_FROM_DEVICE);
2762
2763 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2764
2765 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2766 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2767 rb = (void *)(*data)->data;
2768 rb->index = cpu_to_le32(i);
2769 memcpy(rb->data, page_address(rxb->page), max_len);
2770 /* remap the page for the free benefit */
2771 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2772 max_len,
2773 DMA_FROM_DEVICE);
2774
2775 *data = iwl_fw_error_next_data(*data);
2776 }
2777
2778 spin_unlock(&rxq->lock);
2779
2780 return rb_len;
2781}
473ad712
EG		 2782#define IWL_CSR_TO_DUMP (0x250)
2783
2784static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2785 struct iwl_fw_error_dump_data **data)
2786{
2787 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2788 __le32 *val;
2789 int i;
2790
2791 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2792 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2793 val = (void *)(*data)->data;
2794
2795 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2796 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2797
2798 *data = iwl_fw_error_next_data(*data);
2799
2800 return csr_len;
2801}
2802
06d51e0d
LK		 2803static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2804 struct iwl_fw_error_dump_data **data)
2805{
2806 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2807 unsigned long flags;
2808 __le32 *val;
2809 int i;
2810
23ba9340 2811 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2812 return 0;
2813
2814 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2815 (*data)->len = cpu_to_le32(fh_regs_len);
2816 val = (void *)(*data)->data;
2817
723b45e2
LK		 2818 if (!trans->cfg->gen2)
2819 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2820 i += sizeof(u32))
2821 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2822 else
2823 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2824 i += sizeof(u32))
2825 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2826 i));
06d51e0d
LK		 2827
2828 iwl_trans_release_nic_access(trans, &flags);
2829
2830 *data = iwl_fw_error_next_data(*data);
2831
2832 return sizeof(**data) + fh_regs_len;
2833}
2834
cc79ef66
LK		 2835static u32
2836iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2837 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2838 u32 monitor_len)
2839{
2840 u32 buf_size_in_dwords = (monitor_len >> 2);
2841 u32 *buffer = (u32 *)fw_mon_data->data;
2842 unsigned long flags;
2843 u32 i;
2844
23ba9340 2845 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2846 return 0;
2847
14ef1b43 2848 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2849 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2850 buffer[i] = iwl_read_prph_no_grab(trans,
2851 MON_DMARB_RD_DATA_ADDR);
2852 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2853
2854 iwl_trans_release_nic_access(trans, &flags);
2855
2856 return monitor_len;
2857}
2858
36fb9017
OG		 2859static u32
2860iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2861 struct iwl_fw_error_dump_data **data,
2862 u32 monitor_len)
2863{
2864 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2865 u32 len = 0;
2866
2867 if ((trans_pcie->fw_mon_page &&
2868 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2869 trans->dbg_dest_tlv) {
2870 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2871 u32 base, write_ptr, wrap_cnt;
2872
2873 /* If there was a dest TLV - use the values from there */
2874 if (trans->dbg_dest_tlv) {
2875 write_ptr =
2876 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2877 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2878 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2879 } else {
2880 base = MON_BUFF_BASE_ADDR;
2881 write_ptr = MON_BUFF_WRPTR;
2882 wrap_cnt = MON_BUFF_CYCLE_CNT;
2883 }
2884
2885 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2886 fw_mon_data = (void *)(*data)->data;
2887 fw_mon_data->fw_mon_wr_ptr =
2888 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2889 fw_mon_data->fw_mon_cycle_cnt =
2890 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2891 fw_mon_data->fw_mon_base_ptr =
2892 cpu_to_le32(iwl_read_prph(trans, base));
2893
2894 len += sizeof(**data) + sizeof(*fw_mon_data);
2895 if (trans_pcie->fw_mon_page) {
2896 /*
2897 * The firmware is now asserted, it won't write anything
2898 * to the buffer. CPU can take ownership to fetch the
2899 * data. The buffer will be handed back to the device
2900 * before the firmware will be restarted.
2901 */
2902 dma_sync_single_for_cpu(trans->dev,
2903 trans_pcie->fw_mon_phys,
2904 trans_pcie->fw_mon_size,
2905 DMA_FROM_DEVICE);
2906 memcpy(fw_mon_data->data,
2907 page_address(trans_pcie->fw_mon_page),
2908 trans_pcie->fw_mon_size);
2909
2910 monitor_len = trans_pcie->fw_mon_size;
2911 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2912 /*
2913 * Update pointers to reflect actual values after
2914 * shifting
2915 */
fd527eb5
GBA		 2916 if (trans->dbg_dest_tlv->version) {
2917 base = (iwl_read_prph(trans, base) &
2918 IWL_LDBG_M2S_BUF_BA_MSK) <<
2919 trans->dbg_dest_tlv->base_shift;
2920 base *= IWL_M2S_UNIT_SIZE;
2921 base += trans->cfg->smem_offset;
2922 } else {
2923 base = iwl_read_prph(trans, base) <<
2924 trans->dbg_dest_tlv->base_shift;
2925 }
2926
36fb9017
OG		 2927 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2928 monitor_len / sizeof(u32));
2929 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2930 monitor_len =
2931 iwl_trans_pci_dump_marbh_monitor(trans,
2932 fw_mon_data,
2933 monitor_len);
2934 } else {
2935 /* Didn't match anything - output no monitor data */
2936 monitor_len = 0;
2937 }
2938
2939 len += monitor_len;
2940 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2941 }
2942
2943 return len;
2944}
2945
2946static struct iwl_trans_dump_data
2947*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2948 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2949{
2950 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2951 struct iwl_fw_error_dump_data *data;
b2a3b1c1 2952 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
4d075007 2953 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2954 struct iwl_trans_dump_data *dump_data;
514c3069 2955 u32 len, num_rbs = 0;
99684ae3 2956 u32 monitor_len;
4d075007 2957 int i, ptr;
96a6497b 2958 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
520f03ea
SM		 2959 !trans->cfg->mq_rx_supported &&
2960 trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
4d075007 2961
473ad712
EG		 2962 /* transport dump header */
2963 len = sizeof(*dump_data);
2964
2965 /* host commands */
2966 len += sizeof(*data) +
bb98ecd4 2967 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2968
473ad712 2969 /* FW monitor */
99684ae3 2970 if (trans_pcie->fw_mon_page) {
c544e9c4 2971 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2972 trans_pcie->fw_mon_size;
2973 monitor_len = trans_pcie->fw_mon_size;
2974 } else if (trans->dbg_dest_tlv) {
fd527eb5 2975 u32 base, end, cfg_reg;
99684ae3 2976
fd527eb5
GBA		 2977 if (trans->dbg_dest_tlv->version == 1) {
2978 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2979 cfg_reg = iwl_read_prph(trans, cfg_reg);
2980 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
2981 trans->dbg_dest_tlv->base_shift;
2982 base *= IWL_M2S_UNIT_SIZE;
2983 base += trans->cfg->smem_offset;
99684ae3 2984
fd527eb5
GBA		 2985 monitor_len =
2986 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
2987 trans->dbg_dest_tlv->end_shift;
2988 monitor_len *= IWL_M2S_UNIT_SIZE;
2989 } else {
2990 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2991 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
99684ae3 2992
fd527eb5
GBA		 2993 base = iwl_read_prph(trans, base) <<
2994 trans->dbg_dest_tlv->base_shift;
2995 end = iwl_read_prph(trans, end) <<
2996 trans->dbg_dest_tlv->end_shift;
2997
2998 /* Make "end" point to the actual end */
2999 if (trans->cfg->device_family >=
3000 IWL_DEVICE_FAMILY_8000 ||
3001 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
3002 end += (1 << trans->dbg_dest_tlv->end_shift);
3003 monitor_len = end - base;
3004 }
99684ae3
LK		 3005 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
3006 monitor_len;
3007 } else {
3008 monitor_len = 0;
3009 }
c2d20201 3010
36fb9017 3011 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
520f03ea
SM		 3012 if (!(trans->dbg_dump_mask &
3013 BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)))
3014 return NULL;
3015
36fb9017
OG		 3016 dump_data = vzalloc(len);
3017 if (!dump_data)
3018 return NULL;
3019
3020 data = (void *)dump_data->data;
3021 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3022 dump_data->len = len;
3023
3024 return dump_data;
3025 }
3026
3027 /* CSR registers */
520f03ea
SM		 3028 if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3029 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3030
36fb9017 3031 /* FH registers */
520f03ea
SM		 3032 if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3033 if (trans->cfg->gen2)
3034 len += sizeof(*data) +
3035 (FH_MEM_UPPER_BOUND_GEN2 -
3036 FH_MEM_LOWER_BOUND_GEN2);
3037 else
3038 len += sizeof(*data) +
3039 (FH_MEM_UPPER_BOUND -
3040 FH_MEM_LOWER_BOUND);
3041 }
36fb9017
OG		 3042
3043 if (dump_rbs) {
78485054
SS		 3044 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3045 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3046 /* RBs */
0307c839
GBA		 3047 num_rbs =
3048 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3049 & 0x0FFF;
78485054 3050 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3051 len += num_rbs * (sizeof(*data) +
3052 sizeof(struct iwl_fw_error_dump_rb) +
3053 (PAGE_SIZE << trans_pcie->rx_page_order));
3054 }
3055
5538409b 3056 /* Paged memory for gen2 HW */
520f03ea
SM		 3057 if (trans->cfg->gen2 &&
3058 trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
5538409b
LK		 3059 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
3060 len += sizeof(*data) +
3061 sizeof(struct iwl_fw_error_dump_paging) +
3062 trans_pcie->init_dram.paging[i].size;
3063
48eb7b34
EG		 3064 dump_data = vzalloc(len);
3065 if (!dump_data)
3066 return NULL;
4d075007
JB		 3067
3068 len = 0;
48eb7b34 3069 data = (void *)dump_data->data;
520f03ea
SM		 3070
3071 if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) {
3072 u16 tfd_size = trans_pcie->tfd_size;
3073
3074 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3075 txcmd = (void *)data->data;
3076 spin_lock_bh(&cmdq->lock);
3077 ptr = cmdq->write_ptr;
3078 for (i = 0; i < cmdq->n_window; i++) {
3079 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3080 u32 caplen, cmdlen;
3081
3082 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3083 cmdq->tfds +
3084 tfd_size * ptr);
3085 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3086
3087 if (cmdlen) {
3088 len += sizeof(*txcmd) + caplen;
3089 txcmd->cmdlen = cpu_to_le32(cmdlen);
3090 txcmd->caplen = cpu_to_le32(caplen);
3091 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3092 caplen);
3093 txcmd = (void *)((u8 *)txcmd->data + caplen);
3094 }
3095
3096 ptr = iwl_queue_dec_wrap(trans, ptr);
4d075007 3097 }
520f03ea 3098 spin_unlock_bh(&cmdq->lock);
4d075007 3099
520f03ea
SM		 3100 data->len = cpu_to_le32(len);
3101 len += sizeof(*data);
3102 data = iwl_fw_error_next_data(data);
4d075007 3103 }
67c65f2c 3104
520f03ea
SM		 3105 if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3106 len += iwl_trans_pcie_dump_csr(trans, &data);
3107 if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3108 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3109 if (dump_rbs)
3110 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3111
5538409b 3112 /* Paged memory for gen2 HW */
520f03ea
SM		 3113 if (trans->cfg->gen2 &&
3114 trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
5538409b
LK		 3115 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
3116 struct iwl_fw_error_dump_paging *paging;
3117 dma_addr_t addr =
3118 trans_pcie->init_dram.paging[i].physical;
3119 u32 page_len = trans_pcie->init_dram.paging[i].size;
3120
3121 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3122 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3123 paging = (void *)data->data;
3124 paging->index = cpu_to_le32(i);
3125 dma_sync_single_for_cpu(trans->dev, addr, page_len,
3126 DMA_BIDIRECTIONAL);
3127 memcpy(paging->data,
3128 trans_pcie->init_dram.paging[i].block, page_len);
3129 data = iwl_fw_error_next_data(data);
3130
3131 len += sizeof(*data) + sizeof(*paging) + page_len;
3132 }
3133 }
520f03ea
SM		 3134 if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3135 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3136
48eb7b34
EG		 3137 dump_data->len = len;
3138
3139 return dump_data;
4d075007 3140}
87e5666c 3141
4cbb8e50
LC		 3142#ifdef CONFIG_PM_SLEEP
3143static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3144{
e4c49c49
LC		 3145 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3146 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3147 return iwl_pci_fw_enter_d0i3(trans);
3148
3149 return 0;
3150}
3151
3152static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3153{
e4c49c49
LC		 3154 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3155 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 3156 iwl_pci_fw_exit_d0i3(trans);
3157}
3158#endif /* CONFIG_PM_SLEEP */
3159
623e7766
SS		 3160#define IWL_TRANS_COMMON_OPS \
3161 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3162 .write8 = iwl_trans_pcie_write8, \
3163 .write32 = iwl_trans_pcie_write32, \
3164 .read32 = iwl_trans_pcie_read32, \
3165 .read_prph = iwl_trans_pcie_read_prph, \
3166 .write_prph = iwl_trans_pcie_write_prph, \
3167 .read_mem = iwl_trans_pcie_read_mem, \
3168 .write_mem = iwl_trans_pcie_write_mem, \
3169 .configure = iwl_trans_pcie_configure, \
3170 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3171 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3172 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3173 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3174 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3175 .ref = iwl_trans_pcie_ref, \
3176 .unref = iwl_trans_pcie_unref, \
3177 .dump_data = iwl_trans_pcie_dump_data, \
623e7766
SS		 3178 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3179 .d3_resume = iwl_trans_pcie_d3_resume
3180
3181#ifdef CONFIG_PM_SLEEP
3182#define IWL_TRANS_PM_OPS \
3183 .suspend = iwl_trans_pcie_suspend, \
3184 .resume = iwl_trans_pcie_resume,
3185#else
3186#define IWL_TRANS_PM_OPS
3187#endif /* CONFIG_PM_SLEEP */
3188
d1ff5253 3189static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3190 IWL_TRANS_COMMON_OPS,
3191 IWL_TRANS_PM_OPS
57a1dc89 3192 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3193 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3194 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3195 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3196
623e7766 3197 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3198
623e7766
SS		 3199 .tx = iwl_trans_pcie_tx,
3200 .reclaim = iwl_trans_pcie_reclaim,
3201
3202 .txq_disable = iwl_trans_pcie_txq_disable,
3203 .txq_enable = iwl_trans_pcie_txq_enable,
3204
3205 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3206
d6d517b7
SS		 3207 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3208
623e7766
SS		 3209 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3210 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3211};
3212
3213static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3214 IWL_TRANS_COMMON_OPS,
3215 IWL_TRANS_PM_OPS
3216 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3217 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3218 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3219 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3220
ca60da2e 3221 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3222
ab6c6445 3223 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 3224 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 3225
6b35ff91
SS		 3226 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3227 .txq_free = iwl_trans_pcie_dyn_txq_free,
d6d517b7 3228 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3229 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
e6bb4c9c 3230};
a42a1844 3231
87ce05a2 3232struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 3233 const struct pci_device_id *ent,
3234 const struct iwl_cfg *cfg)
a42a1844 3235{
a42a1844
EG		 3236 struct iwl_trans_pcie *trans_pcie;
3237 struct iwl_trans *trans;
96a6497b 3238 int ret, addr_size;
a42a1844 3239
5a41a86c
SD		 3240 ret = pcim_enable_device(pdev);
3241 if (ret)
3242 return ERR_PTR(ret);
3243
623e7766
SS		 3244 if (cfg->gen2)
3245 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3246 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3247 else
3248 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3249 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 3250 if (!trans)
3251 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3252
3253 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3254
a42a1844 3255 trans_pcie->trans = trans;
326477e4 3256 trans_pcie->opmode_down = true;
7b11488f 3257 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3258 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 3259 mutex_init(&trans_pcie->mutex);
13df1aab 3260 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 3261 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3262 if (!trans_pcie->tso_hdr_page) {
3263 ret = -ENOMEM;
3264 goto out_no_pci;
3265 }
a42a1844 3266
d819c6cf 3267
f2532b04
EG		 3268 if (!cfg->base_params->pcie_l1_allowed) {
3269 /*
3270 * W/A - seems to solve weird behavior. We need to remove this
3271 * if we don't want to stay in L1 all the time. This wastes a
3272 * lot of power.
3273 */
3274 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3275 PCIE_LINK_STATE_L1 |
3276 PCIE_LINK_STATE_CLKPM);
3277 }
a42a1844 3278
6983ba69 3279 if (cfg->use_tfh) {
2c6262b7 3280 addr_size = 64;
3cd1980b 3281 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 3282 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 3283 } else {
2c6262b7 3284 addr_size = 36;
3cd1980b 3285 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 3286 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3287 }
3cd1980b
SS		 3288 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3289
a42a1844
EG		 3290 pci_set_master(pdev);
3291
96a6497b 3292 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3293 if (!ret)
96a6497b
SS		 3294 ret = pci_set_consistent_dma_mask(pdev,
3295 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3296 if (ret) {
3297 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3298 if (!ret)
3299 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3300 DMA_BIT_MASK(32));
a42a1844 3301 /* both attempts failed: */
af3f2f74 3302 if (ret) {
6a4b09f8 3303 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3304 goto out_no_pci;
a42a1844
EG		 3305 }
3306 }
3307
5a41a86c 3308 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3309 if (ret) {
5a41a86c
SD		 3310 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3311 goto out_no_pci;
a42a1844
EG		 3312 }
3313
5a41a86c 3314 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3315 if (!trans_pcie->hw_base) {
5a41a86c 3316 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3317 ret = -ENODEV;
5a41a86c 3318 goto out_no_pci;
a42a1844
EG		 3319 }
3320
a42a1844
EG		 3321 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3322 * PCI Tx retries from interfering with C3 CPU state */
3323 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3324
83f7a85f
EG		 3325 trans_pcie->pci_dev = pdev;
3326 iwl_disable_interrupts(trans);
3327
08079a49 3328 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3329 /*
3330 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3331 * changed, and now the revision step also includes bit 0-1 (no more
3332 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3333 * in the old format.
3334 */
6e584873 3335 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
7a42baa6 3336 unsigned long flags;
7a42baa6 3337
b513ee7f 3338 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3339 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3340
f9e5554c
EG		 3341 ret = iwl_pcie_prepare_card_hw(trans);
3342 if (ret) {
3343 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3344 goto out_no_pci;
f9e5554c
EG		 3345 }
3346
7a42baa6
EH		 3347 /*
3348 * in-order to recognize C step driver should read chip version
3349 * id located at the AUX bus MISC address space.
3350 */
3351 iwl_set_bit(trans, CSR_GP_CNTRL,
a8cbb46f 3352 BIT(trans->cfg->csr->flag_init_done));
7a42baa6
EH		 3353 udelay(2);
3354
3355 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
a8cbb46f
GBA		 3356 BIT(trans->cfg->csr->flag_mac_clock_ready),
3357 BIT(trans->cfg->csr->flag_mac_clock_ready),
7a42baa6
EH		 3358 25000);
3359 if (ret < 0) {
3360 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3361 goto out_no_pci;
7a42baa6
EH		 3362 }
3363
23ba9340 3364 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3365 u32 hw_step;
3366
14ef1b43 3367 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3368 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3369 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3370 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3371 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3372 if (hw_step == 0x3)
3373 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3374 (SILICON_C_STEP << 2);
3375 iwl_trans_release_nic_access(trans, &flags);
3376 }
3377 }
3378
c00ee467
JB		 3379 /*
3380 * 9000-series integrated A-step has a problem with suspend/resume
3381 * and sometimes even causes the whole platform to get stuck. This
3382 * workaround makes the hardware not go into the problematic state.
3383 */
3384 if (trans->cfg->integrated &&
3385 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3386 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3387 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3388 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3389
f6586b69 3390#if IS_ENABLED(CONFIG_IWLMVM)
1afb0ae4 3391 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
33708052
LC		 3392
3393 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3394 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
f6586b69
TP		 3395 u32 hw_status;
3396
3397 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
33708052
LC		 3398 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP)
3399 /*
3400 * b step fw is the same for physical card and fpga
3401 */
3402 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
3403 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) &&
3404 CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) {
3405 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0;
3406 } else {
3407 /*
3408 * a step no FPGA
3409 */
2f7a3863 3410 trans->cfg = &iwl22000_2ac_cfg_hr;
33708052 3411 }
f6586b69
TP		 3412 }
3413#endif
1afb0ae4 3414
2e5d4a8f 3415 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3416 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3417 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3418 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3419
69a10b29 3420 /* Initialize the wait queue for commands */
f946b529 3421 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3422
4cbb8e50
LC		 3423 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3424
2e5d4a8f 3425 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3426 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3427 if (ret)
5a41a86c 3428 goto out_no_pci;
2e5d4a8f
HD		 3429 } else {
3430 ret = iwl_pcie_alloc_ict(trans);
3431 if (ret)
5a41a86c 3432 goto out_no_pci;
a8b691e6 3433
5a41a86c
SD		 3434 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3435 iwl_pcie_isr,
3436 iwl_pcie_irq_handler,
3437 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3438 if (ret) {
3439 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3440 goto out_free_ict;
3441 }
3442 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3443 }
83f7a85f 3444
10a54d81
LC		 3445 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3446 WQ_HIGHPRI | WQ_UNBOUND, 1);
3447 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3448
b3ff1270
LC		 3449#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3450 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3451#else
3452 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3453#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3454
a42a1844
EG		 3455 return trans;
3456
a8b691e6
JB		 3457out_free_ict:
3458 iwl_pcie_free_ict(trans);
a42a1844 3459out_no_pci:
6eb5e529 3460 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3461 iwl_trans_free(trans);
af3f2f74 3462 return ERR_PTR(ret);
a42a1844 3463}
Linux 6.x block layer and io_uring tree(s)