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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
26d535ae | 4 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
bce97731 | 5 | * Copyright(c) 2016 Intel Deutschland GmbH |
ab697a9f EG |
6 | * |
7 | * Portions of this file are derived from the ipw3945 project, as well | |
8 | * as portions of the ieee80211 subsystem header files. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
22 | * | |
23 | * The full GNU General Public License is included in this distribution in the | |
24 | * file called LICENSE. | |
25 | * | |
26 | * Contact Information: | |
d01c5366 | 27 | * Intel Linux Wireless <linuxwifi@intel.com> |
ab697a9f EG |
28 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
29 | * | |
30 | *****************************************************************************/ | |
31 | #include <linux/sched.h> | |
32 | #include <linux/wait.h> | |
1a361cd8 | 33 | #include <linux/gfp.h> |
ab697a9f | 34 | |
1b29dc94 | 35 | #include "iwl-prph.h" |
ab697a9f | 36 | #include "iwl-io.h" |
6468a01a | 37 | #include "internal.h" |
db70f290 | 38 | #include "iwl-op-mode.h" |
ab697a9f EG |
39 | |
40 | /****************************************************************************** | |
41 | * | |
42 | * RX path functions | |
43 | * | |
44 | ******************************************************************************/ | |
45 | ||
46 | /* | |
47 | * Rx theory of operation | |
48 | * | |
49 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
50 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
51 | * used not only for Rx frames, but for any command response or notification | |
52 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
53 | * of indexes into the circular buffer. | |
54 | * | |
55 | * Rx Queue Indexes | |
56 | * The host/firmware share two index registers for managing the Rx buffers. | |
57 | * | |
58 | * The READ index maps to the first position that the firmware may be writing | |
59 | * to -- the driver can read up to (but not including) this position and get | |
60 | * good data. | |
61 | * The READ index is managed by the firmware once the card is enabled. | |
62 | * | |
63 | * The WRITE index maps to the last position the driver has read from -- the | |
64 | * position preceding WRITE is the last slot the firmware can place a packet. | |
65 | * | |
66 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
67 | * WRITE = READ. | |
68 | * | |
69 | * During initialization, the host sets up the READ queue position to the first | |
70 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
71 | * | |
72 | * When the firmware places a packet in a buffer, it will advance the READ index | |
73 | * and fire the RX interrupt. The driver can then query the READ index and | |
74 | * process as many packets as possible, moving the WRITE index forward as it | |
75 | * resets the Rx queue buffers with new memory. | |
76 | * | |
77 | * The management in the driver is as follows: | |
26d535ae SS |
78 | * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. |
79 | * When the interrupt handler is called, the request is processed. | |
80 | * The page is either stolen - transferred to the upper layer | |
81 | * or reused - added immediately to the iwl->rxq->rx_free list. | |
82 | * + When the page is stolen - the driver updates the matching queue's used | |
83 | * count, detaches the RBD and transfers it to the queue used list. | |
84 | * When there are two used RBDs - they are transferred to the allocator empty | |
85 | * list. Work is then scheduled for the allocator to start allocating | |
86 | * eight buffers. | |
87 | * When there are another 6 used RBDs - they are transferred to the allocator | |
88 | * empty list and the driver tries to claim the pre-allocated buffers and | |
89 | * add them to iwl->rxq->rx_free. If it fails - it continues to claim them | |
90 | * until ready. | |
91 | * When there are 8+ buffers in the free list - either from allocation or from | |
92 | * 8 reused unstolen pages - restock is called to update the FW and indexes. | |
93 | * + In order to make sure the allocator always has RBDs to use for allocation | |
94 | * the allocator has initial pool in the size of num_queues*(8-2) - the | |
95 | * maximum missing RBDs per allocation request (request posted with 2 | |
96 | * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). | |
97 | * The queues supplies the recycle of the rest of the RBDs. | |
ab697a9f EG |
98 | * + A received packet is processed and handed to the kernel network stack, |
99 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
26d535ae | 100 | * + If there are no allocated buffers in iwl->rxq->rx_free, |
2bfb5092 JB |
101 | * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. |
102 | * If there were enough free buffers and RX_STALLED is set it is cleared. | |
ab697a9f EG |
103 | * |
104 | * | |
105 | * Driver sequence: | |
106 | * | |
990aa6d7 EG |
107 | * iwl_rxq_alloc() Allocates rx_free |
108 | * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
26d535ae SS |
109 | * iwl_pcie_rxq_restock. |
110 | * Used only during initialization. | |
990aa6d7 | 111 | * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx |
ab697a9f | 112 | * queue, updates firmware pointers, and updates |
26d535ae SS |
113 | * the WRITE index. |
114 | * iwl_pcie_rx_allocator() Background work for allocating pages. | |
ab697a9f EG |
115 | * |
116 | * -- enable interrupts -- | |
990aa6d7 | 117 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the |
ab697a9f EG |
118 | * READ INDEX, detaching the SKB from the pool. |
119 | * Moves the packet buffer from queue to rx_used. | |
26d535ae | 120 | * Posts and claims requests to the allocator. |
990aa6d7 | 121 | * Calls iwl_pcie_rxq_restock to refill any empty |
ab697a9f | 122 | * slots. |
26d535ae SS |
123 | * |
124 | * RBD life-cycle: | |
125 | * | |
126 | * Init: | |
127 | * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue | |
128 | * | |
129 | * Regular Receive interrupt: | |
130 | * Page Stolen: | |
131 | * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> | |
132 | * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue | |
133 | * Page not Stolen: | |
134 | * rxq.queue -> rxq.rx_free -> rxq.queue | |
ab697a9f EG |
135 | * ... |
136 | * | |
137 | */ | |
138 | ||
990aa6d7 EG |
139 | /* |
140 | * iwl_rxq_space - Return number of free slots available in queue. | |
ab697a9f | 141 | */ |
fecba09e | 142 | static int iwl_rxq_space(const struct iwl_rxq *rxq) |
ab697a9f | 143 | { |
96a6497b SS |
144 | /* Make sure rx queue size is a power of 2 */ |
145 | WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); | |
fecba09e | 146 | |
351746c9 IY |
147 | /* |
148 | * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity | |
149 | * between empty and completely full queues. | |
150 | * The following is equivalent to modulo by RX_QUEUE_SIZE and is well | |
151 | * defined for negative dividends. | |
152 | */ | |
96a6497b | 153 | return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); |
ab697a9f EG |
154 | } |
155 | ||
9805c446 EG |
156 | /* |
157 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
158 | */ | |
159 | static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) | |
160 | { | |
161 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
162 | } | |
163 | ||
96a6497b SS |
164 | static void iwl_pcie_write_prph_64(struct iwl_trans *trans, u64 ofs, u64 val) |
165 | { | |
166 | iwl_write_prph(trans, ofs, val & 0xffffffff); | |
167 | iwl_write_prph(trans, ofs + 4, val >> 32); | |
168 | } | |
169 | ||
49bd072d EG |
170 | /* |
171 | * iwl_pcie_rx_stop - stops the Rx DMA | |
172 | */ | |
9805c446 EG |
173 | int iwl_pcie_rx_stop(struct iwl_trans *trans) |
174 | { | |
9805c446 EG |
175 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
176 | return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, | |
177 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
178 | } | |
179 | ||
990aa6d7 EG |
180 | /* |
181 | * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue | |
ab697a9f | 182 | */ |
78485054 SS |
183 | static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, |
184 | struct iwl_rxq *rxq) | |
ab697a9f | 185 | { |
ab697a9f EG |
186 | u32 reg; |
187 | ||
5d63f926 | 188 | lockdep_assert_held(&rxq->lock); |
ab697a9f | 189 | |
5045388c EP |
190 | /* |
191 | * explicitly wake up the NIC if: | |
192 | * 1. shadow registers aren't enabled | |
193 | * 2. there is a chance that the NIC is asleep | |
194 | */ | |
195 | if (!trans->cfg->base_params->shadow_reg_enable && | |
196 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
197 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); | |
198 | ||
199 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
200 | IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", | |
201 | reg); | |
202 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
203 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
5d63f926 JB |
204 | rxq->need_update = true; |
205 | return; | |
ab697a9f EG |
206 | } |
207 | } | |
5045388c EP |
208 | |
209 | rxq->write_actual = round_down(rxq->write, 8); | |
96a6497b SS |
210 | if (trans->cfg->mq_rx_supported) |
211 | iwl_write_prph(trans, RFH_Q_FRBDCB_WIDX(rxq->id), | |
212 | rxq->write_actual); | |
0f851bbc SS |
213 | /* |
214 | * write to FH_RSCSR_CHNL0_WPTR register even in MQ as a W/A to | |
215 | * hardware shadow registers bug - writing to RFH_Q_FRBDCB_WIDX will | |
216 | * not wake the NIC. | |
217 | */ | |
218 | iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); | |
5d63f926 JB |
219 | } |
220 | ||
221 | static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) | |
222 | { | |
223 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
78485054 | 224 | int i; |
5d63f926 | 225 | |
78485054 SS |
226 | for (i = 0; i < trans->num_rx_queues; i++) { |
227 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
ab697a9f | 228 | |
78485054 SS |
229 | if (!rxq->need_update) |
230 | continue; | |
231 | spin_lock(&rxq->lock); | |
232 | iwl_pcie_rxq_inc_wr_ptr(trans, rxq); | |
233 | rxq->need_update = false; | |
234 | spin_unlock(&rxq->lock); | |
235 | } | |
ab697a9f EG |
236 | } |
237 | ||
e0e168dc GG |
238 | /* |
239 | * iwl_pcie_rxq_mq_restock - restock implementation for multi-queue rx | |
240 | */ | |
96a6497b SS |
241 | static void iwl_pcie_rxq_mq_restock(struct iwl_trans *trans, |
242 | struct iwl_rxq *rxq) | |
243 | { | |
244 | struct iwl_rx_mem_buffer *rxb; | |
245 | ||
246 | /* | |
247 | * If the device isn't enabled - no need to try to add buffers... | |
248 | * This can happen when we stop the device and still have an interrupt | |
249 | * pending. We stop the APM before we sync the interrupts because we | |
250 | * have to (see comment there). On the other hand, since the APM is | |
251 | * stopped, we cannot access the HW (in particular not prph). | |
252 | * So don't try to restock if the APM has been already stopped. | |
253 | */ | |
254 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
255 | return; | |
256 | ||
257 | spin_lock(&rxq->lock); | |
258 | while (rxq->free_count) { | |
259 | __le64 *bd = (__le64 *)rxq->bd; | |
260 | ||
261 | /* Get next free Rx buffer, remove from free list */ | |
262 | rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, | |
263 | list); | |
264 | list_del(&rxb->list); | |
265 | ||
266 | /* 12 first bits are expected to be empty */ | |
267 | WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); | |
268 | /* Point to Rx buffer via next RBD in circular buffer */ | |
269 | bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); | |
270 | rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; | |
271 | rxq->free_count--; | |
272 | } | |
273 | spin_unlock(&rxq->lock); | |
274 | ||
275 | /* | |
276 | * If we've added more space for the firmware to place data, tell it. | |
277 | * Increment device's write pointer in multiples of 8. | |
278 | */ | |
279 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
280 | spin_lock(&rxq->lock); | |
281 | iwl_pcie_rxq_inc_wr_ptr(trans, rxq); | |
282 | spin_unlock(&rxq->lock); | |
283 | } | |
284 | } | |
285 | ||
990aa6d7 | 286 | /* |
e0e168dc | 287 | * iwl_pcie_rxq_sq_restock - restock implementation for single queue rx |
ab697a9f | 288 | */ |
e0e168dc GG |
289 | static void iwl_pcie_rxq_sq_restock(struct iwl_trans *trans, |
290 | struct iwl_rxq *rxq) | |
ab697a9f | 291 | { |
ab697a9f | 292 | struct iwl_rx_mem_buffer *rxb; |
ab697a9f | 293 | |
7439046d EG |
294 | /* |
295 | * If the device isn't enabled - not need to try to add buffers... | |
296 | * This can happen when we stop the device and still have an interrupt | |
2bfb5092 JB |
297 | * pending. We stop the APM before we sync the interrupts because we |
298 | * have to (see comment there). On the other hand, since the APM is | |
299 | * stopped, we cannot access the HW (in particular not prph). | |
7439046d EG |
300 | * So don't try to restock if the APM has been already stopped. |
301 | */ | |
eb7ff77e | 302 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) |
7439046d EG |
303 | return; |
304 | ||
51232f7e | 305 | spin_lock(&rxq->lock); |
990aa6d7 | 306 | while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { |
96a6497b | 307 | __le32 *bd = (__le32 *)rxq->bd; |
ab697a9f EG |
308 | /* The overwritten rxb must be a used one */ |
309 | rxb = rxq->queue[rxq->write]; | |
310 | BUG_ON(rxb && rxb->page); | |
311 | ||
312 | /* Get next free Rx buffer, remove from free list */ | |
e2b1930e JB |
313 | rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, |
314 | list); | |
315 | list_del(&rxb->list); | |
ab697a9f EG |
316 | |
317 | /* Point to Rx buffer via next RBD in circular buffer */ | |
96a6497b | 318 | bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); |
ab697a9f EG |
319 | rxq->queue[rxq->write] = rxb; |
320 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
321 | rxq->free_count--; | |
322 | } | |
51232f7e | 323 | spin_unlock(&rxq->lock); |
ab697a9f | 324 | |
ab697a9f EG |
325 | /* If we've added more space for the firmware to place data, tell it. |
326 | * Increment device's write pointer in multiples of 8. */ | |
327 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
51232f7e | 328 | spin_lock(&rxq->lock); |
78485054 | 329 | iwl_pcie_rxq_inc_wr_ptr(trans, rxq); |
51232f7e | 330 | spin_unlock(&rxq->lock); |
ab697a9f EG |
331 | } |
332 | } | |
333 | ||
e0e168dc GG |
334 | /* |
335 | * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool | |
336 | * | |
337 | * If there are slots in the RX queue that need to be restocked, | |
338 | * and we have free pre-allocated buffers, fill the ranks as much | |
339 | * as we can, pulling from rx_free. | |
340 | * | |
341 | * This moves the 'write' index forward to catch up with 'processed', and | |
342 | * also updates the memory address in the firmware to reference the new | |
343 | * target buffer. | |
344 | */ | |
345 | static | |
346 | void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) | |
347 | { | |
348 | if (trans->cfg->mq_rx_supported) | |
349 | iwl_pcie_rxq_mq_restock(trans, rxq); | |
350 | else | |
351 | iwl_pcie_rxq_sq_restock(trans, rxq); | |
352 | } | |
353 | ||
26d535ae SS |
354 | /* |
355 | * iwl_pcie_rx_alloc_page - allocates and returns a page. | |
356 | * | |
357 | */ | |
358 | static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, | |
359 | gfp_t priority) | |
360 | { | |
361 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
26d535ae SS |
362 | struct page *page; |
363 | gfp_t gfp_mask = priority; | |
364 | ||
26d535ae SS |
365 | if (trans_pcie->rx_page_order > 0) |
366 | gfp_mask |= __GFP_COMP; | |
367 | ||
368 | /* Alloc a new receive buffer */ | |
369 | page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); | |
370 | if (!page) { | |
371 | if (net_ratelimit()) | |
372 | IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", | |
373 | trans_pcie->rx_page_order); | |
78485054 SS |
374 | /* |
375 | * Issue an error if we don't have enough pre-allocated | |
376 | * buffers. | |
26d535ae | 377 | ` */ |
78485054 | 378 | if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) |
26d535ae | 379 | IWL_CRIT(trans, |
78485054 | 380 | "Failed to alloc_pages\n"); |
26d535ae SS |
381 | return NULL; |
382 | } | |
383 | return page; | |
384 | } | |
385 | ||
358a46d4 | 386 | /* |
9805c446 | 387 | * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD |
ab697a9f | 388 | * |
358a46d4 EG |
389 | * A used RBD is an Rx buffer that has been given to the stack. To use it again |
390 | * a page must be allocated and the RBD must point to the page. This function | |
391 | * doesn't change the HW pointer but handles the list of pages that is used by | |
990aa6d7 | 392 | * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly |
358a46d4 | 393 | * allocated buffers. |
ab697a9f | 394 | */ |
78485054 SS |
395 | static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, |
396 | struct iwl_rxq *rxq) | |
ab697a9f | 397 | { |
20d3b647 | 398 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab697a9f EG |
399 | struct iwl_rx_mem_buffer *rxb; |
400 | struct page *page; | |
ab697a9f EG |
401 | |
402 | while (1) { | |
51232f7e | 403 | spin_lock(&rxq->lock); |
ab697a9f | 404 | if (list_empty(&rxq->rx_used)) { |
51232f7e | 405 | spin_unlock(&rxq->lock); |
ab697a9f EG |
406 | return; |
407 | } | |
51232f7e | 408 | spin_unlock(&rxq->lock); |
ab697a9f | 409 | |
ab697a9f | 410 | /* Alloc a new receive buffer */ |
26d535ae SS |
411 | page = iwl_pcie_rx_alloc_page(trans, priority); |
412 | if (!page) | |
ab697a9f | 413 | return; |
ab697a9f | 414 | |
51232f7e | 415 | spin_lock(&rxq->lock); |
ab697a9f EG |
416 | |
417 | if (list_empty(&rxq->rx_used)) { | |
51232f7e | 418 | spin_unlock(&rxq->lock); |
b2cf410c | 419 | __free_pages(page, trans_pcie->rx_page_order); |
ab697a9f EG |
420 | return; |
421 | } | |
e2b1930e JB |
422 | rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, |
423 | list); | |
424 | list_del(&rxb->list); | |
51232f7e | 425 | spin_unlock(&rxq->lock); |
ab697a9f EG |
426 | |
427 | BUG_ON(rxb->page); | |
428 | rxb->page = page; | |
429 | /* Get physical address of the RB */ | |
20d3b647 JB |
430 | rxb->page_dma = |
431 | dma_map_page(trans->dev, page, 0, | |
432 | PAGE_SIZE << trans_pcie->rx_page_order, | |
433 | DMA_FROM_DEVICE); | |
7c341582 JB |
434 | if (dma_mapping_error(trans->dev, rxb->page_dma)) { |
435 | rxb->page = NULL; | |
51232f7e | 436 | spin_lock(&rxq->lock); |
7c341582 | 437 | list_add(&rxb->list, &rxq->rx_used); |
51232f7e | 438 | spin_unlock(&rxq->lock); |
7c341582 JB |
439 | __free_pages(page, trans_pcie->rx_page_order); |
440 | return; | |
441 | } | |
ab697a9f | 442 | |
51232f7e | 443 | spin_lock(&rxq->lock); |
ab697a9f EG |
444 | |
445 | list_add_tail(&rxb->list, &rxq->rx_free); | |
446 | rxq->free_count++; | |
447 | ||
51232f7e | 448 | spin_unlock(&rxq->lock); |
ab697a9f EG |
449 | } |
450 | } | |
451 | ||
78485054 | 452 | static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) |
9805c446 EG |
453 | { |
454 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
9805c446 EG |
455 | int i; |
456 | ||
7b542436 | 457 | for (i = 0; i < RX_POOL_SIZE; i++) { |
78485054 | 458 | if (!trans_pcie->rx_pool[i].page) |
c7df1f4b | 459 | continue; |
78485054 | 460 | dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, |
c7df1f4b JB |
461 | PAGE_SIZE << trans_pcie->rx_page_order, |
462 | DMA_FROM_DEVICE); | |
78485054 SS |
463 | __free_pages(trans_pcie->rx_pool[i].page, |
464 | trans_pcie->rx_page_order); | |
465 | trans_pcie->rx_pool[i].page = NULL; | |
9805c446 EG |
466 | } |
467 | } | |
468 | ||
26d535ae SS |
469 | /* |
470 | * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues | |
471 | * | |
472 | * Allocates for each received request 8 pages | |
473 | * Called as a scheduled work item. | |
474 | */ | |
475 | static void iwl_pcie_rx_allocator(struct iwl_trans *trans) | |
476 | { | |
477 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
478 | struct iwl_rb_allocator *rba = &trans_pcie->rba; | |
479 | struct list_head local_empty; | |
480 | int pending = atomic_xchg(&rba->req_pending, 0); | |
481 | ||
482 | IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); | |
483 | ||
484 | /* If we were scheduled - there is at least one request */ | |
485 | spin_lock(&rba->lock); | |
486 | /* swap out the rba->rbd_empty to a local list */ | |
487 | list_replace_init(&rba->rbd_empty, &local_empty); | |
488 | spin_unlock(&rba->lock); | |
489 | ||
490 | while (pending) { | |
491 | int i; | |
492 | struct list_head local_allocated; | |
78485054 SS |
493 | gfp_t gfp_mask = GFP_KERNEL; |
494 | ||
495 | /* Do not post a warning if there are only a few requests */ | |
496 | if (pending < RX_PENDING_WATERMARK) | |
497 | gfp_mask |= __GFP_NOWARN; | |
26d535ae SS |
498 | |
499 | INIT_LIST_HEAD(&local_allocated); | |
500 | ||
501 | for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { | |
502 | struct iwl_rx_mem_buffer *rxb; | |
503 | struct page *page; | |
504 | ||
505 | /* List should never be empty - each reused RBD is | |
506 | * returned to the list, and initial pool covers any | |
507 | * possible gap between the time the page is allocated | |
508 | * to the time the RBD is added. | |
509 | */ | |
510 | BUG_ON(list_empty(&local_empty)); | |
511 | /* Get the first rxb from the rbd list */ | |
512 | rxb = list_first_entry(&local_empty, | |
513 | struct iwl_rx_mem_buffer, list); | |
514 | BUG_ON(rxb->page); | |
515 | ||
516 | /* Alloc a new receive buffer */ | |
78485054 | 517 | page = iwl_pcie_rx_alloc_page(trans, gfp_mask); |
26d535ae SS |
518 | if (!page) |
519 | continue; | |
520 | rxb->page = page; | |
521 | ||
522 | /* Get physical address of the RB */ | |
523 | rxb->page_dma = dma_map_page(trans->dev, page, 0, | |
524 | PAGE_SIZE << trans_pcie->rx_page_order, | |
525 | DMA_FROM_DEVICE); | |
526 | if (dma_mapping_error(trans->dev, rxb->page_dma)) { | |
527 | rxb->page = NULL; | |
528 | __free_pages(page, trans_pcie->rx_page_order); | |
529 | continue; | |
530 | } | |
26d535ae SS |
531 | |
532 | /* move the allocated entry to the out list */ | |
533 | list_move(&rxb->list, &local_allocated); | |
534 | i++; | |
535 | } | |
536 | ||
537 | pending--; | |
538 | if (!pending) { | |
539 | pending = atomic_xchg(&rba->req_pending, 0); | |
540 | IWL_DEBUG_RX(trans, | |
541 | "Pending allocation requests = %d\n", | |
542 | pending); | |
543 | } | |
544 | ||
545 | spin_lock(&rba->lock); | |
546 | /* add the allocated rbds to the allocator allocated list */ | |
547 | list_splice_tail(&local_allocated, &rba->rbd_allocated); | |
548 | /* get more empty RBDs for current pending requests */ | |
549 | list_splice_tail_init(&rba->rbd_empty, &local_empty); | |
550 | spin_unlock(&rba->lock); | |
551 | ||
552 | atomic_inc(&rba->req_ready); | |
553 | } | |
554 | ||
555 | spin_lock(&rba->lock); | |
556 | /* return unused rbds to the allocator empty list */ | |
557 | list_splice_tail(&local_empty, &rba->rbd_empty); | |
558 | spin_unlock(&rba->lock); | |
559 | } | |
560 | ||
561 | /* | |
d56daea4 | 562 | * iwl_pcie_rx_allocator_get - returns the pre-allocated pages |
26d535ae SS |
563 | .* |
564 | .* Called by queue when the queue posted allocation request and | |
565 | * has freed 8 RBDs in order to restock itself. | |
d56daea4 SS |
566 | * This function directly moves the allocated RBs to the queue's ownership |
567 | * and updates the relevant counters. | |
26d535ae | 568 | */ |
d56daea4 SS |
569 | static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, |
570 | struct iwl_rxq *rxq) | |
26d535ae SS |
571 | { |
572 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
573 | struct iwl_rb_allocator *rba = &trans_pcie->rba; | |
574 | int i; | |
575 | ||
d56daea4 SS |
576 | lockdep_assert_held(&rxq->lock); |
577 | ||
26d535ae SS |
578 | /* |
579 | * atomic_dec_if_positive returns req_ready - 1 for any scenario. | |
580 | * If req_ready is 0 atomic_dec_if_positive will return -1 and this | |
d56daea4 | 581 | * function will return early, as there are no ready requests. |
26d535ae SS |
582 | * atomic_dec_if_positive will perofrm the *actual* decrement only if |
583 | * req_ready > 0, i.e. - there are ready requests and the function | |
584 | * hands one request to the caller. | |
585 | */ | |
586 | if (atomic_dec_if_positive(&rba->req_ready) < 0) | |
d56daea4 | 587 | return; |
26d535ae SS |
588 | |
589 | spin_lock(&rba->lock); | |
590 | for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { | |
591 | /* Get next free Rx buffer, remove it from free list */ | |
d56daea4 SS |
592 | struct iwl_rx_mem_buffer *rxb = |
593 | list_first_entry(&rba->rbd_allocated, | |
594 | struct iwl_rx_mem_buffer, list); | |
595 | ||
596 | list_move(&rxb->list, &rxq->rx_free); | |
26d535ae SS |
597 | } |
598 | spin_unlock(&rba->lock); | |
599 | ||
d56daea4 SS |
600 | rxq->used_count -= RX_CLAIM_REQ_ALLOC; |
601 | rxq->free_count += RX_CLAIM_REQ_ALLOC; | |
26d535ae SS |
602 | } |
603 | ||
604 | static void iwl_pcie_rx_allocator_work(struct work_struct *data) | |
ab697a9f | 605 | { |
26d535ae SS |
606 | struct iwl_rb_allocator *rba_p = |
607 | container_of(data, struct iwl_rb_allocator, rx_alloc); | |
5a878bf6 | 608 | struct iwl_trans_pcie *trans_pcie = |
26d535ae | 609 | container_of(rba_p, struct iwl_trans_pcie, rba); |
ab697a9f | 610 | |
26d535ae | 611 | iwl_pcie_rx_allocator(trans_pcie->trans); |
ab697a9f EG |
612 | } |
613 | ||
9805c446 EG |
614 | static int iwl_pcie_rx_alloc(struct iwl_trans *trans) |
615 | { | |
616 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
26d535ae | 617 | struct iwl_rb_allocator *rba = &trans_pcie->rba; |
9805c446 | 618 | struct device *dev = trans->dev; |
78485054 | 619 | int i; |
96a6497b SS |
620 | int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : |
621 | sizeof(__le32); | |
9805c446 | 622 | |
78485054 SS |
623 | if (WARN_ON(trans_pcie->rxq)) |
624 | return -EINVAL; | |
625 | ||
626 | trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), | |
627 | GFP_KERNEL); | |
628 | if (!trans_pcie->rxq) | |
629 | return -EINVAL; | |
9805c446 | 630 | |
26d535ae | 631 | spin_lock_init(&rba->lock); |
9805c446 | 632 | |
78485054 SS |
633 | for (i = 0; i < trans->num_rx_queues; i++) { |
634 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
9805c446 | 635 | |
78485054 | 636 | spin_lock_init(&rxq->lock); |
96a6497b SS |
637 | if (trans->cfg->mq_rx_supported) |
638 | rxq->queue_size = MQ_RX_TABLE_SIZE; | |
639 | else | |
640 | rxq->queue_size = RX_QUEUE_SIZE; | |
641 | ||
78485054 SS |
642 | /* |
643 | * Allocate the circular buffer of Read Buffer Descriptors | |
644 | * (RBDs) | |
645 | */ | |
646 | rxq->bd = dma_zalloc_coherent(dev, | |
96a6497b SS |
647 | free_size * rxq->queue_size, |
648 | &rxq->bd_dma, GFP_KERNEL); | |
78485054 SS |
649 | if (!rxq->bd) |
650 | goto err; | |
9805c446 | 651 | |
96a6497b SS |
652 | if (trans->cfg->mq_rx_supported) { |
653 | rxq->used_bd = dma_zalloc_coherent(dev, | |
654 | sizeof(__le32) * | |
655 | rxq->queue_size, | |
656 | &rxq->used_bd_dma, | |
657 | GFP_KERNEL); | |
658 | if (!rxq->used_bd) | |
659 | goto err; | |
660 | } | |
9805c446 | 661 | |
78485054 SS |
662 | /*Allocate the driver's pointer to receive buffer status */ |
663 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), | |
664 | &rxq->rb_stts_dma, | |
665 | GFP_KERNEL); | |
666 | if (!rxq->rb_stts) | |
667 | goto err; | |
668 | } | |
9805c446 EG |
669 | return 0; |
670 | ||
78485054 SS |
671 | err: |
672 | for (i = 0; i < trans->num_rx_queues; i++) { | |
673 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
674 | ||
675 | if (rxq->bd) | |
96a6497b | 676 | dma_free_coherent(dev, free_size * rxq->queue_size, |
78485054 SS |
677 | rxq->bd, rxq->bd_dma); |
678 | rxq->bd_dma = 0; | |
679 | rxq->bd = NULL; | |
680 | ||
681 | if (rxq->rb_stts) | |
682 | dma_free_coherent(trans->dev, | |
683 | sizeof(struct iwl_rb_status), | |
684 | rxq->rb_stts, rxq->rb_stts_dma); | |
96a6497b SS |
685 | |
686 | if (rxq->used_bd) | |
687 | dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size, | |
688 | rxq->used_bd, rxq->used_bd_dma); | |
689 | rxq->used_bd_dma = 0; | |
690 | rxq->used_bd = NULL; | |
78485054 SS |
691 | } |
692 | kfree(trans_pcie->rxq); | |
96a6497b | 693 | |
9805c446 | 694 | return -ENOMEM; |
ab697a9f EG |
695 | } |
696 | ||
9805c446 EG |
697 | static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) |
698 | { | |
699 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
700 | u32 rb_size; | |
701 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
702 | ||
6c4fbcbc EG |
703 | switch (trans_pcie->rx_buf_size) { |
704 | case IWL_AMSDU_4K: | |
705 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
706 | break; | |
707 | case IWL_AMSDU_8K: | |
9805c446 | 708 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; |
6c4fbcbc EG |
709 | break; |
710 | case IWL_AMSDU_12K: | |
711 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; | |
712 | break; | |
713 | default: | |
714 | WARN_ON(1); | |
9805c446 | 715 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; |
6c4fbcbc | 716 | } |
9805c446 EG |
717 | |
718 | /* Stop Rx DMA */ | |
719 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
ddaf5a5b JB |
720 | /* reset and flush pointers */ |
721 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); | |
722 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); | |
723 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0); | |
9805c446 EG |
724 | |
725 | /* Reset driver's Rx queue write index */ | |
726 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
727 | ||
728 | /* Tell device where to find RBD circular buffer in DRAM */ | |
729 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
730 | (u32)(rxq->bd_dma >> 8)); | |
731 | ||
732 | /* Tell device where in DRAM to update its Rx status */ | |
733 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
734 | rxq->rb_stts_dma >> 4); | |
735 | ||
736 | /* Enable Rx DMA | |
737 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
738 | * the credit mechanism in 5000 HW RX FIFO | |
739 | * Direct rx interrupts to hosts | |
6c4fbcbc | 740 | * Rx buffer size 4 or 8k or 12k |
9805c446 EG |
741 | * RB timeout 0x10 |
742 | * 256 RBDs | |
743 | */ | |
744 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
745 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
746 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
747 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
748 | rb_size| | |
49bd072d | 749 | (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| |
9805c446 EG |
750 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); |
751 | ||
752 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
753 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); | |
6960a059 EG |
754 | |
755 | /* W/A for interrupt coalescing bug in 7260 and 3160 */ | |
756 | if (trans->cfg->host_interrupt_operation_mode) | |
757 | iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); | |
9805c446 EG |
758 | } |
759 | ||
bce97731 | 760 | static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) |
c7df1f4b | 761 | { |
96a6497b SS |
762 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
763 | u32 rb_size, enabled = 0; | |
764 | int i; | |
c7df1f4b | 765 | |
96a6497b SS |
766 | switch (trans_pcie->rx_buf_size) { |
767 | case IWL_AMSDU_4K: | |
768 | rb_size = RFH_RXF_DMA_RB_SIZE_4K; | |
769 | break; | |
770 | case IWL_AMSDU_8K: | |
771 | rb_size = RFH_RXF_DMA_RB_SIZE_8K; | |
772 | break; | |
773 | case IWL_AMSDU_12K: | |
774 | rb_size = RFH_RXF_DMA_RB_SIZE_12K; | |
775 | break; | |
776 | default: | |
777 | WARN_ON(1); | |
778 | rb_size = RFH_RXF_DMA_RB_SIZE_4K; | |
779 | } | |
c7df1f4b | 780 | |
96a6497b SS |
781 | /* Stop Rx DMA */ |
782 | iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); | |
783 | /* disable free amd used rx queue operation */ | |
784 | iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, 0); | |
26d535ae | 785 | |
96a6497b SS |
786 | for (i = 0; i < trans->num_rx_queues; i++) { |
787 | /* Tell device where to find RBD free table in DRAM */ | |
788 | iwl_pcie_write_prph_64(trans, RFH_Q_FRBDCB_BA_LSB(i), | |
bce97731 | 789 | (u64)(trans_pcie->rxq[i].bd_dma)); |
96a6497b SS |
790 | /* Tell device where to find RBD used table in DRAM */ |
791 | iwl_pcie_write_prph_64(trans, RFH_Q_URBDCB_BA_LSB(i), | |
bce97731 | 792 | (u64)(trans_pcie->rxq[i].used_bd_dma)); |
96a6497b SS |
793 | /* Tell device where in DRAM to update its Rx status */ |
794 | iwl_pcie_write_prph_64(trans, RFH_Q_URBD_STTS_WPTR_LSB(i), | |
bce97731 | 795 | trans_pcie->rxq[i].rb_stts_dma); |
96a6497b SS |
796 | /* Reset device indice tables */ |
797 | iwl_write_prph(trans, RFH_Q_FRBDCB_WIDX(i), 0); | |
798 | iwl_write_prph(trans, RFH_Q_FRBDCB_RIDX(i), 0); | |
799 | iwl_write_prph(trans, RFH_Q_URBDCB_WIDX(i), 0); | |
800 | ||
801 | enabled |= BIT(i) | BIT(i + 16); | |
802 | } | |
26d535ae | 803 | |
96a6497b SS |
804 | /* restock default queue */ |
805 | iwl_pcie_rxq_mq_restock(trans, &trans_pcie->rxq[0]); | |
806 | ||
807 | /* | |
808 | * Enable Rx DMA | |
809 | * Single frame mode | |
810 | * Rx buffer size 4 or 8k or 12k | |
811 | * Min RB size 4 or 8 | |
88076015 | 812 | * Drop frames that exceed RB size |
96a6497b SS |
813 | * 512 RBDs |
814 | */ | |
815 | iwl_write_prph(trans, RFH_RXF_DMA_CFG, | |
816 | RFH_DMA_EN_ENABLE_VAL | | |
817 | rb_size | RFH_RXF_DMA_SINGLE_FRAME_MASK | | |
818 | RFH_RXF_DMA_MIN_RB_4_8 | | |
88076015 | 819 | RFH_RXF_DMA_DROP_TOO_LARGE_MASK | |
96a6497b SS |
820 | RFH_RXF_DMA_RBDCB_SIZE_512); |
821 | ||
88076015 SS |
822 | /* |
823 | * Activate DMA snooping. | |
e5f91d91 | 824 | * Set RX DMA chunk size to 64B |
88076015 SS |
825 | * Default queue is 0 |
826 | */ | |
96a6497b | 827 | iwl_write_prph(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP | |
88076015 SS |
828 | (DEFAULT_RXQ_NUM << RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS) | |
829 | RFH_GEN_CFG_SERVICE_DMA_SNOOP); | |
830 | /* Enable the relevant rx queues */ | |
96a6497b | 831 | iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, enabled); |
26d535ae | 832 | |
96a6497b SS |
833 | /* Set interrupt coalescing timer to default (2048 usecs) */ |
834 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); | |
26d535ae SS |
835 | } |
836 | ||
96a6497b | 837 | static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) |
26d535ae | 838 | { |
96a6497b | 839 | lockdep_assert_held(&rxq->lock); |
26d535ae | 840 | |
96a6497b SS |
841 | INIT_LIST_HEAD(&rxq->rx_free); |
842 | INIT_LIST_HEAD(&rxq->rx_used); | |
843 | rxq->free_count = 0; | |
844 | rxq->used_count = 0; | |
26d535ae SS |
845 | } |
846 | ||
bce97731 SS |
847 | static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) |
848 | { | |
849 | WARN_ON(1); | |
850 | return 0; | |
851 | } | |
852 | ||
9805c446 EG |
853 | int iwl_pcie_rx_init(struct iwl_trans *trans) |
854 | { | |
855 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
78485054 | 856 | struct iwl_rxq *def_rxq; |
26d535ae | 857 | struct iwl_rb_allocator *rba = &trans_pcie->rba; |
7b542436 | 858 | int i, err, queue_size, allocator_pool_size, num_alloc; |
9805c446 | 859 | |
78485054 | 860 | if (!trans_pcie->rxq) { |
9805c446 EG |
861 | err = iwl_pcie_rx_alloc(trans); |
862 | if (err) | |
863 | return err; | |
864 | } | |
78485054 | 865 | def_rxq = trans_pcie->rxq; |
26d535ae SS |
866 | if (!rba->alloc_wq) |
867 | rba->alloc_wq = alloc_workqueue("rb_allocator", | |
868 | WQ_HIGHPRI | WQ_UNBOUND, 1); | |
869 | INIT_WORK(&rba->rx_alloc, iwl_pcie_rx_allocator_work); | |
870 | ||
871 | spin_lock(&rba->lock); | |
872 | atomic_set(&rba->req_pending, 0); | |
873 | atomic_set(&rba->req_ready, 0); | |
96a6497b SS |
874 | INIT_LIST_HEAD(&rba->rbd_allocated); |
875 | INIT_LIST_HEAD(&rba->rbd_empty); | |
26d535ae | 876 | spin_unlock(&rba->lock); |
9805c446 | 877 | |
c7df1f4b | 878 | /* free all first - we might be reconfigured for a different size */ |
78485054 | 879 | iwl_pcie_free_rbs_pool(trans); |
9805c446 EG |
880 | |
881 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
78485054 | 882 | def_rxq->queue[i] = NULL; |
9805c446 | 883 | |
78485054 SS |
884 | for (i = 0; i < trans->num_rx_queues; i++) { |
885 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
886 | ||
96a6497b SS |
887 | rxq->id = i; |
888 | ||
78485054 SS |
889 | spin_lock(&rxq->lock); |
890 | /* | |
891 | * Set read write pointer to reflect that we have processed | |
892 | * and used all buffers, but have not restocked the Rx queue | |
893 | * with fresh buffers | |
894 | */ | |
895 | rxq->read = 0; | |
896 | rxq->write = 0; | |
897 | rxq->write_actual = 0; | |
898 | memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); | |
9805c446 | 899 | |
78485054 SS |
900 | iwl_pcie_rx_init_rxb_lists(rxq); |
901 | ||
bce97731 SS |
902 | if (!rxq->napi.poll) |
903 | netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, | |
904 | iwl_pcie_dummy_napi_poll, 64); | |
905 | ||
78485054 SS |
906 | spin_unlock(&rxq->lock); |
907 | } | |
9805c446 | 908 | |
96a6497b | 909 | /* move the pool to the default queue and allocator ownerships */ |
7b542436 SS |
910 | queue_size = trans->cfg->mq_rx_supported ? |
911 | MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; | |
96a6497b SS |
912 | allocator_pool_size = trans->num_rx_queues * |
913 | (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); | |
7b542436 | 914 | num_alloc = queue_size + allocator_pool_size; |
43146925 SS |
915 | BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != |
916 | ARRAY_SIZE(trans_pcie->rx_pool)); | |
7b542436 | 917 | for (i = 0; i < num_alloc; i++) { |
96a6497b SS |
918 | struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; |
919 | ||
920 | if (i < allocator_pool_size) | |
921 | list_add(&rxb->list, &rba->rbd_empty); | |
922 | else | |
923 | list_add(&rxb->list, &def_rxq->rx_used); | |
924 | trans_pcie->global_table[i] = rxb; | |
925 | rxb->vid = (u16)i; | |
926 | } | |
9805c446 | 927 | |
78485054 | 928 | iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); |
96a6497b | 929 | if (trans->cfg->mq_rx_supported) { |
bce97731 | 930 | iwl_pcie_rx_mq_hw_init(trans); |
96a6497b | 931 | } else { |
e0e168dc | 932 | iwl_pcie_rxq_sq_restock(trans, def_rxq); |
96a6497b SS |
933 | iwl_pcie_rx_hw_init(trans, def_rxq); |
934 | } | |
78485054 SS |
935 | |
936 | spin_lock(&def_rxq->lock); | |
937 | iwl_pcie_rxq_inc_wr_ptr(trans, def_rxq); | |
938 | spin_unlock(&def_rxq->lock); | |
9805c446 EG |
939 | |
940 | return 0; | |
941 | } | |
942 | ||
943 | void iwl_pcie_rx_free(struct iwl_trans *trans) | |
944 | { | |
945 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
26d535ae | 946 | struct iwl_rb_allocator *rba = &trans_pcie->rba; |
96a6497b SS |
947 | int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : |
948 | sizeof(__le32); | |
78485054 | 949 | int i; |
9805c446 | 950 | |
78485054 SS |
951 | /* |
952 | * if rxq is NULL, it means that nothing has been allocated, | |
953 | * exit now | |
954 | */ | |
955 | if (!trans_pcie->rxq) { | |
9805c446 EG |
956 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
957 | return; | |
958 | } | |
959 | ||
26d535ae SS |
960 | cancel_work_sync(&rba->rx_alloc); |
961 | if (rba->alloc_wq) { | |
962 | destroy_workqueue(rba->alloc_wq); | |
963 | rba->alloc_wq = NULL; | |
964 | } | |
965 | ||
78485054 SS |
966 | iwl_pcie_free_rbs_pool(trans); |
967 | ||
968 | for (i = 0; i < trans->num_rx_queues; i++) { | |
969 | struct iwl_rxq *rxq = &trans_pcie->rxq[i]; | |
970 | ||
971 | if (rxq->bd) | |
972 | dma_free_coherent(trans->dev, | |
96a6497b | 973 | free_size * rxq->queue_size, |
78485054 SS |
974 | rxq->bd, rxq->bd_dma); |
975 | rxq->bd_dma = 0; | |
976 | rxq->bd = NULL; | |
977 | ||
978 | if (rxq->rb_stts) | |
979 | dma_free_coherent(trans->dev, | |
980 | sizeof(struct iwl_rb_status), | |
981 | rxq->rb_stts, rxq->rb_stts_dma); | |
982 | else | |
983 | IWL_DEBUG_INFO(trans, | |
984 | "Free rxq->rb_stts which is NULL\n"); | |
9805c446 | 985 | |
96a6497b SS |
986 | if (rxq->used_bd) |
987 | dma_free_coherent(trans->dev, | |
988 | sizeof(__le32) * rxq->queue_size, | |
989 | rxq->used_bd, rxq->used_bd_dma); | |
990 | rxq->used_bd_dma = 0; | |
991 | rxq->used_bd = NULL; | |
bce97731 SS |
992 | |
993 | if (rxq->napi.poll) | |
994 | netif_napi_del(&rxq->napi); | |
96a6497b | 995 | } |
78485054 | 996 | kfree(trans_pcie->rxq); |
9805c446 EG |
997 | } |
998 | ||
26d535ae SS |
999 | /* |
1000 | * iwl_pcie_rx_reuse_rbd - Recycle used RBDs | |
1001 | * | |
1002 | * Called when a RBD can be reused. The RBD is transferred to the allocator. | |
1003 | * When there are 2 empty RBDs - a request for allocation is posted | |
1004 | */ | |
1005 | static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, | |
1006 | struct iwl_rx_mem_buffer *rxb, | |
1007 | struct iwl_rxq *rxq, bool emergency) | |
1008 | { | |
1009 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1010 | struct iwl_rb_allocator *rba = &trans_pcie->rba; | |
1011 | ||
1012 | /* Move the RBD to the used list, will be moved to allocator in batches | |
1013 | * before claiming or posting a request*/ | |
1014 | list_add_tail(&rxb->list, &rxq->rx_used); | |
1015 | ||
1016 | if (unlikely(emergency)) | |
1017 | return; | |
1018 | ||
1019 | /* Count the allocator owned RBDs */ | |
1020 | rxq->used_count++; | |
1021 | ||
1022 | /* If we have RX_POST_REQ_ALLOC new released rx buffers - | |
1023 | * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is | |
1024 | * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, | |
1025 | * after but we still need to post another request. | |
1026 | */ | |
1027 | if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { | |
1028 | /* Move the 2 RBDs to the allocator ownership. | |
1029 | Allocator has another 6 from pool for the request completion*/ | |
1030 | spin_lock(&rba->lock); | |
1031 | list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); | |
1032 | spin_unlock(&rba->lock); | |
1033 | ||
1034 | atomic_inc(&rba->req_pending); | |
1035 | queue_work(rba->alloc_wq, &rba->rx_alloc); | |
1036 | } | |
1037 | } | |
1038 | ||
9805c446 | 1039 | static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, |
78485054 | 1040 | struct iwl_rxq *rxq, |
26d535ae SS |
1041 | struct iwl_rx_mem_buffer *rxb, |
1042 | bool emergency) | |
df2f3216 JB |
1043 | { |
1044 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
990aa6d7 | 1045 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
0c19744c | 1046 | bool page_stolen = false; |
b2cf410c | 1047 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; |
0c19744c | 1048 | u32 offset = 0; |
df2f3216 JB |
1049 | |
1050 | if (WARN_ON(!rxb)) | |
1051 | return; | |
1052 | ||
0c19744c JB |
1053 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); |
1054 | ||
1055 | while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { | |
1056 | struct iwl_rx_packet *pkt; | |
0c19744c JB |
1057 | u16 sequence; |
1058 | bool reclaim; | |
f7e6469f | 1059 | int index, cmd_index, len; |
0c19744c JB |
1060 | struct iwl_rx_cmd_buffer rxcb = { |
1061 | ._offset = offset, | |
d13f1862 | 1062 | ._rx_page_order = trans_pcie->rx_page_order, |
0c19744c JB |
1063 | ._page = rxb->page, |
1064 | ._page_stolen = false, | |
0d6c4a2e | 1065 | .truesize = max_len, |
0c19744c JB |
1066 | }; |
1067 | ||
1068 | pkt = rxb_addr(&rxcb); | |
1069 | ||
1070 | if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) | |
1071 | break; | |
1072 | ||
9243efcc LK |
1073 | IWL_DEBUG_RX(trans, |
1074 | "cmd at offset %d: %s (0x%.2x, seq 0x%x)\n", | |
1075 | rxcb._offset, | |
39bdb17e SD |
1076 | iwl_get_cmd_string(trans, |
1077 | iwl_cmd_id(pkt->hdr.cmd, | |
1078 | pkt->hdr.group_id, | |
1079 | 0)), | |
9243efcc | 1080 | pkt->hdr.cmd, le16_to_cpu(pkt->hdr.sequence)); |
0c19744c | 1081 | |
65b30348 | 1082 | len = iwl_rx_packet_len(pkt); |
0c19744c | 1083 | len += sizeof(u32); /* account for status word */ |
f042c2eb JB |
1084 | trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); |
1085 | trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); | |
0c19744c JB |
1086 | |
1087 | /* Reclaim a command buffer only if this packet is a response | |
1088 | * to a (driver-originated) command. | |
1089 | * If the packet (e.g. Rx frame) originated from uCode, | |
1090 | * there is no command buffer to reclaim. | |
1091 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1092 | * but apparently a few don't get set; catch them here. */ | |
1093 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); | |
1094 | if (reclaim) { | |
1095 | int i; | |
1096 | ||
1097 | for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { | |
1098 | if (trans_pcie->no_reclaim_cmds[i] == | |
1099 | pkt->hdr.cmd) { | |
1100 | reclaim = false; | |
1101 | break; | |
1102 | } | |
d663ee73 JB |
1103 | } |
1104 | } | |
df2f3216 | 1105 | |
0c19744c JB |
1106 | sequence = le16_to_cpu(pkt->hdr.sequence); |
1107 | index = SEQ_TO_INDEX(sequence); | |
1108 | cmd_index = get_cmd_index(&txq->q, index); | |
1109 | ||
bce97731 SS |
1110 | if (rxq->id == 0) |
1111 | iwl_op_mode_rx(trans->op_mode, &rxq->napi, | |
1112 | &rxcb); | |
1113 | else | |
1114 | iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, | |
1115 | &rxcb, rxq->id); | |
0c19744c | 1116 | |
96791422 | 1117 | if (reclaim) { |
5d4185ae | 1118 | kzfree(txq->entries[cmd_index].free_buf); |
f4feb8ac | 1119 | txq->entries[cmd_index].free_buf = NULL; |
96791422 EG |
1120 | } |
1121 | ||
0c19744c JB |
1122 | /* |
1123 | * After here, we should always check rxcb._page_stolen, | |
1124 | * if it is true then one of the handlers took the page. | |
1125 | */ | |
1126 | ||
1127 | if (reclaim) { | |
1128 | /* Invoke any callbacks, transfer the buffer to caller, | |
1129 | * and fire off the (possibly) blocking | |
1130 | * iwl_trans_send_cmd() | |
1131 | * as we reclaim the driver command queue */ | |
1132 | if (!rxcb._page_stolen) | |
f7e6469f | 1133 | iwl_pcie_hcmd_complete(trans, &rxcb); |
0c19744c JB |
1134 | else |
1135 | IWL_WARN(trans, "Claim null rxb?\n"); | |
1136 | } | |
1137 | ||
1138 | page_stolen |= rxcb._page_stolen; | |
1139 | offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); | |
df2f3216 JB |
1140 | } |
1141 | ||
0c19744c JB |
1142 | /* page was stolen from us -- free our reference */ |
1143 | if (page_stolen) { | |
b2cf410c | 1144 | __free_pages(rxb->page, trans_pcie->rx_page_order); |
df2f3216 | 1145 | rxb->page = NULL; |
0c19744c | 1146 | } |
df2f3216 JB |
1147 | |
1148 | /* Reuse the page if possible. For notification packets and | |
1149 | * SKBs that fail to Rx correctly, add them back into the | |
1150 | * rx_free list for reuse later. */ | |
df2f3216 JB |
1151 | if (rxb->page != NULL) { |
1152 | rxb->page_dma = | |
1153 | dma_map_page(trans->dev, rxb->page, 0, | |
20d3b647 JB |
1154 | PAGE_SIZE << trans_pcie->rx_page_order, |
1155 | DMA_FROM_DEVICE); | |
7c341582 JB |
1156 | if (dma_mapping_error(trans->dev, rxb->page_dma)) { |
1157 | /* | |
1158 | * free the page(s) as well to not break | |
1159 | * the invariant that the items on the used | |
1160 | * list have no page(s) | |
1161 | */ | |
1162 | __free_pages(rxb->page, trans_pcie->rx_page_order); | |
1163 | rxb->page = NULL; | |
26d535ae | 1164 | iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); |
7c341582 JB |
1165 | } else { |
1166 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1167 | rxq->free_count++; | |
1168 | } | |
df2f3216 | 1169 | } else |
26d535ae | 1170 | iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); |
df2f3216 JB |
1171 | } |
1172 | ||
990aa6d7 EG |
1173 | /* |
1174 | * iwl_pcie_rx_handle - Main entry function for receiving responses from fw | |
ab697a9f | 1175 | */ |
2e5d4a8f | 1176 | static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) |
ab697a9f | 1177 | { |
df2f3216 | 1178 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
2e5d4a8f | 1179 | struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; |
d56daea4 | 1180 | u32 r, i, count = 0; |
26d535ae | 1181 | bool emergency = false; |
ab697a9f | 1182 | |
f14d6b39 JB |
1183 | restart: |
1184 | spin_lock(&rxq->lock); | |
ab697a9f EG |
1185 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1186 | * buffer that the driver may process (last buffer filled by ucode). */ | |
52e2a99e | 1187 | r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; |
ab697a9f EG |
1188 | i = rxq->read; |
1189 | ||
5eae443e SS |
1190 | /* W/A 9000 device step A0 wrap-around bug */ |
1191 | r &= (rxq->queue_size - 1); | |
1192 | ||
ab697a9f EG |
1193 | /* Rx interrupt, but nothing sent from uCode */ |
1194 | if (i == r) | |
5eae443e | 1195 | IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); |
ab697a9f | 1196 | |
ab697a9f | 1197 | while (i != r) { |
48a2d66f | 1198 | struct iwl_rx_mem_buffer *rxb; |
ab697a9f | 1199 | |
96a6497b | 1200 | if (unlikely(rxq->used_count == rxq->queue_size / 2)) |
26d535ae SS |
1201 | emergency = true; |
1202 | ||
96a6497b SS |
1203 | if (trans->cfg->mq_rx_supported) { |
1204 | /* | |
1205 | * used_bd is a 32 bit but only 12 are used to retrieve | |
1206 | * the vid | |
1207 | */ | |
5eae443e | 1208 | u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF; |
96a6497b | 1209 | |
5eae443e SS |
1210 | if (WARN(vid >= ARRAY_SIZE(trans_pcie->global_table), |
1211 | "Invalid rxb index from HW %u\n", (u32)vid)) | |
1212 | goto out; | |
96a6497b SS |
1213 | rxb = trans_pcie->global_table[vid]; |
1214 | } else { | |
1215 | rxb = rxq->queue[i]; | |
1216 | rxq->queue[i] = NULL; | |
1217 | } | |
ab697a9f | 1218 | |
5eae443e | 1219 | IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); |
78485054 | 1220 | iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency); |
ab697a9f | 1221 | |
96a6497b | 1222 | i = (i + 1) & (rxq->queue_size - 1); |
26d535ae | 1223 | |
d56daea4 SS |
1224 | /* |
1225 | * If we have RX_CLAIM_REQ_ALLOC released rx buffers - | |
1226 | * try to claim the pre-allocated buffers from the allocator. | |
1227 | * If not ready - will try to reclaim next time. | |
1228 | * There is no need to reschedule work - allocator exits only | |
1229 | * on success | |
1230 | */ | |
1231 | if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) | |
1232 | iwl_pcie_rx_allocator_get(trans, rxq); | |
1233 | ||
1234 | if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { | |
26d535ae | 1235 | struct iwl_rb_allocator *rba = &trans_pcie->rba; |
26d535ae | 1236 | |
d56daea4 SS |
1237 | /* Add the remaining empty RBDs for allocator use */ |
1238 | spin_lock(&rba->lock); | |
1239 | list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); | |
1240 | spin_unlock(&rba->lock); | |
1241 | } else if (emergency) { | |
255ba065 | 1242 | count++; |
26d535ae | 1243 | if (count == 8) { |
255ba065 | 1244 | count = 0; |
96a6497b | 1245 | if (rxq->used_count < rxq->queue_size / 3) |
26d535ae | 1246 | emergency = false; |
e0e168dc GG |
1247 | |
1248 | rxq->read = i; | |
26d535ae | 1249 | spin_unlock(&rxq->lock); |
78485054 | 1250 | iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); |
96a6497b | 1251 | iwl_pcie_rxq_restock(trans, rxq); |
e0e168dc GG |
1252 | goto restart; |
1253 | } | |
26d535ae | 1254 | } |
ab697a9f | 1255 | } |
5eae443e | 1256 | out: |
ab697a9f EG |
1257 | /* Backtrack one entry */ |
1258 | rxq->read = i; | |
f14d6b39 JB |
1259 | spin_unlock(&rxq->lock); |
1260 | ||
26d535ae SS |
1261 | /* |
1262 | * handle a case where in emergency there are some unallocated RBDs. | |
1263 | * those RBDs are in the used list, but are not tracked by the queue's | |
1264 | * used_count which counts allocator owned RBDs. | |
1265 | * unallocated emergency RBDs must be allocated on exit, otherwise | |
1266 | * when called again the function may not be in emergency mode and | |
1267 | * they will be handed to the allocator with no tracking in the RBD | |
1268 | * allocator counters, which will lead to them never being claimed back | |
1269 | * by the queue. | |
1270 | * by allocating them here, they are now in the queue free list, and | |
1271 | * will be restocked by the next call of iwl_pcie_rxq_restock. | |
1272 | */ | |
1273 | if (unlikely(emergency && count)) | |
78485054 | 1274 | iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); |
255ba065 | 1275 | |
bce97731 SS |
1276 | if (rxq->napi.poll) |
1277 | napi_gro_flush(&rxq->napi, false); | |
e0e168dc GG |
1278 | |
1279 | iwl_pcie_rxq_restock(trans, rxq); | |
ab697a9f EG |
1280 | } |
1281 | ||
2e5d4a8f HD |
1282 | static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) |
1283 | { | |
1284 | u8 queue = entry->entry; | |
1285 | struct msix_entry *entries = entry - queue; | |
1286 | ||
1287 | return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); | |
1288 | } | |
1289 | ||
1290 | static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, | |
1291 | struct msix_entry *entry) | |
1292 | { | |
1293 | /* | |
1294 | * Before sending the interrupt the HW disables it to prevent | |
1295 | * a nested interrupt. This is done by writing 1 to the corresponding | |
1296 | * bit in the mask register. After handling the interrupt, it should be | |
1297 | * re-enabled by clearing this bit. This register is defined as | |
1298 | * write 1 clear (W1C) register, meaning that it's being clear | |
1299 | * by writing 1 to the bit. | |
1300 | */ | |
1301 | iwl_write_direct32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); | |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw | |
1306 | * This interrupt handler should be used with RSS queue only. | |
1307 | */ | |
1308 | irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) | |
1309 | { | |
1310 | struct msix_entry *entry = dev_id; | |
1311 | struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); | |
1312 | struct iwl_trans *trans = trans_pcie->trans; | |
1313 | ||
5eae443e SS |
1314 | if (WARN_ON(entry->entry >= trans->num_rx_queues)) |
1315 | return IRQ_NONE; | |
1316 | ||
2e5d4a8f HD |
1317 | lock_map_acquire(&trans->sync_cmd_lockdep_map); |
1318 | ||
1319 | local_bh_disable(); | |
1320 | iwl_pcie_rx_handle(trans, entry->entry); | |
1321 | local_bh_enable(); | |
1322 | ||
1323 | iwl_pcie_clear_irq(trans, entry); | |
1324 | ||
1325 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
1326 | ||
1327 | return IRQ_HANDLED; | |
1328 | } | |
1329 | ||
990aa6d7 EG |
1330 | /* |
1331 | * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card | |
7ff94706 | 1332 | */ |
990aa6d7 | 1333 | static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) |
7ff94706 | 1334 | { |
f946b529 | 1335 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1103323c | 1336 | int i; |
f946b529 | 1337 | |
7ff94706 | 1338 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ |
035f7ff2 | 1339 | if (trans->cfg->internal_wimax_coex && |
95411d04 | 1340 | !trans->cfg->apmg_not_supported && |
1042db2a | 1341 | (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & |
20d3b647 | 1342 | APMS_CLK_VAL_MRB_FUNC_MODE) || |
1042db2a | 1343 | (iwl_read_prph(trans, APMG_PS_CTRL_REG) & |
20d3b647 | 1344 | APMG_PS_CTRL_VAL_RESET_REQ))) { |
eb7ff77e | 1345 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
8a8bbdb4 | 1346 | iwl_op_mode_wimax_active(trans->op_mode); |
f946b529 | 1347 | wake_up(&trans_pcie->wait_command_queue); |
7ff94706 EG |
1348 | return; |
1349 | } | |
1350 | ||
990aa6d7 | 1351 | iwl_pcie_dump_csr(trans); |
313b0a29 | 1352 | iwl_dump_fh(trans, NULL); |
7ff94706 | 1353 | |
2bfb5092 | 1354 | local_bh_disable(); |
2a988e98 AN |
1355 | /* The STATUS_FW_ERROR bit is set in this function. This must happen |
1356 | * before we wake up the command caller, to ensure a proper cleanup. */ | |
1357 | iwl_trans_fw_error(trans); | |
2bfb5092 | 1358 | local_bh_enable(); |
2a988e98 | 1359 | |
1103323c EG |
1360 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) |
1361 | del_timer(&trans_pcie->txq[i].stuck_timer); | |
1362 | ||
2a988e98 AN |
1363 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
1364 | wake_up(&trans_pcie->wait_command_queue); | |
7ff94706 EG |
1365 | } |
1366 | ||
7117c000 | 1367 | static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) |
fc84472b | 1368 | { |
fc84472b EG |
1369 | u32 inta; |
1370 | ||
46e81af9 | 1371 | lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); |
fc84472b EG |
1372 | |
1373 | trace_iwlwifi_dev_irq(trans->dev); | |
1374 | ||
1375 | /* Discover which interrupts are active/pending */ | |
1376 | inta = iwl_read32(trans, CSR_INT); | |
1377 | ||
fc84472b | 1378 | /* the thread will service interrupts and re-enable them */ |
fe523dc9 | 1379 | return inta; |
fc84472b EG |
1380 | } |
1381 | ||
1382 | /* a device (PCI-E) page is 4096 bytes long */ | |
1383 | #define ICT_SHIFT 12 | |
1384 | #define ICT_SIZE (1 << ICT_SHIFT) | |
1385 | #define ICT_COUNT (ICT_SIZE / sizeof(u32)) | |
1386 | ||
1387 | /* interrupt handler using ict table, with this interrupt driver will | |
1388 | * stop using INTA register to get device's interrupt, reading this register | |
1389 | * is expensive, device will write interrupts in ICT dram table, increment | |
1390 | * index then will fire interrupt to driver, driver will OR all ICT table | |
1391 | * entries from current index up to table entry with 0 value. the result is | |
1392 | * the interrupt we need to service, driver will set the entries back to 0 and | |
1393 | * set index. | |
1394 | */ | |
7117c000 | 1395 | static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) |
fc84472b EG |
1396 | { |
1397 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
fc84472b EG |
1398 | u32 inta; |
1399 | u32 val = 0; | |
1400 | u32 read; | |
1401 | ||
fc84472b EG |
1402 | trace_iwlwifi_dev_irq(trans->dev); |
1403 | ||
1404 | /* Ignore interrupt if there's nothing in NIC to service. | |
1405 | * This may be due to IRQ shared with another device, | |
1406 | * or due to sporadic interrupts thrown from our NIC. */ | |
1407 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); | |
1408 | trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); | |
7ba1faa4 EG |
1409 | if (!read) |
1410 | return 0; | |
fc84472b EG |
1411 | |
1412 | /* | |
1413 | * Collect all entries up to the first 0, starting from ict_index; | |
1414 | * note we already read at ict_index. | |
1415 | */ | |
1416 | do { | |
1417 | val |= read; | |
1418 | IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", | |
1419 | trans_pcie->ict_index, read); | |
1420 | trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; | |
1421 | trans_pcie->ict_index = | |
83f32a4b | 1422 | ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); |
fc84472b EG |
1423 | |
1424 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); | |
1425 | trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, | |
1426 | read); | |
1427 | } while (read); | |
1428 | ||
1429 | /* We should not get this value, just ignore it. */ | |
1430 | if (val == 0xffffffff) | |
1431 | val = 0; | |
1432 | ||
1433 | /* | |
1434 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
1435 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
1436 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
1437 | * so we use them to decide on the real state of the Rx bit. | |
1438 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
1439 | */ | |
1440 | if (val & 0xC0000) | |
1441 | val |= 0x8000; | |
1442 | ||
1443 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
fe523dc9 | 1444 | return inta; |
fc84472b EG |
1445 | } |
1446 | ||
2bfb5092 | 1447 | irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) |
ab697a9f | 1448 | { |
2bfb5092 | 1449 | struct iwl_trans *trans = dev_id; |
20d3b647 JB |
1450 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1451 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
ab697a9f EG |
1452 | u32 inta = 0; |
1453 | u32 handled = 0; | |
ab697a9f | 1454 | |
2bfb5092 JB |
1455 | lock_map_acquire(&trans->sync_cmd_lockdep_map); |
1456 | ||
7b70bd63 | 1457 | spin_lock(&trans_pcie->irq_lock); |
ab697a9f | 1458 | |
0fec9542 EG |
1459 | /* dram interrupt table not set yet, |
1460 | * use legacy interrupt. | |
1461 | */ | |
1462 | if (likely(trans_pcie->use_ict)) | |
7117c000 | 1463 | inta = iwl_pcie_int_cause_ict(trans); |
0fec9542 | 1464 | else |
7117c000 | 1465 | inta = iwl_pcie_int_cause_non_ict(trans); |
0fec9542 | 1466 | |
7ba1faa4 EG |
1467 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
1468 | IWL_DEBUG_ISR(trans, | |
1469 | "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", | |
1470 | inta, trans_pcie->inta_mask, | |
1471 | iwl_read32(trans, CSR_INT_MASK), | |
1472 | iwl_read32(trans, CSR_FH_INT_STATUS)); | |
1473 | if (inta & (~trans_pcie->inta_mask)) | |
1474 | IWL_DEBUG_ISR(trans, | |
1475 | "We got a masked interrupt (0x%08x)\n", | |
1476 | inta & (~trans_pcie->inta_mask)); | |
1477 | } | |
1478 | ||
1479 | inta &= trans_pcie->inta_mask; | |
1480 | ||
1481 | /* | |
1482 | * Ignore interrupt if there's nothing in NIC to service. | |
1483 | * This may be due to IRQ shared with another device, | |
1484 | * or due to sporadic interrupts thrown from our NIC. | |
1485 | */ | |
7117c000 | 1486 | if (unlikely(!inta)) { |
7ba1faa4 EG |
1487 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1488 | /* | |
1489 | * Re-enable interrupts here since we don't | |
1490 | * have anything to service | |
1491 | */ | |
1492 | if (test_bit(STATUS_INT_ENABLED, &trans->status)) | |
1493 | iwl_enable_interrupts(trans); | |
7b70bd63 | 1494 | spin_unlock(&trans_pcie->irq_lock); |
7117c000 EG |
1495 | lock_map_release(&trans->sync_cmd_lockdep_map); |
1496 | return IRQ_NONE; | |
1497 | } | |
1498 | ||
7ba1faa4 EG |
1499 | if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { |
1500 | /* | |
1501 | * Hardware disappeared. It might have | |
1502 | * already raised an interrupt. | |
1503 | */ | |
1504 | IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
7b70bd63 | 1505 | spin_unlock(&trans_pcie->irq_lock); |
7117c000 | 1506 | goto out; |
a0f337cc EG |
1507 | } |
1508 | ||
ab697a9f EG |
1509 | /* Ack/clear/reset pending uCode interrupts. |
1510 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1511 | */ | |
1512 | /* There is a hardware bug in the interrupt mask function that some | |
1513 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
1514 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
1515 | * ICT interrupt handling mechanism has another bug that might cause | |
1516 | * these unmasked interrupts fail to be detected. We workaround the | |
1517 | * hardware bugs here by ACKing all the possible interrupts so that | |
1518 | * interrupt coalescing can still be achieved. | |
1519 | */ | |
7117c000 | 1520 | iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); |
ab697a9f | 1521 | |
51cd53ad | 1522 | if (iwl_have_debug_level(IWL_DL_ISR)) |
0ca24daf | 1523 | IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", |
51cd53ad | 1524 | inta, iwl_read32(trans, CSR_INT_MASK)); |
ab697a9f | 1525 | |
7b70bd63 | 1526 | spin_unlock(&trans_pcie->irq_lock); |
b49ba04a | 1527 | |
ab697a9f EG |
1528 | /* Now service all interrupt bits discovered above. */ |
1529 | if (inta & CSR_INT_BIT_HW_ERR) { | |
0c325769 | 1530 | IWL_ERR(trans, "Hardware error detected. Restarting.\n"); |
ab697a9f EG |
1531 | |
1532 | /* Tell the device to stop sending interrupts */ | |
0c325769 | 1533 | iwl_disable_interrupts(trans); |
ab697a9f | 1534 | |
1f7b6172 | 1535 | isr_stats->hw++; |
990aa6d7 | 1536 | iwl_pcie_irq_handle_error(trans); |
ab697a9f EG |
1537 | |
1538 | handled |= CSR_INT_BIT_HW_ERR; | |
1539 | ||
2bfb5092 | 1540 | goto out; |
ab697a9f EG |
1541 | } |
1542 | ||
a8bceb39 | 1543 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f EG |
1544 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1545 | if (inta & CSR_INT_BIT_SCD) { | |
51cd53ad JB |
1546 | IWL_DEBUG_ISR(trans, |
1547 | "Scheduler finished to transmit the frame/frames.\n"); | |
1f7b6172 | 1548 | isr_stats->sch++; |
ab697a9f EG |
1549 | } |
1550 | ||
1551 | /* Alive notification via Rx interrupt will do the real work */ | |
1552 | if (inta & CSR_INT_BIT_ALIVE) { | |
0c325769 | 1553 | IWL_DEBUG_ISR(trans, "Alive interrupt\n"); |
1f7b6172 | 1554 | isr_stats->alive++; |
ab697a9f EG |
1555 | } |
1556 | } | |
51cd53ad | 1557 | |
ab697a9f EG |
1558 | /* Safely ignore these bits for debug checks below */ |
1559 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1560 | ||
1561 | /* HW RF KILL switch toggled */ | |
1562 | if (inta & CSR_INT_BIT_RF_KILL) { | |
c9eec95c | 1563 | bool hw_rfkill; |
ab697a9f | 1564 | |
8d425517 | 1565 | hw_rfkill = iwl_is_rfkill_set(trans); |
0c325769 | 1566 | IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", |
20d3b647 | 1567 | hw_rfkill ? "disable radio" : "enable radio"); |
ab697a9f | 1568 | |
1f7b6172 | 1569 | isr_stats->rfkill++; |
ab697a9f | 1570 | |
fa9f3281 | 1571 | mutex_lock(&trans_pcie->mutex); |
14cfca71 | 1572 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
fa9f3281 | 1573 | mutex_unlock(&trans_pcie->mutex); |
f946b529 | 1574 | if (hw_rfkill) { |
eb7ff77e AN |
1575 | set_bit(STATUS_RFKILL, &trans->status); |
1576 | if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1577 | &trans->status)) | |
f946b529 EG |
1578 | IWL_DEBUG_RF_KILL(trans, |
1579 | "Rfkill while SYNC HCMD in flight\n"); | |
1580 | wake_up(&trans_pcie->wait_command_queue); | |
1581 | } else { | |
eb7ff77e | 1582 | clear_bit(STATUS_RFKILL, &trans->status); |
f946b529 | 1583 | } |
ab697a9f EG |
1584 | |
1585 | handled |= CSR_INT_BIT_RF_KILL; | |
1586 | } | |
1587 | ||
1588 | /* Chip got too hot and stopped itself */ | |
1589 | if (inta & CSR_INT_BIT_CT_KILL) { | |
0c325769 | 1590 | IWL_ERR(trans, "Microcode CT kill error detected.\n"); |
1f7b6172 | 1591 | isr_stats->ctkill++; |
ab697a9f EG |
1592 | handled |= CSR_INT_BIT_CT_KILL; |
1593 | } | |
1594 | ||
1595 | /* Error detected by uCode */ | |
1596 | if (inta & CSR_INT_BIT_SW_ERR) { | |
0c325769 | 1597 | IWL_ERR(trans, "Microcode SW error detected. " |
ab697a9f | 1598 | " Restarting 0x%X.\n", inta); |
1f7b6172 | 1599 | isr_stats->sw++; |
990aa6d7 | 1600 | iwl_pcie_irq_handle_error(trans); |
ab697a9f EG |
1601 | handled |= CSR_INT_BIT_SW_ERR; |
1602 | } | |
1603 | ||
1604 | /* uCode wakes up after power-down sleep */ | |
1605 | if (inta & CSR_INT_BIT_WAKEUP) { | |
0c325769 | 1606 | IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); |
5d63f926 | 1607 | iwl_pcie_rxq_check_wrptr(trans); |
ea68f460 | 1608 | iwl_pcie_txq_check_wrptrs(trans); |
ab697a9f | 1609 | |
1f7b6172 | 1610 | isr_stats->wakeup++; |
ab697a9f EG |
1611 | |
1612 | handled |= CSR_INT_BIT_WAKEUP; | |
1613 | } | |
1614 | ||
1615 | /* All uCode command responses, including Tx command responses, | |
1616 | * Rx "responses" (frame-received notification), and other | |
1617 | * notifications from uCode come through here*/ | |
1618 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
20d3b647 | 1619 | CSR_INT_BIT_RX_PERIODIC)) { |
0c325769 | 1620 | IWL_DEBUG_ISR(trans, "Rx interrupt\n"); |
ab697a9f EG |
1621 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1622 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1042db2a | 1623 | iwl_write32(trans, CSR_FH_INT_STATUS, |
ab697a9f EG |
1624 | CSR_FH_INT_RX_MASK); |
1625 | } | |
1626 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1627 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1042db2a | 1628 | iwl_write32(trans, |
0c325769 | 1629 | CSR_INT, CSR_INT_BIT_RX_PERIODIC); |
ab697a9f EG |
1630 | } |
1631 | /* Sending RX interrupt require many steps to be done in the | |
1632 | * the device: | |
1633 | * 1- write interrupt to current index in ICT table. | |
1634 | * 2- dma RX frame. | |
1635 | * 3- update RX shared data to indicate last write index. | |
1636 | * 4- send interrupt. | |
1637 | * This could lead to RX race, driver could receive RX interrupt | |
1638 | * but the shared data changes does not reflect this; | |
1639 | * periodic interrupt will detect any dangling Rx activity. | |
1640 | */ | |
1641 | ||
1642 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1042db2a | 1643 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f | 1644 | CSR_INT_PERIODIC_DIS); |
6379103e | 1645 | |
ab697a9f EG |
1646 | /* |
1647 | * Enable periodic interrupt in 8 msec only if we received | |
1648 | * real RX interrupt (instead of just periodic int), to catch | |
1649 | * any dangling Rx interrupt. If it was just the periodic | |
1650 | * interrupt, there was no dangling Rx activity, and no need | |
1651 | * to extend the periodic interrupt; one-shot is enough. | |
1652 | */ | |
1653 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1042db2a | 1654 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
20d3b647 | 1655 | CSR_INT_PERIODIC_ENA); |
ab697a9f | 1656 | |
1f7b6172 | 1657 | isr_stats->rx++; |
f14d6b39 JB |
1658 | |
1659 | local_bh_disable(); | |
2e5d4a8f | 1660 | iwl_pcie_rx_handle(trans, 0); |
f14d6b39 | 1661 | local_bh_enable(); |
ab697a9f EG |
1662 | } |
1663 | ||
1664 | /* This "Tx" DMA channel is used only for loading uCode */ | |
1665 | if (inta & CSR_INT_BIT_FH_TX) { | |
1042db2a | 1666 | iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
0c325769 | 1667 | IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); |
1f7b6172 | 1668 | isr_stats->tx++; |
ab697a9f EG |
1669 | handled |= CSR_INT_BIT_FH_TX; |
1670 | /* Wake up uCode load routine, now that load is complete */ | |
13df1aab JB |
1671 | trans_pcie->ucode_write_complete = true; |
1672 | wake_up(&trans_pcie->ucode_write_waitq); | |
ab697a9f EG |
1673 | } |
1674 | ||
1675 | if (inta & ~handled) { | |
0c325769 | 1676 | IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
1f7b6172 | 1677 | isr_stats->unhandled++; |
ab697a9f EG |
1678 | } |
1679 | ||
0c325769 EG |
1680 | if (inta & ~(trans_pcie->inta_mask)) { |
1681 | IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", | |
1682 | inta & ~trans_pcie->inta_mask); | |
ab697a9f EG |
1683 | } |
1684 | ||
a6bd005f EG |
1685 | /* we are loading the firmware, enable FH_TX interrupt only */ |
1686 | if (handled & CSR_INT_BIT_FH_TX) | |
1687 | iwl_enable_fw_load_int(trans); | |
1688 | /* only Re-enable all interrupt if disabled by irq */ | |
1689 | else if (test_bit(STATUS_INT_ENABLED, &trans->status)) | |
0c325769 | 1690 | iwl_enable_interrupts(trans); |
ab697a9f | 1691 | /* Re-enable RF_KILL if it occurred */ |
8722c899 SG |
1692 | else if (handled & CSR_INT_BIT_RF_KILL) |
1693 | iwl_enable_rfkill_int(trans); | |
2bfb5092 JB |
1694 | |
1695 | out: | |
1696 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
1697 | return IRQ_HANDLED; | |
ab697a9f EG |
1698 | } |
1699 | ||
1a361cd8 EG |
1700 | /****************************************************************************** |
1701 | * | |
1702 | * ICT functions | |
1703 | * | |
1704 | ******************************************************************************/ | |
10667136 | 1705 | |
1a361cd8 | 1706 | /* Free dram table */ |
990aa6d7 | 1707 | void iwl_pcie_free_ict(struct iwl_trans *trans) |
1a361cd8 | 1708 | { |
20d3b647 | 1709 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
0c325769 | 1710 | |
10667136 | 1711 | if (trans_pcie->ict_tbl) { |
1042db2a | 1712 | dma_free_coherent(trans->dev, ICT_SIZE, |
10667136 | 1713 | trans_pcie->ict_tbl, |
0c325769 | 1714 | trans_pcie->ict_tbl_dma); |
10667136 JB |
1715 | trans_pcie->ict_tbl = NULL; |
1716 | trans_pcie->ict_tbl_dma = 0; | |
1a361cd8 EG |
1717 | } |
1718 | } | |
1719 | ||
10667136 JB |
1720 | /* |
1721 | * allocate dram shared table, it is an aligned memory | |
1722 | * block of ICT_SIZE. | |
1a361cd8 EG |
1723 | * also reset all data related to ICT table interrupt. |
1724 | */ | |
990aa6d7 | 1725 | int iwl_pcie_alloc_ict(struct iwl_trans *trans) |
1a361cd8 | 1726 | { |
20d3b647 | 1727 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 | 1728 | |
10667136 | 1729 | trans_pcie->ict_tbl = |
eef31718 | 1730 | dma_zalloc_coherent(trans->dev, ICT_SIZE, |
10667136 JB |
1731 | &trans_pcie->ict_tbl_dma, |
1732 | GFP_KERNEL); | |
1733 | if (!trans_pcie->ict_tbl) | |
1a361cd8 EG |
1734 | return -ENOMEM; |
1735 | ||
10667136 JB |
1736 | /* just an API sanity check ... it is guaranteed to be aligned */ |
1737 | if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { | |
990aa6d7 | 1738 | iwl_pcie_free_ict(trans); |
10667136 JB |
1739 | return -EINVAL; |
1740 | } | |
1a361cd8 | 1741 | |
1a361cd8 EG |
1742 | return 0; |
1743 | } | |
1744 | ||
1745 | /* Device is going up inform it about using ICT interrupt table, | |
1746 | * also we need to tell the driver to start using ICT interrupt. | |
1747 | */ | |
990aa6d7 | 1748 | void iwl_pcie_reset_ict(struct iwl_trans *trans) |
1a361cd8 | 1749 | { |
20d3b647 | 1750 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 | 1751 | u32 val; |
1a361cd8 | 1752 | |
10667136 | 1753 | if (!trans_pcie->ict_tbl) |
ed6a3803 | 1754 | return; |
1a361cd8 | 1755 | |
7b70bd63 | 1756 | spin_lock(&trans_pcie->irq_lock); |
0c325769 | 1757 | iwl_disable_interrupts(trans); |
1a361cd8 | 1758 | |
10667136 | 1759 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
1a361cd8 | 1760 | |
10667136 | 1761 | val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; |
1a361cd8 | 1762 | |
18f5a374 EP |
1763 | val |= CSR_DRAM_INT_TBL_ENABLE | |
1764 | CSR_DRAM_INIT_TBL_WRAP_CHECK | | |
1765 | CSR_DRAM_INIT_TBL_WRITE_POINTER; | |
1a361cd8 | 1766 | |
10667136 | 1767 | IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); |
1a361cd8 | 1768 | |
1042db2a | 1769 | iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); |
0c325769 EG |
1770 | trans_pcie->use_ict = true; |
1771 | trans_pcie->ict_index = 0; | |
1042db2a | 1772 | iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); |
0c325769 | 1773 | iwl_enable_interrupts(trans); |
7b70bd63 | 1774 | spin_unlock(&trans_pcie->irq_lock); |
1a361cd8 EG |
1775 | } |
1776 | ||
1777 | /* Device is going down disable ict interrupt usage */ | |
990aa6d7 | 1778 | void iwl_pcie_disable_ict(struct iwl_trans *trans) |
1a361cd8 | 1779 | { |
20d3b647 | 1780 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 | 1781 | |
7b70bd63 | 1782 | spin_lock(&trans_pcie->irq_lock); |
0c325769 | 1783 | trans_pcie->use_ict = false; |
7b70bd63 | 1784 | spin_unlock(&trans_pcie->irq_lock); |
1a361cd8 EG |
1785 | } |
1786 | ||
85bf9da1 EG |
1787 | irqreturn_t iwl_pcie_isr(int irq, void *data) |
1788 | { | |
1789 | struct iwl_trans *trans = data; | |
1790 | ||
1791 | if (!trans) | |
1792 | return IRQ_NONE; | |
1793 | ||
1794 | /* Disable (but don't clear!) interrupts here to avoid | |
1795 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1796 | * If we have something to service, the tasklet will re-enable ints. | |
1797 | * If we *don't* have something, we'll re-enable before leaving here. | |
1798 | */ | |
1799 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1800 | ||
a0f337cc | 1801 | return IRQ_WAKE_THREAD; |
85bf9da1 | 1802 | } |
2e5d4a8f HD |
1803 | |
1804 | irqreturn_t iwl_pcie_msix_isr(int irq, void *data) | |
1805 | { | |
1806 | return IRQ_WAKE_THREAD; | |
1807 | } | |
1808 | ||
1809 | irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) | |
1810 | { | |
1811 | struct msix_entry *entry = dev_id; | |
1812 | struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); | |
1813 | struct iwl_trans *trans = trans_pcie->trans; | |
46167a8f | 1814 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
2e5d4a8f HD |
1815 | u32 inta_fh, inta_hw; |
1816 | ||
1817 | lock_map_acquire(&trans->sync_cmd_lockdep_map); | |
1818 | ||
1819 | spin_lock(&trans_pcie->irq_lock); | |
1820 | inta_fh = iwl_read_direct32(trans, CSR_MSIX_FH_INT_CAUSES_AD); | |
1821 | inta_hw = iwl_read_direct32(trans, CSR_MSIX_HW_INT_CAUSES_AD); | |
1822 | /* | |
1823 | * Clear causes registers to avoid being handling the same cause. | |
1824 | */ | |
1825 | iwl_write_direct32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); | |
1826 | iwl_write_direct32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); | |
1827 | spin_unlock(&trans_pcie->irq_lock); | |
1828 | ||
1829 | if (unlikely(!(inta_fh | inta_hw))) { | |
1830 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); | |
1831 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
1832 | return IRQ_NONE; | |
1833 | } | |
1834 | ||
1835 | if (iwl_have_debug_level(IWL_DL_ISR)) | |
1836 | IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", | |
1837 | inta_fh, | |
1838 | iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); | |
1839 | ||
1840 | /* This "Tx" DMA channel is used only for loading uCode */ | |
1841 | if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { | |
1842 | IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); | |
1843 | isr_stats->tx++; | |
1844 | /* | |
1845 | * Wake up uCode load routine, | |
1846 | * now that load is complete | |
1847 | */ | |
1848 | trans_pcie->ucode_write_complete = true; | |
1849 | wake_up(&trans_pcie->ucode_write_waitq); | |
1850 | } | |
1851 | ||
1852 | /* Error detected by uCode */ | |
1853 | if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || | |
1854 | (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { | |
1855 | IWL_ERR(trans, | |
1856 | "Microcode SW error detected. Restarting 0x%X.\n", | |
1857 | inta_fh); | |
1858 | isr_stats->sw++; | |
1859 | iwl_pcie_irq_handle_error(trans); | |
1860 | } | |
1861 | ||
1862 | /* After checking FH register check HW register */ | |
1863 | if (iwl_have_debug_level(IWL_DL_ISR)) | |
1864 | IWL_DEBUG_ISR(trans, | |
1865 | "ISR inta_hw 0x%08x, enabled 0x%08x\n", | |
1866 | inta_hw, | |
1867 | iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); | |
1868 | ||
1869 | /* Alive notification via Rx interrupt will do the real work */ | |
1870 | if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { | |
1871 | IWL_DEBUG_ISR(trans, "Alive interrupt\n"); | |
1872 | isr_stats->alive++; | |
1873 | } | |
1874 | ||
1875 | /* uCode wakes up after power-down sleep */ | |
1876 | if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { | |
1877 | IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); | |
1878 | iwl_pcie_rxq_check_wrptr(trans); | |
1879 | iwl_pcie_txq_check_wrptrs(trans); | |
1880 | ||
1881 | isr_stats->wakeup++; | |
1882 | } | |
1883 | ||
1884 | /* Chip got too hot and stopped itself */ | |
1885 | if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { | |
1886 | IWL_ERR(trans, "Microcode CT kill error detected.\n"); | |
1887 | isr_stats->ctkill++; | |
1888 | } | |
1889 | ||
1890 | /* HW RF KILL switch toggled */ | |
1891 | if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) { | |
1892 | bool hw_rfkill; | |
1893 | ||
1894 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1895 | IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", | |
1896 | hw_rfkill ? "disable radio" : "enable radio"); | |
1897 | ||
1898 | isr_stats->rfkill++; | |
1899 | ||
1900 | mutex_lock(&trans_pcie->mutex); | |
1901 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); | |
1902 | mutex_unlock(&trans_pcie->mutex); | |
1903 | if (hw_rfkill) { | |
1904 | set_bit(STATUS_RFKILL, &trans->status); | |
1905 | if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1906 | &trans->status)) | |
1907 | IWL_DEBUG_RF_KILL(trans, | |
1908 | "Rfkill while SYNC HCMD in flight\n"); | |
1909 | wake_up(&trans_pcie->wait_command_queue); | |
1910 | } else { | |
1911 | clear_bit(STATUS_RFKILL, &trans->status); | |
1912 | } | |
1913 | } | |
1914 | ||
1915 | if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { | |
1916 | IWL_ERR(trans, | |
1917 | "Hardware error detected. Restarting.\n"); | |
1918 | ||
1919 | isr_stats->hw++; | |
1920 | iwl_pcie_irq_handle_error(trans); | |
1921 | } | |
1922 | ||
1923 | iwl_pcie_clear_irq(trans, entry); | |
1924 | ||
1925 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
1926 | ||
1927 | return IRQ_HANDLED; | |
1928 | } |