iwlwifi: mvm: set enabled in the PPAG command properly
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2012-2014, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
8ca151b5
JB
9
10#include "iwl-trans.h"
11#include "iwl-op-mode.h"
d962f9b1 12#include "fw/img.h"
8ca151b5
JB
13#include "iwl-debug.h"
14#include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
15#include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
8c23f95c 16#include "iwl-prph.h"
813df5ce 17#include "fw/acpi.h"
b3e4c0f3 18#include "fw/pnvm.h"
8ca151b5
JB
19
20#include "mvm.h"
7174beb6 21#include "fw/dbg.h"
8ca151b5 22#include "iwl-phy-db.h"
9c4f7d51
ST
23#include "iwl-modparams.h"
24#include "iwl-nvm-parse.h"
8ca151b5 25
b3e4c0f3
LC
26#define MVM_UCODE_ALIVE_TIMEOUT (HZ)
27#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5
JB
28
29#define UCODE_VALID_OK cpu_to_le32(0x1)
30
8ca151b5
JB
31struct iwl_mvm_alive_data {
32 bool valid;
33 u32 scd_base_addr;
34};
35
8ca151b5
JB
36static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
37{
38 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
39 .valid = cpu_to_le32(valid_tx_ant),
40 };
41
33223542 42 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 43 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB
44 sizeof(tx_ant_cmd), &tx_ant_cmd);
45}
46
43413a97
SS
47static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
48{
49 int i;
50 struct iwl_rss_config_cmd cmd = {
51 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS
52 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
53 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
54 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
55 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
56 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS
58 };
59
f43495fd
SS
60 if (mvm->trans->num_rx_queues == 1)
61 return 0;
62
854d773e 63 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 64 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS
65 cmd.indirection_table[i] =
66 1 + (i % (mvm->trans->num_rx_queues - 1));
67 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS
68
69 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
70}
71
8edbfaa1
SS
72static int iwl_configure_rxq(struct iwl_mvm *mvm)
73{
dbf592f3 74 int i, num_queues, size, ret;
8edbfaa1 75 struct iwl_rfh_queue_config *cmd;
dbf592f3
JB
76 struct iwl_host_cmd hcmd = {
77 .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD),
78 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
79 };
8edbfaa1 80
64f55156
LC
81 /*
82 * The default queue is configured via context info, so if we
83 * have a single queue, there's nothing to do here.
84 */
85 if (mvm->trans->num_rx_queues == 1)
86 return 0;
87
88 /* skip the default queue */
8edbfaa1
SS
89 num_queues = mvm->trans->num_rx_queues - 1;
90
dbf592f3 91 size = struct_size(cmd, data, num_queues);
8edbfaa1
SS
92
93 cmd = kzalloc(size, GFP_KERNEL);
94 if (!cmd)
95 return -ENOMEM;
96
97 cmd->num_queues = num_queues;
98
99 for (i = 0; i < num_queues; i++) {
100 struct iwl_trans_rxq_dma_data data;
101
102 cmd->data[i].q_num = i + 1;
103 iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data);
104
105 cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb);
106 cmd->data[i].urbd_stts_wrptr =
107 cpu_to_le64(data.urbd_stts_wrptr);
108 cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb);
109 cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid);
110 }
111
dbf592f3
JB
112 hcmd.data[0] = cmd;
113 hcmd.len[0] = size;
114
115 ret = iwl_mvm_send_cmd(mvm, &hcmd);
116
117 kfree(cmd);
118
119 return ret;
8edbfaa1
SS
120}
121
97d5be7e
LK
122static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
123{
124 struct iwl_dqa_enable_cmd dqa_cmd = {
125 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
126 };
127 u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
128 int ret;
129
130 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
131 if (ret)
132 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
133 else
134 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
135
136 return ret;
137}
138
bdccdb85
GBA
139void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
140 struct iwl_rx_cmd_buffer *rxb)
141{
142 struct iwl_rx_packet *pkt = rxb_addr(rxb);
143 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
144 __le32 *dump_data = mfu_dump_notif->data;
145 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
146 int i;
147
148 if (mfu_dump_notif->index_num == 0)
149 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
150 le32_to_cpu(mfu_dump_notif->assert_id));
151
152 for (i = 0; i < n_words; i++)
153 IWL_DEBUG_INFO(mvm,
154 "MFUART assert dump, dword %u: 0x%08x\n",
155 le16_to_cpu(mfu_dump_notif->index_num) *
156 n_words + i,
157 le32_to_cpu(dump_data[i]));
158}
159
8ca151b5
JB
160static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
161 struct iwl_rx_packet *pkt, void *data)
162{
fd1c3318 163 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB
164 struct iwl_mvm *mvm =
165 container_of(notif_wait, struct iwl_mvm, notif_wait);
166 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS
167 struct iwl_umac_alive *umac;
168 struct iwl_lmac_alive *lmac1;
169 struct iwl_lmac_alive *lmac2 = NULL;
170 u16 status;
cfa5d0ca 171 u32 lmac_error_event_table, umac_error_table;
01a9ca51 172
90824f2f
LC
173 /*
174 * For v5 and above, we can check the version, for older
175 * versions we need to check the size.
176 */
b4248c08 177 if (iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
90824f2f
LC
178 UCODE_ALIVE_NTFY, 0) == 5) {
179 struct iwl_alive_ntf_v5 *palive;
180
fd1c3318
JB
181 if (pkt_len < sizeof(*palive))
182 return false;
183
90824f2f
LC
184 palive = (void *)pkt->data;
185 umac = &palive->umac_data;
186 lmac1 = &palive->lmac_data[0];
187 lmac2 = &palive->lmac_data[1];
188 status = le16_to_cpu(palive->status);
189
190 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
191 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
192 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
193
194 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
195 mvm->trans->sku_id[0],
196 mvm->trans->sku_id[1],
197 mvm->trans->sku_id[2]);
198 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC
199 struct iwl_alive_ntf_v4 *palive;
200
fd1c3318
JB
201 if (pkt_len < sizeof(*palive))
202 return false;
203
5c228d63
SS
204 palive = (void *)pkt->data;
205 umac = &palive->umac_data;
206 lmac1 = &palive->lmac_data[0];
207 lmac2 = &palive->lmac_data[1];
208 status = le16_to_cpu(palive->status);
9422b978
LC
209 } else if (iwl_rx_packet_payload_len(pkt) ==
210 sizeof(struct iwl_alive_ntf_v3)) {
211 struct iwl_alive_ntf_v3 *palive3;
212
fd1c3318
JB
213 if (pkt_len < sizeof(*palive3))
214 return false;
215
5c228d63
SS
216 palive3 = (void *)pkt->data;
217 umac = &palive3->umac_data;
218 lmac1 = &palive3->lmac_data;
219 status = le16_to_cpu(palive3->status);
9422b978
LC
220 } else {
221 WARN(1, "unsupported alive notification (size %d)\n",
222 iwl_rx_packet_payload_len(pkt));
223 /* get timeout later */
224 return false;
5c228d63 225 }
01a9ca51 226
22463857
SM
227 lmac_error_event_table =
228 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
229 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
230
5c228d63 231 if (lmac2)
91c28b83 232 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 233 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 234
cfa5d0ca
MG
235 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr);
236
237 if (umac_error_table) {
238 if (umac_error_table >=
239 mvm->trans->cfg->min_umac_error_event_table) {
240 iwl_fw_umac_set_alive_err_table(mvm->trans,
241 umac_error_table);
242 } else {
243 IWL_ERR(mvm,
244 "Not valid error log pointer 0x%08X for %s uCode\n",
245 umac_error_table,
246 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
247 "Init" : "RT");
248 }
3485e76e 249 }
fb5b2846 250
22463857 251 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 252 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 253
5c228d63
SS
254 IWL_DEBUG_FW(mvm,
255 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
256 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 257
5c228d63
SS
258 if (lmac2)
259 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 260
5c228d63
SS
261 IWL_DEBUG_FW(mvm,
262 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
263 le32_to_cpu(umac->umac_major),
264 le32_to_cpu(umac->umac_minor));
8ca151b5 265
0a3a3e9e
SM
266 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
267
8ca151b5
JB
268 return true;
269}
270
1f370650
SS
271static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
272 struct iwl_rx_packet *pkt, void *data)
273{
274 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
275
276 return true;
277}
278
8ca151b5
JB
279static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
280 struct iwl_rx_packet *pkt, void *data)
281{
282 struct iwl_phy_db *phy_db = data;
283
284 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
285 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
286 return true;
287 }
288
ce1f2778 289 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB
290
291 return false;
292}
293
294static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
295 enum iwl_ucode_type ucode_type)
296{
297 struct iwl_notification_wait alive_wait;
94a8d87c 298 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 299 const struct fw_img *fw;
cfbc6c4c 300 int ret;
702e975d 301 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 302 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG
303 bool run_in_rfkill =
304 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
8ca151b5 305
61df750c 306 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA
307 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
308 !(fw_has_capa(&mvm->fw->ucode_capa,
309 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 310 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 311 else
612da1ef 312 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 313 if (WARN_ON(!fw))
8ca151b5 314 return -EINVAL;
702e975d 315 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 316 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB
317
318 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
319 alive_cmd, ARRAY_SIZE(alive_cmd),
320 iwl_alive_fn, &alive_data);
321
b3500b47
EG
322 /*
323 * We want to load the INIT firmware even in RFKILL
324 * For the unified firmware case, the ucode_type is not
325 * INIT, but we still need to run it.
326 */
327 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 328 if (ret) {
702e975d 329 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
330 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
331 return ret;
332 }
333
334 /*
335 * Some things may run in the background now, but we
336 * just wait for the ALIVE notification here.
337 */
338 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
339 MVM_UCODE_ALIVE_TIMEOUT);
340 if (ret) {
d6be9c1d
SS
341 struct iwl_trans *trans = mvm->trans;
342
20f5aef5
JB
343 if (trans->trans_cfg->device_family >=
344 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS
345 IWL_ERR(mvm,
346 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST
347 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
348 iwl_read_umac_prph(trans,
349 UMAG_SB_CPU_2_STATUS));
20f5aef5
JB
350 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
351 iwl_read_umac_prph(trans,
352 UREG_UMAC_CURRENT_PC));
353 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
354 iwl_read_umac_prph(trans,
355 UREG_LMAC1_CURRENT_PC));
356 if (iwl_mvm_is_cdb_supported(mvm))
357 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
358 iwl_read_umac_prph(trans,
359 UREG_LMAC2_CURRENT_PC));
360 } else if (trans->trans_cfg->device_family >=
361 IWL_DEVICE_FAMILY_8000) {
192de2b4
DS
362 IWL_ERR(mvm,
363 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
d6be9c1d
SS
364 iwl_read_prph(trans, SB_CPU_1_STATUS),
365 iwl_read_prph(trans, SB_CPU_2_STATUS));
20f5aef5
JB
366 }
367
368 if (ret == -ETIMEDOUT)
369 iwl_fw_dbg_error_collect(&mvm->fwrt,
370 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
371
702e975d 372 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
373 return ret;
374 }
375
376 if (!alive_data.valid) {
377 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 378 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
379 return -EIO;
380 }
381
b3e4c0f3 382 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait);
70d3ca86
LC
383 if (ret) {
384 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
385 iwl_fw_set_current_image(&mvm->fwrt, old_type);
386 return ret;
387 }
388
8ca151b5
JB
389 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
390
391 /*
392 * Note: all the queues are enabled as part of the interface
393 * initialization, but in firmware restart scenarios they
394 * could be stopped, so wake them up. In firmware restart,
395 * mac80211 will have the queues stopped as well until the
396 * reconfiguration completes. During normal startup, they
397 * will be empty.
398 */
399
4ecafae9 400 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB
401 /*
402 * Set a 'fake' TID for the command queue, since we use the
403 * hweight() of the tid_bitmap as a refcount now. Not that
404 * we ever even consider the command queue as one we might
405 * want to reuse, but be safe nevertheless.
406 */
407 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
408 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 409
65b280fe 410 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC
411#ifdef CONFIG_IWLWIFI_DEBUGFS
412 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
413#endif
8ca151b5 414
d3d9b4fc
EG
415 /*
416 * All the BSSes in the BSS table include the GP2 in the system
417 * at the beacon Rx time, this is of course no longer relevant
418 * since we are resetting the firmware.
419 * Purge all the BSS table.
420 */
421 cfg80211_bss_flush(mvm->hw->wiphy);
422
8ca151b5
JB
423 return 0;
424}
8ca151b5 425
52b15521 426static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
8c5f47b1
JB
427{
428 struct iwl_notification_wait init_wait;
429 struct iwl_nvm_access_complete_cmd nvm_complete = {};
430 struct iwl_init_extended_cfg_cmd init_cfg = {
431 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
432 };
433 static const u16 init_complete[] = {
434 INIT_COMPLETE_NOTIF,
435 };
436 int ret;
437
a4584729
HD
438 if (mvm->trans->cfg->tx_with_siso_diversity)
439 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
440
8c5f47b1
JB
441 lockdep_assert_held(&mvm->mutex);
442
94022562
EG
443 mvm->rfkill_safe_init_done = false;
444
8c5f47b1
JB
445 iwl_init_notification_wait(&mvm->notif_wait,
446 &init_wait,
447 init_complete,
448 ARRAY_SIZE(init_complete),
449 iwl_wait_init_complete,
450 NULL);
451
b108d8c7 452 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
86ce5c74 453
8c5f47b1
JB
454 /* Will also start the device */
455 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
456 if (ret) {
457 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
458 goto error;
459 }
b108d8c7
SM
460 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
461 NULL);
8c5f47b1
JB
462
463 /* Send init config command to mark that we are sending NVM access
464 * commands
465 */
466 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
b3500b47
EG
467 INIT_EXTENDED_CFG_CMD),
468 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
469 sizeof(init_cfg), &init_cfg);
470 if (ret) {
471 IWL_ERR(mvm, "Failed to run init config command: %d\n",
472 ret);
473 goto error;
474 }
475
e9e1ba3d
SS
476 /* Load NVM to NIC if needed */
477 if (mvm->nvm_file_name) {
9c4f7d51
ST
478 iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
479 mvm->nvm_sections);
8c5f47b1 480 iwl_mvm_load_nvm_to_nic(mvm);
e9e1ba3d 481 }
8c5f47b1 482
52b15521 483 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
5bd1d2c1 484 ret = iwl_nvm_init(mvm);
d4f3695e
SS
485 if (ret) {
486 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
487 goto error;
488 }
489 }
490
8c5f47b1 491 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
b3500b47
EG
492 NVM_ACCESS_COMPLETE),
493 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
494 sizeof(nvm_complete), &nvm_complete);
495 if (ret) {
496 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
497 ret);
498 goto error;
499 }
500
501 /* We wait for the INIT complete notification */
e9e1ba3d
SS
502 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
503 MVM_UCODE_ALIVE_TIMEOUT);
504 if (ret)
505 return ret;
506
507 /* Read the NVM only at driver load time, no need to do this twice */
52b15521 508 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
4c625c56 509 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
c135cb56
ST
510 if (IS_ERR(mvm->nvm_data)) {
511 ret = PTR_ERR(mvm->nvm_data);
512 mvm->nvm_data = NULL;
e9e1ba3d
SS
513 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
514 return ret;
515 }
516 }
517
b3500b47
EG
518 mvm->rfkill_safe_init_done = true;
519
e9e1ba3d 520 return 0;
8c5f47b1
JB
521
522error:
523 iwl_remove_notification(&mvm->notif_wait, &init_wait);
524 return ret;
525}
526
c4ace426
GA
527#ifdef CONFIG_ACPI
528static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
529 struct iwl_phy_specific_cfg *phy_filters)
530{
531 /*
532 * TODO: read specific phy config from BIOS
533 * ACPI table for this feature has not been defined yet,
534 * so for now we use hardcoded values.
535 */
536
537 if (IWL_MVM_PHY_FILTER_CHAIN_A) {
538 phy_filters->filter_cfg_chain_a =
539 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
540 }
541 if (IWL_MVM_PHY_FILTER_CHAIN_B) {
542 phy_filters->filter_cfg_chain_b =
543 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
544 }
545 if (IWL_MVM_PHY_FILTER_CHAIN_C) {
546 phy_filters->filter_cfg_chain_c =
547 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
548 }
549 if (IWL_MVM_PHY_FILTER_CHAIN_D) {
550 phy_filters->filter_cfg_chain_d =
551 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
552 }
553}
554
555#else /* CONFIG_ACPI */
556
557static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
558 struct iwl_phy_specific_cfg *phy_filters)
559{
560}
561#endif /* CONFIG_ACPI */
562
8ca151b5
JB
563static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
564{
c4ace426 565 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 566 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA
567 struct iwl_phy_specific_cfg phy_filters = {};
568 u8 cmd_ver;
569 size_t cmd_size;
8ca151b5 570
bb99ff9b 571 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 572 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 573 return 0;
d923b020
LC
574
575 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC
576 /*
577 * TODO: currently we don't set the antenna but letting the NIC
578 * to decide which antenna to use. This should come from BIOS.
579 */
580 phy_cfg_cmd.phy_cfg =
581 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
582 }
583
8ca151b5 584 /* Set parameters */
a0544272 585 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC
586
587 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC
588 phy_cfg_cmd.phy_cfg |=
589 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 590
8ca151b5
JB
591 phy_cfg_cmd.calib_control.event_trigger =
592 mvm->fw->default_calib[ucode_type].event_trigger;
593 phy_cfg_cmd.calib_control.flow_trigger =
594 mvm->fw->default_calib[ucode_type].flow_trigger;
595
c4ace426 596 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP,
e80bfd11
MG
597 PHY_CONFIGURATION_CMD,
598 IWL_FW_CMD_VER_UNKNOWN);
c4ace426
GA
599 if (cmd_ver == 3) {
600 iwl_mvm_phy_filter_init(mvm, &phy_filters);
601 memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
602 sizeof(struct iwl_phy_specific_cfg));
603 }
604
8ca151b5
JB
605 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
606 phy_cfg_cmd.phy_cfg);
c4ace426
GA
607 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
608 sizeof(struct iwl_phy_cfg_cmd_v1);
a1022927 609 return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
c4ace426 610 cmd_size, &phy_cfg_cmd);
8ca151b5
JB
611}
612
3b25f1af 613int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB
614{
615 struct iwl_notification_wait calib_wait;
6eb031d2 616 static const u16 init_complete[] = {
8ca151b5
JB
617 INIT_COMPLETE_NOTIF,
618 CALIB_RES_NOTIF_PHY_DB
619 };
620 int ret;
621
7d6222e2 622 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 623 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 624
8ca151b5
JB
625 lockdep_assert_held(&mvm->mutex);
626
94022562 627 mvm->rfkill_safe_init_done = false;
8ca151b5
JB
628
629 iwl_init_notification_wait(&mvm->notif_wait,
630 &calib_wait,
631 init_complete,
632 ARRAY_SIZE(init_complete),
633 iwl_wait_phy_db_entry,
634 mvm->phy_db);
635
11f8c533
LC
636 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
637
8ca151b5
JB
638 /* Will also start the device */
639 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
640 if (ret) {
641 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 642 goto remove_notif;
8ca151b5
JB
643 }
644
7d34a7d7 645 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG
646 ret = iwl_mvm_send_bt_init_conf(mvm);
647 if (ret)
00e0c6c8 648 goto remove_notif;
b3de3ef4 649 }
931d4160 650
81a67e32 651 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 652 if (!mvm->nvm_data) {
5bd1d2c1 653 ret = iwl_nvm_init(mvm);
8ca151b5
JB
654 if (ret) {
655 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 656 goto remove_notif;
8ca151b5
JB
657 }
658 }
659
81a67e32 660 /* In case we read the NVM from external file, load it to the NIC */
e02a9d60 661 if (mvm->nvm_file_name)
81a67e32
EL
662 iwl_mvm_load_nvm_to_nic(mvm);
663
64866e5d
LC
664 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
665 "Too old NVM version (0x%0x, required = 0x%0x)",
666 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 667
4f59334b
EH
668 /*
669 * abort after reading the nvm in case RF Kill is on, we will complete
670 * the init seq later when RF kill will switch to off
671 */
1a3fe0b2 672 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH
673 IWL_DEBUG_RF_KILL(mvm,
674 "jump over all phy activities due to RF kill\n");
00e0c6c8 675 goto remove_notif;
4f59334b
EH
676 }
677
b3500b47 678 mvm->rfkill_safe_init_done = true;
31b8b343 679
e07cbb53 680 /* Send TX valid antennas before triggering calibrations */
a0544272 681 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 682 if (ret)
00e0c6c8 683 goto remove_notif;
e07cbb53 684
8ca151b5
JB
685 ret = iwl_send_phy_cfg_cmd(mvm);
686 if (ret) {
687 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
688 ret);
00e0c6c8 689 goto remove_notif;
8ca151b5
JB
690 }
691
692 /*
693 * Some things may run in the background now, but we
694 * just wait for the calibration complete notification.
695 */
696 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC
697 MVM_UCODE_CALIB_TIMEOUT);
698 if (!ret)
699 goto out;
31b8b343 700
00e0c6c8 701 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 702 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC
703 ret = 0;
704 } else {
705 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
706 ret);
31b8b343 707 }
00e0c6c8 708
8ca151b5
JB
709 goto out;
710
00e0c6c8 711remove_notif:
8ca151b5
JB
712 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
713out:
b3500b47 714 mvm->rfkill_safe_init_done = false;
a4082843 715 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB
716 /* we want to debug INIT and we have no NVM - fake */
717 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
718 sizeof(struct ieee80211_channel) +
719 sizeof(struct ieee80211_rate),
720 GFP_KERNEL);
721 if (!mvm->nvm_data)
722 return -ENOMEM;
8ca151b5
JB
723 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
724 mvm->nvm_data->bands[0].n_channels = 1;
725 mvm->nvm_data->bands[0].n_bitrates = 1;
726 mvm->nvm_data->bands[0].bitrates =
727 (void *)mvm->nvm_data->channels + 1;
728 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
729 }
730
731 return ret;
732}
733
84bfffa9
EG
734static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
735{
736 struct iwl_ltr_config_cmd cmd = {
737 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
738 };
739
740 if (!mvm->trans->ltr_enabled)
741 return 0;
742
84bfffa9
EG
743 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
744 sizeof(cmd), &cmd);
745}
746
c386dacb 747#ifdef CONFIG_ACPI
42ce76d6 748int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 749{
216cdfb5
LC
750 struct iwl_dev_tx_power_cmd cmd = {
751 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 752 };
9c08cef8 753 __le16 *per_chain;
1edd56e6 754 int ret;
39c1a972 755 u16 len = 0;
fbb7957d
LC
756 u32 n_subbands;
757 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP,
e80bfd11
MG
758 REDUCE_TX_POWER_CMD,
759 IWL_FW_CMD_VER_UNKNOWN);
fbb7957d
LC
760
761 if (cmd_ver == 6) {
762 len = sizeof(cmd.v6);
763 n_subbands = IWL_NUM_SUB_BANDS_V2;
764 per_chain = cmd.v6.per_chain[0][0];
765 } else if (fw_has_api(&mvm->fw->ucode_capa,
766 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 767 len = sizeof(cmd.v5);
fbb7957d 768 n_subbands = IWL_NUM_SUB_BANDS;
9c08cef8
LC
769 per_chain = cmd.v5.per_chain[0][0];
770 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 771 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 772 len = sizeof(cmd.v4);
fbb7957d 773 n_subbands = IWL_NUM_SUB_BANDS;
9c08cef8
LC
774 per_chain = cmd.v4.per_chain[0][0];
775 } else {
216cdfb5 776 len = sizeof(cmd.v3);
fbb7957d 777 n_subbands = IWL_NUM_SUB_BANDS;
9c08cef8
LC
778 per_chain = cmd.v3.per_chain[0][0];
779 }
55bfa4b9 780
216cdfb5
LC
781 /* all structs have the same common part, add it */
782 len += sizeof(cmd.common);
da2830ac 783
9c08cef8 784 ret = iwl_sar_select_profile(&mvm->fwrt, per_chain, ACPI_SAR_NUM_TABLES,
fbb7957d 785 n_subbands, prof_a, prof_b);
1edd56e6
LC
786
787 /* return on error or if the profile is disabled (positive number) */
788 if (ret)
789 return ret;
790
42ce76d6 791 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
42ce76d6
LC
792 return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
793}
794
7fe90e0e
HD
795int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
796{
dd2a1256 797 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 798 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 799 u16 len;
39c1a972 800 int ret;
0c3d7282 801 struct iwl_host_cmd cmd;
e80bfd11
MG
802 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP,
803 GEO_TX_POWER_LIMIT,
804 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 805
dd2a1256
LC
806 /* the ops field is at the same spot for all versions, so set in v1 */
807 geo_tx_cmd.v1.ops =
808 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
809
0ea788ed
LC
810 if (cmd_ver == 3)
811 len = sizeof(geo_tx_cmd.v3);
812 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
813 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC
814 len = sizeof(geo_tx_cmd.v2);
815 else
816 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 817
39c1a972
IZ
818 if (!iwl_sar_geo_support(&mvm->fwrt))
819 return -EOPNOTSUPP;
820
0c3d7282 821 cmd = (struct iwl_host_cmd){
7fe90e0e 822 .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT),
0c3d7282 823 .len = { len, },
7fe90e0e 824 .flags = CMD_WANT_SKB,
39c1a972 825 .data = { &geo_tx_cmd },
7fe90e0e
HD
826 };
827
828 ret = iwl_mvm_send_cmd(mvm, &cmd);
829 if (ret) {
830 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
831 return ret;
832 }
f604324e
LC
833
834 resp = (void *)cmd.resp_pkt->data;
835 ret = le32_to_cpu(resp->profile_idx);
836
837 if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES))
838 ret = -EIO;
839
7fe90e0e
HD
840 iwl_free_resp(&cmd);
841 return ret;
842}
843
a6bff3cb
HD
844static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
845{
dd2a1256 846 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 847 u16 len;
45acebf8 848 u32 n_bands;
0433ae55 849 int ret;
e80bfd11
MG
850 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP,
851 GEO_TX_POWER_LIMIT,
852 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 853
45acebf8
NG
854 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
855 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
856 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
857 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops));
dd2a1256
LC
858 /* the ops field is at the same spot for all versions, so set in v1 */
859 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 860
0ea788ed
LC
861 if (cmd_ver == 3) {
862 len = sizeof(cmd.v3);
45acebf8 863 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
0ea788ed
LC
864 cmd.v3.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
865 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
866 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 867 len = sizeof(cmd.v2);
45acebf8 868 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
dd2a1256 869 cmd.v2.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
39c1a972 870 } else {
dd2a1256 871 len = sizeof(cmd.v1);
45acebf8 872 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
0c3d7282
HD
873 }
874
45acebf8
NG
875 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
876 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
877 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
878 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table));
879 /* the table is at the same position for all versions, so set use v1 */
880 ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0], n_bands);
881
882 /*
883 * It is a valid scenario to not support SAR, or miss wgds table,
884 * but in that case there is no need to send the command.
885 */
886 if (ret)
887 return 0;
888
dd2a1256
LC
889 return iwl_mvm_send_cmd_pdu(mvm,
890 WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT),
891 0, len, &cmd);
a6bff3cb
HD
892}
893
6ce1e5c0
GA
894static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm)
895{
896 union acpi_object *wifi_pkg, *data, *enabled;
f2134f66
GA
897 union iwl_ppag_table_cmd ppag_table;
898 int i, j, ret, tbl_rev, num_sub_bands;
6ce1e5c0 899 int idx = 2;
f2134f66 900 s8 *gain;
6ce1e5c0 901
f2134f66
GA
902 /*
903 * The 'enabled' field is the same in v1 and v2 so we can just
904 * use v1 to access it.
905 */
906 mvm->fwrt.ppag_table.v1.enabled = cpu_to_le32(0);
6ce1e5c0
GA
907 data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD);
908 if (IS_ERR(data))
909 return PTR_ERR(data);
910
f2134f66 911 /* try to read ppag table revision 1 */
6ce1e5c0 912 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
f2134f66
GA
913 ACPI_PPAG_WIFI_DATA_SIZE_V2, &tbl_rev);
914 if (!IS_ERR(wifi_pkg)) {
915 if (tbl_rev != 1) {
916 ret = -EINVAL;
917 goto out_free;
918 }
919 num_sub_bands = IWL_NUM_SUB_BANDS_V2;
920 gain = mvm->fwrt.ppag_table.v2.gain[0];
921 mvm->fwrt.ppag_ver = 2;
922 IWL_DEBUG_RADIO(mvm, "Reading PPAG table v2 (tbl_rev=1)\n");
923 goto read_table;
6ce1e5c0
GA
924 }
925
f2134f66
GA
926 /* try to read ppag table revision 0 */
927 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
928 ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev);
929 if (!IS_ERR(wifi_pkg)) {
930 if (tbl_rev != 0) {
931 ret = -EINVAL;
932 goto out_free;
933 }
934 num_sub_bands = IWL_NUM_SUB_BANDS;
935 gain = mvm->fwrt.ppag_table.v1.gain[0];
936 mvm->fwrt.ppag_ver = 1;
937 IWL_DEBUG_RADIO(mvm, "Reading PPAG table v1 (tbl_rev=0)\n");
938 goto read_table;
3ed83da3 939 }
f2134f66
GA
940 ret = PTR_ERR(wifi_pkg);
941 goto out_free;
3ed83da3 942
f2134f66 943read_table:
6ce1e5c0
GA
944 enabled = &wifi_pkg->package.elements[1];
945 if (enabled->type != ACPI_TYPE_INTEGER ||
946 (enabled->integer.value != 0 && enabled->integer.value != 1)) {
947 ret = -EINVAL;
948 goto out_free;
949 }
950
f2134f66
GA
951 ppag_table.v1.enabled = cpu_to_le32(enabled->integer.value);
952 if (!ppag_table.v1.enabled) {
6ce1e5c0
GA
953 ret = 0;
954 goto out_free;
955 }
956
957 /*
958 * read, verify gain values and save them into the PPAG table.
959 * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the
960 * following sub-bands to High-Band (5GHz).
961 */
f2134f66
GA
962 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
963 for (j = 0; j < num_sub_bands; j++) {
6ce1e5c0
GA
964 union acpi_object *ent;
965
966 ent = &wifi_pkg->package.elements[idx++];
967 if (ent->type != ACPI_TYPE_INTEGER ||
968 (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) ||
969 (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) ||
970 (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) ||
971 (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) {
f2134f66 972 ppag_table.v1.enabled = cpu_to_le32(0);
6ce1e5c0
GA
973 ret = -EINVAL;
974 goto out_free;
975 }
f2134f66 976 gain[i * num_sub_bands + j] = ent->integer.value;
6ce1e5c0
GA
977 }
978 }
979 ret = 0;
980out_free:
981 kfree(data);
982 return ret;
983}
984
985int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
986{
f2134f66
GA
987 u8 cmd_ver;
988 int i, j, ret, num_sub_bands, cmd_size;
989 union iwl_ppag_table_cmd ppag_table;
990 s8 *gain;
6ce1e5c0
GA
991
992 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
993 IWL_DEBUG_RADIO(mvm,
994 "PPAG capability not supported by FW, command not sent.\n");
995 return 0;
996 }
f2134f66
GA
997 if (!mvm->fwrt.ppag_table.v1.enabled) {
998 IWL_DEBUG_RADIO(mvm, "PPAG not enabled, command not sent.\n");
160bab43
GA
999 return 0;
1000 }
1001
efaa85cf
LC
1002 ppag_table.v1.enabled = mvm->fwrt.ppag_table.v1.enabled;
1003
f2134f66 1004 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP,
e80bfd11
MG
1005 PER_PLATFORM_ANT_GAIN_CMD,
1006 IWL_FW_CMD_VER_UNKNOWN);
f2134f66
GA
1007 if (cmd_ver == 1) {
1008 num_sub_bands = IWL_NUM_SUB_BANDS;
1009 gain = mvm->fwrt.ppag_table.v1.gain[0];
1010 cmd_size = sizeof(ppag_table.v1);
1011 if (mvm->fwrt.ppag_ver == 2) {
1012 IWL_DEBUG_RADIO(mvm,
1013 "PPAG table is v2 but FW supports v1, sending truncated table\n");
1014 }
1015 } else if (cmd_ver == 2) {
1016 num_sub_bands = IWL_NUM_SUB_BANDS_V2;
1017 gain = mvm->fwrt.ppag_table.v2.gain[0];
1018 cmd_size = sizeof(ppag_table.v2);
1019 if (mvm->fwrt.ppag_ver == 1) {
1020 IWL_DEBUG_RADIO(mvm,
1021 "PPAG table is v1 but FW supports v2, sending padded table\n");
1022 }
1023 } else {
1024 IWL_DEBUG_RADIO(mvm, "Unsupported PPAG command version\n");
1025 return 0;
1026 }
6ce1e5c0 1027
f2134f66
GA
1028 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
1029 for (j = 0; j < num_sub_bands; j++) {
6ce1e5c0
GA
1030 IWL_DEBUG_RADIO(mvm,
1031 "PPAG table: chain[%d] band[%d]: gain = %d\n",
f2134f66 1032 i, j, gain[i * num_sub_bands + j]);
6ce1e5c0
GA
1033 }
1034 }
f2134f66 1035 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA
1036 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1037 PER_PLATFORM_ANT_GAIN_CMD),
f2134f66 1038 0, cmd_size, &ppag_table);
6ce1e5c0
GA
1039 if (ret < 0)
1040 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1041 ret);
1042
1043 return ret;
1044}
1045
1046static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1047{
1048 int ret;
1049
1050 ret = iwl_mvm_get_ppag_table(mvm);
1051 if (ret < 0) {
1052 IWL_DEBUG_RADIO(mvm,
1053 "PPAG BIOS table invalid or unavailable. (%d)\n",
1054 ret);
1055 return 0;
1056 }
1057 return iwl_mvm_ppag_send_cmd(mvm);
1058}
1059
28dd7ccd
MG
1060static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1061{
1062 int ret;
1063 struct iwl_tas_config_cmd cmd = {};
1064 int list_size;
1065
cdaba917 1066 BUILD_BUG_ON(ARRAY_SIZE(cmd.block_list_array) <
28dd7ccd
MG
1067 APCI_WTAS_BLACK_LIST_MAX);
1068
1069 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1070 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1071 return;
1072 }
1073
cdaba917 1074 ret = iwl_acpi_get_tas(&mvm->fwrt, cmd.block_list_array, &list_size);
28dd7ccd
MG
1075 if (ret < 0) {
1076 IWL_DEBUG_RADIO(mvm,
1077 "TAS table invalid or unavailable. (%d)\n",
1078 ret);
1079 return;
1080 }
1081
1082 if (list_size < 0)
1083 return;
1084
1085 /* list size if TAS enabled can only be non-negative */
cdaba917 1086 cmd.block_list_size = cpu_to_le32((u32)list_size);
28dd7ccd
MG
1087
1088 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
1089 TAS_CONFIG),
1090 0, sizeof(cmd), &cmd);
1091 if (ret < 0)
1092 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1093}
f5b1cb2e 1094
02d31e9b 1095static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm)
f5b1cb2e
GA
1096{
1097 int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
1098 DSM_FUNC_ENABLE_INDONESIA_5G2);
1099
02d31e9b
GA
1100 if (ret < 0)
1101 IWL_DEBUG_RADIO(mvm,
1102 "Failed to evaluate DSM function ENABLE_INDONESIA_5G2, ret=%d\n",
1103 ret);
f5b1cb2e 1104
02d31e9b
GA
1105 else if (ret >= DSM_VALUE_INDONESIA_MAX)
1106 IWL_DEBUG_RADIO(mvm,
1107 "DSM function ENABLE_INDONESIA_5G2 return invalid value, ret=%d\n",
1108 ret);
1109
1110 else if (ret == DSM_VALUE_INDONESIA_ENABLE) {
1111 IWL_DEBUG_RADIO(mvm,
1112 "Evaluated DSM function ENABLE_INDONESIA_5G2: Enabling 5g2\n");
1113 return DSM_VALUE_INDONESIA_ENABLE;
1114 }
1115 /* default behaviour is disabled */
1116 return DSM_VALUE_INDONESIA_DISABLE;
1117}
1118
1119static u8 iwl_mvm_eval_dsm_disable_srd(struct iwl_mvm *mvm)
1120{
1121 int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
1122 DSM_FUNC_DISABLE_SRD);
1123
1124 if (ret < 0)
1125 IWL_DEBUG_RADIO(mvm,
1126 "Failed to evaluate DSM function DISABLE_SRD, ret=%d\n",
1127 ret);
1128
1129 else if (ret >= DSM_VALUE_SRD_MAX)
1130 IWL_DEBUG_RADIO(mvm,
1131 "DSM function DISABLE_SRD return invalid value, ret=%d\n",
1132 ret);
1133
1134 else if (ret == DSM_VALUE_SRD_PASSIVE) {
1135 IWL_DEBUG_RADIO(mvm,
1136 "Evaluated DSM function DISABLE_SRD: setting SRD to passive\n");
1137 return DSM_VALUE_SRD_PASSIVE;
1138
1139 } else if (ret == DSM_VALUE_SRD_DISABLE) {
1140 IWL_DEBUG_RADIO(mvm,
1141 "Evaluated DSM function DISABLE_SRD: disabling SRD\n");
1142 return DSM_VALUE_SRD_DISABLE;
1143 }
1144 /* default behaviour is active */
1145 return DSM_VALUE_SRD_ACTIVE;
f5b1cb2e
GA
1146}
1147
1148static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1149{
02d31e9b
GA
1150 u8 ret;
1151 int cmd_ret;
f5b1cb2e
GA
1152 struct iwl_lari_config_change_cmd cmd = {};
1153
02d31e9b 1154 if (iwl_mvm_eval_dsm_indonesia_5g2(mvm) == DSM_VALUE_INDONESIA_ENABLE)
f5b1cb2e
GA
1155 cmd.config_bitmap |=
1156 cpu_to_le32(LARI_CONFIG_ENABLE_5G2_IN_INDONESIA_MSK);
1157
02d31e9b
GA
1158 ret = iwl_mvm_eval_dsm_disable_srd(mvm);
1159 if (ret == DSM_VALUE_SRD_PASSIVE)
1160 cmd.config_bitmap |=
1161 cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_PASSIVE_MSK);
1162
1163 else if (ret == DSM_VALUE_SRD_DISABLE)
1164 cmd.config_bitmap |=
1165 cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_DISABLED_MSK);
1166
f5b1cb2e
GA
1167 /* apply more config masks here */
1168
1169 if (cmd.config_bitmap) {
02d31e9b
GA
1170 IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE\n");
1171 cmd_ret = iwl_mvm_send_cmd_pdu(mvm,
1172 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1173 LARI_CONFIG_CHANGE),
1174 0, sizeof(cmd), &cmd);
1175 if (cmd_ret < 0)
f5b1cb2e
GA
1176 IWL_DEBUG_RADIO(mvm,
1177 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
02d31e9b 1178 cmd_ret);
f5b1cb2e
GA
1179 }
1180}
69964905 1181#else /* CONFIG_ACPI */
69964905 1182
39c1a972
IZ
1183inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1184 int prof_a, int prof_b)
69964905
LC
1185{
1186 return -ENOENT;
1187}
a6bff3cb 1188
39c1a972 1189inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC
1190{
1191 return -ENOENT;
1192}
1193
a6bff3cb
HD
1194static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1195{
1196 return 0;
1197}
18f1755d 1198
6ce1e5c0
GA
1199int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1200{
1201 return -ENOENT;
1202}
1203
1204static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1205{
7937fd32 1206 return 0;
6ce1e5c0 1207}
28dd7ccd
MG
1208
1209static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1210{
1211}
f5b1cb2e
GA
1212
1213static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1214{
1215}
69964905
LC
1216#endif /* CONFIG_ACPI */
1217
f130bb75
MG
1218void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1219{
1220 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1221 int ret;
1222 u32 resp;
1223
1224 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1225 .flags = cpu_to_le32(flags),
1226 .buf_size = 0,
1227 };
1228 struct iwl_host_cmd host_cmd = {
1229 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1230 .flags = CMD_WANT_SKB,
1231 .data = {&recovery_cmd, },
1232 .len = {sizeof(recovery_cmd), },
1233 };
1234
1235 /* no error log was defined in TLV */
1236 if (!error_log_size)
1237 return;
1238
1239 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1240 /* no buf was allocated while HW reset */
1241 if (!mvm->error_recovery_buf)
1242 return;
1243
1244 host_cmd.data[1] = mvm->error_recovery_buf;
1245 host_cmd.len[1] = error_log_size;
1246 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1247 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1248 }
1249
1250 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1251 kfree(mvm->error_recovery_buf);
1252 mvm->error_recovery_buf = NULL;
1253
1254 if (ret) {
1255 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1256 return;
1257 }
1258
1259 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1260 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1261 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1262 if (resp)
1263 IWL_ERR(mvm,
1264 "Failed to send recovery cmd blob was invalid %d\n",
1265 resp);
1266 }
1267}
1268
42ce76d6
LC
1269static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1270{
1271 int ret;
1272
39c1a972 1273 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
42ce76d6
LC
1274 if (ret < 0) {
1275 IWL_DEBUG_RADIO(mvm,
69964905 1276 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
42ce76d6 1277 ret);
5d041c46
LC
1278 /*
1279 * If not available, don't fail and don't bother with EWRD.
1280 * Return 1 to tell that we can't use WGDS either.
1281 */
1282 return 1;
42ce76d6
LC
1283 }
1284
39c1a972 1285 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
69964905
LC
1286 /* if EWRD is not available, we can still use WRDS, so don't fail */
1287 if (ret < 0)
1288 IWL_DEBUG_RADIO(mvm,
1289 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1290 ret);
1291
1edd56e6 1292 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC
1293}
1294
1f370650 1295static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1296{
1f370650 1297 int ret;
8ca151b5 1298
7d6222e2 1299 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1300 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1301
3b25f1af
EG
1302 WARN_ON(!mvm->nvm_data);
1303 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1304
f2082a53 1305 if (ret) {
8d193ca2 1306 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK
1307
1308 if (iwlmvm_mod_params.init_dbg)
1309 return 0;
1f370650 1310 return ret;
8d193ca2 1311 }
8ca151b5 1312
203c83d3 1313 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG
1314 iwl_trans_stop_device(mvm->trans);
1315 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1316 if (ret)
1f370650 1317 return ret;
8ca151b5 1318
94022562 1319 mvm->rfkill_safe_init_done = false;
8ca151b5 1320 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS
1321 if (ret)
1322 return ret;
1323
94022562
EG
1324 mvm->rfkill_safe_init_done = true;
1325
b108d8c7
SM
1326 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1327 NULL);
da2eb669 1328
702e975d 1329 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS
1330}
1331
1332int iwl_mvm_up(struct iwl_mvm *mvm)
1333{
1334 int ret, i;
1335 struct ieee80211_channel *chan;
1336 struct cfg80211_chan_def chandef;
dd36a507 1337 struct ieee80211_supported_band *sband = NULL;
1f370650
SS
1338
1339 lockdep_assert_held(&mvm->mutex);
1340
1341 ret = iwl_trans_start_hw(mvm->trans);
1342 if (ret)
1343 return ret;
1344
1345 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB
1346 if (ret) {
1347 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
72d3c7bb
JB
1348 if (ret != -ERFKILL)
1349 iwl_fw_dbg_error_collect(&mvm->fwrt,
1350 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB
1351 goto error;
1352 }
1353
d0b813fc 1354 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1355
1f3b0ff8
LE
1356 ret = iwl_mvm_sf_update(mvm, NULL, false);
1357 if (ret)
1358 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1359
a1af4c48 1360 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS
1361 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1362 /* if we have a destination, assume EARLY START */
1363 if (mvm->fw->dbg.dest_tlv)
1364 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1365 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1366 }
6a951267 1367
a0544272 1368 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1369 if (ret)
1370 goto error;
1371
7d6222e2
JB
1372 if (!iwl_mvm_has_unified_ucode(mvm)) {
1373 /* Send phy db control command and then phy db calibration */
1f370650
SS
1374 ret = iwl_send_phy_db_data(mvm->phy_db);
1375 if (ret)
1376 goto error;
1f370650 1377 }
8ca151b5 1378
bb99ff9b
LC
1379 ret = iwl_send_phy_cfg_cmd(mvm);
1380 if (ret)
1381 goto error;
1382
b3de3ef4
EG
1383 ret = iwl_mvm_send_bt_init_conf(mvm);
1384 if (ret)
1385 goto error;
1386
cceb4507
SM
1387 if (fw_has_capa(&mvm->fw->ucode_capa,
1388 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1389 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM
1390 if (ret)
1391 goto error;
1392 }
1393
43413a97 1394 /* Init RSS configuration */
286ca8eb 1395 if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
8edbfaa1
SS
1396 ret = iwl_configure_rxq(mvm);
1397 if (ret) {
1398 IWL_ERR(mvm, "Failed to configure RX queues: %d\n",
1399 ret);
1400 goto error;
1401 }
1402 }
1403
1404 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS
1405 ret = iwl_send_rss_cfg_cmd(mvm);
1406 if (ret) {
1407 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1408 ret);
1409 goto error;
1410 }
1411 }
1412
8ca151b5 1413 /* init the fw <-> mac80211 STA mapping */
be9ae34e 1414 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++)
8ca151b5
JB
1415 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1416
0ae98812 1417 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1418
b2b7875b
JB
1419 /* reset quota debouncing buffer - 0xff will yield invalid data */
1420 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1421
79660869
IL
1422 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1423 ret = iwl_mvm_send_dqa_cmd(mvm);
1424 if (ret)
1425 goto error;
1426 }
97d5be7e 1427
2c2c3647
NE
1428 /*
1429 * Add auxiliary station for scanning.
1430 * Newer versions of this command implies that the fw uses
1431 * internal aux station for all aux activities that don't
1432 * requires a dedicated data queue.
1433 */
1434 if (iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP,
1435 ADD_STA,
1436 0) < 12) {
1437 /*
1438 * In old version the aux station uses mac id like other
1439 * station and not lmac id
1440 */
1441 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1442 if (ret)
1443 goto error;
1444 }
8ca151b5 1445
53a9d61e 1446 /* Add all the PHY contexts */
dd36a507
TM
1447 i = 0;
1448 while (!sband && i < NUM_NL80211_BANDS)
1449 sband = mvm->hw->wiphy->bands[i++];
1450
1451 if (WARN_ON_ONCE(!sband))
1452 goto error;
1453
1454 chan = &sband->channels[0];
1455
53a9d61e
IP
1456 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1457 for (i = 0; i < NUM_PHY_CTX; i++) {
1458 /*
1459 * The channel used here isn't relevant as it's
1460 * going to be overwritten in the other flows.
1461 * For now use the first channel we have.
1462 */
1463 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1464 &chandef, 1, 1);
1465 if (ret)
1466 goto error;
1467 }
8ca151b5 1468
c221daf2
CRI
1469 if (iwl_mvm_is_tt_in_fw(mvm)) {
1470 /* in order to give the responsibility of ct-kill and
1471 * TX backoff to FW we need to send empty temperature reporting
1472 * cmd during init time
1473 */
1474 iwl_mvm_send_temp_report_ths_cmd(mvm);
1475 } else {
1476 /* Initialize tx backoffs to the minimal possible */
1477 iwl_mvm_tt_tx_backoff(mvm, 0);
1478 }
5c89e7bc 1479
242d9c8b 1480#ifdef CONFIG_THERMAL
5c89e7bc 1481 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI
1482
1483 /*
1484 * In case there is no budget from BIOS / Platform NVM the default
1485 * budget should be 2000mW (cooling state 0).
1486 */
1487 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI
1488 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1489 mvm->cooling_dev.cur_state);
75cfe338
LC
1490 if (ret)
1491 goto error;
1492 }
c221daf2 1493#endif
0c0e2c71 1494
aa43ae12
AM
1495 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1496 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1497
c1cb92fc 1498 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB
1499 if (ret)
1500 goto error;
1501
f5b1cb2e 1502 iwl_mvm_lari_cfg(mvm);
35af15d1
AN
1503 /*
1504 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1505 * anyway, so don't init MCC.
1506 */
1507 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1508 ret = iwl_mvm_init_mcc(mvm);
1509 if (ret)
1510 goto error;
1511 }
90d4f7db 1512
859d914c 1513 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1514 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1515 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS
1516 ret = iwl_mvm_config_scan(mvm);
1517 if (ret)
1518 goto error;
1519 }
1520
f130bb75
MG
1521 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1522 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
1523
48e775e6
HD
1524 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1525 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1526
6ce1e5c0
GA
1527 ret = iwl_mvm_ppag_init(mvm);
1528 if (ret)
1529 goto error;
1530
da2830ac 1531 ret = iwl_mvm_sar_init(mvm);
5d041c46
LC
1532 if (ret == 0) {
1533 ret = iwl_mvm_sar_geo_init(mvm);
1edd56e6 1534 } else if (ret == -ENOENT && !iwl_sar_get_wgds_table(&mvm->fwrt)) {
5d041c46
LC
1535 /*
1536 * If basic SAR is not available, we check for WGDS,
1537 * which should *not* be available either. If it is
1538 * available, issue an error, because we can't use SAR
1539 * Geo without basic SAR.
1540 */
1541 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1542 }
da2830ac 1543
5d041c46 1544 if (ret < 0)
a6bff3cb
HD
1545 goto error;
1546
28dd7ccd 1547 iwl_mvm_tas_init(mvm);
7089ae63
JB
1548 iwl_mvm_leds_sync(mvm);
1549
b68bd2e3
IP
1550 iwl_mvm_ftm_initiator_smooth_config(mvm);
1551
53a9d61e 1552 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB
1553 return 0;
1554 error:
f4744258 1555 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1556 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1557 return ret;
1558}
1559
1560int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1561{
1562 int ret, i;
1563
1564 lockdep_assert_held(&mvm->mutex);
1565
1566 ret = iwl_trans_start_hw(mvm->trans);
1567 if (ret)
1568 return ret;
1569
1570 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1571 if (ret) {
1572 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1573 goto error;
1574 }
1575
a0544272 1576 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1577 if (ret)
1578 goto error;
1579
1580 /* Send phy db control command and then phy db calibration*/
1581 ret = iwl_send_phy_db_data(mvm->phy_db);
1582 if (ret)
1583 goto error;
1584
1585 ret = iwl_send_phy_cfg_cmd(mvm);
1586 if (ret)
1587 goto error;
1588
1589 /* init the fw <-> mac80211 STA mapping */
be9ae34e 1590 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++)
8ca151b5
JB
1591 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1592
2c2c3647
NE
1593 if (iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP,
1594 ADD_STA,
1595 0) < 12) {
1596 /*
1597 * Add auxiliary station for scanning.
1598 * Newer versions of this command implies that the fw uses
1599 * internal aux station for all aux activities that don't
1600 * requires a dedicated data queue.
1601 * In old version the aux station uses mac id like other
1602 * station and not lmac id
1603 */
1604 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1605 if (ret)
1606 goto error;
1607 }
8ca151b5
JB
1608
1609 return 0;
1610 error:
fcb6b92a 1611 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1612 return ret;
1613}
1614
0416841d
JB
1615void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1616 struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB
1617{
1618 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1619 struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1620 u32 flags = le32_to_cpu(card_state_notif->flags);
1621
1622 IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1623 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1624 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1625 (flags & CT_KILL_CARD_DISABLED) ?
1626 "Reached" : "Not reached");
8ca151b5
JB
1627}
1628
0416841d
JB
1629void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1630 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI
1631{
1632 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1633 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1634
0c8d0a47
GBA
1635 IWL_DEBUG_INFO(mvm,
1636 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1637 le32_to_cpu(mfuart_notif->installed_ver),
1638 le32_to_cpu(mfuart_notif->external_ver),
1639 le32_to_cpu(mfuart_notif->status),
1640 le32_to_cpu(mfuart_notif->duration));
1641
19f63c53
GBA
1642 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1643 IWL_DEBUG_INFO(mvm,
0c8d0a47 1644 "MFUART: image size: 0x%08x\n",
19f63c53 1645 le32_to_cpu(mfuart_notif->image_size));
30269c12 1646}