iwlwifi: mvm: add support for new WOWLAN_TSC_RSC_PARAM version
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8ca151b5
JB
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8d193ca2 8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
bdccdb85 9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
cceb4507 10 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation
8ca151b5
JB
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
8ca151b5 21 * The full GNU General Public License is included in this distribution
410dc5aa 22 * in the file called COPYING.
8ca151b5
JB
23 *
24 * Contact Information:
cb2f8277 25 * Intel Linux Wireless <linuxwifi@intel.com>
8ca151b5
JB
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 * BSD LICENSE
29 *
8d193ca2 30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
bdccdb85 31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
cceb4507 32 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation
8ca151b5
JB
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 *
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
44 * distribution.
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 *
61 *****************************************************************************/
62#include <net/mac80211.h>
854d773e 63#include <linux/netdevice.h>
8ca151b5
JB
64
65#include "iwl-trans.h"
66#include "iwl-op-mode.h"
d962f9b1 67#include "fw/img.h"
8ca151b5
JB
68#include "iwl-debug.h"
69#include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
70#include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
8c23f95c 71#include "iwl-prph.h"
813df5ce 72#include "fw/acpi.h"
8ca151b5
JB
73
74#include "mvm.h"
7174beb6 75#include "fw/dbg.h"
8ca151b5 76#include "iwl-phy-db.h"
9c4f7d51
ST
77#include "iwl-modparams.h"
78#include "iwl-nvm-parse.h"
8ca151b5
JB
79
80#define MVM_UCODE_ALIVE_TIMEOUT HZ
81#define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
82
83#define UCODE_VALID_OK cpu_to_le32(0x1)
84
8ca151b5
JB
85struct iwl_mvm_alive_data {
86 bool valid;
87 u32 scd_base_addr;
88};
89
8ca151b5
JB
90static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
91{
92 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
93 .valid = cpu_to_le32(valid_tx_ant),
94 };
95
33223542 96 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 97 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB
98 sizeof(tx_ant_cmd), &tx_ant_cmd);
99}
100
43413a97
SS
101static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
102{
103 int i;
104 struct iwl_rss_config_cmd cmd = {
105 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS
106 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
107 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
108 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
109 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
110 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
111 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS
112 };
113
f43495fd
SS
114 if (mvm->trans->num_rx_queues == 1)
115 return 0;
116
854d773e 117 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 118 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS
119 cmd.indirection_table[i] =
120 1 + (i % (mvm->trans->num_rx_queues - 1));
121 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS
122
123 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
124}
125
8edbfaa1
SS
126static int iwl_configure_rxq(struct iwl_mvm *mvm)
127{
dbf592f3 128 int i, num_queues, size, ret;
8edbfaa1 129 struct iwl_rfh_queue_config *cmd;
dbf592f3
JB
130 struct iwl_host_cmd hcmd = {
131 .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD),
132 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
133 };
8edbfaa1
SS
134
135 /* Do not configure default queue, it is configured via context info */
136 num_queues = mvm->trans->num_rx_queues - 1;
137
dbf592f3 138 size = struct_size(cmd, data, num_queues);
8edbfaa1
SS
139
140 cmd = kzalloc(size, GFP_KERNEL);
141 if (!cmd)
142 return -ENOMEM;
143
144 cmd->num_queues = num_queues;
145
146 for (i = 0; i < num_queues; i++) {
147 struct iwl_trans_rxq_dma_data data;
148
149 cmd->data[i].q_num = i + 1;
150 iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data);
151
152 cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb);
153 cmd->data[i].urbd_stts_wrptr =
154 cpu_to_le64(data.urbd_stts_wrptr);
155 cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb);
156 cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid);
157 }
158
dbf592f3
JB
159 hcmd.data[0] = cmd;
160 hcmd.len[0] = size;
161
162 ret = iwl_mvm_send_cmd(mvm, &hcmd);
163
164 kfree(cmd);
165
166 return ret;
8edbfaa1
SS
167}
168
97d5be7e
LK
169static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
170{
171 struct iwl_dqa_enable_cmd dqa_cmd = {
172 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
173 };
174 u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
175 int ret;
176
177 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
178 if (ret)
179 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
180 else
181 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
182
183 return ret;
184}
185
bdccdb85
GBA
186void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
187 struct iwl_rx_cmd_buffer *rxb)
188{
189 struct iwl_rx_packet *pkt = rxb_addr(rxb);
190 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
191 __le32 *dump_data = mfu_dump_notif->data;
192 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
193 int i;
194
195 if (mfu_dump_notif->index_num == 0)
196 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
197 le32_to_cpu(mfu_dump_notif->assert_id));
198
199 for (i = 0; i < n_words; i++)
200 IWL_DEBUG_INFO(mvm,
201 "MFUART assert dump, dword %u: 0x%08x\n",
202 le16_to_cpu(mfu_dump_notif->index_num) *
203 n_words + i,
204 le32_to_cpu(dump_data[i]));
205}
206
8ca151b5
JB
207static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
208 struct iwl_rx_packet *pkt, void *data)
209{
210 struct iwl_mvm *mvm =
211 container_of(notif_wait, struct iwl_mvm, notif_wait);
212 struct iwl_mvm_alive_data *alive_data = data;
5c228d63 213 struct mvm_alive_resp_v3 *palive3;
7e1223b5 214 struct mvm_alive_resp *palive;
5c228d63
SS
215 struct iwl_umac_alive *umac;
216 struct iwl_lmac_alive *lmac1;
217 struct iwl_lmac_alive *lmac2 = NULL;
218 u16 status;
22463857 219 u32 lmac_error_event_table, umac_error_event_table;
01a9ca51 220
5c228d63
SS
221 if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
222 palive = (void *)pkt->data;
223 umac = &palive->umac_data;
224 lmac1 = &palive->lmac_data[0];
225 lmac2 = &palive->lmac_data[1];
226 status = le16_to_cpu(palive->status);
227 } else {
228 palive3 = (void *)pkt->data;
229 umac = &palive3->umac_data;
230 lmac1 = &palive3->lmac_data;
231 status = le16_to_cpu(palive3->status);
232 }
01a9ca51 233
22463857
SM
234 lmac_error_event_table =
235 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
236 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
237
5c228d63 238 if (lmac2)
91c28b83 239 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 240 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 241
22463857 242 umac_error_event_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr);
01a9ca51 243
3485e76e
LC
244 if (!umac_error_event_table) {
245 mvm->support_umac_log = false;
246 } else if (umac_error_event_table >=
247 mvm->trans->cfg->min_umac_error_event_table) {
248 mvm->support_umac_log = true;
3485e76e 249 } else {
fb5b2846
LC
250 IWL_ERR(mvm,
251 "Not valid error log pointer 0x%08X for %s uCode\n",
22463857 252 umac_error_event_table,
fb5b2846
LC
253 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
254 "Init" : "RT");
3485e76e
LC
255 mvm->support_umac_log = false;
256 }
fb5b2846 257
22463857
SM
258 if (mvm->support_umac_log)
259 iwl_fw_umac_set_alive_err_table(mvm->trans,
260 umac_error_event_table);
261
262 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 263 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 264
5c228d63
SS
265 IWL_DEBUG_FW(mvm,
266 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
267 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 268
5c228d63
SS
269 if (lmac2)
270 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 271
5c228d63
SS
272 IWL_DEBUG_FW(mvm,
273 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
274 le32_to_cpu(umac->umac_major),
275 le32_to_cpu(umac->umac_minor));
8ca151b5 276
0a3a3e9e
SM
277 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
278
8ca151b5
JB
279 return true;
280}
281
1f370650
SS
282static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
283 struct iwl_rx_packet *pkt, void *data)
284{
285 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
286
287 return true;
288}
289
8ca151b5
JB
290static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
291 struct iwl_rx_packet *pkt, void *data)
292{
293 struct iwl_phy_db *phy_db = data;
294
295 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
296 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
297 return true;
298 }
299
ce1f2778 300 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB
301
302 return false;
303}
304
305static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
306 enum iwl_ucode_type ucode_type)
307{
308 struct iwl_notification_wait alive_wait;
94a8d87c 309 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 310 const struct fw_img *fw;
cfbc6c4c 311 int ret;
702e975d 312 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
6eb031d2 313 static const u16 alive_cmd[] = { MVM_ALIVE };
b3500b47
EG
314 bool run_in_rfkill =
315 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
8ca151b5 316
61df750c 317 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA
318 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
319 !(fw_has_capa(&mvm->fw->ucode_capa,
320 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 321 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 322 else
612da1ef 323 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 324 if (WARN_ON(!fw))
8ca151b5 325 return -EINVAL;
702e975d 326 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 327 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB
328
329 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
330 alive_cmd, ARRAY_SIZE(alive_cmd),
331 iwl_alive_fn, &alive_data);
332
b3500b47
EG
333 /*
334 * We want to load the INIT firmware even in RFKILL
335 * For the unified firmware case, the ucode_type is not
336 * INIT, but we still need to run it.
337 */
338 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 339 if (ret) {
702e975d 340 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
341 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
342 return ret;
343 }
344
345 /*
346 * Some things may run in the background now, but we
347 * just wait for the ALIVE notification here.
348 */
349 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
350 MVM_UCODE_ALIVE_TIMEOUT);
351 if (ret) {
d6be9c1d
SS
352 struct iwl_trans *trans = mvm->trans;
353
20f5aef5
JB
354 if (trans->trans_cfg->device_family >=
355 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS
356 IWL_ERR(mvm,
357 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST
358 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
359 iwl_read_umac_prph(trans,
360 UMAG_SB_CPU_2_STATUS));
20f5aef5
JB
361 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
362 iwl_read_umac_prph(trans,
363 UREG_UMAC_CURRENT_PC));
364 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
365 iwl_read_umac_prph(trans,
366 UREG_LMAC1_CURRENT_PC));
367 if (iwl_mvm_is_cdb_supported(mvm))
368 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
369 iwl_read_umac_prph(trans,
370 UREG_LMAC2_CURRENT_PC));
371 } else if (trans->trans_cfg->device_family >=
372 IWL_DEVICE_FAMILY_8000) {
192de2b4
DS
373 IWL_ERR(mvm,
374 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
d6be9c1d
SS
375 iwl_read_prph(trans, SB_CPU_1_STATUS),
376 iwl_read_prph(trans, SB_CPU_2_STATUS));
20f5aef5
JB
377 }
378
379 if (ret == -ETIMEDOUT)
380 iwl_fw_dbg_error_collect(&mvm->fwrt,
381 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
382
702e975d 383 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
384 return ret;
385 }
386
387 if (!alive_data.valid) {
388 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 389 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
390 return -EIO;
391 }
392
393 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
394
395 /*
396 * Note: all the queues are enabled as part of the interface
397 * initialization, but in firmware restart scenarios they
398 * could be stopped, so wake them up. In firmware restart,
399 * mac80211 will have the queues stopped as well until the
400 * reconfiguration completes. During normal startup, they
401 * will be empty.
402 */
403
4ecafae9 404 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB
405 /*
406 * Set a 'fake' TID for the command queue, since we use the
407 * hweight() of the tid_bitmap as a refcount now. Not that
408 * we ever even consider the command queue as one we might
409 * want to reuse, but be safe nevertheless.
410 */
411 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
412 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 413
65b280fe 414 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC
415#ifdef CONFIG_IWLWIFI_DEBUGFS
416 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
417#endif
8ca151b5
JB
418
419 return 0;
420}
8ca151b5 421
8c5f47b1
JB
422static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
423{
424 struct iwl_notification_wait init_wait;
425 struct iwl_nvm_access_complete_cmd nvm_complete = {};
426 struct iwl_init_extended_cfg_cmd init_cfg = {
427 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
428 };
429 static const u16 init_complete[] = {
430 INIT_COMPLETE_NOTIF,
431 };
432 int ret;
433
a4584729
HD
434 if (mvm->trans->cfg->tx_with_siso_diversity)
435 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
436
8c5f47b1
JB
437 lockdep_assert_held(&mvm->mutex);
438
94022562
EG
439 mvm->rfkill_safe_init_done = false;
440
8c5f47b1
JB
441 iwl_init_notification_wait(&mvm->notif_wait,
442 &init_wait,
443 init_complete,
444 ARRAY_SIZE(init_complete),
445 iwl_wait_init_complete,
446 NULL);
447
b108d8c7 448 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
86ce5c74 449
8c5f47b1
JB
450 /* Will also start the device */
451 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
452 if (ret) {
453 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
454 goto error;
455 }
b108d8c7
SM
456 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
457 NULL);
8c5f47b1
JB
458
459 /* Send init config command to mark that we are sending NVM access
460 * commands
461 */
462 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
b3500b47
EG
463 INIT_EXTENDED_CFG_CMD),
464 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
465 sizeof(init_cfg), &init_cfg);
466 if (ret) {
467 IWL_ERR(mvm, "Failed to run init config command: %d\n",
468 ret);
469 goto error;
470 }
471
e9e1ba3d
SS
472 /* Load NVM to NIC if needed */
473 if (mvm->nvm_file_name) {
9c4f7d51
ST
474 iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
475 mvm->nvm_sections);
8c5f47b1 476 iwl_mvm_load_nvm_to_nic(mvm);
e9e1ba3d 477 }
8c5f47b1 478
d4f3695e 479 if (IWL_MVM_PARSE_NVM && read_nvm) {
5bd1d2c1 480 ret = iwl_nvm_init(mvm);
d4f3695e
SS
481 if (ret) {
482 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
483 goto error;
484 }
485 }
486
8c5f47b1 487 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
b3500b47
EG
488 NVM_ACCESS_COMPLETE),
489 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
490 sizeof(nvm_complete), &nvm_complete);
491 if (ret) {
492 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
493 ret);
494 goto error;
495 }
496
497 /* We wait for the INIT complete notification */
e9e1ba3d
SS
498 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
499 MVM_UCODE_ALIVE_TIMEOUT);
500 if (ret)
501 return ret;
502
503 /* Read the NVM only at driver load time, no need to do this twice */
d4f3695e 504 if (!IWL_MVM_PARSE_NVM && read_nvm) {
4c625c56 505 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
c135cb56
ST
506 if (IS_ERR(mvm->nvm_data)) {
507 ret = PTR_ERR(mvm->nvm_data);
508 mvm->nvm_data = NULL;
e9e1ba3d
SS
509 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
510 return ret;
511 }
512 }
513
b3500b47
EG
514 mvm->rfkill_safe_init_done = true;
515
e9e1ba3d 516 return 0;
8c5f47b1
JB
517
518error:
519 iwl_remove_notification(&mvm->notif_wait, &init_wait);
520 return ret;
521}
522
c4ace426
GA
523#ifdef CONFIG_ACPI
524static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
525 struct iwl_phy_specific_cfg *phy_filters)
526{
527 /*
528 * TODO: read specific phy config from BIOS
529 * ACPI table for this feature has not been defined yet,
530 * so for now we use hardcoded values.
531 */
532
533 if (IWL_MVM_PHY_FILTER_CHAIN_A) {
534 phy_filters->filter_cfg_chain_a =
535 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
536 }
537 if (IWL_MVM_PHY_FILTER_CHAIN_B) {
538 phy_filters->filter_cfg_chain_b =
539 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
540 }
541 if (IWL_MVM_PHY_FILTER_CHAIN_C) {
542 phy_filters->filter_cfg_chain_c =
543 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
544 }
545 if (IWL_MVM_PHY_FILTER_CHAIN_D) {
546 phy_filters->filter_cfg_chain_d =
547 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
548 }
549}
550
551#else /* CONFIG_ACPI */
552
553static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
554 struct iwl_phy_specific_cfg *phy_filters)
555{
556}
557#endif /* CONFIG_ACPI */
558
8ca151b5
JB
559static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
560{
c4ace426 561 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 562 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA
563 struct iwl_phy_specific_cfg phy_filters = {};
564 u8 cmd_ver;
565 size_t cmd_size;
8ca151b5 566
bb99ff9b 567 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 568 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 569 return 0;
d923b020
LC
570
571 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC
572 /*
573 * TODO: currently we don't set the antenna but letting the NIC
574 * to decide which antenna to use. This should come from BIOS.
575 */
576 phy_cfg_cmd.phy_cfg =
577 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
578 }
579
8ca151b5 580 /* Set parameters */
a0544272 581 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC
582
583 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC
584 phy_cfg_cmd.phy_cfg |=
585 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 586
8ca151b5
JB
587 phy_cfg_cmd.calib_control.event_trigger =
588 mvm->fw->default_calib[ucode_type].event_trigger;
589 phy_cfg_cmd.calib_control.flow_trigger =
590 mvm->fw->default_calib[ucode_type].flow_trigger;
591
c4ace426
GA
592 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP,
593 PHY_CONFIGURATION_CMD);
594 if (cmd_ver == 3) {
595 iwl_mvm_phy_filter_init(mvm, &phy_filters);
596 memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
597 sizeof(struct iwl_phy_specific_cfg));
598 }
599
8ca151b5
JB
600 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
601 phy_cfg_cmd.phy_cfg);
c4ace426
GA
602 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
603 sizeof(struct iwl_phy_cfg_cmd_v1);
a1022927 604 return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
c4ace426 605 cmd_size, &phy_cfg_cmd);
8ca151b5
JB
606}
607
8ca151b5
JB
608int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
609{
610 struct iwl_notification_wait calib_wait;
6eb031d2 611 static const u16 init_complete[] = {
8ca151b5
JB
612 INIT_COMPLETE_NOTIF,
613 CALIB_RES_NOTIF_PHY_DB
614 };
615 int ret;
616
7d6222e2 617 if (iwl_mvm_has_unified_ucode(mvm))
8c5f47b1
JB
618 return iwl_run_unified_mvm_ucode(mvm, true);
619
8ca151b5
JB
620 lockdep_assert_held(&mvm->mutex);
621
94022562 622 mvm->rfkill_safe_init_done = false;
8ca151b5
JB
623
624 iwl_init_notification_wait(&mvm->notif_wait,
625 &calib_wait,
626 init_complete,
627 ARRAY_SIZE(init_complete),
628 iwl_wait_phy_db_entry,
629 mvm->phy_db);
630
631 /* Will also start the device */
632 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
633 if (ret) {
634 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 635 goto remove_notif;
8ca151b5
JB
636 }
637
7d34a7d7 638 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG
639 ret = iwl_mvm_send_bt_init_conf(mvm);
640 if (ret)
00e0c6c8 641 goto remove_notif;
b3de3ef4 642 }
931d4160 643
81a67e32 644 /* Read the NVM only at driver load time, no need to do this twice */
8ca151b5 645 if (read_nvm) {
5bd1d2c1 646 ret = iwl_nvm_init(mvm);
8ca151b5
JB
647 if (ret) {
648 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 649 goto remove_notif;
8ca151b5
JB
650 }
651 }
652
81a67e32 653 /* In case we read the NVM from external file, load it to the NIC */
e02a9d60 654 if (mvm->nvm_file_name)
81a67e32
EL
655 iwl_mvm_load_nvm_to_nic(mvm);
656
64866e5d
LC
657 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
658 "Too old NVM version (0x%0x, required = 0x%0x)",
659 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 660
4f59334b
EH
661 /*
662 * abort after reading the nvm in case RF Kill is on, we will complete
663 * the init seq later when RF kill will switch to off
664 */
1a3fe0b2 665 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH
666 IWL_DEBUG_RF_KILL(mvm,
667 "jump over all phy activities due to RF kill\n");
00e0c6c8 668 goto remove_notif;
4f59334b
EH
669 }
670
b3500b47 671 mvm->rfkill_safe_init_done = true;
31b8b343 672
e07cbb53 673 /* Send TX valid antennas before triggering calibrations */
a0544272 674 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 675 if (ret)
00e0c6c8 676 goto remove_notif;
e07cbb53 677
8ca151b5
JB
678 ret = iwl_send_phy_cfg_cmd(mvm);
679 if (ret) {
680 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
681 ret);
00e0c6c8 682 goto remove_notif;
8ca151b5
JB
683 }
684
685 /*
686 * Some things may run in the background now, but we
687 * just wait for the calibration complete notification.
688 */
689 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC
690 MVM_UCODE_CALIB_TIMEOUT);
691 if (!ret)
692 goto out;
31b8b343 693
00e0c6c8 694 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 695 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC
696 ret = 0;
697 } else {
698 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
699 ret);
31b8b343 700 }
00e0c6c8 701
8ca151b5
JB
702 goto out;
703
00e0c6c8 704remove_notif:
8ca151b5
JB
705 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
706out:
b3500b47 707 mvm->rfkill_safe_init_done = false;
a4082843 708 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB
709 /* we want to debug INIT and we have no NVM - fake */
710 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
711 sizeof(struct ieee80211_channel) +
712 sizeof(struct ieee80211_rate),
713 GFP_KERNEL);
714 if (!mvm->nvm_data)
715 return -ENOMEM;
8ca151b5
JB
716 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
717 mvm->nvm_data->bands[0].n_channels = 1;
718 mvm->nvm_data->bands[0].n_bitrates = 1;
719 mvm->nvm_data->bands[0].bitrates =
720 (void *)mvm->nvm_data->channels + 1;
721 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
722 }
723
724 return ret;
725}
726
84bfffa9
EG
727static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
728{
729 struct iwl_ltr_config_cmd cmd = {
730 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
731 };
732
733 if (!mvm->trans->ltr_enabled)
734 return 0;
735
84bfffa9
EG
736 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
737 sizeof(cmd), &cmd);
738}
739
c386dacb 740#ifdef CONFIG_ACPI
42ce76d6 741int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 742{
0791c2fc
HD
743 union {
744 struct iwl_dev_tx_power_cmd v5;
745 struct iwl_dev_tx_power_cmd_v4 v4;
71e9378b
LC
746 } cmd = {
747 .v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
748 };
1edd56e6 749 int ret;
39c1a972 750 u16 len = 0;
42ce76d6 751
0791c2fc
HD
752 if (fw_has_api(&mvm->fw->ucode_capa,
753 IWL_UCODE_TLV_API_REDUCE_TX_POWER))
754 len = sizeof(cmd.v5);
755 else if (fw_has_capa(&mvm->fw->ucode_capa,
756 IWL_UCODE_TLV_CAPA_TX_POWER_ACK))
39c1a972 757 len = sizeof(struct iwl_dev_tx_power_cmd_v4);
0791c2fc
HD
758 else
759 len = sizeof(cmd.v4.v3);
55bfa4b9 760
da2830ac 761
1edd56e6
LC
762 ret = iwl_sar_select_profile(&mvm->fwrt,
763 cmd.v5.v3.per_chain_restriction,
764 prof_a, prof_b);
765
766 /* return on error or if the profile is disabled (positive number) */
767 if (ret)
768 return ret;
769
42ce76d6 770 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
42ce76d6
LC
771 return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
772}
773
7fe90e0e
HD
774int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
775{
39c1a972 776 union geo_tx_power_profiles_cmd geo_tx_cmd;
0c3d7282 777 u16 len;
39c1a972 778 int ret;
0c3d7282
HD
779 struct iwl_host_cmd cmd;
780
39c1a972
IZ
781 if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
782 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
783 geo_tx_cmd.geo_cmd.ops =
0c3d7282 784 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
39c1a972 785 len = sizeof(geo_tx_cmd.geo_cmd);
0c3d7282 786 } else {
39c1a972 787 geo_tx_cmd.geo_cmd_v1.ops =
0c3d7282 788 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
39c1a972 789 len = sizeof(geo_tx_cmd.geo_cmd_v1);
0c3d7282 790 }
7fe90e0e 791
39c1a972
IZ
792 if (!iwl_sar_geo_support(&mvm->fwrt))
793 return -EOPNOTSUPP;
794
0c3d7282 795 cmd = (struct iwl_host_cmd){
7fe90e0e 796 .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT),
0c3d7282 797 .len = { len, },
7fe90e0e 798 .flags = CMD_WANT_SKB,
39c1a972 799 .data = { &geo_tx_cmd },
7fe90e0e
HD
800 };
801
802 ret = iwl_mvm_send_cmd(mvm, &cmd);
803 if (ret) {
804 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
805 return ret;
806 }
39c1a972 807 ret = iwl_validate_sar_geo_profile(&mvm->fwrt, &cmd);
7fe90e0e
HD
808 iwl_free_resp(&cmd);
809 return ret;
810}
811
a6bff3cb
HD
812static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
813{
a6bff3cb 814 u16 cmd_wide_id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT);
39c1a972
IZ
815 union geo_tx_power_profiles_cmd cmd;
816 u16 len;
0433ae55 817 int ret;
a6bff3cb 818
39c1a972 819 cmd.geo_cmd.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
a6bff3cb 820
0433ae55
GBA
821 ret = iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table);
822 /*
823 * It is a valid scenario to not support SAR, or miss wgds table,
824 * but in that case there is no need to send the command.
825 */
826 if (ret)
827 return 0;
a6bff3cb 828
39c1a972 829 cmd.geo_cmd.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
0c3d7282 830
39c1a972
IZ
831 if (!fw_has_api(&mvm->fwrt.fw->ucode_capa,
832 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
833 len = sizeof(struct iwl_geo_tx_power_profiles_cmd_v1);
834 } else {
835 len = sizeof(cmd.geo_cmd);
0c3d7282
HD
836 }
837
39c1a972 838 return iwl_mvm_send_cmd_pdu(mvm, cmd_wide_id, 0, len, &cmd);
a6bff3cb
HD
839}
840
6ce1e5c0
GA
841static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm)
842{
843 union acpi_object *wifi_pkg, *data, *enabled;
f2134f66
GA
844 union iwl_ppag_table_cmd ppag_table;
845 int i, j, ret, tbl_rev, num_sub_bands;
6ce1e5c0 846 int idx = 2;
f2134f66 847 s8 *gain;
6ce1e5c0 848
f2134f66
GA
849 /*
850 * The 'enabled' field is the same in v1 and v2 so we can just
851 * use v1 to access it.
852 */
853 mvm->fwrt.ppag_table.v1.enabled = cpu_to_le32(0);
6ce1e5c0
GA
854 data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD);
855 if (IS_ERR(data))
856 return PTR_ERR(data);
857
f2134f66 858 /* try to read ppag table revision 1 */
6ce1e5c0 859 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
f2134f66
GA
860 ACPI_PPAG_WIFI_DATA_SIZE_V2, &tbl_rev);
861 if (!IS_ERR(wifi_pkg)) {
862 if (tbl_rev != 1) {
863 ret = -EINVAL;
864 goto out_free;
865 }
866 num_sub_bands = IWL_NUM_SUB_BANDS_V2;
867 gain = mvm->fwrt.ppag_table.v2.gain[0];
868 mvm->fwrt.ppag_ver = 2;
869 IWL_DEBUG_RADIO(mvm, "Reading PPAG table v2 (tbl_rev=1)\n");
870 goto read_table;
6ce1e5c0
GA
871 }
872
f2134f66
GA
873 /* try to read ppag table revision 0 */
874 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
875 ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev);
876 if (!IS_ERR(wifi_pkg)) {
877 if (tbl_rev != 0) {
878 ret = -EINVAL;
879 goto out_free;
880 }
881 num_sub_bands = IWL_NUM_SUB_BANDS;
882 gain = mvm->fwrt.ppag_table.v1.gain[0];
883 mvm->fwrt.ppag_ver = 1;
884 IWL_DEBUG_RADIO(mvm, "Reading PPAG table v1 (tbl_rev=0)\n");
885 goto read_table;
3ed83da3 886 }
f2134f66
GA
887 ret = PTR_ERR(wifi_pkg);
888 goto out_free;
3ed83da3 889
f2134f66 890read_table:
6ce1e5c0
GA
891 enabled = &wifi_pkg->package.elements[1];
892 if (enabled->type != ACPI_TYPE_INTEGER ||
893 (enabled->integer.value != 0 && enabled->integer.value != 1)) {
894 ret = -EINVAL;
895 goto out_free;
896 }
897
f2134f66
GA
898 ppag_table.v1.enabled = cpu_to_le32(enabled->integer.value);
899 if (!ppag_table.v1.enabled) {
6ce1e5c0
GA
900 ret = 0;
901 goto out_free;
902 }
903
904 /*
905 * read, verify gain values and save them into the PPAG table.
906 * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the
907 * following sub-bands to High-Band (5GHz).
908 */
f2134f66
GA
909 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
910 for (j = 0; j < num_sub_bands; j++) {
6ce1e5c0
GA
911 union acpi_object *ent;
912
913 ent = &wifi_pkg->package.elements[idx++];
914 if (ent->type != ACPI_TYPE_INTEGER ||
915 (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) ||
916 (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) ||
917 (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) ||
918 (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) {
f2134f66 919 ppag_table.v1.enabled = cpu_to_le32(0);
6ce1e5c0
GA
920 ret = -EINVAL;
921 goto out_free;
922 }
f2134f66 923 gain[i * num_sub_bands + j] = ent->integer.value;
6ce1e5c0
GA
924 }
925 }
926 ret = 0;
927out_free:
928 kfree(data);
929 return ret;
930}
931
932int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
933{
f2134f66
GA
934 u8 cmd_ver;
935 int i, j, ret, num_sub_bands, cmd_size;
936 union iwl_ppag_table_cmd ppag_table;
937 s8 *gain;
6ce1e5c0
GA
938
939 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
940 IWL_DEBUG_RADIO(mvm,
941 "PPAG capability not supported by FW, command not sent.\n");
942 return 0;
943 }
f2134f66
GA
944 if (!mvm->fwrt.ppag_table.v1.enabled) {
945 IWL_DEBUG_RADIO(mvm, "PPAG not enabled, command not sent.\n");
160bab43
GA
946 return 0;
947 }
948
f2134f66
GA
949 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP,
950 PER_PLATFORM_ANT_GAIN_CMD);
951 if (cmd_ver == 1) {
952 num_sub_bands = IWL_NUM_SUB_BANDS;
953 gain = mvm->fwrt.ppag_table.v1.gain[0];
954 cmd_size = sizeof(ppag_table.v1);
955 if (mvm->fwrt.ppag_ver == 2) {
956 IWL_DEBUG_RADIO(mvm,
957 "PPAG table is v2 but FW supports v1, sending truncated table\n");
958 }
959 } else if (cmd_ver == 2) {
960 num_sub_bands = IWL_NUM_SUB_BANDS_V2;
961 gain = mvm->fwrt.ppag_table.v2.gain[0];
962 cmd_size = sizeof(ppag_table.v2);
963 if (mvm->fwrt.ppag_ver == 1) {
964 IWL_DEBUG_RADIO(mvm,
965 "PPAG table is v1 but FW supports v2, sending padded table\n");
966 }
967 } else {
968 IWL_DEBUG_RADIO(mvm, "Unsupported PPAG command version\n");
969 return 0;
970 }
6ce1e5c0 971
f2134f66
GA
972 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
973 for (j = 0; j < num_sub_bands; j++) {
6ce1e5c0
GA
974 IWL_DEBUG_RADIO(mvm,
975 "PPAG table: chain[%d] band[%d]: gain = %d\n",
f2134f66 976 i, j, gain[i * num_sub_bands + j]);
6ce1e5c0
GA
977 }
978 }
f2134f66 979 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA
980 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
981 PER_PLATFORM_ANT_GAIN_CMD),
f2134f66 982 0, cmd_size, &ppag_table);
6ce1e5c0
GA
983 if (ret < 0)
984 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
985 ret);
986
987 return ret;
988}
989
990static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
991{
992 int ret;
993
994 ret = iwl_mvm_get_ppag_table(mvm);
995 if (ret < 0) {
996 IWL_DEBUG_RADIO(mvm,
997 "PPAG BIOS table invalid or unavailable. (%d)\n",
998 ret);
999 return 0;
1000 }
1001 return iwl_mvm_ppag_send_cmd(mvm);
1002}
1003
28dd7ccd
MG
1004static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1005{
1006 int ret;
1007 struct iwl_tas_config_cmd cmd = {};
1008 int list_size;
1009
1010 BUILD_BUG_ON(ARRAY_SIZE(cmd.black_list_array) <
1011 APCI_WTAS_BLACK_LIST_MAX);
1012
1013 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1014 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1015 return;
1016 }
1017
1018 ret = iwl_acpi_get_tas(&mvm->fwrt, cmd.black_list_array, &list_size);
1019 if (ret < 0) {
1020 IWL_DEBUG_RADIO(mvm,
1021 "TAS table invalid or unavailable. (%d)\n",
1022 ret);
1023 return;
1024 }
1025
1026 if (list_size < 0)
1027 return;
1028
1029 /* list size if TAS enabled can only be non-negative */
1030 cmd.black_list_size = cpu_to_le32((u32)list_size);
1031
1032 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
1033 TAS_CONFIG),
1034 0, sizeof(cmd), &cmd);
1035 if (ret < 0)
1036 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1037}
f5b1cb2e 1038
02d31e9b 1039static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm)
f5b1cb2e
GA
1040{
1041 int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
1042 DSM_FUNC_ENABLE_INDONESIA_5G2);
1043
02d31e9b
GA
1044 if (ret < 0)
1045 IWL_DEBUG_RADIO(mvm,
1046 "Failed to evaluate DSM function ENABLE_INDONESIA_5G2, ret=%d\n",
1047 ret);
f5b1cb2e 1048
02d31e9b
GA
1049 else if (ret >= DSM_VALUE_INDONESIA_MAX)
1050 IWL_DEBUG_RADIO(mvm,
1051 "DSM function ENABLE_INDONESIA_5G2 return invalid value, ret=%d\n",
1052 ret);
1053
1054 else if (ret == DSM_VALUE_INDONESIA_ENABLE) {
1055 IWL_DEBUG_RADIO(mvm,
1056 "Evaluated DSM function ENABLE_INDONESIA_5G2: Enabling 5g2\n");
1057 return DSM_VALUE_INDONESIA_ENABLE;
1058 }
1059 /* default behaviour is disabled */
1060 return DSM_VALUE_INDONESIA_DISABLE;
1061}
1062
1063static u8 iwl_mvm_eval_dsm_disable_srd(struct iwl_mvm *mvm)
1064{
1065 int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
1066 DSM_FUNC_DISABLE_SRD);
1067
1068 if (ret < 0)
1069 IWL_DEBUG_RADIO(mvm,
1070 "Failed to evaluate DSM function DISABLE_SRD, ret=%d\n",
1071 ret);
1072
1073 else if (ret >= DSM_VALUE_SRD_MAX)
1074 IWL_DEBUG_RADIO(mvm,
1075 "DSM function DISABLE_SRD return invalid value, ret=%d\n",
1076 ret);
1077
1078 else if (ret == DSM_VALUE_SRD_PASSIVE) {
1079 IWL_DEBUG_RADIO(mvm,
1080 "Evaluated DSM function DISABLE_SRD: setting SRD to passive\n");
1081 return DSM_VALUE_SRD_PASSIVE;
1082
1083 } else if (ret == DSM_VALUE_SRD_DISABLE) {
1084 IWL_DEBUG_RADIO(mvm,
1085 "Evaluated DSM function DISABLE_SRD: disabling SRD\n");
1086 return DSM_VALUE_SRD_DISABLE;
1087 }
1088 /* default behaviour is active */
1089 return DSM_VALUE_SRD_ACTIVE;
f5b1cb2e
GA
1090}
1091
1092static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1093{
02d31e9b
GA
1094 u8 ret;
1095 int cmd_ret;
f5b1cb2e
GA
1096 struct iwl_lari_config_change_cmd cmd = {};
1097
02d31e9b 1098 if (iwl_mvm_eval_dsm_indonesia_5g2(mvm) == DSM_VALUE_INDONESIA_ENABLE)
f5b1cb2e
GA
1099 cmd.config_bitmap |=
1100 cpu_to_le32(LARI_CONFIG_ENABLE_5G2_IN_INDONESIA_MSK);
1101
02d31e9b
GA
1102 ret = iwl_mvm_eval_dsm_disable_srd(mvm);
1103 if (ret == DSM_VALUE_SRD_PASSIVE)
1104 cmd.config_bitmap |=
1105 cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_PASSIVE_MSK);
1106
1107 else if (ret == DSM_VALUE_SRD_DISABLE)
1108 cmd.config_bitmap |=
1109 cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_DISABLED_MSK);
1110
f5b1cb2e
GA
1111 /* apply more config masks here */
1112
1113 if (cmd.config_bitmap) {
02d31e9b
GA
1114 IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE\n");
1115 cmd_ret = iwl_mvm_send_cmd_pdu(mvm,
1116 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1117 LARI_CONFIG_CHANGE),
1118 0, sizeof(cmd), &cmd);
1119 if (cmd_ret < 0)
f5b1cb2e
GA
1120 IWL_DEBUG_RADIO(mvm,
1121 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
02d31e9b 1122 cmd_ret);
f5b1cb2e
GA
1123 }
1124}
69964905 1125#else /* CONFIG_ACPI */
69964905 1126
39c1a972
IZ
1127inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1128 int prof_a, int prof_b)
69964905
LC
1129{
1130 return -ENOENT;
1131}
a6bff3cb 1132
39c1a972 1133inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC
1134{
1135 return -ENOENT;
1136}
1137
a6bff3cb
HD
1138static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1139{
1140 return 0;
1141}
18f1755d 1142
6ce1e5c0
GA
1143int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1144{
1145 return -ENOENT;
1146}
1147
1148static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1149{
7937fd32 1150 return 0;
6ce1e5c0 1151}
28dd7ccd
MG
1152
1153static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1154{
1155}
f5b1cb2e
GA
1156
1157static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1158{
1159}
69964905
LC
1160#endif /* CONFIG_ACPI */
1161
f130bb75
MG
1162void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1163{
1164 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1165 int ret;
1166 u32 resp;
1167
1168 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1169 .flags = cpu_to_le32(flags),
1170 .buf_size = 0,
1171 };
1172 struct iwl_host_cmd host_cmd = {
1173 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1174 .flags = CMD_WANT_SKB,
1175 .data = {&recovery_cmd, },
1176 .len = {sizeof(recovery_cmd), },
1177 };
1178
1179 /* no error log was defined in TLV */
1180 if (!error_log_size)
1181 return;
1182
1183 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1184 /* no buf was allocated while HW reset */
1185 if (!mvm->error_recovery_buf)
1186 return;
1187
1188 host_cmd.data[1] = mvm->error_recovery_buf;
1189 host_cmd.len[1] = error_log_size;
1190 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1191 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1192 }
1193
1194 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1195 kfree(mvm->error_recovery_buf);
1196 mvm->error_recovery_buf = NULL;
1197
1198 if (ret) {
1199 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1200 return;
1201 }
1202
1203 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1204 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1205 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1206 if (resp)
1207 IWL_ERR(mvm,
1208 "Failed to send recovery cmd blob was invalid %d\n",
1209 resp);
1210 }
1211}
1212
42ce76d6
LC
1213static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1214{
1215 int ret;
1216
39c1a972 1217 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
42ce76d6
LC
1218 if (ret < 0) {
1219 IWL_DEBUG_RADIO(mvm,
69964905 1220 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
42ce76d6 1221 ret);
5d041c46
LC
1222 /*
1223 * If not available, don't fail and don't bother with EWRD.
1224 * Return 1 to tell that we can't use WGDS either.
1225 */
1226 return 1;
42ce76d6
LC
1227 }
1228
39c1a972 1229 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
69964905
LC
1230 /* if EWRD is not available, we can still use WRDS, so don't fail */
1231 if (ret < 0)
1232 IWL_DEBUG_RADIO(mvm,
1233 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1234 ret);
1235
1edd56e6 1236 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC
1237}
1238
1f370650 1239static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1240{
1f370650 1241 int ret;
8ca151b5 1242
7d6222e2 1243 if (iwl_mvm_has_unified_ucode(mvm))
1f370650 1244 return iwl_run_unified_mvm_ucode(mvm, false);
8ca151b5 1245
8d193ca2 1246 ret = iwl_run_init_mvm_ucode(mvm, false);
f2082a53 1247
f2082a53 1248 if (ret) {
8d193ca2 1249 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK
1250
1251 if (iwlmvm_mod_params.init_dbg)
1252 return 0;
1f370650 1253 return ret;
8d193ca2 1254 }
8ca151b5 1255
203c83d3 1256 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG
1257 iwl_trans_stop_device(mvm->trans);
1258 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1259 if (ret)
1f370650 1260 return ret;
8ca151b5 1261
b108d8c7 1262 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
da2eb669 1263
94022562 1264 mvm->rfkill_safe_init_done = false;
8ca151b5 1265 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS
1266 if (ret)
1267 return ret;
1268
94022562
EG
1269 mvm->rfkill_safe_init_done = true;
1270
b108d8c7
SM
1271 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1272 NULL);
da2eb669 1273
702e975d 1274 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS
1275}
1276
1277int iwl_mvm_up(struct iwl_mvm *mvm)
1278{
1279 int ret, i;
1280 struct ieee80211_channel *chan;
1281 struct cfg80211_chan_def chandef;
dd36a507 1282 struct ieee80211_supported_band *sband = NULL;
1f370650
SS
1283
1284 lockdep_assert_held(&mvm->mutex);
1285
1286 ret = iwl_trans_start_hw(mvm->trans);
1287 if (ret)
1288 return ret;
1289
1290 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB
1291 if (ret) {
1292 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
72d3c7bb
JB
1293 if (ret != -ERFKILL)
1294 iwl_fw_dbg_error_collect(&mvm->fwrt,
1295 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB
1296 goto error;
1297 }
1298
d0b813fc 1299 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1300
1f3b0ff8
LE
1301 ret = iwl_mvm_sf_update(mvm, NULL, false);
1302 if (ret)
1303 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1304
a1af4c48 1305 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS
1306 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1307 /* if we have a destination, assume EARLY START */
1308 if (mvm->fw->dbg.dest_tlv)
1309 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1310 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1311 }
6a951267 1312
a0544272 1313 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1314 if (ret)
1315 goto error;
1316
7d6222e2
JB
1317 if (!iwl_mvm_has_unified_ucode(mvm)) {
1318 /* Send phy db control command and then phy db calibration */
1f370650
SS
1319 ret = iwl_send_phy_db_data(mvm->phy_db);
1320 if (ret)
1321 goto error;
1f370650 1322 }
8ca151b5 1323
bb99ff9b
LC
1324 ret = iwl_send_phy_cfg_cmd(mvm);
1325 if (ret)
1326 goto error;
1327
b3de3ef4
EG
1328 ret = iwl_mvm_send_bt_init_conf(mvm);
1329 if (ret)
1330 goto error;
1331
cceb4507
SM
1332 if (fw_has_capa(&mvm->fw->ucode_capa,
1333 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1334 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM
1335 if (ret)
1336 goto error;
1337 }
1338
43413a97 1339 /* Init RSS configuration */
286ca8eb 1340 if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
8edbfaa1
SS
1341 ret = iwl_configure_rxq(mvm);
1342 if (ret) {
1343 IWL_ERR(mvm, "Failed to configure RX queues: %d\n",
1344 ret);
1345 goto error;
1346 }
1347 }
1348
1349 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS
1350 ret = iwl_send_rss_cfg_cmd(mvm);
1351 if (ret) {
1352 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1353 ret);
1354 goto error;
1355 }
1356 }
1357
8ca151b5 1358 /* init the fw <-> mac80211 STA mapping */
0ae98812 1359 for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++)
8ca151b5
JB
1360 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1361
0ae98812 1362 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1363
b2b7875b
JB
1364 /* reset quota debouncing buffer - 0xff will yield invalid data */
1365 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1366
79660869
IL
1367 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1368 ret = iwl_mvm_send_dqa_cmd(mvm);
1369 if (ret)
1370 goto error;
1371 }
97d5be7e 1372
8ca151b5
JB
1373 /* Add auxiliary station for scanning */
1374 ret = iwl_mvm_add_aux_sta(mvm);
1375 if (ret)
1376 goto error;
1377
53a9d61e 1378 /* Add all the PHY contexts */
dd36a507
TM
1379 i = 0;
1380 while (!sband && i < NUM_NL80211_BANDS)
1381 sband = mvm->hw->wiphy->bands[i++];
1382
1383 if (WARN_ON_ONCE(!sband))
1384 goto error;
1385
1386 chan = &sband->channels[0];
1387
53a9d61e
IP
1388 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1389 for (i = 0; i < NUM_PHY_CTX; i++) {
1390 /*
1391 * The channel used here isn't relevant as it's
1392 * going to be overwritten in the other flows.
1393 * For now use the first channel we have.
1394 */
1395 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1396 &chandef, 1, 1);
1397 if (ret)
1398 goto error;
1399 }
8ca151b5 1400
c221daf2
CRI
1401 if (iwl_mvm_is_tt_in_fw(mvm)) {
1402 /* in order to give the responsibility of ct-kill and
1403 * TX backoff to FW we need to send empty temperature reporting
1404 * cmd during init time
1405 */
1406 iwl_mvm_send_temp_report_ths_cmd(mvm);
1407 } else {
1408 /* Initialize tx backoffs to the minimal possible */
1409 iwl_mvm_tt_tx_backoff(mvm, 0);
1410 }
5c89e7bc 1411
242d9c8b 1412#ifdef CONFIG_THERMAL
5c89e7bc 1413 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI
1414
1415 /*
1416 * In case there is no budget from BIOS / Platform NVM the default
1417 * budget should be 2000mW (cooling state 0).
1418 */
1419 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI
1420 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1421 mvm->cooling_dev.cur_state);
75cfe338
LC
1422 if (ret)
1423 goto error;
1424 }
c221daf2 1425#endif
0c0e2c71 1426
aa43ae12
AM
1427 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1428 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1429
c1cb92fc 1430 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB
1431 if (ret)
1432 goto error;
1433
f5b1cb2e 1434 iwl_mvm_lari_cfg(mvm);
35af15d1
AN
1435 /*
1436 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1437 * anyway, so don't init MCC.
1438 */
1439 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1440 ret = iwl_mvm_init_mcc(mvm);
1441 if (ret)
1442 goto error;
1443 }
90d4f7db 1444
859d914c 1445 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1446 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1447 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS
1448 ret = iwl_mvm_config_scan(mvm);
1449 if (ret)
1450 goto error;
1451 }
1452
f130bb75
MG
1453 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1454 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
1455
48e775e6
HD
1456 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1457 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1458
6ce1e5c0
GA
1459 ret = iwl_mvm_ppag_init(mvm);
1460 if (ret)
1461 goto error;
1462
da2830ac 1463 ret = iwl_mvm_sar_init(mvm);
5d041c46
LC
1464 if (ret == 0) {
1465 ret = iwl_mvm_sar_geo_init(mvm);
1edd56e6 1466 } else if (ret == -ENOENT && !iwl_sar_get_wgds_table(&mvm->fwrt)) {
5d041c46
LC
1467 /*
1468 * If basic SAR is not available, we check for WGDS,
1469 * which should *not* be available either. If it is
1470 * available, issue an error, because we can't use SAR
1471 * Geo without basic SAR.
1472 */
1473 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1474 }
da2830ac 1475
5d041c46 1476 if (ret < 0)
a6bff3cb
HD
1477 goto error;
1478
28dd7ccd 1479 iwl_mvm_tas_init(mvm);
7089ae63
JB
1480 iwl_mvm_leds_sync(mvm);
1481
53a9d61e 1482 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB
1483 return 0;
1484 error:
f4744258 1485 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1486 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1487 return ret;
1488}
1489
1490int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1491{
1492 int ret, i;
1493
1494 lockdep_assert_held(&mvm->mutex);
1495
1496 ret = iwl_trans_start_hw(mvm->trans);
1497 if (ret)
1498 return ret;
1499
1500 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1501 if (ret) {
1502 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1503 goto error;
1504 }
1505
a0544272 1506 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1507 if (ret)
1508 goto error;
1509
1510 /* Send phy db control command and then phy db calibration*/
1511 ret = iwl_send_phy_db_data(mvm->phy_db);
1512 if (ret)
1513 goto error;
1514
1515 ret = iwl_send_phy_cfg_cmd(mvm);
1516 if (ret)
1517 goto error;
1518
1519 /* init the fw <-> mac80211 STA mapping */
0ae98812 1520 for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++)
8ca151b5
JB
1521 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1522
1523 /* Add auxiliary station for scanning */
1524 ret = iwl_mvm_add_aux_sta(mvm);
1525 if (ret)
1526 goto error;
1527
1528 return 0;
1529 error:
fcb6b92a 1530 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1531 return ret;
1532}
1533
0416841d
JB
1534void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1535 struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB
1536{
1537 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1538 struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1539 u32 flags = le32_to_cpu(card_state_notif->flags);
1540
1541 IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1542 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1543 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1544 (flags & CT_KILL_CARD_DISABLED) ?
1545 "Reached" : "Not reached");
8ca151b5
JB
1546}
1547
0416841d
JB
1548void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1549 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI
1550{
1551 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1552 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1553
0c8d0a47
GBA
1554 IWL_DEBUG_INFO(mvm,
1555 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1556 le32_to_cpu(mfuart_notif->installed_ver),
1557 le32_to_cpu(mfuart_notif->external_ver),
1558 le32_to_cpu(mfuart_notif->status),
1559 le32_to_cpu(mfuart_notif->duration));
1560
19f63c53
GBA
1561 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1562 IWL_DEBUG_INFO(mvm,
0c8d0a47 1563 "MFUART: image size: 0x%08x\n",
19f63c53 1564 le32_to_cpu(mfuart_notif->image_size));
30269c12 1565}