Commit | Line | Data |
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8e99ea8d JB |
1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
2 | /* | |
4f7411d6 | 3 | * Copyright (C) 2012-2014, 2018-2021 Intel Corporation |
8e99ea8d JB |
4 | * Copyright (C) 2013-2015 Intel Mobile Communications GmbH |
5 | * Copyright (C) 2016-2017 Intel Deutschland GmbH | |
6 | */ | |
8ca151b5 | 7 | #include <net/mac80211.h> |
854d773e | 8 | #include <linux/netdevice.h> |
a2ac0f48 | 9 | #include <linux/dmi.h> |
8ca151b5 JB |
10 | |
11 | #include "iwl-trans.h" | |
12 | #include "iwl-op-mode.h" | |
d962f9b1 | 13 | #include "fw/img.h" |
8ca151b5 JB |
14 | #include "iwl-debug.h" |
15 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
16 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 17 | #include "iwl-prph.h" |
813df5ce | 18 | #include "fw/acpi.h" |
b3e4c0f3 | 19 | #include "fw/pnvm.h" |
8ca151b5 JB |
20 | |
21 | #include "mvm.h" | |
7174beb6 | 22 | #include "fw/dbg.h" |
8ca151b5 | 23 | #include "iwl-phy-db.h" |
9c4f7d51 ST |
24 | #include "iwl-modparams.h" |
25 | #include "iwl-nvm-parse.h" | |
8ca151b5 | 26 | |
b3e4c0f3 LC |
27 | #define MVM_UCODE_ALIVE_TIMEOUT (HZ) |
28 | #define MVM_UCODE_CALIB_TIMEOUT (2 * HZ) | |
8ca151b5 JB |
29 | |
30 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
31 | ||
e12cfc7b MK |
32 | #define IWL_PPAG_MASK 3 |
33 | #define IWL_PPAG_ETSI_MASK BIT(0) | |
34 | ||
8ca151b5 JB |
35 | struct iwl_mvm_alive_data { |
36 | bool valid; | |
37 | u32 scd_base_addr; | |
38 | }; | |
39 | ||
8ca151b5 JB |
40 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) |
41 | { | |
42 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
43 | .valid = cpu_to_le32(valid_tx_ant), | |
44 | }; | |
45 | ||
33223542 | 46 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 47 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
48 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
49 | } | |
50 | ||
43413a97 SS |
51 | static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) |
52 | { | |
53 | int i; | |
54 | struct iwl_rss_config_cmd cmd = { | |
55 | .flags = cpu_to_le32(IWL_RSS_ENABLE), | |
608dce95 SS |
56 | .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | |
57 | BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | | |
58 | BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | | |
59 | BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | | |
60 | BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | | |
61 | BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), | |
43413a97 SS |
62 | }; |
63 | ||
f43495fd SS |
64 | if (mvm->trans->num_rx_queues == 1) |
65 | return 0; | |
66 | ||
854d773e | 67 | /* Do not direct RSS traffic to Q 0 which is our fallback queue */ |
43413a97 | 68 | for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) |
854d773e SS |
69 | cmd.indirection_table[i] = |
70 | 1 + (i % (mvm->trans->num_rx_queues - 1)); | |
71 | netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); | |
43413a97 SS |
72 | |
73 | return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); | |
74 | } | |
75 | ||
97d5be7e LK |
76 | static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) |
77 | { | |
78 | struct iwl_dqa_enable_cmd dqa_cmd = { | |
79 | .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), | |
80 | }; | |
81 | u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); | |
82 | int ret; | |
83 | ||
84 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); | |
85 | if (ret) | |
86 | IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); | |
87 | else | |
88 | IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); | |
89 | ||
90 | return ret; | |
91 | } | |
92 | ||
bdccdb85 GBA |
93 | void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, |
94 | struct iwl_rx_cmd_buffer *rxb) | |
95 | { | |
96 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
97 | struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; | |
98 | __le32 *dump_data = mfu_dump_notif->data; | |
99 | int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); | |
100 | int i; | |
101 | ||
102 | if (mfu_dump_notif->index_num == 0) | |
103 | IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", | |
104 | le32_to_cpu(mfu_dump_notif->assert_id)); | |
105 | ||
106 | for (i = 0; i < n_words; i++) | |
107 | IWL_DEBUG_INFO(mvm, | |
108 | "MFUART assert dump, dword %u: 0x%08x\n", | |
109 | le16_to_cpu(mfu_dump_notif->index_num) * | |
110 | n_words + i, | |
111 | le32_to_cpu(dump_data[i])); | |
112 | } | |
113 | ||
8ca151b5 JB |
114 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
115 | struct iwl_rx_packet *pkt, void *data) | |
116 | { | |
fd1c3318 | 117 | unsigned int pkt_len = iwl_rx_packet_payload_len(pkt); |
8ca151b5 JB |
118 | struct iwl_mvm *mvm = |
119 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
120 | struct iwl_mvm_alive_data *alive_data = data; | |
5c228d63 SS |
121 | struct iwl_umac_alive *umac; |
122 | struct iwl_lmac_alive *lmac1; | |
123 | struct iwl_lmac_alive *lmac2 = NULL; | |
124 | u16 status; | |
cfa5d0ca | 125 | u32 lmac_error_event_table, umac_error_table; |
01a9ca51 | 126 | |
90824f2f LC |
127 | /* |
128 | * For v5 and above, we can check the version, for older | |
129 | * versions we need to check the size. | |
130 | */ | |
b4248c08 | 131 | if (iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP, |
90824f2f LC |
132 | UCODE_ALIVE_NTFY, 0) == 5) { |
133 | struct iwl_alive_ntf_v5 *palive; | |
134 | ||
fd1c3318 JB |
135 | if (pkt_len < sizeof(*palive)) |
136 | return false; | |
137 | ||
90824f2f LC |
138 | palive = (void *)pkt->data; |
139 | umac = &palive->umac_data; | |
140 | lmac1 = &palive->lmac_data[0]; | |
141 | lmac2 = &palive->lmac_data[1]; | |
142 | status = le16_to_cpu(palive->status); | |
143 | ||
144 | mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]); | |
145 | mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]); | |
146 | mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]); | |
147 | ||
148 | IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n", | |
149 | mvm->trans->sku_id[0], | |
150 | mvm->trans->sku_id[1], | |
151 | mvm->trans->sku_id[2]); | |
152 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) { | |
9422b978 LC |
153 | struct iwl_alive_ntf_v4 *palive; |
154 | ||
fd1c3318 JB |
155 | if (pkt_len < sizeof(*palive)) |
156 | return false; | |
157 | ||
5c228d63 SS |
158 | palive = (void *)pkt->data; |
159 | umac = &palive->umac_data; | |
160 | lmac1 = &palive->lmac_data[0]; | |
161 | lmac2 = &palive->lmac_data[1]; | |
162 | status = le16_to_cpu(palive->status); | |
9422b978 LC |
163 | } else if (iwl_rx_packet_payload_len(pkt) == |
164 | sizeof(struct iwl_alive_ntf_v3)) { | |
165 | struct iwl_alive_ntf_v3 *palive3; | |
166 | ||
fd1c3318 JB |
167 | if (pkt_len < sizeof(*palive3)) |
168 | return false; | |
169 | ||
5c228d63 SS |
170 | palive3 = (void *)pkt->data; |
171 | umac = &palive3->umac_data; | |
172 | lmac1 = &palive3->lmac_data; | |
173 | status = le16_to_cpu(palive3->status); | |
9422b978 LC |
174 | } else { |
175 | WARN(1, "unsupported alive notification (size %d)\n", | |
176 | iwl_rx_packet_payload_len(pkt)); | |
177 | /* get timeout later */ | |
178 | return false; | |
5c228d63 | 179 | } |
01a9ca51 | 180 | |
22463857 SM |
181 | lmac_error_event_table = |
182 | le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr); | |
183 | iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table); | |
184 | ||
5c228d63 | 185 | if (lmac2) |
91c28b83 | 186 | mvm->trans->dbg.lmac_error_event_table[1] = |
22463857 | 187 | le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr); |
ffa70264 | 188 | |
4f7411d6 RG |
189 | umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) & |
190 | ~FW_ADDR_CACHE_CONTROL; | |
cfa5d0ca MG |
191 | |
192 | if (umac_error_table) { | |
193 | if (umac_error_table >= | |
194 | mvm->trans->cfg->min_umac_error_event_table) { | |
195 | iwl_fw_umac_set_alive_err_table(mvm->trans, | |
196 | umac_error_table); | |
197 | } else { | |
198 | IWL_ERR(mvm, | |
199 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
200 | umac_error_table, | |
201 | (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? | |
202 | "Init" : "RT"); | |
203 | } | |
3485e76e | 204 | } |
fb5b2846 | 205 | |
22463857 | 206 | alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr); |
5c228d63 | 207 | alive_data->valid = status == IWL_ALIVE_STATUS_OK; |
7e1223b5 | 208 | |
5c228d63 SS |
209 | IWL_DEBUG_FW(mvm, |
210 | "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", | |
211 | status, lmac1->ver_type, lmac1->ver_subtype); | |
7e1223b5 | 212 | |
5c228d63 SS |
213 | if (lmac2) |
214 | IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); | |
7e1223b5 | 215 | |
5c228d63 SS |
216 | IWL_DEBUG_FW(mvm, |
217 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
218 | le32_to_cpu(umac->umac_major), | |
219 | le32_to_cpu(umac->umac_minor)); | |
8ca151b5 | 220 | |
0a3a3e9e SM |
221 | iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac); |
222 | ||
8ca151b5 JB |
223 | return true; |
224 | } | |
225 | ||
1f370650 SS |
226 | static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, |
227 | struct iwl_rx_packet *pkt, void *data) | |
228 | { | |
229 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
230 | ||
231 | return true; | |
232 | } | |
233 | ||
8ca151b5 JB |
234 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, |
235 | struct iwl_rx_packet *pkt, void *data) | |
236 | { | |
237 | struct iwl_phy_db *phy_db = data; | |
238 | ||
239 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
240 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
241 | return true; | |
242 | } | |
243 | ||
ce1f2778 | 244 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); |
8ca151b5 JB |
245 | |
246 | return false; | |
247 | } | |
248 | ||
249 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
250 | enum iwl_ucode_type ucode_type) | |
251 | { | |
252 | struct iwl_notification_wait alive_wait; | |
94a8d87c | 253 | struct iwl_mvm_alive_data alive_data = {}; |
8ca151b5 | 254 | const struct fw_img *fw; |
cfbc6c4c | 255 | int ret; |
702e975d | 256 | enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; |
9422b978 | 257 | static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY }; |
b3500b47 EG |
258 | bool run_in_rfkill = |
259 | ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm); | |
8ca151b5 | 260 | |
61df750c | 261 | if (ucode_type == IWL_UCODE_REGULAR && |
3d2d4422 GBA |
262 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && |
263 | !(fw_has_capa(&mvm->fw->ucode_capa, | |
264 | IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) | |
612da1ef | 265 | fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); |
61df750c | 266 | else |
612da1ef | 267 | fw = iwl_get_ucode_image(mvm->fw, ucode_type); |
befe9b6f | 268 | if (WARN_ON(!fw)) |
8ca151b5 | 269 | return -EINVAL; |
702e975d | 270 | iwl_fw_set_current_image(&mvm->fwrt, ucode_type); |
65b280fe | 271 | clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); |
8ca151b5 JB |
272 | |
273 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
274 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
275 | iwl_alive_fn, &alive_data); | |
276 | ||
b3500b47 EG |
277 | /* |
278 | * We want to load the INIT firmware even in RFKILL | |
279 | * For the unified firmware case, the ucode_type is not | |
280 | * INIT, but we still need to run it. | |
281 | */ | |
282 | ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill); | |
8ca151b5 | 283 | if (ret) { |
702e975d | 284 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
285 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); |
286 | return ret; | |
287 | } | |
288 | ||
289 | /* | |
290 | * Some things may run in the background now, but we | |
291 | * just wait for the ALIVE notification here. | |
292 | */ | |
293 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
294 | MVM_UCODE_ALIVE_TIMEOUT); | |
295 | if (ret) { | |
d6be9c1d SS |
296 | struct iwl_trans *trans = mvm->trans; |
297 | ||
20f5aef5 JB |
298 | if (trans->trans_cfg->device_family >= |
299 | IWL_DEVICE_FAMILY_22000) { | |
d6be9c1d SS |
300 | IWL_ERR(mvm, |
301 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
ea695b7c ST |
302 | iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), |
303 | iwl_read_umac_prph(trans, | |
304 | UMAG_SB_CPU_2_STATUS)); | |
20f5aef5 JB |
305 | IWL_ERR(mvm, "UMAC PC: 0x%x\n", |
306 | iwl_read_umac_prph(trans, | |
307 | UREG_UMAC_CURRENT_PC)); | |
308 | IWL_ERR(mvm, "LMAC PC: 0x%x\n", | |
309 | iwl_read_umac_prph(trans, | |
310 | UREG_LMAC1_CURRENT_PC)); | |
311 | if (iwl_mvm_is_cdb_supported(mvm)) | |
312 | IWL_ERR(mvm, "LMAC2 PC: 0x%x\n", | |
313 | iwl_read_umac_prph(trans, | |
314 | UREG_LMAC2_CURRENT_PC)); | |
315 | } else if (trans->trans_cfg->device_family >= | |
316 | IWL_DEVICE_FAMILY_8000) { | |
192de2b4 DS |
317 | IWL_ERR(mvm, |
318 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
d6be9c1d SS |
319 | iwl_read_prph(trans, SB_CPU_1_STATUS), |
320 | iwl_read_prph(trans, SB_CPU_2_STATUS)); | |
20f5aef5 JB |
321 | } |
322 | ||
323 | if (ret == -ETIMEDOUT) | |
324 | iwl_fw_dbg_error_collect(&mvm->fwrt, | |
325 | FW_DBG_TRIGGER_ALIVE_TIMEOUT); | |
326 | ||
702e975d | 327 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
328 | return ret; |
329 | } | |
330 | ||
331 | if (!alive_data.valid) { | |
332 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
702e975d | 333 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
334 | return -EIO; |
335 | } | |
336 | ||
b3e4c0f3 | 337 | ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait); |
70d3ca86 LC |
338 | if (ret) { |
339 | IWL_ERR(mvm, "Timeout waiting for PNVM load!\n"); | |
340 | iwl_fw_set_current_image(&mvm->fwrt, old_type); | |
341 | return ret; | |
342 | } | |
343 | ||
8ca151b5 JB |
344 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); |
345 | ||
346 | /* | |
347 | * Note: all the queues are enabled as part of the interface | |
348 | * initialization, but in firmware restart scenarios they | |
349 | * could be stopped, so wake them up. In firmware restart, | |
350 | * mac80211 will have the queues stopped as well until the | |
351 | * reconfiguration completes. During normal startup, they | |
352 | * will be empty. | |
353 | */ | |
354 | ||
4ecafae9 | 355 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
1c14089e JB |
356 | /* |
357 | * Set a 'fake' TID for the command queue, since we use the | |
358 | * hweight() of the tid_bitmap as a refcount now. Not that | |
359 | * we ever even consider the command queue as one we might | |
360 | * want to reuse, but be safe nevertheless. | |
361 | */ | |
362 | mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = | |
363 | BIT(IWL_MAX_TID_COUNT + 2); | |
8ca151b5 | 364 | |
65b280fe | 365 | set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); |
f7805b33 LC |
366 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
367 | iwl_fw_set_dbg_rec_on(&mvm->fwrt); | |
368 | #endif | |
8ca151b5 | 369 | |
d3d9b4fc EG |
370 | /* |
371 | * All the BSSes in the BSS table include the GP2 in the system | |
372 | * at the beacon Rx time, this is of course no longer relevant | |
373 | * since we are resetting the firmware. | |
374 | * Purge all the BSS table. | |
375 | */ | |
376 | cfg80211_bss_flush(mvm->hw->wiphy); | |
377 | ||
8ca151b5 JB |
378 | return 0; |
379 | } | |
8ca151b5 | 380 | |
52b15521 | 381 | static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm) |
8c5f47b1 JB |
382 | { |
383 | struct iwl_notification_wait init_wait; | |
384 | struct iwl_nvm_access_complete_cmd nvm_complete = {}; | |
385 | struct iwl_init_extended_cfg_cmd init_cfg = { | |
386 | .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), | |
387 | }; | |
388 | static const u16 init_complete[] = { | |
389 | INIT_COMPLETE_NOTIF, | |
390 | }; | |
391 | int ret; | |
392 | ||
a4584729 HD |
393 | if (mvm->trans->cfg->tx_with_siso_diversity) |
394 | init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); | |
395 | ||
8c5f47b1 JB |
396 | lockdep_assert_held(&mvm->mutex); |
397 | ||
94022562 EG |
398 | mvm->rfkill_safe_init_done = false; |
399 | ||
8c5f47b1 JB |
400 | iwl_init_notification_wait(&mvm->notif_wait, |
401 | &init_wait, | |
402 | init_complete, | |
403 | ARRAY_SIZE(init_complete), | |
404 | iwl_wait_init_complete, | |
405 | NULL); | |
406 | ||
b108d8c7 | 407 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); |
86ce5c74 | 408 | |
8c5f47b1 JB |
409 | /* Will also start the device */ |
410 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
411 | if (ret) { | |
412 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
413 | goto error; | |
414 | } | |
b108d8c7 SM |
415 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, |
416 | NULL); | |
8c5f47b1 JB |
417 | |
418 | /* Send init config command to mark that we are sending NVM access | |
419 | * commands | |
420 | */ | |
421 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, | |
b3500b47 EG |
422 | INIT_EXTENDED_CFG_CMD), |
423 | CMD_SEND_IN_RFKILL, | |
8c5f47b1 JB |
424 | sizeof(init_cfg), &init_cfg); |
425 | if (ret) { | |
426 | IWL_ERR(mvm, "Failed to run init config command: %d\n", | |
427 | ret); | |
428 | goto error; | |
429 | } | |
430 | ||
e9e1ba3d SS |
431 | /* Load NVM to NIC if needed */ |
432 | if (mvm->nvm_file_name) { | |
9ce505fe AN |
433 | ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, |
434 | mvm->nvm_sections); | |
435 | if (ret) | |
436 | goto error; | |
437 | ret = iwl_mvm_load_nvm_to_nic(mvm); | |
438 | if (ret) | |
439 | goto error; | |
e9e1ba3d | 440 | } |
8c5f47b1 | 441 | |
52b15521 | 442 | if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) { |
5bd1d2c1 | 443 | ret = iwl_nvm_init(mvm); |
d4f3695e SS |
444 | if (ret) { |
445 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
446 | goto error; | |
447 | } | |
448 | } | |
449 | ||
8c5f47b1 | 450 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, |
b3500b47 EG |
451 | NVM_ACCESS_COMPLETE), |
452 | CMD_SEND_IN_RFKILL, | |
8c5f47b1 JB |
453 | sizeof(nvm_complete), &nvm_complete); |
454 | if (ret) { | |
455 | IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", | |
456 | ret); | |
457 | goto error; | |
458 | } | |
459 | ||
460 | /* We wait for the INIT complete notification */ | |
e9e1ba3d SS |
461 | ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, |
462 | MVM_UCODE_ALIVE_TIMEOUT); | |
463 | if (ret) | |
464 | return ret; | |
465 | ||
466 | /* Read the NVM only at driver load time, no need to do this twice */ | |
52b15521 | 467 | if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) { |
4c625c56 | 468 | mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); |
c135cb56 ST |
469 | if (IS_ERR(mvm->nvm_data)) { |
470 | ret = PTR_ERR(mvm->nvm_data); | |
471 | mvm->nvm_data = NULL; | |
e9e1ba3d SS |
472 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); |
473 | return ret; | |
474 | } | |
475 | } | |
476 | ||
b3500b47 EG |
477 | mvm->rfkill_safe_init_done = true; |
478 | ||
e9e1ba3d | 479 | return 0; |
8c5f47b1 JB |
480 | |
481 | error: | |
482 | iwl_remove_notification(&mvm->notif_wait, &init_wait); | |
483 | return ret; | |
484 | } | |
485 | ||
c4ace426 GA |
486 | #ifdef CONFIG_ACPI |
487 | static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, | |
488 | struct iwl_phy_specific_cfg *phy_filters) | |
489 | { | |
490 | /* | |
491 | * TODO: read specific phy config from BIOS | |
492 | * ACPI table for this feature has not been defined yet, | |
493 | * so for now we use hardcoded values. | |
494 | */ | |
495 | ||
496 | if (IWL_MVM_PHY_FILTER_CHAIN_A) { | |
497 | phy_filters->filter_cfg_chain_a = | |
498 | cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A); | |
499 | } | |
500 | if (IWL_MVM_PHY_FILTER_CHAIN_B) { | |
501 | phy_filters->filter_cfg_chain_b = | |
502 | cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B); | |
503 | } | |
504 | if (IWL_MVM_PHY_FILTER_CHAIN_C) { | |
505 | phy_filters->filter_cfg_chain_c = | |
506 | cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C); | |
507 | } | |
508 | if (IWL_MVM_PHY_FILTER_CHAIN_D) { | |
509 | phy_filters->filter_cfg_chain_d = | |
510 | cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D); | |
511 | } | |
512 | } | |
513 | ||
514 | #else /* CONFIG_ACPI */ | |
515 | ||
516 | static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, | |
517 | struct iwl_phy_specific_cfg *phy_filters) | |
518 | { | |
519 | } | |
520 | #endif /* CONFIG_ACPI */ | |
521 | ||
8ca151b5 JB |
522 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) |
523 | { | |
c4ace426 | 524 | struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd; |
702e975d | 525 | enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; |
c4ace426 GA |
526 | struct iwl_phy_specific_cfg phy_filters = {}; |
527 | u8 cmd_ver; | |
528 | size_t cmd_size; | |
8ca151b5 | 529 | |
bb99ff9b | 530 | if (iwl_mvm_has_unified_ucode(mvm) && |
d923b020 | 531 | !mvm->trans->cfg->tx_with_siso_diversity) |
bb99ff9b | 532 | return 0; |
d923b020 LC |
533 | |
534 | if (mvm->trans->cfg->tx_with_siso_diversity) { | |
bb99ff9b LC |
535 | /* |
536 | * TODO: currently we don't set the antenna but letting the NIC | |
537 | * to decide which antenna to use. This should come from BIOS. | |
538 | */ | |
539 | phy_cfg_cmd.phy_cfg = | |
540 | cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED); | |
541 | } | |
542 | ||
8ca151b5 | 543 | /* Set parameters */ |
a0544272 | 544 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
86a2b204 LC |
545 | |
546 | /* set flags extra PHY configuration flags from the device's cfg */ | |
7897dfa2 LC |
547 | phy_cfg_cmd.phy_cfg |= |
548 | cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags); | |
86a2b204 | 549 | |
8ca151b5 JB |
550 | phy_cfg_cmd.calib_control.event_trigger = |
551 | mvm->fw->default_calib[ucode_type].event_trigger; | |
552 | phy_cfg_cmd.calib_control.flow_trigger = | |
553 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
554 | ||
c4ace426 | 555 | cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP, |
e80bfd11 MG |
556 | PHY_CONFIGURATION_CMD, |
557 | IWL_FW_CMD_VER_UNKNOWN); | |
c4ace426 GA |
558 | if (cmd_ver == 3) { |
559 | iwl_mvm_phy_filter_init(mvm, &phy_filters); | |
560 | memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters, | |
561 | sizeof(struct iwl_phy_specific_cfg)); | |
562 | } | |
563 | ||
8ca151b5 JB |
564 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", |
565 | phy_cfg_cmd.phy_cfg); | |
c4ace426 GA |
566 | cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) : |
567 | sizeof(struct iwl_phy_cfg_cmd_v1); | |
a1022927 | 568 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
c4ace426 | 569 | cmd_size, &phy_cfg_cmd); |
8ca151b5 JB |
570 | } |
571 | ||
3b25f1af | 572 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm) |
8ca151b5 JB |
573 | { |
574 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 575 | static const u16 init_complete[] = { |
8ca151b5 JB |
576 | INIT_COMPLETE_NOTIF, |
577 | CALIB_RES_NOTIF_PHY_DB | |
578 | }; | |
579 | int ret; | |
580 | ||
7d6222e2 | 581 | if (iwl_mvm_has_unified_ucode(mvm)) |
52b15521 | 582 | return iwl_run_unified_mvm_ucode(mvm); |
8c5f47b1 | 583 | |
8ca151b5 JB |
584 | lockdep_assert_held(&mvm->mutex); |
585 | ||
94022562 | 586 | mvm->rfkill_safe_init_done = false; |
8ca151b5 JB |
587 | |
588 | iwl_init_notification_wait(&mvm->notif_wait, | |
589 | &calib_wait, | |
590 | init_complete, | |
591 | ARRAY_SIZE(init_complete), | |
592 | iwl_wait_phy_db_entry, | |
593 | mvm->phy_db); | |
594 | ||
11f8c533 LC |
595 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); |
596 | ||
8ca151b5 JB |
597 | /* Will also start the device */ |
598 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
599 | if (ret) { | |
600 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
00e0c6c8 | 601 | goto remove_notif; |
8ca151b5 JB |
602 | } |
603 | ||
7d34a7d7 | 604 | if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) { |
b3de3ef4 EG |
605 | ret = iwl_mvm_send_bt_init_conf(mvm); |
606 | if (ret) | |
00e0c6c8 | 607 | goto remove_notif; |
b3de3ef4 | 608 | } |
931d4160 | 609 | |
81a67e32 | 610 | /* Read the NVM only at driver load time, no need to do this twice */ |
3b25f1af | 611 | if (!mvm->nvm_data) { |
5bd1d2c1 | 612 | ret = iwl_nvm_init(mvm); |
8ca151b5 JB |
613 | if (ret) { |
614 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
00e0c6c8 | 615 | goto remove_notif; |
8ca151b5 JB |
616 | } |
617 | } | |
618 | ||
81a67e32 | 619 | /* In case we read the NVM from external file, load it to the NIC */ |
9ce505fe AN |
620 | if (mvm->nvm_file_name) { |
621 | ret = iwl_mvm_load_nvm_to_nic(mvm); | |
622 | if (ret) | |
623 | goto remove_notif; | |
624 | } | |
81a67e32 | 625 | |
64866e5d LC |
626 | WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver, |
627 | "Too old NVM version (0x%0x, required = 0x%0x)", | |
628 | mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver); | |
8ca151b5 | 629 | |
4f59334b EH |
630 | /* |
631 | * abort after reading the nvm in case RF Kill is on, we will complete | |
632 | * the init seq later when RF kill will switch to off | |
633 | */ | |
1a3fe0b2 | 634 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
635 | IWL_DEBUG_RF_KILL(mvm, |
636 | "jump over all phy activities due to RF kill\n"); | |
00e0c6c8 | 637 | goto remove_notif; |
4f59334b EH |
638 | } |
639 | ||
b3500b47 | 640 | mvm->rfkill_safe_init_done = true; |
31b8b343 | 641 | |
e07cbb53 | 642 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 643 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 | 644 | if (ret) |
00e0c6c8 | 645 | goto remove_notif; |
e07cbb53 | 646 | |
8ca151b5 JB |
647 | ret = iwl_send_phy_cfg_cmd(mvm); |
648 | if (ret) { | |
649 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
650 | ret); | |
00e0c6c8 | 651 | goto remove_notif; |
8ca151b5 JB |
652 | } |
653 | ||
654 | /* | |
655 | * Some things may run in the background now, but we | |
656 | * just wait for the calibration complete notification. | |
657 | */ | |
658 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
00e0c6c8 LC |
659 | MVM_UCODE_CALIB_TIMEOUT); |
660 | if (!ret) | |
661 | goto out; | |
31b8b343 | 662 | |
00e0c6c8 | 663 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 | 664 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
00e0c6c8 LC |
665 | ret = 0; |
666 | } else { | |
667 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
668 | ret); | |
31b8b343 | 669 | } |
00e0c6c8 | 670 | |
8ca151b5 JB |
671 | goto out; |
672 | ||
00e0c6c8 | 673 | remove_notif: |
8ca151b5 JB |
674 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); |
675 | out: | |
b3500b47 | 676 | mvm->rfkill_safe_init_done = false; |
a4082843 | 677 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
678 | /* we want to debug INIT and we have no NVM - fake */ |
679 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
680 | sizeof(struct ieee80211_channel) + | |
681 | sizeof(struct ieee80211_rate), | |
682 | GFP_KERNEL); | |
683 | if (!mvm->nvm_data) | |
684 | return -ENOMEM; | |
8ca151b5 JB |
685 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
686 | mvm->nvm_data->bands[0].n_channels = 1; | |
687 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
688 | mvm->nvm_data->bands[0].bitrates = | |
689 | (void *)mvm->nvm_data->channels + 1; | |
690 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
691 | } | |
692 | ||
693 | return ret; | |
694 | } | |
695 | ||
84bfffa9 EG |
696 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
697 | { | |
698 | struct iwl_ltr_config_cmd cmd = { | |
699 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
700 | }; | |
701 | ||
702 | if (!mvm->trans->ltr_enabled) | |
703 | return 0; | |
704 | ||
84bfffa9 EG |
705 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
706 | sizeof(cmd), &cmd); | |
707 | } | |
708 | ||
c386dacb | 709 | #ifdef CONFIG_ACPI |
42ce76d6 | 710 | int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) |
da2830ac | 711 | { |
216cdfb5 LC |
712 | struct iwl_dev_tx_power_cmd cmd = { |
713 | .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS), | |
71e9378b | 714 | }; |
9c08cef8 | 715 | __le16 *per_chain; |
1edd56e6 | 716 | int ret; |
39c1a972 | 717 | u16 len = 0; |
fbb7957d LC |
718 | u32 n_subbands; |
719 | u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP, | |
e80bfd11 MG |
720 | REDUCE_TX_POWER_CMD, |
721 | IWL_FW_CMD_VER_UNKNOWN); | |
fbb7957d LC |
722 | |
723 | if (cmd_ver == 6) { | |
724 | len = sizeof(cmd.v6); | |
725 | n_subbands = IWL_NUM_SUB_BANDS_V2; | |
726 | per_chain = cmd.v6.per_chain[0][0]; | |
727 | } else if (fw_has_api(&mvm->fw->ucode_capa, | |
728 | IWL_UCODE_TLV_API_REDUCE_TX_POWER)) { | |
0791c2fc | 729 | len = sizeof(cmd.v5); |
e12cfc7b | 730 | n_subbands = IWL_NUM_SUB_BANDS_V1; |
9c08cef8 LC |
731 | per_chain = cmd.v5.per_chain[0][0]; |
732 | } else if (fw_has_capa(&mvm->fw->ucode_capa, | |
fbb7957d | 733 | IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) { |
216cdfb5 | 734 | len = sizeof(cmd.v4); |
e12cfc7b | 735 | n_subbands = IWL_NUM_SUB_BANDS_V1; |
9c08cef8 LC |
736 | per_chain = cmd.v4.per_chain[0][0]; |
737 | } else { | |
216cdfb5 | 738 | len = sizeof(cmd.v3); |
e12cfc7b | 739 | n_subbands = IWL_NUM_SUB_BANDS_V1; |
9c08cef8 LC |
740 | per_chain = cmd.v3.per_chain[0][0]; |
741 | } | |
55bfa4b9 | 742 | |
216cdfb5 LC |
743 | /* all structs have the same common part, add it */ |
744 | len += sizeof(cmd.common); | |
da2830ac | 745 | |
dac7171c LC |
746 | ret = iwl_sar_select_profile(&mvm->fwrt, per_chain, |
747 | IWL_NUM_CHAIN_TABLES, | |
fbb7957d | 748 | n_subbands, prof_a, prof_b); |
1edd56e6 LC |
749 | |
750 | /* return on error or if the profile is disabled (positive number) */ | |
751 | if (ret) | |
752 | return ret; | |
753 | ||
42ce76d6 | 754 | IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); |
42ce76d6 LC |
755 | return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); |
756 | } | |
757 | ||
7fe90e0e HD |
758 | int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) |
759 | { | |
dd2a1256 | 760 | union iwl_geo_tx_power_profiles_cmd geo_tx_cmd; |
f604324e | 761 | struct iwl_geo_tx_power_profiles_resp *resp; |
0c3d7282 | 762 | u16 len; |
39c1a972 | 763 | int ret; |
0c3d7282 | 764 | struct iwl_host_cmd cmd; |
e80bfd11 MG |
765 | u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, |
766 | GEO_TX_POWER_LIMIT, | |
767 | IWL_FW_CMD_VER_UNKNOWN); | |
0c3d7282 | 768 | |
dd2a1256 LC |
769 | /* the ops field is at the same spot for all versions, so set in v1 */ |
770 | geo_tx_cmd.v1.ops = | |
771 | cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); | |
772 | ||
0ea788ed LC |
773 | if (cmd_ver == 3) |
774 | len = sizeof(geo_tx_cmd.v3); | |
775 | else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, | |
776 | IWL_UCODE_TLV_API_SAR_TABLE_VER)) | |
dd2a1256 LC |
777 | len = sizeof(geo_tx_cmd.v2); |
778 | else | |
779 | len = sizeof(geo_tx_cmd.v1); | |
7fe90e0e | 780 | |
39c1a972 IZ |
781 | if (!iwl_sar_geo_support(&mvm->fwrt)) |
782 | return -EOPNOTSUPP; | |
783 | ||
0c3d7282 | 784 | cmd = (struct iwl_host_cmd){ |
7fe90e0e | 785 | .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), |
0c3d7282 | 786 | .len = { len, }, |
7fe90e0e | 787 | .flags = CMD_WANT_SKB, |
39c1a972 | 788 | .data = { &geo_tx_cmd }, |
7fe90e0e HD |
789 | }; |
790 | ||
791 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
792 | if (ret) { | |
793 | IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); | |
794 | return ret; | |
795 | } | |
f604324e LC |
796 | |
797 | resp = (void *)cmd.resp_pkt->data; | |
798 | ret = le32_to_cpu(resp->profile_idx); | |
799 | ||
800 | if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES)) | |
801 | ret = -EIO; | |
802 | ||
7fe90e0e HD |
803 | iwl_free_resp(&cmd); |
804 | return ret; | |
805 | } | |
806 | ||
a6bff3cb HD |
807 | static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) |
808 | { | |
dd2a1256 | 809 | union iwl_geo_tx_power_profiles_cmd cmd; |
39c1a972 | 810 | u16 len; |
45acebf8 | 811 | u32 n_bands; |
0433ae55 | 812 | int ret; |
e80bfd11 MG |
813 | u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, |
814 | GEO_TX_POWER_LIMIT, | |
815 | IWL_FW_CMD_VER_UNKNOWN); | |
a6bff3cb | 816 | |
45acebf8 NG |
817 | BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) != |
818 | offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) || | |
819 | offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) != | |
820 | offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops)); | |
dd2a1256 LC |
821 | /* the ops field is at the same spot for all versions, so set in v1 */ |
822 | cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES); | |
0c3d7282 | 823 | |
0ea788ed LC |
824 | if (cmd_ver == 3) { |
825 | len = sizeof(cmd.v3); | |
45acebf8 | 826 | n_bands = ARRAY_SIZE(cmd.v3.table[0]); |
0ea788ed LC |
827 | } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, |
828 | IWL_UCODE_TLV_API_SAR_TABLE_VER)) { | |
dd2a1256 | 829 | len = sizeof(cmd.v2); |
45acebf8 | 830 | n_bands = ARRAY_SIZE(cmd.v2.table[0]); |
39c1a972 | 831 | } else { |
dd2a1256 | 832 | len = sizeof(cmd.v1); |
45acebf8 | 833 | n_bands = ARRAY_SIZE(cmd.v1.table[0]); |
0c3d7282 HD |
834 | } |
835 | ||
45acebf8 NG |
836 | BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) != |
837 | offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) || | |
838 | offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) != | |
839 | offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table)); | |
840 | /* the table is at the same position for all versions, so set use v1 */ | |
841 | ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0], n_bands); | |
842 | ||
843 | /* | |
844 | * It is a valid scenario to not support SAR, or miss wgds table, | |
845 | * but in that case there is no need to send the command. | |
846 | */ | |
847 | if (ret) | |
848 | return 0; | |
849 | ||
28db1862 LC |
850 | /* |
851 | * Set the revision on versions that contain it. | |
852 | * This must be done after calling iwl_sar_geo_init(). | |
853 | */ | |
854 | if (cmd_ver == 3) | |
855 | cmd.v3.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); | |
856 | else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, | |
857 | IWL_UCODE_TLV_API_SAR_TABLE_VER)) | |
858 | cmd.v2.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); | |
859 | ||
dd2a1256 LC |
860 | return iwl_mvm_send_cmd_pdu(mvm, |
861 | WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), | |
862 | 0, len, &cmd); | |
a6bff3cb HD |
863 | } |
864 | ||
6ce1e5c0 GA |
865 | static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm) |
866 | { | |
e12cfc7b | 867 | union acpi_object *wifi_pkg, *data, *flags; |
f2134f66 | 868 | int i, j, ret, tbl_rev, num_sub_bands; |
6ce1e5c0 | 869 | int idx = 2; |
f2134f66 | 870 | s8 *gain; |
6ce1e5c0 | 871 | |
f2134f66 | 872 | /* |
e12cfc7b | 873 | * The 'flags' field is the same in v1 and in v2 so we can just |
f2134f66 GA |
874 | * use v1 to access it. |
875 | */ | |
e12cfc7b MK |
876 | mvm->fwrt.ppag_table.v1.flags = cpu_to_le32(0); |
877 | ||
6ce1e5c0 GA |
878 | data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD); |
879 | if (IS_ERR(data)) | |
880 | return PTR_ERR(data); | |
881 | ||
e12cfc7b | 882 | /* try to read ppag table rev 2 or 1 (both have the same data size) */ |
6ce1e5c0 | 883 | wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, |
f2134f66 GA |
884 | ACPI_PPAG_WIFI_DATA_SIZE_V2, &tbl_rev); |
885 | if (!IS_ERR(wifi_pkg)) { | |
e12cfc7b MK |
886 | if (tbl_rev == 1 || tbl_rev == 2) { |
887 | num_sub_bands = IWL_NUM_SUB_BANDS_V2; | |
888 | gain = mvm->fwrt.ppag_table.v2.gain[0]; | |
889 | mvm->fwrt.ppag_ver = tbl_rev; | |
890 | IWL_DEBUG_RADIO(mvm, | |
891 | "Reading PPAG table v2 (tbl_rev=%d)\n", | |
892 | tbl_rev); | |
893 | goto read_table; | |
894 | } else { | |
f2134f66 GA |
895 | ret = -EINVAL; |
896 | goto out_free; | |
897 | } | |
6ce1e5c0 GA |
898 | } |
899 | ||
f2134f66 GA |
900 | /* try to read ppag table revision 0 */ |
901 | wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, | |
e12cfc7b | 902 | ACPI_PPAG_WIFI_DATA_SIZE_V1, &tbl_rev); |
f2134f66 GA |
903 | if (!IS_ERR(wifi_pkg)) { |
904 | if (tbl_rev != 0) { | |
905 | ret = -EINVAL; | |
906 | goto out_free; | |
907 | } | |
e12cfc7b | 908 | num_sub_bands = IWL_NUM_SUB_BANDS_V1; |
f2134f66 | 909 | gain = mvm->fwrt.ppag_table.v1.gain[0]; |
e12cfc7b | 910 | mvm->fwrt.ppag_ver = 0; |
f2134f66 GA |
911 | IWL_DEBUG_RADIO(mvm, "Reading PPAG table v1 (tbl_rev=0)\n"); |
912 | goto read_table; | |
3ed83da3 | 913 | } |
f2134f66 GA |
914 | ret = PTR_ERR(wifi_pkg); |
915 | goto out_free; | |
3ed83da3 | 916 | |
f2134f66 | 917 | read_table: |
e12cfc7b MK |
918 | flags = &wifi_pkg->package.elements[1]; |
919 | ||
920 | if (flags->type != ACPI_TYPE_INTEGER) { | |
6ce1e5c0 GA |
921 | ret = -EINVAL; |
922 | goto out_free; | |
923 | } | |
924 | ||
e12cfc7b MK |
925 | mvm->fwrt.ppag_table.v1.flags = cpu_to_le32(flags->integer.value & |
926 | IWL_PPAG_MASK); | |
927 | ||
928 | if (!mvm->fwrt.ppag_table.v1.flags) { | |
6ce1e5c0 GA |
929 | ret = 0; |
930 | goto out_free; | |
931 | } | |
932 | ||
933 | /* | |
934 | * read, verify gain values and save them into the PPAG table. | |
935 | * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the | |
936 | * following sub-bands to High-Band (5GHz). | |
937 | */ | |
f2134f66 GA |
938 | for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { |
939 | for (j = 0; j < num_sub_bands; j++) { | |
6ce1e5c0 GA |
940 | union acpi_object *ent; |
941 | ||
942 | ent = &wifi_pkg->package.elements[idx++]; | |
5a684245 | 943 | if (ent->type != ACPI_TYPE_INTEGER) { |
6ce1e5c0 GA |
944 | ret = -EINVAL; |
945 | goto out_free; | |
946 | } | |
5a684245 | 947 | |
f2134f66 | 948 | gain[i * num_sub_bands + j] = ent->integer.value; |
5a684245 LC |
949 | |
950 | if ((j == 0 && | |
951 | (gain[i * num_sub_bands + j] > ACPI_PPAG_MAX_LB || | |
952 | gain[i * num_sub_bands + j] < ACPI_PPAG_MIN_LB)) || | |
953 | (j != 0 && | |
954 | (gain[i * num_sub_bands + j] > ACPI_PPAG_MAX_HB || | |
955 | gain[i * num_sub_bands + j] < ACPI_PPAG_MIN_HB))) { | |
e12cfc7b | 956 | mvm->fwrt.ppag_table.v1.flags = cpu_to_le32(0); |
5a684245 LC |
957 | ret = -EINVAL; |
958 | goto out_free; | |
959 | } | |
6ce1e5c0 GA |
960 | } |
961 | } | |
e12cfc7b | 962 | |
6ce1e5c0 GA |
963 | ret = 0; |
964 | out_free: | |
965 | kfree(data); | |
966 | return ret; | |
967 | } | |
968 | ||
969 | int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) | |
970 | { | |
f2134f66 GA |
971 | u8 cmd_ver; |
972 | int i, j, ret, num_sub_bands, cmd_size; | |
f2134f66 | 973 | s8 *gain; |
6ce1e5c0 GA |
974 | |
975 | if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) { | |
976 | IWL_DEBUG_RADIO(mvm, | |
977 | "PPAG capability not supported by FW, command not sent.\n"); | |
978 | return 0; | |
979 | } | |
e12cfc7b | 980 | if (!mvm->fwrt.ppag_table.v1.flags) { |
f2134f66 | 981 | IWL_DEBUG_RADIO(mvm, "PPAG not enabled, command not sent.\n"); |
160bab43 GA |
982 | return 0; |
983 | } | |
984 | ||
f2134f66 | 985 | cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, |
e80bfd11 MG |
986 | PER_PLATFORM_ANT_GAIN_CMD, |
987 | IWL_FW_CMD_VER_UNKNOWN); | |
f2134f66 | 988 | if (cmd_ver == 1) { |
e12cfc7b | 989 | num_sub_bands = IWL_NUM_SUB_BANDS_V1; |
f2134f66 | 990 | gain = mvm->fwrt.ppag_table.v1.gain[0]; |
659844d3 | 991 | cmd_size = sizeof(mvm->fwrt.ppag_table.v1); |
e12cfc7b | 992 | if (mvm->fwrt.ppag_ver == 1 || mvm->fwrt.ppag_ver == 2) { |
f2134f66 | 993 | IWL_DEBUG_RADIO(mvm, |
e12cfc7b MK |
994 | "PPAG table rev is %d but FW supports v1, sending truncated table\n", |
995 | mvm->fwrt.ppag_ver); | |
996 | mvm->fwrt.ppag_table.v1.flags &= | |
997 | cpu_to_le32(IWL_PPAG_ETSI_MASK); | |
f2134f66 | 998 | } |
e12cfc7b | 999 | } else if (cmd_ver == 2 || cmd_ver == 3) { |
f2134f66 GA |
1000 | num_sub_bands = IWL_NUM_SUB_BANDS_V2; |
1001 | gain = mvm->fwrt.ppag_table.v2.gain[0]; | |
659844d3 | 1002 | cmd_size = sizeof(mvm->fwrt.ppag_table.v2); |
e12cfc7b | 1003 | if (mvm->fwrt.ppag_ver == 0) { |
f2134f66 GA |
1004 | IWL_DEBUG_RADIO(mvm, |
1005 | "PPAG table is v1 but FW supports v2, sending padded table\n"); | |
e12cfc7b MK |
1006 | } else if (cmd_ver == 2 && mvm->fwrt.ppag_ver == 2) { |
1007 | IWL_DEBUG_RADIO(mvm, | |
1008 | "PPAG table is v3 but FW supports v2, sending partial bitmap.\n"); | |
1009 | mvm->fwrt.ppag_table.v1.flags &= | |
1010 | cpu_to_le32(IWL_PPAG_ETSI_MASK); | |
f2134f66 GA |
1011 | } |
1012 | } else { | |
1013 | IWL_DEBUG_RADIO(mvm, "Unsupported PPAG command version\n"); | |
1014 | return 0; | |
1015 | } | |
6ce1e5c0 | 1016 | |
f2134f66 GA |
1017 | for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { |
1018 | for (j = 0; j < num_sub_bands; j++) { | |
6ce1e5c0 GA |
1019 | IWL_DEBUG_RADIO(mvm, |
1020 | "PPAG table: chain[%d] band[%d]: gain = %d\n", | |
f2134f66 | 1021 | i, j, gain[i * num_sub_bands + j]); |
6ce1e5c0 GA |
1022 | } |
1023 | } | |
f2134f66 | 1024 | IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n"); |
6ce1e5c0 GA |
1025 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP, |
1026 | PER_PLATFORM_ANT_GAIN_CMD), | |
659844d3 | 1027 | 0, cmd_size, &mvm->fwrt.ppag_table); |
6ce1e5c0 GA |
1028 | if (ret < 0) |
1029 | IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n", | |
1030 | ret); | |
1031 | ||
1032 | return ret; | |
1033 | } | |
1034 | ||
a2ac0f48 | 1035 | static const struct dmi_system_id dmi_ppag_approved_list[] = { |
ca176edd LC |
1036 | { .ident = "HP", |
1037 | .matches = { | |
1038 | DMI_MATCH(DMI_SYS_VENDOR, "HP"), | |
1039 | }, | |
1040 | }, | |
dd158ed6 LC |
1041 | { .ident = "SAMSUNG", |
1042 | .matches = { | |
1043 | DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"), | |
1044 | }, | |
1045 | }, | |
4a76553c LC |
1046 | { .ident = "MSFT", |
1047 | .matches = { | |
1048 | DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"), | |
1049 | }, | |
1050 | }, | |
a7abc1ea LC |
1051 | { .ident = "ASUS", |
1052 | .matches = { | |
1053 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek COMPUTER INC."), | |
1054 | }, | |
1055 | }, | |
a22549f1 | 1056 | {} |
a2ac0f48 LC |
1057 | }; |
1058 | ||
6ce1e5c0 GA |
1059 | static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) |
1060 | { | |
78a19d52 | 1061 | /* no need to read the table, done in INIT stage */ |
a2ac0f48 LC |
1062 | if (!dmi_check_system(dmi_ppag_approved_list)) { |
1063 | IWL_DEBUG_RADIO(mvm, | |
1064 | "System vendor '%s' is not in the approved list, disabling PPAG.\n", | |
1065 | dmi_get_system_info(DMI_SYS_VENDOR)); | |
e12cfc7b | 1066 | mvm->fwrt.ppag_table.v1.flags = cpu_to_le32(0); |
a2ac0f48 LC |
1067 | return 0; |
1068 | } | |
1069 | ||
6ce1e5c0 GA |
1070 | return iwl_mvm_ppag_send_cmd(mvm); |
1071 | } | |
1072 | ||
28dd7ccd MG |
1073 | static void iwl_mvm_tas_init(struct iwl_mvm *mvm) |
1074 | { | |
1075 | int ret; | |
1076 | struct iwl_tas_config_cmd cmd = {}; | |
1077 | int list_size; | |
1078 | ||
cdaba917 | 1079 | BUILD_BUG_ON(ARRAY_SIZE(cmd.block_list_array) < |
28dd7ccd MG |
1080 | APCI_WTAS_BLACK_LIST_MAX); |
1081 | ||
1082 | if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) { | |
1083 | IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n"); | |
1084 | return; | |
1085 | } | |
1086 | ||
cdaba917 | 1087 | ret = iwl_acpi_get_tas(&mvm->fwrt, cmd.block_list_array, &list_size); |
28dd7ccd MG |
1088 | if (ret < 0) { |
1089 | IWL_DEBUG_RADIO(mvm, | |
1090 | "TAS table invalid or unavailable. (%d)\n", | |
1091 | ret); | |
1092 | return; | |
1093 | } | |
1094 | ||
1095 | if (list_size < 0) | |
1096 | return; | |
1097 | ||
1098 | /* list size if TAS enabled can only be non-negative */ | |
cdaba917 | 1099 | cmd.block_list_size = cpu_to_le32((u32)list_size); |
28dd7ccd MG |
1100 | |
1101 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, | |
1102 | TAS_CONFIG), | |
1103 | 0, sizeof(cmd), &cmd); | |
1104 | if (ret < 0) | |
1105 | IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret); | |
1106 | } | |
f5b1cb2e | 1107 | |
4e8fe214 GG |
1108 | static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm) |
1109 | { | |
1110 | u8 value; | |
1111 | int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, DSM_RFI_FUNC_ENABLE, | |
1112 | &iwl_rfi_guid, &value); | |
1113 | ||
1114 | if (ret < 0) { | |
1115 | IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret); | |
1116 | ||
1117 | } else if (value >= DSM_VALUE_RFI_MAX) { | |
1118 | IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n", | |
1119 | value); | |
1120 | ||
1121 | } else if (value == DSM_VALUE_RFI_ENABLE) { | |
1122 | IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n"); | |
1123 | return DSM_VALUE_RFI_ENABLE; | |
1124 | } | |
1125 | ||
1126 | IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n"); | |
1127 | ||
1128 | /* default behaviour is disabled */ | |
1129 | return DSM_VALUE_RFI_DISABLE; | |
1130 | } | |
1131 | ||
f5b1cb2e GA |
1132 | static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) |
1133 | { | |
7119f02b MK |
1134 | int ret; |
1135 | u32 value; | |
54b4fda5 | 1136 | struct iwl_lari_config_change_cmd_v4 cmd = {}; |
f5b1cb2e | 1137 | |
f21afaba | 1138 | cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt); |
d2bfda8a | 1139 | |
7119f02b MK |
1140 | ret = iwl_acpi_get_dsm_u32((&mvm->fwrt)->dev, 0, DSM_FUNC_11AX_ENABLEMENT, |
1141 | &iwl_guid, &value); | |
1142 | if (!ret) | |
1143 | cmd.oem_11ax_allow_bitmap = cpu_to_le32(value); | |
f5b1cb2e GA |
1144 | /* apply more config masks here */ |
1145 | ||
54b4fda5 AN |
1146 | ret = iwl_acpi_get_dsm_u32((&mvm->fwrt)->dev, 0, |
1147 | DSM_FUNC_ENABLE_UNII4_CHAN, | |
1148 | &iwl_guid, &value); | |
1149 | if (!ret) | |
1150 | cmd.oem_unii4_allow_bitmap = cpu_to_le32(value); | |
1151 | ||
1152 | if (cmd.config_bitmap || | |
1153 | cmd.oem_11ax_allow_bitmap || | |
1154 | cmd.oem_unii4_allow_bitmap) { | |
3c21990b MK |
1155 | size_t cmd_size; |
1156 | u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, | |
1157 | REGULATORY_AND_NVM_GROUP, | |
1158 | LARI_CONFIG_CHANGE, 1); | |
54b4fda5 AN |
1159 | if (cmd_ver == 4) |
1160 | cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4); | |
1161 | else if (cmd_ver == 3) | |
3c21990b MK |
1162 | cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3); |
1163 | else if (cmd_ver == 2) | |
1164 | cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2); | |
1165 | else | |
1166 | cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1); | |
1167 | ||
3ce88247 | 1168 | IWL_DEBUG_RADIO(mvm, |
7119f02b MK |
1169 | "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n", |
1170 | le32_to_cpu(cmd.config_bitmap), | |
1171 | le32_to_cpu(cmd.oem_11ax_allow_bitmap)); | |
54b4fda5 AN |
1172 | IWL_DEBUG_RADIO(mvm, |
1173 | "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, cmd_ver=%d\n", | |
1174 | le32_to_cpu(cmd.oem_unii4_allow_bitmap), | |
1175 | cmd_ver); | |
7119f02b MK |
1176 | ret = iwl_mvm_send_cmd_pdu(mvm, |
1177 | WIDE_ID(REGULATORY_AND_NVM_GROUP, | |
1178 | LARI_CONFIG_CHANGE), | |
1179 | 0, cmd_size, &cmd); | |
1180 | if (ret < 0) | |
f5b1cb2e GA |
1181 | IWL_DEBUG_RADIO(mvm, |
1182 | "Failed to send LARI_CONFIG_CHANGE (%d)\n", | |
7119f02b | 1183 | ret); |
f5b1cb2e GA |
1184 | } |
1185 | } | |
78a19d52 MK |
1186 | |
1187 | void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm) | |
1188 | { | |
1189 | int ret; | |
1190 | ||
1191 | /* read PPAG table */ | |
1192 | ret = iwl_mvm_get_ppag_table(mvm); | |
1193 | if (ret < 0) { | |
1194 | IWL_DEBUG_RADIO(mvm, | |
1195 | "PPAG BIOS table invalid or unavailable. (%d)\n", | |
1196 | ret); | |
1197 | } | |
1198 | ||
1199 | /* read SAR tables */ | |
1200 | ret = iwl_sar_get_wrds_table(&mvm->fwrt); | |
1201 | if (ret < 0) { | |
1202 | IWL_DEBUG_RADIO(mvm, | |
1203 | "WRDS SAR BIOS table invalid or unavailable. (%d)\n", | |
1204 | ret); | |
1205 | /* | |
1206 | * If not available, don't fail and don't bother with EWRD and | |
1207 | * WGDS */ | |
1208 | ||
1209 | if (!iwl_sar_get_wgds_table(&mvm->fwrt)) { | |
1210 | /* | |
1211 | * If basic SAR is not available, we check for WGDS, | |
1212 | * which should *not* be available either. If it is | |
1213 | * available, issue an error, because we can't use SAR | |
1214 | * Geo without basic SAR. | |
1215 | */ | |
1216 | IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); | |
1217 | } | |
1218 | ||
1219 | } else { | |
1220 | ret = iwl_sar_get_ewrd_table(&mvm->fwrt); | |
1221 | /* if EWRD is not available, we can still use | |
1222 | * WRDS, so don't fail */ | |
1223 | if (ret < 0) | |
1224 | IWL_DEBUG_RADIO(mvm, | |
1225 | "EWRD SAR BIOS table invalid or unavailable. (%d)\n", | |
1226 | ret); | |
1227 | ||
1228 | /* read geo SAR table */ | |
1229 | if (iwl_sar_geo_support(&mvm->fwrt)) { | |
1230 | ret = iwl_sar_get_wgds_table(&mvm->fwrt); | |
1231 | if (ret < 0) | |
1232 | IWL_DEBUG_RADIO(mvm, | |
1233 | "Geo SAR BIOS table invalid or unavailable. (%d)\n", | |
1234 | ret); | |
1235 | /* we don't fail if the table is not available */ | |
1236 | } | |
1237 | } | |
1238 | } | |
69964905 | 1239 | #else /* CONFIG_ACPI */ |
69964905 | 1240 | |
39c1a972 IZ |
1241 | inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, |
1242 | int prof_a, int prof_b) | |
69964905 | 1243 | { |
78a19d52 | 1244 | return 1; |
69964905 | 1245 | } |
a6bff3cb | 1246 | |
39c1a972 | 1247 | inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) |
5d041c46 LC |
1248 | { |
1249 | return -ENOENT; | |
1250 | } | |
1251 | ||
a6bff3cb HD |
1252 | static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) |
1253 | { | |
1254 | return 0; | |
1255 | } | |
18f1755d | 1256 | |
6ce1e5c0 GA |
1257 | int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) |
1258 | { | |
1259 | return -ENOENT; | |
1260 | } | |
1261 | ||
1262 | static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) | |
1263 | { | |
7937fd32 | 1264 | return 0; |
6ce1e5c0 | 1265 | } |
28dd7ccd MG |
1266 | |
1267 | static void iwl_mvm_tas_init(struct iwl_mvm *mvm) | |
1268 | { | |
1269 | } | |
f5b1cb2e GA |
1270 | |
1271 | static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) | |
1272 | { | |
1273 | } | |
4e8fe214 GG |
1274 | |
1275 | static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm) | |
1276 | { | |
1277 | return DSM_VALUE_RFI_DISABLE; | |
1278 | } | |
78a19d52 MK |
1279 | |
1280 | void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm) | |
1281 | { | |
1282 | } | |
69964905 LC |
1283 | #endif /* CONFIG_ACPI */ |
1284 | ||
f130bb75 MG |
1285 | void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags) |
1286 | { | |
1287 | u32 error_log_size = mvm->fw->ucode_capa.error_log_size; | |
1288 | int ret; | |
1289 | u32 resp; | |
1290 | ||
1291 | struct iwl_fw_error_recovery_cmd recovery_cmd = { | |
1292 | .flags = cpu_to_le32(flags), | |
1293 | .buf_size = 0, | |
1294 | }; | |
1295 | struct iwl_host_cmd host_cmd = { | |
1296 | .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD), | |
1297 | .flags = CMD_WANT_SKB, | |
1298 | .data = {&recovery_cmd, }, | |
1299 | .len = {sizeof(recovery_cmd), }, | |
1300 | }; | |
1301 | ||
1302 | /* no error log was defined in TLV */ | |
1303 | if (!error_log_size) | |
1304 | return; | |
1305 | ||
1306 | if (flags & ERROR_RECOVERY_UPDATE_DB) { | |
1307 | /* no buf was allocated while HW reset */ | |
1308 | if (!mvm->error_recovery_buf) | |
1309 | return; | |
1310 | ||
1311 | host_cmd.data[1] = mvm->error_recovery_buf; | |
1312 | host_cmd.len[1] = error_log_size; | |
1313 | host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; | |
1314 | recovery_cmd.buf_size = cpu_to_le32(error_log_size); | |
1315 | } | |
1316 | ||
1317 | ret = iwl_mvm_send_cmd(mvm, &host_cmd); | |
1318 | kfree(mvm->error_recovery_buf); | |
1319 | mvm->error_recovery_buf = NULL; | |
1320 | ||
1321 | if (ret) { | |
1322 | IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret); | |
1323 | return; | |
1324 | } | |
1325 | ||
1326 | /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */ | |
1327 | if (flags & ERROR_RECOVERY_UPDATE_DB) { | |
1328 | resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data); | |
1329 | if (resp) | |
1330 | IWL_ERR(mvm, | |
1331 | "Failed to send recovery cmd blob was invalid %d\n", | |
1332 | resp); | |
1333 | } | |
1334 | } | |
1335 | ||
42ce76d6 LC |
1336 | static int iwl_mvm_sar_init(struct iwl_mvm *mvm) |
1337 | { | |
1edd56e6 | 1338 | return iwl_mvm_sar_select_profile(mvm, 1, 1); |
da2830ac LC |
1339 | } |
1340 | ||
1f370650 | 1341 | static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) |
8ca151b5 | 1342 | { |
1f370650 | 1343 | int ret; |
8ca151b5 | 1344 | |
7d6222e2 | 1345 | if (iwl_mvm_has_unified_ucode(mvm)) |
52b15521 | 1346 | return iwl_run_unified_mvm_ucode(mvm); |
8ca151b5 | 1347 | |
3b25f1af EG |
1348 | WARN_ON(!mvm->nvm_data); |
1349 | ret = iwl_run_init_mvm_ucode(mvm); | |
f2082a53 | 1350 | |
f2082a53 | 1351 | if (ret) { |
8d193ca2 | 1352 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); |
f4744258 LK |
1353 | |
1354 | if (iwlmvm_mod_params.init_dbg) | |
1355 | return 0; | |
1f370650 | 1356 | return ret; |
8d193ca2 | 1357 | } |
8ca151b5 | 1358 | |
203c83d3 | 1359 | iwl_fw_dbg_stop_sync(&mvm->fwrt); |
bab3cb92 EG |
1360 | iwl_trans_stop_device(mvm->trans); |
1361 | ret = iwl_trans_start_hw(mvm->trans); | |
f2082a53 | 1362 | if (ret) |
1f370650 | 1363 | return ret; |
8ca151b5 | 1364 | |
94022562 | 1365 | mvm->rfkill_safe_init_done = false; |
8ca151b5 | 1366 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); |
1f370650 SS |
1367 | if (ret) |
1368 | return ret; | |
1369 | ||
94022562 EG |
1370 | mvm->rfkill_safe_init_done = true; |
1371 | ||
b108d8c7 SM |
1372 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, |
1373 | NULL); | |
da2eb669 | 1374 | |
702e975d | 1375 | return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); |
1f370650 SS |
1376 | } |
1377 | ||
1378 | int iwl_mvm_up(struct iwl_mvm *mvm) | |
1379 | { | |
1380 | int ret, i; | |
1381 | struct ieee80211_channel *chan; | |
1382 | struct cfg80211_chan_def chandef; | |
dd36a507 | 1383 | struct ieee80211_supported_band *sband = NULL; |
1f370650 SS |
1384 | |
1385 | lockdep_assert_held(&mvm->mutex); | |
1386 | ||
1387 | ret = iwl_trans_start_hw(mvm->trans); | |
1388 | if (ret) | |
1389 | return ret; | |
1390 | ||
1391 | ret = iwl_mvm_load_rt_fw(mvm); | |
8ca151b5 JB |
1392 | if (ret) { |
1393 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
72d3c7bb JB |
1394 | if (ret != -ERFKILL) |
1395 | iwl_fw_dbg_error_collect(&mvm->fwrt, | |
1396 | FW_DBG_TRIGGER_DRIVER); | |
8ca151b5 JB |
1397 | goto error; |
1398 | } | |
1399 | ||
d0b813fc | 1400 | iwl_get_shared_mem_conf(&mvm->fwrt); |
04fd2c28 | 1401 | |
1f3b0ff8 LE |
1402 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
1403 | if (ret) | |
1404 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
1405 | ||
a1af4c48 | 1406 | if (!iwl_trans_dbg_ini_valid(mvm->trans)) { |
7a14c23d SS |
1407 | mvm->fwrt.dump.conf = FW_DBG_INVALID; |
1408 | /* if we have a destination, assume EARLY START */ | |
1409 | if (mvm->fw->dbg.dest_tlv) | |
1410 | mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; | |
1411 | iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); | |
1412 | } | |
6a951267 | 1413 | |
a0544272 | 1414 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1415 | if (ret) |
1416 | goto error; | |
1417 | ||
7d6222e2 JB |
1418 | if (!iwl_mvm_has_unified_ucode(mvm)) { |
1419 | /* Send phy db control command and then phy db calibration */ | |
1f370650 SS |
1420 | ret = iwl_send_phy_db_data(mvm->phy_db); |
1421 | if (ret) | |
1422 | goto error; | |
1f370650 | 1423 | } |
8ca151b5 | 1424 | |
bb99ff9b LC |
1425 | ret = iwl_send_phy_cfg_cmd(mvm); |
1426 | if (ret) | |
1427 | goto error; | |
1428 | ||
b3de3ef4 EG |
1429 | ret = iwl_mvm_send_bt_init_conf(mvm); |
1430 | if (ret) | |
1431 | goto error; | |
1432 | ||
cceb4507 SM |
1433 | if (fw_has_capa(&mvm->fw->ucode_capa, |
1434 | IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { | |
a8eb340f | 1435 | ret = iwl_set_soc_latency(&mvm->fwrt); |
cceb4507 SM |
1436 | if (ret) |
1437 | goto error; | |
1438 | } | |
1439 | ||
43413a97 | 1440 | /* Init RSS configuration */ |
9cd243f2 MG |
1441 | ret = iwl_configure_rxq(&mvm->fwrt); |
1442 | if (ret) | |
1443 | goto error; | |
8edbfaa1 SS |
1444 | |
1445 | if (iwl_mvm_has_new_rx_api(mvm)) { | |
43413a97 SS |
1446 | ret = iwl_send_rss_cfg_cmd(mvm); |
1447 | if (ret) { | |
1448 | IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", | |
1449 | ret); | |
1450 | goto error; | |
1451 | } | |
1452 | } | |
1453 | ||
8ca151b5 | 1454 | /* init the fw <-> mac80211 STA mapping */ |
be9ae34e | 1455 | for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) |
8ca151b5 JB |
1456 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); |
1457 | ||
0ae98812 | 1458 | mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; |
1d3c3f63 | 1459 | |
b2b7875b JB |
1460 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
1461 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
1462 | ||
79660869 IL |
1463 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) { |
1464 | ret = iwl_mvm_send_dqa_cmd(mvm); | |
1465 | if (ret) | |
1466 | goto error; | |
1467 | } | |
97d5be7e | 1468 | |
2c2c3647 NE |
1469 | /* |
1470 | * Add auxiliary station for scanning. | |
1471 | * Newer versions of this command implies that the fw uses | |
1472 | * internal aux station for all aux activities that don't | |
1473 | * requires a dedicated data queue. | |
1474 | */ | |
1475 | if (iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP, | |
1476 | ADD_STA, | |
1477 | 0) < 12) { | |
1478 | /* | |
1479 | * In old version the aux station uses mac id like other | |
1480 | * station and not lmac id | |
1481 | */ | |
1482 | ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX); | |
1483 | if (ret) | |
1484 | goto error; | |
1485 | } | |
8ca151b5 | 1486 | |
53a9d61e | 1487 | /* Add all the PHY contexts */ |
dd36a507 TM |
1488 | i = 0; |
1489 | while (!sband && i < NUM_NL80211_BANDS) | |
1490 | sband = mvm->hw->wiphy->bands[i++]; | |
1491 | ||
1492 | if (WARN_ON_ONCE(!sband)) | |
1493 | goto error; | |
1494 | ||
1495 | chan = &sband->channels[0]; | |
1496 | ||
53a9d61e IP |
1497 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); |
1498 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
1499 | /* | |
1500 | * The channel used here isn't relevant as it's | |
1501 | * going to be overwritten in the other flows. | |
1502 | * For now use the first channel we have. | |
1503 | */ | |
1504 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
1505 | &chandef, 1, 1); | |
1506 | if (ret) | |
1507 | goto error; | |
1508 | } | |
8ca151b5 | 1509 | |
c221daf2 CRI |
1510 | if (iwl_mvm_is_tt_in_fw(mvm)) { |
1511 | /* in order to give the responsibility of ct-kill and | |
1512 | * TX backoff to FW we need to send empty temperature reporting | |
1513 | * cmd during init time | |
1514 | */ | |
1515 | iwl_mvm_send_temp_report_ths_cmd(mvm); | |
1516 | } else { | |
1517 | /* Initialize tx backoffs to the minimal possible */ | |
1518 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
1519 | } | |
5c89e7bc | 1520 | |
242d9c8b | 1521 | #ifdef CONFIG_THERMAL |
5c89e7bc | 1522 | /* TODO: read the budget from BIOS / Platform NVM */ |
944eafc2 CRI |
1523 | |
1524 | /* | |
1525 | * In case there is no budget from BIOS / Platform NVM the default | |
1526 | * budget should be 2000mW (cooling state 0). | |
1527 | */ | |
1528 | if (iwl_mvm_is_ctdp_supported(mvm)) { | |
5c89e7bc CRI |
1529 | ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, |
1530 | mvm->cooling_dev.cur_state); | |
75cfe338 LC |
1531 | if (ret) |
1532 | goto error; | |
1533 | } | |
c221daf2 | 1534 | #endif |
0c0e2c71 | 1535 | |
aa43ae12 AM |
1536 | if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2)) |
1537 | WARN_ON(iwl_mvm_config_ltr(mvm)); | |
9180ac50 | 1538 | |
c1cb92fc | 1539 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
1540 | if (ret) |
1541 | goto error; | |
1542 | ||
f5b1cb2e | 1543 | iwl_mvm_lari_cfg(mvm); |
35af15d1 AN |
1544 | /* |
1545 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
1546 | * anyway, so don't init MCC. | |
1547 | */ | |
1548 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
1549 | ret = iwl_mvm_init_mcc(mvm); | |
1550 | if (ret) | |
1551 | goto error; | |
1552 | } | |
90d4f7db | 1553 | |
859d914c | 1554 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
4ca87a5f | 1555 | mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; |
b66b5817 | 1556 | mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; |
d2496221 DS |
1557 | ret = iwl_mvm_config_scan(mvm); |
1558 | if (ret) | |
1559 | goto error; | |
1560 | } | |
1561 | ||
f130bb75 MG |
1562 | if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) |
1563 | iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB); | |
1564 | ||
48e775e6 HD |
1565 | if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid)) |
1566 | IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n"); | |
1567 | ||
6ce1e5c0 GA |
1568 | ret = iwl_mvm_ppag_init(mvm); |
1569 | if (ret) | |
1570 | goto error; | |
1571 | ||
da2830ac | 1572 | ret = iwl_mvm_sar_init(mvm); |
78a19d52 | 1573 | if (ret == 0) |
5d041c46 | 1574 | ret = iwl_mvm_sar_geo_init(mvm); |
78a19d52 | 1575 | else if (ret < 0) |
a6bff3cb HD |
1576 | goto error; |
1577 | ||
28dd7ccd | 1578 | iwl_mvm_tas_init(mvm); |
7089ae63 JB |
1579 | iwl_mvm_leds_sync(mvm); |
1580 | ||
b68bd2e3 IP |
1581 | iwl_mvm_ftm_initiator_smooth_config(mvm); |
1582 | ||
4e8fe214 GG |
1583 | if (fw_has_capa(&mvm->fw->ucode_capa, |
1584 | IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) { | |
1585 | if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE) | |
1586 | iwl_rfi_send_config_cmd(mvm, NULL); | |
1587 | } | |
1588 | ||
53a9d61e | 1589 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
1590 | return 0; |
1591 | error: | |
f4744258 | 1592 | if (!iwlmvm_mod_params.init_dbg || !ret) |
de8ba41b | 1593 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1594 | return ret; |
1595 | } | |
1596 | ||
1597 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
1598 | { | |
1599 | int ret, i; | |
1600 | ||
1601 | lockdep_assert_held(&mvm->mutex); | |
1602 | ||
1603 | ret = iwl_trans_start_hw(mvm->trans); | |
1604 | if (ret) | |
1605 | return ret; | |
1606 | ||
1607 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
1608 | if (ret) { | |
1609 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
1610 | goto error; | |
1611 | } | |
1612 | ||
a0544272 | 1613 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1614 | if (ret) |
1615 | goto error; | |
1616 | ||
1617 | /* Send phy db control command and then phy db calibration*/ | |
1618 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1619 | if (ret) | |
1620 | goto error; | |
1621 | ||
1622 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1623 | if (ret) | |
1624 | goto error; | |
1625 | ||
1626 | /* init the fw <-> mac80211 STA mapping */ | |
be9ae34e | 1627 | for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) |
8ca151b5 JB |
1628 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); |
1629 | ||
2c2c3647 NE |
1630 | if (iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP, |
1631 | ADD_STA, | |
1632 | 0) < 12) { | |
1633 | /* | |
1634 | * Add auxiliary station for scanning. | |
1635 | * Newer versions of this command implies that the fw uses | |
1636 | * internal aux station for all aux activities that don't | |
1637 | * requires a dedicated data queue. | |
1638 | * In old version the aux station uses mac id like other | |
1639 | * station and not lmac id | |
1640 | */ | |
1641 | ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX); | |
1642 | if (ret) | |
1643 | goto error; | |
1644 | } | |
8ca151b5 JB |
1645 | |
1646 | return 0; | |
1647 | error: | |
fcb6b92a | 1648 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1649 | return ret; |
1650 | } | |
1651 | ||
0416841d JB |
1652 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1653 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1654 | { |
1655 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1656 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1657 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1658 | ||
1659 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1660 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1661 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1662 | (flags & CT_KILL_CARD_DISABLED) ? | |
1663 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1664 | } |
1665 | ||
0416841d JB |
1666 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1667 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1668 | { |
1669 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1670 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1671 | ||
0c8d0a47 GBA |
1672 | IWL_DEBUG_INFO(mvm, |
1673 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1674 | le32_to_cpu(mfuart_notif->installed_ver), | |
1675 | le32_to_cpu(mfuart_notif->external_ver), | |
1676 | le32_to_cpu(mfuart_notif->status), | |
1677 | le32_to_cpu(mfuart_notif->duration)); | |
1678 | ||
19f63c53 GBA |
1679 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) |
1680 | IWL_DEBUG_INFO(mvm, | |
0c8d0a47 | 1681 | "MFUART: image size: 0x%08x\n", |
19f63c53 | 1682 | le32_to_cpu(mfuart_notif->image_size)); |
30269c12 | 1683 | } |