projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
wifi: iwlwifi: remove disable_dummy_notification
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
1724fc78 3 * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
8e99ea8d
JB		 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
a2ac0f48 9#include <linux/dmi.h>
8ca151b5
JB		 10
11#include "iwl-trans.h"
12#include "iwl-op-mode.h"
d962f9b1 13#include "fw/img.h"
8ca151b5 14#include "iwl-debug.h"
8c23f95c 15#include "iwl-prph.h"
813df5ce 16#include "fw/acpi.h"
b3e4c0f3 17#include "fw/pnvm.h"
8ca151b5
JB		 18
19#include "mvm.h"
7174beb6 20#include "fw/dbg.h"
8ca151b5 21#include "iwl-phy-db.h"
9c4f7d51
ST		 22#include "iwl-modparams.h"
23#include "iwl-nvm-parse.h"
cf85123a 24#include "time-sync.h"
8ca151b5 25
b3e4c0f3
LC		 26#define MVM_UCODE_ALIVE_TIMEOUT (HZ)
27#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5 28
c3f40c3e
MK		 29#define IWL_TAS_US_MCC 0x5553
30#define IWL_TAS_CANADA_MCC 0x4341
31
8ca151b5
JB		 32struct iwl_mvm_alive_data {
33 bool valid;
34 u32 scd_base_addr;
35};
36
8ca151b5
JB		 37static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
38{
39 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
40 .valid = cpu_to_le32(valid_tx_ant),
41 };
42
33223542 43 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 44 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB		 45 sizeof(tx_ant_cmd), &tx_ant_cmd);
46}
47
43413a97
SS		 48static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
49{
50 int i;
51 struct iwl_rss_config_cmd cmd = {
52 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS		 53 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
54 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
55 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
56 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
58 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS		 59 };
60
f43495fd
SS		 61 if (mvm->trans->num_rx_queues == 1)
62 return 0;
63
854d773e 64 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 65 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS		 66 cmd.indirection_table[i] =
67 1 + (i % (mvm->trans->num_rx_queues - 1));
68 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS		 69
70 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
71}
72
97d5be7e
LK		 73static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
74{
75 struct iwl_dqa_enable_cmd dqa_cmd = {
76 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
77 };
f0c86427 78 u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD);
97d5be7e
LK		 79 int ret;
80
81 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
82 if (ret)
83 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
84 else
85 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
86
87 return ret;
88}
89
bdccdb85
GBA		 90void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
91 struct iwl_rx_cmd_buffer *rxb)
92{
93 struct iwl_rx_packet *pkt = rxb_addr(rxb);
94 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
95 __le32 *dump_data = mfu_dump_notif->data;
96 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
97 int i;
98
99 if (mfu_dump_notif->index_num == 0)
100 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
101 le32_to_cpu(mfu_dump_notif->assert_id));
102
103 for (i = 0; i < n_words; i++)
104 IWL_DEBUG_INFO(mvm,
105 "MFUART assert dump, dword %u: 0x%08x\n",
106 le16_to_cpu(mfu_dump_notif->index_num) *
107 n_words + i,
108 le32_to_cpu(dump_data[i]));
109}
110
8ca151b5
JB		 111static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
112 struct iwl_rx_packet *pkt, void *data)
113{
fd1c3318 114 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB		 115 struct iwl_mvm *mvm =
116 container_of(notif_wait, struct iwl_mvm, notif_wait);
117 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS		 118 struct iwl_umac_alive *umac;
119 struct iwl_lmac_alive *lmac1;
120 struct iwl_lmac_alive *lmac2 = NULL;
121 u16 status;
cfa5d0ca 122 u32 lmac_error_event_table, umac_error_table;
708d8c53
JB		 123 u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
124 UCODE_ALIVE_NTFY, 0);
5053a451 125 u32 i;
b2f20cf2 126
01a9ca51 127
c0941ace
MS		 128 if (version == 6) {
129 struct iwl_alive_ntf_v6 *palive;
130
131 if (pkt_len < sizeof(*palive))
132 return false;
133
134 palive = (void *)pkt->data;
135 mvm->trans->dbg.imr_data.imr_enable =
136 le32_to_cpu(palive->imr.enabled);
137 mvm->trans->dbg.imr_data.imr_size =
138 le32_to_cpu(palive->imr.size);
139 mvm->trans->dbg.imr_data.imr2sram_remainbyte =
140 mvm->trans->dbg.imr_data.imr_size;
141 mvm->trans->dbg.imr_data.imr_base_addr =
142 palive->imr.base_addr;
143 mvm->trans->dbg.imr_data.imr_curr_addr =
144 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr);
145 IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n",
146 mvm->trans->dbg.imr_data.imr_enable,
147 mvm->trans->dbg.imr_data.imr_size,
148 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr));
5053a451
MS		 149
150 if (!mvm->trans->dbg.imr_data.imr_enable) {
151 for (i = 0; i < ARRAY_SIZE(mvm->trans->dbg.active_regions); i++) {
152 struct iwl_ucode_tlv *reg_tlv;
153 struct iwl_fw_ini_region_tlv *reg;
154
155 reg_tlv = mvm->trans->dbg.active_regions[i];
156 if (!reg_tlv)
157 continue;
158
159 reg = (void *)reg_tlv->data;
160 /*
161 * We have only one DRAM IMR region, so we
162 * can break as soon as we find the first
163 * one.
164 */
165 if (reg->type == IWL_FW_INI_REGION_DRAM_IMR) {
166 mvm->trans->dbg.unsupported_region_msk |= BIT(i);
167 break;
168 }
169 }
170 }
c0941ace
MS		 171 }
172
173 if (version >= 5) {
90824f2f
LC		 174 struct iwl_alive_ntf_v5 *palive;
175
fd1c3318
JB		 176 if (pkt_len < sizeof(*palive))
177 return false;
178
90824f2f
LC		 179 palive = (void *)pkt->data;
180 umac = &palive->umac_data;
181 lmac1 = &palive->lmac_data[0];
182 lmac2 = &palive->lmac_data[1];
183 status = le16_to_cpu(palive->status);
184
185 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
186 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
187 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
188
189 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
190 mvm->trans->sku_id[0],
191 mvm->trans->sku_id[1],
192 mvm->trans->sku_id[2]);
193 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC		 194 struct iwl_alive_ntf_v4 *palive;
195
fd1c3318
JB		 196 if (pkt_len < sizeof(*palive))
197 return false;
198
5c228d63
SS		 199 palive = (void *)pkt->data;
200 umac = &palive->umac_data;
201 lmac1 = &palive->lmac_data[0];
202 lmac2 = &palive->lmac_data[1];
203 status = le16_to_cpu(palive->status);
9422b978
LC		 204 } else if (iwl_rx_packet_payload_len(pkt) ==
205 sizeof(struct iwl_alive_ntf_v3)) {
206 struct iwl_alive_ntf_v3 *palive3;
207
fd1c3318
JB		 208 if (pkt_len < sizeof(*palive3))
209 return false;
210
5c228d63
SS		 211 palive3 = (void *)pkt->data;
212 umac = &palive3->umac_data;
213 lmac1 = &palive3->lmac_data;
214 status = le16_to_cpu(palive3->status);
9422b978
LC		 215 } else {
216 WARN(1, "unsupported alive notification (size %d)\n",
217 iwl_rx_packet_payload_len(pkt));
218 /* get timeout later */
219 return false;
5c228d63 220 }
01a9ca51 221
22463857
SM		 222 lmac_error_event_table =
223 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
224 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
225
5c228d63 226 if (lmac2)
91c28b83 227 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 228 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 229
4f7411d6
RG		 230 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
231 ~FW_ADDR_CACHE_CONTROL;
cfa5d0ca
MG		 232
233 if (umac_error_table) {
234 if (umac_error_table >=
834f920e 235 mvm->trans->cfg->min_umac_error_event_table) {
cfa5d0ca
MG		 236 iwl_fw_umac_set_alive_err_table(mvm->trans,
237 umac_error_table);
238 } else {
239 IWL_ERR(mvm,
240 "Not valid error log pointer 0x%08X for %s uCode\n",
241 umac_error_table,
242 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
243 "Init" : "RT");
244 }
3485e76e 245 }
fb5b2846 246
22463857 247 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 248 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 249
5c228d63
SS		 250 IWL_DEBUG_FW(mvm,
251 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
252 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 253
5c228d63
SS		 254 if (lmac2)
255 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 256
5c228d63
SS		 257 IWL_DEBUG_FW(mvm,
258 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
259 le32_to_cpu(umac->umac_major),
260 le32_to_cpu(umac->umac_minor));
8ca151b5 261
0a3a3e9e
SM		 262 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
263
8ca151b5
JB		 264 return true;
265}
266
1f370650
SS		 267static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
268 struct iwl_rx_packet *pkt, void *data)
269{
270 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
271
272 return true;
273}
274
8ca151b5
JB		 275static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
276 struct iwl_rx_packet *pkt, void *data)
277{
278 struct iwl_phy_db *phy_db = data;
279
280 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
281 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
282 return true;
283 }
284
ce1f2778 285 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB		 286
287 return false;
288}
289
a7de31d5
MG		 290static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
291{
184f10db
MG		 292#define IWL_FW_PRINT_REG_INFO(reg_name) \
293 IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
294
a7de31d5
MG		 295 struct iwl_trans *trans = mvm->trans;
296 enum iwl_device_family device_family = trans->trans_cfg->device_family;
297
298 if (device_family < IWL_DEVICE_FAMILY_8000)
299 return;
300
301 if (device_family <= IWL_DEVICE_FAMILY_9000)
184f10db 302 IWL_FW_PRINT_REG_INFO(WFPM_ARC1_PD_NOTIFICATION);
a7de31d5 303 else
184f10db 304 IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);
f2f17ca0 305
184f10db 306 IWL_FW_PRINT_REG_INFO(HPM_SECONDARY_DEVICE_STATE);
f2f17ca0 307
184f10db
MG		 308 /* print OPT info */
309 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_ADDR);
310 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_DATA);
a7de31d5
MG		 311}
312
8ca151b5
JB		 313static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
314 enum iwl_ucode_type ucode_type)
315{
316 struct iwl_notification_wait alive_wait;
94a8d87c 317 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 318 const struct fw_img *fw;
cfbc6c4c 319 int ret;
702e975d 320 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 321 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG		 322 bool run_in_rfkill =
323 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
5e31b3df
MS		 324 u8 count;
325 struct iwl_pc_data *pc_data;
8ca151b5 326
61df750c 327 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA		 328 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
329 !(fw_has_capa(&mvm->fw->ucode_capa,
330 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 331 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 332 else
612da1ef 333 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 334 if (WARN_ON(!fw))
8ca151b5 335 return -EINVAL;
702e975d 336 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 337 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB		 338
339 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
340 alive_cmd, ARRAY_SIZE(alive_cmd),
341 iwl_alive_fn, &alive_data);
342
b3500b47
EG		 343 /*
344 * We want to load the INIT firmware even in RFKILL
345 * For the unified firmware case, the ucode_type is not
346 * INIT, but we still need to run it.
347 */
348 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 349 if (ret) {
702e975d 350 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 351 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
352 return ret;
353 }
354
355 /*
356 * Some things may run in the background now, but we
357 * just wait for the ALIVE notification here.
358 */
359 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
360 MVM_UCODE_ALIVE_TIMEOUT);
56731878
DG		 361
362 if (mvm->trans->trans_cfg->device_family ==
363 IWL_DEVICE_FAMILY_AX210) {
364 /* print these registers regardless of alive fail/success */
365 IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n",
366 iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
367 IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n",
368 iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
369 IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n",
370 iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
b8133439
AS		 371 IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n",
372 iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
56731878
DG		 373 }
374
8ca151b5 375 if (ret) {
d6be9c1d
SS		 376 struct iwl_trans *trans = mvm->trans;
377
5667ccc2 378 /* SecBoot info */
20f5aef5
JB		 379 if (trans->trans_cfg->device_family >=
380 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS		 381 IWL_ERR(mvm,
382 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST		 383 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
384 iwl_read_umac_prph(trans,
385 UMAG_SB_CPU_2_STATUS));
5667ccc2
MG		 386 } else if (trans->trans_cfg->device_family >=
387 IWL_DEVICE_FAMILY_8000) {
388 IWL_ERR(mvm,
389 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
390 iwl_read_prph(trans, SB_CPU_1_STATUS),
391 iwl_read_prph(trans, SB_CPU_2_STATUS));
392 }
393
a7de31d5
MG		 394 iwl_mvm_print_pd_notification(mvm);
395
5667ccc2
MG		 396 /* LMAC/UMAC PC info */
397 if (trans->trans_cfg->device_family >=
5e31b3df
MS		 398 IWL_DEVICE_FAMILY_22000) {
399 pc_data = trans->dbg.pc_data;
400 for (count = 0; count < trans->dbg.num_pc;
401 count++, pc_data++)
402 IWL_ERR(mvm, "%s: 0x%x\n",
403 pc_data->pc_name,
404 pc_data->pc_address);
405 } else if (trans->trans_cfg->device_family >=
5667ccc2 406 IWL_DEVICE_FAMILY_9000) {
20f5aef5
JB		 407 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
408 iwl_read_umac_prph(trans,
409 UREG_UMAC_CURRENT_PC));
410 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
411 iwl_read_umac_prph(trans,
412 UREG_LMAC1_CURRENT_PC));
413 if (iwl_mvm_is_cdb_supported(mvm))
414 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
415 iwl_read_umac_prph(trans,
416 UREG_LMAC2_CURRENT_PC));
20f5aef5
JB		 417 }
418
b8133439 419 if (ret == -ETIMEDOUT && !mvm->pldr_sync)
20f5aef5
JB		 420 iwl_fw_dbg_error_collect(&mvm->fwrt,
421 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
422
702e975d 423 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 424 return ret;
425 }
426
427 if (!alive_data.valid) {
428 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 429 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 430 return -EIO;
431 }
432
f31f7cd9
GG		 433 /* if reached this point, Alive notification was received */
434 iwl_mei_alive_notif(true);
733eb54f 435
33182810
AG		 436 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait,
437 &mvm->fw->ucode_capa);
70d3ca86
LC		 438 if (ret) {
439 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
440 iwl_fw_set_current_image(&mvm->fwrt, old_type);
441 return ret;
442 }
443
8ca151b5
JB		 444 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
445
446 /*
447 * Note: all the queues are enabled as part of the interface
448 * initialization, but in firmware restart scenarios they
449 * could be stopped, so wake them up. In firmware restart,
450 * mac80211 will have the queues stopped as well until the
451 * reconfiguration completes. During normal startup, they
452 * will be empty.
453 */
454
4ecafae9 455 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB		 456 /*
457 * Set a 'fake' TID for the command queue, since we use the
458 * hweight() of the tid_bitmap as a refcount now. Not that
459 * we ever even consider the command queue as one we might
460 * want to reuse, but be safe nevertheless.
461 */
462 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
463 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 464
65b280fe 465 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC		 466#ifdef CONFIG_IWLWIFI_DEBUGFS
467 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
468#endif
8ca151b5 469
d3d9b4fc
EG		 470 /*
471 * All the BSSes in the BSS table include the GP2 in the system
472 * at the beacon Rx time, this is of course no longer relevant
473 * since we are resetting the firmware.
474 * Purge all the BSS table.
475 */
476 cfg80211_bss_flush(mvm->hw->wiphy);
477
8ca151b5
JB		 478 return 0;
479}
8ca151b5 480
c4ace426
GA		 481static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
482 struct iwl_phy_specific_cfg *phy_filters)
483{
c4c95454
JB		 484#ifdef CONFIG_ACPI
485 *phy_filters = mvm->phy_filters;
c4ace426 486#endif /* CONFIG_ACPI */
c4c95454 487}
c4ace426 488
c593d2fa
AB		 489#if defined(CONFIG_ACPI) && defined(CONFIG_EFI)
490static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
491{
492 u8 cmd_ver;
493 int ret;
494 struct iwl_host_cmd cmd = {
495 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
496 SAR_OFFSET_MAPPING_TABLE_CMD),
497 .flags = 0,
498 .data[0] = &mvm->fwrt.sgom_table,
499 .len[0] = sizeof(mvm->fwrt.sgom_table),
500 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
501 };
502
503 if (!mvm->fwrt.sgom_enabled) {
504 IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n");
505 return 0;
506 }
507
971cbe50 508 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
c593d2fa
AB		 509 IWL_FW_CMD_VER_UNKNOWN);
510
511 if (cmd_ver != 2) {
512 IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n",
513 cmd_ver);
514 return 0;
515 }
516
517 ret = iwl_mvm_send_cmd(mvm, &cmd);
518 if (ret < 0)
519 IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret);
520
521 return ret;
522}
523#else
524
525static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
526{
527 return 0;
528}
529#endif
530
8ca151b5
JB		 531static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
532{
971cbe50 533 u32 cmd_id = PHY_CONFIGURATION_CMD;
c4ace426 534 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 535 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA		 536 u8 cmd_ver;
537 size_t cmd_size;
8ca151b5 538
bb99ff9b 539 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 540 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 541 return 0;
d923b020
LC		 542
543 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC		 544 /*
545 * TODO: currently we don't set the antenna but letting the NIC
546 * to decide which antenna to use. This should come from BIOS.
547 */
548 phy_cfg_cmd.phy_cfg =
549 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
550 }
551
8ca151b5 552 /* Set parameters */
a0544272 553 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC		 554
555 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC		 556 phy_cfg_cmd.phy_cfg |=
557 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 558
8ca151b5
JB		 559 phy_cfg_cmd.calib_control.event_trigger =
560 mvm->fw->default_calib[ucode_type].event_trigger;
561 phy_cfg_cmd.calib_control.flow_trigger =
562 mvm->fw->default_calib[ucode_type].flow_trigger;
563
971cbe50 564 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 565 IWL_FW_CMD_VER_UNKNOWN);
c4c95454
JB		 566 if (cmd_ver >= 3)
567 iwl_mvm_phy_filter_init(mvm, &phy_cfg_cmd.phy_specific_cfg);
c4ace426 568
8ca151b5
JB		 569 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
570 phy_cfg_cmd.phy_cfg);
c4ace426
GA		 571 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
572 sizeof(struct iwl_phy_cfg_cmd_v1);
971cbe50 573 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd);
8ca151b5
JB		 574}
575
e305a408
MS		 576static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
577{
578 struct iwl_notification_wait init_wait;
579 struct iwl_nvm_access_complete_cmd nvm_complete = {};
580 struct iwl_init_extended_cfg_cmd init_cfg = {
581 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
582 };
583 static const u16 init_complete[] = {
584 INIT_COMPLETE_NOTIF,
585 };
586 int ret;
587
588 if (mvm->trans->cfg->tx_with_siso_diversity)
589 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
590
591 lockdep_assert_held(&mvm->mutex);
592
593 mvm->rfkill_safe_init_done = false;
594
595 iwl_init_notification_wait(&mvm->notif_wait,
596 &init_wait,
597 init_complete,
598 ARRAY_SIZE(init_complete),
599 iwl_wait_init_complete,
600 NULL);
601
602 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
603
604 /* Will also start the device */
605 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
606 if (ret) {
607 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
608 goto error;
609 }
610 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
611 NULL);
612
613 /* Send init config command to mark that we are sending NVM access
614 * commands
615 */
616 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
617 INIT_EXTENDED_CFG_CMD),
618 CMD_SEND_IN_RFKILL,
619 sizeof(init_cfg), &init_cfg);
620 if (ret) {
621 IWL_ERR(mvm, "Failed to run init config command: %d\n",
622 ret);
623 goto error;
624 }
625
626 /* Load NVM to NIC if needed */
627 if (mvm->nvm_file_name) {
628 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
629 mvm->nvm_sections);
630 if (ret)
631 goto error;
632 ret = iwl_mvm_load_nvm_to_nic(mvm);
633 if (ret)
634 goto error;
635 }
636
637 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
638 ret = iwl_nvm_init(mvm);
639 if (ret) {
640 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
641 goto error;
642 }
643 }
644
645 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
646 NVM_ACCESS_COMPLETE),
647 CMD_SEND_IN_RFKILL,
648 sizeof(nvm_complete), &nvm_complete);
649 if (ret) {
650 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
651 ret);
652 goto error;
653 }
654
d2ccc5c1
MS		 655 ret = iwl_send_phy_cfg_cmd(mvm);
656 if (ret) {
657 IWL_ERR(mvm, "Failed to run PHY configuration: %d\n",
658 ret);
659 goto error;
660 }
661
e305a408
MS		 662 /* We wait for the INIT complete notification */
663 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
664 MVM_UCODE_ALIVE_TIMEOUT);
665 if (ret)
666 return ret;
667
668 /* Read the NVM only at driver load time, no need to do this twice */
669 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
670 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
671 if (IS_ERR(mvm->nvm_data)) {
672 ret = PTR_ERR(mvm->nvm_data);
673 mvm->nvm_data = NULL;
674 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
675 return ret;
676 }
677 }
678
679 mvm->rfkill_safe_init_done = true;
680
681 return 0;
682
683error:
684 iwl_remove_notification(&mvm->notif_wait, &init_wait);
685 return ret;
686}
687
3b25f1af 688int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB		 689{
690 struct iwl_notification_wait calib_wait;
6eb031d2 691 static const u16 init_complete[] = {
8ca151b5
JB		 692 INIT_COMPLETE_NOTIF,
693 CALIB_RES_NOTIF_PHY_DB
694 };
695 int ret;
696
7d6222e2 697 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 698 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 699
8ca151b5
JB		 700 lockdep_assert_held(&mvm->mutex);
701
94022562 702 mvm->rfkill_safe_init_done = false;
8ca151b5
JB		 703
704 iwl_init_notification_wait(&mvm->notif_wait,
705 &calib_wait,
706 init_complete,
707 ARRAY_SIZE(init_complete),
708 iwl_wait_phy_db_entry,
709 mvm->phy_db);
710
11f8c533
LC		 711 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
712
8ca151b5
JB		 713 /* Will also start the device */
714 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
715 if (ret) {
716 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 717 goto remove_notif;
8ca151b5
JB		 718 }
719
7d34a7d7 720 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG		 721 ret = iwl_mvm_send_bt_init_conf(mvm);
722 if (ret)
00e0c6c8 723 goto remove_notif;
b3de3ef4 724 }
931d4160 725
81a67e32 726 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 727 if (!mvm->nvm_data) {
5bd1d2c1 728 ret = iwl_nvm_init(mvm);
8ca151b5
JB		 729 if (ret) {
730 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 731 goto remove_notif;
8ca151b5
JB		 732 }
733 }
734
81a67e32 735 /* In case we read the NVM from external file, load it to the NIC */
9ce505fe
AN		 736 if (mvm->nvm_file_name) {
737 ret = iwl_mvm_load_nvm_to_nic(mvm);
738 if (ret)
739 goto remove_notif;
740 }
81a67e32 741
64866e5d
LC		 742 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
743 "Too old NVM version (0x%0x, required = 0x%0x)",
744 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 745
4f59334b
EH		 746 /*
747 * abort after reading the nvm in case RF Kill is on, we will complete
748 * the init seq later when RF kill will switch to off
749 */
1a3fe0b2 750 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH		 751 IWL_DEBUG_RF_KILL(mvm,
752 "jump over all phy activities due to RF kill\n");
00e0c6c8 753 goto remove_notif;
4f59334b
EH		 754 }
755
b3500b47 756 mvm->rfkill_safe_init_done = true;
31b8b343 757
e07cbb53 758 /* Send TX valid antennas before triggering calibrations */
a0544272 759 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 760 if (ret)
00e0c6c8 761 goto remove_notif;
e07cbb53 762
8ca151b5
JB		 763 ret = iwl_send_phy_cfg_cmd(mvm);
764 if (ret) {
765 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
766 ret);
00e0c6c8 767 goto remove_notif;
8ca151b5
JB		 768 }
769
770 /*
771 * Some things may run in the background now, but we
772 * just wait for the calibration complete notification.
773 */
774 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC		 775 MVM_UCODE_CALIB_TIMEOUT);
776 if (!ret)
777 goto out;
31b8b343 778
00e0c6c8 779 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 780 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC		 781 ret = 0;
782 } else {
783 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
784 ret);
31b8b343 785 }
00e0c6c8 786
8ca151b5
JB		 787 goto out;
788
00e0c6c8 789remove_notif:
8ca151b5
JB		 790 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
791out:
b3500b47 792 mvm->rfkill_safe_init_done = false;
a4082843 793 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB		 794 /* we want to debug INIT and we have no NVM - fake */
795 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
796 sizeof(struct ieee80211_channel) +
797 sizeof(struct ieee80211_rate),
798 GFP_KERNEL);
799 if (!mvm->nvm_data)
800 return -ENOMEM;
8ca151b5
JB		 801 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
802 mvm->nvm_data->bands[0].n_channels = 1;
803 mvm->nvm_data->bands[0].n_bitrates = 1;
804 mvm->nvm_data->bands[0].bitrates =
3827cb59 805 (void *)((u8 *)mvm->nvm_data->channels + 1);
8ca151b5
JB		 806 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
807 }
808
809 return ret;
810}
811
84bfffa9
EG		 812static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
813{
814 struct iwl_ltr_config_cmd cmd = {
815 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
816 };
817
818 if (!mvm->trans->ltr_enabled)
819 return 0;
820
84bfffa9
EG		 821 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
822 sizeof(cmd), &cmd);
823}
824
c386dacb 825#ifdef CONFIG_ACPI
42ce76d6 826int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 827{
971cbe50 828 u32 cmd_id = REDUCE_TX_POWER_CMD;
216cdfb5
LC		 829 struct iwl_dev_tx_power_cmd cmd = {
830 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 831 };
9c08cef8 832 __le16 *per_chain;
1edd56e6 833 int ret;
39c1a972 834 u16 len = 0;
fbb7957d 835 u32 n_subbands;
971cbe50 836 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 837 IWL_FW_CMD_VER_UNKNOWN);
b0aa02b3
AB		 838 if (cmd_ver == 7) {
839 len = sizeof(cmd.v7);
840 n_subbands = IWL_NUM_SUB_BANDS_V2;
841 per_chain = cmd.v7.per_chain[0][0];
842 cmd.v7.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags);
843 } else if (cmd_ver == 6) {
fbb7957d
LC		 844 len = sizeof(cmd.v6);
845 n_subbands = IWL_NUM_SUB_BANDS_V2;
846 per_chain = cmd.v6.per_chain[0][0];
847 } else if (fw_has_api(&mvm->fw->ucode_capa,
848 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 849 len = sizeof(cmd.v5);
e12cfc7b 850 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 851 per_chain = cmd.v5.per_chain[0][0];
852 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 853 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 854 len = sizeof(cmd.v4);
e12cfc7b 855 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 856 per_chain = cmd.v4.per_chain[0][0];
857 } else {
216cdfb5 858 len = sizeof(cmd.v3);
e12cfc7b 859 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 860 per_chain = cmd.v3.per_chain[0][0];
861 }
55bfa4b9 862
216cdfb5
LC		 863 /* all structs have the same common part, add it */
864 len += sizeof(cmd.common);
da2830ac 865
dac7171c
LC		 866 ret = iwl_sar_select_profile(&mvm->fwrt, per_chain,
867 IWL_NUM_CHAIN_TABLES,
fbb7957d 868 n_subbands, prof_a, prof_b);
1edd56e6
LC		 869
870 /* return on error or if the profile is disabled (positive number) */
871 if (ret)
872 return ret;
873
6d19a5eb
EG		 874 iwl_mei_set_power_limit(per_chain);
875
42ce76d6 876 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
971cbe50 877 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
42ce76d6
LC		 878}
879
7fe90e0e
HD		 880int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
881{
dd2a1256 882 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 883 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 884 u16 len;
39c1a972 885 int ret;
c8611331
JB		 886 struct iwl_host_cmd cmd = {
887 .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD),
888 .flags = CMD_WANT_SKB,
889 .data = { &geo_tx_cmd },
890 };
971cbe50 891 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
e80bfd11 892 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 893
dd2a1256
LC		 894 /* the ops field is at the same spot for all versions, so set in v1 */
895 geo_tx_cmd.v1.ops =
896 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
897
97f8a3d1
AB		 898 if (cmd_ver == 5)
899 len = sizeof(geo_tx_cmd.v5);
900 else if (cmd_ver == 4)
901 len = sizeof(geo_tx_cmd.v4);
902 else if (cmd_ver == 3)
0ea788ed
LC		 903 len = sizeof(geo_tx_cmd.v3);
904 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
905 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC		 906 len = sizeof(geo_tx_cmd.v2);
907 else
908 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 909
39c1a972
IZ		 910 if (!iwl_sar_geo_support(&mvm->fwrt))
911 return -EOPNOTSUPP;
912
c8611331 913 cmd.len[0] = len;
7fe90e0e
HD		 914
915 ret = iwl_mvm_send_cmd(mvm, &cmd);
916 if (ret) {
917 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
918 return ret;
919 }
f604324e
LC		 920
921 resp = (void *)cmd.resp_pkt->data;
922 ret = le32_to_cpu(resp->profile_idx);
923
97f8a3d1 924 if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES_REV3))
f604324e
LC		 925 ret = -EIO;
926
7fe90e0e
HD		 927 iwl_free_resp(&cmd);
928 return ret;
929}
930
a6bff3cb
HD		 931static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
932{
971cbe50 933 u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD);
dd2a1256 934 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 935 u16 len;
45acebf8 936 u32 n_bands;
97f8a3d1 937 u32 n_profiles;
ac9952f6 938 u32 sk = 0;
0433ae55 939 int ret;
971cbe50 940 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 941 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 942
45acebf8
NG		 943 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
944 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
945 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
97f8a3d1
AB		 946 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) ||
947 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) !=
948 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) ||
949 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) !=
950 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops));
951
dd2a1256
LC		 952 /* the ops field is at the same spot for all versions, so set in v1 */
953 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 954
97f8a3d1
AB		 955 if (cmd_ver == 5) {
956 len = sizeof(cmd.v5);
957 n_bands = ARRAY_SIZE(cmd.v5.table[0]);
958 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
959 } else if (cmd_ver == 4) {
960 len = sizeof(cmd.v4);
961 n_bands = ARRAY_SIZE(cmd.v4.table[0]);
962 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
963 } else if (cmd_ver == 3) {
0ea788ed 964 len = sizeof(cmd.v3);
45acebf8 965 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
97f8a3d1 966 n_profiles = ACPI_NUM_GEO_PROFILES;
0ea788ed
LC		 967 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
968 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 969 len = sizeof(cmd.v2);
45acebf8 970 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
97f8a3d1 971 n_profiles = ACPI_NUM_GEO_PROFILES;
39c1a972 972 } else {
dd2a1256 973 len = sizeof(cmd.v1);
45acebf8 974 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
97f8a3d1 975 n_profiles = ACPI_NUM_GEO_PROFILES;
0c3d7282
HD		 976 }
977
45acebf8
NG		 978 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
979 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
980 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
97f8a3d1
AB		 981 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) ||
982 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) !=
983 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) ||
984 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) !=
985 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table));
45acebf8 986 /* the table is at the same position for all versions, so set use v1 */
97f8a3d1
AB		 987 ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0],
988 n_bands, n_profiles);
45acebf8
NG		 989
990 /*
991 * It is a valid scenario to not support SAR, or miss wgds table,
992 * but in that case there is no need to send the command.
993 */
994 if (ret)
995 return 0;
996
ac9952f6
LC		 997 /* Only set to South Korea if the table revision is 1 */
998 if (mvm->fwrt.geo_rev == 1)
999 sk = 1;
1000
28db1862 1001 /*
ac9952f6
LC		 1002 * Set the table_revision to South Korea (1) or not (0). The
1003 * element name is misleading, as it doesn't contain the table
1004 * revision number, but whether the South Korea variation
1005 * should be used.
28db1862
LC		 1006 * This must be done after calling iwl_sar_geo_init().
1007 */
97f8a3d1 1008 if (cmd_ver == 5)
ac9952f6 1009 cmd.v5.table_revision = cpu_to_le32(sk);
97f8a3d1 1010 else if (cmd_ver == 4)
ac9952f6 1011 cmd.v4.table_revision = cpu_to_le32(sk);
97f8a3d1 1012 else if (cmd_ver == 3)
ac9952f6 1013 cmd.v3.table_revision = cpu_to_le32(sk);
28db1862
LC		 1014 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
1015 IWL_UCODE_TLV_API_SAR_TABLE_VER))
ac9952f6 1016 cmd.v2.table_revision = cpu_to_le32(sk);
28db1862 1017
971cbe50 1018 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
6ce1e5c0
GA		 1019}
1020
1021int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1022{
8bdc52b9 1023 union iwl_ppag_table_cmd cmd;
e8e10a37 1024 int ret, cmd_size;
160bab43 1025
e8e10a37 1026 ret = iwl_read_ppag_table(&mvm->fwrt, &cmd, &cmd_size);
b20bdd9c 1027 /* Not supporting PPAG table is a valid scenario */
473bc264 1028 if (ret < 0)
b20bdd9c 1029 return 0;
6ce1e5c0 1030
f2134f66 1031 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA		 1032 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1033 PER_PLATFORM_ANT_GAIN_CMD),
8bdc52b9 1034 0, cmd_size, &cmd);
6ce1e5c0
GA		 1035 if (ret < 0)
1036 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1037 ret);
1038
1039 return ret;
1040}
1041
1042static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1043{
78a19d52 1044 /* no need to read the table, done in INIT stage */
e8e10a37 1045 if (!(iwl_acpi_is_ppag_approved(&mvm->fwrt)))
a2ac0f48 1046 return 0;
a2ac0f48 1047
6ce1e5c0
GA		 1048 return iwl_mvm_ppag_send_cmd(mvm);
1049}
1050
2856f623
AB		 1051static const struct dmi_system_id dmi_tas_approved_list[] = {
1052 { .ident = "HP",
1053 .matches = {
1054 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1055 },
1056 },
1057 { .ident = "SAMSUNG",
1058 .matches = {
1059 DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
1060 },
1061 },
1062 { .ident = "LENOVO",
1063 .matches = {
d0246a0e 1064 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2856f623
AB		 1065 },
1066 },
1067 { .ident = "DELL",
1068 .matches = {
1069 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1070 },
1071 },
3ecf3411
AG		 1072 { .ident = "MSFT",
1073 .matches = {
1074 DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
1075 },
1076 },
06471b67
AG		 1077 { .ident = "Acer",
1078 .matches = {
1079 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1080 },
1081 },
1082 { .ident = "ASUS",
1083 .matches = {
1084 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1085 },
1086 },
1087 { .ident = "MSI",
1088 .matches = {
1089 DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International Co., Ltd."),
1090 },
1091 },
1092 { .ident = "Honor",
1093 .matches = {
1094 DMI_MATCH(DMI_SYS_VENDOR, "HONOR"),
1095 },
1096 },
2856f623
AB		 1097 /* keep last */
1098 {}
1099};
1100
9457077d
AN		 1101bool iwl_mvm_is_vendor_in_approved_list(void)
1102{
1103 return dmi_check_system(dmi_tas_approved_list);
1104}
1105
c3f40c3e
MK		 1106static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc)
1107{
1108 int i;
1109 u32 size = le32_to_cpu(*le_size);
1110
1111 /* Verify that there is room for another country */
1112 if (size >= IWL_TAS_BLOCK_LIST_MAX)
1113 return false;
1114
1115 for (i = 0; i < size; i++) {
1116 if (list[i] == cpu_to_le32(mcc))
1117 return true;
1118 }
1119
1120 list[size++] = cpu_to_le32(mcc);
1121 *le_size = cpu_to_le32(size);
1122 return true;
1123}
1124
28dd7ccd
MG		 1125static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1126{
971cbe50 1127 u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG);
28dd7ccd 1128 int ret;
6da7ba3a
AB		 1129 union iwl_tas_config_cmd cmd = {};
1130 int cmd_size, fw_ver;
28dd7ccd 1131
6da7ba3a 1132 BUILD_BUG_ON(ARRAY_SIZE(cmd.v3.block_list_array) <
28dd7ccd
MG		 1133 APCI_WTAS_BLACK_LIST_MAX);
1134
1135 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1136 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1137 return;
1138 }
1139
971cbe50
JB		 1140 fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
1141 IWL_FW_CMD_VER_UNKNOWN);
6da7ba3a
AB		 1142
1143 ret = iwl_acpi_get_tas(&mvm->fwrt, &cmd, fw_ver);
28dd7ccd
MG		 1144 if (ret < 0) {
1145 IWL_DEBUG_RADIO(mvm,
1146 "TAS table invalid or unavailable. (%d)\n",
1147 ret);
1148 return;
1149 }
1150
7c530588 1151 if (ret == 0)
28dd7ccd
MG		 1152 return;
1153
c4fbf653 1154 if (!iwl_mvm_is_vendor_in_approved_list()) {
c3f40c3e
MK		 1155 IWL_DEBUG_RADIO(mvm,
1156 "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
1157 dmi_get_system_info(DMI_SYS_VENDOR));
6da7ba3a
AB		 1158 if ((!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1159 &cmd.v4.block_list_size,
1160 IWL_TAS_US_MCC)) ||
1161 (!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1162 &cmd.v4.block_list_size,
1163 IWL_TAS_CANADA_MCC))) {
c3f40c3e
MK		 1164 IWL_DEBUG_RADIO(mvm,
1165 "Unable to add US/Canada to TAS block list, disabling TAS\n");
1166 return;
1167 }
06471b67
AG		 1168 } else {
1169 IWL_DEBUG_RADIO(mvm,
1170 "System vendor '%s' is in the approved list.\n",
1171 dmi_get_system_info(DMI_SYS_VENDOR));
c3f40c3e
MK		 1172 }
1173
6da7ba3a
AB		 1174 /* v4 is the same size as v3, so no need to differentiate here */
1175 cmd_size = fw_ver < 3 ?
7c530588
MK		 1176 sizeof(struct iwl_tas_config_cmd_v2) :
1177 sizeof(struct iwl_tas_config_cmd_v3);
28dd7ccd 1178
971cbe50 1179 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd);
28dd7ccd
MG		 1180 if (ret < 0)
1181 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1182}
f5b1cb2e 1183
4e8fe214
GG		 1184static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1185{
1186 u8 value;
45fe1b6b 1187 int ret = iwl_acpi_get_dsm_u8(mvm->fwrt.dev, 0, DSM_RFI_FUNC_ENABLE,
4e8fe214
GG		 1188 &iwl_rfi_guid, &value);
1189
1190 if (ret < 0) {
1191 IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
1192
1193 } else if (value >= DSM_VALUE_RFI_MAX) {
1194 IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n",
1195 value);
1196
1197 } else if (value == DSM_VALUE_RFI_ENABLE) {
1198 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
1199 return DSM_VALUE_RFI_ENABLE;
1200 }
1201
1202 IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n");
1203
1204 /* default behaviour is disabled */
1205 return DSM_VALUE_RFI_DISABLE;
1206}
1207
f5b1cb2e
GA		 1208static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1209{
7119f02b
MK		 1210 int ret;
1211 u32 value;
8f323d06 1212 struct iwl_lari_config_change_cmd_v6 cmd = {};
f5b1cb2e 1213
f21afaba 1214 cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt);
d2bfda8a 1215
45fe1b6b 1216 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_11AX_ENABLEMENT,
7119f02b
MK		 1217 &iwl_guid, &value);
1218 if (!ret)
1219 cmd.oem_11ax_allow_bitmap = cpu_to_le32(value);
f5b1cb2e 1220
45fe1b6b 1221 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
54b4fda5
AN		 1222 DSM_FUNC_ENABLE_UNII4_CHAN,
1223 &iwl_guid, &value);
1224 if (!ret)
1225 cmd.oem_unii4_allow_bitmap = cpu_to_le32(value);
1226
45fe1b6b 1227 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1f578d4f
MK		 1228 DSM_FUNC_ACTIVATE_CHANNEL,
1229 &iwl_guid, &value);
1230 if (!ret)
1231 cmd.chan_state_active_bitmap = cpu_to_le32(value);
1232
698b166e
LC		 1233 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1234 DSM_FUNC_ENABLE_6E,
1235 &iwl_guid, &value);
1236 if (!ret)
1237 cmd.oem_uhb_allow_bitmap = cpu_to_le32(value);
1238
8f323d06
AB		 1239 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1240 DSM_FUNC_FORCE_DISABLE_CHANNELS,
1241 &iwl_guid, &value);
1242 if (!ret)
1243 cmd.force_disable_channels_bitmap = cpu_to_le32(value);
1244
54b4fda5 1245 if (cmd.config_bitmap ||
698b166e 1246 cmd.oem_uhb_allow_bitmap ||
54b4fda5 1247 cmd.oem_11ax_allow_bitmap ||
1f578d4f 1248 cmd.oem_unii4_allow_bitmap ||
8f323d06
AB		 1249 cmd.chan_state_active_bitmap ||
1250 cmd.force_disable_channels_bitmap) {
3c21990b
MK		 1251 size_t cmd_size;
1252 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw,
971cbe50
JB		 1253 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1254 LARI_CONFIG_CHANGE),
1255 1);
8f323d06
AB		 1256 switch (cmd_ver) {
1257 case 6:
1258 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v6);
1259 break;
1260 case 5:
1f578d4f 1261 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v5);
8f323d06
AB		 1262 break;
1263 case 4:
54b4fda5 1264 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4);
8f323d06
AB		 1265 break;
1266 case 3:
3c21990b 1267 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3);
8f323d06
AB		 1268 break;
1269 case 2:
3c21990b 1270 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2);
8f323d06
AB		 1271 break;
1272 default:
3c21990b 1273 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1);
8f323d06
AB		 1274 break;
1275 }
3c21990b 1276
3ce88247 1277 IWL_DEBUG_RADIO(mvm,
7119f02b
MK		 1278 "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n",
1279 le32_to_cpu(cmd.config_bitmap),
1280 le32_to_cpu(cmd.oem_11ax_allow_bitmap));
54b4fda5 1281 IWL_DEBUG_RADIO(mvm,
1f578d4f 1282 "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, chan_state_active_bitmap=0x%x, cmd_ver=%d\n",
54b4fda5 1283 le32_to_cpu(cmd.oem_unii4_allow_bitmap),
1f578d4f 1284 le32_to_cpu(cmd.chan_state_active_bitmap),
54b4fda5 1285 cmd_ver);
698b166e 1286 IWL_DEBUG_RADIO(mvm,
8f323d06
AB		 1287 "sending LARI_CONFIG_CHANGE, oem_uhb_allow_bitmap=0x%x, force_disable_channels_bitmap=0x%x\n",
1288 le32_to_cpu(cmd.oem_uhb_allow_bitmap),
1289 le32_to_cpu(cmd.force_disable_channels_bitmap));
7119f02b
MK		 1290 ret = iwl_mvm_send_cmd_pdu(mvm,
1291 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1292 LARI_CONFIG_CHANGE),
1293 0, cmd_size, &cmd);
1294 if (ret < 0)
f5b1cb2e
GA		 1295 IWL_DEBUG_RADIO(mvm,
1296 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
7119f02b 1297 ret);
f5b1cb2e
GA		 1298 }
1299}
78a19d52
MK		 1300
1301void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1302{
1303 int ret;
1304
1305 /* read PPAG table */
e8e10a37 1306 ret = iwl_acpi_get_ppag_table(&mvm->fwrt);
78a19d52
MK		 1307 if (ret < 0) {
1308 IWL_DEBUG_RADIO(mvm,
1309 "PPAG BIOS table invalid or unavailable. (%d)\n",
1310 ret);
1311 }
1312
1313 /* read SAR tables */
1314 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
1315 if (ret < 0) {
1316 IWL_DEBUG_RADIO(mvm,
1317 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1318 ret);
1319 /*
1320 * If not available, don't fail and don't bother with EWRD and
1321 * WGDS */
1322
1323 if (!iwl_sar_get_wgds_table(&mvm->fwrt)) {
1324 /*
1325 * If basic SAR is not available, we check for WGDS,
1326 * which should *not* be available either. If it is
1327 * available, issue an error, because we can't use SAR
1328 * Geo without basic SAR.
1329 */
1330 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1331 }
1332
1333 } else {
1334 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
1335 /* if EWRD is not available, we can still use
1336 * WRDS, so don't fail */
1337 if (ret < 0)
1338 IWL_DEBUG_RADIO(mvm,
1339 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1340 ret);
1341
1342 /* read geo SAR table */
1343 if (iwl_sar_geo_support(&mvm->fwrt)) {
1344 ret = iwl_sar_get_wgds_table(&mvm->fwrt);
1345 if (ret < 0)
1346 IWL_DEBUG_RADIO(mvm,
1347 "Geo SAR BIOS table invalid or unavailable. (%d)\n",
1348 ret);
1349 /* we don't fail if the table is not available */
1350 }
1351 }
c4c95454
JB		 1352
1353 iwl_acpi_get_phy_filters(&mvm->fwrt, &mvm->phy_filters);
78a19d52 1354}
69964905 1355#else /* CONFIG_ACPI */
69964905 1356
39c1a972
IZ		 1357inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1358 int prof_a, int prof_b)
69964905 1359{
78a19d52 1360 return 1;
69964905 1361}
a6bff3cb 1362
39c1a972 1363inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC		 1364{
1365 return -ENOENT;
1366}
1367
a6bff3cb
HD		 1368static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1369{
1370 return 0;
1371}
18f1755d 1372
6ce1e5c0
GA		 1373int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1374{
1375 return -ENOENT;
1376}
1377
1378static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1379{
7937fd32 1380 return 0;
6ce1e5c0 1381}
28dd7ccd
MG		 1382
1383static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1384{
1385}
f5b1cb2e
GA		 1386
1387static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1388{
1389}
4e8fe214 1390
9457077d
AN		 1391bool iwl_mvm_is_vendor_in_approved_list(void)
1392{
1393 return false;
1394}
1395
4e8fe214
GG		 1396static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1397{
1398 return DSM_VALUE_RFI_DISABLE;
1399}
78a19d52
MK		 1400
1401void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1402{
1403}
c593d2fa 1404
69964905
LC		 1405#endif /* CONFIG_ACPI */
1406
f130bb75
MG		 1407void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1408{
1409 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1410 int ret;
1411 u32 resp;
1412
1413 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1414 .flags = cpu_to_le32(flags),
1415 .buf_size = 0,
1416 };
1417 struct iwl_host_cmd host_cmd = {
1418 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1419 .flags = CMD_WANT_SKB,
1420 .data = {&recovery_cmd, },
1421 .len = {sizeof(recovery_cmd), },
1422 };
1423
1424 /* no error log was defined in TLV */
1425 if (!error_log_size)
1426 return;
1427
1428 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1429 /* no buf was allocated while HW reset */
1430 if (!mvm->error_recovery_buf)
1431 return;
1432
1433 host_cmd.data[1] = mvm->error_recovery_buf;
1434 host_cmd.len[1] = error_log_size;
1435 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1436 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1437 }
1438
1439 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1440 kfree(mvm->error_recovery_buf);
1441 mvm->error_recovery_buf = NULL;
1442
1443 if (ret) {
1444 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1445 return;
1446 }
1447
1448 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1449 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1450 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1451 if (resp)
1452 IWL_ERR(mvm,
1453 "Failed to send recovery cmd blob was invalid %d\n",
1454 resp);
1455 }
1456}
1457
42ce76d6
LC		 1458static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1459{
1edd56e6 1460 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC		 1461}
1462
1f370650 1463static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1464{
1f370650 1465 int ret;
8ca151b5 1466
7d6222e2 1467 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1468 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1469
3b25f1af 1470 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1471
f2082a53 1472 if (ret) {
8d193ca2 1473 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK		 1474
1475 if (iwlmvm_mod_params.init_dbg)
1476 return 0;
1f370650 1477 return ret;
8d193ca2 1478 }
8ca151b5 1479
203c83d3 1480 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG		 1481 iwl_trans_stop_device(mvm->trans);
1482 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1483 if (ret)
1f370650 1484 return ret;
8ca151b5 1485
94022562 1486 mvm->rfkill_safe_init_done = false;
8ca151b5 1487 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS		 1488 if (ret)
1489 return ret;
1490
94022562
EG		 1491 mvm->rfkill_safe_init_done = true;
1492
b108d8c7
SM		 1493 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1494 NULL);
da2eb669 1495
702e975d 1496 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS		 1497}
1498
1499int iwl_mvm_up(struct iwl_mvm *mvm)
1500{
1501 int ret, i;
1502 struct ieee80211_channel *chan;
1503 struct cfg80211_chan_def chandef;
dd36a507 1504 struct ieee80211_supported_band *sband = NULL;
733eb54f 1505 u32 sb_cfg;
1f370650
SS		 1506
1507 lockdep_assert_held(&mvm->mutex);
1508
1509 ret = iwl_trans_start_hw(mvm->trans);
1510 if (ret)
1511 return ret;
733eb54f
AS		 1512
1513 sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
b8133439
AS		 1514 mvm->pldr_sync = !(sb_cfg & SB_CFG_RESIDES_IN_OTP_MASK);
1515 if (mvm->pldr_sync && iwl_mei_pldr_req())
274d9aa9 1516 return -EBUSY;
1f370650
SS		 1517
1518 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB		 1519 if (ret) {
1520 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
b8133439 1521 if (ret != -ERFKILL && !mvm->pldr_sync)
72d3c7bb
JB		 1522 iwl_fw_dbg_error_collect(&mvm->fwrt,
1523 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB		 1524 goto error;
1525 }
1526
b8133439
AS		 1527 /* FW loaded successfully */
1528 mvm->pldr_sync = false;
1529
d0b813fc 1530 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1531
1f3b0ff8
LE		 1532 ret = iwl_mvm_sf_update(mvm, NULL, false);
1533 if (ret)
1534 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1535
a1af4c48 1536 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS		 1537 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1538 /* if we have a destination, assume EARLY START */
1539 if (mvm->fw->dbg.dest_tlv)
1540 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1541 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1542 }
6a951267 1543
a0544272 1544 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1545 if (ret)
1546 goto error;
1547
7d6222e2
JB		 1548 if (!iwl_mvm_has_unified_ucode(mvm)) {
1549 /* Send phy db control command and then phy db calibration */
1f370650
SS		 1550 ret = iwl_send_phy_db_data(mvm->phy_db);
1551 if (ret)
1552 goto error;
d2ccc5c1
MS		 1553 ret = iwl_send_phy_cfg_cmd(mvm);
1554 if (ret)
1555 goto error;
1f370650 1556 }
8ca151b5 1557
b3de3ef4
EG		 1558 ret = iwl_mvm_send_bt_init_conf(mvm);
1559 if (ret)
1560 goto error;
1561
cceb4507
SM		 1562 if (fw_has_capa(&mvm->fw->ucode_capa,
1563 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1564 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM		 1565 if (ret)
1566 goto error;
1567 }
1568
43413a97 1569 /* Init RSS configuration */
9cd243f2
MG		 1570 ret = iwl_configure_rxq(&mvm->fwrt);
1571 if (ret)
1572 goto error;
8edbfaa1
SS		 1573
1574 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS		 1575 ret = iwl_send_rss_cfg_cmd(mvm);
1576 if (ret) {
1577 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1578 ret);
1579 goto error;
1580 }
1581 }
1582
8ca151b5 1583 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1584 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1585 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB		 1586 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1587 }
8ca151b5 1588
d464550b
YB		 1589 for (i = 0; i < IWL_MVM_FW_MAX_LINK_ID + 1; i++)
1590 RCU_INIT_POINTER(mvm->link_id_to_link_conf[i], NULL);
1591
d6f6b0d8
GG		 1592 memset(&mvm->fw_link_ids_map, 0, sizeof(mvm->fw_link_ids_map));
1593
0ae98812 1594 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1595
b2b7875b
JB		 1596 /* reset quota debouncing buffer - 0xff will yield invalid data */
1597 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1598
79660869
IL		 1599 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1600 ret = iwl_mvm_send_dqa_cmd(mvm);
1601 if (ret)
1602 goto error;
1603 }
97d5be7e 1604
2c2c3647
NE		 1605 /*
1606 * Add auxiliary station for scanning.
1607 * Newer versions of this command implies that the fw uses
1608 * internal aux station for all aux activities that don't
1609 * requires a dedicated data queue.
1610 */
1724fc78 1611 if (!iwl_mvm_has_new_station_api(mvm->fw)) {
2c2c3647
NE		 1612 /*
1613 * In old version the aux station uses mac id like other
1614 * station and not lmac id
1615 */
1616 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1617 if (ret)
1618 goto error;
1619 }
8ca151b5 1620
53a9d61e 1621 /* Add all the PHY contexts */
dd36a507
TM		 1622 i = 0;
1623 while (!sband && i < NUM_NL80211_BANDS)
1624 sband = mvm->hw->wiphy->bands[i++];
1625
583d1833
DC		 1626 if (WARN_ON_ONCE(!sband)) {
1627 ret = -ENODEV;
dd36a507 1628 goto error;
583d1833 1629 }
dd36a507
TM		 1630
1631 chan = &sband->channels[0];
1632
53a9d61e
IP		 1633 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1634 for (i = 0; i < NUM_PHY_CTX; i++) {
1635 /*
1636 * The channel used here isn't relevant as it's
1637 * going to be overwritten in the other flows.
1638 * For now use the first channel we have.
1639 */
1640 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1641 &chandef, 1, 1);
1642 if (ret)
1643 goto error;
1644 }
8ca151b5 1645
c221daf2
CRI		 1646 if (iwl_mvm_is_tt_in_fw(mvm)) {
1647 /* in order to give the responsibility of ct-kill and
1648 * TX backoff to FW we need to send empty temperature reporting
1649 * cmd during init time
1650 */
1651 iwl_mvm_send_temp_report_ths_cmd(mvm);
1652 } else {
1653 /* Initialize tx backoffs to the minimal possible */
1654 iwl_mvm_tt_tx_backoff(mvm, 0);
1655 }
5c89e7bc 1656
242d9c8b 1657#ifdef CONFIG_THERMAL
5c89e7bc 1658 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI		 1659
1660 /*
1661 * In case there is no budget from BIOS / Platform NVM the default
1662 * budget should be 2000mW (cooling state 0).
1663 */
1664 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI		 1665 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1666 mvm->cooling_dev.cur_state);
75cfe338
LC		 1667 if (ret)
1668 goto error;
1669 }
c221daf2 1670#endif
0c0e2c71 1671
aa43ae12
AM		 1672 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1673 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1674
c1cb92fc 1675 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB		 1676 if (ret)
1677 goto error;
1678
f5b1cb2e 1679 iwl_mvm_lari_cfg(mvm);
35af15d1
AN		 1680 /*
1681 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1682 * anyway, so don't init MCC.
1683 */
1684 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1685 ret = iwl_mvm_init_mcc(mvm);
1686 if (ret)
1687 goto error;
1688 }
90d4f7db 1689
859d914c 1690 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1691 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1692 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS		 1693 ret = iwl_mvm_config_scan(mvm);
1694 if (ret)
1695 goto error;
1696 }
1697
cf85123a 1698 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) {
f130bb75 1699 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
ead65aa2
JB		 1700
1701 if (mvm->time_sync.active)
1702 iwl_mvm_time_sync_config(mvm, mvm->time_sync.peer_addr,
1703 IWL_TIME_SYNC_PROTOCOL_TM |
1704 IWL_TIME_SYNC_PROTOCOL_FTM);
cf85123a 1705 }
f130bb75 1706
1595ecce
KP		 1707 if (!mvm->ptp_data.ptp_clock)
1708 iwl_mvm_ptp_init(mvm);
1709
48e775e6
HD		 1710 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1711 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1712
6ce1e5c0
GA		 1713 ret = iwl_mvm_ppag_init(mvm);
1714 if (ret)
1715 goto error;
1716
da2830ac 1717 ret = iwl_mvm_sar_init(mvm);
78a19d52 1718 if (ret == 0)
5d041c46 1719 ret = iwl_mvm_sar_geo_init(mvm);
5f06f6bf 1720 if (ret < 0)
a6bff3cb
HD		 1721 goto error;
1722
c593d2fa
AB		 1723 ret = iwl_mvm_sgom_init(mvm);
1724 if (ret)
1725 goto error;
1726
28dd7ccd 1727 iwl_mvm_tas_init(mvm);
7089ae63
JB		 1728 iwl_mvm_leds_sync(mvm);
1729
9e26f098 1730 if (iwl_rfi_supported(mvm)) {
4e8fe214
GG		 1731 if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE)
1732 iwl_rfi_send_config_cmd(mvm, NULL);
1733 }
1734
5aa7ce31
AS		 1735 iwl_mvm_mei_device_state(mvm, true);
1736
53a9d61e 1737 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB		 1738 return 0;
1739 error:
f4744258 1740 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1741 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1742 return ret;
1743}
1744
1745int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1746{
1747 int ret, i;
1748
1749 lockdep_assert_held(&mvm->mutex);
1750
1751 ret = iwl_trans_start_hw(mvm->trans);
1752 if (ret)
1753 return ret;
1754
1755 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1756 if (ret) {
1757 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1758 goto error;
1759 }
1760
a0544272 1761 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1762 if (ret)
1763 goto error;
1764
1765 /* Send phy db control command and then phy db calibration*/
1766 ret = iwl_send_phy_db_data(mvm->phy_db);
1767 if (ret)
1768 goto error;
1769
1770 ret = iwl_send_phy_cfg_cmd(mvm);
1771 if (ret)
1772 goto error;
1773
1774 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1775 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1776 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB		 1777 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1778 }
8ca151b5 1779
1724fc78 1780 if (!iwl_mvm_has_new_station_api(mvm->fw)) {
2c2c3647
NE		 1781 /*
1782 * Add auxiliary station for scanning.
1783 * Newer versions of this command implies that the fw uses
1784 * internal aux station for all aux activities that don't
1785 * requires a dedicated data queue.
1786 * In old version the aux station uses mac id like other
1787 * station and not lmac id
1788 */
1789 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1790 if (ret)
1791 goto error;
1792 }
8ca151b5
JB		 1793
1794 return 0;
1795 error:
fcb6b92a 1796 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1797 return ret;
1798}
1799
0416841d
JB		 1800void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1801 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI		 1802{
1803 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1804 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1805
0c8d0a47
GBA		 1806 IWL_DEBUG_INFO(mvm,
1807 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1808 le32_to_cpu(mfuart_notif->installed_ver),
1809 le32_to_cpu(mfuart_notif->external_ver),
1810 le32_to_cpu(mfuart_notif->status),
1811 le32_to_cpu(mfuart_notif->duration));
1812
19f63c53
GBA		 1813 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1814 IWL_DEBUG_INFO(mvm,
0c8d0a47 1815 "MFUART: image size: 0x%08x\n",
19f63c53 1816 le32_to_cpu(mfuart_notif->image_size));
30269c12 1817}
Linux 6.x block layer and io_uring tree(s)