iwlwifi: bump FW API to 71 for AX devices
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
a7de31d5 3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
8e99ea8d
JB
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
a2ac0f48 9#include <linux/dmi.h>
8ca151b5
JB
10
11#include "iwl-trans.h"
12#include "iwl-op-mode.h"
d962f9b1 13#include "fw/img.h"
8ca151b5 14#include "iwl-debug.h"
8c23f95c 15#include "iwl-prph.h"
813df5ce 16#include "fw/acpi.h"
b3e4c0f3 17#include "fw/pnvm.h"
8ca151b5
JB
18
19#include "mvm.h"
7174beb6 20#include "fw/dbg.h"
8ca151b5 21#include "iwl-phy-db.h"
9c4f7d51
ST
22#include "iwl-modparams.h"
23#include "iwl-nvm-parse.h"
8ca151b5 24
b3e4c0f3
LC
25#define MVM_UCODE_ALIVE_TIMEOUT (HZ)
26#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5 27
e12cfc7b
MK
28#define IWL_PPAG_MASK 3
29#define IWL_PPAG_ETSI_MASK BIT(0)
30
c3f40c3e
MK
31#define IWL_TAS_US_MCC 0x5553
32#define IWL_TAS_CANADA_MCC 0x4341
33
8ca151b5
JB
34struct iwl_mvm_alive_data {
35 bool valid;
36 u32 scd_base_addr;
37};
38
8ca151b5
JB
39static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
40{
41 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
42 .valid = cpu_to_le32(valid_tx_ant),
43 };
44
33223542 45 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 46 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB
47 sizeof(tx_ant_cmd), &tx_ant_cmd);
48}
49
43413a97
SS
50static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
51{
52 int i;
53 struct iwl_rss_config_cmd cmd = {
54 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS
55 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
56 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
58 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
59 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
60 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS
61 };
62
f43495fd
SS
63 if (mvm->trans->num_rx_queues == 1)
64 return 0;
65
854d773e 66 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 67 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS
68 cmd.indirection_table[i] =
69 1 + (i % (mvm->trans->num_rx_queues - 1));
70 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS
71
72 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
73}
74
97d5be7e
LK
75static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
76{
77 struct iwl_dqa_enable_cmd dqa_cmd = {
78 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
79 };
f0c86427 80 u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD);
97d5be7e
LK
81 int ret;
82
83 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
84 if (ret)
85 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
86 else
87 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
88
89 return ret;
90}
91
bdccdb85
GBA
92void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
93 struct iwl_rx_cmd_buffer *rxb)
94{
95 struct iwl_rx_packet *pkt = rxb_addr(rxb);
96 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
97 __le32 *dump_data = mfu_dump_notif->data;
98 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
99 int i;
100
101 if (mfu_dump_notif->index_num == 0)
102 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
103 le32_to_cpu(mfu_dump_notif->assert_id));
104
105 for (i = 0; i < n_words; i++)
106 IWL_DEBUG_INFO(mvm,
107 "MFUART assert dump, dword %u: 0x%08x\n",
108 le16_to_cpu(mfu_dump_notif->index_num) *
109 n_words + i,
110 le32_to_cpu(dump_data[i]));
111}
112
8ca151b5
JB
113static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
114 struct iwl_rx_packet *pkt, void *data)
115{
fd1c3318 116 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB
117 struct iwl_mvm *mvm =
118 container_of(notif_wait, struct iwl_mvm, notif_wait);
119 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS
120 struct iwl_umac_alive *umac;
121 struct iwl_lmac_alive *lmac1;
122 struct iwl_lmac_alive *lmac2 = NULL;
123 u16 status;
cfa5d0ca 124 u32 lmac_error_event_table, umac_error_table;
708d8c53
JB
125 u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
126 UCODE_ALIVE_NTFY, 0);
01a9ca51 127
c0941ace
MS
128 if (version == 6) {
129 struct iwl_alive_ntf_v6 *palive;
130
131 if (pkt_len < sizeof(*palive))
132 return false;
133
134 palive = (void *)pkt->data;
135 mvm->trans->dbg.imr_data.imr_enable =
136 le32_to_cpu(palive->imr.enabled);
137 mvm->trans->dbg.imr_data.imr_size =
138 le32_to_cpu(palive->imr.size);
139 mvm->trans->dbg.imr_data.imr2sram_remainbyte =
140 mvm->trans->dbg.imr_data.imr_size;
141 mvm->trans->dbg.imr_data.imr_base_addr =
142 palive->imr.base_addr;
143 mvm->trans->dbg.imr_data.imr_curr_addr =
144 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr);
145 IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n",
146 mvm->trans->dbg.imr_data.imr_enable,
147 mvm->trans->dbg.imr_data.imr_size,
148 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr));
149 }
150
151 if (version >= 5) {
90824f2f
LC
152 struct iwl_alive_ntf_v5 *palive;
153
fd1c3318
JB
154 if (pkt_len < sizeof(*palive))
155 return false;
156
90824f2f
LC
157 palive = (void *)pkt->data;
158 umac = &palive->umac_data;
159 lmac1 = &palive->lmac_data[0];
160 lmac2 = &palive->lmac_data[1];
161 status = le16_to_cpu(palive->status);
162
163 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
164 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
165 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
166
167 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
168 mvm->trans->sku_id[0],
169 mvm->trans->sku_id[1],
170 mvm->trans->sku_id[2]);
171 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC
172 struct iwl_alive_ntf_v4 *palive;
173
fd1c3318
JB
174 if (pkt_len < sizeof(*palive))
175 return false;
176
5c228d63
SS
177 palive = (void *)pkt->data;
178 umac = &palive->umac_data;
179 lmac1 = &palive->lmac_data[0];
180 lmac2 = &palive->lmac_data[1];
181 status = le16_to_cpu(palive->status);
9422b978
LC
182 } else if (iwl_rx_packet_payload_len(pkt) ==
183 sizeof(struct iwl_alive_ntf_v3)) {
184 struct iwl_alive_ntf_v3 *palive3;
185
fd1c3318
JB
186 if (pkt_len < sizeof(*palive3))
187 return false;
188
5c228d63
SS
189 palive3 = (void *)pkt->data;
190 umac = &palive3->umac_data;
191 lmac1 = &palive3->lmac_data;
192 status = le16_to_cpu(palive3->status);
9422b978
LC
193 } else {
194 WARN(1, "unsupported alive notification (size %d)\n",
195 iwl_rx_packet_payload_len(pkt));
196 /* get timeout later */
197 return false;
5c228d63 198 }
01a9ca51 199
22463857
SM
200 lmac_error_event_table =
201 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
202 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
203
5c228d63 204 if (lmac2)
91c28b83 205 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 206 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 207
4f7411d6
RG
208 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
209 ~FW_ADDR_CACHE_CONTROL;
cfa5d0ca
MG
210
211 if (umac_error_table) {
212 if (umac_error_table >=
213 mvm->trans->cfg->min_umac_error_event_table) {
214 iwl_fw_umac_set_alive_err_table(mvm->trans,
215 umac_error_table);
216 } else {
217 IWL_ERR(mvm,
218 "Not valid error log pointer 0x%08X for %s uCode\n",
219 umac_error_table,
220 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
221 "Init" : "RT");
222 }
3485e76e 223 }
fb5b2846 224
22463857 225 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 226 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 227
5c228d63
SS
228 IWL_DEBUG_FW(mvm,
229 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
230 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 231
5c228d63
SS
232 if (lmac2)
233 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 234
5c228d63
SS
235 IWL_DEBUG_FW(mvm,
236 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
237 le32_to_cpu(umac->umac_major),
238 le32_to_cpu(umac->umac_minor));
8ca151b5 239
0a3a3e9e
SM
240 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
241
8ca151b5
JB
242 return true;
243}
244
1f370650
SS
245static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
246 struct iwl_rx_packet *pkt, void *data)
247{
248 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
249
250 return true;
251}
252
8ca151b5
JB
253static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
254 struct iwl_rx_packet *pkt, void *data)
255{
256 struct iwl_phy_db *phy_db = data;
257
258 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
259 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
260 return true;
261 }
262
ce1f2778 263 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB
264
265 return false;
266}
267
a7de31d5
MG
268static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
269{
270 struct iwl_trans *trans = mvm->trans;
271 enum iwl_device_family device_family = trans->trans_cfg->device_family;
272
273 if (device_family < IWL_DEVICE_FAMILY_8000)
274 return;
275
276 if (device_family <= IWL_DEVICE_FAMILY_9000)
277 IWL_ERR(mvm, "WFPM_ARC1_PD_NOTIFICATION: 0x%x\n",
278 iwl_read_umac_prph(trans, WFPM_ARC1_PD_NOTIFICATION));
279 else
280 IWL_ERR(mvm, "WFPM_LMAC1_PD_NOTIFICATION: 0x%x\n",
281 iwl_read_umac_prph(trans, WFPM_LMAC1_PD_NOTIFICATION));
f2f17ca0
MG
282
283 IWL_ERR(mvm, "HPM_SECONDARY_DEVICE_STATE: 0x%x\n",
284 iwl_read_umac_prph(trans, HPM_SECONDARY_DEVICE_STATE));
285
a7de31d5
MG
286}
287
8ca151b5
JB
288static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
289 enum iwl_ucode_type ucode_type)
290{
291 struct iwl_notification_wait alive_wait;
94a8d87c 292 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 293 const struct fw_img *fw;
cfbc6c4c 294 int ret;
702e975d 295 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 296 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG
297 bool run_in_rfkill =
298 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
8ca151b5 299
61df750c 300 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA
301 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
302 !(fw_has_capa(&mvm->fw->ucode_capa,
303 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 304 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 305 else
612da1ef 306 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 307 if (WARN_ON(!fw))
8ca151b5 308 return -EINVAL;
702e975d 309 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 310 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB
311
312 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
313 alive_cmd, ARRAY_SIZE(alive_cmd),
314 iwl_alive_fn, &alive_data);
315
b3500b47
EG
316 /*
317 * We want to load the INIT firmware even in RFKILL
318 * For the unified firmware case, the ucode_type is not
319 * INIT, but we still need to run it.
320 */
321 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 322 if (ret) {
702e975d 323 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
324 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
325 return ret;
326 }
327
328 /*
329 * Some things may run in the background now, but we
330 * just wait for the ALIVE notification here.
331 */
332 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
333 MVM_UCODE_ALIVE_TIMEOUT);
334 if (ret) {
d6be9c1d
SS
335 struct iwl_trans *trans = mvm->trans;
336
5667ccc2 337 /* SecBoot info */
20f5aef5
JB
338 if (trans->trans_cfg->device_family >=
339 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS
340 IWL_ERR(mvm,
341 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST
342 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
343 iwl_read_umac_prph(trans,
344 UMAG_SB_CPU_2_STATUS));
5667ccc2
MG
345 } else if (trans->trans_cfg->device_family >=
346 IWL_DEVICE_FAMILY_8000) {
347 IWL_ERR(mvm,
348 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
349 iwl_read_prph(trans, SB_CPU_1_STATUS),
350 iwl_read_prph(trans, SB_CPU_2_STATUS));
351 }
352
a7de31d5
MG
353 iwl_mvm_print_pd_notification(mvm);
354
5667ccc2
MG
355 /* LMAC/UMAC PC info */
356 if (trans->trans_cfg->device_family >=
357 IWL_DEVICE_FAMILY_9000) {
20f5aef5
JB
358 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
359 iwl_read_umac_prph(trans,
360 UREG_UMAC_CURRENT_PC));
361 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
362 iwl_read_umac_prph(trans,
363 UREG_LMAC1_CURRENT_PC));
364 if (iwl_mvm_is_cdb_supported(mvm))
365 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
366 iwl_read_umac_prph(trans,
367 UREG_LMAC2_CURRENT_PC));
20f5aef5
JB
368 }
369
370 if (ret == -ETIMEDOUT)
371 iwl_fw_dbg_error_collect(&mvm->fwrt,
372 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
373
702e975d 374 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
375 return ret;
376 }
377
378 if (!alive_data.valid) {
379 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 380 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
381 return -EIO;
382 }
383
b3e4c0f3 384 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait);
70d3ca86
LC
385 if (ret) {
386 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
387 iwl_fw_set_current_image(&mvm->fwrt, old_type);
388 return ret;
389 }
390
8ca151b5
JB
391 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
392
393 /*
394 * Note: all the queues are enabled as part of the interface
395 * initialization, but in firmware restart scenarios they
396 * could be stopped, so wake them up. In firmware restart,
397 * mac80211 will have the queues stopped as well until the
398 * reconfiguration completes. During normal startup, they
399 * will be empty.
400 */
401
4ecafae9 402 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB
403 /*
404 * Set a 'fake' TID for the command queue, since we use the
405 * hweight() of the tid_bitmap as a refcount now. Not that
406 * we ever even consider the command queue as one we might
407 * want to reuse, but be safe nevertheless.
408 */
409 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
410 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 411
65b280fe 412 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC
413#ifdef CONFIG_IWLWIFI_DEBUGFS
414 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
415#endif
8ca151b5 416
d3d9b4fc
EG
417 /*
418 * All the BSSes in the BSS table include the GP2 in the system
419 * at the beacon Rx time, this is of course no longer relevant
420 * since we are resetting the firmware.
421 * Purge all the BSS table.
422 */
423 cfg80211_bss_flush(mvm->hw->wiphy);
424
8ca151b5
JB
425 return 0;
426}
8ca151b5 427
52b15521 428static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
8c5f47b1
JB
429{
430 struct iwl_notification_wait init_wait;
431 struct iwl_nvm_access_complete_cmd nvm_complete = {};
432 struct iwl_init_extended_cfg_cmd init_cfg = {
433 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
434 };
435 static const u16 init_complete[] = {
436 INIT_COMPLETE_NOTIF,
437 };
438 int ret;
439
a4584729
HD
440 if (mvm->trans->cfg->tx_with_siso_diversity)
441 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
442
8c5f47b1
JB
443 lockdep_assert_held(&mvm->mutex);
444
94022562
EG
445 mvm->rfkill_safe_init_done = false;
446
8c5f47b1
JB
447 iwl_init_notification_wait(&mvm->notif_wait,
448 &init_wait,
449 init_complete,
450 ARRAY_SIZE(init_complete),
451 iwl_wait_init_complete,
452 NULL);
453
b108d8c7 454 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
86ce5c74 455
8c5f47b1
JB
456 /* Will also start the device */
457 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
458 if (ret) {
459 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
460 goto error;
461 }
b108d8c7
SM
462 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
463 NULL);
8c5f47b1
JB
464
465 /* Send init config command to mark that we are sending NVM access
466 * commands
467 */
468 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
b3500b47
EG
469 INIT_EXTENDED_CFG_CMD),
470 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
471 sizeof(init_cfg), &init_cfg);
472 if (ret) {
473 IWL_ERR(mvm, "Failed to run init config command: %d\n",
474 ret);
475 goto error;
476 }
477
e9e1ba3d
SS
478 /* Load NVM to NIC if needed */
479 if (mvm->nvm_file_name) {
9ce505fe
AN
480 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
481 mvm->nvm_sections);
482 if (ret)
483 goto error;
484 ret = iwl_mvm_load_nvm_to_nic(mvm);
485 if (ret)
486 goto error;
e9e1ba3d 487 }
8c5f47b1 488
52b15521 489 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
5bd1d2c1 490 ret = iwl_nvm_init(mvm);
d4f3695e
SS
491 if (ret) {
492 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
493 goto error;
494 }
495 }
496
8c5f47b1 497 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
b3500b47
EG
498 NVM_ACCESS_COMPLETE),
499 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
500 sizeof(nvm_complete), &nvm_complete);
501 if (ret) {
502 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
503 ret);
504 goto error;
505 }
506
507 /* We wait for the INIT complete notification */
e9e1ba3d
SS
508 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
509 MVM_UCODE_ALIVE_TIMEOUT);
510 if (ret)
511 return ret;
512
513 /* Read the NVM only at driver load time, no need to do this twice */
52b15521 514 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
4c625c56 515 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
c135cb56
ST
516 if (IS_ERR(mvm->nvm_data)) {
517 ret = PTR_ERR(mvm->nvm_data);
518 mvm->nvm_data = NULL;
e9e1ba3d
SS
519 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
520 return ret;
521 }
522 }
523
b3500b47
EG
524 mvm->rfkill_safe_init_done = true;
525
e9e1ba3d 526 return 0;
8c5f47b1
JB
527
528error:
529 iwl_remove_notification(&mvm->notif_wait, &init_wait);
530 return ret;
531}
532
c4ace426
GA
533#ifdef CONFIG_ACPI
534static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
535 struct iwl_phy_specific_cfg *phy_filters)
536{
537 /*
538 * TODO: read specific phy config from BIOS
539 * ACPI table for this feature has not been defined yet,
540 * so for now we use hardcoded values.
541 */
542
543 if (IWL_MVM_PHY_FILTER_CHAIN_A) {
544 phy_filters->filter_cfg_chain_a =
545 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
546 }
547 if (IWL_MVM_PHY_FILTER_CHAIN_B) {
548 phy_filters->filter_cfg_chain_b =
549 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
550 }
551 if (IWL_MVM_PHY_FILTER_CHAIN_C) {
552 phy_filters->filter_cfg_chain_c =
553 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
554 }
555 if (IWL_MVM_PHY_FILTER_CHAIN_D) {
556 phy_filters->filter_cfg_chain_d =
557 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
558 }
559}
c4ace426
GA
560#else /* CONFIG_ACPI */
561
562static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
563 struct iwl_phy_specific_cfg *phy_filters)
564{
565}
566#endif /* CONFIG_ACPI */
567
c593d2fa
AB
568#if defined(CONFIG_ACPI) && defined(CONFIG_EFI)
569static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
570{
571 u8 cmd_ver;
572 int ret;
573 struct iwl_host_cmd cmd = {
574 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
575 SAR_OFFSET_MAPPING_TABLE_CMD),
576 .flags = 0,
577 .data[0] = &mvm->fwrt.sgom_table,
578 .len[0] = sizeof(mvm->fwrt.sgom_table),
579 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
580 };
581
582 if (!mvm->fwrt.sgom_enabled) {
583 IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n");
584 return 0;
585 }
586
971cbe50 587 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
c593d2fa
AB
588 IWL_FW_CMD_VER_UNKNOWN);
589
590 if (cmd_ver != 2) {
591 IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n",
592 cmd_ver);
593 return 0;
594 }
595
596 ret = iwl_mvm_send_cmd(mvm, &cmd);
597 if (ret < 0)
598 IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret);
599
600 return ret;
601}
602#else
603
604static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
605{
606 return 0;
607}
608#endif
609
8ca151b5
JB
610static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
611{
971cbe50 612 u32 cmd_id = PHY_CONFIGURATION_CMD;
c4ace426 613 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 614 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA
615 struct iwl_phy_specific_cfg phy_filters = {};
616 u8 cmd_ver;
617 size_t cmd_size;
8ca151b5 618
bb99ff9b 619 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 620 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 621 return 0;
d923b020
LC
622
623 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC
624 /*
625 * TODO: currently we don't set the antenna but letting the NIC
626 * to decide which antenna to use. This should come from BIOS.
627 */
628 phy_cfg_cmd.phy_cfg =
629 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
630 }
631
8ca151b5 632 /* Set parameters */
a0544272 633 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC
634
635 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC
636 phy_cfg_cmd.phy_cfg |=
637 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 638
8ca151b5
JB
639 phy_cfg_cmd.calib_control.event_trigger =
640 mvm->fw->default_calib[ucode_type].event_trigger;
641 phy_cfg_cmd.calib_control.flow_trigger =
642 mvm->fw->default_calib[ucode_type].flow_trigger;
643
971cbe50 644 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 645 IWL_FW_CMD_VER_UNKNOWN);
c4ace426
GA
646 if (cmd_ver == 3) {
647 iwl_mvm_phy_filter_init(mvm, &phy_filters);
648 memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
649 sizeof(struct iwl_phy_specific_cfg));
650 }
651
8ca151b5
JB
652 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
653 phy_cfg_cmd.phy_cfg);
c4ace426
GA
654 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
655 sizeof(struct iwl_phy_cfg_cmd_v1);
971cbe50 656 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd);
8ca151b5
JB
657}
658
3b25f1af 659int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB
660{
661 struct iwl_notification_wait calib_wait;
6eb031d2 662 static const u16 init_complete[] = {
8ca151b5
JB
663 INIT_COMPLETE_NOTIF,
664 CALIB_RES_NOTIF_PHY_DB
665 };
666 int ret;
667
7d6222e2 668 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 669 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 670
8ca151b5
JB
671 lockdep_assert_held(&mvm->mutex);
672
94022562 673 mvm->rfkill_safe_init_done = false;
8ca151b5
JB
674
675 iwl_init_notification_wait(&mvm->notif_wait,
676 &calib_wait,
677 init_complete,
678 ARRAY_SIZE(init_complete),
679 iwl_wait_phy_db_entry,
680 mvm->phy_db);
681
11f8c533
LC
682 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
683
8ca151b5
JB
684 /* Will also start the device */
685 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
686 if (ret) {
687 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 688 goto remove_notif;
8ca151b5
JB
689 }
690
7d34a7d7 691 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG
692 ret = iwl_mvm_send_bt_init_conf(mvm);
693 if (ret)
00e0c6c8 694 goto remove_notif;
b3de3ef4 695 }
931d4160 696
81a67e32 697 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 698 if (!mvm->nvm_data) {
5bd1d2c1 699 ret = iwl_nvm_init(mvm);
8ca151b5
JB
700 if (ret) {
701 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 702 goto remove_notif;
8ca151b5
JB
703 }
704 }
705
81a67e32 706 /* In case we read the NVM from external file, load it to the NIC */
9ce505fe
AN
707 if (mvm->nvm_file_name) {
708 ret = iwl_mvm_load_nvm_to_nic(mvm);
709 if (ret)
710 goto remove_notif;
711 }
81a67e32 712
64866e5d
LC
713 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
714 "Too old NVM version (0x%0x, required = 0x%0x)",
715 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 716
4f59334b
EH
717 /*
718 * abort after reading the nvm in case RF Kill is on, we will complete
719 * the init seq later when RF kill will switch to off
720 */
1a3fe0b2 721 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH
722 IWL_DEBUG_RF_KILL(mvm,
723 "jump over all phy activities due to RF kill\n");
00e0c6c8 724 goto remove_notif;
4f59334b
EH
725 }
726
b3500b47 727 mvm->rfkill_safe_init_done = true;
31b8b343 728
e07cbb53 729 /* Send TX valid antennas before triggering calibrations */
a0544272 730 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 731 if (ret)
00e0c6c8 732 goto remove_notif;
e07cbb53 733
8ca151b5
JB
734 ret = iwl_send_phy_cfg_cmd(mvm);
735 if (ret) {
736 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
737 ret);
00e0c6c8 738 goto remove_notif;
8ca151b5
JB
739 }
740
741 /*
742 * Some things may run in the background now, but we
743 * just wait for the calibration complete notification.
744 */
745 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC
746 MVM_UCODE_CALIB_TIMEOUT);
747 if (!ret)
748 goto out;
31b8b343 749
00e0c6c8 750 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 751 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC
752 ret = 0;
753 } else {
754 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
755 ret);
31b8b343 756 }
00e0c6c8 757
8ca151b5
JB
758 goto out;
759
00e0c6c8 760remove_notif:
8ca151b5
JB
761 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
762out:
b3500b47 763 mvm->rfkill_safe_init_done = false;
a4082843 764 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB
765 /* we want to debug INIT and we have no NVM - fake */
766 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
767 sizeof(struct ieee80211_channel) +
768 sizeof(struct ieee80211_rate),
769 GFP_KERNEL);
770 if (!mvm->nvm_data)
771 return -ENOMEM;
8ca151b5
JB
772 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
773 mvm->nvm_data->bands[0].n_channels = 1;
774 mvm->nvm_data->bands[0].n_bitrates = 1;
775 mvm->nvm_data->bands[0].bitrates =
3827cb59 776 (void *)((u8 *)mvm->nvm_data->channels + 1);
8ca151b5
JB
777 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
778 }
779
780 return ret;
781}
782
84bfffa9
EG
783static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
784{
785 struct iwl_ltr_config_cmd cmd = {
786 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
787 };
788
789 if (!mvm->trans->ltr_enabled)
790 return 0;
791
84bfffa9
EG
792 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
793 sizeof(cmd), &cmd);
794}
795
c386dacb 796#ifdef CONFIG_ACPI
42ce76d6 797int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 798{
971cbe50 799 u32 cmd_id = REDUCE_TX_POWER_CMD;
216cdfb5
LC
800 struct iwl_dev_tx_power_cmd cmd = {
801 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 802 };
9c08cef8 803 __le16 *per_chain;
1edd56e6 804 int ret;
39c1a972 805 u16 len = 0;
fbb7957d 806 u32 n_subbands;
971cbe50 807 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 808 IWL_FW_CMD_VER_UNKNOWN);
fbb7957d
LC
809
810 if (cmd_ver == 6) {
811 len = sizeof(cmd.v6);
812 n_subbands = IWL_NUM_SUB_BANDS_V2;
813 per_chain = cmd.v6.per_chain[0][0];
814 } else if (fw_has_api(&mvm->fw->ucode_capa,
815 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 816 len = sizeof(cmd.v5);
e12cfc7b 817 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
818 per_chain = cmd.v5.per_chain[0][0];
819 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 820 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 821 len = sizeof(cmd.v4);
e12cfc7b 822 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
823 per_chain = cmd.v4.per_chain[0][0];
824 } else {
216cdfb5 825 len = sizeof(cmd.v3);
e12cfc7b 826 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
827 per_chain = cmd.v3.per_chain[0][0];
828 }
55bfa4b9 829
216cdfb5
LC
830 /* all structs have the same common part, add it */
831 len += sizeof(cmd.common);
da2830ac 832
dac7171c
LC
833 ret = iwl_sar_select_profile(&mvm->fwrt, per_chain,
834 IWL_NUM_CHAIN_TABLES,
fbb7957d 835 n_subbands, prof_a, prof_b);
1edd56e6
LC
836
837 /* return on error or if the profile is disabled (positive number) */
838 if (ret)
839 return ret;
840
6d19a5eb
EG
841 iwl_mei_set_power_limit(per_chain);
842
42ce76d6 843 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
971cbe50 844 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
42ce76d6
LC
845}
846
7fe90e0e
HD
847int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
848{
dd2a1256 849 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 850 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 851 u16 len;
39c1a972 852 int ret;
c8611331
JB
853 struct iwl_host_cmd cmd = {
854 .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD),
855 .flags = CMD_WANT_SKB,
856 .data = { &geo_tx_cmd },
857 };
971cbe50 858 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
e80bfd11 859 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 860
dd2a1256
LC
861 /* the ops field is at the same spot for all versions, so set in v1 */
862 geo_tx_cmd.v1.ops =
863 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
864
97f8a3d1
AB
865 if (cmd_ver == 5)
866 len = sizeof(geo_tx_cmd.v5);
867 else if (cmd_ver == 4)
868 len = sizeof(geo_tx_cmd.v4);
869 else if (cmd_ver == 3)
0ea788ed
LC
870 len = sizeof(geo_tx_cmd.v3);
871 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
872 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC
873 len = sizeof(geo_tx_cmd.v2);
874 else
875 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 876
39c1a972
IZ
877 if (!iwl_sar_geo_support(&mvm->fwrt))
878 return -EOPNOTSUPP;
879
c8611331 880 cmd.len[0] = len;
7fe90e0e
HD
881
882 ret = iwl_mvm_send_cmd(mvm, &cmd);
883 if (ret) {
884 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
885 return ret;
886 }
f604324e
LC
887
888 resp = (void *)cmd.resp_pkt->data;
889 ret = le32_to_cpu(resp->profile_idx);
890
97f8a3d1 891 if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES_REV3))
f604324e
LC
892 ret = -EIO;
893
7fe90e0e
HD
894 iwl_free_resp(&cmd);
895 return ret;
896}
897
a6bff3cb
HD
898static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
899{
971cbe50 900 u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD);
dd2a1256 901 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 902 u16 len;
45acebf8 903 u32 n_bands;
97f8a3d1 904 u32 n_profiles;
ac9952f6 905 u32 sk = 0;
0433ae55 906 int ret;
971cbe50 907 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 908 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 909
45acebf8
NG
910 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
911 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
912 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
97f8a3d1
AB
913 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) ||
914 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) !=
915 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) ||
916 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) !=
917 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops));
918
dd2a1256
LC
919 /* the ops field is at the same spot for all versions, so set in v1 */
920 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 921
97f8a3d1
AB
922 if (cmd_ver == 5) {
923 len = sizeof(cmd.v5);
924 n_bands = ARRAY_SIZE(cmd.v5.table[0]);
925 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
926 } else if (cmd_ver == 4) {
927 len = sizeof(cmd.v4);
928 n_bands = ARRAY_SIZE(cmd.v4.table[0]);
929 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
930 } else if (cmd_ver == 3) {
0ea788ed 931 len = sizeof(cmd.v3);
45acebf8 932 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
97f8a3d1 933 n_profiles = ACPI_NUM_GEO_PROFILES;
0ea788ed
LC
934 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
935 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 936 len = sizeof(cmd.v2);
45acebf8 937 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
97f8a3d1 938 n_profiles = ACPI_NUM_GEO_PROFILES;
39c1a972 939 } else {
dd2a1256 940 len = sizeof(cmd.v1);
45acebf8 941 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
97f8a3d1 942 n_profiles = ACPI_NUM_GEO_PROFILES;
0c3d7282
HD
943 }
944
45acebf8
NG
945 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
946 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
947 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
97f8a3d1
AB
948 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) ||
949 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) !=
950 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) ||
951 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) !=
952 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table));
45acebf8 953 /* the table is at the same position for all versions, so set use v1 */
97f8a3d1
AB
954 ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0],
955 n_bands, n_profiles);
45acebf8
NG
956
957 /*
958 * It is a valid scenario to not support SAR, or miss wgds table,
959 * but in that case there is no need to send the command.
960 */
961 if (ret)
962 return 0;
963
ac9952f6
LC
964 /* Only set to South Korea if the table revision is 1 */
965 if (mvm->fwrt.geo_rev == 1)
966 sk = 1;
967
28db1862 968 /*
ac9952f6
LC
969 * Set the table_revision to South Korea (1) or not (0). The
970 * element name is misleading, as it doesn't contain the table
971 * revision number, but whether the South Korea variation
972 * should be used.
28db1862
LC
973 * This must be done after calling iwl_sar_geo_init().
974 */
97f8a3d1 975 if (cmd_ver == 5)
ac9952f6 976 cmd.v5.table_revision = cpu_to_le32(sk);
97f8a3d1 977 else if (cmd_ver == 4)
ac9952f6 978 cmd.v4.table_revision = cpu_to_le32(sk);
97f8a3d1 979 else if (cmd_ver == 3)
ac9952f6 980 cmd.v3.table_revision = cpu_to_le32(sk);
28db1862
LC
981 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
982 IWL_UCODE_TLV_API_SAR_TABLE_VER))
ac9952f6 983 cmd.v2.table_revision = cpu_to_le32(sk);
28db1862 984
971cbe50 985 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
a6bff3cb
HD
986}
987
6ce1e5c0
GA
988static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm)
989{
e12cfc7b 990 union acpi_object *wifi_pkg, *data, *flags;
f2134f66 991 int i, j, ret, tbl_rev, num_sub_bands;
6ce1e5c0
GA
992 int idx = 2;
993
8bdc52b9 994 mvm->fwrt.ppag_flags = 0;
e12cfc7b 995
6ce1e5c0
GA
996 data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD);
997 if (IS_ERR(data))
998 return PTR_ERR(data);
999
e12cfc7b 1000 /* try to read ppag table rev 2 or 1 (both have the same data size) */
6ce1e5c0 1001 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
f2134f66
GA
1002 ACPI_PPAG_WIFI_DATA_SIZE_V2, &tbl_rev);
1003 if (!IS_ERR(wifi_pkg)) {
e12cfc7b
MK
1004 if (tbl_rev == 1 || tbl_rev == 2) {
1005 num_sub_bands = IWL_NUM_SUB_BANDS_V2;
e12cfc7b
MK
1006 IWL_DEBUG_RADIO(mvm,
1007 "Reading PPAG table v2 (tbl_rev=%d)\n",
1008 tbl_rev);
1009 goto read_table;
1010 } else {
f2134f66
GA
1011 ret = -EINVAL;
1012 goto out_free;
1013 }
6ce1e5c0
GA
1014 }
1015
f2134f66
GA
1016 /* try to read ppag table revision 0 */
1017 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
e12cfc7b 1018 ACPI_PPAG_WIFI_DATA_SIZE_V1, &tbl_rev);
f2134f66
GA
1019 if (!IS_ERR(wifi_pkg)) {
1020 if (tbl_rev != 0) {
1021 ret = -EINVAL;
1022 goto out_free;
1023 }
e12cfc7b 1024 num_sub_bands = IWL_NUM_SUB_BANDS_V1;
f2134f66
GA
1025 IWL_DEBUG_RADIO(mvm, "Reading PPAG table v1 (tbl_rev=0)\n");
1026 goto read_table;
3ed83da3 1027 }
f2134f66
GA
1028 ret = PTR_ERR(wifi_pkg);
1029 goto out_free;
3ed83da3 1030
f2134f66 1031read_table:
8bdc52b9 1032 mvm->fwrt.ppag_ver = tbl_rev;
e12cfc7b
MK
1033 flags = &wifi_pkg->package.elements[1];
1034
1035 if (flags->type != ACPI_TYPE_INTEGER) {
6ce1e5c0
GA
1036 ret = -EINVAL;
1037 goto out_free;
1038 }
1039
8bdc52b9 1040 mvm->fwrt.ppag_flags = flags->integer.value & IWL_PPAG_MASK;
e12cfc7b 1041
8bdc52b9 1042 if (!mvm->fwrt.ppag_flags) {
6ce1e5c0
GA
1043 ret = 0;
1044 goto out_free;
1045 }
1046
1047 /*
1048 * read, verify gain values and save them into the PPAG table.
1049 * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the
1050 * following sub-bands to High-Band (5GHz).
1051 */
f2134f66
GA
1052 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
1053 for (j = 0; j < num_sub_bands; j++) {
6ce1e5c0
GA
1054 union acpi_object *ent;
1055
1056 ent = &wifi_pkg->package.elements[idx++];
5a684245 1057 if (ent->type != ACPI_TYPE_INTEGER) {
6ce1e5c0
GA
1058 ret = -EINVAL;
1059 goto out_free;
1060 }
5a684245 1061
8bdc52b9 1062 mvm->fwrt.ppag_chains[i].subbands[j] = ent->integer.value;
5a684245
LC
1063
1064 if ((j == 0 &&
8bdc52b9
MK
1065 (mvm->fwrt.ppag_chains[i].subbands[j] > ACPI_PPAG_MAX_LB ||
1066 mvm->fwrt.ppag_chains[i].subbands[j] < ACPI_PPAG_MIN_LB)) ||
5a684245 1067 (j != 0 &&
8bdc52b9
MK
1068 (mvm->fwrt.ppag_chains[i].subbands[j] > ACPI_PPAG_MAX_HB ||
1069 mvm->fwrt.ppag_chains[i].subbands[j] < ACPI_PPAG_MIN_HB))) {
1070 mvm->fwrt.ppag_flags = 0;
5a684245
LC
1071 ret = -EINVAL;
1072 goto out_free;
1073 }
6ce1e5c0
GA
1074 }
1075 }
e12cfc7b 1076
6ce1e5c0
GA
1077 ret = 0;
1078out_free:
1079 kfree(data);
1080 return ret;
1081}
1082
1083int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1084{
8bdc52b9 1085 union iwl_ppag_table_cmd cmd;
f2134f66
GA
1086 u8 cmd_ver;
1087 int i, j, ret, num_sub_bands, cmd_size;
f2134f66 1088 s8 *gain;
6ce1e5c0
GA
1089
1090 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
1091 IWL_DEBUG_RADIO(mvm,
1092 "PPAG capability not supported by FW, command not sent.\n");
1093 return 0;
1094 }
8bdc52b9 1095 if (!mvm->fwrt.ppag_flags) {
f2134f66 1096 IWL_DEBUG_RADIO(mvm, "PPAG not enabled, command not sent.\n");
160bab43
GA
1097 return 0;
1098 }
1099
8bdc52b9
MK
1100 /* The 'flags' field is the same in v1 and in v2 so we can just
1101 * use v1 to access it.
1102 */
1103 cmd.v1.flags = cpu_to_le32(mvm->fwrt.ppag_flags);
971cbe50
JB
1104 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw,
1105 WIDE_ID(PHY_OPS_GROUP, PER_PLATFORM_ANT_GAIN_CMD),
e80bfd11 1106 IWL_FW_CMD_VER_UNKNOWN);
f2134f66 1107 if (cmd_ver == 1) {
e12cfc7b 1108 num_sub_bands = IWL_NUM_SUB_BANDS_V1;
8bdc52b9
MK
1109 gain = cmd.v1.gain[0];
1110 cmd_size = sizeof(cmd.v1);
e12cfc7b 1111 if (mvm->fwrt.ppag_ver == 1 || mvm->fwrt.ppag_ver == 2) {
f2134f66 1112 IWL_DEBUG_RADIO(mvm,
e12cfc7b
MK
1113 "PPAG table rev is %d but FW supports v1, sending truncated table\n",
1114 mvm->fwrt.ppag_ver);
8bdc52b9 1115 cmd.v1.flags &= cpu_to_le32(IWL_PPAG_ETSI_MASK);
f2134f66 1116 }
e12cfc7b 1117 } else if (cmd_ver == 2 || cmd_ver == 3) {
f2134f66 1118 num_sub_bands = IWL_NUM_SUB_BANDS_V2;
8bdc52b9
MK
1119 gain = cmd.v2.gain[0];
1120 cmd_size = sizeof(cmd.v2);
e12cfc7b 1121 if (mvm->fwrt.ppag_ver == 0) {
f2134f66
GA
1122 IWL_DEBUG_RADIO(mvm,
1123 "PPAG table is v1 but FW supports v2, sending padded table\n");
e12cfc7b
MK
1124 } else if (cmd_ver == 2 && mvm->fwrt.ppag_ver == 2) {
1125 IWL_DEBUG_RADIO(mvm,
1126 "PPAG table is v3 but FW supports v2, sending partial bitmap.\n");
8bdc52b9 1127 cmd.v1.flags &= cpu_to_le32(IWL_PPAG_ETSI_MASK);
f2134f66
GA
1128 }
1129 } else {
1130 IWL_DEBUG_RADIO(mvm, "Unsupported PPAG command version\n");
1131 return 0;
1132 }
6ce1e5c0 1133
f2134f66
GA
1134 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
1135 for (j = 0; j < num_sub_bands; j++) {
8bdc52b9
MK
1136 gain[i * num_sub_bands + j] =
1137 mvm->fwrt.ppag_chains[i].subbands[j];
6ce1e5c0
GA
1138 IWL_DEBUG_RADIO(mvm,
1139 "PPAG table: chain[%d] band[%d]: gain = %d\n",
f2134f66 1140 i, j, gain[i * num_sub_bands + j]);
6ce1e5c0
GA
1141 }
1142 }
f2134f66 1143 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA
1144 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1145 PER_PLATFORM_ANT_GAIN_CMD),
8bdc52b9 1146 0, cmd_size, &cmd);
6ce1e5c0
GA
1147 if (ret < 0)
1148 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1149 ret);
1150
1151 return ret;
1152}
1153
a2ac0f48 1154static const struct dmi_system_id dmi_ppag_approved_list[] = {
ca176edd
LC
1155 { .ident = "HP",
1156 .matches = {
1157 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1158 },
1159 },
dd158ed6
LC
1160 { .ident = "SAMSUNG",
1161 .matches = {
1162 DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
1163 },
1164 },
4a76553c
LC
1165 { .ident = "MSFT",
1166 .matches = {
1167 DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
1168 },
1169 },
a7abc1ea
LC
1170 { .ident = "ASUS",
1171 .matches = {
1172 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek COMPUTER INC."),
1173 },
1174 },
a22549f1 1175 {}
a2ac0f48
LC
1176};
1177
6ce1e5c0
GA
1178static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1179{
78a19d52 1180 /* no need to read the table, done in INIT stage */
a2ac0f48
LC
1181 if (!dmi_check_system(dmi_ppag_approved_list)) {
1182 IWL_DEBUG_RADIO(mvm,
1183 "System vendor '%s' is not in the approved list, disabling PPAG.\n",
1184 dmi_get_system_info(DMI_SYS_VENDOR));
8bdc52b9 1185 mvm->fwrt.ppag_flags = 0;
a2ac0f48
LC
1186 return 0;
1187 }
1188
6ce1e5c0
GA
1189 return iwl_mvm_ppag_send_cmd(mvm);
1190}
1191
2856f623
AB
1192static const struct dmi_system_id dmi_tas_approved_list[] = {
1193 { .ident = "HP",
1194 .matches = {
1195 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1196 },
1197 },
1198 { .ident = "SAMSUNG",
1199 .matches = {
1200 DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
1201 },
1202 },
1203 { .ident = "LENOVO",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "Lenovo"),
1206 },
1207 },
1208 { .ident = "DELL",
1209 .matches = {
1210 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1211 },
1212 },
1213
1214 /* keep last */
1215 {}
1216};
1217
c3f40c3e
MK
1218static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc)
1219{
1220 int i;
1221 u32 size = le32_to_cpu(*le_size);
1222
1223 /* Verify that there is room for another country */
1224 if (size >= IWL_TAS_BLOCK_LIST_MAX)
1225 return false;
1226
1227 for (i = 0; i < size; i++) {
1228 if (list[i] == cpu_to_le32(mcc))
1229 return true;
1230 }
1231
1232 list[size++] = cpu_to_le32(mcc);
1233 *le_size = cpu_to_le32(size);
1234 return true;
1235}
1236
28dd7ccd
MG
1237static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1238{
971cbe50 1239 u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG);
28dd7ccd 1240 int ret;
6da7ba3a
AB
1241 union iwl_tas_config_cmd cmd = {};
1242 int cmd_size, fw_ver;
28dd7ccd 1243
6da7ba3a 1244 BUILD_BUG_ON(ARRAY_SIZE(cmd.v3.block_list_array) <
28dd7ccd
MG
1245 APCI_WTAS_BLACK_LIST_MAX);
1246
1247 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1248 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1249 return;
1250 }
1251
971cbe50
JB
1252 fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
1253 IWL_FW_CMD_VER_UNKNOWN);
6da7ba3a
AB
1254
1255 ret = iwl_acpi_get_tas(&mvm->fwrt, &cmd, fw_ver);
28dd7ccd
MG
1256 if (ret < 0) {
1257 IWL_DEBUG_RADIO(mvm,
1258 "TAS table invalid or unavailable. (%d)\n",
1259 ret);
1260 return;
1261 }
1262
7c530588 1263 if (ret == 0)
28dd7ccd
MG
1264 return;
1265
c3f40c3e
MK
1266 if (!dmi_check_system(dmi_tas_approved_list)) {
1267 IWL_DEBUG_RADIO(mvm,
1268 "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
1269 dmi_get_system_info(DMI_SYS_VENDOR));
6da7ba3a
AB
1270 if ((!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1271 &cmd.v4.block_list_size,
1272 IWL_TAS_US_MCC)) ||
1273 (!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1274 &cmd.v4.block_list_size,
1275 IWL_TAS_CANADA_MCC))) {
c3f40c3e
MK
1276 IWL_DEBUG_RADIO(mvm,
1277 "Unable to add US/Canada to TAS block list, disabling TAS\n");
1278 return;
1279 }
1280 }
1281
6da7ba3a
AB
1282 /* v4 is the same size as v3, so no need to differentiate here */
1283 cmd_size = fw_ver < 3 ?
7c530588
MK
1284 sizeof(struct iwl_tas_config_cmd_v2) :
1285 sizeof(struct iwl_tas_config_cmd_v3);
28dd7ccd 1286
971cbe50 1287 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd);
28dd7ccd
MG
1288 if (ret < 0)
1289 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1290}
f5b1cb2e 1291
4e8fe214
GG
1292static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1293{
1294 u8 value;
45fe1b6b 1295 int ret = iwl_acpi_get_dsm_u8(mvm->fwrt.dev, 0, DSM_RFI_FUNC_ENABLE,
4e8fe214
GG
1296 &iwl_rfi_guid, &value);
1297
1298 if (ret < 0) {
1299 IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
1300
1301 } else if (value >= DSM_VALUE_RFI_MAX) {
1302 IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n",
1303 value);
1304
1305 } else if (value == DSM_VALUE_RFI_ENABLE) {
1306 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
1307 return DSM_VALUE_RFI_ENABLE;
1308 }
1309
1310 IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n");
1311
1312 /* default behaviour is disabled */
1313 return DSM_VALUE_RFI_DISABLE;
1314}
1315
f5b1cb2e
GA
1316static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1317{
7119f02b
MK
1318 int ret;
1319 u32 value;
8f323d06 1320 struct iwl_lari_config_change_cmd_v6 cmd = {};
f5b1cb2e 1321
f21afaba 1322 cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt);
d2bfda8a 1323
45fe1b6b 1324 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_11AX_ENABLEMENT,
7119f02b
MK
1325 &iwl_guid, &value);
1326 if (!ret)
1327 cmd.oem_11ax_allow_bitmap = cpu_to_le32(value);
f5b1cb2e 1328
45fe1b6b 1329 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
54b4fda5
AN
1330 DSM_FUNC_ENABLE_UNII4_CHAN,
1331 &iwl_guid, &value);
1332 if (!ret)
1333 cmd.oem_unii4_allow_bitmap = cpu_to_le32(value);
1334
45fe1b6b 1335 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1f578d4f
MK
1336 DSM_FUNC_ACTIVATE_CHANNEL,
1337 &iwl_guid, &value);
1338 if (!ret)
1339 cmd.chan_state_active_bitmap = cpu_to_le32(value);
1340
698b166e
LC
1341 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1342 DSM_FUNC_ENABLE_6E,
1343 &iwl_guid, &value);
1344 if (!ret)
1345 cmd.oem_uhb_allow_bitmap = cpu_to_le32(value);
1346
8f323d06
AB
1347 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1348 DSM_FUNC_FORCE_DISABLE_CHANNELS,
1349 &iwl_guid, &value);
1350 if (!ret)
1351 cmd.force_disable_channels_bitmap = cpu_to_le32(value);
1352
54b4fda5 1353 if (cmd.config_bitmap ||
698b166e 1354 cmd.oem_uhb_allow_bitmap ||
54b4fda5 1355 cmd.oem_11ax_allow_bitmap ||
1f578d4f 1356 cmd.oem_unii4_allow_bitmap ||
8f323d06
AB
1357 cmd.chan_state_active_bitmap ||
1358 cmd.force_disable_channels_bitmap) {
3c21990b
MK
1359 size_t cmd_size;
1360 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw,
971cbe50
JB
1361 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1362 LARI_CONFIG_CHANGE),
1363 1);
8f323d06
AB
1364 switch (cmd_ver) {
1365 case 6:
1366 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v6);
1367 break;
1368 case 5:
1f578d4f 1369 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v5);
8f323d06
AB
1370 break;
1371 case 4:
54b4fda5 1372 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4);
8f323d06
AB
1373 break;
1374 case 3:
3c21990b 1375 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3);
8f323d06
AB
1376 break;
1377 case 2:
3c21990b 1378 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2);
8f323d06
AB
1379 break;
1380 default:
3c21990b 1381 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1);
8f323d06
AB
1382 break;
1383 }
3c21990b 1384
3ce88247 1385 IWL_DEBUG_RADIO(mvm,
7119f02b
MK
1386 "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n",
1387 le32_to_cpu(cmd.config_bitmap),
1388 le32_to_cpu(cmd.oem_11ax_allow_bitmap));
54b4fda5 1389 IWL_DEBUG_RADIO(mvm,
1f578d4f 1390 "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, chan_state_active_bitmap=0x%x, cmd_ver=%d\n",
54b4fda5 1391 le32_to_cpu(cmd.oem_unii4_allow_bitmap),
1f578d4f 1392 le32_to_cpu(cmd.chan_state_active_bitmap),
54b4fda5 1393 cmd_ver);
698b166e 1394 IWL_DEBUG_RADIO(mvm,
8f323d06
AB
1395 "sending LARI_CONFIG_CHANGE, oem_uhb_allow_bitmap=0x%x, force_disable_channels_bitmap=0x%x\n",
1396 le32_to_cpu(cmd.oem_uhb_allow_bitmap),
1397 le32_to_cpu(cmd.force_disable_channels_bitmap));
7119f02b
MK
1398 ret = iwl_mvm_send_cmd_pdu(mvm,
1399 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1400 LARI_CONFIG_CHANGE),
1401 0, cmd_size, &cmd);
1402 if (ret < 0)
f5b1cb2e
GA
1403 IWL_DEBUG_RADIO(mvm,
1404 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
7119f02b 1405 ret);
f5b1cb2e
GA
1406 }
1407}
78a19d52
MK
1408
1409void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1410{
1411 int ret;
1412
1413 /* read PPAG table */
1414 ret = iwl_mvm_get_ppag_table(mvm);
1415 if (ret < 0) {
1416 IWL_DEBUG_RADIO(mvm,
1417 "PPAG BIOS table invalid or unavailable. (%d)\n",
1418 ret);
1419 }
1420
1421 /* read SAR tables */
1422 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
1423 if (ret < 0) {
1424 IWL_DEBUG_RADIO(mvm,
1425 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1426 ret);
1427 /*
1428 * If not available, don't fail and don't bother with EWRD and
1429 * WGDS */
1430
1431 if (!iwl_sar_get_wgds_table(&mvm->fwrt)) {
1432 /*
1433 * If basic SAR is not available, we check for WGDS,
1434 * which should *not* be available either. If it is
1435 * available, issue an error, because we can't use SAR
1436 * Geo without basic SAR.
1437 */
1438 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1439 }
1440
1441 } else {
1442 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
1443 /* if EWRD is not available, we can still use
1444 * WRDS, so don't fail */
1445 if (ret < 0)
1446 IWL_DEBUG_RADIO(mvm,
1447 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1448 ret);
1449
1450 /* read geo SAR table */
1451 if (iwl_sar_geo_support(&mvm->fwrt)) {
1452 ret = iwl_sar_get_wgds_table(&mvm->fwrt);
1453 if (ret < 0)
1454 IWL_DEBUG_RADIO(mvm,
1455 "Geo SAR BIOS table invalid or unavailable. (%d)\n",
1456 ret);
1457 /* we don't fail if the table is not available */
1458 }
1459 }
1460}
69964905 1461#else /* CONFIG_ACPI */
69964905 1462
39c1a972
IZ
1463inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1464 int prof_a, int prof_b)
69964905 1465{
78a19d52 1466 return 1;
69964905 1467}
a6bff3cb 1468
39c1a972 1469inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC
1470{
1471 return -ENOENT;
1472}
1473
a6bff3cb
HD
1474static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1475{
1476 return 0;
1477}
18f1755d 1478
6ce1e5c0
GA
1479int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1480{
1481 return -ENOENT;
1482}
1483
1484static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1485{
7937fd32 1486 return 0;
6ce1e5c0 1487}
28dd7ccd
MG
1488
1489static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1490{
1491}
f5b1cb2e
GA
1492
1493static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1494{
1495}
4e8fe214
GG
1496
1497static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1498{
1499 return DSM_VALUE_RFI_DISABLE;
1500}
78a19d52
MK
1501
1502void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1503{
1504}
c593d2fa 1505
69964905
LC
1506#endif /* CONFIG_ACPI */
1507
f130bb75
MG
1508void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1509{
1510 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1511 int ret;
1512 u32 resp;
1513
1514 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1515 .flags = cpu_to_le32(flags),
1516 .buf_size = 0,
1517 };
1518 struct iwl_host_cmd host_cmd = {
1519 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1520 .flags = CMD_WANT_SKB,
1521 .data = {&recovery_cmd, },
1522 .len = {sizeof(recovery_cmd), },
1523 };
1524
1525 /* no error log was defined in TLV */
1526 if (!error_log_size)
1527 return;
1528
1529 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1530 /* no buf was allocated while HW reset */
1531 if (!mvm->error_recovery_buf)
1532 return;
1533
1534 host_cmd.data[1] = mvm->error_recovery_buf;
1535 host_cmd.len[1] = error_log_size;
1536 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1537 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1538 }
1539
1540 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1541 kfree(mvm->error_recovery_buf);
1542 mvm->error_recovery_buf = NULL;
1543
1544 if (ret) {
1545 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1546 return;
1547 }
1548
1549 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1550 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1551 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1552 if (resp)
1553 IWL_ERR(mvm,
1554 "Failed to send recovery cmd blob was invalid %d\n",
1555 resp);
1556 }
1557}
1558
42ce76d6
LC
1559static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1560{
1edd56e6 1561 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC
1562}
1563
1f370650 1564static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1565{
1f370650 1566 int ret;
8ca151b5 1567
7d6222e2 1568 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1569 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1570
3b25f1af 1571 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1572
f2082a53 1573 if (ret) {
8d193ca2 1574 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK
1575
1576 if (iwlmvm_mod_params.init_dbg)
1577 return 0;
1f370650 1578 return ret;
8d193ca2 1579 }
8ca151b5 1580
203c83d3 1581 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG
1582 iwl_trans_stop_device(mvm->trans);
1583 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1584 if (ret)
1f370650 1585 return ret;
8ca151b5 1586
94022562 1587 mvm->rfkill_safe_init_done = false;
8ca151b5 1588 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS
1589 if (ret)
1590 return ret;
1591
94022562
EG
1592 mvm->rfkill_safe_init_done = true;
1593
b108d8c7
SM
1594 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1595 NULL);
da2eb669 1596
702e975d 1597 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS
1598}
1599
1600int iwl_mvm_up(struct iwl_mvm *mvm)
1601{
1602 int ret, i;
1603 struct ieee80211_channel *chan;
1604 struct cfg80211_chan_def chandef;
dd36a507 1605 struct ieee80211_supported_band *sband = NULL;
1f370650
SS
1606
1607 lockdep_assert_held(&mvm->mutex);
1608
1609 ret = iwl_trans_start_hw(mvm->trans);
1610 if (ret)
1611 return ret;
1612
1613 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB
1614 if (ret) {
1615 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
72d3c7bb
JB
1616 if (ret != -ERFKILL)
1617 iwl_fw_dbg_error_collect(&mvm->fwrt,
1618 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB
1619 goto error;
1620 }
1621
d0b813fc 1622 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1623
1f3b0ff8
LE
1624 ret = iwl_mvm_sf_update(mvm, NULL, false);
1625 if (ret)
1626 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1627
a1af4c48 1628 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS
1629 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1630 /* if we have a destination, assume EARLY START */
1631 if (mvm->fw->dbg.dest_tlv)
1632 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1633 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1634 }
6a951267 1635
a0544272 1636 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1637 if (ret)
1638 goto error;
1639
7d6222e2
JB
1640 if (!iwl_mvm_has_unified_ucode(mvm)) {
1641 /* Send phy db control command and then phy db calibration */
1f370650
SS
1642 ret = iwl_send_phy_db_data(mvm->phy_db);
1643 if (ret)
1644 goto error;
1f370650 1645 }
8ca151b5 1646
bb99ff9b
LC
1647 ret = iwl_send_phy_cfg_cmd(mvm);
1648 if (ret)
1649 goto error;
1650
b3de3ef4
EG
1651 ret = iwl_mvm_send_bt_init_conf(mvm);
1652 if (ret)
1653 goto error;
1654
cceb4507
SM
1655 if (fw_has_capa(&mvm->fw->ucode_capa,
1656 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1657 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM
1658 if (ret)
1659 goto error;
1660 }
1661
43413a97 1662 /* Init RSS configuration */
9cd243f2
MG
1663 ret = iwl_configure_rxq(&mvm->fwrt);
1664 if (ret)
1665 goto error;
8edbfaa1
SS
1666
1667 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS
1668 ret = iwl_send_rss_cfg_cmd(mvm);
1669 if (ret) {
1670 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1671 ret);
1672 goto error;
1673 }
1674 }
1675
8ca151b5 1676 /* init the fw <-> mac80211 STA mapping */
be9ae34e 1677 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++)
8ca151b5
JB
1678 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1679
0ae98812 1680 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1681
b2b7875b
JB
1682 /* reset quota debouncing buffer - 0xff will yield invalid data */
1683 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1684
79660869
IL
1685 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1686 ret = iwl_mvm_send_dqa_cmd(mvm);
1687 if (ret)
1688 goto error;
1689 }
97d5be7e 1690
2c2c3647
NE
1691 /*
1692 * Add auxiliary station for scanning.
1693 * Newer versions of this command implies that the fw uses
1694 * internal aux station for all aux activities that don't
1695 * requires a dedicated data queue.
1696 */
971cbe50 1697 if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
2c2c3647
NE
1698 /*
1699 * In old version the aux station uses mac id like other
1700 * station and not lmac id
1701 */
1702 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1703 if (ret)
1704 goto error;
1705 }
8ca151b5 1706
53a9d61e 1707 /* Add all the PHY contexts */
dd36a507
TM
1708 i = 0;
1709 while (!sband && i < NUM_NL80211_BANDS)
1710 sband = mvm->hw->wiphy->bands[i++];
1711
583d1833
DC
1712 if (WARN_ON_ONCE(!sband)) {
1713 ret = -ENODEV;
dd36a507 1714 goto error;
583d1833 1715 }
dd36a507
TM
1716
1717 chan = &sband->channels[0];
1718
53a9d61e
IP
1719 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1720 for (i = 0; i < NUM_PHY_CTX; i++) {
1721 /*
1722 * The channel used here isn't relevant as it's
1723 * going to be overwritten in the other flows.
1724 * For now use the first channel we have.
1725 */
1726 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1727 &chandef, 1, 1);
1728 if (ret)
1729 goto error;
1730 }
8ca151b5 1731
c221daf2
CRI
1732 if (iwl_mvm_is_tt_in_fw(mvm)) {
1733 /* in order to give the responsibility of ct-kill and
1734 * TX backoff to FW we need to send empty temperature reporting
1735 * cmd during init time
1736 */
1737 iwl_mvm_send_temp_report_ths_cmd(mvm);
1738 } else {
1739 /* Initialize tx backoffs to the minimal possible */
1740 iwl_mvm_tt_tx_backoff(mvm, 0);
1741 }
5c89e7bc 1742
242d9c8b 1743#ifdef CONFIG_THERMAL
5c89e7bc 1744 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI
1745
1746 /*
1747 * In case there is no budget from BIOS / Platform NVM the default
1748 * budget should be 2000mW (cooling state 0).
1749 */
1750 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI
1751 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1752 mvm->cooling_dev.cur_state);
75cfe338
LC
1753 if (ret)
1754 goto error;
1755 }
c221daf2 1756#endif
0c0e2c71 1757
aa43ae12
AM
1758 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1759 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1760
c1cb92fc 1761 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB
1762 if (ret)
1763 goto error;
1764
f5b1cb2e 1765 iwl_mvm_lari_cfg(mvm);
35af15d1
AN
1766 /*
1767 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1768 * anyway, so don't init MCC.
1769 */
1770 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1771 ret = iwl_mvm_init_mcc(mvm);
1772 if (ret)
1773 goto error;
1774 }
90d4f7db 1775
859d914c 1776 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1777 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1778 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS
1779 ret = iwl_mvm_config_scan(mvm);
1780 if (ret)
1781 goto error;
1782 }
1783
f130bb75
MG
1784 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1785 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
1786
48e775e6
HD
1787 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1788 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1789
6ce1e5c0
GA
1790 ret = iwl_mvm_ppag_init(mvm);
1791 if (ret)
1792 goto error;
1793
da2830ac 1794 ret = iwl_mvm_sar_init(mvm);
78a19d52 1795 if (ret == 0)
5d041c46 1796 ret = iwl_mvm_sar_geo_init(mvm);
78a19d52 1797 else if (ret < 0)
a6bff3cb
HD
1798 goto error;
1799
c593d2fa
AB
1800 ret = iwl_mvm_sgom_init(mvm);
1801 if (ret)
1802 goto error;
1803
28dd7ccd 1804 iwl_mvm_tas_init(mvm);
7089ae63
JB
1805 iwl_mvm_leds_sync(mvm);
1806
b68bd2e3
IP
1807 iwl_mvm_ftm_initiator_smooth_config(mvm);
1808
4e8fe214
GG
1809 if (fw_has_capa(&mvm->fw->ucode_capa,
1810 IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) {
1811 if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE)
1812 iwl_rfi_send_config_cmd(mvm, NULL);
1813 }
1814
53a9d61e 1815 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB
1816 return 0;
1817 error:
f4744258 1818 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1819 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1820 return ret;
1821}
1822
1823int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1824{
1825 int ret, i;
1826
1827 lockdep_assert_held(&mvm->mutex);
1828
1829 ret = iwl_trans_start_hw(mvm->trans);
1830 if (ret)
1831 return ret;
1832
1833 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1834 if (ret) {
1835 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1836 goto error;
1837 }
1838
a0544272 1839 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1840 if (ret)
1841 goto error;
1842
1843 /* Send phy db control command and then phy db calibration*/
1844 ret = iwl_send_phy_db_data(mvm->phy_db);
1845 if (ret)
1846 goto error;
1847
1848 ret = iwl_send_phy_cfg_cmd(mvm);
1849 if (ret)
1850 goto error;
1851
1852 /* init the fw <-> mac80211 STA mapping */
be9ae34e 1853 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++)
8ca151b5
JB
1854 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1855
971cbe50 1856 if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
2c2c3647
NE
1857 /*
1858 * Add auxiliary station for scanning.
1859 * Newer versions of this command implies that the fw uses
1860 * internal aux station for all aux activities that don't
1861 * requires a dedicated data queue.
1862 * In old version the aux station uses mac id like other
1863 * station and not lmac id
1864 */
1865 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1866 if (ret)
1867 goto error;
1868 }
8ca151b5
JB
1869
1870 return 0;
1871 error:
fcb6b92a 1872 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1873 return ret;
1874}
1875
0416841d
JB
1876void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1877 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI
1878{
1879 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1880 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1881
0c8d0a47
GBA
1882 IWL_DEBUG_INFO(mvm,
1883 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1884 le32_to_cpu(mfuart_notif->installed_ver),
1885 le32_to_cpu(mfuart_notif->external_ver),
1886 le32_to_cpu(mfuart_notif->status),
1887 le32_to_cpu(mfuart_notif->duration));
1888
19f63c53
GBA
1889 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1890 IWL_DEBUG_INFO(mvm,
0c8d0a47 1891 "MFUART: image size: 0x%08x\n",
19f63c53 1892 le32_to_cpu(mfuart_notif->image_size));
30269c12 1893}