projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: mvm: correct rate_idx bounds-check
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8ca151b5
JB		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
43413a97 10 * Copyright(c) 2016 Intel Deutschland GmbH
8ca151b5
JB		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
8ca151b5
JB		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
8ca151b5
JB		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
51368bf7 35 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
8ca151b5
JB		 37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
66#include <net/mac80211.h>
854d773e 67#include <linux/netdevice.h>
da2830ac 68#include <linux/acpi.h>
8ca151b5
JB		 69
70#include "iwl-trans.h"
71#include "iwl-op-mode.h"
72#include "iwl-fw.h"
73#include "iwl-debug.h"
74#include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
75#include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
8c23f95c 76#include "iwl-prph.h"
8ca151b5
JB		 77#include "iwl-eeprom-parse.h"
78
79#include "mvm.h"
2f89a5d7 80#include "fw-dbg.h"
8ca151b5
JB		 81#include "iwl-phy-db.h"
82
83#define MVM_UCODE_ALIVE_TIMEOUT HZ
84#define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
85
86#define UCODE_VALID_OK cpu_to_le32(0x1)
87
8ca151b5
JB		 88struct iwl_mvm_alive_data {
89 bool valid;
90 u32 scd_base_addr;
91};
92
8ca151b5
JB		 93static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
94{
95 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
96 .valid = cpu_to_le32(valid_tx_ant),
97 };
98
33223542 99 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 100 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB		 101 sizeof(tx_ant_cmd), &tx_ant_cmd);
102}
103
43413a97
SS		 104static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
105{
106 int i;
107 struct iwl_rss_config_cmd cmd = {
108 .flags = cpu_to_le32(IWL_RSS_ENABLE),
109 .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP |
854d773e 110 IWL_RSS_HASH_TYPE_IPV4_UDP |
43413a97
SS		 111 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD |
112 IWL_RSS_HASH_TYPE_IPV6_TCP |
854d773e 113 IWL_RSS_HASH_TYPE_IPV6_UDP |
43413a97
SS		 114 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
115 };
116
f43495fd
SS		 117 if (mvm->trans->num_rx_queues == 1)
118 return 0;
119
854d773e 120 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 121 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS		 122 cmd.indirection_table[i] =
123 1 + (i % (mvm->trans->num_rx_queues - 1));
124 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS		 125
126 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
127}
128
97d5be7e
LK		 129static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
130{
131 struct iwl_dqa_enable_cmd dqa_cmd = {
132 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
133 };
134 u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
135 int ret;
136
137 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
138 if (ret)
139 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
140 else
141 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
142
143 return ret;
144}
145
905e36ae 146void iwl_free_fw_paging(struct iwl_mvm *mvm)
a6c4fb44
MG		 147{
148 int i;
149
150 if (!mvm->fw_paging_db[0].fw_paging_block)
151 return;
152
153 for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
3edbc7da
EG		 154 struct iwl_fw_paging *paging = &mvm->fw_paging_db[i];
155
156 if (!paging->fw_paging_block) {
a6c4fb44
MG		 157 IWL_DEBUG_FW(mvm,
158 "Paging: block %d already freed, continue to next page\n",
159 i);
160
161 continue;
162 }
3edbc7da
EG		 163 dma_unmap_page(mvm->trans->dev, paging->fw_paging_phys,
164 paging->fw_paging_size, DMA_BIDIRECTIONAL);
a6c4fb44 165
3edbc7da
EG		 166 __free_pages(paging->fw_paging_block,
167 get_order(paging->fw_paging_size));
168 paging->fw_paging_block = NULL;
a6c4fb44 169 }
e1120187 170 kfree(mvm->trans->paging_download_buf);
905e36ae 171 mvm->trans->paging_download_buf = NULL;
f742aaf3 172 mvm->trans->paging_db = NULL;
905e36ae 173
a6c4fb44
MG		 174 memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
175}
176
177static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
178{
179 int sec_idx, idx;
180 u32 offset = 0;
181
182 /*
183 * find where is the paging image start point:
184 * if CPU2 exist and it's in paging format, then the image looks like:
185 * CPU1 sections (2 or more)
186 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
187 * CPU2 sections (not paged)
188 * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
189 * non paged to CPU2 paging sec
190 * CPU2 paging CSS
191 * CPU2 paging image (including instruction and data)
192 */
193 for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
194 if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
195 sec_idx++;
196 break;
197 }
198 }
199
cd47a3d3
MG		 200 /*
201 * If paging is enabled there should be at least 2 more sections left
202 * (one for CSS and one for Paging data)
203 */
204 if (sec_idx >= ARRAY_SIZE(image->sec) - 1) {
205 IWL_ERR(mvm, "Paging: Missing CSS and/or paging sections\n");
a6c4fb44
MG		 206 iwl_free_fw_paging(mvm);
207 return -EINVAL;
208 }
209
210 /* copy the CSS block to the dram */
211 IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
212 sec_idx);
213
214 memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
215 image->sec[sec_idx].data,
216 mvm->fw_paging_db[0].fw_paging_size);
217
218 IWL_DEBUG_FW(mvm,
219 "Paging: copied %d CSS bytes to first block\n",
220 mvm->fw_paging_db[0].fw_paging_size);
221
222 sec_idx++;
223
224 /*
225 * copy the paging blocks to the dram
226 * loop index start from 1 since that CSS block already copied to dram
227 * and CSS index is 0.
228 * loop stop at num_of_paging_blk since that last block is not full.
229 */
230 for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
231 memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
232 image->sec[sec_idx].data + offset,
233 mvm->fw_paging_db[idx].fw_paging_size);
234
235 IWL_DEBUG_FW(mvm,
236 "Paging: copied %d paging bytes to block %d\n",
237 mvm->fw_paging_db[idx].fw_paging_size,
238 idx);
239
240 offset += mvm->fw_paging_db[idx].fw_paging_size;
241 }
242
243 /* copy the last paging block */
244 if (mvm->num_of_pages_in_last_blk > 0) {
245 memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
246 image->sec[sec_idx].data + offset,
247 FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
248
249 IWL_DEBUG_FW(mvm,
250 "Paging: copied %d pages in the last block %d\n",
251 mvm->num_of_pages_in_last_blk, idx);
252 }
253
254 return 0;
255}
256
257static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
258 const struct fw_img *image)
259{
260 struct page *block;
261 dma_addr_t phys = 0;
262 int blk_idx = 0;
263 int order, num_of_pages;
264 int dma_enabled;
265
266 if (mvm->fw_paging_db[0].fw_paging_block)
267 return 0;
268
269 dma_enabled = is_device_dma_capable(mvm->trans->dev);
270
271 /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
272 BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
273
274 num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
275 mvm->num_of_paging_blk = ((num_of_pages - 1) /
276 NUM_OF_PAGE_PER_GROUP) + 1;
277
278 mvm->num_of_pages_in_last_blk =
279 num_of_pages -
280 NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
281
282 IWL_DEBUG_FW(mvm,
283 "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
284 mvm->num_of_paging_blk,
285 mvm->num_of_pages_in_last_blk);
286
287 /* allocate block of 4Kbytes for paging CSS */
288 order = get_order(FW_PAGING_SIZE);
289 block = alloc_pages(GFP_KERNEL, order);
290 if (!block) {
291 /* free all the previous pages since we failed */
292 iwl_free_fw_paging(mvm);
293 return -ENOMEM;
294 }
295
296 mvm->fw_paging_db[blk_idx].fw_paging_block = block;
297 mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
298
299 if (dma_enabled) {
300 phys = dma_map_page(mvm->trans->dev, block, 0,
301 PAGE_SIZE << order, DMA_BIDIRECTIONAL);
302 if (dma_mapping_error(mvm->trans->dev, phys)) {
303 /*
304 * free the previous pages and the current one since
305 * we failed to map_page.
306 */
307 iwl_free_fw_paging(mvm);
308 return -ENOMEM;
309 }
310 mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
e1120187
MG		 311 } else {
312 mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG |
313 blk_idx << BLOCK_2_EXP_SIZE;
a6c4fb44
MG		 314 }
315
316 IWL_DEBUG_FW(mvm,
317 "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
318 order);
319
320 /*
321 * allocate blocks in dram.
322 * since that CSS allocated in fw_paging_db[0] loop start from index 1
323 */
324 for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
325 /* allocate block of PAGING_BLOCK_SIZE (32K) */
326 order = get_order(PAGING_BLOCK_SIZE);
327 block = alloc_pages(GFP_KERNEL, order);
328 if (!block) {
329 /* free all the previous pages since we failed */
330 iwl_free_fw_paging(mvm);
331 return -ENOMEM;
332 }
333
334 mvm->fw_paging_db[blk_idx].fw_paging_block = block;
335 mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
336
337 if (dma_enabled) {
338 phys = dma_map_page(mvm->trans->dev, block, 0,
339 PAGE_SIZE << order,
340 DMA_BIDIRECTIONAL);
341 if (dma_mapping_error(mvm->trans->dev, phys)) {
342 /*
343 * free the previous pages and the current one
344 * since we failed to map_page.
345 */
346 iwl_free_fw_paging(mvm);
347 return -ENOMEM;
348 }
349 mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
e1120187
MG		 350 } else {
351 mvm->fw_paging_db[blk_idx].fw_paging_phys =
352 PAGING_ADDR_SIG |
353 blk_idx << BLOCK_2_EXP_SIZE;
a6c4fb44
MG		 354 }
355
356 IWL_DEBUG_FW(mvm,
357 "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
358 order);
359 }
360
361 return 0;
362}
363
364static int iwl_save_fw_paging(struct iwl_mvm *mvm,
365 const struct fw_img *fw)
366{
367 int ret;
368
369 ret = iwl_alloc_fw_paging_mem(mvm, fw);
370 if (ret)
371 return ret;
372
373 return iwl_fill_paging_mem(mvm, fw);
374}
375
376/* send paging cmd to FW in case CPU2 has paging image */
377static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
378{
d975d720 379 struct iwl_fw_paging_cmd paging_cmd = {
a6c4fb44
MG		 380 .flags =
381 cpu_to_le32(PAGING_CMD_IS_SECURED |
382 PAGING_CMD_IS_ENABLED |
383 (mvm->num_of_pages_in_last_blk <<
384 PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
385 .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
386 .block_num = cpu_to_le32(mvm->num_of_paging_blk),
387 };
d975d720
SS		 388 int blk_idx, size = sizeof(paging_cmd);
389
390 /* A bit hard coded - but this is the old API and will be deprecated */
391 if (!iwl_mvm_has_new_tx_api(mvm))
392 size -= NUM_OF_FW_PAGING_BLOCKS * 4;
a6c4fb44
MG		 393
394 /* loop for for all paging blocks + CSS block */
395 for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
d975d720
SS		 396 dma_addr_t addr = mvm->fw_paging_db[blk_idx].fw_paging_phys;
397
398 addr = addr >> PAGE_2_EXP_SIZE;
399
400 if (iwl_mvm_has_new_tx_api(mvm)) {
401 __le64 phy_addr = cpu_to_le64(addr);
402
403 paging_cmd.device_phy_addr.addr64[blk_idx] = phy_addr;
404 } else {
405 __le32 phy_addr = cpu_to_le32(addr);
406
407 paging_cmd.device_phy_addr.addr32[blk_idx] = phy_addr;
408 }
a6c4fb44
MG		 409 }
410
411 return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
412 IWL_ALWAYS_LONG_GROUP, 0),
d975d720 413 0, size, &paging_cmd);
a6c4fb44
MG		 414}
415
e1120187
MG		 416/*
417 * Send paging item cmd to FW in case CPU2 has paging image
418 */
419static int iwl_trans_get_paging_item(struct iwl_mvm *mvm)
420{
421 int ret;
422 struct iwl_fw_get_item_cmd fw_get_item_cmd = {
423 .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING),
424 };
425
426 struct iwl_fw_get_item_resp *item_resp;
427 struct iwl_host_cmd cmd = {
428 .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0),
429 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
430 .data = { &fw_get_item_cmd, },
431 };
432
433 cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd);
434
435 ret = iwl_mvm_send_cmd(mvm, &cmd);
436 if (ret) {
437 IWL_ERR(mvm,
438 "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n",
439 ret);
440 return ret;
441 }
442
443 item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data;
444 if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) {
445 IWL_ERR(mvm,
446 "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n",
447 le32_to_cpu(item_resp->item_id));
448 ret = -EIO;
449 goto exit;
450 }
451
c94d7996
MG		 452 /* Add an extra page for headers */
453 mvm->trans->paging_download_buf = kzalloc(PAGING_BLOCK_SIZE +
454 FW_PAGING_SIZE,
e1120187
MG		 455 GFP_KERNEL);
456 if (!mvm->trans->paging_download_buf) {
457 ret = -ENOMEM;
458 goto exit;
459 }
460 mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val);
461 mvm->trans->paging_db = mvm->fw_paging_db;
462 IWL_DEBUG_FW(mvm,
463 "Paging: got paging request address (paging_req_addr 0x%08x)\n",
464 mvm->trans->paging_req_addr);
465
466exit:
467 iwl_free_resp(&cmd);
468
469 return ret;
470}
471
8ca151b5
JB		 472static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
473 struct iwl_rx_packet *pkt, void *data)
474{
475 struct iwl_mvm *mvm =
476 container_of(notif_wait, struct iwl_mvm, notif_wait);
477 struct iwl_mvm_alive_data *alive_data = data;
7e1223b5 478 struct mvm_alive_resp_ver1 *palive1;
01a9ca51 479 struct mvm_alive_resp_ver2 *palive2;
7e1223b5 480 struct mvm_alive_resp *palive;
01a9ca51 481
7e1223b5
EG		 482 if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
483 palive1 = (void *)pkt->data;
01a9ca51
EH		 484
485 mvm->support_umac_log = false;
486 mvm->error_event_table =
7e1223b5
EG		 487 le32_to_cpu(palive1->error_event_table_ptr);
488 mvm->log_event_table =
489 le32_to_cpu(palive1->log_event_table_ptr);
490 alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
01a9ca51 491
7e1223b5 492 alive_data->valid = le16_to_cpu(palive1->status) ==
01a9ca51
EH		 493 IWL_ALIVE_STATUS_OK;
494 IWL_DEBUG_FW(mvm,
495 "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
7e1223b5
EG		 496 le16_to_cpu(palive1->status), palive1->ver_type,
497 palive1->ver_subtype, palive1->flags);
498 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
01a9ca51
EH		 499 palive2 = (void *)pkt->data;
500
01a9ca51
EH		 501 mvm->error_event_table =
502 le32_to_cpu(palive2->error_event_table_ptr);
503 mvm->log_event_table =
504 le32_to_cpu(palive2->log_event_table_ptr);
505 alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
506 mvm->umac_error_event_table =
507 le32_to_cpu(palive2->error_info_addr);
91479b64
EH		 508 mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
509 mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
01a9ca51
EH		 510
511 alive_data->valid = le16_to_cpu(palive2->status) ==
512 IWL_ALIVE_STATUS_OK;
ffa70264
EG		 513 if (mvm->umac_error_event_table)
514 mvm->support_umac_log = true;
515
01a9ca51
EH		 516 IWL_DEBUG_FW(mvm,
517 "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
518 le16_to_cpu(palive2->status), palive2->ver_type,
519 palive2->ver_subtype, palive2->flags);
520
521 IWL_DEBUG_FW(mvm,
522 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
523 palive2->umac_major, palive2->umac_minor);
7e1223b5
EG		 524 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
525 palive = (void *)pkt->data;
526
527 mvm->error_event_table =
528 le32_to_cpu(palive->error_event_table_ptr);
529 mvm->log_event_table =
530 le32_to_cpu(palive->log_event_table_ptr);
531 alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
532 mvm->umac_error_event_table =
533 le32_to_cpu(palive->error_info_addr);
534 mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
535 mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
536
537 alive_data->valid = le16_to_cpu(palive->status) ==
538 IWL_ALIVE_STATUS_OK;
539 if (mvm->umac_error_event_table)
540 mvm->support_umac_log = true;
541
542 IWL_DEBUG_FW(mvm,
543 "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
544 le16_to_cpu(palive->status), palive->ver_type,
545 palive->ver_subtype, palive->flags);
546
547 IWL_DEBUG_FW(mvm,
548 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
549 le32_to_cpu(palive->umac_major),
550 le32_to_cpu(palive->umac_minor));
01a9ca51 551 }
8ca151b5
JB		 552
553 return true;
554}
555
556static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
557 struct iwl_rx_packet *pkt, void *data)
558{
559 struct iwl_phy_db *phy_db = data;
560
561 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
562 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
563 return true;
564 }
565
ce1f2778 566 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB		 567
568 return false;
569}
570
571static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
572 enum iwl_ucode_type ucode_type)
573{
574 struct iwl_notification_wait alive_wait;
575 struct iwl_mvm_alive_data alive_data;
576 const struct fw_img *fw;
577 int ret, i;
578 enum iwl_ucode_type old_type = mvm->cur_ucode;
6eb031d2 579 static const u16 alive_cmd[] = { MVM_ALIVE };
91479b64 580 struct iwl_sf_region st_fwrd_space;
8ca151b5 581
61df750c 582 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA		 583 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
584 !(fw_has_capa(&mvm->fw->ucode_capa,
585 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 586 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 587 else
612da1ef 588 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 589 if (WARN_ON(!fw))
8ca151b5 590 return -EINVAL;
befe9b6f
JB		 591 mvm->cur_ucode = ucode_type;
592 mvm->ucode_loaded = false;
8ca151b5
JB		 593
594 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
595 alive_cmd, ARRAY_SIZE(alive_cmd),
596 iwl_alive_fn, &alive_data);
597
598 ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
599 if (ret) {
600 mvm->cur_ucode = old_type;
601 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
602 return ret;
603 }
604
605 /*
606 * Some things may run in the background now, but we
607 * just wait for the ALIVE notification here.
608 */
609 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
610 MVM_UCODE_ALIVE_TIMEOUT);
611 if (ret) {
192de2b4
DS		 612 if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
613 IWL_ERR(mvm,
614 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
615 iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
616 iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
8ca151b5
JB		 617 mvm->cur_ucode = old_type;
618 return ret;
619 }
620
621 if (!alive_data.valid) {
622 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
623 mvm->cur_ucode = old_type;
624 return -EIO;
625 }
626
91479b64
EH		 627 /*
628 * update the sdio allocation according to the pointer we get in the
629 * alive notification.
630 */
631 st_fwrd_space.addr = mvm->sf_space.addr;
632 st_fwrd_space.size = mvm->sf_space.size;
633 ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
82e8aea0
ES		 634 if (ret) {
635 IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
636 return ret;
637 }
91479b64 638
8ca151b5
JB		 639 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
640
a6c4fb44
MG		 641 /*
642 * configure and operate fw paging mechanism.
643 * driver configures the paging flow only once, CPU2 paging image
644 * included in the IWL_UCODE_INIT image.
645 */
646 if (fw->paging_mem_size) {
e1120187
MG		 647 /*
648 * When dma is not enabled, the driver needs to copy / write
649 * the downloaded / uploaded page to / from the smem.
650 * This gets the location of the place were the pages are
651 * stored.
652 */
653 if (!is_device_dma_capable(mvm->trans->dev)) {
654 ret = iwl_trans_get_paging_item(mvm);
655 if (ret) {
656 IWL_ERR(mvm, "failed to get FW paging item\n");
657 return ret;
658 }
659 }
660
a6c4fb44
MG		 661 ret = iwl_save_fw_paging(mvm, fw);
662 if (ret) {
663 IWL_ERR(mvm, "failed to save the FW paging image\n");
664 return ret;
665 }
666
667 ret = iwl_send_paging_cmd(mvm, fw);
668 if (ret) {
669 IWL_ERR(mvm, "failed to send the paging cmd\n");
670 iwl_free_fw_paging(mvm);
671 return ret;
672 }
673 }
674
8ca151b5
JB		 675 /*
676 * Note: all the queues are enabled as part of the interface
677 * initialization, but in firmware restart scenarios they
678 * could be stopped, so wake them up. In firmware restart,
679 * mac80211 will have the queues stopped as well until the
680 * reconfiguration completes. During normal startup, they
681 * will be empty.
682 */
683
4ecafae9 684 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
097129c9
LK		 685 if (iwl_mvm_is_dqa_supported(mvm))
686 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].hw_queue_refcount = 1;
687 else
688 mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1;
8ca151b5 689
df197c00
JB		 690 for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
691 atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
8ca151b5
JB		 692
693 mvm->ucode_loaded = true;
694
695 return 0;
696}
8ca151b5
JB		 697
698static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
699{
700 struct iwl_phy_cfg_cmd phy_cfg_cmd;
701 enum iwl_ucode_type ucode_type = mvm->cur_ucode;
702
703 /* Set parameters */
a0544272 704 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
8ca151b5
JB		 705 phy_cfg_cmd.calib_control.event_trigger =
706 mvm->fw->default_calib[ucode_type].event_trigger;
707 phy_cfg_cmd.calib_control.flow_trigger =
708 mvm->fw->default_calib[ucode_type].flow_trigger;
709
710 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
711 phy_cfg_cmd.phy_cfg);
712
a1022927 713 return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
8ca151b5
JB		 714 sizeof(phy_cfg_cmd), &phy_cfg_cmd);
715}
716
8ca151b5
JB		 717int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
718{
719 struct iwl_notification_wait calib_wait;
6eb031d2 720 static const u16 init_complete[] = {
8ca151b5
JB		 721 INIT_COMPLETE_NOTIF,
722 CALIB_RES_NOTIF_PHY_DB
723 };
724 int ret;
725
726 lockdep_assert_held(&mvm->mutex);
727
8d193ca2 728 if (WARN_ON_ONCE(mvm->calibrating))
8ca151b5
JB		 729 return 0;
730
731 iwl_init_notification_wait(&mvm->notif_wait,
732 &calib_wait,
733 init_complete,
734 ARRAY_SIZE(init_complete),
735 iwl_wait_phy_db_entry,
736 mvm->phy_db);
737
738 /* Will also start the device */
739 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
740 if (ret) {
741 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
742 goto error;
743 }
744
ae397472 745 ret = iwl_send_bt_init_conf(mvm);
931d4160
EG		 746 if (ret)
747 goto error;
748
81a67e32 749 /* Read the NVM only at driver load time, no need to do this twice */
8ca151b5
JB		 750 if (read_nvm) {
751 /* Read nvm */
14b485f0 752 ret = iwl_nvm_init(mvm, true);
8ca151b5
JB		 753 if (ret) {
754 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
755 goto error;
756 }
757 }
758
81a67e32 759 /* In case we read the NVM from external file, load it to the NIC */
e02a9d60 760 if (mvm->nvm_file_name)
81a67e32
EL		 761 iwl_mvm_load_nvm_to_nic(mvm);
762
8ca151b5
JB		 763 ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
764 WARN_ON(ret);
765
4f59334b
EH		 766 /*
767 * abort after reading the nvm in case RF Kill is on, we will complete
768 * the init seq later when RF kill will switch to off
769 */
1a3fe0b2 770 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH		 771 IWL_DEBUG_RF_KILL(mvm,
772 "jump over all phy activities due to RF kill\n");
773 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
a4082843
AN		 774 ret = 1;
775 goto out;
4f59334b
EH		 776 }
777
31b8b343
EG		 778 mvm->calibrating = true;
779
e07cbb53 780 /* Send TX valid antennas before triggering calibrations */
a0544272 781 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53
DS		 782 if (ret)
783 goto error;
784
8ca151b5
JB		 785 /*
786 * Send phy configurations command to init uCode
787 * to start the 16.0 uCode init image internal calibrations.
788 */
789 ret = iwl_send_phy_cfg_cmd(mvm);
790 if (ret) {
791 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
792 ret);
793 goto error;
794 }
795
796 /*
797 * Some things may run in the background now, but we
798 * just wait for the calibration complete notification.
799 */
800 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
801 MVM_UCODE_CALIB_TIMEOUT);
31b8b343 802
1a3fe0b2 803 if (ret && iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343
EG		 804 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
805 ret = 1;
806 }
8ca151b5
JB		 807 goto out;
808
809error:
810 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
811out:
31b8b343 812 mvm->calibrating = false;
a4082843 813 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB		 814 /* we want to debug INIT and we have no NVM - fake */
815 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
816 sizeof(struct ieee80211_channel) +
817 sizeof(struct ieee80211_rate),
818 GFP_KERNEL);
819 if (!mvm->nvm_data)
820 return -ENOMEM;
8ca151b5
JB		 821 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
822 mvm->nvm_data->bands[0].n_channels = 1;
823 mvm->nvm_data->bands[0].n_bitrates = 1;
824 mvm->nvm_data->bands[0].bitrates =
825 (void *)mvm->nvm_data->channels + 1;
826 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
827 }
828
829 return ret;
830}
831
db06f04d
SS		 832static void iwl_mvm_parse_shared_mem_a000(struct iwl_mvm *mvm,
833 struct iwl_rx_packet *pkt)
04fd2c28 834{
db06f04d
SS		 835 struct iwl_shared_mem_cfg *mem_cfg = (void *)pkt->data;
836 int i;
04fd2c28 837
db06f04d
SS		 838 mvm->shared_mem_cfg.num_txfifo_entries =
839 ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size);
840 for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++)
841 mvm->shared_mem_cfg.txfifo_size[i] =
842 le32_to_cpu(mem_cfg->txfifo_size[i]);
843 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
844 mvm->shared_mem_cfg.rxfifo_size[i] =
845 le32_to_cpu(mem_cfg->rxfifo_size[i]);
04fd2c28 846
db06f04d
SS		 847 BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) !=
848 sizeof(mem_cfg->internal_txfifo_size));
5b086414 849
db06f04d
SS		 850 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
851 i++)
852 mvm->shared_mem_cfg.internal_txfifo_size[i] =
853 le32_to_cpu(mem_cfg->internal_txfifo_size[i]);
854}
04fd2c28 855
db06f04d
SS		 856static void iwl_mvm_parse_shared_mem(struct iwl_mvm *mvm,
857 struct iwl_rx_packet *pkt)
858{
859 struct iwl_shared_mem_cfg_v1 *mem_cfg = (void *)pkt->data;
860 int i;
861
862 mvm->shared_mem_cfg.num_txfifo_entries =
863 ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size);
864 for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++)
04fd2c28
LK		 865 mvm->shared_mem_cfg.txfifo_size[i] =
866 le32_to_cpu(mem_cfg->txfifo_size[i]);
867 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
868 mvm->shared_mem_cfg.rxfifo_size[i] =
869 le32_to_cpu(mem_cfg->rxfifo_size[i]);
5b086414 870
db06f04d 871 /* new API has more data, from rxfifo_addr field and on */
5b086414
GBA		 872 if (fw_has_capa(&mvm->fw->ucode_capa,
873 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
5b086414
GBA		 874 BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) !=
875 sizeof(mem_cfg->internal_txfifo_size));
876
877 for (i = 0;
878 i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
879 i++)
880 mvm->shared_mem_cfg.internal_txfifo_size[i] =
881 le32_to_cpu(mem_cfg->internal_txfifo_size[i]);
882 }
db06f04d
SS		 883}
884
885static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
886{
887 struct iwl_host_cmd cmd = {
888 .flags = CMD_WANT_SKB,
889 .data = { NULL, },
890 .len = { 0, },
891 };
892 struct iwl_rx_packet *pkt;
893
894 lockdep_assert_held(&mvm->mutex);
895
896 if (fw_has_capa(&mvm->fw->ucode_capa,
897 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
898 cmd.id = iwl_cmd_id(SHARED_MEM_CFG_CMD, SYSTEM_GROUP, 0);
899 else
900 cmd.id = SHARED_MEM_CFG;
901
902 if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
903 return;
904
905 pkt = cmd.resp_pkt;
906 if (iwl_mvm_has_new_tx_api(mvm))
907 iwl_mvm_parse_shared_mem_a000(mvm, pkt);
908 else
909 iwl_mvm_parse_shared_mem(mvm, pkt);
5b086414 910
04fd2c28
LK		 911 IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
912
04fd2c28
LK		 913 iwl_free_resp(&cmd);
914}
915
84bfffa9
EG		 916static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
917{
918 struct iwl_ltr_config_cmd cmd = {
919 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
920 };
921
922 if (!mvm->trans->ltr_enabled)
923 return 0;
924
84bfffa9
EG		 925 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
926 sizeof(cmd), &cmd);
927}
928
da2830ac
LC		 929#define ACPI_WRDS_METHOD "WRDS"
930#define ACPI_WRDS_WIFI (0x07)
931#define ACPI_WRDS_TABLE_SIZE 10
932
933struct iwl_mvm_sar_table {
934 bool enabled;
935 u8 values[ACPI_WRDS_TABLE_SIZE];
936};
937
938#ifdef CONFIG_ACPI
939static int iwl_mvm_sar_get_wrds(struct iwl_mvm *mvm, union acpi_object *wrds,
940 struct iwl_mvm_sar_table *sar_table)
941{
942 union acpi_object *data_pkg;
943 u32 i;
944
945 /* We need at least two packages, one for the revision and one
946 * for the data itself. Also check that the revision is valid
947 * (i.e. it is an integer set to 0).
948 */
949 if (wrds->type != ACPI_TYPE_PACKAGE ||
950 wrds->package.count < 2 ||
951 wrds->package.elements[0].type != ACPI_TYPE_INTEGER ||
952 wrds->package.elements[0].integer.value != 0) {
953 IWL_DEBUG_RADIO(mvm, "Unsupported wrds structure\n");
954 return -EINVAL;
955 }
956
957 /* loop through all the packages to find the one for WiFi */
958 for (i = 1; i < wrds->package.count; i++) {
959 union acpi_object *domain;
960
961 data_pkg = &wrds->package.elements[i];
962
963 /* Skip anything that is not a package with the right
964 * amount of elements (i.e. domain_type,
965 * enabled/disabled plus the sar table size.
966 */
967 if (data_pkg->type != ACPI_TYPE_PACKAGE ||
968 data_pkg->package.count != ACPI_WRDS_TABLE_SIZE + 2)
969 continue;
970
971 domain = &data_pkg->package.elements[0];
972 if (domain->type == ACPI_TYPE_INTEGER &&
973 domain->integer.value == ACPI_WRDS_WIFI)
974 break;
975
976 data_pkg = NULL;
977 }
978
979 if (!data_pkg)
980 return -ENOENT;
981
982 if (data_pkg->package.elements[1].type != ACPI_TYPE_INTEGER)
983 return -EINVAL;
984
985 sar_table->enabled = !!(data_pkg->package.elements[1].integer.value);
986
987 for (i = 0; i < ACPI_WRDS_TABLE_SIZE; i++) {
988 union acpi_object *entry;
989
990 entry = &data_pkg->package.elements[i + 2];
991 if ((entry->type != ACPI_TYPE_INTEGER) ||
992 (entry->integer.value > U8_MAX))
993 return -EINVAL;
994
995 sar_table->values[i] = entry->integer.value;
996 }
997
998 return 0;
999}
1000
1001static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm,
1002 struct iwl_mvm_sar_table *sar_table)
1003{
1004 acpi_handle root_handle;
1005 acpi_handle handle;
1006 struct acpi_buffer wrds = {ACPI_ALLOCATE_BUFFER, NULL};
1007 acpi_status status;
1008 int ret;
1009
1010 root_handle = ACPI_HANDLE(mvm->dev);
1011 if (!root_handle) {
1012 IWL_DEBUG_RADIO(mvm,
1013 "Could not retrieve root port ACPI handle\n");
1014 return -ENOENT;
1015 }
1016
1017 /* Get the method's handle */
1018 status = acpi_get_handle(root_handle, (acpi_string)ACPI_WRDS_METHOD,
1019 &handle);
1020 if (ACPI_FAILURE(status)) {
1021 IWL_DEBUG_RADIO(mvm, "WRDS method not found\n");
1022 return -ENOENT;
1023 }
1024
1025 /* Call WRDS with no arguments */
1026 status = acpi_evaluate_object(handle, NULL, NULL, &wrds);
1027 if (ACPI_FAILURE(status)) {
1028 IWL_DEBUG_RADIO(mvm, "WRDS invocation failed (0x%x)\n", status);
1029 return -ENOENT;
1030 }
1031
1032 ret = iwl_mvm_sar_get_wrds(mvm, wrds.pointer, sar_table);
1033 kfree(wrds.pointer);
1034
1035 return ret;
1036}
1037#else /* CONFIG_ACPI */
1038static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm,
1039 struct iwl_mvm_sar_table *sar_table)
1040{
1041 return -ENOENT;
1042}
1043#endif /* CONFIG_ACPI */
1044
1045static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1046{
1047 struct iwl_mvm_sar_table sar_table;
1048 struct iwl_dev_tx_power_cmd cmd = {
55bfa4b9 1049 .v3.v2.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
da2830ac
LC		 1050 };
1051 int ret, i, j, idx;
55bfa4b9 1052 int len = sizeof(cmd);
da2830ac
LC		 1053
1054 /* we can't do anything with the table if the FW doesn't support it */
1055 if (!fw_has_api(&mvm->fw->ucode_capa,
1056 IWL_UCODE_TLV_API_TX_POWER_CHAIN)) {
1057 IWL_DEBUG_RADIO(mvm,
1058 "FW doesn't support per-chain TX power settings.\n");
1059 return 0;
1060 }
1061
55bfa4b9
LC		 1062 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TX_POWER_ACK))
1063 len = sizeof(cmd.v3);
1064
da2830ac
LC		 1065 ret = iwl_mvm_sar_get_table(mvm, &sar_table);
1066 if (ret < 0) {
1067 IWL_DEBUG_RADIO(mvm,
1068 "SAR BIOS table invalid or unavailable. (%d)\n",
1069 ret);
1070 /* we don't fail if the table is not available */
1071 return 0;
1072 }
1073
1074 if (!sar_table.enabled)
1075 return 0;
1076
1077 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
1078
1079 BUILD_BUG_ON(IWL_NUM_CHAIN_LIMITS * IWL_NUM_SUB_BANDS !=
1080 ACPI_WRDS_TABLE_SIZE);
1081
1082 for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
1083 IWL_DEBUG_RADIO(mvm, " Chain[%d]:\n", i);
1084 for (j = 0; j < IWL_NUM_SUB_BANDS; j++) {
1085 idx = (i * IWL_NUM_SUB_BANDS) + j;
55bfa4b9 1086 cmd.v3.per_chain_restriction[i][j] =
da2830ac
LC		 1087 cpu_to_le16(sar_table.values[idx]);
1088 IWL_DEBUG_RADIO(mvm, " Band[%d] = %d * .125dBm\n",
1089 j, sar_table.values[idx]);
1090 }
1091 }
1092
55bfa4b9 1093 ret = iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
da2830ac
LC		 1094 if (ret)
1095 IWL_ERR(mvm, "failed to set per-chain TX power: %d\n", ret);
1096
1097 return ret;
1098}
1099
8ca151b5
JB		 1100int iwl_mvm_up(struct iwl_mvm *mvm)
1101{
1102 int ret, i;
53a9d61e
IP		 1103 struct ieee80211_channel *chan;
1104 struct cfg80211_chan_def chandef;
8ca151b5
JB		 1105
1106 lockdep_assert_held(&mvm->mutex);
1107
1108 ret = iwl_trans_start_hw(mvm->trans);
1109 if (ret)
1110 return ret;
1111
ff116373
EL		 1112 /*
1113 * If we haven't completed the run of the init ucode during
1114 * module loading, load init ucode now
1115 * (for example, if we were in RFKILL)
1116 */
8d193ca2 1117 ret = iwl_run_init_mvm_ucode(mvm, false);
f2082a53
SS		 1118
1119 if (iwlmvm_mod_params.init_dbg)
1120 return 0;
1121
1122 if (ret) {
8d193ca2
EH		 1123 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
1124 /* this can't happen */
1125 if (WARN_ON(ret > 0))
1126 ret = -ERFKILL;
1127 goto error;
1128 }
8ca151b5 1129
f2082a53
SS		 1130 /*
1131 * Stop and start the transport without entering low power
1132 * mode. This will save the state of other components on the
1133 * device that are triggered by the INIT firwmare (MFUART).
1134 */
1135 _iwl_trans_stop_device(mvm->trans, false);
1136 ret = _iwl_trans_start_hw(mvm->trans, false);
1137 if (ret)
1138 goto error;
8ca151b5
JB		 1139
1140 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1141 if (ret) {
1142 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
1143 goto error;
1144 }
1145
6c7d32cf 1146 iwl_mvm_get_shared_mem_conf(mvm);
04fd2c28 1147
1f3b0ff8
LE		 1148 ret = iwl_mvm_sf_update(mvm, NULL, false);
1149 if (ret)
1150 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1151
6a951267 1152 mvm->fw_dbg_conf = FW_DBG_INVALID;
945d4202
EG		 1153 /* if we have a destination, assume EARLY START */
1154 if (mvm->fw->dbg_dest_tlv)
1155 mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
d2709ad7 1156 iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
6a951267 1157
a0544272 1158 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1159 if (ret)
1160 goto error;
1161
931d4160
EG		 1162 ret = iwl_send_bt_init_conf(mvm);
1163 if (ret)
1164 goto error;
1165
8ca151b5
JB		 1166 /* Send phy db control command and then phy db calibration*/
1167 ret = iwl_send_phy_db_data(mvm->phy_db);
1168 if (ret)
1169 goto error;
1170
1171 ret = iwl_send_phy_cfg_cmd(mvm);
1172 if (ret)
1173 goto error;
1174
43413a97
SS		 1175 /* Init RSS configuration */
1176 if (iwl_mvm_has_new_rx_api(mvm)) {
1177 ret = iwl_send_rss_cfg_cmd(mvm);
1178 if (ret) {
1179 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1180 ret);
1181 goto error;
1182 }
1183 }
1184
8ca151b5
JB		 1185 /* init the fw <-> mac80211 STA mapping */
1186 for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
1187 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1188
1d3c3f63
AN		 1189 mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
1190
b2b7875b
JB		 1191 /* reset quota debouncing buffer - 0xff will yield invalid data */
1192 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1193
97d5be7e
LK		 1194 /* Enable DQA-mode if required */
1195 if (iwl_mvm_is_dqa_supported(mvm)) {
1196 ret = iwl_mvm_send_dqa_cmd(mvm);
1197 if (ret)
1198 goto error;
1199 } else {
1200 IWL_DEBUG_FW(mvm, "Working in non-DQA mode\n");
1201 }
1202
8ca151b5
JB		 1203 /* Add auxiliary station for scanning */
1204 ret = iwl_mvm_add_aux_sta(mvm);
1205 if (ret)
1206 goto error;
1207
53a9d61e 1208 /* Add all the PHY contexts */
57fbcce3 1209 chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0];
53a9d61e
IP		 1210 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1211 for (i = 0; i < NUM_PHY_CTX; i++) {
1212 /*
1213 * The channel used here isn't relevant as it's
1214 * going to be overwritten in the other flows.
1215 * For now use the first channel we have.
1216 */
1217 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1218 &chandef, 1, 1);
1219 if (ret)
1220 goto error;
1221 }
8ca151b5 1222
c221daf2
CRI		 1223#ifdef CONFIG_THERMAL
1224 if (iwl_mvm_is_tt_in_fw(mvm)) {
1225 /* in order to give the responsibility of ct-kill and
1226 * TX backoff to FW we need to send empty temperature reporting
1227 * cmd during init time
1228 */
1229 iwl_mvm_send_temp_report_ths_cmd(mvm);
1230 } else {
1231 /* Initialize tx backoffs to the minimal possible */
1232 iwl_mvm_tt_tx_backoff(mvm, 0);
1233 }
5c89e7bc
CRI		 1234
1235 /* TODO: read the budget from BIOS / Platform NVM */
75cfe338 1236 if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) {
5c89e7bc
CRI		 1237 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1238 mvm->cooling_dev.cur_state);
75cfe338
LC		 1239 if (ret)
1240 goto error;
1241 }
c221daf2 1242#else
0c0e2c71
IY		 1243 /* Initialize tx backoffs to the minimal possible */
1244 iwl_mvm_tt_tx_backoff(mvm, 0);
c221daf2 1245#endif
0c0e2c71 1246
84bfffa9 1247 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1248
c1cb92fc 1249 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB		 1250 if (ret)
1251 goto error;
1252
35af15d1
AN		 1253 /*
1254 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1255 * anyway, so don't init MCC.
1256 */
1257 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1258 ret = iwl_mvm_init_mcc(mvm);
1259 if (ret)
1260 goto error;
1261 }
90d4f7db 1262
859d914c 1263 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1264 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS		 1265 ret = iwl_mvm_config_scan(mvm);
1266 if (ret)
1267 goto error;
1268 }
1269
93190fb0
AA		 1270 if (iwl_mvm_is_csum_supported(mvm) &&
1271 mvm->cfg->features & NETIF_F_RXCSUM)
1272 iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
1273
7498cf4c
EP		 1274 /* allow FW/transport low power modes if not during restart */
1275 if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1276 iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
1277
da2830ac
LC		 1278 ret = iwl_mvm_sar_init(mvm);
1279 if (ret)
1280 goto error;
1281
53a9d61e 1282 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB		 1283 return 0;
1284 error:
fcb6b92a 1285 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1286 return ret;
1287}
1288
1289int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1290{
1291 int ret, i;
1292
1293 lockdep_assert_held(&mvm->mutex);
1294
1295 ret = iwl_trans_start_hw(mvm->trans);
1296 if (ret)
1297 return ret;
1298
1299 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1300 if (ret) {
1301 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1302 goto error;
1303 }
1304
a0544272 1305 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1306 if (ret)
1307 goto error;
1308
1309 /* Send phy db control command and then phy db calibration*/
1310 ret = iwl_send_phy_db_data(mvm->phy_db);
1311 if (ret)
1312 goto error;
1313
1314 ret = iwl_send_phy_cfg_cmd(mvm);
1315 if (ret)
1316 goto error;
1317
1318 /* init the fw <-> mac80211 STA mapping */
1319 for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
1320 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1321
1322 /* Add auxiliary station for scanning */
1323 ret = iwl_mvm_add_aux_sta(mvm);
1324 if (ret)
1325 goto error;
1326
1327 return 0;
1328 error:
fcb6b92a 1329 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1330 return ret;
1331}
1332
0416841d
JB		 1333void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1334 struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB		 1335{
1336 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1337 struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1338 u32 flags = le32_to_cpu(card_state_notif->flags);
1339
1340 IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1341 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1342 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1343 (flags & CT_KILL_CARD_DISABLED) ?
1344 "Reached" : "Not reached");
8ca151b5
JB		 1345}
1346
0416841d
JB		 1347void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1348 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI		 1349{
1350 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1351 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1352
1353 IWL_DEBUG_INFO(mvm,
1354 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1355 le32_to_cpu(mfuart_notif->installed_ver),
1356 le32_to_cpu(mfuart_notif->external_ver),
1357 le32_to_cpu(mfuart_notif->status),
1358 le32_to_cpu(mfuart_notif->duration));
30269c12 1359}
Linux 6.x block layer and io_uring tree(s)