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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
bdccdb85 | 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
48e775e6 | 11 | * Copyright(c) 2018 - 2019 Intel Corporation |
8ca151b5 JB |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of version 2 of the GNU General Public License as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
8ca151b5 | 22 | * The full GNU General Public License is included in this distribution |
410dc5aa | 23 | * in the file called COPYING. |
8ca151b5 JB |
24 | * |
25 | * Contact Information: | |
cb2f8277 | 26 | * Intel Linux Wireless <linuxwifi@intel.com> |
8ca151b5 JB |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | * BSD LICENSE | |
30 | * | |
51368bf7 | 31 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 32 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
bdccdb85 | 33 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
48e775e6 | 34 | * Copyright(c) 2018 - 2019 Intel Corporation |
8ca151b5 JB |
35 | * All rights reserved. |
36 | * | |
37 | * Redistribution and use in source and binary forms, with or without | |
38 | * modification, are permitted provided that the following conditions | |
39 | * are met: | |
40 | * | |
41 | * * Redistributions of source code must retain the above copyright | |
42 | * notice, this list of conditions and the following disclaimer. | |
43 | * * Redistributions in binary form must reproduce the above copyright | |
44 | * notice, this list of conditions and the following disclaimer in | |
45 | * the documentation and/or other materials provided with the | |
46 | * distribution. | |
47 | * * Neither the name Intel Corporation nor the names of its | |
48 | * contributors may be used to endorse or promote products derived | |
49 | * from this software without specific prior written permission. | |
50 | * | |
51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
52 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
53 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
54 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
55 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
56 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
57 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
58 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
59 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
60 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
61 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
62 | * | |
63 | *****************************************************************************/ | |
64 | #include <net/mac80211.h> | |
854d773e | 65 | #include <linux/netdevice.h> |
8ca151b5 JB |
66 | |
67 | #include "iwl-trans.h" | |
68 | #include "iwl-op-mode.h" | |
d962f9b1 | 69 | #include "fw/img.h" |
8ca151b5 JB |
70 | #include "iwl-debug.h" |
71 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
72 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 73 | #include "iwl-prph.h" |
813df5ce | 74 | #include "fw/acpi.h" |
8ca151b5 JB |
75 | |
76 | #include "mvm.h" | |
7174beb6 | 77 | #include "fw/dbg.h" |
8ca151b5 | 78 | #include "iwl-phy-db.h" |
9c4f7d51 ST |
79 | #include "iwl-modparams.h" |
80 | #include "iwl-nvm-parse.h" | |
8ca151b5 JB |
81 | |
82 | #define MVM_UCODE_ALIVE_TIMEOUT HZ | |
83 | #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) | |
84 | ||
85 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
86 | ||
8ca151b5 JB |
87 | struct iwl_mvm_alive_data { |
88 | bool valid; | |
89 | u32 scd_base_addr; | |
90 | }; | |
91 | ||
8ca151b5 JB |
92 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) |
93 | { | |
94 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
95 | .valid = cpu_to_le32(valid_tx_ant), | |
96 | }; | |
97 | ||
33223542 | 98 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 99 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
100 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
101 | } | |
102 | ||
43413a97 SS |
103 | static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) |
104 | { | |
105 | int i; | |
106 | struct iwl_rss_config_cmd cmd = { | |
107 | .flags = cpu_to_le32(IWL_RSS_ENABLE), | |
608dce95 SS |
108 | .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | |
109 | BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | | |
110 | BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | | |
111 | BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | | |
112 | BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | | |
113 | BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), | |
43413a97 SS |
114 | }; |
115 | ||
f43495fd SS |
116 | if (mvm->trans->num_rx_queues == 1) |
117 | return 0; | |
118 | ||
854d773e | 119 | /* Do not direct RSS traffic to Q 0 which is our fallback queue */ |
43413a97 | 120 | for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) |
854d773e SS |
121 | cmd.indirection_table[i] = |
122 | 1 + (i % (mvm->trans->num_rx_queues - 1)); | |
123 | netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); | |
43413a97 SS |
124 | |
125 | return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); | |
126 | } | |
127 | ||
8edbfaa1 SS |
128 | static int iwl_configure_rxq(struct iwl_mvm *mvm) |
129 | { | |
dbf592f3 | 130 | int i, num_queues, size, ret; |
8edbfaa1 | 131 | struct iwl_rfh_queue_config *cmd; |
dbf592f3 JB |
132 | struct iwl_host_cmd hcmd = { |
133 | .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD), | |
134 | .dataflags[0] = IWL_HCMD_DFL_NOCOPY, | |
135 | }; | |
8edbfaa1 SS |
136 | |
137 | /* Do not configure default queue, it is configured via context info */ | |
138 | num_queues = mvm->trans->num_rx_queues - 1; | |
139 | ||
dbf592f3 | 140 | size = struct_size(cmd, data, num_queues); |
8edbfaa1 SS |
141 | |
142 | cmd = kzalloc(size, GFP_KERNEL); | |
143 | if (!cmd) | |
144 | return -ENOMEM; | |
145 | ||
146 | cmd->num_queues = num_queues; | |
147 | ||
148 | for (i = 0; i < num_queues; i++) { | |
149 | struct iwl_trans_rxq_dma_data data; | |
150 | ||
151 | cmd->data[i].q_num = i + 1; | |
152 | iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data); | |
153 | ||
154 | cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb); | |
155 | cmd->data[i].urbd_stts_wrptr = | |
156 | cpu_to_le64(data.urbd_stts_wrptr); | |
157 | cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb); | |
158 | cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid); | |
159 | } | |
160 | ||
dbf592f3 JB |
161 | hcmd.data[0] = cmd; |
162 | hcmd.len[0] = size; | |
163 | ||
164 | ret = iwl_mvm_send_cmd(mvm, &hcmd); | |
165 | ||
166 | kfree(cmd); | |
167 | ||
168 | return ret; | |
8edbfaa1 SS |
169 | } |
170 | ||
97d5be7e LK |
171 | static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) |
172 | { | |
173 | struct iwl_dqa_enable_cmd dqa_cmd = { | |
174 | .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), | |
175 | }; | |
176 | u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); | |
177 | int ret; | |
178 | ||
179 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); | |
180 | if (ret) | |
181 | IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); | |
182 | else | |
183 | IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); | |
184 | ||
185 | return ret; | |
186 | } | |
187 | ||
bdccdb85 GBA |
188 | void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, |
189 | struct iwl_rx_cmd_buffer *rxb) | |
190 | { | |
191 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
192 | struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; | |
193 | __le32 *dump_data = mfu_dump_notif->data; | |
194 | int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); | |
195 | int i; | |
196 | ||
197 | if (mfu_dump_notif->index_num == 0) | |
198 | IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", | |
199 | le32_to_cpu(mfu_dump_notif->assert_id)); | |
200 | ||
201 | for (i = 0; i < n_words; i++) | |
202 | IWL_DEBUG_INFO(mvm, | |
203 | "MFUART assert dump, dword %u: 0x%08x\n", | |
204 | le16_to_cpu(mfu_dump_notif->index_num) * | |
205 | n_words + i, | |
206 | le32_to_cpu(dump_data[i])); | |
207 | } | |
208 | ||
8ca151b5 JB |
209 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
210 | struct iwl_rx_packet *pkt, void *data) | |
211 | { | |
212 | struct iwl_mvm *mvm = | |
213 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
214 | struct iwl_mvm_alive_data *alive_data = data; | |
5c228d63 | 215 | struct mvm_alive_resp_v3 *palive3; |
7e1223b5 | 216 | struct mvm_alive_resp *palive; |
5c228d63 SS |
217 | struct iwl_umac_alive *umac; |
218 | struct iwl_lmac_alive *lmac1; | |
219 | struct iwl_lmac_alive *lmac2 = NULL; | |
220 | u16 status; | |
22463857 | 221 | u32 lmac_error_event_table, umac_error_event_table; |
01a9ca51 | 222 | |
5c228d63 SS |
223 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { |
224 | palive = (void *)pkt->data; | |
225 | umac = &palive->umac_data; | |
226 | lmac1 = &palive->lmac_data[0]; | |
227 | lmac2 = &palive->lmac_data[1]; | |
228 | status = le16_to_cpu(palive->status); | |
229 | } else { | |
230 | palive3 = (void *)pkt->data; | |
231 | umac = &palive3->umac_data; | |
232 | lmac1 = &palive3->lmac_data; | |
233 | status = le16_to_cpu(palive3->status); | |
234 | } | |
01a9ca51 | 235 | |
22463857 SM |
236 | lmac_error_event_table = |
237 | le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr); | |
238 | iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table); | |
239 | ||
5c228d63 | 240 | if (lmac2) |
91c28b83 | 241 | mvm->trans->dbg.lmac_error_event_table[1] = |
22463857 | 242 | le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr); |
ffa70264 | 243 | |
22463857 | 244 | umac_error_event_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr); |
01a9ca51 | 245 | |
3485e76e LC |
246 | if (!umac_error_event_table) { |
247 | mvm->support_umac_log = false; | |
248 | } else if (umac_error_event_table >= | |
249 | mvm->trans->cfg->min_umac_error_event_table) { | |
250 | mvm->support_umac_log = true; | |
3485e76e | 251 | } else { |
fb5b2846 LC |
252 | IWL_ERR(mvm, |
253 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
22463857 | 254 | umac_error_event_table, |
fb5b2846 LC |
255 | (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? |
256 | "Init" : "RT"); | |
3485e76e LC |
257 | mvm->support_umac_log = false; |
258 | } | |
fb5b2846 | 259 | |
22463857 SM |
260 | if (mvm->support_umac_log) |
261 | iwl_fw_umac_set_alive_err_table(mvm->trans, | |
262 | umac_error_event_table); | |
263 | ||
264 | alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr); | |
5c228d63 | 265 | alive_data->valid = status == IWL_ALIVE_STATUS_OK; |
7e1223b5 | 266 | |
5c228d63 SS |
267 | IWL_DEBUG_FW(mvm, |
268 | "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", | |
269 | status, lmac1->ver_type, lmac1->ver_subtype); | |
7e1223b5 | 270 | |
5c228d63 SS |
271 | if (lmac2) |
272 | IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); | |
7e1223b5 | 273 | |
5c228d63 SS |
274 | IWL_DEBUG_FW(mvm, |
275 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
276 | le32_to_cpu(umac->umac_major), | |
277 | le32_to_cpu(umac->umac_minor)); | |
8ca151b5 | 278 | |
0a3a3e9e SM |
279 | iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac); |
280 | ||
8ca151b5 JB |
281 | return true; |
282 | } | |
283 | ||
1f370650 SS |
284 | static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, |
285 | struct iwl_rx_packet *pkt, void *data) | |
286 | { | |
287 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
288 | ||
289 | return true; | |
290 | } | |
291 | ||
8ca151b5 JB |
292 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, |
293 | struct iwl_rx_packet *pkt, void *data) | |
294 | { | |
295 | struct iwl_phy_db *phy_db = data; | |
296 | ||
297 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
298 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
299 | return true; | |
300 | } | |
301 | ||
ce1f2778 | 302 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); |
8ca151b5 JB |
303 | |
304 | return false; | |
305 | } | |
306 | ||
307 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
308 | enum iwl_ucode_type ucode_type) | |
309 | { | |
310 | struct iwl_notification_wait alive_wait; | |
94a8d87c | 311 | struct iwl_mvm_alive_data alive_data = {}; |
8ca151b5 | 312 | const struct fw_img *fw; |
cfbc6c4c | 313 | int ret; |
702e975d | 314 | enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; |
6eb031d2 | 315 | static const u16 alive_cmd[] = { MVM_ALIVE }; |
b3500b47 EG |
316 | bool run_in_rfkill = |
317 | ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm); | |
8ca151b5 | 318 | |
61df750c | 319 | if (ucode_type == IWL_UCODE_REGULAR && |
3d2d4422 GBA |
320 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && |
321 | !(fw_has_capa(&mvm->fw->ucode_capa, | |
322 | IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) | |
612da1ef | 323 | fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); |
61df750c | 324 | else |
612da1ef | 325 | fw = iwl_get_ucode_image(mvm->fw, ucode_type); |
befe9b6f | 326 | if (WARN_ON(!fw)) |
8ca151b5 | 327 | return -EINVAL; |
702e975d | 328 | iwl_fw_set_current_image(&mvm->fwrt, ucode_type); |
65b280fe | 329 | clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); |
8ca151b5 JB |
330 | |
331 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
332 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
333 | iwl_alive_fn, &alive_data); | |
334 | ||
b3500b47 EG |
335 | /* |
336 | * We want to load the INIT firmware even in RFKILL | |
337 | * For the unified firmware case, the ucode_type is not | |
338 | * INIT, but we still need to run it. | |
339 | */ | |
340 | ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill); | |
8ca151b5 | 341 | if (ret) { |
702e975d | 342 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
343 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); |
344 | return ret; | |
345 | } | |
346 | ||
347 | /* | |
348 | * Some things may run in the background now, but we | |
349 | * just wait for the ALIVE notification here. | |
350 | */ | |
351 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
352 | MVM_UCODE_ALIVE_TIMEOUT); | |
353 | if (ret) { | |
d6be9c1d SS |
354 | struct iwl_trans *trans = mvm->trans; |
355 | ||
67b8261c | 356 | if (ret == -ETIMEDOUT) |
700b3799 SM |
357 | iwl_fw_dbg_error_collect(&mvm->fwrt, |
358 | FW_DBG_TRIGGER_ALIVE_TIMEOUT); | |
67b8261c | 359 | |
286ca8eb | 360 | if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) |
d6be9c1d SS |
361 | IWL_ERR(mvm, |
362 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
ea695b7c ST |
363 | iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), |
364 | iwl_read_umac_prph(trans, | |
365 | UMAG_SB_CPU_2_STATUS)); | |
286ca8eb | 366 | else if (trans->trans_cfg->device_family >= |
79b6c8fe | 367 | IWL_DEVICE_FAMILY_8000) |
192de2b4 DS |
368 | IWL_ERR(mvm, |
369 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
d6be9c1d SS |
370 | iwl_read_prph(trans, SB_CPU_1_STATUS), |
371 | iwl_read_prph(trans, SB_CPU_2_STATUS)); | |
702e975d | 372 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
373 | return ret; |
374 | } | |
375 | ||
376 | if (!alive_data.valid) { | |
377 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
702e975d | 378 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
379 | return -EIO; |
380 | } | |
381 | ||
382 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); | |
383 | ||
384 | /* | |
385 | * Note: all the queues are enabled as part of the interface | |
386 | * initialization, but in firmware restart scenarios they | |
387 | * could be stopped, so wake them up. In firmware restart, | |
388 | * mac80211 will have the queues stopped as well until the | |
389 | * reconfiguration completes. During normal startup, they | |
390 | * will be empty. | |
391 | */ | |
392 | ||
4ecafae9 | 393 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
1c14089e JB |
394 | /* |
395 | * Set a 'fake' TID for the command queue, since we use the | |
396 | * hweight() of the tid_bitmap as a refcount now. Not that | |
397 | * we ever even consider the command queue as one we might | |
398 | * want to reuse, but be safe nevertheless. | |
399 | */ | |
400 | mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = | |
401 | BIT(IWL_MAX_TID_COUNT + 2); | |
8ca151b5 | 402 | |
65b280fe | 403 | set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); |
f7805b33 LC |
404 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
405 | iwl_fw_set_dbg_rec_on(&mvm->fwrt); | |
406 | #endif | |
8ca151b5 JB |
407 | |
408 | return 0; | |
409 | } | |
8ca151b5 | 410 | |
8c5f47b1 JB |
411 | static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
412 | { | |
413 | struct iwl_notification_wait init_wait; | |
414 | struct iwl_nvm_access_complete_cmd nvm_complete = {}; | |
415 | struct iwl_init_extended_cfg_cmd init_cfg = { | |
416 | .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), | |
417 | }; | |
418 | static const u16 init_complete[] = { | |
419 | INIT_COMPLETE_NOTIF, | |
420 | }; | |
421 | int ret; | |
422 | ||
a4584729 HD |
423 | if (mvm->trans->cfg->tx_with_siso_diversity) |
424 | init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); | |
425 | ||
8c5f47b1 JB |
426 | lockdep_assert_held(&mvm->mutex); |
427 | ||
94022562 EG |
428 | mvm->rfkill_safe_init_done = false; |
429 | ||
8c5f47b1 JB |
430 | iwl_init_notification_wait(&mvm->notif_wait, |
431 | &init_wait, | |
432 | init_complete, | |
433 | ARRAY_SIZE(init_complete), | |
434 | iwl_wait_init_complete, | |
435 | NULL); | |
436 | ||
b108d8c7 | 437 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); |
86ce5c74 | 438 | |
8c5f47b1 JB |
439 | /* Will also start the device */ |
440 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
441 | if (ret) { | |
442 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
443 | goto error; | |
444 | } | |
b108d8c7 SM |
445 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, |
446 | NULL); | |
8c5f47b1 JB |
447 | |
448 | /* Send init config command to mark that we are sending NVM access | |
449 | * commands | |
450 | */ | |
451 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, | |
b3500b47 EG |
452 | INIT_EXTENDED_CFG_CMD), |
453 | CMD_SEND_IN_RFKILL, | |
8c5f47b1 JB |
454 | sizeof(init_cfg), &init_cfg); |
455 | if (ret) { | |
456 | IWL_ERR(mvm, "Failed to run init config command: %d\n", | |
457 | ret); | |
458 | goto error; | |
459 | } | |
460 | ||
e9e1ba3d SS |
461 | /* Load NVM to NIC if needed */ |
462 | if (mvm->nvm_file_name) { | |
9c4f7d51 ST |
463 | iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, |
464 | mvm->nvm_sections); | |
8c5f47b1 | 465 | iwl_mvm_load_nvm_to_nic(mvm); |
e9e1ba3d | 466 | } |
8c5f47b1 | 467 | |
d4f3695e | 468 | if (IWL_MVM_PARSE_NVM && read_nvm) { |
5bd1d2c1 | 469 | ret = iwl_nvm_init(mvm); |
d4f3695e SS |
470 | if (ret) { |
471 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
472 | goto error; | |
473 | } | |
474 | } | |
475 | ||
8c5f47b1 | 476 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, |
b3500b47 EG |
477 | NVM_ACCESS_COMPLETE), |
478 | CMD_SEND_IN_RFKILL, | |
8c5f47b1 JB |
479 | sizeof(nvm_complete), &nvm_complete); |
480 | if (ret) { | |
481 | IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", | |
482 | ret); | |
483 | goto error; | |
484 | } | |
485 | ||
486 | /* We wait for the INIT complete notification */ | |
e9e1ba3d SS |
487 | ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, |
488 | MVM_UCODE_ALIVE_TIMEOUT); | |
489 | if (ret) | |
490 | return ret; | |
491 | ||
492 | /* Read the NVM only at driver load time, no need to do this twice */ | |
d4f3695e | 493 | if (!IWL_MVM_PARSE_NVM && read_nvm) { |
4c625c56 | 494 | mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); |
c135cb56 ST |
495 | if (IS_ERR(mvm->nvm_data)) { |
496 | ret = PTR_ERR(mvm->nvm_data); | |
497 | mvm->nvm_data = NULL; | |
e9e1ba3d SS |
498 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); |
499 | return ret; | |
500 | } | |
501 | } | |
502 | ||
b3500b47 EG |
503 | mvm->rfkill_safe_init_done = true; |
504 | ||
e9e1ba3d | 505 | return 0; |
8c5f47b1 JB |
506 | |
507 | error: | |
508 | iwl_remove_notification(&mvm->notif_wait, &init_wait); | |
509 | return ret; | |
510 | } | |
511 | ||
8ca151b5 JB |
512 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) |
513 | { | |
514 | struct iwl_phy_cfg_cmd phy_cfg_cmd; | |
702e975d | 515 | enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; |
8ca151b5 | 516 | |
bb99ff9b | 517 | if (iwl_mvm_has_unified_ucode(mvm) && |
d923b020 | 518 | !mvm->trans->cfg->tx_with_siso_diversity) |
bb99ff9b | 519 | return 0; |
d923b020 LC |
520 | |
521 | if (mvm->trans->cfg->tx_with_siso_diversity) { | |
bb99ff9b LC |
522 | /* |
523 | * TODO: currently we don't set the antenna but letting the NIC | |
524 | * to decide which antenna to use. This should come from BIOS. | |
525 | */ | |
526 | phy_cfg_cmd.phy_cfg = | |
527 | cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED); | |
528 | } | |
529 | ||
8ca151b5 | 530 | /* Set parameters */ |
a0544272 | 531 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
86a2b204 LC |
532 | |
533 | /* set flags extra PHY configuration flags from the device's cfg */ | |
534 | phy_cfg_cmd.phy_cfg |= cpu_to_le32(mvm->cfg->extra_phy_cfg_flags); | |
535 | ||
8ca151b5 JB |
536 | phy_cfg_cmd.calib_control.event_trigger = |
537 | mvm->fw->default_calib[ucode_type].event_trigger; | |
538 | phy_cfg_cmd.calib_control.flow_trigger = | |
539 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
540 | ||
541 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", | |
542 | phy_cfg_cmd.phy_cfg); | |
543 | ||
a1022927 | 544 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
545 | sizeof(phy_cfg_cmd), &phy_cfg_cmd); |
546 | } | |
547 | ||
8ca151b5 JB |
548 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
549 | { | |
550 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 551 | static const u16 init_complete[] = { |
8ca151b5 JB |
552 | INIT_COMPLETE_NOTIF, |
553 | CALIB_RES_NOTIF_PHY_DB | |
554 | }; | |
555 | int ret; | |
556 | ||
7d6222e2 | 557 | if (iwl_mvm_has_unified_ucode(mvm)) |
8c5f47b1 JB |
558 | return iwl_run_unified_mvm_ucode(mvm, true); |
559 | ||
8ca151b5 JB |
560 | lockdep_assert_held(&mvm->mutex); |
561 | ||
94022562 | 562 | mvm->rfkill_safe_init_done = false; |
8ca151b5 JB |
563 | |
564 | iwl_init_notification_wait(&mvm->notif_wait, | |
565 | &calib_wait, | |
566 | init_complete, | |
567 | ARRAY_SIZE(init_complete), | |
568 | iwl_wait_phy_db_entry, | |
569 | mvm->phy_db); | |
570 | ||
571 | /* Will also start the device */ | |
572 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
573 | if (ret) { | |
574 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
00e0c6c8 | 575 | goto remove_notif; |
8ca151b5 JB |
576 | } |
577 | ||
7d34a7d7 | 578 | if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) { |
b3de3ef4 EG |
579 | ret = iwl_mvm_send_bt_init_conf(mvm); |
580 | if (ret) | |
00e0c6c8 | 581 | goto remove_notif; |
b3de3ef4 | 582 | } |
931d4160 | 583 | |
81a67e32 | 584 | /* Read the NVM only at driver load time, no need to do this twice */ |
8ca151b5 | 585 | if (read_nvm) { |
5bd1d2c1 | 586 | ret = iwl_nvm_init(mvm); |
8ca151b5 JB |
587 | if (ret) { |
588 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
00e0c6c8 | 589 | goto remove_notif; |
8ca151b5 JB |
590 | } |
591 | } | |
592 | ||
81a67e32 | 593 | /* In case we read the NVM from external file, load it to the NIC */ |
e02a9d60 | 594 | if (mvm->nvm_file_name) |
81a67e32 EL |
595 | iwl_mvm_load_nvm_to_nic(mvm); |
596 | ||
64866e5d LC |
597 | WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver, |
598 | "Too old NVM version (0x%0x, required = 0x%0x)", | |
599 | mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver); | |
8ca151b5 | 600 | |
4f59334b EH |
601 | /* |
602 | * abort after reading the nvm in case RF Kill is on, we will complete | |
603 | * the init seq later when RF kill will switch to off | |
604 | */ | |
1a3fe0b2 | 605 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
606 | IWL_DEBUG_RF_KILL(mvm, |
607 | "jump over all phy activities due to RF kill\n"); | |
00e0c6c8 | 608 | goto remove_notif; |
4f59334b EH |
609 | } |
610 | ||
b3500b47 | 611 | mvm->rfkill_safe_init_done = true; |
31b8b343 | 612 | |
e07cbb53 | 613 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 614 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 | 615 | if (ret) |
00e0c6c8 | 616 | goto remove_notif; |
e07cbb53 | 617 | |
8ca151b5 JB |
618 | ret = iwl_send_phy_cfg_cmd(mvm); |
619 | if (ret) { | |
620 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
621 | ret); | |
00e0c6c8 | 622 | goto remove_notif; |
8ca151b5 JB |
623 | } |
624 | ||
625 | /* | |
626 | * Some things may run in the background now, but we | |
627 | * just wait for the calibration complete notification. | |
628 | */ | |
629 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
00e0c6c8 LC |
630 | MVM_UCODE_CALIB_TIMEOUT); |
631 | if (!ret) | |
632 | goto out; | |
31b8b343 | 633 | |
00e0c6c8 | 634 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 | 635 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
00e0c6c8 LC |
636 | ret = 0; |
637 | } else { | |
638 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
639 | ret); | |
31b8b343 | 640 | } |
00e0c6c8 | 641 | |
8ca151b5 JB |
642 | goto out; |
643 | ||
00e0c6c8 | 644 | remove_notif: |
8ca151b5 JB |
645 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); |
646 | out: | |
b3500b47 | 647 | mvm->rfkill_safe_init_done = false; |
a4082843 | 648 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
649 | /* we want to debug INIT and we have no NVM - fake */ |
650 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
651 | sizeof(struct ieee80211_channel) + | |
652 | sizeof(struct ieee80211_rate), | |
653 | GFP_KERNEL); | |
654 | if (!mvm->nvm_data) | |
655 | return -ENOMEM; | |
8ca151b5 JB |
656 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
657 | mvm->nvm_data->bands[0].n_channels = 1; | |
658 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
659 | mvm->nvm_data->bands[0].bitrates = | |
660 | (void *)mvm->nvm_data->channels + 1; | |
661 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
662 | } | |
663 | ||
664 | return ret; | |
665 | } | |
666 | ||
84bfffa9 EG |
667 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
668 | { | |
669 | struct iwl_ltr_config_cmd cmd = { | |
670 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
671 | }; | |
672 | ||
673 | if (!mvm->trans->ltr_enabled) | |
674 | return 0; | |
675 | ||
84bfffa9 EG |
676 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
677 | sizeof(cmd), &cmd); | |
678 | } | |
679 | ||
c386dacb | 680 | #ifdef CONFIG_ACPI |
42ce76d6 | 681 | int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) |
da2830ac | 682 | { |
0791c2fc HD |
683 | union { |
684 | struct iwl_dev_tx_power_cmd v5; | |
685 | struct iwl_dev_tx_power_cmd_v4 v4; | |
686 | } cmd; | |
da2830ac | 687 | |
39c1a972 | 688 | u16 len = 0; |
42ce76d6 | 689 | |
0791c2fc HD |
690 | cmd.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS); |
691 | ||
692 | if (fw_has_api(&mvm->fw->ucode_capa, | |
693 | IWL_UCODE_TLV_API_REDUCE_TX_POWER)) | |
694 | len = sizeof(cmd.v5); | |
695 | else if (fw_has_capa(&mvm->fw->ucode_capa, | |
696 | IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) | |
39c1a972 | 697 | len = sizeof(struct iwl_dev_tx_power_cmd_v4); |
0791c2fc HD |
698 | else |
699 | len = sizeof(cmd.v4.v3); | |
55bfa4b9 | 700 | |
da2830ac | 701 | |
39c1a972 IZ |
702 | if (iwl_sar_select_profile(&mvm->fwrt, cmd.v5.v3.per_chain_restriction, |
703 | prof_a, prof_b)) | |
704 | return -ENOENT; | |
42ce76d6 | 705 | IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); |
42ce76d6 LC |
706 | return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); |
707 | } | |
708 | ||
7fe90e0e HD |
709 | int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) |
710 | { | |
39c1a972 | 711 | union geo_tx_power_profiles_cmd geo_tx_cmd; |
0c3d7282 | 712 | u16 len; |
39c1a972 | 713 | int ret; |
0c3d7282 HD |
714 | struct iwl_host_cmd cmd; |
715 | ||
39c1a972 IZ |
716 | if (fw_has_api(&mvm->fwrt.fw->ucode_capa, |
717 | IWL_UCODE_TLV_API_SAR_TABLE_VER)) { | |
718 | geo_tx_cmd.geo_cmd.ops = | |
0c3d7282 | 719 | cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); |
39c1a972 | 720 | len = sizeof(geo_tx_cmd.geo_cmd); |
0c3d7282 | 721 | } else { |
39c1a972 | 722 | geo_tx_cmd.geo_cmd_v1.ops = |
0c3d7282 | 723 | cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); |
39c1a972 | 724 | len = sizeof(geo_tx_cmd.geo_cmd_v1); |
0c3d7282 | 725 | } |
7fe90e0e | 726 | |
39c1a972 IZ |
727 | if (!iwl_sar_geo_support(&mvm->fwrt)) |
728 | return -EOPNOTSUPP; | |
729 | ||
0c3d7282 | 730 | cmd = (struct iwl_host_cmd){ |
7fe90e0e | 731 | .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), |
0c3d7282 | 732 | .len = { len, }, |
7fe90e0e | 733 | .flags = CMD_WANT_SKB, |
39c1a972 | 734 | .data = { &geo_tx_cmd }, |
7fe90e0e HD |
735 | }; |
736 | ||
737 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
738 | if (ret) { | |
739 | IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); | |
740 | return ret; | |
741 | } | |
39c1a972 | 742 | ret = iwl_validate_sar_geo_profile(&mvm->fwrt, &cmd); |
7fe90e0e HD |
743 | iwl_free_resp(&cmd); |
744 | return ret; | |
745 | } | |
746 | ||
a6bff3cb HD |
747 | static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) |
748 | { | |
a6bff3cb | 749 | u16 cmd_wide_id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT); |
39c1a972 IZ |
750 | union geo_tx_power_profiles_cmd cmd; |
751 | u16 len; | |
a6bff3cb | 752 | |
39c1a972 | 753 | cmd.geo_cmd.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES); |
a6bff3cb | 754 | |
39c1a972 | 755 | iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table); |
a6bff3cb | 756 | |
39c1a972 | 757 | cmd.geo_cmd.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); |
0c3d7282 | 758 | |
39c1a972 IZ |
759 | if (!fw_has_api(&mvm->fwrt.fw->ucode_capa, |
760 | IWL_UCODE_TLV_API_SAR_TABLE_VER)) { | |
761 | len = sizeof(struct iwl_geo_tx_power_profiles_cmd_v1); | |
762 | } else { | |
763 | len = sizeof(cmd.geo_cmd); | |
0c3d7282 HD |
764 | } |
765 | ||
39c1a972 | 766 | return iwl_mvm_send_cmd_pdu(mvm, cmd_wide_id, 0, len, &cmd); |
a6bff3cb HD |
767 | } |
768 | ||
6ce1e5c0 GA |
769 | static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm) |
770 | { | |
771 | union acpi_object *wifi_pkg, *data, *enabled; | |
772 | int i, j, ret, tbl_rev; | |
773 | int idx = 2; | |
774 | ||
39c1a972 | 775 | mvm->fwrt.ppag_table.enabled = cpu_to_le32(0); |
6ce1e5c0 GA |
776 | data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD); |
777 | if (IS_ERR(data)) | |
778 | return PTR_ERR(data); | |
779 | ||
780 | wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, | |
781 | ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev); | |
782 | ||
3ed83da3 | 783 | if (IS_ERR(wifi_pkg)) { |
6ce1e5c0 GA |
784 | ret = PTR_ERR(wifi_pkg); |
785 | goto out_free; | |
786 | } | |
787 | ||
3ed83da3 LC |
788 | if (tbl_rev != 0) { |
789 | ret = -EINVAL; | |
790 | goto out_free; | |
791 | } | |
792 | ||
6ce1e5c0 GA |
793 | enabled = &wifi_pkg->package.elements[1]; |
794 | if (enabled->type != ACPI_TYPE_INTEGER || | |
795 | (enabled->integer.value != 0 && enabled->integer.value != 1)) { | |
796 | ret = -EINVAL; | |
797 | goto out_free; | |
798 | } | |
799 | ||
39c1a972 IZ |
800 | mvm->fwrt.ppag_table.enabled = cpu_to_le32(enabled->integer.value); |
801 | if (!mvm->fwrt.ppag_table.enabled) { | |
6ce1e5c0 GA |
802 | ret = 0; |
803 | goto out_free; | |
804 | } | |
805 | ||
806 | /* | |
807 | * read, verify gain values and save them into the PPAG table. | |
808 | * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the | |
809 | * following sub-bands to High-Band (5GHz). | |
810 | */ | |
811 | for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) { | |
812 | for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) { | |
813 | union acpi_object *ent; | |
814 | ||
815 | ent = &wifi_pkg->package.elements[idx++]; | |
816 | if (ent->type != ACPI_TYPE_INTEGER || | |
817 | (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) || | |
818 | (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) || | |
819 | (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) || | |
820 | (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) { | |
39c1a972 | 821 | mvm->fwrt.ppag_table.enabled = cpu_to_le32(0); |
6ce1e5c0 GA |
822 | ret = -EINVAL; |
823 | goto out_free; | |
824 | } | |
39c1a972 | 825 | mvm->fwrt.ppag_table.gain[i][j] = ent->integer.value; |
6ce1e5c0 GA |
826 | } |
827 | } | |
828 | ret = 0; | |
829 | out_free: | |
830 | kfree(data); | |
831 | return ret; | |
832 | } | |
833 | ||
834 | int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) | |
835 | { | |
836 | int i, j, ret; | |
837 | ||
838 | if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) { | |
839 | IWL_DEBUG_RADIO(mvm, | |
840 | "PPAG capability not supported by FW, command not sent.\n"); | |
841 | return 0; | |
842 | } | |
843 | ||
844 | IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n"); | |
845 | IWL_DEBUG_RADIO(mvm, "PPAG is %s\n", | |
39c1a972 | 846 | mvm->fwrt.ppag_table.enabled ? "enabled" : "disabled"); |
6ce1e5c0 GA |
847 | |
848 | for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) { | |
849 | for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) { | |
850 | IWL_DEBUG_RADIO(mvm, | |
851 | "PPAG table: chain[%d] band[%d]: gain = %d\n", | |
39c1a972 | 852 | i, j, mvm->fwrt.ppag_table.gain[i][j]); |
6ce1e5c0 GA |
853 | } |
854 | } | |
855 | ||
856 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP, | |
857 | PER_PLATFORM_ANT_GAIN_CMD), | |
39c1a972 IZ |
858 | 0, sizeof(mvm->fwrt.ppag_table), |
859 | &mvm->fwrt.ppag_table); | |
6ce1e5c0 GA |
860 | if (ret < 0) |
861 | IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n", | |
862 | ret); | |
863 | ||
864 | return ret; | |
865 | } | |
866 | ||
867 | static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) | |
868 | { | |
869 | int ret; | |
870 | ||
871 | ret = iwl_mvm_get_ppag_table(mvm); | |
872 | if (ret < 0) { | |
873 | IWL_DEBUG_RADIO(mvm, | |
874 | "PPAG BIOS table invalid or unavailable. (%d)\n", | |
875 | ret); | |
876 | return 0; | |
877 | } | |
878 | return iwl_mvm_ppag_send_cmd(mvm); | |
879 | } | |
880 | ||
69964905 | 881 | #else /* CONFIG_ACPI */ |
69964905 | 882 | |
39c1a972 IZ |
883 | inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, |
884 | int prof_a, int prof_b) | |
69964905 LC |
885 | { |
886 | return -ENOENT; | |
887 | } | |
a6bff3cb | 888 | |
39c1a972 | 889 | inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) |
5d041c46 LC |
890 | { |
891 | return -ENOENT; | |
892 | } | |
893 | ||
a6bff3cb HD |
894 | static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) |
895 | { | |
896 | return 0; | |
897 | } | |
18f1755d | 898 | |
6ce1e5c0 GA |
899 | int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) |
900 | { | |
901 | return -ENOENT; | |
902 | } | |
903 | ||
904 | static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) | |
905 | { | |
7937fd32 | 906 | return 0; |
6ce1e5c0 | 907 | } |
69964905 LC |
908 | #endif /* CONFIG_ACPI */ |
909 | ||
f130bb75 MG |
910 | void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags) |
911 | { | |
912 | u32 error_log_size = mvm->fw->ucode_capa.error_log_size; | |
913 | int ret; | |
914 | u32 resp; | |
915 | ||
916 | struct iwl_fw_error_recovery_cmd recovery_cmd = { | |
917 | .flags = cpu_to_le32(flags), | |
918 | .buf_size = 0, | |
919 | }; | |
920 | struct iwl_host_cmd host_cmd = { | |
921 | .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD), | |
922 | .flags = CMD_WANT_SKB, | |
923 | .data = {&recovery_cmd, }, | |
924 | .len = {sizeof(recovery_cmd), }, | |
925 | }; | |
926 | ||
927 | /* no error log was defined in TLV */ | |
928 | if (!error_log_size) | |
929 | return; | |
930 | ||
931 | if (flags & ERROR_RECOVERY_UPDATE_DB) { | |
932 | /* no buf was allocated while HW reset */ | |
933 | if (!mvm->error_recovery_buf) | |
934 | return; | |
935 | ||
936 | host_cmd.data[1] = mvm->error_recovery_buf; | |
937 | host_cmd.len[1] = error_log_size; | |
938 | host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; | |
939 | recovery_cmd.buf_size = cpu_to_le32(error_log_size); | |
940 | } | |
941 | ||
942 | ret = iwl_mvm_send_cmd(mvm, &host_cmd); | |
943 | kfree(mvm->error_recovery_buf); | |
944 | mvm->error_recovery_buf = NULL; | |
945 | ||
946 | if (ret) { | |
947 | IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret); | |
948 | return; | |
949 | } | |
950 | ||
951 | /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */ | |
952 | if (flags & ERROR_RECOVERY_UPDATE_DB) { | |
953 | resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data); | |
954 | if (resp) | |
955 | IWL_ERR(mvm, | |
956 | "Failed to send recovery cmd blob was invalid %d\n", | |
957 | resp); | |
958 | } | |
959 | } | |
960 | ||
42ce76d6 LC |
961 | static int iwl_mvm_sar_init(struct iwl_mvm *mvm) |
962 | { | |
963 | int ret; | |
964 | ||
39c1a972 | 965 | ret = iwl_sar_get_wrds_table(&mvm->fwrt); |
42ce76d6 LC |
966 | if (ret < 0) { |
967 | IWL_DEBUG_RADIO(mvm, | |
69964905 | 968 | "WRDS SAR BIOS table invalid or unavailable. (%d)\n", |
42ce76d6 | 969 | ret); |
5d041c46 LC |
970 | /* |
971 | * If not available, don't fail and don't bother with EWRD. | |
972 | * Return 1 to tell that we can't use WGDS either. | |
973 | */ | |
974 | return 1; | |
42ce76d6 LC |
975 | } |
976 | ||
39c1a972 | 977 | ret = iwl_sar_get_ewrd_table(&mvm->fwrt); |
69964905 LC |
978 | /* if EWRD is not available, we can still use WRDS, so don't fail */ |
979 | if (ret < 0) | |
980 | IWL_DEBUG_RADIO(mvm, | |
981 | "EWRD SAR BIOS table invalid or unavailable. (%d)\n", | |
982 | ret); | |
983 | ||
42ce76d6 | 984 | ret = iwl_mvm_sar_select_profile(mvm, 1, 1); |
5d041c46 LC |
985 | /* |
986 | * If we don't have profile 0 from BIOS, just skip it. This | |
987 | * means that SAR Geo will not be enabled either, even if we | |
988 | * have other valid profiles. | |
989 | */ | |
42ce76d6 | 990 | if (ret == -ENOENT) |
5d041c46 | 991 | return 1; |
da2830ac LC |
992 | |
993 | return ret; | |
994 | } | |
995 | ||
1f370650 | 996 | static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) |
8ca151b5 | 997 | { |
1f370650 | 998 | int ret; |
8ca151b5 | 999 | |
7d6222e2 | 1000 | if (iwl_mvm_has_unified_ucode(mvm)) |
1f370650 | 1001 | return iwl_run_unified_mvm_ucode(mvm, false); |
8ca151b5 | 1002 | |
8d193ca2 | 1003 | ret = iwl_run_init_mvm_ucode(mvm, false); |
f2082a53 | 1004 | |
f2082a53 | 1005 | if (ret) { |
8d193ca2 | 1006 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); |
f4744258 LK |
1007 | |
1008 | if (iwlmvm_mod_params.init_dbg) | |
1009 | return 0; | |
1f370650 | 1010 | return ret; |
8d193ca2 | 1011 | } |
8ca151b5 | 1012 | |
203c83d3 | 1013 | iwl_fw_dbg_stop_sync(&mvm->fwrt); |
bab3cb92 EG |
1014 | iwl_trans_stop_device(mvm->trans); |
1015 | ret = iwl_trans_start_hw(mvm->trans); | |
f2082a53 | 1016 | if (ret) |
1f370650 | 1017 | return ret; |
8ca151b5 | 1018 | |
b108d8c7 | 1019 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); |
da2eb669 | 1020 | |
94022562 | 1021 | mvm->rfkill_safe_init_done = false; |
8ca151b5 | 1022 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); |
1f370650 SS |
1023 | if (ret) |
1024 | return ret; | |
1025 | ||
94022562 EG |
1026 | mvm->rfkill_safe_init_done = true; |
1027 | ||
b108d8c7 SM |
1028 | iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, |
1029 | NULL); | |
da2eb669 | 1030 | |
702e975d | 1031 | return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); |
1f370650 SS |
1032 | } |
1033 | ||
1034 | int iwl_mvm_up(struct iwl_mvm *mvm) | |
1035 | { | |
1036 | int ret, i; | |
1037 | struct ieee80211_channel *chan; | |
1038 | struct cfg80211_chan_def chandef; | |
dd36a507 | 1039 | struct ieee80211_supported_band *sband = NULL; |
1f370650 SS |
1040 | |
1041 | lockdep_assert_held(&mvm->mutex); | |
1042 | ||
1043 | ret = iwl_trans_start_hw(mvm->trans); | |
1044 | if (ret) | |
1045 | return ret; | |
1046 | ||
1047 | ret = iwl_mvm_load_rt_fw(mvm); | |
8ca151b5 JB |
1048 | if (ret) { |
1049 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
72d3c7bb JB |
1050 | if (ret != -ERFKILL) |
1051 | iwl_fw_dbg_error_collect(&mvm->fwrt, | |
1052 | FW_DBG_TRIGGER_DRIVER); | |
8ca151b5 JB |
1053 | goto error; |
1054 | } | |
1055 | ||
d0b813fc | 1056 | iwl_get_shared_mem_conf(&mvm->fwrt); |
04fd2c28 | 1057 | |
1f3b0ff8 LE |
1058 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
1059 | if (ret) | |
1060 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
1061 | ||
a1af4c48 | 1062 | if (!iwl_trans_dbg_ini_valid(mvm->trans)) { |
7a14c23d SS |
1063 | mvm->fwrt.dump.conf = FW_DBG_INVALID; |
1064 | /* if we have a destination, assume EARLY START */ | |
1065 | if (mvm->fw->dbg.dest_tlv) | |
1066 | mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; | |
1067 | iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); | |
1068 | } | |
6a951267 | 1069 | |
a0544272 | 1070 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1071 | if (ret) |
1072 | goto error; | |
1073 | ||
7d6222e2 JB |
1074 | if (!iwl_mvm_has_unified_ucode(mvm)) { |
1075 | /* Send phy db control command and then phy db calibration */ | |
1f370650 SS |
1076 | ret = iwl_send_phy_db_data(mvm->phy_db); |
1077 | if (ret) | |
1078 | goto error; | |
1f370650 | 1079 | } |
8ca151b5 | 1080 | |
bb99ff9b LC |
1081 | ret = iwl_send_phy_cfg_cmd(mvm); |
1082 | if (ret) | |
1083 | goto error; | |
1084 | ||
b3de3ef4 EG |
1085 | ret = iwl_mvm_send_bt_init_conf(mvm); |
1086 | if (ret) | |
1087 | goto error; | |
1088 | ||
43413a97 | 1089 | /* Init RSS configuration */ |
286ca8eb | 1090 | if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { |
8edbfaa1 SS |
1091 | ret = iwl_configure_rxq(mvm); |
1092 | if (ret) { | |
1093 | IWL_ERR(mvm, "Failed to configure RX queues: %d\n", | |
1094 | ret); | |
1095 | goto error; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | if (iwl_mvm_has_new_rx_api(mvm)) { | |
43413a97 SS |
1100 | ret = iwl_send_rss_cfg_cmd(mvm); |
1101 | if (ret) { | |
1102 | IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", | |
1103 | ret); | |
1104 | goto error; | |
1105 | } | |
1106 | } | |
1107 | ||
8ca151b5 | 1108 | /* init the fw <-> mac80211 STA mapping */ |
0ae98812 | 1109 | for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) |
8ca151b5 JB |
1110 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); |
1111 | ||
0ae98812 | 1112 | mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; |
1d3c3f63 | 1113 | |
b2b7875b JB |
1114 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
1115 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
1116 | ||
79660869 IL |
1117 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) { |
1118 | ret = iwl_mvm_send_dqa_cmd(mvm); | |
1119 | if (ret) | |
1120 | goto error; | |
1121 | } | |
97d5be7e | 1122 | |
8ca151b5 JB |
1123 | /* Add auxiliary station for scanning */ |
1124 | ret = iwl_mvm_add_aux_sta(mvm); | |
1125 | if (ret) | |
1126 | goto error; | |
1127 | ||
53a9d61e | 1128 | /* Add all the PHY contexts */ |
dd36a507 TM |
1129 | i = 0; |
1130 | while (!sband && i < NUM_NL80211_BANDS) | |
1131 | sband = mvm->hw->wiphy->bands[i++]; | |
1132 | ||
1133 | if (WARN_ON_ONCE(!sband)) | |
1134 | goto error; | |
1135 | ||
1136 | chan = &sband->channels[0]; | |
1137 | ||
53a9d61e IP |
1138 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); |
1139 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
1140 | /* | |
1141 | * The channel used here isn't relevant as it's | |
1142 | * going to be overwritten in the other flows. | |
1143 | * For now use the first channel we have. | |
1144 | */ | |
1145 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
1146 | &chandef, 1, 1); | |
1147 | if (ret) | |
1148 | goto error; | |
1149 | } | |
8ca151b5 | 1150 | |
c221daf2 CRI |
1151 | if (iwl_mvm_is_tt_in_fw(mvm)) { |
1152 | /* in order to give the responsibility of ct-kill and | |
1153 | * TX backoff to FW we need to send empty temperature reporting | |
1154 | * cmd during init time | |
1155 | */ | |
1156 | iwl_mvm_send_temp_report_ths_cmd(mvm); | |
1157 | } else { | |
1158 | /* Initialize tx backoffs to the minimal possible */ | |
1159 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
1160 | } | |
5c89e7bc | 1161 | |
242d9c8b | 1162 | #ifdef CONFIG_THERMAL |
5c89e7bc | 1163 | /* TODO: read the budget from BIOS / Platform NVM */ |
944eafc2 CRI |
1164 | |
1165 | /* | |
1166 | * In case there is no budget from BIOS / Platform NVM the default | |
1167 | * budget should be 2000mW (cooling state 0). | |
1168 | */ | |
1169 | if (iwl_mvm_is_ctdp_supported(mvm)) { | |
5c89e7bc CRI |
1170 | ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, |
1171 | mvm->cooling_dev.cur_state); | |
75cfe338 LC |
1172 | if (ret) |
1173 | goto error; | |
1174 | } | |
c221daf2 | 1175 | #endif |
0c0e2c71 | 1176 | |
aa43ae12 AM |
1177 | if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2)) |
1178 | WARN_ON(iwl_mvm_config_ltr(mvm)); | |
9180ac50 | 1179 | |
c1cb92fc | 1180 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
1181 | if (ret) |
1182 | goto error; | |
1183 | ||
35af15d1 AN |
1184 | /* |
1185 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
1186 | * anyway, so don't init MCC. | |
1187 | */ | |
1188 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
1189 | ret = iwl_mvm_init_mcc(mvm); | |
1190 | if (ret) | |
1191 | goto error; | |
1192 | } | |
90d4f7db | 1193 | |
859d914c | 1194 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
4ca87a5f | 1195 | mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; |
b66b5817 | 1196 | mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; |
d2496221 DS |
1197 | ret = iwl_mvm_config_scan(mvm); |
1198 | if (ret) | |
1199 | goto error; | |
1200 | } | |
1201 | ||
f130bb75 MG |
1202 | if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) |
1203 | iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB); | |
1204 | ||
48e775e6 HD |
1205 | if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid)) |
1206 | IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n"); | |
1207 | ||
6ce1e5c0 GA |
1208 | ret = iwl_mvm_ppag_init(mvm); |
1209 | if (ret) | |
1210 | goto error; | |
1211 | ||
da2830ac | 1212 | ret = iwl_mvm_sar_init(mvm); |
5d041c46 LC |
1213 | if (ret == 0) { |
1214 | ret = iwl_mvm_sar_geo_init(mvm); | |
39c1a972 | 1215 | } else if (ret > 0 && !iwl_sar_get_wgds_table(&mvm->fwrt)) { |
5d041c46 LC |
1216 | /* |
1217 | * If basic SAR is not available, we check for WGDS, | |
1218 | * which should *not* be available either. If it is | |
1219 | * available, issue an error, because we can't use SAR | |
1220 | * Geo without basic SAR. | |
1221 | */ | |
1222 | IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); | |
1223 | } | |
da2830ac | 1224 | |
5d041c46 | 1225 | if (ret < 0) |
a6bff3cb HD |
1226 | goto error; |
1227 | ||
7089ae63 JB |
1228 | iwl_mvm_leds_sync(mvm); |
1229 | ||
53a9d61e | 1230 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
1231 | return 0; |
1232 | error: | |
f4744258 | 1233 | if (!iwlmvm_mod_params.init_dbg || !ret) |
de8ba41b | 1234 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1235 | return ret; |
1236 | } | |
1237 | ||
1238 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
1239 | { | |
1240 | int ret, i; | |
1241 | ||
1242 | lockdep_assert_held(&mvm->mutex); | |
1243 | ||
1244 | ret = iwl_trans_start_hw(mvm->trans); | |
1245 | if (ret) | |
1246 | return ret; | |
1247 | ||
1248 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
1249 | if (ret) { | |
1250 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
1251 | goto error; | |
1252 | } | |
1253 | ||
a0544272 | 1254 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1255 | if (ret) |
1256 | goto error; | |
1257 | ||
1258 | /* Send phy db control command and then phy db calibration*/ | |
1259 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1260 | if (ret) | |
1261 | goto error; | |
1262 | ||
1263 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1264 | if (ret) | |
1265 | goto error; | |
1266 | ||
1267 | /* init the fw <-> mac80211 STA mapping */ | |
0ae98812 | 1268 | for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) |
8ca151b5 JB |
1269 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); |
1270 | ||
1271 | /* Add auxiliary station for scanning */ | |
1272 | ret = iwl_mvm_add_aux_sta(mvm); | |
1273 | if (ret) | |
1274 | goto error; | |
1275 | ||
1276 | return 0; | |
1277 | error: | |
fcb6b92a | 1278 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1279 | return ret; |
1280 | } | |
1281 | ||
0416841d JB |
1282 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1283 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1284 | { |
1285 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1286 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1287 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1288 | ||
1289 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1290 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1291 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1292 | (flags & CT_KILL_CARD_DISABLED) ? | |
1293 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1294 | } |
1295 | ||
0416841d JB |
1296 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1297 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1298 | { |
1299 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1300 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1301 | ||
0c8d0a47 GBA |
1302 | IWL_DEBUG_INFO(mvm, |
1303 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1304 | le32_to_cpu(mfuart_notif->installed_ver), | |
1305 | le32_to_cpu(mfuart_notif->external_ver), | |
1306 | le32_to_cpu(mfuart_notif->status), | |
1307 | le32_to_cpu(mfuart_notif->duration)); | |
1308 | ||
19f63c53 GBA |
1309 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) |
1310 | IWL_DEBUG_INFO(mvm, | |
0c8d0a47 | 1311 | "MFUART: image size: 0x%08x\n", |
19f63c53 | 1312 | le32_to_cpu(mfuart_notif->image_size)); |
30269c12 | 1313 | } |