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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
43413a97 | 10 | * Copyright(c) 2016 Intel Deutschland GmbH |
8ca151b5 JB |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
24 | * USA | |
25 | * | |
26 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 27 | * in the file called COPYING. |
8ca151b5 JB |
28 | * |
29 | * Contact Information: | |
cb2f8277 | 30 | * Intel Linux Wireless <linuxwifi@intel.com> |
8ca151b5 JB |
31 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
32 | * | |
33 | * BSD LICENSE | |
34 | * | |
51368bf7 | 35 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 36 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
8ca151b5 JB |
37 | * All rights reserved. |
38 | * | |
39 | * Redistribution and use in source and binary forms, with or without | |
40 | * modification, are permitted provided that the following conditions | |
41 | * are met: | |
42 | * | |
43 | * * Redistributions of source code must retain the above copyright | |
44 | * notice, this list of conditions and the following disclaimer. | |
45 | * * Redistributions in binary form must reproduce the above copyright | |
46 | * notice, this list of conditions and the following disclaimer in | |
47 | * the documentation and/or other materials provided with the | |
48 | * distribution. | |
49 | * * Neither the name Intel Corporation nor the names of its | |
50 | * contributors may be used to endorse or promote products derived | |
51 | * from this software without specific prior written permission. | |
52 | * | |
53 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
54 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
55 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
56 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
57 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
58 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
59 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
60 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
61 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
62 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
64 | * | |
65 | *****************************************************************************/ | |
66 | #include <net/mac80211.h> | |
854d773e | 67 | #include <linux/netdevice.h> |
da2830ac | 68 | #include <linux/acpi.h> |
8ca151b5 JB |
69 | |
70 | #include "iwl-trans.h" | |
71 | #include "iwl-op-mode.h" | |
72 | #include "iwl-fw.h" | |
73 | #include "iwl-debug.h" | |
74 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
75 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 76 | #include "iwl-prph.h" |
8ca151b5 JB |
77 | #include "iwl-eeprom-parse.h" |
78 | ||
79 | #include "mvm.h" | |
2f89a5d7 | 80 | #include "fw-dbg.h" |
8ca151b5 JB |
81 | #include "iwl-phy-db.h" |
82 | ||
83 | #define MVM_UCODE_ALIVE_TIMEOUT HZ | |
84 | #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) | |
85 | ||
86 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
87 | ||
8ca151b5 JB |
88 | struct iwl_mvm_alive_data { |
89 | bool valid; | |
90 | u32 scd_base_addr; | |
91 | }; | |
92 | ||
93 | static inline const struct fw_img * | |
94 | iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) | |
95 | { | |
96 | if (ucode_type >= IWL_UCODE_TYPE_MAX) | |
97 | return NULL; | |
98 | ||
99 | return &mvm->fw->img[ucode_type]; | |
100 | } | |
101 | ||
102 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) | |
103 | { | |
104 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
105 | .valid = cpu_to_le32(valid_tx_ant), | |
106 | }; | |
107 | ||
33223542 | 108 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 109 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
110 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
111 | } | |
112 | ||
43413a97 SS |
113 | static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) |
114 | { | |
115 | int i; | |
116 | struct iwl_rss_config_cmd cmd = { | |
117 | .flags = cpu_to_le32(IWL_RSS_ENABLE), | |
118 | .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP | | |
854d773e | 119 | IWL_RSS_HASH_TYPE_IPV4_UDP | |
43413a97 SS |
120 | IWL_RSS_HASH_TYPE_IPV4_PAYLOAD | |
121 | IWL_RSS_HASH_TYPE_IPV6_TCP | | |
854d773e | 122 | IWL_RSS_HASH_TYPE_IPV6_UDP | |
43413a97 SS |
123 | IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, |
124 | }; | |
125 | ||
f43495fd SS |
126 | if (mvm->trans->num_rx_queues == 1) |
127 | return 0; | |
128 | ||
854d773e | 129 | /* Do not direct RSS traffic to Q 0 which is our fallback queue */ |
43413a97 | 130 | for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) |
854d773e SS |
131 | cmd.indirection_table[i] = |
132 | 1 + (i % (mvm->trans->num_rx_queues - 1)); | |
133 | netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); | |
43413a97 SS |
134 | |
135 | return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); | |
136 | } | |
137 | ||
97d5be7e LK |
138 | static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) |
139 | { | |
140 | struct iwl_dqa_enable_cmd dqa_cmd = { | |
141 | .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), | |
142 | }; | |
143 | u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); | |
144 | int ret; | |
145 | ||
146 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); | |
147 | if (ret) | |
148 | IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); | |
149 | else | |
150 | IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
905e36ae | 155 | void iwl_free_fw_paging(struct iwl_mvm *mvm) |
a6c4fb44 MG |
156 | { |
157 | int i; | |
158 | ||
159 | if (!mvm->fw_paging_db[0].fw_paging_block) | |
160 | return; | |
161 | ||
162 | for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) { | |
3edbc7da EG |
163 | struct iwl_fw_paging *paging = &mvm->fw_paging_db[i]; |
164 | ||
165 | if (!paging->fw_paging_block) { | |
a6c4fb44 MG |
166 | IWL_DEBUG_FW(mvm, |
167 | "Paging: block %d already freed, continue to next page\n", | |
168 | i); | |
169 | ||
170 | continue; | |
171 | } | |
3edbc7da EG |
172 | dma_unmap_page(mvm->trans->dev, paging->fw_paging_phys, |
173 | paging->fw_paging_size, DMA_BIDIRECTIONAL); | |
a6c4fb44 | 174 | |
3edbc7da EG |
175 | __free_pages(paging->fw_paging_block, |
176 | get_order(paging->fw_paging_size)); | |
177 | paging->fw_paging_block = NULL; | |
a6c4fb44 | 178 | } |
e1120187 | 179 | kfree(mvm->trans->paging_download_buf); |
905e36ae | 180 | mvm->trans->paging_download_buf = NULL; |
f742aaf3 | 181 | mvm->trans->paging_db = NULL; |
905e36ae | 182 | |
a6c4fb44 MG |
183 | memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db)); |
184 | } | |
185 | ||
186 | static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image) | |
187 | { | |
188 | int sec_idx, idx; | |
189 | u32 offset = 0; | |
190 | ||
191 | /* | |
192 | * find where is the paging image start point: | |
193 | * if CPU2 exist and it's in paging format, then the image looks like: | |
194 | * CPU1 sections (2 or more) | |
195 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2 | |
196 | * CPU2 sections (not paged) | |
197 | * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2 | |
198 | * non paged to CPU2 paging sec | |
199 | * CPU2 paging CSS | |
200 | * CPU2 paging image (including instruction and data) | |
201 | */ | |
202 | for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) { | |
203 | if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) { | |
204 | sec_idx++; | |
205 | break; | |
206 | } | |
207 | } | |
208 | ||
cd47a3d3 MG |
209 | /* |
210 | * If paging is enabled there should be at least 2 more sections left | |
211 | * (one for CSS and one for Paging data) | |
212 | */ | |
213 | if (sec_idx >= ARRAY_SIZE(image->sec) - 1) { | |
214 | IWL_ERR(mvm, "Paging: Missing CSS and/or paging sections\n"); | |
a6c4fb44 MG |
215 | iwl_free_fw_paging(mvm); |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | /* copy the CSS block to the dram */ | |
220 | IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n", | |
221 | sec_idx); | |
222 | ||
223 | memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block), | |
224 | image->sec[sec_idx].data, | |
225 | mvm->fw_paging_db[0].fw_paging_size); | |
226 | ||
227 | IWL_DEBUG_FW(mvm, | |
228 | "Paging: copied %d CSS bytes to first block\n", | |
229 | mvm->fw_paging_db[0].fw_paging_size); | |
230 | ||
231 | sec_idx++; | |
232 | ||
233 | /* | |
234 | * copy the paging blocks to the dram | |
235 | * loop index start from 1 since that CSS block already copied to dram | |
236 | * and CSS index is 0. | |
237 | * loop stop at num_of_paging_blk since that last block is not full. | |
238 | */ | |
239 | for (idx = 1; idx < mvm->num_of_paging_blk; idx++) { | |
240 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
241 | image->sec[sec_idx].data + offset, | |
242 | mvm->fw_paging_db[idx].fw_paging_size); | |
243 | ||
244 | IWL_DEBUG_FW(mvm, | |
245 | "Paging: copied %d paging bytes to block %d\n", | |
246 | mvm->fw_paging_db[idx].fw_paging_size, | |
247 | idx); | |
248 | ||
249 | offset += mvm->fw_paging_db[idx].fw_paging_size; | |
250 | } | |
251 | ||
252 | /* copy the last paging block */ | |
253 | if (mvm->num_of_pages_in_last_blk > 0) { | |
254 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
255 | image->sec[sec_idx].data + offset, | |
256 | FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk); | |
257 | ||
258 | IWL_DEBUG_FW(mvm, | |
259 | "Paging: copied %d pages in the last block %d\n", | |
260 | mvm->num_of_pages_in_last_blk, idx); | |
261 | } | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm, | |
267 | const struct fw_img *image) | |
268 | { | |
269 | struct page *block; | |
270 | dma_addr_t phys = 0; | |
271 | int blk_idx = 0; | |
272 | int order, num_of_pages; | |
273 | int dma_enabled; | |
274 | ||
275 | if (mvm->fw_paging_db[0].fw_paging_block) | |
276 | return 0; | |
277 | ||
278 | dma_enabled = is_device_dma_capable(mvm->trans->dev); | |
279 | ||
280 | /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */ | |
281 | BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); | |
282 | ||
283 | num_of_pages = image->paging_mem_size / FW_PAGING_SIZE; | |
284 | mvm->num_of_paging_blk = ((num_of_pages - 1) / | |
285 | NUM_OF_PAGE_PER_GROUP) + 1; | |
286 | ||
287 | mvm->num_of_pages_in_last_blk = | |
288 | num_of_pages - | |
289 | NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1); | |
290 | ||
291 | IWL_DEBUG_FW(mvm, | |
292 | "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n", | |
293 | mvm->num_of_paging_blk, | |
294 | mvm->num_of_pages_in_last_blk); | |
295 | ||
296 | /* allocate block of 4Kbytes for paging CSS */ | |
297 | order = get_order(FW_PAGING_SIZE); | |
298 | block = alloc_pages(GFP_KERNEL, order); | |
299 | if (!block) { | |
300 | /* free all the previous pages since we failed */ | |
301 | iwl_free_fw_paging(mvm); | |
302 | return -ENOMEM; | |
303 | } | |
304 | ||
305 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
306 | mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE; | |
307 | ||
308 | if (dma_enabled) { | |
309 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
310 | PAGE_SIZE << order, DMA_BIDIRECTIONAL); | |
311 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
312 | /* | |
313 | * free the previous pages and the current one since | |
314 | * we failed to map_page. | |
315 | */ | |
316 | iwl_free_fw_paging(mvm); | |
317 | return -ENOMEM; | |
318 | } | |
319 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
320 | } else { |
321 | mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG | | |
322 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
323 | } |
324 | ||
325 | IWL_DEBUG_FW(mvm, | |
326 | "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n", | |
327 | order); | |
328 | ||
329 | /* | |
330 | * allocate blocks in dram. | |
331 | * since that CSS allocated in fw_paging_db[0] loop start from index 1 | |
332 | */ | |
333 | for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
334 | /* allocate block of PAGING_BLOCK_SIZE (32K) */ | |
335 | order = get_order(PAGING_BLOCK_SIZE); | |
336 | block = alloc_pages(GFP_KERNEL, order); | |
337 | if (!block) { | |
338 | /* free all the previous pages since we failed */ | |
339 | iwl_free_fw_paging(mvm); | |
340 | return -ENOMEM; | |
341 | } | |
342 | ||
343 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
344 | mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE; | |
345 | ||
346 | if (dma_enabled) { | |
347 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
348 | PAGE_SIZE << order, | |
349 | DMA_BIDIRECTIONAL); | |
350 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
351 | /* | |
352 | * free the previous pages and the current one | |
353 | * since we failed to map_page. | |
354 | */ | |
355 | iwl_free_fw_paging(mvm); | |
356 | return -ENOMEM; | |
357 | } | |
358 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
359 | } else { |
360 | mvm->fw_paging_db[blk_idx].fw_paging_phys = | |
361 | PAGING_ADDR_SIG | | |
362 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
363 | } |
364 | ||
365 | IWL_DEBUG_FW(mvm, | |
366 | "Paging: allocated 32K bytes (order %d) for firmware paging.\n", | |
367 | order); | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int iwl_save_fw_paging(struct iwl_mvm *mvm, | |
374 | const struct fw_img *fw) | |
375 | { | |
376 | int ret; | |
377 | ||
378 | ret = iwl_alloc_fw_paging_mem(mvm, fw); | |
379 | if (ret) | |
380 | return ret; | |
381 | ||
382 | return iwl_fill_paging_mem(mvm, fw); | |
383 | } | |
384 | ||
385 | /* send paging cmd to FW in case CPU2 has paging image */ | |
386 | static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw) | |
387 | { | |
388 | int blk_idx; | |
389 | __le32 dev_phy_addr; | |
390 | struct iwl_fw_paging_cmd fw_paging_cmd = { | |
391 | .flags = | |
392 | cpu_to_le32(PAGING_CMD_IS_SECURED | | |
393 | PAGING_CMD_IS_ENABLED | | |
394 | (mvm->num_of_pages_in_last_blk << | |
395 | PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)), | |
396 | .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE), | |
397 | .block_num = cpu_to_le32(mvm->num_of_paging_blk), | |
398 | }; | |
399 | ||
400 | /* loop for for all paging blocks + CSS block */ | |
401 | for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
402 | dev_phy_addr = | |
403 | cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >> | |
404 | PAGE_2_EXP_SIZE); | |
405 | fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr; | |
406 | } | |
407 | ||
408 | return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD, | |
409 | IWL_ALWAYS_LONG_GROUP, 0), | |
410 | 0, sizeof(fw_paging_cmd), &fw_paging_cmd); | |
411 | } | |
412 | ||
e1120187 MG |
413 | /* |
414 | * Send paging item cmd to FW in case CPU2 has paging image | |
415 | */ | |
416 | static int iwl_trans_get_paging_item(struct iwl_mvm *mvm) | |
417 | { | |
418 | int ret; | |
419 | struct iwl_fw_get_item_cmd fw_get_item_cmd = { | |
420 | .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING), | |
421 | }; | |
422 | ||
423 | struct iwl_fw_get_item_resp *item_resp; | |
424 | struct iwl_host_cmd cmd = { | |
425 | .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0), | |
426 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, | |
427 | .data = { &fw_get_item_cmd, }, | |
428 | }; | |
429 | ||
430 | cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd); | |
431 | ||
432 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
433 | if (ret) { | |
434 | IWL_ERR(mvm, | |
435 | "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n", | |
436 | ret); | |
437 | return ret; | |
438 | } | |
439 | ||
440 | item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data; | |
441 | if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) { | |
442 | IWL_ERR(mvm, | |
443 | "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n", | |
444 | le32_to_cpu(item_resp->item_id)); | |
445 | ret = -EIO; | |
446 | goto exit; | |
447 | } | |
448 | ||
c94d7996 MG |
449 | /* Add an extra page for headers */ |
450 | mvm->trans->paging_download_buf = kzalloc(PAGING_BLOCK_SIZE + | |
451 | FW_PAGING_SIZE, | |
e1120187 MG |
452 | GFP_KERNEL); |
453 | if (!mvm->trans->paging_download_buf) { | |
454 | ret = -ENOMEM; | |
455 | goto exit; | |
456 | } | |
457 | mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val); | |
458 | mvm->trans->paging_db = mvm->fw_paging_db; | |
459 | IWL_DEBUG_FW(mvm, | |
460 | "Paging: got paging request address (paging_req_addr 0x%08x)\n", | |
461 | mvm->trans->paging_req_addr); | |
462 | ||
463 | exit: | |
464 | iwl_free_resp(&cmd); | |
465 | ||
466 | return ret; | |
467 | } | |
468 | ||
8ca151b5 JB |
469 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
470 | struct iwl_rx_packet *pkt, void *data) | |
471 | { | |
472 | struct iwl_mvm *mvm = | |
473 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
474 | struct iwl_mvm_alive_data *alive_data = data; | |
7e1223b5 | 475 | struct mvm_alive_resp_ver1 *palive1; |
01a9ca51 | 476 | struct mvm_alive_resp_ver2 *palive2; |
7e1223b5 | 477 | struct mvm_alive_resp *palive; |
01a9ca51 | 478 | |
7e1223b5 EG |
479 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) { |
480 | palive1 = (void *)pkt->data; | |
01a9ca51 EH |
481 | |
482 | mvm->support_umac_log = false; | |
483 | mvm->error_event_table = | |
7e1223b5 EG |
484 | le32_to_cpu(palive1->error_event_table_ptr); |
485 | mvm->log_event_table = | |
486 | le32_to_cpu(palive1->log_event_table_ptr); | |
487 | alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr); | |
01a9ca51 | 488 | |
7e1223b5 | 489 | alive_data->valid = le16_to_cpu(palive1->status) == |
01a9ca51 EH |
490 | IWL_ALIVE_STATUS_OK; |
491 | IWL_DEBUG_FW(mvm, | |
492 | "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
7e1223b5 EG |
493 | le16_to_cpu(palive1->status), palive1->ver_type, |
494 | palive1->ver_subtype, palive1->flags); | |
495 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) { | |
01a9ca51 EH |
496 | palive2 = (void *)pkt->data; |
497 | ||
01a9ca51 EH |
498 | mvm->error_event_table = |
499 | le32_to_cpu(palive2->error_event_table_ptr); | |
500 | mvm->log_event_table = | |
501 | le32_to_cpu(palive2->log_event_table_ptr); | |
502 | alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr); | |
503 | mvm->umac_error_event_table = | |
504 | le32_to_cpu(palive2->error_info_addr); | |
91479b64 EH |
505 | mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr); |
506 | mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size); | |
01a9ca51 EH |
507 | |
508 | alive_data->valid = le16_to_cpu(palive2->status) == | |
509 | IWL_ALIVE_STATUS_OK; | |
ffa70264 EG |
510 | if (mvm->umac_error_event_table) |
511 | mvm->support_umac_log = true; | |
512 | ||
01a9ca51 EH |
513 | IWL_DEBUG_FW(mvm, |
514 | "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
515 | le16_to_cpu(palive2->status), palive2->ver_type, | |
516 | palive2->ver_subtype, palive2->flags); | |
517 | ||
518 | IWL_DEBUG_FW(mvm, | |
519 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
520 | palive2->umac_major, palive2->umac_minor); | |
7e1223b5 EG |
521 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { |
522 | palive = (void *)pkt->data; | |
523 | ||
524 | mvm->error_event_table = | |
525 | le32_to_cpu(palive->error_event_table_ptr); | |
526 | mvm->log_event_table = | |
527 | le32_to_cpu(palive->log_event_table_ptr); | |
528 | alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr); | |
529 | mvm->umac_error_event_table = | |
530 | le32_to_cpu(palive->error_info_addr); | |
531 | mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr); | |
532 | mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size); | |
533 | ||
534 | alive_data->valid = le16_to_cpu(palive->status) == | |
535 | IWL_ALIVE_STATUS_OK; | |
536 | if (mvm->umac_error_event_table) | |
537 | mvm->support_umac_log = true; | |
538 | ||
539 | IWL_DEBUG_FW(mvm, | |
540 | "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
541 | le16_to_cpu(palive->status), palive->ver_type, | |
542 | palive->ver_subtype, palive->flags); | |
543 | ||
544 | IWL_DEBUG_FW(mvm, | |
545 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
546 | le32_to_cpu(palive->umac_major), | |
547 | le32_to_cpu(palive->umac_minor)); | |
01a9ca51 | 548 | } |
8ca151b5 JB |
549 | |
550 | return true; | |
551 | } | |
552 | ||
553 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, | |
554 | struct iwl_rx_packet *pkt, void *data) | |
555 | { | |
556 | struct iwl_phy_db *phy_db = data; | |
557 | ||
558 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
559 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
560 | return true; | |
561 | } | |
562 | ||
ce1f2778 | 563 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); |
8ca151b5 JB |
564 | |
565 | return false; | |
566 | } | |
567 | ||
568 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
569 | enum iwl_ucode_type ucode_type) | |
570 | { | |
571 | struct iwl_notification_wait alive_wait; | |
572 | struct iwl_mvm_alive_data alive_data; | |
573 | const struct fw_img *fw; | |
574 | int ret, i; | |
575 | enum iwl_ucode_type old_type = mvm->cur_ucode; | |
6eb031d2 | 576 | static const u16 alive_cmd[] = { MVM_ALIVE }; |
91479b64 | 577 | struct iwl_sf_region st_fwrd_space; |
8ca151b5 | 578 | |
61df750c | 579 | if (ucode_type == IWL_UCODE_REGULAR && |
3d2d4422 GBA |
580 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && |
581 | !(fw_has_capa(&mvm->fw->ucode_capa, | |
582 | IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) | |
61df750c EH |
583 | fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER); |
584 | else | |
585 | fw = iwl_get_ucode_image(mvm, ucode_type); | |
befe9b6f | 586 | if (WARN_ON(!fw)) |
8ca151b5 | 587 | return -EINVAL; |
befe9b6f JB |
588 | mvm->cur_ucode = ucode_type; |
589 | mvm->ucode_loaded = false; | |
8ca151b5 JB |
590 | |
591 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
592 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
593 | iwl_alive_fn, &alive_data); | |
594 | ||
595 | ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); | |
596 | if (ret) { | |
597 | mvm->cur_ucode = old_type; | |
598 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); | |
599 | return ret; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Some things may run in the background now, but we | |
604 | * just wait for the ALIVE notification here. | |
605 | */ | |
606 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
607 | MVM_UCODE_ALIVE_TIMEOUT); | |
608 | if (ret) { | |
192de2b4 DS |
609 | if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
610 | IWL_ERR(mvm, | |
611 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
612 | iwl_read_prph(mvm->trans, SB_CPU_1_STATUS), | |
613 | iwl_read_prph(mvm->trans, SB_CPU_2_STATUS)); | |
8ca151b5 JB |
614 | mvm->cur_ucode = old_type; |
615 | return ret; | |
616 | } | |
617 | ||
618 | if (!alive_data.valid) { | |
619 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
620 | mvm->cur_ucode = old_type; | |
621 | return -EIO; | |
622 | } | |
623 | ||
91479b64 EH |
624 | /* |
625 | * update the sdio allocation according to the pointer we get in the | |
626 | * alive notification. | |
627 | */ | |
628 | st_fwrd_space.addr = mvm->sf_space.addr; | |
629 | st_fwrd_space.size = mvm->sf_space.size; | |
630 | ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space); | |
82e8aea0 ES |
631 | if (ret) { |
632 | IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret); | |
633 | return ret; | |
634 | } | |
91479b64 | 635 | |
8ca151b5 JB |
636 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); |
637 | ||
a6c4fb44 MG |
638 | /* |
639 | * configure and operate fw paging mechanism. | |
640 | * driver configures the paging flow only once, CPU2 paging image | |
641 | * included in the IWL_UCODE_INIT image. | |
642 | */ | |
643 | if (fw->paging_mem_size) { | |
e1120187 MG |
644 | /* |
645 | * When dma is not enabled, the driver needs to copy / write | |
646 | * the downloaded / uploaded page to / from the smem. | |
647 | * This gets the location of the place were the pages are | |
648 | * stored. | |
649 | */ | |
650 | if (!is_device_dma_capable(mvm->trans->dev)) { | |
651 | ret = iwl_trans_get_paging_item(mvm); | |
652 | if (ret) { | |
653 | IWL_ERR(mvm, "failed to get FW paging item\n"); | |
654 | return ret; | |
655 | } | |
656 | } | |
657 | ||
a6c4fb44 MG |
658 | ret = iwl_save_fw_paging(mvm, fw); |
659 | if (ret) { | |
660 | IWL_ERR(mvm, "failed to save the FW paging image\n"); | |
661 | return ret; | |
662 | } | |
663 | ||
664 | ret = iwl_send_paging_cmd(mvm, fw); | |
665 | if (ret) { | |
666 | IWL_ERR(mvm, "failed to send the paging cmd\n"); | |
667 | iwl_free_fw_paging(mvm); | |
668 | return ret; | |
669 | } | |
670 | } | |
671 | ||
8ca151b5 JB |
672 | /* |
673 | * Note: all the queues are enabled as part of the interface | |
674 | * initialization, but in firmware restart scenarios they | |
675 | * could be stopped, so wake them up. In firmware restart, | |
676 | * mac80211 will have the queues stopped as well until the | |
677 | * reconfiguration completes. During normal startup, they | |
678 | * will be empty. | |
679 | */ | |
680 | ||
4ecafae9 | 681 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
097129c9 LK |
682 | if (iwl_mvm_is_dqa_supported(mvm)) |
683 | mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].hw_queue_refcount = 1; | |
684 | else | |
685 | mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1; | |
8ca151b5 | 686 | |
df197c00 JB |
687 | for (i = 0; i < IEEE80211_MAX_QUEUES; i++) |
688 | atomic_set(&mvm->mac80211_queue_stop_count[i], 0); | |
8ca151b5 JB |
689 | |
690 | mvm->ucode_loaded = true; | |
691 | ||
692 | return 0; | |
693 | } | |
8ca151b5 JB |
694 | |
695 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) | |
696 | { | |
697 | struct iwl_phy_cfg_cmd phy_cfg_cmd; | |
698 | enum iwl_ucode_type ucode_type = mvm->cur_ucode; | |
699 | ||
700 | /* Set parameters */ | |
a0544272 | 701 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
8ca151b5 JB |
702 | phy_cfg_cmd.calib_control.event_trigger = |
703 | mvm->fw->default_calib[ucode_type].event_trigger; | |
704 | phy_cfg_cmd.calib_control.flow_trigger = | |
705 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
706 | ||
707 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", | |
708 | phy_cfg_cmd.phy_cfg); | |
709 | ||
a1022927 | 710 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
711 | sizeof(phy_cfg_cmd), &phy_cfg_cmd); |
712 | } | |
713 | ||
8ca151b5 JB |
714 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
715 | { | |
716 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 717 | static const u16 init_complete[] = { |
8ca151b5 JB |
718 | INIT_COMPLETE_NOTIF, |
719 | CALIB_RES_NOTIF_PHY_DB | |
720 | }; | |
721 | int ret; | |
722 | ||
723 | lockdep_assert_held(&mvm->mutex); | |
724 | ||
8d193ca2 | 725 | if (WARN_ON_ONCE(mvm->calibrating)) |
8ca151b5 JB |
726 | return 0; |
727 | ||
728 | iwl_init_notification_wait(&mvm->notif_wait, | |
729 | &calib_wait, | |
730 | init_complete, | |
731 | ARRAY_SIZE(init_complete), | |
732 | iwl_wait_phy_db_entry, | |
733 | mvm->phy_db); | |
734 | ||
735 | /* Will also start the device */ | |
736 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
737 | if (ret) { | |
738 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
739 | goto error; | |
740 | } | |
741 | ||
ae397472 | 742 | ret = iwl_send_bt_init_conf(mvm); |
931d4160 EG |
743 | if (ret) |
744 | goto error; | |
745 | ||
81a67e32 | 746 | /* Read the NVM only at driver load time, no need to do this twice */ |
8ca151b5 JB |
747 | if (read_nvm) { |
748 | /* Read nvm */ | |
14b485f0 | 749 | ret = iwl_nvm_init(mvm, true); |
8ca151b5 JB |
750 | if (ret) { |
751 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
752 | goto error; | |
753 | } | |
754 | } | |
755 | ||
81a67e32 | 756 | /* In case we read the NVM from external file, load it to the NIC */ |
e02a9d60 | 757 | if (mvm->nvm_file_name) |
81a67e32 EL |
758 | iwl_mvm_load_nvm_to_nic(mvm); |
759 | ||
8ca151b5 JB |
760 | ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans); |
761 | WARN_ON(ret); | |
762 | ||
4f59334b EH |
763 | /* |
764 | * abort after reading the nvm in case RF Kill is on, we will complete | |
765 | * the init seq later when RF kill will switch to off | |
766 | */ | |
1a3fe0b2 | 767 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
768 | IWL_DEBUG_RF_KILL(mvm, |
769 | "jump over all phy activities due to RF kill\n"); | |
770 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
a4082843 AN |
771 | ret = 1; |
772 | goto out; | |
4f59334b EH |
773 | } |
774 | ||
31b8b343 EG |
775 | mvm->calibrating = true; |
776 | ||
e07cbb53 | 777 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 778 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 DS |
779 | if (ret) |
780 | goto error; | |
781 | ||
8ca151b5 JB |
782 | /* |
783 | * Send phy configurations command to init uCode | |
784 | * to start the 16.0 uCode init image internal calibrations. | |
785 | */ | |
786 | ret = iwl_send_phy_cfg_cmd(mvm); | |
787 | if (ret) { | |
788 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
789 | ret); | |
790 | goto error; | |
791 | } | |
792 | ||
793 | /* | |
794 | * Some things may run in the background now, but we | |
795 | * just wait for the calibration complete notification. | |
796 | */ | |
797 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
798 | MVM_UCODE_CALIB_TIMEOUT); | |
31b8b343 | 799 | |
1a3fe0b2 | 800 | if (ret && iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 EG |
801 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
802 | ret = 1; | |
803 | } | |
8ca151b5 JB |
804 | goto out; |
805 | ||
806 | error: | |
807 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
808 | out: | |
31b8b343 | 809 | mvm->calibrating = false; |
a4082843 | 810 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
811 | /* we want to debug INIT and we have no NVM - fake */ |
812 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
813 | sizeof(struct ieee80211_channel) + | |
814 | sizeof(struct ieee80211_rate), | |
815 | GFP_KERNEL); | |
816 | if (!mvm->nvm_data) | |
817 | return -ENOMEM; | |
8ca151b5 JB |
818 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
819 | mvm->nvm_data->bands[0].n_channels = 1; | |
820 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
821 | mvm->nvm_data->bands[0].bitrates = | |
822 | (void *)mvm->nvm_data->channels + 1; | |
823 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
824 | } | |
825 | ||
826 | return ret; | |
827 | } | |
828 | ||
04fd2c28 LK |
829 | static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm) |
830 | { | |
831 | struct iwl_host_cmd cmd = { | |
04fd2c28 LK |
832 | .flags = CMD_WANT_SKB, |
833 | .data = { NULL, }, | |
834 | .len = { 0, }, | |
835 | }; | |
04fd2c28 | 836 | struct iwl_shared_mem_cfg *mem_cfg; |
5b086414 | 837 | struct iwl_rx_packet *pkt; |
04fd2c28 LK |
838 | u32 i; |
839 | ||
840 | lockdep_assert_held(&mvm->mutex); | |
841 | ||
5b086414 GBA |
842 | if (fw_has_capa(&mvm->fw->ucode_capa, |
843 | IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) | |
844 | cmd.id = iwl_cmd_id(SHARED_MEM_CFG_CMD, SYSTEM_GROUP, 0); | |
845 | else | |
846 | cmd.id = SHARED_MEM_CFG; | |
847 | ||
04fd2c28 LK |
848 | if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd))) |
849 | return; | |
850 | ||
851 | pkt = cmd.resp_pkt; | |
04fd2c28 LK |
852 | mem_cfg = (void *)pkt->data; |
853 | ||
854 | mvm->shared_mem_cfg.shared_mem_addr = | |
855 | le32_to_cpu(mem_cfg->shared_mem_addr); | |
856 | mvm->shared_mem_cfg.shared_mem_size = | |
857 | le32_to_cpu(mem_cfg->shared_mem_size); | |
858 | mvm->shared_mem_cfg.sample_buff_addr = | |
859 | le32_to_cpu(mem_cfg->sample_buff_addr); | |
860 | mvm->shared_mem_cfg.sample_buff_size = | |
861 | le32_to_cpu(mem_cfg->sample_buff_size); | |
862 | mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr); | |
863 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) | |
864 | mvm->shared_mem_cfg.txfifo_size[i] = | |
865 | le32_to_cpu(mem_cfg->txfifo_size[i]); | |
866 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) | |
867 | mvm->shared_mem_cfg.rxfifo_size[i] = | |
868 | le32_to_cpu(mem_cfg->rxfifo_size[i]); | |
869 | mvm->shared_mem_cfg.page_buff_addr = | |
870 | le32_to_cpu(mem_cfg->page_buff_addr); | |
871 | mvm->shared_mem_cfg.page_buff_size = | |
872 | le32_to_cpu(mem_cfg->page_buff_size); | |
5b086414 GBA |
873 | |
874 | /* new API has more data */ | |
875 | if (fw_has_capa(&mvm->fw->ucode_capa, | |
876 | IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { | |
877 | mvm->shared_mem_cfg.rxfifo_addr = | |
878 | le32_to_cpu(mem_cfg->rxfifo_addr); | |
879 | mvm->shared_mem_cfg.internal_txfifo_addr = | |
880 | le32_to_cpu(mem_cfg->internal_txfifo_addr); | |
881 | ||
882 | BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) != | |
883 | sizeof(mem_cfg->internal_txfifo_size)); | |
884 | ||
885 | for (i = 0; | |
886 | i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size); | |
887 | i++) | |
888 | mvm->shared_mem_cfg.internal_txfifo_size[i] = | |
889 | le32_to_cpu(mem_cfg->internal_txfifo_size[i]); | |
890 | } | |
891 | ||
04fd2c28 LK |
892 | IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); |
893 | ||
04fd2c28 LK |
894 | iwl_free_resp(&cmd); |
895 | } | |
896 | ||
84bfffa9 EG |
897 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
898 | { | |
899 | struct iwl_ltr_config_cmd cmd = { | |
900 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
901 | }; | |
902 | ||
903 | if (!mvm->trans->ltr_enabled) | |
904 | return 0; | |
905 | ||
84bfffa9 EG |
906 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
907 | sizeof(cmd), &cmd); | |
908 | } | |
909 | ||
da2830ac LC |
910 | #define ACPI_WRDS_METHOD "WRDS" |
911 | #define ACPI_WRDS_WIFI (0x07) | |
912 | #define ACPI_WRDS_TABLE_SIZE 10 | |
913 | ||
914 | struct iwl_mvm_sar_table { | |
915 | bool enabled; | |
916 | u8 values[ACPI_WRDS_TABLE_SIZE]; | |
917 | }; | |
918 | ||
919 | #ifdef CONFIG_ACPI | |
920 | static int iwl_mvm_sar_get_wrds(struct iwl_mvm *mvm, union acpi_object *wrds, | |
921 | struct iwl_mvm_sar_table *sar_table) | |
922 | { | |
923 | union acpi_object *data_pkg; | |
924 | u32 i; | |
925 | ||
926 | /* We need at least two packages, one for the revision and one | |
927 | * for the data itself. Also check that the revision is valid | |
928 | * (i.e. it is an integer set to 0). | |
929 | */ | |
930 | if (wrds->type != ACPI_TYPE_PACKAGE || | |
931 | wrds->package.count < 2 || | |
932 | wrds->package.elements[0].type != ACPI_TYPE_INTEGER || | |
933 | wrds->package.elements[0].integer.value != 0) { | |
934 | IWL_DEBUG_RADIO(mvm, "Unsupported wrds structure\n"); | |
935 | return -EINVAL; | |
936 | } | |
937 | ||
938 | /* loop through all the packages to find the one for WiFi */ | |
939 | for (i = 1; i < wrds->package.count; i++) { | |
940 | union acpi_object *domain; | |
941 | ||
942 | data_pkg = &wrds->package.elements[i]; | |
943 | ||
944 | /* Skip anything that is not a package with the right | |
945 | * amount of elements (i.e. domain_type, | |
946 | * enabled/disabled plus the sar table size. | |
947 | */ | |
948 | if (data_pkg->type != ACPI_TYPE_PACKAGE || | |
949 | data_pkg->package.count != ACPI_WRDS_TABLE_SIZE + 2) | |
950 | continue; | |
951 | ||
952 | domain = &data_pkg->package.elements[0]; | |
953 | if (domain->type == ACPI_TYPE_INTEGER && | |
954 | domain->integer.value == ACPI_WRDS_WIFI) | |
955 | break; | |
956 | ||
957 | data_pkg = NULL; | |
958 | } | |
959 | ||
960 | if (!data_pkg) | |
961 | return -ENOENT; | |
962 | ||
963 | if (data_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) | |
964 | return -EINVAL; | |
965 | ||
966 | sar_table->enabled = !!(data_pkg->package.elements[1].integer.value); | |
967 | ||
968 | for (i = 0; i < ACPI_WRDS_TABLE_SIZE; i++) { | |
969 | union acpi_object *entry; | |
970 | ||
971 | entry = &data_pkg->package.elements[i + 2]; | |
972 | if ((entry->type != ACPI_TYPE_INTEGER) || | |
973 | (entry->integer.value > U8_MAX)) | |
974 | return -EINVAL; | |
975 | ||
976 | sar_table->values[i] = entry->integer.value; | |
977 | } | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm, | |
983 | struct iwl_mvm_sar_table *sar_table) | |
984 | { | |
985 | acpi_handle root_handle; | |
986 | acpi_handle handle; | |
987 | struct acpi_buffer wrds = {ACPI_ALLOCATE_BUFFER, NULL}; | |
988 | acpi_status status; | |
989 | int ret; | |
990 | ||
991 | root_handle = ACPI_HANDLE(mvm->dev); | |
992 | if (!root_handle) { | |
993 | IWL_DEBUG_RADIO(mvm, | |
994 | "Could not retrieve root port ACPI handle\n"); | |
995 | return -ENOENT; | |
996 | } | |
997 | ||
998 | /* Get the method's handle */ | |
999 | status = acpi_get_handle(root_handle, (acpi_string)ACPI_WRDS_METHOD, | |
1000 | &handle); | |
1001 | if (ACPI_FAILURE(status)) { | |
1002 | IWL_DEBUG_RADIO(mvm, "WRDS method not found\n"); | |
1003 | return -ENOENT; | |
1004 | } | |
1005 | ||
1006 | /* Call WRDS with no arguments */ | |
1007 | status = acpi_evaluate_object(handle, NULL, NULL, &wrds); | |
1008 | if (ACPI_FAILURE(status)) { | |
1009 | IWL_DEBUG_RADIO(mvm, "WRDS invocation failed (0x%x)\n", status); | |
1010 | return -ENOENT; | |
1011 | } | |
1012 | ||
1013 | ret = iwl_mvm_sar_get_wrds(mvm, wrds.pointer, sar_table); | |
1014 | kfree(wrds.pointer); | |
1015 | ||
1016 | return ret; | |
1017 | } | |
1018 | #else /* CONFIG_ACPI */ | |
1019 | static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm, | |
1020 | struct iwl_mvm_sar_table *sar_table) | |
1021 | { | |
1022 | return -ENOENT; | |
1023 | } | |
1024 | #endif /* CONFIG_ACPI */ | |
1025 | ||
1026 | static int iwl_mvm_sar_init(struct iwl_mvm *mvm) | |
1027 | { | |
1028 | struct iwl_mvm_sar_table sar_table; | |
1029 | struct iwl_dev_tx_power_cmd cmd = { | |
1030 | .v2.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS), | |
1031 | }; | |
1032 | int ret, i, j, idx; | |
1033 | ||
1034 | /* we can't do anything with the table if the FW doesn't support it */ | |
1035 | if (!fw_has_api(&mvm->fw->ucode_capa, | |
1036 | IWL_UCODE_TLV_API_TX_POWER_CHAIN)) { | |
1037 | IWL_DEBUG_RADIO(mvm, | |
1038 | "FW doesn't support per-chain TX power settings.\n"); | |
1039 | return 0; | |
1040 | } | |
1041 | ||
1042 | ret = iwl_mvm_sar_get_table(mvm, &sar_table); | |
1043 | if (ret < 0) { | |
1044 | IWL_DEBUG_RADIO(mvm, | |
1045 | "SAR BIOS table invalid or unavailable. (%d)\n", | |
1046 | ret); | |
1047 | /* we don't fail if the table is not available */ | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | if (!sar_table.enabled) | |
1052 | return 0; | |
1053 | ||
1054 | IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); | |
1055 | ||
1056 | BUILD_BUG_ON(IWL_NUM_CHAIN_LIMITS * IWL_NUM_SUB_BANDS != | |
1057 | ACPI_WRDS_TABLE_SIZE); | |
1058 | ||
1059 | for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { | |
1060 | IWL_DEBUG_RADIO(mvm, " Chain[%d]:\n", i); | |
1061 | for (j = 0; j < IWL_NUM_SUB_BANDS; j++) { | |
1062 | idx = (i * IWL_NUM_SUB_BANDS) + j; | |
1063 | cmd.per_chain_restriction[i][j] = | |
1064 | cpu_to_le16(sar_table.values[idx]); | |
1065 | IWL_DEBUG_RADIO(mvm, " Band[%d] = %d * .125dBm\n", | |
1066 | j, sar_table.values[idx]); | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | ret = iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, | |
1071 | sizeof(cmd), &cmd); | |
1072 | if (ret) | |
1073 | IWL_ERR(mvm, "failed to set per-chain TX power: %d\n", ret); | |
1074 | ||
1075 | return ret; | |
1076 | } | |
1077 | ||
8ca151b5 JB |
1078 | int iwl_mvm_up(struct iwl_mvm *mvm) |
1079 | { | |
1080 | int ret, i; | |
53a9d61e IP |
1081 | struct ieee80211_channel *chan; |
1082 | struct cfg80211_chan_def chandef; | |
8ca151b5 JB |
1083 | |
1084 | lockdep_assert_held(&mvm->mutex); | |
1085 | ||
1086 | ret = iwl_trans_start_hw(mvm->trans); | |
1087 | if (ret) | |
1088 | return ret; | |
1089 | ||
ff116373 EL |
1090 | /* |
1091 | * If we haven't completed the run of the init ucode during | |
1092 | * module loading, load init ucode now | |
1093 | * (for example, if we were in RFKILL) | |
1094 | */ | |
8d193ca2 EH |
1095 | ret = iwl_run_init_mvm_ucode(mvm, false); |
1096 | if (ret && !iwlmvm_mod_params.init_dbg) { | |
1097 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); | |
1098 | /* this can't happen */ | |
1099 | if (WARN_ON(ret > 0)) | |
1100 | ret = -ERFKILL; | |
1101 | goto error; | |
1102 | } | |
1103 | if (!iwlmvm_mod_params.init_dbg) { | |
1104 | /* | |
1105 | * Stop and start the transport without entering low power | |
1106 | * mode. This will save the state of other components on the | |
1107 | * device that are triggered by the INIT firwmare (MFUART). | |
1108 | */ | |
1109 | _iwl_trans_stop_device(mvm->trans, false); | |
d643c432 | 1110 | ret = _iwl_trans_start_hw(mvm->trans, false); |
8d193ca2 | 1111 | if (ret) |
d643c432 | 1112 | goto error; |
8ca151b5 JB |
1113 | } |
1114 | ||
1115 | if (iwlmvm_mod_params.init_dbg) | |
1116 | return 0; | |
1117 | ||
1118 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
1119 | if (ret) { | |
1120 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
1121 | goto error; | |
1122 | } | |
1123 | ||
6c7d32cf | 1124 | iwl_mvm_get_shared_mem_conf(mvm); |
04fd2c28 | 1125 | |
1f3b0ff8 LE |
1126 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
1127 | if (ret) | |
1128 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
1129 | ||
6a951267 | 1130 | mvm->fw_dbg_conf = FW_DBG_INVALID; |
945d4202 EG |
1131 | /* if we have a destination, assume EARLY START */ |
1132 | if (mvm->fw->dbg_dest_tlv) | |
1133 | mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE; | |
d2709ad7 | 1134 | iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE); |
6a951267 | 1135 | |
a0544272 | 1136 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1137 | if (ret) |
1138 | goto error; | |
1139 | ||
931d4160 EG |
1140 | ret = iwl_send_bt_init_conf(mvm); |
1141 | if (ret) | |
1142 | goto error; | |
1143 | ||
8ca151b5 JB |
1144 | /* Send phy db control command and then phy db calibration*/ |
1145 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1146 | if (ret) | |
1147 | goto error; | |
1148 | ||
1149 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1150 | if (ret) | |
1151 | goto error; | |
1152 | ||
43413a97 SS |
1153 | /* Init RSS configuration */ |
1154 | if (iwl_mvm_has_new_rx_api(mvm)) { | |
1155 | ret = iwl_send_rss_cfg_cmd(mvm); | |
1156 | if (ret) { | |
1157 | IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", | |
1158 | ret); | |
1159 | goto error; | |
1160 | } | |
1161 | } | |
1162 | ||
8ca151b5 JB |
1163 | /* init the fw <-> mac80211 STA mapping */ |
1164 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1165 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1166 | ||
1d3c3f63 AN |
1167 | mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT; |
1168 | ||
b2b7875b JB |
1169 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
1170 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
1171 | ||
97d5be7e LK |
1172 | /* Enable DQA-mode if required */ |
1173 | if (iwl_mvm_is_dqa_supported(mvm)) { | |
1174 | ret = iwl_mvm_send_dqa_cmd(mvm); | |
1175 | if (ret) | |
1176 | goto error; | |
1177 | } else { | |
1178 | IWL_DEBUG_FW(mvm, "Working in non-DQA mode\n"); | |
1179 | } | |
1180 | ||
8ca151b5 JB |
1181 | /* Add auxiliary station for scanning */ |
1182 | ret = iwl_mvm_add_aux_sta(mvm); | |
1183 | if (ret) | |
1184 | goto error; | |
1185 | ||
53a9d61e | 1186 | /* Add all the PHY contexts */ |
57fbcce3 | 1187 | chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0]; |
53a9d61e IP |
1188 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); |
1189 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
1190 | /* | |
1191 | * The channel used here isn't relevant as it's | |
1192 | * going to be overwritten in the other flows. | |
1193 | * For now use the first channel we have. | |
1194 | */ | |
1195 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
1196 | &chandef, 1, 1); | |
1197 | if (ret) | |
1198 | goto error; | |
1199 | } | |
8ca151b5 | 1200 | |
c221daf2 CRI |
1201 | #ifdef CONFIG_THERMAL |
1202 | if (iwl_mvm_is_tt_in_fw(mvm)) { | |
1203 | /* in order to give the responsibility of ct-kill and | |
1204 | * TX backoff to FW we need to send empty temperature reporting | |
1205 | * cmd during init time | |
1206 | */ | |
1207 | iwl_mvm_send_temp_report_ths_cmd(mvm); | |
1208 | } else { | |
1209 | /* Initialize tx backoffs to the minimal possible */ | |
1210 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
1211 | } | |
5c89e7bc CRI |
1212 | |
1213 | /* TODO: read the budget from BIOS / Platform NVM */ | |
1214 | if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) | |
1215 | ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, | |
1216 | mvm->cooling_dev.cur_state); | |
c221daf2 | 1217 | #else |
0c0e2c71 IY |
1218 | /* Initialize tx backoffs to the minimal possible */ |
1219 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
c221daf2 | 1220 | #endif |
0c0e2c71 | 1221 | |
84bfffa9 | 1222 | WARN_ON(iwl_mvm_config_ltr(mvm)); |
9180ac50 | 1223 | |
c1cb92fc | 1224 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
1225 | if (ret) |
1226 | goto error; | |
1227 | ||
35af15d1 AN |
1228 | /* |
1229 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
1230 | * anyway, so don't init MCC. | |
1231 | */ | |
1232 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
1233 | ret = iwl_mvm_init_mcc(mvm); | |
1234 | if (ret) | |
1235 | goto error; | |
1236 | } | |
90d4f7db | 1237 | |
859d914c | 1238 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
4ca87a5f | 1239 | mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; |
d2496221 DS |
1240 | ret = iwl_mvm_config_scan(mvm); |
1241 | if (ret) | |
1242 | goto error; | |
1243 | } | |
1244 | ||
93190fb0 AA |
1245 | if (iwl_mvm_is_csum_supported(mvm) && |
1246 | mvm->cfg->features & NETIF_F_RXCSUM) | |
1247 | iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3); | |
1248 | ||
7498cf4c EP |
1249 | /* allow FW/transport low power modes if not during restart */ |
1250 | if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) | |
1251 | iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); | |
1252 | ||
da2830ac LC |
1253 | ret = iwl_mvm_sar_init(mvm); |
1254 | if (ret) | |
1255 | goto error; | |
1256 | ||
53a9d61e | 1257 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
1258 | return 0; |
1259 | error: | |
fcb6b92a | 1260 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1261 | return ret; |
1262 | } | |
1263 | ||
1264 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
1265 | { | |
1266 | int ret, i; | |
1267 | ||
1268 | lockdep_assert_held(&mvm->mutex); | |
1269 | ||
1270 | ret = iwl_trans_start_hw(mvm->trans); | |
1271 | if (ret) | |
1272 | return ret; | |
1273 | ||
1274 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
1275 | if (ret) { | |
1276 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
1277 | goto error; | |
1278 | } | |
1279 | ||
a0544272 | 1280 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1281 | if (ret) |
1282 | goto error; | |
1283 | ||
1284 | /* Send phy db control command and then phy db calibration*/ | |
1285 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1286 | if (ret) | |
1287 | goto error; | |
1288 | ||
1289 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1290 | if (ret) | |
1291 | goto error; | |
1292 | ||
1293 | /* init the fw <-> mac80211 STA mapping */ | |
1294 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1295 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1296 | ||
1297 | /* Add auxiliary station for scanning */ | |
1298 | ret = iwl_mvm_add_aux_sta(mvm); | |
1299 | if (ret) | |
1300 | goto error; | |
1301 | ||
1302 | return 0; | |
1303 | error: | |
fcb6b92a | 1304 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1305 | return ret; |
1306 | } | |
1307 | ||
0416841d JB |
1308 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1309 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1310 | { |
1311 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1312 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1313 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1314 | ||
1315 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1316 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1317 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1318 | (flags & CT_KILL_CARD_DISABLED) ? | |
1319 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1320 | } |
1321 | ||
0416841d JB |
1322 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1323 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1324 | { |
1325 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1326 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1327 | ||
1328 | IWL_DEBUG_INFO(mvm, | |
1329 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1330 | le32_to_cpu(mfuart_notif->installed_ver), | |
1331 | le32_to_cpu(mfuart_notif->external_ver), | |
1332 | le32_to_cpu(mfuart_notif->status), | |
1333 | le32_to_cpu(mfuart_notif->duration)); | |
30269c12 | 1334 | } |