hostap: convert to struct proc_ops
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8ca151b5
JB
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
bdccdb85 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
48e775e6 11 * Copyright(c) 2018 - 2019 Intel Corporation
8ca151b5
JB
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
8ca151b5 22 * The full GNU General Public License is included in this distribution
410dc5aa 23 * in the file called COPYING.
8ca151b5
JB
24 *
25 * Contact Information:
cb2f8277 26 * Intel Linux Wireless <linuxwifi@intel.com>
8ca151b5
JB
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
51368bf7 31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
bdccdb85 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
48e775e6 34 * Copyright(c) 2018 - 2019 Intel Corporation
8ca151b5
JB
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
64#include <net/mac80211.h>
854d773e 65#include <linux/netdevice.h>
8ca151b5
JB
66
67#include "iwl-trans.h"
68#include "iwl-op-mode.h"
d962f9b1 69#include "fw/img.h"
8ca151b5
JB
70#include "iwl-debug.h"
71#include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
72#include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
8c23f95c 73#include "iwl-prph.h"
813df5ce 74#include "fw/acpi.h"
8ca151b5
JB
75
76#include "mvm.h"
7174beb6 77#include "fw/dbg.h"
8ca151b5 78#include "iwl-phy-db.h"
9c4f7d51
ST
79#include "iwl-modparams.h"
80#include "iwl-nvm-parse.h"
8ca151b5
JB
81
82#define MVM_UCODE_ALIVE_TIMEOUT HZ
83#define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
84
85#define UCODE_VALID_OK cpu_to_le32(0x1)
86
8ca151b5
JB
87struct iwl_mvm_alive_data {
88 bool valid;
89 u32 scd_base_addr;
90};
91
8ca151b5
JB
92static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
93{
94 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
95 .valid = cpu_to_le32(valid_tx_ant),
96 };
97
33223542 98 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 99 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB
100 sizeof(tx_ant_cmd), &tx_ant_cmd);
101}
102
43413a97
SS
103static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
104{
105 int i;
106 struct iwl_rss_config_cmd cmd = {
107 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS
108 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
109 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
110 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
111 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
112 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
113 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS
114 };
115
f43495fd
SS
116 if (mvm->trans->num_rx_queues == 1)
117 return 0;
118
854d773e 119 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 120 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS
121 cmd.indirection_table[i] =
122 1 + (i % (mvm->trans->num_rx_queues - 1));
123 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS
124
125 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
126}
127
8edbfaa1
SS
128static int iwl_configure_rxq(struct iwl_mvm *mvm)
129{
dbf592f3 130 int i, num_queues, size, ret;
8edbfaa1 131 struct iwl_rfh_queue_config *cmd;
dbf592f3
JB
132 struct iwl_host_cmd hcmd = {
133 .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD),
134 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
135 };
8edbfaa1
SS
136
137 /* Do not configure default queue, it is configured via context info */
138 num_queues = mvm->trans->num_rx_queues - 1;
139
dbf592f3 140 size = struct_size(cmd, data, num_queues);
8edbfaa1
SS
141
142 cmd = kzalloc(size, GFP_KERNEL);
143 if (!cmd)
144 return -ENOMEM;
145
146 cmd->num_queues = num_queues;
147
148 for (i = 0; i < num_queues; i++) {
149 struct iwl_trans_rxq_dma_data data;
150
151 cmd->data[i].q_num = i + 1;
152 iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data);
153
154 cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb);
155 cmd->data[i].urbd_stts_wrptr =
156 cpu_to_le64(data.urbd_stts_wrptr);
157 cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb);
158 cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid);
159 }
160
dbf592f3
JB
161 hcmd.data[0] = cmd;
162 hcmd.len[0] = size;
163
164 ret = iwl_mvm_send_cmd(mvm, &hcmd);
165
166 kfree(cmd);
167
168 return ret;
8edbfaa1
SS
169}
170
97d5be7e
LK
171static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
172{
173 struct iwl_dqa_enable_cmd dqa_cmd = {
174 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
175 };
176 u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
177 int ret;
178
179 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
180 if (ret)
181 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
182 else
183 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
184
185 return ret;
186}
187
bdccdb85
GBA
188void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
189 struct iwl_rx_cmd_buffer *rxb)
190{
191 struct iwl_rx_packet *pkt = rxb_addr(rxb);
192 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
193 __le32 *dump_data = mfu_dump_notif->data;
194 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
195 int i;
196
197 if (mfu_dump_notif->index_num == 0)
198 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
199 le32_to_cpu(mfu_dump_notif->assert_id));
200
201 for (i = 0; i < n_words; i++)
202 IWL_DEBUG_INFO(mvm,
203 "MFUART assert dump, dword %u: 0x%08x\n",
204 le16_to_cpu(mfu_dump_notif->index_num) *
205 n_words + i,
206 le32_to_cpu(dump_data[i]));
207}
208
8ca151b5
JB
209static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
210 struct iwl_rx_packet *pkt, void *data)
211{
212 struct iwl_mvm *mvm =
213 container_of(notif_wait, struct iwl_mvm, notif_wait);
214 struct iwl_mvm_alive_data *alive_data = data;
5c228d63 215 struct mvm_alive_resp_v3 *palive3;
7e1223b5 216 struct mvm_alive_resp *palive;
5c228d63
SS
217 struct iwl_umac_alive *umac;
218 struct iwl_lmac_alive *lmac1;
219 struct iwl_lmac_alive *lmac2 = NULL;
220 u16 status;
22463857 221 u32 lmac_error_event_table, umac_error_event_table;
01a9ca51 222
5c228d63
SS
223 if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
224 palive = (void *)pkt->data;
225 umac = &palive->umac_data;
226 lmac1 = &palive->lmac_data[0];
227 lmac2 = &palive->lmac_data[1];
228 status = le16_to_cpu(palive->status);
229 } else {
230 palive3 = (void *)pkt->data;
231 umac = &palive3->umac_data;
232 lmac1 = &palive3->lmac_data;
233 status = le16_to_cpu(palive3->status);
234 }
01a9ca51 235
22463857
SM
236 lmac_error_event_table =
237 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
238 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
239
5c228d63 240 if (lmac2)
91c28b83 241 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 242 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 243
22463857 244 umac_error_event_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr);
01a9ca51 245
3485e76e
LC
246 if (!umac_error_event_table) {
247 mvm->support_umac_log = false;
248 } else if (umac_error_event_table >=
249 mvm->trans->cfg->min_umac_error_event_table) {
250 mvm->support_umac_log = true;
3485e76e 251 } else {
fb5b2846
LC
252 IWL_ERR(mvm,
253 "Not valid error log pointer 0x%08X for %s uCode\n",
22463857 254 umac_error_event_table,
fb5b2846
LC
255 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
256 "Init" : "RT");
3485e76e
LC
257 mvm->support_umac_log = false;
258 }
fb5b2846 259
22463857
SM
260 if (mvm->support_umac_log)
261 iwl_fw_umac_set_alive_err_table(mvm->trans,
262 umac_error_event_table);
263
264 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 265 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 266
5c228d63
SS
267 IWL_DEBUG_FW(mvm,
268 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
269 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 270
5c228d63
SS
271 if (lmac2)
272 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 273
5c228d63
SS
274 IWL_DEBUG_FW(mvm,
275 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
276 le32_to_cpu(umac->umac_major),
277 le32_to_cpu(umac->umac_minor));
8ca151b5 278
0a3a3e9e
SM
279 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
280
8ca151b5
JB
281 return true;
282}
283
1f370650
SS
284static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
285 struct iwl_rx_packet *pkt, void *data)
286{
287 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
288
289 return true;
290}
291
8ca151b5
JB
292static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
293 struct iwl_rx_packet *pkt, void *data)
294{
295 struct iwl_phy_db *phy_db = data;
296
297 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
298 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
299 return true;
300 }
301
ce1f2778 302 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB
303
304 return false;
305}
306
307static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
308 enum iwl_ucode_type ucode_type)
309{
310 struct iwl_notification_wait alive_wait;
94a8d87c 311 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 312 const struct fw_img *fw;
cfbc6c4c 313 int ret;
702e975d 314 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
6eb031d2 315 static const u16 alive_cmd[] = { MVM_ALIVE };
b3500b47
EG
316 bool run_in_rfkill =
317 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
8ca151b5 318
61df750c 319 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA
320 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
321 !(fw_has_capa(&mvm->fw->ucode_capa,
322 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 323 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 324 else
612da1ef 325 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 326 if (WARN_ON(!fw))
8ca151b5 327 return -EINVAL;
702e975d 328 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 329 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB
330
331 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
332 alive_cmd, ARRAY_SIZE(alive_cmd),
333 iwl_alive_fn, &alive_data);
334
b3500b47
EG
335 /*
336 * We want to load the INIT firmware even in RFKILL
337 * For the unified firmware case, the ucode_type is not
338 * INIT, but we still need to run it.
339 */
340 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 341 if (ret) {
702e975d 342 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
343 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
344 return ret;
345 }
346
347 /*
348 * Some things may run in the background now, but we
349 * just wait for the ALIVE notification here.
350 */
351 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
352 MVM_UCODE_ALIVE_TIMEOUT);
353 if (ret) {
d6be9c1d
SS
354 struct iwl_trans *trans = mvm->trans;
355
20f5aef5
JB
356 if (trans->trans_cfg->device_family >=
357 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS
358 IWL_ERR(mvm,
359 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST
360 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
361 iwl_read_umac_prph(trans,
362 UMAG_SB_CPU_2_STATUS));
20f5aef5
JB
363 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
364 iwl_read_umac_prph(trans,
365 UREG_UMAC_CURRENT_PC));
366 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
367 iwl_read_umac_prph(trans,
368 UREG_LMAC1_CURRENT_PC));
369 if (iwl_mvm_is_cdb_supported(mvm))
370 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
371 iwl_read_umac_prph(trans,
372 UREG_LMAC2_CURRENT_PC));
373 } else if (trans->trans_cfg->device_family >=
374 IWL_DEVICE_FAMILY_8000) {
192de2b4
DS
375 IWL_ERR(mvm,
376 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
d6be9c1d
SS
377 iwl_read_prph(trans, SB_CPU_1_STATUS),
378 iwl_read_prph(trans, SB_CPU_2_STATUS));
20f5aef5
JB
379 }
380
381 if (ret == -ETIMEDOUT)
382 iwl_fw_dbg_error_collect(&mvm->fwrt,
383 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
384
702e975d 385 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
386 return ret;
387 }
388
389 if (!alive_data.valid) {
390 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 391 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
392 return -EIO;
393 }
394
395 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
396
397 /*
398 * Note: all the queues are enabled as part of the interface
399 * initialization, but in firmware restart scenarios they
400 * could be stopped, so wake them up. In firmware restart,
401 * mac80211 will have the queues stopped as well until the
402 * reconfiguration completes. During normal startup, they
403 * will be empty.
404 */
405
4ecafae9 406 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB
407 /*
408 * Set a 'fake' TID for the command queue, since we use the
409 * hweight() of the tid_bitmap as a refcount now. Not that
410 * we ever even consider the command queue as one we might
411 * want to reuse, but be safe nevertheless.
412 */
413 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
414 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 415
65b280fe 416 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC
417#ifdef CONFIG_IWLWIFI_DEBUGFS
418 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
419#endif
8ca151b5
JB
420
421 return 0;
422}
8ca151b5 423
8c5f47b1
JB
424static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
425{
426 struct iwl_notification_wait init_wait;
427 struct iwl_nvm_access_complete_cmd nvm_complete = {};
428 struct iwl_init_extended_cfg_cmd init_cfg = {
429 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
430 };
431 static const u16 init_complete[] = {
432 INIT_COMPLETE_NOTIF,
433 };
434 int ret;
435
a4584729
HD
436 if (mvm->trans->cfg->tx_with_siso_diversity)
437 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
438
8c5f47b1
JB
439 lockdep_assert_held(&mvm->mutex);
440
94022562
EG
441 mvm->rfkill_safe_init_done = false;
442
8c5f47b1
JB
443 iwl_init_notification_wait(&mvm->notif_wait,
444 &init_wait,
445 init_complete,
446 ARRAY_SIZE(init_complete),
447 iwl_wait_init_complete,
448 NULL);
449
b108d8c7 450 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
86ce5c74 451
8c5f47b1
JB
452 /* Will also start the device */
453 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
454 if (ret) {
455 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
456 goto error;
457 }
b108d8c7
SM
458 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
459 NULL);
8c5f47b1
JB
460
461 /* Send init config command to mark that we are sending NVM access
462 * commands
463 */
464 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
b3500b47
EG
465 INIT_EXTENDED_CFG_CMD),
466 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
467 sizeof(init_cfg), &init_cfg);
468 if (ret) {
469 IWL_ERR(mvm, "Failed to run init config command: %d\n",
470 ret);
471 goto error;
472 }
473
e9e1ba3d
SS
474 /* Load NVM to NIC if needed */
475 if (mvm->nvm_file_name) {
9c4f7d51
ST
476 iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
477 mvm->nvm_sections);
8c5f47b1 478 iwl_mvm_load_nvm_to_nic(mvm);
e9e1ba3d 479 }
8c5f47b1 480
d4f3695e 481 if (IWL_MVM_PARSE_NVM && read_nvm) {
5bd1d2c1 482 ret = iwl_nvm_init(mvm);
d4f3695e
SS
483 if (ret) {
484 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
485 goto error;
486 }
487 }
488
8c5f47b1 489 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
b3500b47
EG
490 NVM_ACCESS_COMPLETE),
491 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
492 sizeof(nvm_complete), &nvm_complete);
493 if (ret) {
494 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
495 ret);
496 goto error;
497 }
498
499 /* We wait for the INIT complete notification */
e9e1ba3d
SS
500 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
501 MVM_UCODE_ALIVE_TIMEOUT);
502 if (ret)
503 return ret;
504
505 /* Read the NVM only at driver load time, no need to do this twice */
d4f3695e 506 if (!IWL_MVM_PARSE_NVM && read_nvm) {
4c625c56 507 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
c135cb56
ST
508 if (IS_ERR(mvm->nvm_data)) {
509 ret = PTR_ERR(mvm->nvm_data);
510 mvm->nvm_data = NULL;
e9e1ba3d
SS
511 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
512 return ret;
513 }
514 }
515
b3500b47
EG
516 mvm->rfkill_safe_init_done = true;
517
e9e1ba3d 518 return 0;
8c5f47b1
JB
519
520error:
521 iwl_remove_notification(&mvm->notif_wait, &init_wait);
522 return ret;
523}
524
8ca151b5
JB
525static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
526{
527 struct iwl_phy_cfg_cmd phy_cfg_cmd;
702e975d 528 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
8ca151b5 529
bb99ff9b 530 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 531 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 532 return 0;
d923b020
LC
533
534 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC
535 /*
536 * TODO: currently we don't set the antenna but letting the NIC
537 * to decide which antenna to use. This should come from BIOS.
538 */
539 phy_cfg_cmd.phy_cfg =
540 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
541 }
542
8ca151b5 543 /* Set parameters */
a0544272 544 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC
545
546 /* set flags extra PHY configuration flags from the device's cfg */
547 phy_cfg_cmd.phy_cfg |= cpu_to_le32(mvm->cfg->extra_phy_cfg_flags);
548
8ca151b5
JB
549 phy_cfg_cmd.calib_control.event_trigger =
550 mvm->fw->default_calib[ucode_type].event_trigger;
551 phy_cfg_cmd.calib_control.flow_trigger =
552 mvm->fw->default_calib[ucode_type].flow_trigger;
553
554 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
555 phy_cfg_cmd.phy_cfg);
556
a1022927 557 return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
8ca151b5
JB
558 sizeof(phy_cfg_cmd), &phy_cfg_cmd);
559}
560
8ca151b5
JB
561int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
562{
563 struct iwl_notification_wait calib_wait;
6eb031d2 564 static const u16 init_complete[] = {
8ca151b5
JB
565 INIT_COMPLETE_NOTIF,
566 CALIB_RES_NOTIF_PHY_DB
567 };
568 int ret;
569
7d6222e2 570 if (iwl_mvm_has_unified_ucode(mvm))
8c5f47b1
JB
571 return iwl_run_unified_mvm_ucode(mvm, true);
572
8ca151b5
JB
573 lockdep_assert_held(&mvm->mutex);
574
94022562 575 mvm->rfkill_safe_init_done = false;
8ca151b5
JB
576
577 iwl_init_notification_wait(&mvm->notif_wait,
578 &calib_wait,
579 init_complete,
580 ARRAY_SIZE(init_complete),
581 iwl_wait_phy_db_entry,
582 mvm->phy_db);
583
584 /* Will also start the device */
585 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
586 if (ret) {
587 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 588 goto remove_notif;
8ca151b5
JB
589 }
590
7d34a7d7 591 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG
592 ret = iwl_mvm_send_bt_init_conf(mvm);
593 if (ret)
00e0c6c8 594 goto remove_notif;
b3de3ef4 595 }
931d4160 596
81a67e32 597 /* Read the NVM only at driver load time, no need to do this twice */
8ca151b5 598 if (read_nvm) {
5bd1d2c1 599 ret = iwl_nvm_init(mvm);
8ca151b5
JB
600 if (ret) {
601 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 602 goto remove_notif;
8ca151b5
JB
603 }
604 }
605
81a67e32 606 /* In case we read the NVM from external file, load it to the NIC */
e02a9d60 607 if (mvm->nvm_file_name)
81a67e32
EL
608 iwl_mvm_load_nvm_to_nic(mvm);
609
64866e5d
LC
610 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
611 "Too old NVM version (0x%0x, required = 0x%0x)",
612 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 613
4f59334b
EH
614 /*
615 * abort after reading the nvm in case RF Kill is on, we will complete
616 * the init seq later when RF kill will switch to off
617 */
1a3fe0b2 618 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH
619 IWL_DEBUG_RF_KILL(mvm,
620 "jump over all phy activities due to RF kill\n");
00e0c6c8 621 goto remove_notif;
4f59334b
EH
622 }
623
b3500b47 624 mvm->rfkill_safe_init_done = true;
31b8b343 625
e07cbb53 626 /* Send TX valid antennas before triggering calibrations */
a0544272 627 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 628 if (ret)
00e0c6c8 629 goto remove_notif;
e07cbb53 630
8ca151b5
JB
631 ret = iwl_send_phy_cfg_cmd(mvm);
632 if (ret) {
633 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
634 ret);
00e0c6c8 635 goto remove_notif;
8ca151b5
JB
636 }
637
638 /*
639 * Some things may run in the background now, but we
640 * just wait for the calibration complete notification.
641 */
642 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC
643 MVM_UCODE_CALIB_TIMEOUT);
644 if (!ret)
645 goto out;
31b8b343 646
00e0c6c8 647 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 648 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC
649 ret = 0;
650 } else {
651 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
652 ret);
31b8b343 653 }
00e0c6c8 654
8ca151b5
JB
655 goto out;
656
00e0c6c8 657remove_notif:
8ca151b5
JB
658 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
659out:
b3500b47 660 mvm->rfkill_safe_init_done = false;
a4082843 661 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB
662 /* we want to debug INIT and we have no NVM - fake */
663 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
664 sizeof(struct ieee80211_channel) +
665 sizeof(struct ieee80211_rate),
666 GFP_KERNEL);
667 if (!mvm->nvm_data)
668 return -ENOMEM;
8ca151b5
JB
669 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
670 mvm->nvm_data->bands[0].n_channels = 1;
671 mvm->nvm_data->bands[0].n_bitrates = 1;
672 mvm->nvm_data->bands[0].bitrates =
673 (void *)mvm->nvm_data->channels + 1;
674 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
675 }
676
677 return ret;
678}
679
84bfffa9
EG
680static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
681{
682 struct iwl_ltr_config_cmd cmd = {
683 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
684 };
685
686 if (!mvm->trans->ltr_enabled)
687 return 0;
688
84bfffa9
EG
689 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
690 sizeof(cmd), &cmd);
691}
692
c386dacb 693#ifdef CONFIG_ACPI
42ce76d6 694int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 695{
0791c2fc
HD
696 union {
697 struct iwl_dev_tx_power_cmd v5;
698 struct iwl_dev_tx_power_cmd_v4 v4;
699 } cmd;
da2830ac 700
39c1a972 701 u16 len = 0;
42ce76d6 702
0791c2fc
HD
703 cmd.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS);
704
705 if (fw_has_api(&mvm->fw->ucode_capa,
706 IWL_UCODE_TLV_API_REDUCE_TX_POWER))
707 len = sizeof(cmd.v5);
708 else if (fw_has_capa(&mvm->fw->ucode_capa,
709 IWL_UCODE_TLV_CAPA_TX_POWER_ACK))
39c1a972 710 len = sizeof(struct iwl_dev_tx_power_cmd_v4);
0791c2fc
HD
711 else
712 len = sizeof(cmd.v4.v3);
55bfa4b9 713
da2830ac 714
39c1a972
IZ
715 if (iwl_sar_select_profile(&mvm->fwrt, cmd.v5.v3.per_chain_restriction,
716 prof_a, prof_b))
717 return -ENOENT;
42ce76d6 718 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
42ce76d6
LC
719 return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
720}
721
7fe90e0e
HD
722int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
723{
39c1a972 724 union geo_tx_power_profiles_cmd geo_tx_cmd;
0c3d7282 725 u16 len;
39c1a972 726 int ret;
0c3d7282
HD
727 struct iwl_host_cmd cmd;
728
39c1a972
IZ
729 if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
730 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
731 geo_tx_cmd.geo_cmd.ops =
0c3d7282 732 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
39c1a972 733 len = sizeof(geo_tx_cmd.geo_cmd);
0c3d7282 734 } else {
39c1a972 735 geo_tx_cmd.geo_cmd_v1.ops =
0c3d7282 736 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
39c1a972 737 len = sizeof(geo_tx_cmd.geo_cmd_v1);
0c3d7282 738 }
7fe90e0e 739
39c1a972
IZ
740 if (!iwl_sar_geo_support(&mvm->fwrt))
741 return -EOPNOTSUPP;
742
0c3d7282 743 cmd = (struct iwl_host_cmd){
7fe90e0e 744 .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT),
0c3d7282 745 .len = { len, },
7fe90e0e 746 .flags = CMD_WANT_SKB,
39c1a972 747 .data = { &geo_tx_cmd },
7fe90e0e
HD
748 };
749
750 ret = iwl_mvm_send_cmd(mvm, &cmd);
751 if (ret) {
752 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
753 return ret;
754 }
39c1a972 755 ret = iwl_validate_sar_geo_profile(&mvm->fwrt, &cmd);
7fe90e0e
HD
756 iwl_free_resp(&cmd);
757 return ret;
758}
759
a6bff3cb
HD
760static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
761{
a6bff3cb 762 u16 cmd_wide_id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT);
39c1a972
IZ
763 union geo_tx_power_profiles_cmd cmd;
764 u16 len;
a6bff3cb 765
39c1a972 766 cmd.geo_cmd.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
a6bff3cb 767
39c1a972 768 iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table);
a6bff3cb 769
39c1a972 770 cmd.geo_cmd.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
0c3d7282 771
39c1a972
IZ
772 if (!fw_has_api(&mvm->fwrt.fw->ucode_capa,
773 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
774 len = sizeof(struct iwl_geo_tx_power_profiles_cmd_v1);
775 } else {
776 len = sizeof(cmd.geo_cmd);
0c3d7282
HD
777 }
778
39c1a972 779 return iwl_mvm_send_cmd_pdu(mvm, cmd_wide_id, 0, len, &cmd);
a6bff3cb
HD
780}
781
6ce1e5c0
GA
782static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm)
783{
784 union acpi_object *wifi_pkg, *data, *enabled;
785 int i, j, ret, tbl_rev;
786 int idx = 2;
787
39c1a972 788 mvm->fwrt.ppag_table.enabled = cpu_to_le32(0);
6ce1e5c0
GA
789 data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD);
790 if (IS_ERR(data))
791 return PTR_ERR(data);
792
793 wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
794 ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev);
795
3ed83da3 796 if (IS_ERR(wifi_pkg)) {
6ce1e5c0
GA
797 ret = PTR_ERR(wifi_pkg);
798 goto out_free;
799 }
800
3ed83da3
LC
801 if (tbl_rev != 0) {
802 ret = -EINVAL;
803 goto out_free;
804 }
805
6ce1e5c0
GA
806 enabled = &wifi_pkg->package.elements[1];
807 if (enabled->type != ACPI_TYPE_INTEGER ||
808 (enabled->integer.value != 0 && enabled->integer.value != 1)) {
809 ret = -EINVAL;
810 goto out_free;
811 }
812
39c1a972
IZ
813 mvm->fwrt.ppag_table.enabled = cpu_to_le32(enabled->integer.value);
814 if (!mvm->fwrt.ppag_table.enabled) {
6ce1e5c0
GA
815 ret = 0;
816 goto out_free;
817 }
818
819 /*
820 * read, verify gain values and save them into the PPAG table.
821 * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the
822 * following sub-bands to High-Band (5GHz).
823 */
824 for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) {
825 for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) {
826 union acpi_object *ent;
827
828 ent = &wifi_pkg->package.elements[idx++];
829 if (ent->type != ACPI_TYPE_INTEGER ||
830 (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) ||
831 (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) ||
832 (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) ||
833 (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) {
39c1a972 834 mvm->fwrt.ppag_table.enabled = cpu_to_le32(0);
6ce1e5c0
GA
835 ret = -EINVAL;
836 goto out_free;
837 }
39c1a972 838 mvm->fwrt.ppag_table.gain[i][j] = ent->integer.value;
6ce1e5c0
GA
839 }
840 }
841 ret = 0;
842out_free:
843 kfree(data);
844 return ret;
845}
846
847int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
848{
849 int i, j, ret;
850
851 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
852 IWL_DEBUG_RADIO(mvm,
853 "PPAG capability not supported by FW, command not sent.\n");
854 return 0;
855 }
856
160bab43
GA
857 if (!mvm->fwrt.ppag_table.enabled) {
858 IWL_DEBUG_RADIO(mvm,
859 "PPAG not enabled, command not sent.\n");
860 return 0;
861 }
862
6ce1e5c0 863 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA
864
865 for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) {
866 for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) {
867 IWL_DEBUG_RADIO(mvm,
868 "PPAG table: chain[%d] band[%d]: gain = %d\n",
39c1a972 869 i, j, mvm->fwrt.ppag_table.gain[i][j]);
6ce1e5c0
GA
870 }
871 }
872
873 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
874 PER_PLATFORM_ANT_GAIN_CMD),
39c1a972
IZ
875 0, sizeof(mvm->fwrt.ppag_table),
876 &mvm->fwrt.ppag_table);
6ce1e5c0
GA
877 if (ret < 0)
878 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
879 ret);
880
881 return ret;
882}
883
884static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
885{
886 int ret;
887
888 ret = iwl_mvm_get_ppag_table(mvm);
889 if (ret < 0) {
890 IWL_DEBUG_RADIO(mvm,
891 "PPAG BIOS table invalid or unavailable. (%d)\n",
892 ret);
893 return 0;
894 }
895 return iwl_mvm_ppag_send_cmd(mvm);
896}
897
69964905 898#else /* CONFIG_ACPI */
69964905 899
39c1a972
IZ
900inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
901 int prof_a, int prof_b)
69964905
LC
902{
903 return -ENOENT;
904}
a6bff3cb 905
39c1a972 906inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC
907{
908 return -ENOENT;
909}
910
a6bff3cb
HD
911static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
912{
913 return 0;
914}
18f1755d 915
6ce1e5c0
GA
916int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
917{
918 return -ENOENT;
919}
920
921static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
922{
7937fd32 923 return 0;
6ce1e5c0 924}
69964905
LC
925#endif /* CONFIG_ACPI */
926
f130bb75
MG
927void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
928{
929 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
930 int ret;
931 u32 resp;
932
933 struct iwl_fw_error_recovery_cmd recovery_cmd = {
934 .flags = cpu_to_le32(flags),
935 .buf_size = 0,
936 };
937 struct iwl_host_cmd host_cmd = {
938 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
939 .flags = CMD_WANT_SKB,
940 .data = {&recovery_cmd, },
941 .len = {sizeof(recovery_cmd), },
942 };
943
944 /* no error log was defined in TLV */
945 if (!error_log_size)
946 return;
947
948 if (flags & ERROR_RECOVERY_UPDATE_DB) {
949 /* no buf was allocated while HW reset */
950 if (!mvm->error_recovery_buf)
951 return;
952
953 host_cmd.data[1] = mvm->error_recovery_buf;
954 host_cmd.len[1] = error_log_size;
955 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
956 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
957 }
958
959 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
960 kfree(mvm->error_recovery_buf);
961 mvm->error_recovery_buf = NULL;
962
963 if (ret) {
964 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
965 return;
966 }
967
968 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
969 if (flags & ERROR_RECOVERY_UPDATE_DB) {
970 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
971 if (resp)
972 IWL_ERR(mvm,
973 "Failed to send recovery cmd blob was invalid %d\n",
974 resp);
975 }
976}
977
42ce76d6
LC
978static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
979{
980 int ret;
981
39c1a972 982 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
42ce76d6
LC
983 if (ret < 0) {
984 IWL_DEBUG_RADIO(mvm,
69964905 985 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
42ce76d6 986 ret);
5d041c46
LC
987 /*
988 * If not available, don't fail and don't bother with EWRD.
989 * Return 1 to tell that we can't use WGDS either.
990 */
991 return 1;
42ce76d6
LC
992 }
993
39c1a972 994 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
69964905
LC
995 /* if EWRD is not available, we can still use WRDS, so don't fail */
996 if (ret < 0)
997 IWL_DEBUG_RADIO(mvm,
998 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
999 ret);
1000
42ce76d6 1001 ret = iwl_mvm_sar_select_profile(mvm, 1, 1);
5d041c46
LC
1002 /*
1003 * If we don't have profile 0 from BIOS, just skip it. This
1004 * means that SAR Geo will not be enabled either, even if we
1005 * have other valid profiles.
1006 */
42ce76d6 1007 if (ret == -ENOENT)
5d041c46 1008 return 1;
da2830ac
LC
1009
1010 return ret;
1011}
1012
1f370650 1013static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1014{
1f370650 1015 int ret;
8ca151b5 1016
7d6222e2 1017 if (iwl_mvm_has_unified_ucode(mvm))
1f370650 1018 return iwl_run_unified_mvm_ucode(mvm, false);
8ca151b5 1019
8d193ca2 1020 ret = iwl_run_init_mvm_ucode(mvm, false);
f2082a53 1021
f2082a53 1022 if (ret) {
8d193ca2 1023 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK
1024
1025 if (iwlmvm_mod_params.init_dbg)
1026 return 0;
1f370650 1027 return ret;
8d193ca2 1028 }
8ca151b5 1029
203c83d3 1030 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG
1031 iwl_trans_stop_device(mvm->trans);
1032 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1033 if (ret)
1f370650 1034 return ret;
8ca151b5 1035
b108d8c7 1036 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
da2eb669 1037
94022562 1038 mvm->rfkill_safe_init_done = false;
8ca151b5 1039 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS
1040 if (ret)
1041 return ret;
1042
94022562
EG
1043 mvm->rfkill_safe_init_done = true;
1044
b108d8c7
SM
1045 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1046 NULL);
da2eb669 1047
702e975d 1048 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS
1049}
1050
1051int iwl_mvm_up(struct iwl_mvm *mvm)
1052{
1053 int ret, i;
1054 struct ieee80211_channel *chan;
1055 struct cfg80211_chan_def chandef;
dd36a507 1056 struct ieee80211_supported_band *sband = NULL;
1f370650
SS
1057
1058 lockdep_assert_held(&mvm->mutex);
1059
1060 ret = iwl_trans_start_hw(mvm->trans);
1061 if (ret)
1062 return ret;
1063
1064 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB
1065 if (ret) {
1066 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
72d3c7bb
JB
1067 if (ret != -ERFKILL)
1068 iwl_fw_dbg_error_collect(&mvm->fwrt,
1069 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB
1070 goto error;
1071 }
1072
d0b813fc 1073 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1074
1f3b0ff8
LE
1075 ret = iwl_mvm_sf_update(mvm, NULL, false);
1076 if (ret)
1077 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1078
a1af4c48 1079 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS
1080 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1081 /* if we have a destination, assume EARLY START */
1082 if (mvm->fw->dbg.dest_tlv)
1083 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1084 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1085 }
6a951267 1086
a0544272 1087 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1088 if (ret)
1089 goto error;
1090
7d6222e2
JB
1091 if (!iwl_mvm_has_unified_ucode(mvm)) {
1092 /* Send phy db control command and then phy db calibration */
1f370650
SS
1093 ret = iwl_send_phy_db_data(mvm->phy_db);
1094 if (ret)
1095 goto error;
1f370650 1096 }
8ca151b5 1097
bb99ff9b
LC
1098 ret = iwl_send_phy_cfg_cmd(mvm);
1099 if (ret)
1100 goto error;
1101
b3de3ef4
EG
1102 ret = iwl_mvm_send_bt_init_conf(mvm);
1103 if (ret)
1104 goto error;
1105
43413a97 1106 /* Init RSS configuration */
286ca8eb 1107 if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
8edbfaa1
SS
1108 ret = iwl_configure_rxq(mvm);
1109 if (ret) {
1110 IWL_ERR(mvm, "Failed to configure RX queues: %d\n",
1111 ret);
1112 goto error;
1113 }
1114 }
1115
1116 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS
1117 ret = iwl_send_rss_cfg_cmd(mvm);
1118 if (ret) {
1119 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1120 ret);
1121 goto error;
1122 }
1123 }
1124
8ca151b5 1125 /* init the fw <-> mac80211 STA mapping */
0ae98812 1126 for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++)
8ca151b5
JB
1127 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1128
0ae98812 1129 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1130
b2b7875b
JB
1131 /* reset quota debouncing buffer - 0xff will yield invalid data */
1132 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1133
79660869
IL
1134 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1135 ret = iwl_mvm_send_dqa_cmd(mvm);
1136 if (ret)
1137 goto error;
1138 }
97d5be7e 1139
8ca151b5
JB
1140 /* Add auxiliary station for scanning */
1141 ret = iwl_mvm_add_aux_sta(mvm);
1142 if (ret)
1143 goto error;
1144
53a9d61e 1145 /* Add all the PHY contexts */
dd36a507
TM
1146 i = 0;
1147 while (!sband && i < NUM_NL80211_BANDS)
1148 sband = mvm->hw->wiphy->bands[i++];
1149
1150 if (WARN_ON_ONCE(!sband))
1151 goto error;
1152
1153 chan = &sband->channels[0];
1154
53a9d61e
IP
1155 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1156 for (i = 0; i < NUM_PHY_CTX; i++) {
1157 /*
1158 * The channel used here isn't relevant as it's
1159 * going to be overwritten in the other flows.
1160 * For now use the first channel we have.
1161 */
1162 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1163 &chandef, 1, 1);
1164 if (ret)
1165 goto error;
1166 }
8ca151b5 1167
c221daf2
CRI
1168 if (iwl_mvm_is_tt_in_fw(mvm)) {
1169 /* in order to give the responsibility of ct-kill and
1170 * TX backoff to FW we need to send empty temperature reporting
1171 * cmd during init time
1172 */
1173 iwl_mvm_send_temp_report_ths_cmd(mvm);
1174 } else {
1175 /* Initialize tx backoffs to the minimal possible */
1176 iwl_mvm_tt_tx_backoff(mvm, 0);
1177 }
5c89e7bc 1178
242d9c8b 1179#ifdef CONFIG_THERMAL
5c89e7bc 1180 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI
1181
1182 /*
1183 * In case there is no budget from BIOS / Platform NVM the default
1184 * budget should be 2000mW (cooling state 0).
1185 */
1186 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI
1187 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1188 mvm->cooling_dev.cur_state);
75cfe338
LC
1189 if (ret)
1190 goto error;
1191 }
c221daf2 1192#endif
0c0e2c71 1193
aa43ae12
AM
1194 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1195 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1196
c1cb92fc 1197 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB
1198 if (ret)
1199 goto error;
1200
35af15d1
AN
1201 /*
1202 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1203 * anyway, so don't init MCC.
1204 */
1205 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1206 ret = iwl_mvm_init_mcc(mvm);
1207 if (ret)
1208 goto error;
1209 }
90d4f7db 1210
859d914c 1211 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1212 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1213 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS
1214 ret = iwl_mvm_config_scan(mvm);
1215 if (ret)
1216 goto error;
1217 }
1218
f130bb75
MG
1219 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1220 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
1221
48e775e6
HD
1222 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1223 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1224
6ce1e5c0
GA
1225 ret = iwl_mvm_ppag_init(mvm);
1226 if (ret)
1227 goto error;
1228
da2830ac 1229 ret = iwl_mvm_sar_init(mvm);
5d041c46
LC
1230 if (ret == 0) {
1231 ret = iwl_mvm_sar_geo_init(mvm);
39c1a972 1232 } else if (ret > 0 && !iwl_sar_get_wgds_table(&mvm->fwrt)) {
5d041c46
LC
1233 /*
1234 * If basic SAR is not available, we check for WGDS,
1235 * which should *not* be available either. If it is
1236 * available, issue an error, because we can't use SAR
1237 * Geo without basic SAR.
1238 */
1239 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1240 }
da2830ac 1241
5d041c46 1242 if (ret < 0)
a6bff3cb
HD
1243 goto error;
1244
7089ae63
JB
1245 iwl_mvm_leds_sync(mvm);
1246
53a9d61e 1247 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB
1248 return 0;
1249 error:
f4744258 1250 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1251 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1252 return ret;
1253}
1254
1255int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1256{
1257 int ret, i;
1258
1259 lockdep_assert_held(&mvm->mutex);
1260
1261 ret = iwl_trans_start_hw(mvm->trans);
1262 if (ret)
1263 return ret;
1264
1265 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1266 if (ret) {
1267 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1268 goto error;
1269 }
1270
a0544272 1271 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1272 if (ret)
1273 goto error;
1274
1275 /* Send phy db control command and then phy db calibration*/
1276 ret = iwl_send_phy_db_data(mvm->phy_db);
1277 if (ret)
1278 goto error;
1279
1280 ret = iwl_send_phy_cfg_cmd(mvm);
1281 if (ret)
1282 goto error;
1283
1284 /* init the fw <-> mac80211 STA mapping */
0ae98812 1285 for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++)
8ca151b5
JB
1286 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1287
1288 /* Add auxiliary station for scanning */
1289 ret = iwl_mvm_add_aux_sta(mvm);
1290 if (ret)
1291 goto error;
1292
1293 return 0;
1294 error:
fcb6b92a 1295 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1296 return ret;
1297}
1298
0416841d
JB
1299void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1300 struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB
1301{
1302 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1303 struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1304 u32 flags = le32_to_cpu(card_state_notif->flags);
1305
1306 IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1307 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1308 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1309 (flags & CT_KILL_CARD_DISABLED) ?
1310 "Reached" : "Not reached");
8ca151b5
JB
1311}
1312
0416841d
JB
1313void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1314 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI
1315{
1316 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1317 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1318
0c8d0a47
GBA
1319 IWL_DEBUG_INFO(mvm,
1320 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1321 le32_to_cpu(mfuart_notif->installed_ver),
1322 le32_to_cpu(mfuart_notif->external_ver),
1323 le32_to_cpu(mfuart_notif->status),
1324 le32_to_cpu(mfuart_notif->duration));
1325
19f63c53
GBA
1326 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1327 IWL_DEBUG_INFO(mvm,
0c8d0a47 1328 "MFUART: image size: 0x%08x\n",
19f63c53 1329 le32_to_cpu(mfuart_notif->image_size));
30269c12 1330}