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wifi: iwlwifi: iwlmei: fix compilation error
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
a7de31d5 3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
8e99ea8d
JB		 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
a2ac0f48 9#include <linux/dmi.h>
8ca151b5
JB		 10
11#include "iwl-trans.h"
12#include "iwl-op-mode.h"
d962f9b1 13#include "fw/img.h"
8ca151b5 14#include "iwl-debug.h"
8c23f95c 15#include "iwl-prph.h"
813df5ce 16#include "fw/acpi.h"
b3e4c0f3 17#include "fw/pnvm.h"
8ca151b5
JB		 18
19#include "mvm.h"
7174beb6 20#include "fw/dbg.h"
8ca151b5 21#include "iwl-phy-db.h"
9c4f7d51
ST		 22#include "iwl-modparams.h"
23#include "iwl-nvm-parse.h"
cf85123a 24#include "time-sync.h"
8ca151b5 25
b3e4c0f3
LC		 26#define MVM_UCODE_ALIVE_TIMEOUT (HZ)
27#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5 28
c3f40c3e
MK		 29#define IWL_TAS_US_MCC 0x5553
30#define IWL_TAS_CANADA_MCC 0x4341
31
8ca151b5
JB		 32struct iwl_mvm_alive_data {
33 bool valid;
34 u32 scd_base_addr;
35};
36
8ca151b5
JB		 37static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
38{
39 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
40 .valid = cpu_to_le32(valid_tx_ant),
41 };
42
33223542 43 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 44 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB		 45 sizeof(tx_ant_cmd), &tx_ant_cmd);
46}
47
43413a97
SS		 48static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
49{
50 int i;
51 struct iwl_rss_config_cmd cmd = {
52 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS		 53 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
54 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
55 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
56 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
58 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS		 59 };
60
f43495fd
SS		 61 if (mvm->trans->num_rx_queues == 1)
62 return 0;
63
854d773e 64 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 65 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS		 66 cmd.indirection_table[i] =
67 1 + (i % (mvm->trans->num_rx_queues - 1));
68 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS		 69
70 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
71}
72
97d5be7e
LK		 73static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
74{
75 struct iwl_dqa_enable_cmd dqa_cmd = {
76 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
77 };
f0c86427 78 u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD);
97d5be7e
LK		 79 int ret;
80
81 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
82 if (ret)
83 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
84 else
85 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
86
87 return ret;
88}
89
bdccdb85
GBA		 90void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
91 struct iwl_rx_cmd_buffer *rxb)
92{
93 struct iwl_rx_packet *pkt = rxb_addr(rxb);
94 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
95 __le32 *dump_data = mfu_dump_notif->data;
96 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
97 int i;
98
99 if (mfu_dump_notif->index_num == 0)
100 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
101 le32_to_cpu(mfu_dump_notif->assert_id));
102
103 for (i = 0; i < n_words; i++)
104 IWL_DEBUG_INFO(mvm,
105 "MFUART assert dump, dword %u: 0x%08x\n",
106 le16_to_cpu(mfu_dump_notif->index_num) *
107 n_words + i,
108 le32_to_cpu(dump_data[i]));
109}
110
8ca151b5
JB		 111static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
112 struct iwl_rx_packet *pkt, void *data)
113{
fd1c3318 114 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB		 115 struct iwl_mvm *mvm =
116 container_of(notif_wait, struct iwl_mvm, notif_wait);
117 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS		 118 struct iwl_umac_alive *umac;
119 struct iwl_lmac_alive *lmac1;
120 struct iwl_lmac_alive *lmac2 = NULL;
121 u16 status;
cfa5d0ca 122 u32 lmac_error_event_table, umac_error_table;
708d8c53
JB		 123 u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
124 UCODE_ALIVE_NTFY, 0);
5053a451 125 u32 i;
b2f20cf2 126
01a9ca51 127
c0941ace
MS		 128 if (version == 6) {
129 struct iwl_alive_ntf_v6 *palive;
130
131 if (pkt_len < sizeof(*palive))
132 return false;
133
134 palive = (void *)pkt->data;
135 mvm->trans->dbg.imr_data.imr_enable =
136 le32_to_cpu(palive->imr.enabled);
137 mvm->trans->dbg.imr_data.imr_size =
138 le32_to_cpu(palive->imr.size);
139 mvm->trans->dbg.imr_data.imr2sram_remainbyte =
140 mvm->trans->dbg.imr_data.imr_size;
141 mvm->trans->dbg.imr_data.imr_base_addr =
142 palive->imr.base_addr;
143 mvm->trans->dbg.imr_data.imr_curr_addr =
144 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr);
145 IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n",
146 mvm->trans->dbg.imr_data.imr_enable,
147 mvm->trans->dbg.imr_data.imr_size,
148 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr));
5053a451
MS		 149
150 if (!mvm->trans->dbg.imr_data.imr_enable) {
151 for (i = 0; i < ARRAY_SIZE(mvm->trans->dbg.active_regions); i++) {
152 struct iwl_ucode_tlv *reg_tlv;
153 struct iwl_fw_ini_region_tlv *reg;
154
155 reg_tlv = mvm->trans->dbg.active_regions[i];
156 if (!reg_tlv)
157 continue;
158
159 reg = (void *)reg_tlv->data;
160 /*
161 * We have only one DRAM IMR region, so we
162 * can break as soon as we find the first
163 * one.
164 */
165 if (reg->type == IWL_FW_INI_REGION_DRAM_IMR) {
166 mvm->trans->dbg.unsupported_region_msk |= BIT(i);
167 break;
168 }
169 }
170 }
c0941ace
MS		 171 }
172
173 if (version >= 5) {
90824f2f
LC		 174 struct iwl_alive_ntf_v5 *palive;
175
fd1c3318
JB		 176 if (pkt_len < sizeof(*palive))
177 return false;
178
90824f2f
LC		 179 palive = (void *)pkt->data;
180 umac = &palive->umac_data;
181 lmac1 = &palive->lmac_data[0];
182 lmac2 = &palive->lmac_data[1];
183 status = le16_to_cpu(palive->status);
184
185 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
186 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
187 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
188
189 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
190 mvm->trans->sku_id[0],
191 mvm->trans->sku_id[1],
192 mvm->trans->sku_id[2]);
193 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC		 194 struct iwl_alive_ntf_v4 *palive;
195
fd1c3318
JB		 196 if (pkt_len < sizeof(*palive))
197 return false;
198
5c228d63
SS		 199 palive = (void *)pkt->data;
200 umac = &palive->umac_data;
201 lmac1 = &palive->lmac_data[0];
202 lmac2 = &palive->lmac_data[1];
203 status = le16_to_cpu(palive->status);
9422b978
LC		 204 } else if (iwl_rx_packet_payload_len(pkt) ==
205 sizeof(struct iwl_alive_ntf_v3)) {
206 struct iwl_alive_ntf_v3 *palive3;
207
fd1c3318
JB		 208 if (pkt_len < sizeof(*palive3))
209 return false;
210
5c228d63
SS		 211 palive3 = (void *)pkt->data;
212 umac = &palive3->umac_data;
213 lmac1 = &palive3->lmac_data;
214 status = le16_to_cpu(palive3->status);
9422b978
LC		 215 } else {
216 WARN(1, "unsupported alive notification (size %d)\n",
217 iwl_rx_packet_payload_len(pkt));
218 /* get timeout later */
219 return false;
5c228d63 220 }
01a9ca51 221
22463857
SM		 222 lmac_error_event_table =
223 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
224 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
225
5c228d63 226 if (lmac2)
91c28b83 227 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 228 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 229
4f7411d6
RG		 230 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
231 ~FW_ADDR_CACHE_CONTROL;
cfa5d0ca
MG		 232
233 if (umac_error_table) {
234 if (umac_error_table >=
834f920e 235 mvm->trans->cfg->min_umac_error_event_table) {
cfa5d0ca
MG		 236 iwl_fw_umac_set_alive_err_table(mvm->trans,
237 umac_error_table);
238 } else {
239 IWL_ERR(mvm,
240 "Not valid error log pointer 0x%08X for %s uCode\n",
241 umac_error_table,
242 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
243 "Init" : "RT");
244 }
3485e76e 245 }
fb5b2846 246
22463857 247 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 248 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 249
5c228d63
SS		 250 IWL_DEBUG_FW(mvm,
251 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
252 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 253
5c228d63
SS		 254 if (lmac2)
255 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 256
5c228d63
SS		 257 IWL_DEBUG_FW(mvm,
258 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
259 le32_to_cpu(umac->umac_major),
260 le32_to_cpu(umac->umac_minor));
8ca151b5 261
0a3a3e9e
SM		 262 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
263
8ca151b5
JB		 264 return true;
265}
266
1f370650
SS		 267static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
268 struct iwl_rx_packet *pkt, void *data)
269{
270 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
271
272 return true;
273}
274
8ca151b5
JB		 275static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
276 struct iwl_rx_packet *pkt, void *data)
277{
278 struct iwl_phy_db *phy_db = data;
279
280 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
281 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
282 return true;
283 }
284
ce1f2778 285 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB		 286
287 return false;
288}
289
a7de31d5
MG		 290static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
291{
184f10db
MG		 292#define IWL_FW_PRINT_REG_INFO(reg_name) \
293 IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
294
a7de31d5
MG		 295 struct iwl_trans *trans = mvm->trans;
296 enum iwl_device_family device_family = trans->trans_cfg->device_family;
297
298 if (device_family < IWL_DEVICE_FAMILY_8000)
299 return;
300
301 if (device_family <= IWL_DEVICE_FAMILY_9000)
184f10db 302 IWL_FW_PRINT_REG_INFO(WFPM_ARC1_PD_NOTIFICATION);
a7de31d5 303 else
184f10db 304 IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);
f2f17ca0 305
184f10db 306 IWL_FW_PRINT_REG_INFO(HPM_SECONDARY_DEVICE_STATE);
f2f17ca0 307
184f10db
MG		 308 /* print OPT info */
309 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_ADDR);
310 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_DATA);
a7de31d5
MG		 311}
312
8ca151b5
JB		 313static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
314 enum iwl_ucode_type ucode_type)
315{
316 struct iwl_notification_wait alive_wait;
94a8d87c 317 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 318 const struct fw_img *fw;
cfbc6c4c 319 int ret;
702e975d 320 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 321 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG		 322 bool run_in_rfkill =
323 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
5e31b3df
MS		 324 u8 count;
325 struct iwl_pc_data *pc_data;
8ca151b5 326
61df750c 327 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA		 328 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
329 !(fw_has_capa(&mvm->fw->ucode_capa,
330 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 331 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 332 else
612da1ef 333 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 334 if (WARN_ON(!fw))
8ca151b5 335 return -EINVAL;
702e975d 336 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 337 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB		 338
339 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
340 alive_cmd, ARRAY_SIZE(alive_cmd),
341 iwl_alive_fn, &alive_data);
342
b3500b47
EG		 343 /*
344 * We want to load the INIT firmware even in RFKILL
345 * For the unified firmware case, the ucode_type is not
346 * INIT, but we still need to run it.
347 */
348 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 349 if (ret) {
702e975d 350 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 351 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
352 return ret;
353 }
354
355 /*
356 * Some things may run in the background now, but we
357 * just wait for the ALIVE notification here.
358 */
359 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
360 MVM_UCODE_ALIVE_TIMEOUT);
56731878
DG		 361
362 if (mvm->trans->trans_cfg->device_family ==
363 IWL_DEVICE_FAMILY_AX210) {
364 /* print these registers regardless of alive fail/success */
365 IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n",
366 iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
367 IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n",
368 iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
369 IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n",
370 iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
b8133439
AS		 371 IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n",
372 iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
56731878
DG		 373 }
374
8ca151b5 375 if (ret) {
d6be9c1d
SS		 376 struct iwl_trans *trans = mvm->trans;
377
5667ccc2 378 /* SecBoot info */
20f5aef5
JB		 379 if (trans->trans_cfg->device_family >=
380 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS		 381 IWL_ERR(mvm,
382 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST		 383 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
384 iwl_read_umac_prph(trans,
385 UMAG_SB_CPU_2_STATUS));
5667ccc2
MG		 386 } else if (trans->trans_cfg->device_family >=
387 IWL_DEVICE_FAMILY_8000) {
388 IWL_ERR(mvm,
389 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
390 iwl_read_prph(trans, SB_CPU_1_STATUS),
391 iwl_read_prph(trans, SB_CPU_2_STATUS));
392 }
393
a7de31d5
MG		 394 iwl_mvm_print_pd_notification(mvm);
395
5667ccc2
MG		 396 /* LMAC/UMAC PC info */
397 if (trans->trans_cfg->device_family >=
5e31b3df
MS		 398 IWL_DEVICE_FAMILY_22000) {
399 pc_data = trans->dbg.pc_data;
400 for (count = 0; count < trans->dbg.num_pc;
401 count++, pc_data++)
402 IWL_ERR(mvm, "%s: 0x%x\n",
403 pc_data->pc_name,
404 pc_data->pc_address);
405 } else if (trans->trans_cfg->device_family >=
5667ccc2 406 IWL_DEVICE_FAMILY_9000) {
20f5aef5
JB		 407 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
408 iwl_read_umac_prph(trans,
409 UREG_UMAC_CURRENT_PC));
410 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
411 iwl_read_umac_prph(trans,
412 UREG_LMAC1_CURRENT_PC));
413 if (iwl_mvm_is_cdb_supported(mvm))
414 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
415 iwl_read_umac_prph(trans,
416 UREG_LMAC2_CURRENT_PC));
20f5aef5
JB		 417 }
418
b8133439 419 if (ret == -ETIMEDOUT && !mvm->pldr_sync)
20f5aef5
JB		 420 iwl_fw_dbg_error_collect(&mvm->fwrt,
421 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
422
702e975d 423 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 424 return ret;
425 }
426
427 if (!alive_data.valid) {
428 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 429 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 430 return -EIO;
431 }
432
f31f7cd9
GG		 433 /* if reached this point, Alive notification was received */
434 iwl_mei_alive_notif(true);
733eb54f 435
b3e4c0f3 436 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait);
70d3ca86
LC		 437 if (ret) {
438 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
439 iwl_fw_set_current_image(&mvm->fwrt, old_type);
440 return ret;
441 }
442
8ca151b5
JB		 443 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
444
445 /*
446 * Note: all the queues are enabled as part of the interface
447 * initialization, but in firmware restart scenarios they
448 * could be stopped, so wake them up. In firmware restart,
449 * mac80211 will have the queues stopped as well until the
450 * reconfiguration completes. During normal startup, they
451 * will be empty.
452 */
453
4ecafae9 454 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB		 455 /*
456 * Set a 'fake' TID for the command queue, since we use the
457 * hweight() of the tid_bitmap as a refcount now. Not that
458 * we ever even consider the command queue as one we might
459 * want to reuse, but be safe nevertheless.
460 */
461 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
462 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 463
65b280fe 464 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC		 465#ifdef CONFIG_IWLWIFI_DEBUGFS
466 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
467#endif
8ca151b5 468
d3d9b4fc
EG		 469 /*
470 * All the BSSes in the BSS table include the GP2 in the system
471 * at the beacon Rx time, this is of course no longer relevant
472 * since we are resetting the firmware.
473 * Purge all the BSS table.
474 */
475 cfg80211_bss_flush(mvm->hw->wiphy);
476
8ca151b5
JB		 477 return 0;
478}
8ca151b5 479
c4ace426
GA		 480#ifdef CONFIG_ACPI
481static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
482 struct iwl_phy_specific_cfg *phy_filters)
483{
484 /*
485 * TODO: read specific phy config from BIOS
486 * ACPI table for this feature has not been defined yet,
487 * so for now we use hardcoded values.
488 */
489
490 if (IWL_MVM_PHY_FILTER_CHAIN_A) {
491 phy_filters->filter_cfg_chain_a =
492 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
493 }
494 if (IWL_MVM_PHY_FILTER_CHAIN_B) {
495 phy_filters->filter_cfg_chain_b =
496 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
497 }
498 if (IWL_MVM_PHY_FILTER_CHAIN_C) {
499 phy_filters->filter_cfg_chain_c =
500 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
501 }
502 if (IWL_MVM_PHY_FILTER_CHAIN_D) {
503 phy_filters->filter_cfg_chain_d =
504 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
505 }
506}
c4ace426
GA		 507#else /* CONFIG_ACPI */
508
509static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
510 struct iwl_phy_specific_cfg *phy_filters)
511{
512}
513#endif /* CONFIG_ACPI */
514
c593d2fa
AB		 515#if defined(CONFIG_ACPI) && defined(CONFIG_EFI)
516static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
517{
518 u8 cmd_ver;
519 int ret;
520 struct iwl_host_cmd cmd = {
521 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
522 SAR_OFFSET_MAPPING_TABLE_CMD),
523 .flags = 0,
524 .data[0] = &mvm->fwrt.sgom_table,
525 .len[0] = sizeof(mvm->fwrt.sgom_table),
526 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
527 };
528
529 if (!mvm->fwrt.sgom_enabled) {
530 IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n");
531 return 0;
532 }
533
971cbe50 534 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
c593d2fa
AB		 535 IWL_FW_CMD_VER_UNKNOWN);
536
537 if (cmd_ver != 2) {
538 IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n",
539 cmd_ver);
540 return 0;
541 }
542
543 ret = iwl_mvm_send_cmd(mvm, &cmd);
544 if (ret < 0)
545 IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret);
546
547 return ret;
548}
549#else
550
551static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
552{
553 return 0;
554}
555#endif
556
8ca151b5
JB		 557static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
558{
971cbe50 559 u32 cmd_id = PHY_CONFIGURATION_CMD;
c4ace426 560 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 561 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA		 562 struct iwl_phy_specific_cfg phy_filters = {};
563 u8 cmd_ver;
564 size_t cmd_size;
8ca151b5 565
bb99ff9b 566 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 567 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 568 return 0;
d923b020
LC		 569
570 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC		 571 /*
572 * TODO: currently we don't set the antenna but letting the NIC
573 * to decide which antenna to use. This should come from BIOS.
574 */
575 phy_cfg_cmd.phy_cfg =
576 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
577 }
578
8ca151b5 579 /* Set parameters */
a0544272 580 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC		 581
582 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC		 583 phy_cfg_cmd.phy_cfg |=
584 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 585
8ca151b5
JB		 586 phy_cfg_cmd.calib_control.event_trigger =
587 mvm->fw->default_calib[ucode_type].event_trigger;
588 phy_cfg_cmd.calib_control.flow_trigger =
589 mvm->fw->default_calib[ucode_type].flow_trigger;
590
971cbe50 591 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 592 IWL_FW_CMD_VER_UNKNOWN);
c4ace426
GA		 593 if (cmd_ver == 3) {
594 iwl_mvm_phy_filter_init(mvm, &phy_filters);
595 memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
596 sizeof(struct iwl_phy_specific_cfg));
597 }
598
8ca151b5
JB		 599 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
600 phy_cfg_cmd.phy_cfg);
c4ace426
GA		 601 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
602 sizeof(struct iwl_phy_cfg_cmd_v1);
971cbe50 603 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd);
8ca151b5
JB		 604}
605
e305a408
MS		 606static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
607{
608 struct iwl_notification_wait init_wait;
609 struct iwl_nvm_access_complete_cmd nvm_complete = {};
610 struct iwl_init_extended_cfg_cmd init_cfg = {
611 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
612 };
613 static const u16 init_complete[] = {
614 INIT_COMPLETE_NOTIF,
615 };
616 int ret;
617
618 if (mvm->trans->cfg->tx_with_siso_diversity)
619 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
620
621 lockdep_assert_held(&mvm->mutex);
622
623 mvm->rfkill_safe_init_done = false;
624
625 iwl_init_notification_wait(&mvm->notif_wait,
626 &init_wait,
627 init_complete,
628 ARRAY_SIZE(init_complete),
629 iwl_wait_init_complete,
630 NULL);
631
632 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
633
634 /* Will also start the device */
635 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
636 if (ret) {
637 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
638 goto error;
639 }
640 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
641 NULL);
642
643 /* Send init config command to mark that we are sending NVM access
644 * commands
645 */
646 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
647 INIT_EXTENDED_CFG_CMD),
648 CMD_SEND_IN_RFKILL,
649 sizeof(init_cfg), &init_cfg);
650 if (ret) {
651 IWL_ERR(mvm, "Failed to run init config command: %d\n",
652 ret);
653 goto error;
654 }
655
656 /* Load NVM to NIC if needed */
657 if (mvm->nvm_file_name) {
658 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
659 mvm->nvm_sections);
660 if (ret)
661 goto error;
662 ret = iwl_mvm_load_nvm_to_nic(mvm);
663 if (ret)
664 goto error;
665 }
666
667 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
668 ret = iwl_nvm_init(mvm);
669 if (ret) {
670 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
671 goto error;
672 }
673 }
674
675 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
676 NVM_ACCESS_COMPLETE),
677 CMD_SEND_IN_RFKILL,
678 sizeof(nvm_complete), &nvm_complete);
679 if (ret) {
680 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
681 ret);
682 goto error;
683 }
684
d2ccc5c1
MS		 685 ret = iwl_send_phy_cfg_cmd(mvm);
686 if (ret) {
687 IWL_ERR(mvm, "Failed to run PHY configuration: %d\n",
688 ret);
689 goto error;
690 }
691
e305a408
MS		 692 /* We wait for the INIT complete notification */
693 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
694 MVM_UCODE_ALIVE_TIMEOUT);
695 if (ret)
696 return ret;
697
698 /* Read the NVM only at driver load time, no need to do this twice */
699 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
700 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
701 if (IS_ERR(mvm->nvm_data)) {
702 ret = PTR_ERR(mvm->nvm_data);
703 mvm->nvm_data = NULL;
704 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
705 return ret;
706 }
707 }
708
709 mvm->rfkill_safe_init_done = true;
710
711 return 0;
712
713error:
714 iwl_remove_notification(&mvm->notif_wait, &init_wait);
715 return ret;
716}
717
3b25f1af 718int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB		 719{
720 struct iwl_notification_wait calib_wait;
6eb031d2 721 static const u16 init_complete[] = {
8ca151b5
JB		 722 INIT_COMPLETE_NOTIF,
723 CALIB_RES_NOTIF_PHY_DB
724 };
725 int ret;
726
7d6222e2 727 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 728 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 729
8ca151b5
JB		 730 lockdep_assert_held(&mvm->mutex);
731
94022562 732 mvm->rfkill_safe_init_done = false;
8ca151b5
JB		 733
734 iwl_init_notification_wait(&mvm->notif_wait,
735 &calib_wait,
736 init_complete,
737 ARRAY_SIZE(init_complete),
738 iwl_wait_phy_db_entry,
739 mvm->phy_db);
740
11f8c533
LC		 741 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
742
8ca151b5
JB		 743 /* Will also start the device */
744 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
745 if (ret) {
746 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 747 goto remove_notif;
8ca151b5
JB		 748 }
749
7d34a7d7 750 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG		 751 ret = iwl_mvm_send_bt_init_conf(mvm);
752 if (ret)
00e0c6c8 753 goto remove_notif;
b3de3ef4 754 }
931d4160 755
81a67e32 756 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 757 if (!mvm->nvm_data) {
5bd1d2c1 758 ret = iwl_nvm_init(mvm);
8ca151b5
JB		 759 if (ret) {
760 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 761 goto remove_notif;
8ca151b5
JB		 762 }
763 }
764
81a67e32 765 /* In case we read the NVM from external file, load it to the NIC */
9ce505fe
AN		 766 if (mvm->nvm_file_name) {
767 ret = iwl_mvm_load_nvm_to_nic(mvm);
768 if (ret)
769 goto remove_notif;
770 }
81a67e32 771
64866e5d
LC		 772 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
773 "Too old NVM version (0x%0x, required = 0x%0x)",
774 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 775
4f59334b
EH		 776 /*
777 * abort after reading the nvm in case RF Kill is on, we will complete
778 * the init seq later when RF kill will switch to off
779 */
1a3fe0b2 780 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH		 781 IWL_DEBUG_RF_KILL(mvm,
782 "jump over all phy activities due to RF kill\n");
00e0c6c8 783 goto remove_notif;
4f59334b
EH		 784 }
785
b3500b47 786 mvm->rfkill_safe_init_done = true;
31b8b343 787
e07cbb53 788 /* Send TX valid antennas before triggering calibrations */
a0544272 789 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 790 if (ret)
00e0c6c8 791 goto remove_notif;
e07cbb53 792
8ca151b5
JB		 793 ret = iwl_send_phy_cfg_cmd(mvm);
794 if (ret) {
795 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
796 ret);
00e0c6c8 797 goto remove_notif;
8ca151b5
JB		 798 }
799
800 /*
801 * Some things may run in the background now, but we
802 * just wait for the calibration complete notification.
803 */
804 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC		 805 MVM_UCODE_CALIB_TIMEOUT);
806 if (!ret)
807 goto out;
31b8b343 808
00e0c6c8 809 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 810 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC		 811 ret = 0;
812 } else {
813 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
814 ret);
31b8b343 815 }
00e0c6c8 816
8ca151b5
JB		 817 goto out;
818
00e0c6c8 819remove_notif:
8ca151b5
JB		 820 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
821out:
b3500b47 822 mvm->rfkill_safe_init_done = false;
a4082843 823 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB		 824 /* we want to debug INIT and we have no NVM - fake */
825 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
826 sizeof(struct ieee80211_channel) +
827 sizeof(struct ieee80211_rate),
828 GFP_KERNEL);
829 if (!mvm->nvm_data)
830 return -ENOMEM;
8ca151b5
JB		 831 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
832 mvm->nvm_data->bands[0].n_channels = 1;
833 mvm->nvm_data->bands[0].n_bitrates = 1;
834 mvm->nvm_data->bands[0].bitrates =
3827cb59 835 (void *)((u8 *)mvm->nvm_data->channels + 1);
8ca151b5
JB		 836 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
837 }
838
839 return ret;
840}
841
84bfffa9
EG		 842static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
843{
844 struct iwl_ltr_config_cmd cmd = {
845 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
846 };
847
848 if (!mvm->trans->ltr_enabled)
849 return 0;
850
84bfffa9
EG		 851 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
852 sizeof(cmd), &cmd);
853}
854
c386dacb 855#ifdef CONFIG_ACPI
42ce76d6 856int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 857{
971cbe50 858 u32 cmd_id = REDUCE_TX_POWER_CMD;
216cdfb5
LC		 859 struct iwl_dev_tx_power_cmd cmd = {
860 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 861 };
9c08cef8 862 __le16 *per_chain;
1edd56e6 863 int ret;
39c1a972 864 u16 len = 0;
fbb7957d 865 u32 n_subbands;
971cbe50 866 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 867 IWL_FW_CMD_VER_UNKNOWN);
b0aa02b3
AB		 868 if (cmd_ver == 7) {
869 len = sizeof(cmd.v7);
870 n_subbands = IWL_NUM_SUB_BANDS_V2;
871 per_chain = cmd.v7.per_chain[0][0];
872 cmd.v7.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags);
873 } else if (cmd_ver == 6) {
fbb7957d
LC		 874 len = sizeof(cmd.v6);
875 n_subbands = IWL_NUM_SUB_BANDS_V2;
876 per_chain = cmd.v6.per_chain[0][0];
877 } else if (fw_has_api(&mvm->fw->ucode_capa,
878 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 879 len = sizeof(cmd.v5);
e12cfc7b 880 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 881 per_chain = cmd.v5.per_chain[0][0];
882 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 883 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 884 len = sizeof(cmd.v4);
e12cfc7b 885 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 886 per_chain = cmd.v4.per_chain[0][0];
887 } else {
216cdfb5 888 len = sizeof(cmd.v3);
e12cfc7b 889 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 890 per_chain = cmd.v3.per_chain[0][0];
891 }
55bfa4b9 892
216cdfb5
LC		 893 /* all structs have the same common part, add it */
894 len += sizeof(cmd.common);
da2830ac 895
dac7171c
LC		 896 ret = iwl_sar_select_profile(&mvm->fwrt, per_chain,
897 IWL_NUM_CHAIN_TABLES,
fbb7957d 898 n_subbands, prof_a, prof_b);
1edd56e6
LC		 899
900 /* return on error or if the profile is disabled (positive number) */
901 if (ret)
902 return ret;
903
6d19a5eb
EG		 904 iwl_mei_set_power_limit(per_chain);
905
42ce76d6 906 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
971cbe50 907 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
42ce76d6
LC		 908}
909
7fe90e0e
HD		 910int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
911{
dd2a1256 912 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 913 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 914 u16 len;
39c1a972 915 int ret;
c8611331
JB		 916 struct iwl_host_cmd cmd = {
917 .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD),
918 .flags = CMD_WANT_SKB,
919 .data = { &geo_tx_cmd },
920 };
971cbe50 921 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
e80bfd11 922 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 923
dd2a1256
LC		 924 /* the ops field is at the same spot for all versions, so set in v1 */
925 geo_tx_cmd.v1.ops =
926 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
927
97f8a3d1
AB		 928 if (cmd_ver == 5)
929 len = sizeof(geo_tx_cmd.v5);
930 else if (cmd_ver == 4)
931 len = sizeof(geo_tx_cmd.v4);
932 else if (cmd_ver == 3)
0ea788ed
LC		 933 len = sizeof(geo_tx_cmd.v3);
934 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
935 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC		 936 len = sizeof(geo_tx_cmd.v2);
937 else
938 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 939
39c1a972
IZ		 940 if (!iwl_sar_geo_support(&mvm->fwrt))
941 return -EOPNOTSUPP;
942
c8611331 943 cmd.len[0] = len;
7fe90e0e
HD		 944
945 ret = iwl_mvm_send_cmd(mvm, &cmd);
946 if (ret) {
947 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
948 return ret;
949 }
f604324e
LC		 950
951 resp = (void *)cmd.resp_pkt->data;
952 ret = le32_to_cpu(resp->profile_idx);
953
97f8a3d1 954 if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES_REV3))
f604324e
LC		 955 ret = -EIO;
956
7fe90e0e
HD		 957 iwl_free_resp(&cmd);
958 return ret;
959}
960
a6bff3cb
HD		 961static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
962{
971cbe50 963 u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD);
dd2a1256 964 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 965 u16 len;
45acebf8 966 u32 n_bands;
97f8a3d1 967 u32 n_profiles;
ac9952f6 968 u32 sk = 0;
0433ae55 969 int ret;
971cbe50 970 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 971 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 972
45acebf8
NG		 973 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
974 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
975 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
97f8a3d1
AB		 976 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) ||
977 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) !=
978 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) ||
979 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) !=
980 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops));
981
dd2a1256
LC		 982 /* the ops field is at the same spot for all versions, so set in v1 */
983 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 984
97f8a3d1
AB		 985 if (cmd_ver == 5) {
986 len = sizeof(cmd.v5);
987 n_bands = ARRAY_SIZE(cmd.v5.table[0]);
988 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
989 } else if (cmd_ver == 4) {
990 len = sizeof(cmd.v4);
991 n_bands = ARRAY_SIZE(cmd.v4.table[0]);
992 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
993 } else if (cmd_ver == 3) {
0ea788ed 994 len = sizeof(cmd.v3);
45acebf8 995 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
97f8a3d1 996 n_profiles = ACPI_NUM_GEO_PROFILES;
0ea788ed
LC		 997 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
998 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 999 len = sizeof(cmd.v2);
45acebf8 1000 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
97f8a3d1 1001 n_profiles = ACPI_NUM_GEO_PROFILES;
39c1a972 1002 } else {
dd2a1256 1003 len = sizeof(cmd.v1);
45acebf8 1004 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
97f8a3d1 1005 n_profiles = ACPI_NUM_GEO_PROFILES;
0c3d7282
HD		 1006 }
1007
45acebf8
NG		 1008 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
1009 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
1010 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
97f8a3d1
AB		 1011 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) ||
1012 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) !=
1013 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) ||
1014 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) !=
1015 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table));
45acebf8 1016 /* the table is at the same position for all versions, so set use v1 */
97f8a3d1
AB		 1017 ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0],
1018 n_bands, n_profiles);
45acebf8
NG		 1019
1020 /*
1021 * It is a valid scenario to not support SAR, or miss wgds table,
1022 * but in that case there is no need to send the command.
1023 */
1024 if (ret)
1025 return 0;
1026
ac9952f6
LC		 1027 /* Only set to South Korea if the table revision is 1 */
1028 if (mvm->fwrt.geo_rev == 1)
1029 sk = 1;
1030
28db1862 1031 /*
ac9952f6
LC		 1032 * Set the table_revision to South Korea (1) or not (0). The
1033 * element name is misleading, as it doesn't contain the table
1034 * revision number, but whether the South Korea variation
1035 * should be used.
28db1862
LC		 1036 * This must be done after calling iwl_sar_geo_init().
1037 */
97f8a3d1 1038 if (cmd_ver == 5)
ac9952f6 1039 cmd.v5.table_revision = cpu_to_le32(sk);
97f8a3d1 1040 else if (cmd_ver == 4)
ac9952f6 1041 cmd.v4.table_revision = cpu_to_le32(sk);
97f8a3d1 1042 else if (cmd_ver == 3)
ac9952f6 1043 cmd.v3.table_revision = cpu_to_le32(sk);
28db1862
LC		 1044 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
1045 IWL_UCODE_TLV_API_SAR_TABLE_VER))
ac9952f6 1046 cmd.v2.table_revision = cpu_to_le32(sk);
28db1862 1047
971cbe50 1048 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
6ce1e5c0
GA		 1049}
1050
1051int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1052{
8bdc52b9 1053 union iwl_ppag_table_cmd cmd;
e8e10a37 1054 int ret, cmd_size;
160bab43 1055
e8e10a37 1056 ret = iwl_read_ppag_table(&mvm->fwrt, &cmd, &cmd_size);
b20bdd9c 1057 /* Not supporting PPAG table is a valid scenario */
473bc264 1058 if (ret < 0)
b20bdd9c 1059 return 0;
6ce1e5c0 1060
f2134f66 1061 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA		 1062 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1063 PER_PLATFORM_ANT_GAIN_CMD),
8bdc52b9 1064 0, cmd_size, &cmd);
6ce1e5c0
GA		 1065 if (ret < 0)
1066 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1067 ret);
1068
1069 return ret;
1070}
1071
1072static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1073{
78a19d52 1074 /* no need to read the table, done in INIT stage */
e8e10a37 1075 if (!(iwl_acpi_is_ppag_approved(&mvm->fwrt)))
a2ac0f48 1076 return 0;
a2ac0f48 1077
6ce1e5c0
GA		 1078 return iwl_mvm_ppag_send_cmd(mvm);
1079}
1080
2856f623
AB		 1081static const struct dmi_system_id dmi_tas_approved_list[] = {
1082 { .ident = "HP",
1083 .matches = {
1084 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1085 },
1086 },
1087 { .ident = "SAMSUNG",
1088 .matches = {
1089 DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
1090 },
1091 },
1092 { .ident = "LENOVO",
1093 .matches = {
1094 DMI_MATCH(DMI_SYS_VENDOR, "Lenovo"),
1095 },
1096 },
1097 { .ident = "DELL",
1098 .matches = {
1099 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1100 },
1101 },
3ecf3411
AG		 1102 { .ident = "MSFT",
1103 .matches = {
1104 DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
1105 },
1106 },
2856f623
AB		 1107
1108 /* keep last */
1109 {}
1110};
1111
9457077d
AN		 1112bool iwl_mvm_is_vendor_in_approved_list(void)
1113{
1114 return dmi_check_system(dmi_tas_approved_list);
1115}
1116
c3f40c3e
MK		 1117static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc)
1118{
1119 int i;
1120 u32 size = le32_to_cpu(*le_size);
1121
1122 /* Verify that there is room for another country */
1123 if (size >= IWL_TAS_BLOCK_LIST_MAX)
1124 return false;
1125
1126 for (i = 0; i < size; i++) {
1127 if (list[i] == cpu_to_le32(mcc))
1128 return true;
1129 }
1130
1131 list[size++] = cpu_to_le32(mcc);
1132 *le_size = cpu_to_le32(size);
1133 return true;
1134}
1135
28dd7ccd
MG		 1136static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1137{
971cbe50 1138 u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG);
28dd7ccd 1139 int ret;
6da7ba3a
AB		 1140 union iwl_tas_config_cmd cmd = {};
1141 int cmd_size, fw_ver;
28dd7ccd 1142
6da7ba3a 1143 BUILD_BUG_ON(ARRAY_SIZE(cmd.v3.block_list_array) <
28dd7ccd
MG		 1144 APCI_WTAS_BLACK_LIST_MAX);
1145
1146 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1147 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1148 return;
1149 }
1150
971cbe50
JB		 1151 fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
1152 IWL_FW_CMD_VER_UNKNOWN);
6da7ba3a
AB		 1153
1154 ret = iwl_acpi_get_tas(&mvm->fwrt, &cmd, fw_ver);
28dd7ccd
MG		 1155 if (ret < 0) {
1156 IWL_DEBUG_RADIO(mvm,
1157 "TAS table invalid or unavailable. (%d)\n",
1158 ret);
1159 return;
1160 }
1161
7c530588 1162 if (ret == 0)
28dd7ccd
MG		 1163 return;
1164
c3f40c3e
MK		 1165 if (!dmi_check_system(dmi_tas_approved_list)) {
1166 IWL_DEBUG_RADIO(mvm,
1167 "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
1168 dmi_get_system_info(DMI_SYS_VENDOR));
6da7ba3a
AB		 1169 if ((!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1170 &cmd.v4.block_list_size,
1171 IWL_TAS_US_MCC)) ||
1172 (!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1173 &cmd.v4.block_list_size,
1174 IWL_TAS_CANADA_MCC))) {
c3f40c3e
MK		 1175 IWL_DEBUG_RADIO(mvm,
1176 "Unable to add US/Canada to TAS block list, disabling TAS\n");
1177 return;
1178 }
1179 }
1180
6da7ba3a
AB		 1181 /* v4 is the same size as v3, so no need to differentiate here */
1182 cmd_size = fw_ver < 3 ?
7c530588
MK		 1183 sizeof(struct iwl_tas_config_cmd_v2) :
1184 sizeof(struct iwl_tas_config_cmd_v3);
28dd7ccd 1185
971cbe50 1186 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd);
28dd7ccd
MG		 1187 if (ret < 0)
1188 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1189}
f5b1cb2e 1190
4e8fe214
GG		 1191static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1192{
1193 u8 value;
45fe1b6b 1194 int ret = iwl_acpi_get_dsm_u8(mvm->fwrt.dev, 0, DSM_RFI_FUNC_ENABLE,
4e8fe214
GG		 1195 &iwl_rfi_guid, &value);
1196
1197 if (ret < 0) {
1198 IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
1199
1200 } else if (value >= DSM_VALUE_RFI_MAX) {
1201 IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n",
1202 value);
1203
1204 } else if (value == DSM_VALUE_RFI_ENABLE) {
1205 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
1206 return DSM_VALUE_RFI_ENABLE;
1207 }
1208
1209 IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n");
1210
1211 /* default behaviour is disabled */
1212 return DSM_VALUE_RFI_DISABLE;
1213}
1214
f5b1cb2e
GA		 1215static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1216{
7119f02b
MK		 1217 int ret;
1218 u32 value;
8f323d06 1219 struct iwl_lari_config_change_cmd_v6 cmd = {};
f5b1cb2e 1220
f21afaba 1221 cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt);
d2bfda8a 1222
45fe1b6b 1223 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_11AX_ENABLEMENT,
7119f02b
MK		 1224 &iwl_guid, &value);
1225 if (!ret)
1226 cmd.oem_11ax_allow_bitmap = cpu_to_le32(value);
f5b1cb2e 1227
45fe1b6b 1228 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
54b4fda5
AN		 1229 DSM_FUNC_ENABLE_UNII4_CHAN,
1230 &iwl_guid, &value);
1231 if (!ret)
1232 cmd.oem_unii4_allow_bitmap = cpu_to_le32(value);
1233
45fe1b6b 1234 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1f578d4f
MK		 1235 DSM_FUNC_ACTIVATE_CHANNEL,
1236 &iwl_guid, &value);
1237 if (!ret)
1238 cmd.chan_state_active_bitmap = cpu_to_le32(value);
1239
698b166e
LC		 1240 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1241 DSM_FUNC_ENABLE_6E,
1242 &iwl_guid, &value);
1243 if (!ret)
1244 cmd.oem_uhb_allow_bitmap = cpu_to_le32(value);
1245
8f323d06
AB		 1246 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1247 DSM_FUNC_FORCE_DISABLE_CHANNELS,
1248 &iwl_guid, &value);
1249 if (!ret)
1250 cmd.force_disable_channels_bitmap = cpu_to_le32(value);
1251
54b4fda5 1252 if (cmd.config_bitmap ||
698b166e 1253 cmd.oem_uhb_allow_bitmap ||
54b4fda5 1254 cmd.oem_11ax_allow_bitmap ||
1f578d4f 1255 cmd.oem_unii4_allow_bitmap ||
8f323d06
AB		 1256 cmd.chan_state_active_bitmap ||
1257 cmd.force_disable_channels_bitmap) {
3c21990b
MK		 1258 size_t cmd_size;
1259 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw,
971cbe50
JB		 1260 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1261 LARI_CONFIG_CHANGE),
1262 1);
8f323d06
AB		 1263 switch (cmd_ver) {
1264 case 6:
1265 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v6);
1266 break;
1267 case 5:
1f578d4f 1268 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v5);
8f323d06
AB		 1269 break;
1270 case 4:
54b4fda5 1271 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4);
8f323d06
AB		 1272 break;
1273 case 3:
3c21990b 1274 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3);
8f323d06
AB		 1275 break;
1276 case 2:
3c21990b 1277 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2);
8f323d06
AB		 1278 break;
1279 default:
3c21990b 1280 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1);
8f323d06
AB		 1281 break;
1282 }
3c21990b 1283
3ce88247 1284 IWL_DEBUG_RADIO(mvm,
7119f02b
MK		 1285 "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n",
1286 le32_to_cpu(cmd.config_bitmap),
1287 le32_to_cpu(cmd.oem_11ax_allow_bitmap));
54b4fda5 1288 IWL_DEBUG_RADIO(mvm,
1f578d4f 1289 "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, chan_state_active_bitmap=0x%x, cmd_ver=%d\n",
54b4fda5 1290 le32_to_cpu(cmd.oem_unii4_allow_bitmap),
1f578d4f 1291 le32_to_cpu(cmd.chan_state_active_bitmap),
54b4fda5 1292 cmd_ver);
698b166e 1293 IWL_DEBUG_RADIO(mvm,
8f323d06
AB		 1294 "sending LARI_CONFIG_CHANGE, oem_uhb_allow_bitmap=0x%x, force_disable_channels_bitmap=0x%x\n",
1295 le32_to_cpu(cmd.oem_uhb_allow_bitmap),
1296 le32_to_cpu(cmd.force_disable_channels_bitmap));
7119f02b
MK		 1297 ret = iwl_mvm_send_cmd_pdu(mvm,
1298 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1299 LARI_CONFIG_CHANGE),
1300 0, cmd_size, &cmd);
1301 if (ret < 0)
f5b1cb2e
GA		 1302 IWL_DEBUG_RADIO(mvm,
1303 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
7119f02b 1304 ret);
f5b1cb2e
GA		 1305 }
1306}
78a19d52
MK		 1307
1308void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1309{
1310 int ret;
1311
1312 /* read PPAG table */
e8e10a37 1313 ret = iwl_acpi_get_ppag_table(&mvm->fwrt);
78a19d52
MK		 1314 if (ret < 0) {
1315 IWL_DEBUG_RADIO(mvm,
1316 "PPAG BIOS table invalid or unavailable. (%d)\n",
1317 ret);
1318 }
1319
1320 /* read SAR tables */
1321 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
1322 if (ret < 0) {
1323 IWL_DEBUG_RADIO(mvm,
1324 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1325 ret);
1326 /*
1327 * If not available, don't fail and don't bother with EWRD and
1328 * WGDS */
1329
1330 if (!iwl_sar_get_wgds_table(&mvm->fwrt)) {
1331 /*
1332 * If basic SAR is not available, we check for WGDS,
1333 * which should *not* be available either. If it is
1334 * available, issue an error, because we can't use SAR
1335 * Geo without basic SAR.
1336 */
1337 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1338 }
1339
1340 } else {
1341 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
1342 /* if EWRD is not available, we can still use
1343 * WRDS, so don't fail */
1344 if (ret < 0)
1345 IWL_DEBUG_RADIO(mvm,
1346 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1347 ret);
1348
1349 /* read geo SAR table */
1350 if (iwl_sar_geo_support(&mvm->fwrt)) {
1351 ret = iwl_sar_get_wgds_table(&mvm->fwrt);
1352 if (ret < 0)
1353 IWL_DEBUG_RADIO(mvm,
1354 "Geo SAR BIOS table invalid or unavailable. (%d)\n",
1355 ret);
1356 /* we don't fail if the table is not available */
1357 }
1358 }
1359}
69964905 1360#else /* CONFIG_ACPI */
69964905 1361
39c1a972
IZ		 1362inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1363 int prof_a, int prof_b)
69964905 1364{
78a19d52 1365 return 1;
69964905 1366}
a6bff3cb 1367
39c1a972 1368inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC		 1369{
1370 return -ENOENT;
1371}
1372
a6bff3cb
HD		 1373static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1374{
1375 return 0;
1376}
18f1755d 1377
6ce1e5c0
GA		 1378int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1379{
1380 return -ENOENT;
1381}
1382
1383static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1384{
7937fd32 1385 return 0;
6ce1e5c0 1386}
28dd7ccd
MG		 1387
1388static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1389{
1390}
f5b1cb2e
GA		 1391
1392static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1393{
1394}
4e8fe214 1395
9457077d
AN		 1396bool iwl_mvm_is_vendor_in_approved_list(void)
1397{
1398 return false;
1399}
1400
4e8fe214
GG		 1401static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1402{
1403 return DSM_VALUE_RFI_DISABLE;
1404}
78a19d52
MK		 1405
1406void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1407{
1408}
c593d2fa 1409
69964905
LC		 1410#endif /* CONFIG_ACPI */
1411
f130bb75
MG		 1412void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1413{
1414 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1415 int ret;
1416 u32 resp;
1417
1418 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1419 .flags = cpu_to_le32(flags),
1420 .buf_size = 0,
1421 };
1422 struct iwl_host_cmd host_cmd = {
1423 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1424 .flags = CMD_WANT_SKB,
1425 .data = {&recovery_cmd, },
1426 .len = {sizeof(recovery_cmd), },
1427 };
1428
1429 /* no error log was defined in TLV */
1430 if (!error_log_size)
1431 return;
1432
1433 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1434 /* no buf was allocated while HW reset */
1435 if (!mvm->error_recovery_buf)
1436 return;
1437
1438 host_cmd.data[1] = mvm->error_recovery_buf;
1439 host_cmd.len[1] = error_log_size;
1440 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1441 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1442 }
1443
1444 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1445 kfree(mvm->error_recovery_buf);
1446 mvm->error_recovery_buf = NULL;
1447
1448 if (ret) {
1449 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1450 return;
1451 }
1452
1453 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1454 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1455 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1456 if (resp)
1457 IWL_ERR(mvm,
1458 "Failed to send recovery cmd blob was invalid %d\n",
1459 resp);
1460 }
1461}
1462
42ce76d6
LC		 1463static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1464{
1edd56e6 1465 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC		 1466}
1467
1f370650 1468static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1469{
1f370650 1470 int ret;
8ca151b5 1471
7d6222e2 1472 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1473 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1474
3b25f1af 1475 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1476
f2082a53 1477 if (ret) {
8d193ca2 1478 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK		 1479
1480 if (iwlmvm_mod_params.init_dbg)
1481 return 0;
1f370650 1482 return ret;
8d193ca2 1483 }
8ca151b5 1484
203c83d3 1485 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG		 1486 iwl_trans_stop_device(mvm->trans);
1487 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1488 if (ret)
1f370650 1489 return ret;
8ca151b5 1490
94022562 1491 mvm->rfkill_safe_init_done = false;
8ca151b5 1492 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS		 1493 if (ret)
1494 return ret;
1495
94022562
EG		 1496 mvm->rfkill_safe_init_done = true;
1497
b108d8c7
SM		 1498 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1499 NULL);
da2eb669 1500
702e975d 1501 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS		 1502}
1503
1504int iwl_mvm_up(struct iwl_mvm *mvm)
1505{
1506 int ret, i;
1507 struct ieee80211_channel *chan;
1508 struct cfg80211_chan_def chandef;
dd36a507 1509 struct ieee80211_supported_band *sband = NULL;
733eb54f 1510 u32 sb_cfg;
1f370650
SS		 1511
1512 lockdep_assert_held(&mvm->mutex);
1513
1514 ret = iwl_trans_start_hw(mvm->trans);
1515 if (ret)
1516 return ret;
733eb54f
AS		 1517
1518 sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
b8133439
AS		 1519 mvm->pldr_sync = !(sb_cfg & SB_CFG_RESIDES_IN_OTP_MASK);
1520 if (mvm->pldr_sync && iwl_mei_pldr_req())
274d9aa9 1521 return -EBUSY;
1f370650
SS		 1522
1523 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB		 1524 if (ret) {
1525 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
b8133439 1526 if (ret != -ERFKILL && !mvm->pldr_sync)
72d3c7bb
JB		 1527 iwl_fw_dbg_error_collect(&mvm->fwrt,
1528 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB		 1529 goto error;
1530 }
1531
b8133439
AS		 1532 /* FW loaded successfully */
1533 mvm->pldr_sync = false;
1534
d0b813fc 1535 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1536
1f3b0ff8
LE		 1537 ret = iwl_mvm_sf_update(mvm, NULL, false);
1538 if (ret)
1539 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1540
a1af4c48 1541 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS		 1542 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1543 /* if we have a destination, assume EARLY START */
1544 if (mvm->fw->dbg.dest_tlv)
1545 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1546 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1547 }
6a951267 1548
a0544272 1549 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1550 if (ret)
1551 goto error;
1552
7d6222e2
JB		 1553 if (!iwl_mvm_has_unified_ucode(mvm)) {
1554 /* Send phy db control command and then phy db calibration */
1f370650
SS		 1555 ret = iwl_send_phy_db_data(mvm->phy_db);
1556 if (ret)
1557 goto error;
d2ccc5c1
MS		 1558 ret = iwl_send_phy_cfg_cmd(mvm);
1559 if (ret)
1560 goto error;
1f370650 1561 }
8ca151b5 1562
b3de3ef4
EG		 1563 ret = iwl_mvm_send_bt_init_conf(mvm);
1564 if (ret)
1565 goto error;
1566
cceb4507
SM		 1567 if (fw_has_capa(&mvm->fw->ucode_capa,
1568 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1569 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM		 1570 if (ret)
1571 goto error;
1572 }
1573
43413a97 1574 /* Init RSS configuration */
9cd243f2
MG		 1575 ret = iwl_configure_rxq(&mvm->fwrt);
1576 if (ret)
1577 goto error;
8edbfaa1
SS		 1578
1579 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS		 1580 ret = iwl_send_rss_cfg_cmd(mvm);
1581 if (ret) {
1582 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1583 ret);
1584 goto error;
1585 }
1586 }
1587
8ca151b5 1588 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1589 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1590 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB		 1591 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1592 }
8ca151b5 1593
d464550b
YB		 1594 for (i = 0; i < IWL_MVM_FW_MAX_LINK_ID + 1; i++)
1595 RCU_INIT_POINTER(mvm->link_id_to_link_conf[i], NULL);
1596
d6f6b0d8
GG		 1597 memset(&mvm->fw_link_ids_map, 0, sizeof(mvm->fw_link_ids_map));
1598
0ae98812 1599 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1600
b2b7875b
JB		 1601 /* reset quota debouncing buffer - 0xff will yield invalid data */
1602 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1603
79660869
IL		 1604 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1605 ret = iwl_mvm_send_dqa_cmd(mvm);
1606 if (ret)
1607 goto error;
1608 }
97d5be7e 1609
2c2c3647
NE		 1610 /*
1611 * Add auxiliary station for scanning.
1612 * Newer versions of this command implies that the fw uses
1613 * internal aux station for all aux activities that don't
1614 * requires a dedicated data queue.
1615 */
971cbe50 1616 if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
2c2c3647
NE		 1617 /*
1618 * In old version the aux station uses mac id like other
1619 * station and not lmac id
1620 */
1621 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1622 if (ret)
1623 goto error;
1624 }
8ca151b5 1625
53a9d61e 1626 /* Add all the PHY contexts */
dd36a507
TM		 1627 i = 0;
1628 while (!sband && i < NUM_NL80211_BANDS)
1629 sband = mvm->hw->wiphy->bands[i++];
1630
583d1833
DC		 1631 if (WARN_ON_ONCE(!sband)) {
1632 ret = -ENODEV;
dd36a507 1633 goto error;
583d1833 1634 }
dd36a507
TM		 1635
1636 chan = &sband->channels[0];
1637
53a9d61e
IP		 1638 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1639 for (i = 0; i < NUM_PHY_CTX; i++) {
1640 /*
1641 * The channel used here isn't relevant as it's
1642 * going to be overwritten in the other flows.
1643 * For now use the first channel we have.
1644 */
1645 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1646 &chandef, 1, 1);
1647 if (ret)
1648 goto error;
1649 }
8ca151b5 1650
c221daf2
CRI		 1651 if (iwl_mvm_is_tt_in_fw(mvm)) {
1652 /* in order to give the responsibility of ct-kill and
1653 * TX backoff to FW we need to send empty temperature reporting
1654 * cmd during init time
1655 */
1656 iwl_mvm_send_temp_report_ths_cmd(mvm);
1657 } else {
1658 /* Initialize tx backoffs to the minimal possible */
1659 iwl_mvm_tt_tx_backoff(mvm, 0);
1660 }
5c89e7bc 1661
242d9c8b 1662#ifdef CONFIG_THERMAL
5c89e7bc 1663 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI		 1664
1665 /*
1666 * In case there is no budget from BIOS / Platform NVM the default
1667 * budget should be 2000mW (cooling state 0).
1668 */
1669 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI		 1670 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1671 mvm->cooling_dev.cur_state);
75cfe338
LC		 1672 if (ret)
1673 goto error;
1674 }
c221daf2 1675#endif
0c0e2c71 1676
aa43ae12
AM		 1677 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1678 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1679
c1cb92fc 1680 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB		 1681 if (ret)
1682 goto error;
1683
f5b1cb2e 1684 iwl_mvm_lari_cfg(mvm);
35af15d1
AN		 1685 /*
1686 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1687 * anyway, so don't init MCC.
1688 */
1689 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1690 ret = iwl_mvm_init_mcc(mvm);
1691 if (ret)
1692 goto error;
1693 }
90d4f7db 1694
859d914c 1695 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1696 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1697 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS		 1698 ret = iwl_mvm_config_scan(mvm);
1699 if (ret)
1700 goto error;
1701 }
1702
cf85123a 1703 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) {
f130bb75 1704 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
cf85123a
AS		 1705 iwl_mvm_time_sync_config(mvm, mvm->time_sync.peer_addr,
1706 IWL_TIME_SYNC_PROTOCOL_TM |
1707 IWL_TIME_SYNC_PROTOCOL_FTM);
1708 }
f130bb75 1709
1595ecce
KP		 1710 if (!mvm->ptp_data.ptp_clock)
1711 iwl_mvm_ptp_init(mvm);
1712
48e775e6
HD		 1713 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1714 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1715
6ce1e5c0
GA		 1716 ret = iwl_mvm_ppag_init(mvm);
1717 if (ret)
1718 goto error;
1719
da2830ac 1720 ret = iwl_mvm_sar_init(mvm);
78a19d52 1721 if (ret == 0)
5d041c46 1722 ret = iwl_mvm_sar_geo_init(mvm);
5f06f6bf 1723 if (ret < 0)
a6bff3cb
HD		 1724 goto error;
1725
c593d2fa
AB		 1726 ret = iwl_mvm_sgom_init(mvm);
1727 if (ret)
1728 goto error;
1729
28dd7ccd 1730 iwl_mvm_tas_init(mvm);
7089ae63
JB		 1731 iwl_mvm_leds_sync(mvm);
1732
4e8fe214
GG		 1733 if (fw_has_capa(&mvm->fw->ucode_capa,
1734 IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) {
1735 if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE)
1736 iwl_rfi_send_config_cmd(mvm, NULL);
1737 }
1738
5aa7ce31
AS		 1739 iwl_mvm_mei_device_state(mvm, true);
1740
53a9d61e 1741 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB		 1742 return 0;
1743 error:
f4744258 1744 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1745 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1746 return ret;
1747}
1748
1749int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1750{
1751 int ret, i;
1752
1753 lockdep_assert_held(&mvm->mutex);
1754
1755 ret = iwl_trans_start_hw(mvm->trans);
1756 if (ret)
1757 return ret;
1758
1759 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1760 if (ret) {
1761 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1762 goto error;
1763 }
1764
a0544272 1765 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1766 if (ret)
1767 goto error;
1768
1769 /* Send phy db control command and then phy db calibration*/
1770 ret = iwl_send_phy_db_data(mvm->phy_db);
1771 if (ret)
1772 goto error;
1773
1774 ret = iwl_send_phy_cfg_cmd(mvm);
1775 if (ret)
1776 goto error;
1777
1778 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1779 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1780 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB		 1781 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1782 }
8ca151b5 1783
971cbe50 1784 if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
2c2c3647
NE		 1785 /*
1786 * Add auxiliary station for scanning.
1787 * Newer versions of this command implies that the fw uses
1788 * internal aux station for all aux activities that don't
1789 * requires a dedicated data queue.
1790 * In old version the aux station uses mac id like other
1791 * station and not lmac id
1792 */
1793 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1794 if (ret)
1795 goto error;
1796 }
8ca151b5
JB		 1797
1798 return 0;
1799 error:
fcb6b92a 1800 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1801 return ret;
1802}
1803
0416841d
JB		 1804void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1805 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI		 1806{
1807 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1808 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1809
0c8d0a47
GBA		 1810 IWL_DEBUG_INFO(mvm,
1811 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1812 le32_to_cpu(mfuart_notif->installed_ver),
1813 le32_to_cpu(mfuart_notif->external_ver),
1814 le32_to_cpu(mfuart_notif->status),
1815 le32_to_cpu(mfuart_notif->duration));
1816
19f63c53
GBA		 1817 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1818 IWL_DEBUG_INFO(mvm,
0c8d0a47 1819 "MFUART: image size: 0x%08x\n",
19f63c53 1820 le32_to_cpu(mfuart_notif->image_size));
30269c12 1821}
Linux 6.x block layer and io_uring tree(s)