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wifi: iwlwifi: mvm: fix the PHY context resolution for p2p device
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
1724fc78 3 * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
8e99ea8d
JB		 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
a2ac0f48 9#include <linux/dmi.h>
8ca151b5
JB		 10
11#include "iwl-trans.h"
12#include "iwl-op-mode.h"
d962f9b1 13#include "fw/img.h"
8ca151b5 14#include "iwl-debug.h"
8c23f95c 15#include "iwl-prph.h"
813df5ce 16#include "fw/acpi.h"
b3e4c0f3 17#include "fw/pnvm.h"
8ca151b5
JB		 18
19#include "mvm.h"
7174beb6 20#include "fw/dbg.h"
8ca151b5 21#include "iwl-phy-db.h"
9c4f7d51
ST		 22#include "iwl-modparams.h"
23#include "iwl-nvm-parse.h"
cf85123a 24#include "time-sync.h"
8ca151b5 25
b3e4c0f3
LC		 26#define MVM_UCODE_ALIVE_TIMEOUT (HZ)
27#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5 28
c3f40c3e
MK		 29#define IWL_TAS_US_MCC 0x5553
30#define IWL_TAS_CANADA_MCC 0x4341
31
8ca151b5
JB		 32struct iwl_mvm_alive_data {
33 bool valid;
34 u32 scd_base_addr;
35};
36
8ca151b5
JB		 37static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
38{
39 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
40 .valid = cpu_to_le32(valid_tx_ant),
41 };
42
33223542 43 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 44 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB		 45 sizeof(tx_ant_cmd), &tx_ant_cmd);
46}
47
43413a97
SS		 48static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
49{
50 int i;
51 struct iwl_rss_config_cmd cmd = {
52 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS		 53 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
54 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
55 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
56 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
58 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS		 59 };
60
f43495fd
SS		 61 if (mvm->trans->num_rx_queues == 1)
62 return 0;
63
854d773e 64 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 65 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS		 66 cmd.indirection_table[i] =
67 1 + (i % (mvm->trans->num_rx_queues - 1));
68 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS		 69
70 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
71}
72
97d5be7e
LK		 73static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
74{
75 struct iwl_dqa_enable_cmd dqa_cmd = {
76 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
77 };
f0c86427 78 u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD);
97d5be7e
LK		 79 int ret;
80
81 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
82 if (ret)
83 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
84 else
85 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
86
87 return ret;
88}
89
bdccdb85
GBA		 90void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
91 struct iwl_rx_cmd_buffer *rxb)
92{
93 struct iwl_rx_packet *pkt = rxb_addr(rxb);
94 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
95 __le32 *dump_data = mfu_dump_notif->data;
96 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
97 int i;
98
99 if (mfu_dump_notif->index_num == 0)
100 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
101 le32_to_cpu(mfu_dump_notif->assert_id));
102
103 for (i = 0; i < n_words; i++)
104 IWL_DEBUG_INFO(mvm,
105 "MFUART assert dump, dword %u: 0x%08x\n",
106 le16_to_cpu(mfu_dump_notif->index_num) *
107 n_words + i,
108 le32_to_cpu(dump_data[i]));
109}
110
8ca151b5
JB		 111static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
112 struct iwl_rx_packet *pkt, void *data)
113{
fd1c3318 114 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB		 115 struct iwl_mvm *mvm =
116 container_of(notif_wait, struct iwl_mvm, notif_wait);
117 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS		 118 struct iwl_umac_alive *umac;
119 struct iwl_lmac_alive *lmac1;
120 struct iwl_lmac_alive *lmac2 = NULL;
121 u16 status;
cfa5d0ca 122 u32 lmac_error_event_table, umac_error_table;
708d8c53
JB		 123 u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
124 UCODE_ALIVE_NTFY, 0);
5053a451 125 u32 i;
b2f20cf2 126
01a9ca51 127
c0941ace
MS		 128 if (version == 6) {
129 struct iwl_alive_ntf_v6 *palive;
130
131 if (pkt_len < sizeof(*palive))
132 return false;
133
134 palive = (void *)pkt->data;
135 mvm->trans->dbg.imr_data.imr_enable =
136 le32_to_cpu(palive->imr.enabled);
137 mvm->trans->dbg.imr_data.imr_size =
138 le32_to_cpu(palive->imr.size);
139 mvm->trans->dbg.imr_data.imr2sram_remainbyte =
140 mvm->trans->dbg.imr_data.imr_size;
141 mvm->trans->dbg.imr_data.imr_base_addr =
142 palive->imr.base_addr;
143 mvm->trans->dbg.imr_data.imr_curr_addr =
144 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr);
145 IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n",
146 mvm->trans->dbg.imr_data.imr_enable,
147 mvm->trans->dbg.imr_data.imr_size,
148 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr));
5053a451
MS		 149
150 if (!mvm->trans->dbg.imr_data.imr_enable) {
151 for (i = 0; i < ARRAY_SIZE(mvm->trans->dbg.active_regions); i++) {
152 struct iwl_ucode_tlv *reg_tlv;
153 struct iwl_fw_ini_region_tlv *reg;
154
155 reg_tlv = mvm->trans->dbg.active_regions[i];
156 if (!reg_tlv)
157 continue;
158
159 reg = (void *)reg_tlv->data;
160 /*
161 * We have only one DRAM IMR region, so we
162 * can break as soon as we find the first
163 * one.
164 */
165 if (reg->type == IWL_FW_INI_REGION_DRAM_IMR) {
166 mvm->trans->dbg.unsupported_region_msk |= BIT(i);
167 break;
168 }
169 }
170 }
c0941ace
MS		 171 }
172
173 if (version >= 5) {
90824f2f
LC		 174 struct iwl_alive_ntf_v5 *palive;
175
fd1c3318
JB		 176 if (pkt_len < sizeof(*palive))
177 return false;
178
90824f2f
LC		 179 palive = (void *)pkt->data;
180 umac = &palive->umac_data;
181 lmac1 = &palive->lmac_data[0];
182 lmac2 = &palive->lmac_data[1];
183 status = le16_to_cpu(palive->status);
184
185 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
186 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
187 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
188
189 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
190 mvm->trans->sku_id[0],
191 mvm->trans->sku_id[1],
192 mvm->trans->sku_id[2]);
193 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC		 194 struct iwl_alive_ntf_v4 *palive;
195
fd1c3318
JB		 196 if (pkt_len < sizeof(*palive))
197 return false;
198
5c228d63
SS		 199 palive = (void *)pkt->data;
200 umac = &palive->umac_data;
201 lmac1 = &palive->lmac_data[0];
202 lmac2 = &palive->lmac_data[1];
203 status = le16_to_cpu(palive->status);
9422b978
LC		 204 } else if (iwl_rx_packet_payload_len(pkt) ==
205 sizeof(struct iwl_alive_ntf_v3)) {
206 struct iwl_alive_ntf_v3 *palive3;
207
fd1c3318
JB		 208 if (pkt_len < sizeof(*palive3))
209 return false;
210
5c228d63
SS		 211 palive3 = (void *)pkt->data;
212 umac = &palive3->umac_data;
213 lmac1 = &palive3->lmac_data;
214 status = le16_to_cpu(palive3->status);
9422b978
LC		 215 } else {
216 WARN(1, "unsupported alive notification (size %d)\n",
217 iwl_rx_packet_payload_len(pkt));
218 /* get timeout later */
219 return false;
5c228d63 220 }
01a9ca51 221
22463857
SM		 222 lmac_error_event_table =
223 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
224 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
225
5c228d63 226 if (lmac2)
91c28b83 227 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 228 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 229
4f7411d6
RG		 230 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
231 ~FW_ADDR_CACHE_CONTROL;
cfa5d0ca
MG		 232
233 if (umac_error_table) {
234 if (umac_error_table >=
834f920e 235 mvm->trans->cfg->min_umac_error_event_table) {
cfa5d0ca
MG		 236 iwl_fw_umac_set_alive_err_table(mvm->trans,
237 umac_error_table);
238 } else {
239 IWL_ERR(mvm,
240 "Not valid error log pointer 0x%08X for %s uCode\n",
241 umac_error_table,
242 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
243 "Init" : "RT");
244 }
3485e76e 245 }
fb5b2846 246
22463857 247 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 248 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 249
5c228d63
SS		 250 IWL_DEBUG_FW(mvm,
251 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
252 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 253
5c228d63
SS		 254 if (lmac2)
255 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 256
5c228d63
SS		 257 IWL_DEBUG_FW(mvm,
258 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
259 le32_to_cpu(umac->umac_major),
260 le32_to_cpu(umac->umac_minor));
8ca151b5 261
0a3a3e9e
SM		 262 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
263
8ca151b5
JB		 264 return true;
265}
266
1f370650
SS		 267static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
268 struct iwl_rx_packet *pkt, void *data)
269{
270 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
271
272 return true;
273}
274
8ca151b5
JB		 275static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
276 struct iwl_rx_packet *pkt, void *data)
277{
278 struct iwl_phy_db *phy_db = data;
279
280 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
281 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
282 return true;
283 }
284
ce1f2778 285 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB		 286
287 return false;
288}
289
a7de31d5
MG		 290static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
291{
184f10db
MG		 292#define IWL_FW_PRINT_REG_INFO(reg_name) \
293 IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
294
a7de31d5
MG		 295 struct iwl_trans *trans = mvm->trans;
296 enum iwl_device_family device_family = trans->trans_cfg->device_family;
297
298 if (device_family < IWL_DEVICE_FAMILY_8000)
299 return;
300
301 if (device_family <= IWL_DEVICE_FAMILY_9000)
184f10db 302 IWL_FW_PRINT_REG_INFO(WFPM_ARC1_PD_NOTIFICATION);
a7de31d5 303 else
184f10db 304 IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);
f2f17ca0 305
184f10db 306 IWL_FW_PRINT_REG_INFO(HPM_SECONDARY_DEVICE_STATE);
f2f17ca0 307
184f10db
MG		 308 /* print OPT info */
309 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_ADDR);
310 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_DATA);
a7de31d5
MG		 311}
312
8ca151b5
JB		 313static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
314 enum iwl_ucode_type ucode_type)
315{
316 struct iwl_notification_wait alive_wait;
94a8d87c 317 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 318 const struct fw_img *fw;
cfbc6c4c 319 int ret;
702e975d 320 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 321 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG		 322 bool run_in_rfkill =
323 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
5e31b3df
MS		 324 u8 count;
325 struct iwl_pc_data *pc_data;
8ca151b5 326
61df750c 327 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA		 328 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
329 !(fw_has_capa(&mvm->fw->ucode_capa,
330 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 331 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 332 else
612da1ef 333 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 334 if (WARN_ON(!fw))
8ca151b5 335 return -EINVAL;
702e975d 336 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 337 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB		 338
339 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
340 alive_cmd, ARRAY_SIZE(alive_cmd),
341 iwl_alive_fn, &alive_data);
342
b3500b47
EG		 343 /*
344 * We want to load the INIT firmware even in RFKILL
345 * For the unified firmware case, the ucode_type is not
346 * INIT, but we still need to run it.
347 */
348 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 349 if (ret) {
702e975d 350 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 351 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
352 return ret;
353 }
354
355 /*
356 * Some things may run in the background now, but we
357 * just wait for the ALIVE notification here.
358 */
359 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
360 MVM_UCODE_ALIVE_TIMEOUT);
56731878
DG		 361
362 if (mvm->trans->trans_cfg->device_family ==
363 IWL_DEVICE_FAMILY_AX210) {
364 /* print these registers regardless of alive fail/success */
365 IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n",
366 iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
367 IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n",
368 iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
369 IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n",
370 iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
b8133439
AS		 371 IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n",
372 iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
56731878
DG		 373 }
374
8ca151b5 375 if (ret) {
d6be9c1d
SS		 376 struct iwl_trans *trans = mvm->trans;
377
5667ccc2 378 /* SecBoot info */
20f5aef5
JB		 379 if (trans->trans_cfg->device_family >=
380 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS		 381 IWL_ERR(mvm,
382 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST		 383 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
384 iwl_read_umac_prph(trans,
385 UMAG_SB_CPU_2_STATUS));
5667ccc2
MG		 386 } else if (trans->trans_cfg->device_family >=
387 IWL_DEVICE_FAMILY_8000) {
388 IWL_ERR(mvm,
389 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
390 iwl_read_prph(trans, SB_CPU_1_STATUS),
391 iwl_read_prph(trans, SB_CPU_2_STATUS));
392 }
393
a7de31d5
MG		 394 iwl_mvm_print_pd_notification(mvm);
395
5667ccc2
MG		 396 /* LMAC/UMAC PC info */
397 if (trans->trans_cfg->device_family >=
5e31b3df
MS		 398 IWL_DEVICE_FAMILY_22000) {
399 pc_data = trans->dbg.pc_data;
400 for (count = 0; count < trans->dbg.num_pc;
401 count++, pc_data++)
402 IWL_ERR(mvm, "%s: 0x%x\n",
403 pc_data->pc_name,
404 pc_data->pc_address);
405 } else if (trans->trans_cfg->device_family >=
5667ccc2 406 IWL_DEVICE_FAMILY_9000) {
20f5aef5
JB		 407 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
408 iwl_read_umac_prph(trans,
409 UREG_UMAC_CURRENT_PC));
410 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
411 iwl_read_umac_prph(trans,
412 UREG_LMAC1_CURRENT_PC));
413 if (iwl_mvm_is_cdb_supported(mvm))
414 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
415 iwl_read_umac_prph(trans,
416 UREG_LMAC2_CURRENT_PC));
20f5aef5
JB		 417 }
418
b8133439 419 if (ret == -ETIMEDOUT && !mvm->pldr_sync)
20f5aef5
JB		 420 iwl_fw_dbg_error_collect(&mvm->fwrt,
421 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
422
702e975d 423 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 424 return ret;
425 }
426
427 if (!alive_data.valid) {
428 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 429 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB		 430 return -EIO;
431 }
432
f31f7cd9
GG		 433 /* if reached this point, Alive notification was received */
434 iwl_mei_alive_notif(true);
733eb54f 435
33182810
AG		 436 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait,
437 &mvm->fw->ucode_capa);
70d3ca86
LC		 438 if (ret) {
439 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
440 iwl_fw_set_current_image(&mvm->fwrt, old_type);
441 return ret;
442 }
443
8ca151b5
JB		 444 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
445
446 /*
447 * Note: all the queues are enabled as part of the interface
448 * initialization, but in firmware restart scenarios they
449 * could be stopped, so wake them up. In firmware restart,
450 * mac80211 will have the queues stopped as well until the
451 * reconfiguration completes. During normal startup, they
452 * will be empty.
453 */
454
4ecafae9 455 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB		 456 /*
457 * Set a 'fake' TID for the command queue, since we use the
458 * hweight() of the tid_bitmap as a refcount now. Not that
459 * we ever even consider the command queue as one we might
460 * want to reuse, but be safe nevertheless.
461 */
462 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
463 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 464
65b280fe 465 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC		 466#ifdef CONFIG_IWLWIFI_DEBUGFS
467 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
468#endif
8ca151b5 469
d3d9b4fc
EG		 470 /*
471 * All the BSSes in the BSS table include the GP2 in the system
472 * at the beacon Rx time, this is of course no longer relevant
473 * since we are resetting the firmware.
474 * Purge all the BSS table.
475 */
476 cfg80211_bss_flush(mvm->hw->wiphy);
477
8ca151b5
JB		 478 return 0;
479}
8ca151b5 480
c4ace426
GA		 481static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
482 struct iwl_phy_specific_cfg *phy_filters)
483{
c4c95454
JB		 484#ifdef CONFIG_ACPI
485 *phy_filters = mvm->phy_filters;
c4ace426 486#endif /* CONFIG_ACPI */
c4c95454 487}
c4ace426 488
c593d2fa
AB		 489#if defined(CONFIG_ACPI) && defined(CONFIG_EFI)
490static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
491{
492 u8 cmd_ver;
493 int ret;
494 struct iwl_host_cmd cmd = {
495 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
496 SAR_OFFSET_MAPPING_TABLE_CMD),
497 .flags = 0,
498 .data[0] = &mvm->fwrt.sgom_table,
499 .len[0] = sizeof(mvm->fwrt.sgom_table),
500 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
501 };
502
503 if (!mvm->fwrt.sgom_enabled) {
504 IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n");
505 return 0;
506 }
507
971cbe50 508 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
c593d2fa
AB		 509 IWL_FW_CMD_VER_UNKNOWN);
510
511 if (cmd_ver != 2) {
512 IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n",
513 cmd_ver);
514 return 0;
515 }
516
517 ret = iwl_mvm_send_cmd(mvm, &cmd);
518 if (ret < 0)
519 IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret);
520
521 return ret;
522}
523#else
524
525static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
526{
527 return 0;
528}
529#endif
530
8ca151b5
JB		 531static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
532{
971cbe50 533 u32 cmd_id = PHY_CONFIGURATION_CMD;
c4ace426 534 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 535 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA		 536 u8 cmd_ver;
537 size_t cmd_size;
8ca151b5 538
bb99ff9b 539 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 540 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 541 return 0;
d923b020
LC		 542
543 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC		 544 /*
545 * TODO: currently we don't set the antenna but letting the NIC
546 * to decide which antenna to use. This should come from BIOS.
547 */
548 phy_cfg_cmd.phy_cfg =
549 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
550 }
551
8ca151b5 552 /* Set parameters */
a0544272 553 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC		 554
555 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC		 556 phy_cfg_cmd.phy_cfg |=
557 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 558
8ca151b5
JB		 559 phy_cfg_cmd.calib_control.event_trigger =
560 mvm->fw->default_calib[ucode_type].event_trigger;
561 phy_cfg_cmd.calib_control.flow_trigger =
562 mvm->fw->default_calib[ucode_type].flow_trigger;
563
971cbe50 564 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 565 IWL_FW_CMD_VER_UNKNOWN);
c4c95454
JB		 566 if (cmd_ver >= 3)
567 iwl_mvm_phy_filter_init(mvm, &phy_cfg_cmd.phy_specific_cfg);
c4ace426 568
8ca151b5
JB		 569 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
570 phy_cfg_cmd.phy_cfg);
c4ace426
GA		 571 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
572 sizeof(struct iwl_phy_cfg_cmd_v1);
971cbe50 573 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd);
8ca151b5
JB		 574}
575
e305a408
MS		 576static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
577{
578 struct iwl_notification_wait init_wait;
579 struct iwl_nvm_access_complete_cmd nvm_complete = {};
580 struct iwl_init_extended_cfg_cmd init_cfg = {
581 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
582 };
583 static const u16 init_complete[] = {
584 INIT_COMPLETE_NOTIF,
585 };
bdd94061 586 u32 sb_cfg;
e305a408
MS		 587 int ret;
588
589 if (mvm->trans->cfg->tx_with_siso_diversity)
590 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
591
592 lockdep_assert_held(&mvm->mutex);
593
594 mvm->rfkill_safe_init_done = false;
595
a856ce66
JB		 596 if (mvm->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
597 sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
598 /* if needed, we'll reset this on our way out later */
3277baa9 599 mvm->pldr_sync = sb_cfg == SB_CFG_RESIDES_IN_ROM;
a856ce66
JB		 600 if (mvm->pldr_sync && iwl_mei_pldr_req())
601 return -EBUSY;
602 }
bdd94061 603
e305a408
MS		 604 iwl_init_notification_wait(&mvm->notif_wait,
605 &init_wait,
606 init_complete,
607 ARRAY_SIZE(init_complete),
608 iwl_wait_init_complete,
609 NULL);
610
611 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
612
613 /* Will also start the device */
614 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
615 if (ret) {
616 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
bdd94061
JB		 617
618 /* if we needed reset then fail here, but notify and remove */
619 if (mvm->pldr_sync) {
620 iwl_mei_alive_notif(false);
621 iwl_trans_pcie_remove(mvm->trans, true);
622 }
623
e305a408
MS		 624 goto error;
625 }
626 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
627 NULL);
628
629 /* Send init config command to mark that we are sending NVM access
630 * commands
631 */
632 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
633 INIT_EXTENDED_CFG_CMD),
634 CMD_SEND_IN_RFKILL,
635 sizeof(init_cfg), &init_cfg);
636 if (ret) {
637 IWL_ERR(mvm, "Failed to run init config command: %d\n",
638 ret);
639 goto error;
640 }
641
642 /* Load NVM to NIC if needed */
643 if (mvm->nvm_file_name) {
644 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
645 mvm->nvm_sections);
646 if (ret)
647 goto error;
648 ret = iwl_mvm_load_nvm_to_nic(mvm);
649 if (ret)
650 goto error;
651 }
652
653 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
654 ret = iwl_nvm_init(mvm);
655 if (ret) {
656 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
657 goto error;
658 }
659 }
660
661 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
662 NVM_ACCESS_COMPLETE),
663 CMD_SEND_IN_RFKILL,
664 sizeof(nvm_complete), &nvm_complete);
665 if (ret) {
666 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
667 ret);
668 goto error;
669 }
670
d2ccc5c1
MS		 671 ret = iwl_send_phy_cfg_cmd(mvm);
672 if (ret) {
673 IWL_ERR(mvm, "Failed to run PHY configuration: %d\n",
674 ret);
675 goto error;
676 }
677
e305a408
MS		 678 /* We wait for the INIT complete notification */
679 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
680 MVM_UCODE_ALIVE_TIMEOUT);
681 if (ret)
682 return ret;
683
684 /* Read the NVM only at driver load time, no need to do this twice */
685 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
4ea1ed1d
EG		 686 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw,
687 mvm->set_tx_ant, mvm->set_rx_ant);
e305a408
MS		 688 if (IS_ERR(mvm->nvm_data)) {
689 ret = PTR_ERR(mvm->nvm_data);
690 mvm->nvm_data = NULL;
691 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
692 return ret;
693 }
694 }
695
696 mvm->rfkill_safe_init_done = true;
697
698 return 0;
699
700error:
701 iwl_remove_notification(&mvm->notif_wait, &init_wait);
702 return ret;
703}
704
3b25f1af 705int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB		 706{
707 struct iwl_notification_wait calib_wait;
6eb031d2 708 static const u16 init_complete[] = {
8ca151b5
JB		 709 INIT_COMPLETE_NOTIF,
710 CALIB_RES_NOTIF_PHY_DB
711 };
712 int ret;
713
7d6222e2 714 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 715 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 716
8ca151b5
JB		 717 lockdep_assert_held(&mvm->mutex);
718
94022562 719 mvm->rfkill_safe_init_done = false;
8ca151b5
JB		 720
721 iwl_init_notification_wait(&mvm->notif_wait,
722 &calib_wait,
723 init_complete,
724 ARRAY_SIZE(init_complete),
725 iwl_wait_phy_db_entry,
726 mvm->phy_db);
727
11f8c533
LC		 728 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
729
8ca151b5
JB		 730 /* Will also start the device */
731 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
732 if (ret) {
733 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 734 goto remove_notif;
8ca151b5
JB		 735 }
736
7d34a7d7 737 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG		 738 ret = iwl_mvm_send_bt_init_conf(mvm);
739 if (ret)
00e0c6c8 740 goto remove_notif;
b3de3ef4 741 }
931d4160 742
81a67e32 743 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 744 if (!mvm->nvm_data) {
5bd1d2c1 745 ret = iwl_nvm_init(mvm);
8ca151b5
JB		 746 if (ret) {
747 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 748 goto remove_notif;
8ca151b5
JB		 749 }
750 }
751
81a67e32 752 /* In case we read the NVM from external file, load it to the NIC */
9ce505fe
AN		 753 if (mvm->nvm_file_name) {
754 ret = iwl_mvm_load_nvm_to_nic(mvm);
755 if (ret)
756 goto remove_notif;
757 }
81a67e32 758
64866e5d
LC		 759 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
760 "Too old NVM version (0x%0x, required = 0x%0x)",
761 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 762
4f59334b
EH		 763 /*
764 * abort after reading the nvm in case RF Kill is on, we will complete
765 * the init seq later when RF kill will switch to off
766 */
1a3fe0b2 767 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH		 768 IWL_DEBUG_RF_KILL(mvm,
769 "jump over all phy activities due to RF kill\n");
00e0c6c8 770 goto remove_notif;
4f59334b
EH		 771 }
772
b3500b47 773 mvm->rfkill_safe_init_done = true;
31b8b343 774
e07cbb53 775 /* Send TX valid antennas before triggering calibrations */
a0544272 776 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 777 if (ret)
00e0c6c8 778 goto remove_notif;
e07cbb53 779
8ca151b5
JB		 780 ret = iwl_send_phy_cfg_cmd(mvm);
781 if (ret) {
782 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
783 ret);
00e0c6c8 784 goto remove_notif;
8ca151b5
JB		 785 }
786
787 /*
788 * Some things may run in the background now, but we
789 * just wait for the calibration complete notification.
790 */
791 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC		 792 MVM_UCODE_CALIB_TIMEOUT);
793 if (!ret)
794 goto out;
31b8b343 795
00e0c6c8 796 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 797 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC		 798 ret = 0;
799 } else {
800 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
801 ret);
31b8b343 802 }
00e0c6c8 803
8ca151b5
JB		 804 goto out;
805
00e0c6c8 806remove_notif:
8ca151b5
JB		 807 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
808out:
b3500b47 809 mvm->rfkill_safe_init_done = false;
a4082843 810 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB		 811 /* we want to debug INIT and we have no NVM - fake */
812 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
813 sizeof(struct ieee80211_channel) +
814 sizeof(struct ieee80211_rate),
815 GFP_KERNEL);
816 if (!mvm->nvm_data)
817 return -ENOMEM;
8ca151b5
JB		 818 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
819 mvm->nvm_data->bands[0].n_channels = 1;
820 mvm->nvm_data->bands[0].n_bitrates = 1;
821 mvm->nvm_data->bands[0].bitrates =
8ba438ef 822 (void *)(mvm->nvm_data->channels + 1);
8ca151b5
JB		 823 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
824 }
825
826 return ret;
827}
828
84bfffa9
EG		 829static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
830{
831 struct iwl_ltr_config_cmd cmd = {
832 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
833 };
834
835 if (!mvm->trans->ltr_enabled)
836 return 0;
837
84bfffa9
EG		 838 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
839 sizeof(cmd), &cmd);
840}
841
c386dacb 842#ifdef CONFIG_ACPI
42ce76d6 843int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 844{
971cbe50 845 u32 cmd_id = REDUCE_TX_POWER_CMD;
216cdfb5
LC		 846 struct iwl_dev_tx_power_cmd cmd = {
847 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 848 };
9c08cef8 849 __le16 *per_chain;
1edd56e6 850 int ret;
39c1a972 851 u16 len = 0;
fbb7957d 852 u32 n_subbands;
971cbe50 853 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 854 IWL_FW_CMD_VER_UNKNOWN);
b0aa02b3
AB		 855 if (cmd_ver == 7) {
856 len = sizeof(cmd.v7);
857 n_subbands = IWL_NUM_SUB_BANDS_V2;
858 per_chain = cmd.v7.per_chain[0][0];
859 cmd.v7.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags);
860 } else if (cmd_ver == 6) {
fbb7957d
LC		 861 len = sizeof(cmd.v6);
862 n_subbands = IWL_NUM_SUB_BANDS_V2;
863 per_chain = cmd.v6.per_chain[0][0];
864 } else if (fw_has_api(&mvm->fw->ucode_capa,
865 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 866 len = sizeof(cmd.v5);
e12cfc7b 867 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 868 per_chain = cmd.v5.per_chain[0][0];
869 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 870 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 871 len = sizeof(cmd.v4);
e12cfc7b 872 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 873 per_chain = cmd.v4.per_chain[0][0];
874 } else {
216cdfb5 875 len = sizeof(cmd.v3);
e12cfc7b 876 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC		 877 per_chain = cmd.v3.per_chain[0][0];
878 }
55bfa4b9 879
216cdfb5
LC		 880 /* all structs have the same common part, add it */
881 len += sizeof(cmd.common);
da2830ac 882
dac7171c
LC		 883 ret = iwl_sar_select_profile(&mvm->fwrt, per_chain,
884 IWL_NUM_CHAIN_TABLES,
fbb7957d 885 n_subbands, prof_a, prof_b);
1edd56e6
LC		 886
887 /* return on error or if the profile is disabled (positive number) */
888 if (ret)
889 return ret;
890
6d19a5eb
EG		 891 iwl_mei_set_power_limit(per_chain);
892
42ce76d6 893 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
971cbe50 894 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
42ce76d6
LC		 895}
896
7fe90e0e
HD		 897int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
898{
dd2a1256 899 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 900 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 901 u16 len;
39c1a972 902 int ret;
c8611331
JB		 903 struct iwl_host_cmd cmd = {
904 .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD),
905 .flags = CMD_WANT_SKB,
906 .data = { &geo_tx_cmd },
907 };
971cbe50 908 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
e80bfd11 909 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 910
dd2a1256
LC		 911 /* the ops field is at the same spot for all versions, so set in v1 */
912 geo_tx_cmd.v1.ops =
913 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
914
97f8a3d1
AB		 915 if (cmd_ver == 5)
916 len = sizeof(geo_tx_cmd.v5);
917 else if (cmd_ver == 4)
918 len = sizeof(geo_tx_cmd.v4);
919 else if (cmd_ver == 3)
0ea788ed
LC		 920 len = sizeof(geo_tx_cmd.v3);
921 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
922 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC		 923 len = sizeof(geo_tx_cmd.v2);
924 else
925 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 926
39c1a972
IZ		 927 if (!iwl_sar_geo_support(&mvm->fwrt))
928 return -EOPNOTSUPP;
929
c8611331 930 cmd.len[0] = len;
7fe90e0e
HD		 931
932 ret = iwl_mvm_send_cmd(mvm, &cmd);
933 if (ret) {
934 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
935 return ret;
936 }
f604324e
LC		 937
938 resp = (void *)cmd.resp_pkt->data;
939 ret = le32_to_cpu(resp->profile_idx);
940
97f8a3d1 941 if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES_REV3))
f604324e
LC		 942 ret = -EIO;
943
7fe90e0e
HD		 944 iwl_free_resp(&cmd);
945 return ret;
946}
947
a6bff3cb
HD		 948static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
949{
971cbe50 950 u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD);
dd2a1256 951 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 952 u16 len;
45acebf8 953 u32 n_bands;
97f8a3d1 954 u32 n_profiles;
ac9952f6 955 u32 sk = 0;
0433ae55 956 int ret;
971cbe50 957 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 958 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 959
45acebf8
NG		 960 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
961 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
962 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
97f8a3d1
AB		 963 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) ||
964 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) !=
965 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) ||
966 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) !=
967 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops));
968
dd2a1256
LC		 969 /* the ops field is at the same spot for all versions, so set in v1 */
970 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 971
97f8a3d1
AB		 972 if (cmd_ver == 5) {
973 len = sizeof(cmd.v5);
974 n_bands = ARRAY_SIZE(cmd.v5.table[0]);
975 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
976 } else if (cmd_ver == 4) {
977 len = sizeof(cmd.v4);
978 n_bands = ARRAY_SIZE(cmd.v4.table[0]);
979 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
980 } else if (cmd_ver == 3) {
0ea788ed 981 len = sizeof(cmd.v3);
45acebf8 982 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
97f8a3d1 983 n_profiles = ACPI_NUM_GEO_PROFILES;
0ea788ed
LC		 984 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
985 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 986 len = sizeof(cmd.v2);
45acebf8 987 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
97f8a3d1 988 n_profiles = ACPI_NUM_GEO_PROFILES;
39c1a972 989 } else {
dd2a1256 990 len = sizeof(cmd.v1);
45acebf8 991 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
97f8a3d1 992 n_profiles = ACPI_NUM_GEO_PROFILES;
0c3d7282
HD		 993 }
994
45acebf8
NG		 995 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
996 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
997 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
97f8a3d1
AB		 998 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) ||
999 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) !=
1000 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) ||
1001 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) !=
1002 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table));
45acebf8 1003 /* the table is at the same position for all versions, so set use v1 */
97f8a3d1
AB		 1004 ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0],
1005 n_bands, n_profiles);
45acebf8
NG		 1006
1007 /*
1008 * It is a valid scenario to not support SAR, or miss wgds table,
1009 * but in that case there is no need to send the command.
1010 */
1011 if (ret)
1012 return 0;
1013
ac9952f6
LC		 1014 /* Only set to South Korea if the table revision is 1 */
1015 if (mvm->fwrt.geo_rev == 1)
1016 sk = 1;
1017
28db1862 1018 /*
ac9952f6
LC		 1019 * Set the table_revision to South Korea (1) or not (0). The
1020 * element name is misleading, as it doesn't contain the table
1021 * revision number, but whether the South Korea variation
1022 * should be used.
28db1862
LC		 1023 * This must be done after calling iwl_sar_geo_init().
1024 */
97f8a3d1 1025 if (cmd_ver == 5)
ac9952f6 1026 cmd.v5.table_revision = cpu_to_le32(sk);
97f8a3d1 1027 else if (cmd_ver == 4)
ac9952f6 1028 cmd.v4.table_revision = cpu_to_le32(sk);
97f8a3d1 1029 else if (cmd_ver == 3)
ac9952f6 1030 cmd.v3.table_revision = cpu_to_le32(sk);
28db1862
LC		 1031 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
1032 IWL_UCODE_TLV_API_SAR_TABLE_VER))
ac9952f6 1033 cmd.v2.table_revision = cpu_to_le32(sk);
28db1862 1034
971cbe50 1035 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
6ce1e5c0
GA		 1036}
1037
1038int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1039{
8bdc52b9 1040 union iwl_ppag_table_cmd cmd;
e8e10a37 1041 int ret, cmd_size;
160bab43 1042
e8e10a37 1043 ret = iwl_read_ppag_table(&mvm->fwrt, &cmd, &cmd_size);
b20bdd9c 1044 /* Not supporting PPAG table is a valid scenario */
473bc264 1045 if (ret < 0)
b20bdd9c 1046 return 0;
6ce1e5c0 1047
f2134f66 1048 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA		 1049 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1050 PER_PLATFORM_ANT_GAIN_CMD),
8bdc52b9 1051 0, cmd_size, &cmd);
6ce1e5c0
GA		 1052 if (ret < 0)
1053 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1054 ret);
1055
1056 return ret;
1057}
1058
1059static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1060{
78a19d52 1061 /* no need to read the table, done in INIT stage */
e8e10a37 1062 if (!(iwl_acpi_is_ppag_approved(&mvm->fwrt)))
a2ac0f48 1063 return 0;
a2ac0f48 1064
6ce1e5c0
GA		 1065 return iwl_mvm_ppag_send_cmd(mvm);
1066}
1067
2856f623
AB		 1068static const struct dmi_system_id dmi_tas_approved_list[] = {
1069 { .ident = "HP",
1070 .matches = {
1071 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1072 },
1073 },
1074 { .ident = "SAMSUNG",
1075 .matches = {
1076 DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
1077 },
1078 },
1079 { .ident = "LENOVO",
1080 .matches = {
d0246a0e 1081 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2856f623
AB		 1082 },
1083 },
1084 { .ident = "DELL",
1085 .matches = {
1086 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1087 },
1088 },
3ecf3411
AG		 1089 { .ident = "MSFT",
1090 .matches = {
1091 DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
1092 },
1093 },
06471b67
AG		 1094 { .ident = "Acer",
1095 .matches = {
1096 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1097 },
1098 },
1099 { .ident = "ASUS",
1100 .matches = {
1101 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1102 },
1103 },
8bbe27db
MC		 1104 { .ident = "GOOGLE-HP",
1105 .matches = {
1106 DMI_MATCH(DMI_SYS_VENDOR, "Google"),
1107 DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
1108 },
1109 },
06471b67
AG		 1110 { .ident = "MSI",
1111 .matches = {
1112 DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International Co., Ltd."),
1113 },
1114 },
1115 { .ident = "Honor",
1116 .matches = {
1117 DMI_MATCH(DMI_SYS_VENDOR, "HONOR"),
1118 },
1119 },
2856f623
AB		 1120 /* keep last */
1121 {}
1122};
1123
9457077d
AN		 1124bool iwl_mvm_is_vendor_in_approved_list(void)
1125{
1126 return dmi_check_system(dmi_tas_approved_list);
1127}
1128
c3f40c3e
MK		 1129static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc)
1130{
1131 int i;
1132 u32 size = le32_to_cpu(*le_size);
1133
1134 /* Verify that there is room for another country */
1135 if (size >= IWL_TAS_BLOCK_LIST_MAX)
1136 return false;
1137
1138 for (i = 0; i < size; i++) {
1139 if (list[i] == cpu_to_le32(mcc))
1140 return true;
1141 }
1142
1143 list[size++] = cpu_to_le32(mcc);
1144 *le_size = cpu_to_le32(size);
1145 return true;
1146}
1147
28dd7ccd
MG		 1148static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1149{
971cbe50 1150 u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG);
28dd7ccd 1151 int ret;
6da7ba3a
AB		 1152 union iwl_tas_config_cmd cmd = {};
1153 int cmd_size, fw_ver;
28dd7ccd 1154
6da7ba3a 1155 BUILD_BUG_ON(ARRAY_SIZE(cmd.v3.block_list_array) <
28dd7ccd
MG		 1156 APCI_WTAS_BLACK_LIST_MAX);
1157
1158 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1159 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1160 return;
1161 }
1162
971cbe50
JB		 1163 fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
1164 IWL_FW_CMD_VER_UNKNOWN);
6da7ba3a
AB		 1165
1166 ret = iwl_acpi_get_tas(&mvm->fwrt, &cmd, fw_ver);
28dd7ccd
MG		 1167 if (ret < 0) {
1168 IWL_DEBUG_RADIO(mvm,
1169 "TAS table invalid or unavailable. (%d)\n",
1170 ret);
1171 return;
1172 }
1173
7c530588 1174 if (ret == 0)
28dd7ccd
MG		 1175 return;
1176
c4fbf653 1177 if (!iwl_mvm_is_vendor_in_approved_list()) {
c3f40c3e
MK		 1178 IWL_DEBUG_RADIO(mvm,
1179 "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
1180 dmi_get_system_info(DMI_SYS_VENDOR));
6da7ba3a
AB		 1181 if ((!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1182 &cmd.v4.block_list_size,
1183 IWL_TAS_US_MCC)) ||
1184 (!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1185 &cmd.v4.block_list_size,
1186 IWL_TAS_CANADA_MCC))) {
c3f40c3e
MK		 1187 IWL_DEBUG_RADIO(mvm,
1188 "Unable to add US/Canada to TAS block list, disabling TAS\n");
1189 return;
1190 }
06471b67
AG		 1191 } else {
1192 IWL_DEBUG_RADIO(mvm,
1193 "System vendor '%s' is in the approved list.\n",
1194 dmi_get_system_info(DMI_SYS_VENDOR));
c3f40c3e
MK		 1195 }
1196
6da7ba3a
AB		 1197 /* v4 is the same size as v3, so no need to differentiate here */
1198 cmd_size = fw_ver < 3 ?
7c530588
MK		 1199 sizeof(struct iwl_tas_config_cmd_v2) :
1200 sizeof(struct iwl_tas_config_cmd_v3);
28dd7ccd 1201
971cbe50 1202 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd);
28dd7ccd
MG		 1203 if (ret < 0)
1204 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1205}
f5b1cb2e 1206
4e8fe214
GG		 1207static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1208{
1209 u8 value;
45fe1b6b 1210 int ret = iwl_acpi_get_dsm_u8(mvm->fwrt.dev, 0, DSM_RFI_FUNC_ENABLE,
4e8fe214
GG		 1211 &iwl_rfi_guid, &value);
1212
1213 if (ret < 0) {
1214 IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
1215
1216 } else if (value >= DSM_VALUE_RFI_MAX) {
1217 IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n",
1218 value);
1219
1220 } else if (value == DSM_VALUE_RFI_ENABLE) {
1221 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
1222 return DSM_VALUE_RFI_ENABLE;
1223 }
1224
1225 IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n");
1226
1227 /* default behaviour is disabled */
1228 return DSM_VALUE_RFI_DISABLE;
1229}
1230
f5b1cb2e
GA		 1231static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1232{
7119f02b
MK		 1233 int ret;
1234 u32 value;
c8e01fe0 1235 struct iwl_lari_config_change_cmd_v7 cmd = {};
f5b1cb2e 1236
f21afaba 1237 cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt);
d2bfda8a 1238
45fe1b6b 1239 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_11AX_ENABLEMENT,
7119f02b
MK		 1240 &iwl_guid, &value);
1241 if (!ret)
1242 cmd.oem_11ax_allow_bitmap = cpu_to_le32(value);
f5b1cb2e 1243
45fe1b6b 1244 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
54b4fda5
AN		 1245 DSM_FUNC_ENABLE_UNII4_CHAN,
1246 &iwl_guid, &value);
1247 if (!ret)
1248 cmd.oem_unii4_allow_bitmap = cpu_to_le32(value);
1249
45fe1b6b 1250 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1f578d4f
MK		 1251 DSM_FUNC_ACTIVATE_CHANNEL,
1252 &iwl_guid, &value);
1253 if (!ret)
1254 cmd.chan_state_active_bitmap = cpu_to_le32(value);
1255
698b166e
LC		 1256 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1257 DSM_FUNC_ENABLE_6E,
1258 &iwl_guid, &value);
1259 if (!ret)
1260 cmd.oem_uhb_allow_bitmap = cpu_to_le32(value);
1261
8f323d06
AB		 1262 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1263 DSM_FUNC_FORCE_DISABLE_CHANNELS,
1264 &iwl_guid, &value);
1265 if (!ret)
1266 cmd.force_disable_channels_bitmap = cpu_to_le32(value);
1267
c8e01fe0
AG		 1268 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1269 DSM_FUNC_ENERGY_DETECTION_THRESHOLD,
1270 &iwl_guid, &value);
1271 if (!ret)
1272 cmd.edt_bitmap = cpu_to_le32(value);
1273
54b4fda5 1274 if (cmd.config_bitmap ||
698b166e 1275 cmd.oem_uhb_allow_bitmap ||
54b4fda5 1276 cmd.oem_11ax_allow_bitmap ||
1f578d4f 1277 cmd.oem_unii4_allow_bitmap ||
8f323d06 1278 cmd.chan_state_active_bitmap ||
c8e01fe0
AG		 1279 cmd.force_disable_channels_bitmap ||
1280 cmd.edt_bitmap) {
3c21990b
MK		 1281 size_t cmd_size;
1282 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw,
971cbe50
JB		 1283 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1284 LARI_CONFIG_CHANGE),
1285 1);
8f323d06 1286 switch (cmd_ver) {
c8e01fe0
AG		 1287 case 7:
1288 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v7);
1289 break;
8f323d06
AB		 1290 case 6:
1291 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v6);
1292 break;
1293 case 5:
1f578d4f 1294 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v5);
8f323d06
AB		 1295 break;
1296 case 4:
54b4fda5 1297 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4);
8f323d06
AB		 1298 break;
1299 case 3:
3c21990b 1300 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3);
8f323d06
AB		 1301 break;
1302 case 2:
3c21990b 1303 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2);
8f323d06
AB		 1304 break;
1305 default:
3c21990b 1306 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1);
8f323d06
AB		 1307 break;
1308 }
3c21990b 1309
3ce88247 1310 IWL_DEBUG_RADIO(mvm,
7119f02b
MK		 1311 "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n",
1312 le32_to_cpu(cmd.config_bitmap),
1313 le32_to_cpu(cmd.oem_11ax_allow_bitmap));
54b4fda5 1314 IWL_DEBUG_RADIO(mvm,
1f578d4f 1315 "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, chan_state_active_bitmap=0x%x, cmd_ver=%d\n",
54b4fda5 1316 le32_to_cpu(cmd.oem_unii4_allow_bitmap),
1f578d4f 1317 le32_to_cpu(cmd.chan_state_active_bitmap),
54b4fda5 1318 cmd_ver);
698b166e 1319 IWL_DEBUG_RADIO(mvm,
8f323d06
AB		 1320 "sending LARI_CONFIG_CHANGE, oem_uhb_allow_bitmap=0x%x, force_disable_channels_bitmap=0x%x\n",
1321 le32_to_cpu(cmd.oem_uhb_allow_bitmap),
1322 le32_to_cpu(cmd.force_disable_channels_bitmap));
c8e01fe0
AG		 1323 IWL_DEBUG_RADIO(mvm,
1324 "sending LARI_CONFIG_CHANGE, edt_bitmap=0x%x\n",
1325 le32_to_cpu(cmd.edt_bitmap));
7119f02b
MK		 1326 ret = iwl_mvm_send_cmd_pdu(mvm,
1327 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1328 LARI_CONFIG_CHANGE),
1329 0, cmd_size, &cmd);
1330 if (ret < 0)
f5b1cb2e
GA		 1331 IWL_DEBUG_RADIO(mvm,
1332 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
7119f02b 1333 ret);
f5b1cb2e
GA		 1334 }
1335}
78a19d52
MK		 1336
1337void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1338{
1339 int ret;
1340
1341 /* read PPAG table */
e8e10a37 1342 ret = iwl_acpi_get_ppag_table(&mvm->fwrt);
78a19d52
MK		 1343 if (ret < 0) {
1344 IWL_DEBUG_RADIO(mvm,
1345 "PPAG BIOS table invalid or unavailable. (%d)\n",
1346 ret);
1347 }
1348
1349 /* read SAR tables */
1350 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
1351 if (ret < 0) {
1352 IWL_DEBUG_RADIO(mvm,
1353 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1354 ret);
1355 /*
1356 * If not available, don't fail and don't bother with EWRD and
1357 * WGDS */
1358
1359 if (!iwl_sar_get_wgds_table(&mvm->fwrt)) {
1360 /*
1361 * If basic SAR is not available, we check for WGDS,
1362 * which should *not* be available either. If it is
1363 * available, issue an error, because we can't use SAR
1364 * Geo without basic SAR.
1365 */
1366 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1367 }
1368
1369 } else {
1370 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
1371 /* if EWRD is not available, we can still use
1372 * WRDS, so don't fail */
1373 if (ret < 0)
1374 IWL_DEBUG_RADIO(mvm,
1375 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1376 ret);
1377
1378 /* read geo SAR table */
1379 if (iwl_sar_geo_support(&mvm->fwrt)) {
1380 ret = iwl_sar_get_wgds_table(&mvm->fwrt);
1381 if (ret < 0)
1382 IWL_DEBUG_RADIO(mvm,
1383 "Geo SAR BIOS table invalid or unavailable. (%d)\n",
1384 ret);
1385 /* we don't fail if the table is not available */
1386 }
1387 }
c4c95454
JB		 1388
1389 iwl_acpi_get_phy_filters(&mvm->fwrt, &mvm->phy_filters);
78a19d52 1390}
69964905 1391#else /* CONFIG_ACPI */
69964905 1392
39c1a972
IZ		 1393inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1394 int prof_a, int prof_b)
69964905 1395{
78a19d52 1396 return 1;
69964905 1397}
a6bff3cb 1398
39c1a972 1399inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC		 1400{
1401 return -ENOENT;
1402}
1403
a6bff3cb
HD		 1404static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1405{
1406 return 0;
1407}
18f1755d 1408
6ce1e5c0
GA		 1409int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1410{
1411 return -ENOENT;
1412}
1413
1414static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1415{
7937fd32 1416 return 0;
6ce1e5c0 1417}
28dd7ccd
MG		 1418
1419static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1420{
1421}
f5b1cb2e
GA		 1422
1423static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1424{
1425}
4e8fe214 1426
9457077d
AN		 1427bool iwl_mvm_is_vendor_in_approved_list(void)
1428{
1429 return false;
1430}
1431
4e8fe214
GG		 1432static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1433{
1434 return DSM_VALUE_RFI_DISABLE;
1435}
78a19d52
MK		 1436
1437void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1438{
1439}
c593d2fa 1440
69964905
LC		 1441#endif /* CONFIG_ACPI */
1442
f130bb75
MG		 1443void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1444{
1445 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1446 int ret;
1447 u32 resp;
1448
1449 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1450 .flags = cpu_to_le32(flags),
1451 .buf_size = 0,
1452 };
1453 struct iwl_host_cmd host_cmd = {
1454 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1455 .flags = CMD_WANT_SKB,
1456 .data = {&recovery_cmd, },
1457 .len = {sizeof(recovery_cmd), },
1458 };
1459
1460 /* no error log was defined in TLV */
1461 if (!error_log_size)
1462 return;
1463
1464 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1465 /* no buf was allocated while HW reset */
1466 if (!mvm->error_recovery_buf)
1467 return;
1468
1469 host_cmd.data[1] = mvm->error_recovery_buf;
1470 host_cmd.len[1] = error_log_size;
1471 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1472 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1473 }
1474
1475 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1476 kfree(mvm->error_recovery_buf);
1477 mvm->error_recovery_buf = NULL;
1478
1479 if (ret) {
1480 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1481 return;
1482 }
1483
1484 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1485 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1486 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1487 if (resp)
1488 IWL_ERR(mvm,
1489 "Failed to send recovery cmd blob was invalid %d\n",
1490 resp);
1491 }
1492}
1493
42ce76d6
LC		 1494static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1495{
1edd56e6 1496 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC		 1497}
1498
1f370650 1499static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1500{
1f370650 1501 int ret;
8ca151b5 1502
7d6222e2 1503 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1504 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1505
3b25f1af 1506 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1507
f2082a53 1508 if (ret) {
8d193ca2 1509 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK		 1510
1511 if (iwlmvm_mod_params.init_dbg)
1512 return 0;
1f370650 1513 return ret;
8d193ca2 1514 }
8ca151b5 1515
203c83d3 1516 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG		 1517 iwl_trans_stop_device(mvm->trans);
1518 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1519 if (ret)
1f370650 1520 return ret;
8ca151b5 1521
94022562 1522 mvm->rfkill_safe_init_done = false;
8ca151b5 1523 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS		 1524 if (ret)
1525 return ret;
1526
94022562
EG		 1527 mvm->rfkill_safe_init_done = true;
1528
b108d8c7
SM		 1529 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1530 NULL);
da2eb669 1531
702e975d 1532 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS		 1533}
1534
1535int iwl_mvm_up(struct iwl_mvm *mvm)
1536{
1537 int ret, i;
dd36a507 1538 struct ieee80211_supported_band *sband = NULL;
1f370650
SS		 1539
1540 lockdep_assert_held(&mvm->mutex);
1541
1542 ret = iwl_trans_start_hw(mvm->trans);
1543 if (ret)
1544 return ret;
733eb54f 1545
1f370650 1546 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB		 1547 if (ret) {
1548 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
b8133439 1549 if (ret != -ERFKILL && !mvm->pldr_sync)
72d3c7bb
JB		 1550 iwl_fw_dbg_error_collect(&mvm->fwrt,
1551 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB		 1552 goto error;
1553 }
1554
b8133439
AS		 1555 /* FW loaded successfully */
1556 mvm->pldr_sync = false;
1557
fc2fe0a5 1558 iwl_fw_disable_dbg_asserts(&mvm->fwrt);
d0b813fc 1559 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1560
1f3b0ff8
LE		 1561 ret = iwl_mvm_sf_update(mvm, NULL, false);
1562 if (ret)
1563 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1564
a1af4c48 1565 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS		 1566 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1567 /* if we have a destination, assume EARLY START */
1568 if (mvm->fw->dbg.dest_tlv)
1569 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1570 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1571 }
6a951267 1572
a0544272 1573 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1574 if (ret)
1575 goto error;
1576
7d6222e2
JB		 1577 if (!iwl_mvm_has_unified_ucode(mvm)) {
1578 /* Send phy db control command and then phy db calibration */
1f370650
SS		 1579 ret = iwl_send_phy_db_data(mvm->phy_db);
1580 if (ret)
1581 goto error;
d2ccc5c1
MS		 1582 ret = iwl_send_phy_cfg_cmd(mvm);
1583 if (ret)
1584 goto error;
1f370650 1585 }
8ca151b5 1586
b3de3ef4
EG		 1587 ret = iwl_mvm_send_bt_init_conf(mvm);
1588 if (ret)
1589 goto error;
1590
cceb4507
SM		 1591 if (fw_has_capa(&mvm->fw->ucode_capa,
1592 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1593 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM		 1594 if (ret)
1595 goto error;
1596 }
1597
c0a2f819
BB		 1598 iwl_mvm_lari_cfg(mvm);
1599
43413a97 1600 /* Init RSS configuration */
9cd243f2
MG		 1601 ret = iwl_configure_rxq(&mvm->fwrt);
1602 if (ret)
1603 goto error;
8edbfaa1
SS		 1604
1605 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS		 1606 ret = iwl_send_rss_cfg_cmd(mvm);
1607 if (ret) {
1608 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1609 ret);
1610 goto error;
1611 }
1612 }
1613
8ca151b5 1614 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1615 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1616 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB		 1617 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1618 }
8ca151b5 1619
d464550b
YB		 1620 for (i = 0; i < IWL_MVM_FW_MAX_LINK_ID + 1; i++)
1621 RCU_INIT_POINTER(mvm->link_id_to_link_conf[i], NULL);
1622
d6f6b0d8
GG		 1623 memset(&mvm->fw_link_ids_map, 0, sizeof(mvm->fw_link_ids_map));
1624
0ae98812 1625 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1626
b2b7875b
JB		 1627 /* reset quota debouncing buffer - 0xff will yield invalid data */
1628 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1629
79660869
IL		 1630 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1631 ret = iwl_mvm_send_dqa_cmd(mvm);
1632 if (ret)
1633 goto error;
1634 }
97d5be7e 1635
2c2c3647
NE		 1636 /*
1637 * Add auxiliary station for scanning.
1638 * Newer versions of this command implies that the fw uses
1639 * internal aux station for all aux activities that don't
1640 * requires a dedicated data queue.
1641 */
1724fc78 1642 if (!iwl_mvm_has_new_station_api(mvm->fw)) {
2c2c3647
NE		 1643 /*
1644 * In old version the aux station uses mac id like other
1645 * station and not lmac id
1646 */
1647 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1648 if (ret)
1649 goto error;
1650 }
8ca151b5 1651
53a9d61e 1652 /* Add all the PHY contexts */
dd36a507
TM		 1653 i = 0;
1654 while (!sband && i < NUM_NL80211_BANDS)
1655 sband = mvm->hw->wiphy->bands[i++];
1656
583d1833
DC		 1657 if (WARN_ON_ONCE(!sband)) {
1658 ret = -ENODEV;
dd36a507 1659 goto error;
583d1833 1660 }
dd36a507 1661
c221daf2
CRI		 1662 if (iwl_mvm_is_tt_in_fw(mvm)) {
1663 /* in order to give the responsibility of ct-kill and
1664 * TX backoff to FW we need to send empty temperature reporting
1665 * cmd during init time
1666 */
1667 iwl_mvm_send_temp_report_ths_cmd(mvm);
1668 } else {
1669 /* Initialize tx backoffs to the minimal possible */
1670 iwl_mvm_tt_tx_backoff(mvm, 0);
1671 }
5c89e7bc 1672
242d9c8b 1673#ifdef CONFIG_THERMAL
5c89e7bc 1674 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI		 1675
1676 /*
1677 * In case there is no budget from BIOS / Platform NVM the default
1678 * budget should be 2000mW (cooling state 0).
1679 */
1680 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI		 1681 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1682 mvm->cooling_dev.cur_state);
75cfe338
LC		 1683 if (ret)
1684 goto error;
1685 }
c221daf2 1686#endif
0c0e2c71 1687
aa43ae12
AM		 1688 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1689 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1690
c1cb92fc 1691 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB		 1692 if (ret)
1693 goto error;
1694
35af15d1
AN		 1695 /*
1696 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1697 * anyway, so don't init MCC.
1698 */
1699 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1700 ret = iwl_mvm_init_mcc(mvm);
1701 if (ret)
1702 goto error;
1703 }
90d4f7db 1704
859d914c 1705 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1706 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1707 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS		 1708 ret = iwl_mvm_config_scan(mvm);
1709 if (ret)
1710 goto error;
1711 }
1712
cf85123a 1713 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) {
f130bb75 1714 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
ead65aa2
JB		 1715
1716 if (mvm->time_sync.active)
1717 iwl_mvm_time_sync_config(mvm, mvm->time_sync.peer_addr,
1718 IWL_TIME_SYNC_PROTOCOL_TM |
1719 IWL_TIME_SYNC_PROTOCOL_FTM);
cf85123a 1720 }
f130bb75 1721
1595ecce
KP		 1722 if (!mvm->ptp_data.ptp_clock)
1723 iwl_mvm_ptp_init(mvm);
1724
48e775e6
HD		 1725 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1726 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1727
6ce1e5c0
GA		 1728 ret = iwl_mvm_ppag_init(mvm);
1729 if (ret)
1730 goto error;
1731
da2830ac 1732 ret = iwl_mvm_sar_init(mvm);
78a19d52 1733 if (ret == 0)
5d041c46 1734 ret = iwl_mvm_sar_geo_init(mvm);
5f06f6bf 1735 if (ret < 0)
a6bff3cb
HD		 1736 goto error;
1737
c593d2fa
AB		 1738 ret = iwl_mvm_sgom_init(mvm);
1739 if (ret)
1740 goto error;
1741
28dd7ccd 1742 iwl_mvm_tas_init(mvm);
7089ae63
JB		 1743 iwl_mvm_leds_sync(mvm);
1744
9e26f098 1745 if (iwl_rfi_supported(mvm)) {
4e8fe214
GG		 1746 if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE)
1747 iwl_rfi_send_config_cmd(mvm, NULL);
1748 }
1749
5aa7ce31
AS		 1750 iwl_mvm_mei_device_state(mvm, true);
1751
53a9d61e 1752 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB		 1753 return 0;
1754 error:
f4744258 1755 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1756 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1757 return ret;
1758}
1759
1760int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1761{
1762 int ret, i;
1763
1764 lockdep_assert_held(&mvm->mutex);
1765
1766 ret = iwl_trans_start_hw(mvm->trans);
1767 if (ret)
1768 return ret;
1769
1770 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1771 if (ret) {
1772 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1773 goto error;
1774 }
1775
a0544272 1776 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1777 if (ret)
1778 goto error;
1779
1780 /* Send phy db control command and then phy db calibration*/
1781 ret = iwl_send_phy_db_data(mvm->phy_db);
1782 if (ret)
1783 goto error;
1784
1785 ret = iwl_send_phy_cfg_cmd(mvm);
1786 if (ret)
1787 goto error;
1788
1789 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1790 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1791 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB		 1792 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1793 }
8ca151b5 1794
1724fc78 1795 if (!iwl_mvm_has_new_station_api(mvm->fw)) {
2c2c3647
NE		 1796 /*
1797 * Add auxiliary station for scanning.
1798 * Newer versions of this command implies that the fw uses
1799 * internal aux station for all aux activities that don't
1800 * requires a dedicated data queue.
1801 * In old version the aux station uses mac id like other
1802 * station and not lmac id
1803 */
1804 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1805 if (ret)
1806 goto error;
1807 }
8ca151b5
JB		 1808
1809 return 0;
1810 error:
fcb6b92a 1811 iwl_mvm_stop_device(mvm);
8ca151b5
JB		 1812 return ret;
1813}
1814
0416841d
JB		 1815void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1816 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI		 1817{
1818 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1819 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1820
0c8d0a47
GBA		 1821 IWL_DEBUG_INFO(mvm,
1822 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1823 le32_to_cpu(mfuart_notif->installed_ver),
1824 le32_to_cpu(mfuart_notif->external_ver),
1825 le32_to_cpu(mfuart_notif->status),
1826 le32_to_cpu(mfuart_notif->duration));
1827
19f63c53
GBA		 1828 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1829 IWL_DEBUG_INFO(mvm,
0c8d0a47 1830 "MFUART: image size: 0x%08x\n",
19f63c53 1831 le32_to_cpu(mfuart_notif->image_size));
30269c12 1832}
Linux 6.x block layer and io_uring tree(s)