wifi: iwlwifi: mvm: return error value in case PLDR sync failed
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
a7de31d5 3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
8e99ea8d
JB
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
a2ac0f48 9#include <linux/dmi.h>
8ca151b5
JB
10
11#include "iwl-trans.h"
12#include "iwl-op-mode.h"
d962f9b1 13#include "fw/img.h"
8ca151b5 14#include "iwl-debug.h"
8c23f95c 15#include "iwl-prph.h"
813df5ce 16#include "fw/acpi.h"
b3e4c0f3 17#include "fw/pnvm.h"
8ca151b5
JB
18
19#include "mvm.h"
7174beb6 20#include "fw/dbg.h"
8ca151b5 21#include "iwl-phy-db.h"
9c4f7d51
ST
22#include "iwl-modparams.h"
23#include "iwl-nvm-parse.h"
8ca151b5 24
b3e4c0f3
LC
25#define MVM_UCODE_ALIVE_TIMEOUT (HZ)
26#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5 27
c3f40c3e
MK
28#define IWL_TAS_US_MCC 0x5553
29#define IWL_TAS_CANADA_MCC 0x4341
30
8ca151b5
JB
31struct iwl_mvm_alive_data {
32 bool valid;
33 u32 scd_base_addr;
34};
35
8ca151b5
JB
36static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
37{
38 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
39 .valid = cpu_to_le32(valid_tx_ant),
40 };
41
33223542 42 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 43 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB
44 sizeof(tx_ant_cmd), &tx_ant_cmd);
45}
46
43413a97
SS
47static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
48{
49 int i;
50 struct iwl_rss_config_cmd cmd = {
51 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS
52 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
53 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
54 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
55 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
56 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS
58 };
59
f43495fd
SS
60 if (mvm->trans->num_rx_queues == 1)
61 return 0;
62
854d773e 63 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 64 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS
65 cmd.indirection_table[i] =
66 1 + (i % (mvm->trans->num_rx_queues - 1));
67 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS
68
69 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
70}
71
97d5be7e
LK
72static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
73{
74 struct iwl_dqa_enable_cmd dqa_cmd = {
75 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
76 };
f0c86427 77 u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD);
97d5be7e
LK
78 int ret;
79
80 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
81 if (ret)
82 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
83 else
84 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
85
86 return ret;
87}
88
bdccdb85
GBA
89void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
90 struct iwl_rx_cmd_buffer *rxb)
91{
92 struct iwl_rx_packet *pkt = rxb_addr(rxb);
93 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
94 __le32 *dump_data = mfu_dump_notif->data;
95 int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
96 int i;
97
98 if (mfu_dump_notif->index_num == 0)
99 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
100 le32_to_cpu(mfu_dump_notif->assert_id));
101
102 for (i = 0; i < n_words; i++)
103 IWL_DEBUG_INFO(mvm,
104 "MFUART assert dump, dword %u: 0x%08x\n",
105 le16_to_cpu(mfu_dump_notif->index_num) *
106 n_words + i,
107 le32_to_cpu(dump_data[i]));
108}
109
8ca151b5
JB
110static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
111 struct iwl_rx_packet *pkt, void *data)
112{
fd1c3318 113 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB
114 struct iwl_mvm *mvm =
115 container_of(notif_wait, struct iwl_mvm, notif_wait);
116 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS
117 struct iwl_umac_alive *umac;
118 struct iwl_lmac_alive *lmac1;
119 struct iwl_lmac_alive *lmac2 = NULL;
120 u16 status;
cfa5d0ca 121 u32 lmac_error_event_table, umac_error_table;
708d8c53
JB
122 u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
123 UCODE_ALIVE_NTFY, 0);
5053a451 124 u32 i;
01a9ca51 125
c0941ace
MS
126 if (version == 6) {
127 struct iwl_alive_ntf_v6 *palive;
128
129 if (pkt_len < sizeof(*palive))
130 return false;
131
132 palive = (void *)pkt->data;
133 mvm->trans->dbg.imr_data.imr_enable =
134 le32_to_cpu(palive->imr.enabled);
135 mvm->trans->dbg.imr_data.imr_size =
136 le32_to_cpu(palive->imr.size);
137 mvm->trans->dbg.imr_data.imr2sram_remainbyte =
138 mvm->trans->dbg.imr_data.imr_size;
139 mvm->trans->dbg.imr_data.imr_base_addr =
140 palive->imr.base_addr;
141 mvm->trans->dbg.imr_data.imr_curr_addr =
142 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr);
143 IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n",
144 mvm->trans->dbg.imr_data.imr_enable,
145 mvm->trans->dbg.imr_data.imr_size,
146 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr));
5053a451
MS
147
148 if (!mvm->trans->dbg.imr_data.imr_enable) {
149 for (i = 0; i < ARRAY_SIZE(mvm->trans->dbg.active_regions); i++) {
150 struct iwl_ucode_tlv *reg_tlv;
151 struct iwl_fw_ini_region_tlv *reg;
152
153 reg_tlv = mvm->trans->dbg.active_regions[i];
154 if (!reg_tlv)
155 continue;
156
157 reg = (void *)reg_tlv->data;
158 /*
159 * We have only one DRAM IMR region, so we
160 * can break as soon as we find the first
161 * one.
162 */
163 if (reg->type == IWL_FW_INI_REGION_DRAM_IMR) {
164 mvm->trans->dbg.unsupported_region_msk |= BIT(i);
165 break;
166 }
167 }
168 }
c0941ace
MS
169 }
170
171 if (version >= 5) {
90824f2f
LC
172 struct iwl_alive_ntf_v5 *palive;
173
fd1c3318
JB
174 if (pkt_len < sizeof(*palive))
175 return false;
176
90824f2f
LC
177 palive = (void *)pkt->data;
178 umac = &palive->umac_data;
179 lmac1 = &palive->lmac_data[0];
180 lmac2 = &palive->lmac_data[1];
181 status = le16_to_cpu(palive->status);
182
183 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
184 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
185 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
186
187 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
188 mvm->trans->sku_id[0],
189 mvm->trans->sku_id[1],
190 mvm->trans->sku_id[2]);
191 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC
192 struct iwl_alive_ntf_v4 *palive;
193
fd1c3318
JB
194 if (pkt_len < sizeof(*palive))
195 return false;
196
5c228d63
SS
197 palive = (void *)pkt->data;
198 umac = &palive->umac_data;
199 lmac1 = &palive->lmac_data[0];
200 lmac2 = &palive->lmac_data[1];
201 status = le16_to_cpu(palive->status);
9422b978
LC
202 } else if (iwl_rx_packet_payload_len(pkt) ==
203 sizeof(struct iwl_alive_ntf_v3)) {
204 struct iwl_alive_ntf_v3 *palive3;
205
fd1c3318
JB
206 if (pkt_len < sizeof(*palive3))
207 return false;
208
5c228d63
SS
209 palive3 = (void *)pkt->data;
210 umac = &palive3->umac_data;
211 lmac1 = &palive3->lmac_data;
212 status = le16_to_cpu(palive3->status);
9422b978
LC
213 } else {
214 WARN(1, "unsupported alive notification (size %d)\n",
215 iwl_rx_packet_payload_len(pkt));
216 /* get timeout later */
217 return false;
5c228d63 218 }
01a9ca51 219
22463857
SM
220 lmac_error_event_table =
221 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
222 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
223
5c228d63 224 if (lmac2)
91c28b83 225 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 226 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 227
4f7411d6
RG
228 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
229 ~FW_ADDR_CACHE_CONTROL;
cfa5d0ca
MG
230
231 if (umac_error_table) {
232 if (umac_error_table >=
233 mvm->trans->cfg->min_umac_error_event_table) {
234 iwl_fw_umac_set_alive_err_table(mvm->trans,
235 umac_error_table);
236 } else {
237 IWL_ERR(mvm,
238 "Not valid error log pointer 0x%08X for %s uCode\n",
239 umac_error_table,
240 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
241 "Init" : "RT");
242 }
3485e76e 243 }
fb5b2846 244
22463857 245 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 246 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 247
5c228d63
SS
248 IWL_DEBUG_FW(mvm,
249 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
250 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 251
5c228d63
SS
252 if (lmac2)
253 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 254
5c228d63
SS
255 IWL_DEBUG_FW(mvm,
256 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
257 le32_to_cpu(umac->umac_major),
258 le32_to_cpu(umac->umac_minor));
8ca151b5 259
0a3a3e9e
SM
260 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
261
8ca151b5
JB
262 return true;
263}
264
1f370650
SS
265static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
266 struct iwl_rx_packet *pkt, void *data)
267{
268 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
269
270 return true;
271}
272
8ca151b5
JB
273static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
274 struct iwl_rx_packet *pkt, void *data)
275{
276 struct iwl_phy_db *phy_db = data;
277
278 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
279 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
280 return true;
281 }
282
ce1f2778 283 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB
284
285 return false;
286}
287
a7de31d5
MG
288static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
289{
184f10db
MG
290#define IWL_FW_PRINT_REG_INFO(reg_name) \
291 IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
292
a7de31d5
MG
293 struct iwl_trans *trans = mvm->trans;
294 enum iwl_device_family device_family = trans->trans_cfg->device_family;
295
296 if (device_family < IWL_DEVICE_FAMILY_8000)
297 return;
298
299 if (device_family <= IWL_DEVICE_FAMILY_9000)
184f10db 300 IWL_FW_PRINT_REG_INFO(WFPM_ARC1_PD_NOTIFICATION);
a7de31d5 301 else
184f10db 302 IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);
f2f17ca0 303
184f10db 304 IWL_FW_PRINT_REG_INFO(HPM_SECONDARY_DEVICE_STATE);
f2f17ca0 305
184f10db
MG
306 /* print OPT info */
307 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_ADDR);
308 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_DATA);
a7de31d5
MG
309}
310
8ca151b5
JB
311static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
312 enum iwl_ucode_type ucode_type)
313{
314 struct iwl_notification_wait alive_wait;
94a8d87c 315 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 316 const struct fw_img *fw;
cfbc6c4c 317 int ret;
702e975d 318 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 319 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG
320 bool run_in_rfkill =
321 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
8ca151b5 322
61df750c 323 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA
324 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
325 !(fw_has_capa(&mvm->fw->ucode_capa,
326 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 327 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 328 else
612da1ef 329 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 330 if (WARN_ON(!fw))
8ca151b5 331 return -EINVAL;
702e975d 332 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 333 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB
334
335 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
336 alive_cmd, ARRAY_SIZE(alive_cmd),
337 iwl_alive_fn, &alive_data);
338
b3500b47
EG
339 /*
340 * We want to load the INIT firmware even in RFKILL
341 * For the unified firmware case, the ucode_type is not
342 * INIT, but we still need to run it.
343 */
344 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 345 if (ret) {
702e975d 346 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
347 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
348 return ret;
349 }
350
351 /*
352 * Some things may run in the background now, but we
353 * just wait for the ALIVE notification here.
354 */
355 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
356 MVM_UCODE_ALIVE_TIMEOUT);
56731878
DG
357
358 if (mvm->trans->trans_cfg->device_family ==
359 IWL_DEVICE_FAMILY_AX210) {
360 /* print these registers regardless of alive fail/success */
361 IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n",
362 iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
363 IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n",
364 iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
365 IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n",
366 iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
b8133439
AS
367 IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n",
368 iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
56731878
DG
369 }
370
8ca151b5 371 if (ret) {
d6be9c1d
SS
372 struct iwl_trans *trans = mvm->trans;
373
5667ccc2 374 /* SecBoot info */
20f5aef5
JB
375 if (trans->trans_cfg->device_family >=
376 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS
377 IWL_ERR(mvm,
378 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST
379 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
380 iwl_read_umac_prph(trans,
381 UMAG_SB_CPU_2_STATUS));
5667ccc2
MG
382 } else if (trans->trans_cfg->device_family >=
383 IWL_DEVICE_FAMILY_8000) {
384 IWL_ERR(mvm,
385 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
386 iwl_read_prph(trans, SB_CPU_1_STATUS),
387 iwl_read_prph(trans, SB_CPU_2_STATUS));
388 }
389
a7de31d5
MG
390 iwl_mvm_print_pd_notification(mvm);
391
5667ccc2
MG
392 /* LMAC/UMAC PC info */
393 if (trans->trans_cfg->device_family >=
394 IWL_DEVICE_FAMILY_9000) {
20f5aef5
JB
395 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
396 iwl_read_umac_prph(trans,
397 UREG_UMAC_CURRENT_PC));
398 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
399 iwl_read_umac_prph(trans,
400 UREG_LMAC1_CURRENT_PC));
401 if (iwl_mvm_is_cdb_supported(mvm))
402 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
403 iwl_read_umac_prph(trans,
404 UREG_LMAC2_CURRENT_PC));
20f5aef5
JB
405 }
406
b8133439 407 if (ret == -ETIMEDOUT && !mvm->pldr_sync)
20f5aef5
JB
408 iwl_fw_dbg_error_collect(&mvm->fwrt,
409 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
410
702e975d 411 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
412 return ret;
413 }
414
415 if (!alive_data.valid) {
416 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 417 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
418 return -EIO;
419 }
420
733eb54f
AS
421 iwl_mei_alive_notif(!ret);
422
b3e4c0f3 423 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait);
70d3ca86
LC
424 if (ret) {
425 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
426 iwl_fw_set_current_image(&mvm->fwrt, old_type);
427 return ret;
428 }
429
8ca151b5
JB
430 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
431
432 /*
433 * Note: all the queues are enabled as part of the interface
434 * initialization, but in firmware restart scenarios they
435 * could be stopped, so wake them up. In firmware restart,
436 * mac80211 will have the queues stopped as well until the
437 * reconfiguration completes. During normal startup, they
438 * will be empty.
439 */
440
4ecafae9 441 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB
442 /*
443 * Set a 'fake' TID for the command queue, since we use the
444 * hweight() of the tid_bitmap as a refcount now. Not that
445 * we ever even consider the command queue as one we might
446 * want to reuse, but be safe nevertheless.
447 */
448 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
449 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 450
65b280fe 451 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC
452#ifdef CONFIG_IWLWIFI_DEBUGFS
453 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
454#endif
8ca151b5 455
d3d9b4fc
EG
456 /*
457 * All the BSSes in the BSS table include the GP2 in the system
458 * at the beacon Rx time, this is of course no longer relevant
459 * since we are resetting the firmware.
460 * Purge all the BSS table.
461 */
462 cfg80211_bss_flush(mvm->hw->wiphy);
463
8ca151b5
JB
464 return 0;
465}
8ca151b5 466
52b15521 467static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
8c5f47b1
JB
468{
469 struct iwl_notification_wait init_wait;
470 struct iwl_nvm_access_complete_cmd nvm_complete = {};
471 struct iwl_init_extended_cfg_cmd init_cfg = {
472 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
473 };
474 static const u16 init_complete[] = {
475 INIT_COMPLETE_NOTIF,
476 };
477 int ret;
478
a4584729
HD
479 if (mvm->trans->cfg->tx_with_siso_diversity)
480 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
481
8c5f47b1
JB
482 lockdep_assert_held(&mvm->mutex);
483
94022562
EG
484 mvm->rfkill_safe_init_done = false;
485
8c5f47b1
JB
486 iwl_init_notification_wait(&mvm->notif_wait,
487 &init_wait,
488 init_complete,
489 ARRAY_SIZE(init_complete),
490 iwl_wait_init_complete,
491 NULL);
492
b108d8c7 493 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
86ce5c74 494
8c5f47b1
JB
495 /* Will also start the device */
496 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
497 if (ret) {
498 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
499 goto error;
500 }
b108d8c7
SM
501 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
502 NULL);
8c5f47b1
JB
503
504 /* Send init config command to mark that we are sending NVM access
505 * commands
506 */
507 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
b3500b47
EG
508 INIT_EXTENDED_CFG_CMD),
509 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
510 sizeof(init_cfg), &init_cfg);
511 if (ret) {
512 IWL_ERR(mvm, "Failed to run init config command: %d\n",
513 ret);
514 goto error;
515 }
516
e9e1ba3d
SS
517 /* Load NVM to NIC if needed */
518 if (mvm->nvm_file_name) {
9ce505fe
AN
519 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
520 mvm->nvm_sections);
521 if (ret)
522 goto error;
523 ret = iwl_mvm_load_nvm_to_nic(mvm);
524 if (ret)
525 goto error;
e9e1ba3d 526 }
8c5f47b1 527
52b15521 528 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
5bd1d2c1 529 ret = iwl_nvm_init(mvm);
d4f3695e
SS
530 if (ret) {
531 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
532 goto error;
533 }
534 }
535
8c5f47b1 536 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
b3500b47
EG
537 NVM_ACCESS_COMPLETE),
538 CMD_SEND_IN_RFKILL,
8c5f47b1
JB
539 sizeof(nvm_complete), &nvm_complete);
540 if (ret) {
541 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
542 ret);
543 goto error;
544 }
545
546 /* We wait for the INIT complete notification */
e9e1ba3d
SS
547 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
548 MVM_UCODE_ALIVE_TIMEOUT);
549 if (ret)
550 return ret;
551
552 /* Read the NVM only at driver load time, no need to do this twice */
52b15521 553 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
4c625c56 554 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
c135cb56
ST
555 if (IS_ERR(mvm->nvm_data)) {
556 ret = PTR_ERR(mvm->nvm_data);
557 mvm->nvm_data = NULL;
e9e1ba3d
SS
558 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
559 return ret;
560 }
561 }
562
b3500b47
EG
563 mvm->rfkill_safe_init_done = true;
564
e9e1ba3d 565 return 0;
8c5f47b1
JB
566
567error:
568 iwl_remove_notification(&mvm->notif_wait, &init_wait);
569 return ret;
570}
571
c4ace426
GA
572#ifdef CONFIG_ACPI
573static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
574 struct iwl_phy_specific_cfg *phy_filters)
575{
576 /*
577 * TODO: read specific phy config from BIOS
578 * ACPI table for this feature has not been defined yet,
579 * so for now we use hardcoded values.
580 */
581
582 if (IWL_MVM_PHY_FILTER_CHAIN_A) {
583 phy_filters->filter_cfg_chain_a =
584 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
585 }
586 if (IWL_MVM_PHY_FILTER_CHAIN_B) {
587 phy_filters->filter_cfg_chain_b =
588 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
589 }
590 if (IWL_MVM_PHY_FILTER_CHAIN_C) {
591 phy_filters->filter_cfg_chain_c =
592 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
593 }
594 if (IWL_MVM_PHY_FILTER_CHAIN_D) {
595 phy_filters->filter_cfg_chain_d =
596 cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
597 }
598}
c4ace426
GA
599#else /* CONFIG_ACPI */
600
601static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
602 struct iwl_phy_specific_cfg *phy_filters)
603{
604}
605#endif /* CONFIG_ACPI */
606
c593d2fa
AB
607#if defined(CONFIG_ACPI) && defined(CONFIG_EFI)
608static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
609{
610 u8 cmd_ver;
611 int ret;
612 struct iwl_host_cmd cmd = {
613 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
614 SAR_OFFSET_MAPPING_TABLE_CMD),
615 .flags = 0,
616 .data[0] = &mvm->fwrt.sgom_table,
617 .len[0] = sizeof(mvm->fwrt.sgom_table),
618 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
619 };
620
621 if (!mvm->fwrt.sgom_enabled) {
622 IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n");
623 return 0;
624 }
625
971cbe50 626 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
c593d2fa
AB
627 IWL_FW_CMD_VER_UNKNOWN);
628
629 if (cmd_ver != 2) {
630 IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n",
631 cmd_ver);
632 return 0;
633 }
634
635 ret = iwl_mvm_send_cmd(mvm, &cmd);
636 if (ret < 0)
637 IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret);
638
639 return ret;
640}
641#else
642
643static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
644{
645 return 0;
646}
647#endif
648
8ca151b5
JB
649static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
650{
971cbe50 651 u32 cmd_id = PHY_CONFIGURATION_CMD;
c4ace426 652 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 653 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA
654 struct iwl_phy_specific_cfg phy_filters = {};
655 u8 cmd_ver;
656 size_t cmd_size;
8ca151b5 657
bb99ff9b 658 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 659 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 660 return 0;
d923b020
LC
661
662 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC
663 /*
664 * TODO: currently we don't set the antenna but letting the NIC
665 * to decide which antenna to use. This should come from BIOS.
666 */
667 phy_cfg_cmd.phy_cfg =
668 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
669 }
670
8ca151b5 671 /* Set parameters */
a0544272 672 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC
673
674 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC
675 phy_cfg_cmd.phy_cfg |=
676 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 677
8ca151b5
JB
678 phy_cfg_cmd.calib_control.event_trigger =
679 mvm->fw->default_calib[ucode_type].event_trigger;
680 phy_cfg_cmd.calib_control.flow_trigger =
681 mvm->fw->default_calib[ucode_type].flow_trigger;
682
971cbe50 683 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 684 IWL_FW_CMD_VER_UNKNOWN);
c4ace426
GA
685 if (cmd_ver == 3) {
686 iwl_mvm_phy_filter_init(mvm, &phy_filters);
687 memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
688 sizeof(struct iwl_phy_specific_cfg));
689 }
690
8ca151b5
JB
691 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
692 phy_cfg_cmd.phy_cfg);
c4ace426
GA
693 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
694 sizeof(struct iwl_phy_cfg_cmd_v1);
971cbe50 695 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd);
8ca151b5
JB
696}
697
3b25f1af 698int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB
699{
700 struct iwl_notification_wait calib_wait;
6eb031d2 701 static const u16 init_complete[] = {
8ca151b5
JB
702 INIT_COMPLETE_NOTIF,
703 CALIB_RES_NOTIF_PHY_DB
704 };
705 int ret;
706
7d6222e2 707 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 708 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 709
8ca151b5
JB
710 lockdep_assert_held(&mvm->mutex);
711
94022562 712 mvm->rfkill_safe_init_done = false;
8ca151b5
JB
713
714 iwl_init_notification_wait(&mvm->notif_wait,
715 &calib_wait,
716 init_complete,
717 ARRAY_SIZE(init_complete),
718 iwl_wait_phy_db_entry,
719 mvm->phy_db);
720
11f8c533
LC
721 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
722
8ca151b5
JB
723 /* Will also start the device */
724 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
725 if (ret) {
726 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 727 goto remove_notif;
8ca151b5
JB
728 }
729
7d34a7d7 730 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG
731 ret = iwl_mvm_send_bt_init_conf(mvm);
732 if (ret)
00e0c6c8 733 goto remove_notif;
b3de3ef4 734 }
931d4160 735
81a67e32 736 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 737 if (!mvm->nvm_data) {
5bd1d2c1 738 ret = iwl_nvm_init(mvm);
8ca151b5
JB
739 if (ret) {
740 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 741 goto remove_notif;
8ca151b5
JB
742 }
743 }
744
81a67e32 745 /* In case we read the NVM from external file, load it to the NIC */
9ce505fe
AN
746 if (mvm->nvm_file_name) {
747 ret = iwl_mvm_load_nvm_to_nic(mvm);
748 if (ret)
749 goto remove_notif;
750 }
81a67e32 751
64866e5d
LC
752 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
753 "Too old NVM version (0x%0x, required = 0x%0x)",
754 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 755
4f59334b
EH
756 /*
757 * abort after reading the nvm in case RF Kill is on, we will complete
758 * the init seq later when RF kill will switch to off
759 */
1a3fe0b2 760 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH
761 IWL_DEBUG_RF_KILL(mvm,
762 "jump over all phy activities due to RF kill\n");
00e0c6c8 763 goto remove_notif;
4f59334b
EH
764 }
765
b3500b47 766 mvm->rfkill_safe_init_done = true;
31b8b343 767
e07cbb53 768 /* Send TX valid antennas before triggering calibrations */
a0544272 769 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 770 if (ret)
00e0c6c8 771 goto remove_notif;
e07cbb53 772
8ca151b5
JB
773 ret = iwl_send_phy_cfg_cmd(mvm);
774 if (ret) {
775 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
776 ret);
00e0c6c8 777 goto remove_notif;
8ca151b5
JB
778 }
779
780 /*
781 * Some things may run in the background now, but we
782 * just wait for the calibration complete notification.
783 */
784 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC
785 MVM_UCODE_CALIB_TIMEOUT);
786 if (!ret)
787 goto out;
31b8b343 788
00e0c6c8 789 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 790 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC
791 ret = 0;
792 } else {
793 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
794 ret);
31b8b343 795 }
00e0c6c8 796
8ca151b5
JB
797 goto out;
798
00e0c6c8 799remove_notif:
8ca151b5
JB
800 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
801out:
b3500b47 802 mvm->rfkill_safe_init_done = false;
a4082843 803 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB
804 /* we want to debug INIT and we have no NVM - fake */
805 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
806 sizeof(struct ieee80211_channel) +
807 sizeof(struct ieee80211_rate),
808 GFP_KERNEL);
809 if (!mvm->nvm_data)
810 return -ENOMEM;
8ca151b5
JB
811 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
812 mvm->nvm_data->bands[0].n_channels = 1;
813 mvm->nvm_data->bands[0].n_bitrates = 1;
814 mvm->nvm_data->bands[0].bitrates =
3827cb59 815 (void *)((u8 *)mvm->nvm_data->channels + 1);
8ca151b5
JB
816 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
817 }
818
819 return ret;
820}
821
84bfffa9
EG
822static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
823{
824 struct iwl_ltr_config_cmd cmd = {
825 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
826 };
827
828 if (!mvm->trans->ltr_enabled)
829 return 0;
830
84bfffa9
EG
831 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
832 sizeof(cmd), &cmd);
833}
834
c386dacb 835#ifdef CONFIG_ACPI
42ce76d6 836int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 837{
971cbe50 838 u32 cmd_id = REDUCE_TX_POWER_CMD;
216cdfb5
LC
839 struct iwl_dev_tx_power_cmd cmd = {
840 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 841 };
9c08cef8 842 __le16 *per_chain;
1edd56e6 843 int ret;
39c1a972 844 u16 len = 0;
fbb7957d 845 u32 n_subbands;
971cbe50 846 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 847 IWL_FW_CMD_VER_UNKNOWN);
b0aa02b3
AB
848 if (cmd_ver == 7) {
849 len = sizeof(cmd.v7);
850 n_subbands = IWL_NUM_SUB_BANDS_V2;
851 per_chain = cmd.v7.per_chain[0][0];
852 cmd.v7.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags);
853 } else if (cmd_ver == 6) {
fbb7957d
LC
854 len = sizeof(cmd.v6);
855 n_subbands = IWL_NUM_SUB_BANDS_V2;
856 per_chain = cmd.v6.per_chain[0][0];
857 } else if (fw_has_api(&mvm->fw->ucode_capa,
858 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 859 len = sizeof(cmd.v5);
e12cfc7b 860 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
861 per_chain = cmd.v5.per_chain[0][0];
862 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 863 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 864 len = sizeof(cmd.v4);
e12cfc7b 865 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
866 per_chain = cmd.v4.per_chain[0][0];
867 } else {
216cdfb5 868 len = sizeof(cmd.v3);
e12cfc7b 869 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
870 per_chain = cmd.v3.per_chain[0][0];
871 }
55bfa4b9 872
216cdfb5
LC
873 /* all structs have the same common part, add it */
874 len += sizeof(cmd.common);
da2830ac 875
dac7171c
LC
876 ret = iwl_sar_select_profile(&mvm->fwrt, per_chain,
877 IWL_NUM_CHAIN_TABLES,
fbb7957d 878 n_subbands, prof_a, prof_b);
1edd56e6
LC
879
880 /* return on error or if the profile is disabled (positive number) */
881 if (ret)
882 return ret;
883
6d19a5eb
EG
884 iwl_mei_set_power_limit(per_chain);
885
42ce76d6 886 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
971cbe50 887 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
42ce76d6
LC
888}
889
7fe90e0e
HD
890int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
891{
dd2a1256 892 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 893 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 894 u16 len;
39c1a972 895 int ret;
c8611331
JB
896 struct iwl_host_cmd cmd = {
897 .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD),
898 .flags = CMD_WANT_SKB,
899 .data = { &geo_tx_cmd },
900 };
971cbe50 901 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
e80bfd11 902 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 903
dd2a1256
LC
904 /* the ops field is at the same spot for all versions, so set in v1 */
905 geo_tx_cmd.v1.ops =
906 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
907
97f8a3d1
AB
908 if (cmd_ver == 5)
909 len = sizeof(geo_tx_cmd.v5);
910 else if (cmd_ver == 4)
911 len = sizeof(geo_tx_cmd.v4);
912 else if (cmd_ver == 3)
0ea788ed
LC
913 len = sizeof(geo_tx_cmd.v3);
914 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
915 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC
916 len = sizeof(geo_tx_cmd.v2);
917 else
918 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 919
39c1a972
IZ
920 if (!iwl_sar_geo_support(&mvm->fwrt))
921 return -EOPNOTSUPP;
922
c8611331 923 cmd.len[0] = len;
7fe90e0e
HD
924
925 ret = iwl_mvm_send_cmd(mvm, &cmd);
926 if (ret) {
927 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
928 return ret;
929 }
f604324e
LC
930
931 resp = (void *)cmd.resp_pkt->data;
932 ret = le32_to_cpu(resp->profile_idx);
933
97f8a3d1 934 if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES_REV3))
f604324e
LC
935 ret = -EIO;
936
7fe90e0e
HD
937 iwl_free_resp(&cmd);
938 return ret;
939}
940
a6bff3cb
HD
941static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
942{
971cbe50 943 u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD);
dd2a1256 944 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 945 u16 len;
45acebf8 946 u32 n_bands;
97f8a3d1 947 u32 n_profiles;
ac9952f6 948 u32 sk = 0;
0433ae55 949 int ret;
971cbe50 950 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 951 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 952
45acebf8
NG
953 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
954 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
955 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
97f8a3d1
AB
956 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) ||
957 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) !=
958 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) ||
959 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) !=
960 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops));
961
dd2a1256
LC
962 /* the ops field is at the same spot for all versions, so set in v1 */
963 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 964
97f8a3d1
AB
965 if (cmd_ver == 5) {
966 len = sizeof(cmd.v5);
967 n_bands = ARRAY_SIZE(cmd.v5.table[0]);
968 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
969 } else if (cmd_ver == 4) {
970 len = sizeof(cmd.v4);
971 n_bands = ARRAY_SIZE(cmd.v4.table[0]);
972 n_profiles = ACPI_NUM_GEO_PROFILES_REV3;
973 } else if (cmd_ver == 3) {
0ea788ed 974 len = sizeof(cmd.v3);
45acebf8 975 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
97f8a3d1 976 n_profiles = ACPI_NUM_GEO_PROFILES;
0ea788ed
LC
977 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
978 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 979 len = sizeof(cmd.v2);
45acebf8 980 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
97f8a3d1 981 n_profiles = ACPI_NUM_GEO_PROFILES;
39c1a972 982 } else {
dd2a1256 983 len = sizeof(cmd.v1);
45acebf8 984 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
97f8a3d1 985 n_profiles = ACPI_NUM_GEO_PROFILES;
0c3d7282
HD
986 }
987
45acebf8
NG
988 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
989 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
990 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
97f8a3d1
AB
991 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) ||
992 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) !=
993 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) ||
994 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) !=
995 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table));
45acebf8 996 /* the table is at the same position for all versions, so set use v1 */
97f8a3d1
AB
997 ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0],
998 n_bands, n_profiles);
45acebf8
NG
999
1000 /*
1001 * It is a valid scenario to not support SAR, or miss wgds table,
1002 * but in that case there is no need to send the command.
1003 */
1004 if (ret)
1005 return 0;
1006
ac9952f6
LC
1007 /* Only set to South Korea if the table revision is 1 */
1008 if (mvm->fwrt.geo_rev == 1)
1009 sk = 1;
1010
28db1862 1011 /*
ac9952f6
LC
1012 * Set the table_revision to South Korea (1) or not (0). The
1013 * element name is misleading, as it doesn't contain the table
1014 * revision number, but whether the South Korea variation
1015 * should be used.
28db1862
LC
1016 * This must be done after calling iwl_sar_geo_init().
1017 */
97f8a3d1 1018 if (cmd_ver == 5)
ac9952f6 1019 cmd.v5.table_revision = cpu_to_le32(sk);
97f8a3d1 1020 else if (cmd_ver == 4)
ac9952f6 1021 cmd.v4.table_revision = cpu_to_le32(sk);
97f8a3d1 1022 else if (cmd_ver == 3)
ac9952f6 1023 cmd.v3.table_revision = cpu_to_le32(sk);
28db1862
LC
1024 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
1025 IWL_UCODE_TLV_API_SAR_TABLE_VER))
ac9952f6 1026 cmd.v2.table_revision = cpu_to_le32(sk);
28db1862 1027
971cbe50 1028 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
6ce1e5c0
GA
1029}
1030
1031int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1032{
8bdc52b9 1033 union iwl_ppag_table_cmd cmd;
e8e10a37 1034 int ret, cmd_size;
160bab43 1035
e8e10a37 1036 ret = iwl_read_ppag_table(&mvm->fwrt, &cmd, &cmd_size);
b20bdd9c 1037 /* Not supporting PPAG table is a valid scenario */
e8e10a37 1038 if(ret < 0)
b20bdd9c 1039 return 0;
6ce1e5c0 1040
f2134f66 1041 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA
1042 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1043 PER_PLATFORM_ANT_GAIN_CMD),
8bdc52b9 1044 0, cmd_size, &cmd);
6ce1e5c0
GA
1045 if (ret < 0)
1046 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1047 ret);
1048
1049 return ret;
1050}
1051
1052static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1053{
78a19d52 1054 /* no need to read the table, done in INIT stage */
e8e10a37 1055 if (!(iwl_acpi_is_ppag_approved(&mvm->fwrt)))
a2ac0f48 1056 return 0;
a2ac0f48 1057
6ce1e5c0
GA
1058 return iwl_mvm_ppag_send_cmd(mvm);
1059}
1060
2856f623
AB
1061static const struct dmi_system_id dmi_tas_approved_list[] = {
1062 { .ident = "HP",
1063 .matches = {
1064 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1065 },
1066 },
1067 { .ident = "SAMSUNG",
1068 .matches = {
1069 DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
1070 },
1071 },
1072 { .ident = "LENOVO",
1073 .matches = {
1074 DMI_MATCH(DMI_SYS_VENDOR, "Lenovo"),
1075 },
1076 },
1077 { .ident = "DELL",
1078 .matches = {
1079 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1080 },
1081 },
1082
1083 /* keep last */
1084 {}
1085};
1086
c3f40c3e
MK
1087static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc)
1088{
1089 int i;
1090 u32 size = le32_to_cpu(*le_size);
1091
1092 /* Verify that there is room for another country */
1093 if (size >= IWL_TAS_BLOCK_LIST_MAX)
1094 return false;
1095
1096 for (i = 0; i < size; i++) {
1097 if (list[i] == cpu_to_le32(mcc))
1098 return true;
1099 }
1100
1101 list[size++] = cpu_to_le32(mcc);
1102 *le_size = cpu_to_le32(size);
1103 return true;
1104}
1105
28dd7ccd
MG
1106static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1107{
971cbe50 1108 u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG);
28dd7ccd 1109 int ret;
6da7ba3a
AB
1110 union iwl_tas_config_cmd cmd = {};
1111 int cmd_size, fw_ver;
28dd7ccd 1112
6da7ba3a 1113 BUILD_BUG_ON(ARRAY_SIZE(cmd.v3.block_list_array) <
28dd7ccd
MG
1114 APCI_WTAS_BLACK_LIST_MAX);
1115
1116 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1117 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1118 return;
1119 }
1120
971cbe50
JB
1121 fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
1122 IWL_FW_CMD_VER_UNKNOWN);
6da7ba3a
AB
1123
1124 ret = iwl_acpi_get_tas(&mvm->fwrt, &cmd, fw_ver);
28dd7ccd
MG
1125 if (ret < 0) {
1126 IWL_DEBUG_RADIO(mvm,
1127 "TAS table invalid or unavailable. (%d)\n",
1128 ret);
1129 return;
1130 }
1131
7c530588 1132 if (ret == 0)
28dd7ccd
MG
1133 return;
1134
c3f40c3e
MK
1135 if (!dmi_check_system(dmi_tas_approved_list)) {
1136 IWL_DEBUG_RADIO(mvm,
1137 "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
1138 dmi_get_system_info(DMI_SYS_VENDOR));
6da7ba3a
AB
1139 if ((!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1140 &cmd.v4.block_list_size,
1141 IWL_TAS_US_MCC)) ||
1142 (!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array,
1143 &cmd.v4.block_list_size,
1144 IWL_TAS_CANADA_MCC))) {
c3f40c3e
MK
1145 IWL_DEBUG_RADIO(mvm,
1146 "Unable to add US/Canada to TAS block list, disabling TAS\n");
1147 return;
1148 }
1149 }
1150
6da7ba3a
AB
1151 /* v4 is the same size as v3, so no need to differentiate here */
1152 cmd_size = fw_ver < 3 ?
7c530588
MK
1153 sizeof(struct iwl_tas_config_cmd_v2) :
1154 sizeof(struct iwl_tas_config_cmd_v3);
28dd7ccd 1155
971cbe50 1156 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd);
28dd7ccd
MG
1157 if (ret < 0)
1158 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1159}
f5b1cb2e 1160
4e8fe214
GG
1161static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1162{
1163 u8 value;
45fe1b6b 1164 int ret = iwl_acpi_get_dsm_u8(mvm->fwrt.dev, 0, DSM_RFI_FUNC_ENABLE,
4e8fe214
GG
1165 &iwl_rfi_guid, &value);
1166
1167 if (ret < 0) {
1168 IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
1169
1170 } else if (value >= DSM_VALUE_RFI_MAX) {
1171 IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n",
1172 value);
1173
1174 } else if (value == DSM_VALUE_RFI_ENABLE) {
1175 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
1176 return DSM_VALUE_RFI_ENABLE;
1177 }
1178
1179 IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n");
1180
1181 /* default behaviour is disabled */
1182 return DSM_VALUE_RFI_DISABLE;
1183}
1184
f5b1cb2e
GA
1185static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1186{
7119f02b
MK
1187 int ret;
1188 u32 value;
8f323d06 1189 struct iwl_lari_config_change_cmd_v6 cmd = {};
f5b1cb2e 1190
f21afaba 1191 cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt);
d2bfda8a 1192
45fe1b6b 1193 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_11AX_ENABLEMENT,
7119f02b
MK
1194 &iwl_guid, &value);
1195 if (!ret)
1196 cmd.oem_11ax_allow_bitmap = cpu_to_le32(value);
f5b1cb2e 1197
45fe1b6b 1198 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
54b4fda5
AN
1199 DSM_FUNC_ENABLE_UNII4_CHAN,
1200 &iwl_guid, &value);
1201 if (!ret)
1202 cmd.oem_unii4_allow_bitmap = cpu_to_le32(value);
1203
45fe1b6b 1204 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1f578d4f
MK
1205 DSM_FUNC_ACTIVATE_CHANNEL,
1206 &iwl_guid, &value);
1207 if (!ret)
1208 cmd.chan_state_active_bitmap = cpu_to_le32(value);
1209
698b166e
LC
1210 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1211 DSM_FUNC_ENABLE_6E,
1212 &iwl_guid, &value);
1213 if (!ret)
1214 cmd.oem_uhb_allow_bitmap = cpu_to_le32(value);
1215
8f323d06
AB
1216 ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0,
1217 DSM_FUNC_FORCE_DISABLE_CHANNELS,
1218 &iwl_guid, &value);
1219 if (!ret)
1220 cmd.force_disable_channels_bitmap = cpu_to_le32(value);
1221
54b4fda5 1222 if (cmd.config_bitmap ||
698b166e 1223 cmd.oem_uhb_allow_bitmap ||
54b4fda5 1224 cmd.oem_11ax_allow_bitmap ||
1f578d4f 1225 cmd.oem_unii4_allow_bitmap ||
8f323d06
AB
1226 cmd.chan_state_active_bitmap ||
1227 cmd.force_disable_channels_bitmap) {
3c21990b
MK
1228 size_t cmd_size;
1229 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw,
971cbe50
JB
1230 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1231 LARI_CONFIG_CHANGE),
1232 1);
8f323d06
AB
1233 switch (cmd_ver) {
1234 case 6:
1235 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v6);
1236 break;
1237 case 5:
1f578d4f 1238 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v5);
8f323d06
AB
1239 break;
1240 case 4:
54b4fda5 1241 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4);
8f323d06
AB
1242 break;
1243 case 3:
3c21990b 1244 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3);
8f323d06
AB
1245 break;
1246 case 2:
3c21990b 1247 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2);
8f323d06
AB
1248 break;
1249 default:
3c21990b 1250 cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1);
8f323d06
AB
1251 break;
1252 }
3c21990b 1253
3ce88247 1254 IWL_DEBUG_RADIO(mvm,
7119f02b
MK
1255 "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n",
1256 le32_to_cpu(cmd.config_bitmap),
1257 le32_to_cpu(cmd.oem_11ax_allow_bitmap));
54b4fda5 1258 IWL_DEBUG_RADIO(mvm,
1f578d4f 1259 "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, chan_state_active_bitmap=0x%x, cmd_ver=%d\n",
54b4fda5 1260 le32_to_cpu(cmd.oem_unii4_allow_bitmap),
1f578d4f 1261 le32_to_cpu(cmd.chan_state_active_bitmap),
54b4fda5 1262 cmd_ver);
698b166e 1263 IWL_DEBUG_RADIO(mvm,
8f323d06
AB
1264 "sending LARI_CONFIG_CHANGE, oem_uhb_allow_bitmap=0x%x, force_disable_channels_bitmap=0x%x\n",
1265 le32_to_cpu(cmd.oem_uhb_allow_bitmap),
1266 le32_to_cpu(cmd.force_disable_channels_bitmap));
7119f02b
MK
1267 ret = iwl_mvm_send_cmd_pdu(mvm,
1268 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1269 LARI_CONFIG_CHANGE),
1270 0, cmd_size, &cmd);
1271 if (ret < 0)
f5b1cb2e
GA
1272 IWL_DEBUG_RADIO(mvm,
1273 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
7119f02b 1274 ret);
f5b1cb2e
GA
1275 }
1276}
78a19d52
MK
1277
1278void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1279{
1280 int ret;
1281
1282 /* read PPAG table */
e8e10a37 1283 ret = iwl_acpi_get_ppag_table(&mvm->fwrt);
78a19d52
MK
1284 if (ret < 0) {
1285 IWL_DEBUG_RADIO(mvm,
1286 "PPAG BIOS table invalid or unavailable. (%d)\n",
1287 ret);
1288 }
1289
1290 /* read SAR tables */
1291 ret = iwl_sar_get_wrds_table(&mvm->fwrt);
1292 if (ret < 0) {
1293 IWL_DEBUG_RADIO(mvm,
1294 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1295 ret);
1296 /*
1297 * If not available, don't fail and don't bother with EWRD and
1298 * WGDS */
1299
1300 if (!iwl_sar_get_wgds_table(&mvm->fwrt)) {
1301 /*
1302 * If basic SAR is not available, we check for WGDS,
1303 * which should *not* be available either. If it is
1304 * available, issue an error, because we can't use SAR
1305 * Geo without basic SAR.
1306 */
1307 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1308 }
1309
1310 } else {
1311 ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
1312 /* if EWRD is not available, we can still use
1313 * WRDS, so don't fail */
1314 if (ret < 0)
1315 IWL_DEBUG_RADIO(mvm,
1316 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1317 ret);
1318
1319 /* read geo SAR table */
1320 if (iwl_sar_geo_support(&mvm->fwrt)) {
1321 ret = iwl_sar_get_wgds_table(&mvm->fwrt);
1322 if (ret < 0)
1323 IWL_DEBUG_RADIO(mvm,
1324 "Geo SAR BIOS table invalid or unavailable. (%d)\n",
1325 ret);
1326 /* we don't fail if the table is not available */
1327 }
1328 }
1329}
69964905 1330#else /* CONFIG_ACPI */
69964905 1331
39c1a972
IZ
1332inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
1333 int prof_a, int prof_b)
69964905 1334{
78a19d52 1335 return 1;
69964905 1336}
a6bff3cb 1337
39c1a972 1338inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
5d041c46
LC
1339{
1340 return -ENOENT;
1341}
1342
a6bff3cb
HD
1343static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1344{
1345 return 0;
1346}
18f1755d 1347
6ce1e5c0
GA
1348int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1349{
1350 return -ENOENT;
1351}
1352
1353static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1354{
7937fd32 1355 return 0;
6ce1e5c0 1356}
28dd7ccd
MG
1357
1358static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1359{
1360}
f5b1cb2e
GA
1361
1362static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1363{
1364}
4e8fe214
GG
1365
1366static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
1367{
1368 return DSM_VALUE_RFI_DISABLE;
1369}
78a19d52
MK
1370
1371void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
1372{
1373}
c593d2fa 1374
69964905
LC
1375#endif /* CONFIG_ACPI */
1376
f130bb75
MG
1377void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1378{
1379 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1380 int ret;
1381 u32 resp;
1382
1383 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1384 .flags = cpu_to_le32(flags),
1385 .buf_size = 0,
1386 };
1387 struct iwl_host_cmd host_cmd = {
1388 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1389 .flags = CMD_WANT_SKB,
1390 .data = {&recovery_cmd, },
1391 .len = {sizeof(recovery_cmd), },
1392 };
1393
1394 /* no error log was defined in TLV */
1395 if (!error_log_size)
1396 return;
1397
1398 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1399 /* no buf was allocated while HW reset */
1400 if (!mvm->error_recovery_buf)
1401 return;
1402
1403 host_cmd.data[1] = mvm->error_recovery_buf;
1404 host_cmd.len[1] = error_log_size;
1405 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1406 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1407 }
1408
1409 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1410 kfree(mvm->error_recovery_buf);
1411 mvm->error_recovery_buf = NULL;
1412
1413 if (ret) {
1414 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1415 return;
1416 }
1417
1418 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1419 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1420 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1421 if (resp)
1422 IWL_ERR(mvm,
1423 "Failed to send recovery cmd blob was invalid %d\n",
1424 resp);
1425 }
1426}
1427
42ce76d6
LC
1428static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1429{
1edd56e6 1430 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC
1431}
1432
1f370650 1433static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1434{
1f370650 1435 int ret;
8ca151b5 1436
7d6222e2 1437 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1438 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1439
3b25f1af 1440 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1441
f2082a53 1442 if (ret) {
8d193ca2 1443 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK
1444
1445 if (iwlmvm_mod_params.init_dbg)
1446 return 0;
1f370650 1447 return ret;
8d193ca2 1448 }
8ca151b5 1449
203c83d3 1450 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG
1451 iwl_trans_stop_device(mvm->trans);
1452 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1453 if (ret)
1f370650 1454 return ret;
8ca151b5 1455
94022562 1456 mvm->rfkill_safe_init_done = false;
8ca151b5 1457 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS
1458 if (ret)
1459 return ret;
1460
94022562
EG
1461 mvm->rfkill_safe_init_done = true;
1462
b108d8c7
SM
1463 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1464 NULL);
da2eb669 1465
702e975d 1466 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS
1467}
1468
1469int iwl_mvm_up(struct iwl_mvm *mvm)
1470{
1471 int ret, i;
1472 struct ieee80211_channel *chan;
1473 struct cfg80211_chan_def chandef;
dd36a507 1474 struct ieee80211_supported_band *sband = NULL;
733eb54f 1475 u32 sb_cfg;
1f370650
SS
1476
1477 lockdep_assert_held(&mvm->mutex);
1478
1479 ret = iwl_trans_start_hw(mvm->trans);
1480 if (ret)
1481 return ret;
733eb54f
AS
1482
1483 sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
b8133439
AS
1484 mvm->pldr_sync = !(sb_cfg & SB_CFG_RESIDES_IN_OTP_MASK);
1485 if (mvm->pldr_sync && iwl_mei_pldr_req())
274d9aa9 1486 return -EBUSY;
1f370650
SS
1487
1488 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB
1489 if (ret) {
1490 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
b8133439 1491 if (ret != -ERFKILL && !mvm->pldr_sync)
72d3c7bb
JB
1492 iwl_fw_dbg_error_collect(&mvm->fwrt,
1493 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB
1494 goto error;
1495 }
1496
b8133439
AS
1497 /* FW loaded successfully */
1498 mvm->pldr_sync = false;
1499
d0b813fc 1500 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1501
1f3b0ff8
LE
1502 ret = iwl_mvm_sf_update(mvm, NULL, false);
1503 if (ret)
1504 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1505
a1af4c48 1506 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS
1507 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1508 /* if we have a destination, assume EARLY START */
1509 if (mvm->fw->dbg.dest_tlv)
1510 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1511 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1512 }
6a951267 1513
a0544272 1514 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1515 if (ret)
1516 goto error;
1517
7d6222e2
JB
1518 if (!iwl_mvm_has_unified_ucode(mvm)) {
1519 /* Send phy db control command and then phy db calibration */
1f370650
SS
1520 ret = iwl_send_phy_db_data(mvm->phy_db);
1521 if (ret)
1522 goto error;
1f370650 1523 }
8ca151b5 1524
bb99ff9b
LC
1525 ret = iwl_send_phy_cfg_cmd(mvm);
1526 if (ret)
1527 goto error;
1528
b3de3ef4
EG
1529 ret = iwl_mvm_send_bt_init_conf(mvm);
1530 if (ret)
1531 goto error;
1532
cceb4507
SM
1533 if (fw_has_capa(&mvm->fw->ucode_capa,
1534 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1535 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM
1536 if (ret)
1537 goto error;
1538 }
1539
43413a97 1540 /* Init RSS configuration */
9cd243f2
MG
1541 ret = iwl_configure_rxq(&mvm->fwrt);
1542 if (ret)
1543 goto error;
8edbfaa1
SS
1544
1545 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS
1546 ret = iwl_send_rss_cfg_cmd(mvm);
1547 if (ret) {
1548 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1549 ret);
1550 goto error;
1551 }
1552 }
1553
8ca151b5 1554 /* init the fw <-> mac80211 STA mapping */
be9ae34e 1555 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++)
8ca151b5
JB
1556 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1557
0ae98812 1558 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1559
b2b7875b
JB
1560 /* reset quota debouncing buffer - 0xff will yield invalid data */
1561 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1562
79660869
IL
1563 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1564 ret = iwl_mvm_send_dqa_cmd(mvm);
1565 if (ret)
1566 goto error;
1567 }
97d5be7e 1568
2c2c3647
NE
1569 /*
1570 * Add auxiliary station for scanning.
1571 * Newer versions of this command implies that the fw uses
1572 * internal aux station for all aux activities that don't
1573 * requires a dedicated data queue.
1574 */
971cbe50 1575 if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
2c2c3647
NE
1576 /*
1577 * In old version the aux station uses mac id like other
1578 * station and not lmac id
1579 */
1580 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1581 if (ret)
1582 goto error;
1583 }
8ca151b5 1584
53a9d61e 1585 /* Add all the PHY contexts */
dd36a507
TM
1586 i = 0;
1587 while (!sband && i < NUM_NL80211_BANDS)
1588 sband = mvm->hw->wiphy->bands[i++];
1589
583d1833
DC
1590 if (WARN_ON_ONCE(!sband)) {
1591 ret = -ENODEV;
dd36a507 1592 goto error;
583d1833 1593 }
dd36a507
TM
1594
1595 chan = &sband->channels[0];
1596
53a9d61e
IP
1597 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1598 for (i = 0; i < NUM_PHY_CTX; i++) {
1599 /*
1600 * The channel used here isn't relevant as it's
1601 * going to be overwritten in the other flows.
1602 * For now use the first channel we have.
1603 */
1604 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1605 &chandef, 1, 1);
1606 if (ret)
1607 goto error;
1608 }
8ca151b5 1609
c221daf2
CRI
1610 if (iwl_mvm_is_tt_in_fw(mvm)) {
1611 /* in order to give the responsibility of ct-kill and
1612 * TX backoff to FW we need to send empty temperature reporting
1613 * cmd during init time
1614 */
1615 iwl_mvm_send_temp_report_ths_cmd(mvm);
1616 } else {
1617 /* Initialize tx backoffs to the minimal possible */
1618 iwl_mvm_tt_tx_backoff(mvm, 0);
1619 }
5c89e7bc 1620
242d9c8b 1621#ifdef CONFIG_THERMAL
5c89e7bc 1622 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI
1623
1624 /*
1625 * In case there is no budget from BIOS / Platform NVM the default
1626 * budget should be 2000mW (cooling state 0).
1627 */
1628 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI
1629 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1630 mvm->cooling_dev.cur_state);
75cfe338
LC
1631 if (ret)
1632 goto error;
1633 }
c221daf2 1634#endif
0c0e2c71 1635
aa43ae12
AM
1636 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1637 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1638
c1cb92fc 1639 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB
1640 if (ret)
1641 goto error;
1642
f5b1cb2e 1643 iwl_mvm_lari_cfg(mvm);
35af15d1
AN
1644 /*
1645 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1646 * anyway, so don't init MCC.
1647 */
1648 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1649 ret = iwl_mvm_init_mcc(mvm);
1650 if (ret)
1651 goto error;
1652 }
90d4f7db 1653
859d914c 1654 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1655 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1656 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS
1657 ret = iwl_mvm_config_scan(mvm);
1658 if (ret)
1659 goto error;
1660 }
1661
f130bb75
MG
1662 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1663 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
1664
48e775e6
HD
1665 if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
1666 IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
1667
6ce1e5c0
GA
1668 ret = iwl_mvm_ppag_init(mvm);
1669 if (ret)
1670 goto error;
1671
da2830ac 1672 ret = iwl_mvm_sar_init(mvm);
78a19d52 1673 if (ret == 0)
5d041c46 1674 ret = iwl_mvm_sar_geo_init(mvm);
5f06f6bf 1675 if (ret < 0)
a6bff3cb
HD
1676 goto error;
1677
c593d2fa
AB
1678 ret = iwl_mvm_sgom_init(mvm);
1679 if (ret)
1680 goto error;
1681
28dd7ccd 1682 iwl_mvm_tas_init(mvm);
7089ae63
JB
1683 iwl_mvm_leds_sync(mvm);
1684
b68bd2e3
IP
1685 iwl_mvm_ftm_initiator_smooth_config(mvm);
1686
4e8fe214
GG
1687 if (fw_has_capa(&mvm->fw->ucode_capa,
1688 IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) {
1689 if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE)
1690 iwl_rfi_send_config_cmd(mvm, NULL);
1691 }
1692
5aa7ce31
AS
1693 iwl_mvm_mei_device_state(mvm, true);
1694
53a9d61e 1695 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB
1696 return 0;
1697 error:
f4744258 1698 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1699 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1700 return ret;
1701}
1702
1703int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1704{
1705 int ret, i;
1706
1707 lockdep_assert_held(&mvm->mutex);
1708
1709 ret = iwl_trans_start_hw(mvm->trans);
1710 if (ret)
1711 return ret;
1712
1713 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1714 if (ret) {
1715 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1716 goto error;
1717 }
1718
a0544272 1719 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1720 if (ret)
1721 goto error;
1722
1723 /* Send phy db control command and then phy db calibration*/
1724 ret = iwl_send_phy_db_data(mvm->phy_db);
1725 if (ret)
1726 goto error;
1727
1728 ret = iwl_send_phy_cfg_cmd(mvm);
1729 if (ret)
1730 goto error;
1731
1732 /* init the fw <-> mac80211 STA mapping */
be9ae34e 1733 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++)
8ca151b5
JB
1734 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1735
971cbe50 1736 if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
2c2c3647
NE
1737 /*
1738 * Add auxiliary station for scanning.
1739 * Newer versions of this command implies that the fw uses
1740 * internal aux station for all aux activities that don't
1741 * requires a dedicated data queue.
1742 * In old version the aux station uses mac id like other
1743 * station and not lmac id
1744 */
1745 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1746 if (ret)
1747 goto error;
1748 }
8ca151b5
JB
1749
1750 return 0;
1751 error:
fcb6b92a 1752 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1753 return ret;
1754}
1755
0416841d
JB
1756void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1757 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI
1758{
1759 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1760 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1761
0c8d0a47
GBA
1762 IWL_DEBUG_INFO(mvm,
1763 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1764 le32_to_cpu(mfuart_notif->installed_ver),
1765 le32_to_cpu(mfuart_notif->external_ver),
1766 le32_to_cpu(mfuart_notif->status),
1767 le32_to_cpu(mfuart_notif->duration));
1768
19f63c53
GBA
1769 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1770 IWL_DEBUG_INFO(mvm,
0c8d0a47 1771 "MFUART: image size: 0x%08x\n",
19f63c53 1772 le32_to_cpu(mfuart_notif->image_size));
30269c12 1773}