Merge tag 's390-6.10-7' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8e99ea8d
JB
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
74f4cd71 3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
8e99ea8d
JB
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
8ca151b5 7#include <net/mac80211.h>
854d773e 8#include <linux/netdevice.h>
a2ac0f48 9#include <linux/dmi.h>
8ca151b5
JB
10
11#include "iwl-trans.h"
12#include "iwl-op-mode.h"
d962f9b1 13#include "fw/img.h"
8ca151b5 14#include "iwl-debug.h"
8c23f95c 15#include "iwl-prph.h"
813df5ce 16#include "fw/acpi.h"
b3e4c0f3 17#include "fw/pnvm.h"
4a9bb5b4 18#include "fw/uefi.h"
427661e4 19#include "fw/regulatory.h"
8ca151b5
JB
20
21#include "mvm.h"
7174beb6 22#include "fw/dbg.h"
8ca151b5 23#include "iwl-phy-db.h"
9c4f7d51
ST
24#include "iwl-modparams.h"
25#include "iwl-nvm-parse.h"
cf85123a 26#include "time-sync.h"
8ca151b5 27
abea0d06 28#define MVM_UCODE_ALIVE_TIMEOUT (2 * HZ)
b3e4c0f3 29#define MVM_UCODE_CALIB_TIMEOUT (2 * HZ)
8ca151b5 30
4a9bb5b4
MS
31#define IWL_UATS_VLP_AP_SUPPORTED BIT(29)
32#define IWL_UATS_AFC_AP_SUPPORTED BIT(30)
33
8ca151b5
JB
34struct iwl_mvm_alive_data {
35 bool valid;
36 u32 scd_base_addr;
37};
38
8ca151b5
JB
39static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
40{
41 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
42 .valid = cpu_to_le32(valid_tx_ant),
43 };
44
33223542 45 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 46 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB
47 sizeof(tx_ant_cmd), &tx_ant_cmd);
48}
49
43413a97
SS
50static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
51{
52 int i;
53 struct iwl_rss_config_cmd cmd = {
54 .flags = cpu_to_le32(IWL_RSS_ENABLE),
608dce95
SS
55 .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
56 BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
57 BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
58 BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
59 BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
60 BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
43413a97
SS
61 };
62
f43495fd
SS
63 if (mvm->trans->num_rx_queues == 1)
64 return 0;
65
854d773e 66 /* Do not direct RSS traffic to Q 0 which is our fallback queue */
43413a97 67 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
854d773e
SS
68 cmd.indirection_table[i] =
69 1 + (i % (mvm->trans->num_rx_queues - 1));
70 netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
43413a97
SS
71
72 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
73}
74
97d5be7e
LK
75static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
76{
77 struct iwl_dqa_enable_cmd dqa_cmd = {
78 .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
79 };
f0c86427 80 u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD);
97d5be7e
LK
81 int ret;
82
83 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
84 if (ret)
85 IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
86 else
87 IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
88
89 return ret;
90}
91
bdccdb85
GBA
92void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
93 struct iwl_rx_cmd_buffer *rxb)
94{
95 struct iwl_rx_packet *pkt = rxb_addr(rxb);
96 struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
bdccdb85
GBA
97
98 if (mfu_dump_notif->index_num == 0)
99 IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
100 le32_to_cpu(mfu_dump_notif->assert_id));
bdccdb85
GBA
101}
102
8ca151b5
JB
103static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
104 struct iwl_rx_packet *pkt, void *data)
105{
fd1c3318 106 unsigned int pkt_len = iwl_rx_packet_payload_len(pkt);
8ca151b5
JB
107 struct iwl_mvm *mvm =
108 container_of(notif_wait, struct iwl_mvm, notif_wait);
109 struct iwl_mvm_alive_data *alive_data = data;
5c228d63
SS
110 struct iwl_umac_alive *umac;
111 struct iwl_lmac_alive *lmac1;
112 struct iwl_lmac_alive *lmac2 = NULL;
113 u16 status;
cfa5d0ca 114 u32 lmac_error_event_table, umac_error_table;
708d8c53
JB
115 u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
116 UCODE_ALIVE_NTFY, 0);
5053a451 117 u32 i;
b2f20cf2 118
01a9ca51 119
c0941ace
MS
120 if (version == 6) {
121 struct iwl_alive_ntf_v6 *palive;
122
123 if (pkt_len < sizeof(*palive))
124 return false;
125
126 palive = (void *)pkt->data;
127 mvm->trans->dbg.imr_data.imr_enable =
128 le32_to_cpu(palive->imr.enabled);
129 mvm->trans->dbg.imr_data.imr_size =
130 le32_to_cpu(palive->imr.size);
131 mvm->trans->dbg.imr_data.imr2sram_remainbyte =
132 mvm->trans->dbg.imr_data.imr_size;
133 mvm->trans->dbg.imr_data.imr_base_addr =
134 palive->imr.base_addr;
135 mvm->trans->dbg.imr_data.imr_curr_addr =
136 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr);
137 IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n",
138 mvm->trans->dbg.imr_data.imr_enable,
139 mvm->trans->dbg.imr_data.imr_size,
140 le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr));
5053a451
MS
141
142 if (!mvm->trans->dbg.imr_data.imr_enable) {
143 for (i = 0; i < ARRAY_SIZE(mvm->trans->dbg.active_regions); i++) {
144 struct iwl_ucode_tlv *reg_tlv;
145 struct iwl_fw_ini_region_tlv *reg;
146
147 reg_tlv = mvm->trans->dbg.active_regions[i];
148 if (!reg_tlv)
149 continue;
150
151 reg = (void *)reg_tlv->data;
152 /*
153 * We have only one DRAM IMR region, so we
154 * can break as soon as we find the first
155 * one.
156 */
157 if (reg->type == IWL_FW_INI_REGION_DRAM_IMR) {
158 mvm->trans->dbg.unsupported_region_msk |= BIT(i);
159 break;
160 }
161 }
162 }
c0941ace
MS
163 }
164
165 if (version >= 5) {
90824f2f
LC
166 struct iwl_alive_ntf_v5 *palive;
167
fd1c3318
JB
168 if (pkt_len < sizeof(*palive))
169 return false;
170
90824f2f
LC
171 palive = (void *)pkt->data;
172 umac = &palive->umac_data;
173 lmac1 = &palive->lmac_data[0];
174 lmac2 = &palive->lmac_data[1];
175 status = le16_to_cpu(palive->status);
176
177 mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]);
178 mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]);
179 mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]);
180
181 IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n",
182 mvm->trans->sku_id[0],
183 mvm->trans->sku_id[1],
184 mvm->trans->sku_id[2]);
185 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) {
9422b978
LC
186 struct iwl_alive_ntf_v4 *palive;
187
fd1c3318
JB
188 if (pkt_len < sizeof(*palive))
189 return false;
190
5c228d63
SS
191 palive = (void *)pkt->data;
192 umac = &palive->umac_data;
193 lmac1 = &palive->lmac_data[0];
194 lmac2 = &palive->lmac_data[1];
195 status = le16_to_cpu(palive->status);
9422b978
LC
196 } else if (iwl_rx_packet_payload_len(pkt) ==
197 sizeof(struct iwl_alive_ntf_v3)) {
198 struct iwl_alive_ntf_v3 *palive3;
199
fd1c3318
JB
200 if (pkt_len < sizeof(*palive3))
201 return false;
202
5c228d63
SS
203 palive3 = (void *)pkt->data;
204 umac = &palive3->umac_data;
205 lmac1 = &palive3->lmac_data;
206 status = le16_to_cpu(palive3->status);
9422b978
LC
207 } else {
208 WARN(1, "unsupported alive notification (size %d)\n",
209 iwl_rx_packet_payload_len(pkt));
210 /* get timeout later */
211 return false;
5c228d63 212 }
01a9ca51 213
22463857
SM
214 lmac_error_event_table =
215 le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
216 iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
217
5c228d63 218 if (lmac2)
91c28b83 219 mvm->trans->dbg.lmac_error_event_table[1] =
22463857 220 le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
ffa70264 221
4f7411d6
RG
222 umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
223 ~FW_ADDR_CACHE_CONTROL;
cfa5d0ca
MG
224
225 if (umac_error_table) {
226 if (umac_error_table >=
834f920e 227 mvm->trans->cfg->min_umac_error_event_table) {
cfa5d0ca
MG
228 iwl_fw_umac_set_alive_err_table(mvm->trans,
229 umac_error_table);
230 } else {
231 IWL_ERR(mvm,
232 "Not valid error log pointer 0x%08X for %s uCode\n",
233 umac_error_table,
234 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
235 "Init" : "RT");
236 }
3485e76e 237 }
fb5b2846 238
22463857 239 alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
5c228d63 240 alive_data->valid = status == IWL_ALIVE_STATUS_OK;
7e1223b5 241
5c228d63
SS
242 IWL_DEBUG_FW(mvm,
243 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
244 status, lmac1->ver_type, lmac1->ver_subtype);
7e1223b5 245
5c228d63
SS
246 if (lmac2)
247 IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
7e1223b5 248
5c228d63
SS
249 IWL_DEBUG_FW(mvm,
250 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
251 le32_to_cpu(umac->umac_major),
252 le32_to_cpu(umac->umac_minor));
8ca151b5 253
0a3a3e9e
SM
254 iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
255
8ca151b5
JB
256 return true;
257}
258
1f370650
SS
259static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
260 struct iwl_rx_packet *pkt, void *data)
261{
262 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
263
264 return true;
265}
266
8ca151b5
JB
267static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
268 struct iwl_rx_packet *pkt, void *data)
269{
270 struct iwl_phy_db *phy_db = data;
271
272 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
273 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
274 return true;
275 }
276
ce1f2778 277 WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
8ca151b5
JB
278
279 return false;
280}
281
a7de31d5
MG
282static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
283{
184f10db
MG
284#define IWL_FW_PRINT_REG_INFO(reg_name) \
285 IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
286
a7de31d5
MG
287 struct iwl_trans *trans = mvm->trans;
288 enum iwl_device_family device_family = trans->trans_cfg->device_family;
289
290 if (device_family < IWL_DEVICE_FAMILY_8000)
291 return;
292
293 if (device_family <= IWL_DEVICE_FAMILY_9000)
184f10db 294 IWL_FW_PRINT_REG_INFO(WFPM_ARC1_PD_NOTIFICATION);
a7de31d5 295 else
184f10db 296 IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);
f2f17ca0 297
184f10db 298 IWL_FW_PRINT_REG_INFO(HPM_SECONDARY_DEVICE_STATE);
f2f17ca0 299
184f10db
MG
300 /* print OPT info */
301 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_ADDR);
302 IWL_FW_PRINT_REG_INFO(WFPM_MAC_OTP_CFG7_DATA);
a7de31d5
MG
303}
304
8ca151b5
JB
305static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
306 enum iwl_ucode_type ucode_type)
307{
308 struct iwl_notification_wait alive_wait;
94a8d87c 309 struct iwl_mvm_alive_data alive_data = {};
8ca151b5 310 const struct fw_img *fw;
cfbc6c4c 311 int ret;
702e975d 312 enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
9422b978 313 static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY };
b3500b47
EG
314 bool run_in_rfkill =
315 ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
5e31b3df
MS
316 u8 count;
317 struct iwl_pc_data *pc_data;
8ca151b5 318
61df750c 319 if (ucode_type == IWL_UCODE_REGULAR &&
3d2d4422
GBA
320 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
321 !(fw_has_capa(&mvm->fw->ucode_capa,
322 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
612da1ef 323 fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
61df750c 324 else
612da1ef 325 fw = iwl_get_ucode_image(mvm->fw, ucode_type);
befe9b6f 326 if (WARN_ON(!fw))
8ca151b5 327 return -EINVAL;
702e975d 328 iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
65b280fe 329 clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
8ca151b5
JB
330
331 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
332 alive_cmd, ARRAY_SIZE(alive_cmd),
333 iwl_alive_fn, &alive_data);
334
b3500b47
EG
335 /*
336 * We want to load the INIT firmware even in RFKILL
337 * For the unified firmware case, the ucode_type is not
338 * INIT, but we still need to run it.
339 */
340 ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
8ca151b5 341 if (ret) {
702e975d 342 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
343 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
344 return ret;
345 }
346
347 /*
348 * Some things may run in the background now, but we
349 * just wait for the ALIVE notification here.
350 */
351 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
352 MVM_UCODE_ALIVE_TIMEOUT);
56731878
DG
353
354 if (mvm->trans->trans_cfg->device_family ==
355 IWL_DEVICE_FAMILY_AX210) {
356 /* print these registers regardless of alive fail/success */
357 IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n",
358 iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
359 IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n",
360 iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
361 IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n",
362 iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
b8133439
AS
363 IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n",
364 iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
56731878
DG
365 }
366
8ca151b5 367 if (ret) {
d6be9c1d
SS
368 struct iwl_trans *trans = mvm->trans;
369
5667ccc2 370 /* SecBoot info */
20f5aef5
JB
371 if (trans->trans_cfg->device_family >=
372 IWL_DEVICE_FAMILY_22000) {
d6be9c1d
SS
373 IWL_ERR(mvm,
374 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
ea695b7c
ST
375 iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
376 iwl_read_umac_prph(trans,
377 UMAG_SB_CPU_2_STATUS));
5667ccc2
MG
378 } else if (trans->trans_cfg->device_family >=
379 IWL_DEVICE_FAMILY_8000) {
380 IWL_ERR(mvm,
381 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
382 iwl_read_prph(trans, SB_CPU_1_STATUS),
383 iwl_read_prph(trans, SB_CPU_2_STATUS));
384 }
385
a7de31d5
MG
386 iwl_mvm_print_pd_notification(mvm);
387
5667ccc2
MG
388 /* LMAC/UMAC PC info */
389 if (trans->trans_cfg->device_family >=
5e31b3df
MS
390 IWL_DEVICE_FAMILY_22000) {
391 pc_data = trans->dbg.pc_data;
392 for (count = 0; count < trans->dbg.num_pc;
393 count++, pc_data++)
394 IWL_ERR(mvm, "%s: 0x%x\n",
395 pc_data->pc_name,
396 pc_data->pc_address);
397 } else if (trans->trans_cfg->device_family >=
5667ccc2 398 IWL_DEVICE_FAMILY_9000) {
20f5aef5
JB
399 IWL_ERR(mvm, "UMAC PC: 0x%x\n",
400 iwl_read_umac_prph(trans,
401 UREG_UMAC_CURRENT_PC));
402 IWL_ERR(mvm, "LMAC PC: 0x%x\n",
403 iwl_read_umac_prph(trans,
404 UREG_LMAC1_CURRENT_PC));
405 if (iwl_mvm_is_cdb_supported(mvm))
406 IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
407 iwl_read_umac_prph(trans,
408 UREG_LMAC2_CURRENT_PC));
20f5aef5
JB
409 }
410
b8133439 411 if (ret == -ETIMEDOUT && !mvm->pldr_sync)
20f5aef5
JB
412 iwl_fw_dbg_error_collect(&mvm->fwrt,
413 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
414
702e975d 415 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
416 return ret;
417 }
418
419 if (!alive_data.valid) {
420 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
702e975d 421 iwl_fw_set_current_image(&mvm->fwrt, old_type);
8ca151b5
JB
422 return -EIO;
423 }
424
f31f7cd9
GG
425 /* if reached this point, Alive notification was received */
426 iwl_mei_alive_notif(true);
733eb54f 427
33182810
AG
428 ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait,
429 &mvm->fw->ucode_capa);
70d3ca86
LC
430 if (ret) {
431 IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
432 iwl_fw_set_current_image(&mvm->fwrt, old_type);
433 return ret;
434 }
435
8ca151b5
JB
436 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
437
438 /*
439 * Note: all the queues are enabled as part of the interface
440 * initialization, but in firmware restart scenarios they
441 * could be stopped, so wake them up. In firmware restart,
442 * mac80211 will have the queues stopped as well until the
443 * reconfiguration completes. During normal startup, they
444 * will be empty.
445 */
446
4ecafae9 447 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
1c14089e
JB
448 /*
449 * Set a 'fake' TID for the command queue, since we use the
450 * hweight() of the tid_bitmap as a refcount now. Not that
451 * we ever even consider the command queue as one we might
452 * want to reuse, but be safe nevertheless.
453 */
454 mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
455 BIT(IWL_MAX_TID_COUNT + 2);
8ca151b5 456
65b280fe 457 set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
f7805b33
LC
458#ifdef CONFIG_IWLWIFI_DEBUGFS
459 iwl_fw_set_dbg_rec_on(&mvm->fwrt);
460#endif
8ca151b5 461
d3d9b4fc
EG
462 /*
463 * All the BSSes in the BSS table include the GP2 in the system
464 * at the beacon Rx time, this is of course no longer relevant
465 * since we are resetting the firmware.
466 * Purge all the BSS table.
467 */
468 cfg80211_bss_flush(mvm->hw->wiphy);
469
8ca151b5
JB
470 return 0;
471}
8ca151b5 472
c4ace426
GA
473static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
474 struct iwl_phy_specific_cfg *phy_filters)
475{
c4c95454
JB
476#ifdef CONFIG_ACPI
477 *phy_filters = mvm->phy_filters;
c4ace426 478#endif /* CONFIG_ACPI */
c4c95454 479}
c4ace426 480
4a9bb5b4
MS
481static void iwl_mvm_uats_init(struct iwl_mvm *mvm)
482{
483 u8 cmd_ver;
484 int ret;
485 struct iwl_host_cmd cmd = {
486 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
2848df96 487 MCC_ALLOWED_AP_TYPE_CMD),
4a9bb5b4
MS
488 .flags = 0,
489 .data[0] = &mvm->fwrt.uats_table,
490 .len[0] = sizeof(mvm->fwrt.uats_table),
491 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
492 };
493
494 if (!(mvm->trans->trans_cfg->device_family >=
495 IWL_DEVICE_FAMILY_AX210)) {
496 IWL_DEBUG_RADIO(mvm, "UATS feature is not supported\n");
497 return;
498 }
499
500 if (!mvm->fwrt.uats_enabled) {
501 IWL_DEBUG_RADIO(mvm, "UATS feature is disabled\n");
502 return;
503 }
504
505 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
506 IWL_FW_CMD_VER_UNKNOWN);
507 if (cmd_ver != 1) {
508 IWL_DEBUG_RADIO(mvm,
2848df96 509 "MCC_ALLOWED_AP_TYPE_CMD ver %d not supported\n",
4a9bb5b4
MS
510 cmd_ver);
511 return;
512 }
513
514 ret = iwl_uefi_get_uats_table(mvm->trans, &mvm->fwrt);
515 if (ret < 0) {
516 IWL_ERR(mvm, "failed to read UATS table (%d)\n", ret);
517 return;
518 }
519
520 ret = iwl_mvm_send_cmd(mvm, &cmd);
521 if (ret < 0)
2848df96
JB
522 IWL_ERR(mvm, "failed to send MCC_ALLOWED_AP_TYPE_CMD (%d)\n",
523 ret);
4a9bb5b4 524 else
2848df96 525 IWL_DEBUG_RADIO(mvm, "MCC_ALLOWED_AP_TYPE_CMD sent to FW\n");
4a9bb5b4
MS
526}
527
c593d2fa
AB
528static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
529{
530 u8 cmd_ver;
531 int ret;
532 struct iwl_host_cmd cmd = {
533 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP,
534 SAR_OFFSET_MAPPING_TABLE_CMD),
535 .flags = 0,
536 .data[0] = &mvm->fwrt.sgom_table,
537 .len[0] = sizeof(mvm->fwrt.sgom_table),
538 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
539 };
540
541 if (!mvm->fwrt.sgom_enabled) {
542 IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n");
543 return 0;
544 }
545
971cbe50 546 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
c593d2fa
AB
547 IWL_FW_CMD_VER_UNKNOWN);
548
549 if (cmd_ver != 2) {
550 IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n",
551 cmd_ver);
552 return 0;
553 }
554
555 ret = iwl_mvm_send_cmd(mvm, &cmd);
556 if (ret < 0)
557 IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret);
558
559 return ret;
560}
c593d2fa 561
8ca151b5
JB
562static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
563{
971cbe50 564 u32 cmd_id = PHY_CONFIGURATION_CMD;
c4ace426 565 struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
702e975d 566 enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
c4ace426
GA
567 u8 cmd_ver;
568 size_t cmd_size;
8ca151b5 569
bb99ff9b 570 if (iwl_mvm_has_unified_ucode(mvm) &&
d923b020 571 !mvm->trans->cfg->tx_with_siso_diversity)
bb99ff9b 572 return 0;
d923b020
LC
573
574 if (mvm->trans->cfg->tx_with_siso_diversity) {
bb99ff9b
LC
575 /*
576 * TODO: currently we don't set the antenna but letting the NIC
577 * to decide which antenna to use. This should come from BIOS.
578 */
579 phy_cfg_cmd.phy_cfg =
580 cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
581 }
582
8ca151b5 583 /* Set parameters */
a0544272 584 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
86a2b204
LC
585
586 /* set flags extra PHY configuration flags from the device's cfg */
7897dfa2
LC
587 phy_cfg_cmd.phy_cfg |=
588 cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
86a2b204 589
8ca151b5
JB
590 phy_cfg_cmd.calib_control.event_trigger =
591 mvm->fw->default_calib[ucode_type].event_trigger;
592 phy_cfg_cmd.calib_control.flow_trigger =
593 mvm->fw->default_calib[ucode_type].flow_trigger;
594
971cbe50 595 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 596 IWL_FW_CMD_VER_UNKNOWN);
c4c95454
JB
597 if (cmd_ver >= 3)
598 iwl_mvm_phy_filter_init(mvm, &phy_cfg_cmd.phy_specific_cfg);
c4ace426 599
8ca151b5
JB
600 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
601 phy_cfg_cmd.phy_cfg);
c4ace426
GA
602 cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
603 sizeof(struct iwl_phy_cfg_cmd_v1);
971cbe50 604 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd);
8ca151b5
JB
605}
606
e305a408
MS
607static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
608{
609 struct iwl_notification_wait init_wait;
610 struct iwl_nvm_access_complete_cmd nvm_complete = {};
611 struct iwl_init_extended_cfg_cmd init_cfg = {
612 .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
613 };
614 static const u16 init_complete[] = {
615 INIT_COMPLETE_NOTIF,
616 };
bdd94061 617 u32 sb_cfg;
e305a408
MS
618 int ret;
619
620 if (mvm->trans->cfg->tx_with_siso_diversity)
621 init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
622
623 lockdep_assert_held(&mvm->mutex);
624
625 mvm->rfkill_safe_init_done = false;
626
a856ce66
JB
627 if (mvm->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
628 sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
629 /* if needed, we'll reset this on our way out later */
3277baa9 630 mvm->pldr_sync = sb_cfg == SB_CFG_RESIDES_IN_ROM;
a856ce66
JB
631 if (mvm->pldr_sync && iwl_mei_pldr_req())
632 return -EBUSY;
633 }
bdd94061 634
e305a408
MS
635 iwl_init_notification_wait(&mvm->notif_wait,
636 &init_wait,
637 init_complete,
638 ARRAY_SIZE(init_complete),
639 iwl_wait_init_complete,
640 NULL);
641
642 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
643
644 /* Will also start the device */
645 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
646 if (ret) {
647 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
bdd94061
JB
648
649 /* if we needed reset then fail here, but notify and remove */
650 if (mvm->pldr_sync) {
651 iwl_mei_alive_notif(false);
652 iwl_trans_pcie_remove(mvm->trans, true);
653 }
654
e305a408
MS
655 goto error;
656 }
657 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
658 NULL);
659
554fa711 660 if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
de0c2cdc
JB
661 mvm->trans->step_urm = !!(iwl_read_umac_prph(mvm->trans,
662 CNVI_PMU_STEP_FLOW) &
663 CNVI_PMU_STEP_FLOW_FORCE_URM);
664
e305a408
MS
665 /* Send init config command to mark that we are sending NVM access
666 * commands
667 */
668 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
669 INIT_EXTENDED_CFG_CMD),
670 CMD_SEND_IN_RFKILL,
671 sizeof(init_cfg), &init_cfg);
672 if (ret) {
673 IWL_ERR(mvm, "Failed to run init config command: %d\n",
674 ret);
675 goto error;
676 }
677
678 /* Load NVM to NIC if needed */
679 if (mvm->nvm_file_name) {
680 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
681 mvm->nvm_sections);
682 if (ret)
683 goto error;
684 ret = iwl_mvm_load_nvm_to_nic(mvm);
685 if (ret)
686 goto error;
687 }
688
689 if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
690 ret = iwl_nvm_init(mvm);
691 if (ret) {
692 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
693 goto error;
694 }
695 }
696
697 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
698 NVM_ACCESS_COMPLETE),
699 CMD_SEND_IN_RFKILL,
700 sizeof(nvm_complete), &nvm_complete);
701 if (ret) {
702 IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
703 ret);
704 goto error;
705 }
706
d2ccc5c1
MS
707 ret = iwl_send_phy_cfg_cmd(mvm);
708 if (ret) {
709 IWL_ERR(mvm, "Failed to run PHY configuration: %d\n",
710 ret);
711 goto error;
712 }
713
e305a408
MS
714 /* We wait for the INIT complete notification */
715 ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
716 MVM_UCODE_ALIVE_TIMEOUT);
717 if (ret)
718 return ret;
719
720 /* Read the NVM only at driver load time, no need to do this twice */
721 if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
4ea1ed1d
EG
722 mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw,
723 mvm->set_tx_ant, mvm->set_rx_ant);
e305a408
MS
724 if (IS_ERR(mvm->nvm_data)) {
725 ret = PTR_ERR(mvm->nvm_data);
726 mvm->nvm_data = NULL;
727 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
728 return ret;
729 }
730 }
731
732 mvm->rfkill_safe_init_done = true;
733
734 return 0;
735
736error:
737 iwl_remove_notification(&mvm->notif_wait, &init_wait);
738 return ret;
739}
740
3b25f1af 741int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
8ca151b5
JB
742{
743 struct iwl_notification_wait calib_wait;
6eb031d2 744 static const u16 init_complete[] = {
8ca151b5
JB
745 INIT_COMPLETE_NOTIF,
746 CALIB_RES_NOTIF_PHY_DB
747 };
748 int ret;
749
7d6222e2 750 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 751 return iwl_run_unified_mvm_ucode(mvm);
8c5f47b1 752
8ca151b5
JB
753 lockdep_assert_held(&mvm->mutex);
754
94022562 755 mvm->rfkill_safe_init_done = false;
8ca151b5
JB
756
757 iwl_init_notification_wait(&mvm->notif_wait,
758 &calib_wait,
759 init_complete,
760 ARRAY_SIZE(init_complete),
761 iwl_wait_phy_db_entry,
762 mvm->phy_db);
763
11f8c533
LC
764 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
765
8ca151b5
JB
766 /* Will also start the device */
767 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
768 if (ret) {
769 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
00e0c6c8 770 goto remove_notif;
8ca151b5
JB
771 }
772
7d34a7d7 773 if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
b3de3ef4
EG
774 ret = iwl_mvm_send_bt_init_conf(mvm);
775 if (ret)
00e0c6c8 776 goto remove_notif;
b3de3ef4 777 }
931d4160 778
81a67e32 779 /* Read the NVM only at driver load time, no need to do this twice */
3b25f1af 780 if (!mvm->nvm_data) {
5bd1d2c1 781 ret = iwl_nvm_init(mvm);
8ca151b5
JB
782 if (ret) {
783 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
00e0c6c8 784 goto remove_notif;
8ca151b5
JB
785 }
786 }
787
81a67e32 788 /* In case we read the NVM from external file, load it to the NIC */
9ce505fe
AN
789 if (mvm->nvm_file_name) {
790 ret = iwl_mvm_load_nvm_to_nic(mvm);
791 if (ret)
792 goto remove_notif;
793 }
81a67e32 794
64866e5d
LC
795 WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
796 "Too old NVM version (0x%0x, required = 0x%0x)",
797 mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
8ca151b5 798
4f59334b
EH
799 /*
800 * abort after reading the nvm in case RF Kill is on, we will complete
801 * the init seq later when RF kill will switch to off
802 */
1a3fe0b2 803 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH
804 IWL_DEBUG_RF_KILL(mvm,
805 "jump over all phy activities due to RF kill\n");
00e0c6c8 806 goto remove_notif;
4f59334b
EH
807 }
808
b3500b47 809 mvm->rfkill_safe_init_done = true;
31b8b343 810
e07cbb53 811 /* Send TX valid antennas before triggering calibrations */
a0544272 812 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53 813 if (ret)
00e0c6c8 814 goto remove_notif;
e07cbb53 815
8ca151b5
JB
816 ret = iwl_send_phy_cfg_cmd(mvm);
817 if (ret) {
818 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
819 ret);
00e0c6c8 820 goto remove_notif;
8ca151b5
JB
821 }
822
823 /*
824 * Some things may run in the background now, but we
825 * just wait for the calibration complete notification.
826 */
827 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
00e0c6c8
LC
828 MVM_UCODE_CALIB_TIMEOUT);
829 if (!ret)
830 goto out;
31b8b343 831
00e0c6c8 832 if (iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343 833 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
00e0c6c8
LC
834 ret = 0;
835 } else {
836 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
837 ret);
31b8b343 838 }
00e0c6c8 839
8ca151b5
JB
840 goto out;
841
00e0c6c8 842remove_notif:
8ca151b5
JB
843 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
844out:
b3500b47 845 mvm->rfkill_safe_init_done = false;
a4082843 846 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB
847 /* we want to debug INIT and we have no NVM - fake */
848 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
849 sizeof(struct ieee80211_channel) +
850 sizeof(struct ieee80211_rate),
851 GFP_KERNEL);
852 if (!mvm->nvm_data)
853 return -ENOMEM;
8ca151b5
JB
854 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
855 mvm->nvm_data->bands[0].n_channels = 1;
856 mvm->nvm_data->bands[0].n_bitrates = 1;
857 mvm->nvm_data->bands[0].bitrates =
8ba438ef 858 (void *)(mvm->nvm_data->channels + 1);
8ca151b5
JB
859 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
860 }
861
862 return ret;
863}
864
84bfffa9
EG
865static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
866{
867 struct iwl_ltr_config_cmd cmd = {
868 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
869 };
870
871 if (!mvm->trans->ltr_enabled)
872 return 0;
873
84bfffa9
EG
874 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
875 sizeof(cmd), &cmd);
876}
877
42ce76d6 878int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
da2830ac 879{
971cbe50 880 u32 cmd_id = REDUCE_TX_POWER_CMD;
216cdfb5
LC
881 struct iwl_dev_tx_power_cmd cmd = {
882 .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
71e9378b 883 };
9c08cef8 884 __le16 *per_chain;
1edd56e6 885 int ret;
39c1a972 886 u16 len = 0;
fbb7957d 887 u32 n_subbands;
788e4c75
EG
888 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id, 3);
889
8f892e22 890 if (cmd_ver >= 7) {
b0aa02b3
AB
891 len = sizeof(cmd.v7);
892 n_subbands = IWL_NUM_SUB_BANDS_V2;
893 per_chain = cmd.v7.per_chain[0][0];
894 cmd.v7.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags);
8f892e22
EG
895 if (cmd_ver == 8)
896 len = sizeof(cmd.v8);
b0aa02b3 897 } else if (cmd_ver == 6) {
fbb7957d
LC
898 len = sizeof(cmd.v6);
899 n_subbands = IWL_NUM_SUB_BANDS_V2;
900 per_chain = cmd.v6.per_chain[0][0];
901 } else if (fw_has_api(&mvm->fw->ucode_capa,
902 IWL_UCODE_TLV_API_REDUCE_TX_POWER)) {
0791c2fc 903 len = sizeof(cmd.v5);
e12cfc7b 904 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
905 per_chain = cmd.v5.per_chain[0][0];
906 } else if (fw_has_capa(&mvm->fw->ucode_capa,
fbb7957d 907 IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) {
216cdfb5 908 len = sizeof(cmd.v4);
e12cfc7b 909 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
910 per_chain = cmd.v4.per_chain[0][0];
911 } else {
216cdfb5 912 len = sizeof(cmd.v3);
e12cfc7b 913 n_subbands = IWL_NUM_SUB_BANDS_V1;
9c08cef8
LC
914 per_chain = cmd.v3.per_chain[0][0];
915 }
55bfa4b9 916
216cdfb5
LC
917 /* all structs have the same common part, add it */
918 len += sizeof(cmd.common);
da2830ac 919
2594e4d9
MK
920 ret = iwl_sar_fill_profile(&mvm->fwrt, per_chain,
921 IWL_NUM_CHAIN_TABLES,
922 n_subbands, prof_a, prof_b);
1edd56e6
LC
923
924 /* return on error or if the profile is disabled (positive number) */
925 if (ret)
926 return ret;
927
6d19a5eb
EG
928 iwl_mei_set_power_limit(per_chain);
929
42ce76d6 930 IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
971cbe50 931 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
42ce76d6
LC
932}
933
7fe90e0e
HD
934int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
935{
dd2a1256 936 union iwl_geo_tx_power_profiles_cmd geo_tx_cmd;
f604324e 937 struct iwl_geo_tx_power_profiles_resp *resp;
0c3d7282 938 u16 len;
39c1a972 939 int ret;
c8611331
JB
940 struct iwl_host_cmd cmd = {
941 .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD),
942 .flags = CMD_WANT_SKB,
943 .data = { &geo_tx_cmd },
944 };
971cbe50 945 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id,
e80bfd11 946 IWL_FW_CMD_VER_UNKNOWN);
0c3d7282 947
dd2a1256
LC
948 /* the ops field is at the same spot for all versions, so set in v1 */
949 geo_tx_cmd.v1.ops =
950 cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
951
97f8a3d1
AB
952 if (cmd_ver == 5)
953 len = sizeof(geo_tx_cmd.v5);
954 else if (cmd_ver == 4)
955 len = sizeof(geo_tx_cmd.v4);
956 else if (cmd_ver == 3)
0ea788ed
LC
957 len = sizeof(geo_tx_cmd.v3);
958 else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
959 IWL_UCODE_TLV_API_SAR_TABLE_VER))
dd2a1256
LC
960 len = sizeof(geo_tx_cmd.v2);
961 else
962 len = sizeof(geo_tx_cmd.v1);
7fe90e0e 963
39c1a972
IZ
964 if (!iwl_sar_geo_support(&mvm->fwrt))
965 return -EOPNOTSUPP;
966
c8611331 967 cmd.len[0] = len;
7fe90e0e
HD
968
969 ret = iwl_mvm_send_cmd(mvm, &cmd);
970 if (ret) {
971 IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
972 return ret;
973 }
f604324e
LC
974
975 resp = (void *)cmd.resp_pkt->data;
976 ret = le32_to_cpu(resp->profile_idx);
977
2594e4d9 978 if (WARN_ON(ret > BIOS_GEO_MAX_PROFILE_NUM))
f604324e
LC
979 ret = -EIO;
980
7fe90e0e
HD
981 iwl_free_resp(&cmd);
982 return ret;
983}
984
a6bff3cb
HD
985static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
986{
971cbe50 987 u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD);
dd2a1256 988 union iwl_geo_tx_power_profiles_cmd cmd;
39c1a972 989 u16 len;
45acebf8 990 u32 n_bands;
97f8a3d1 991 u32 n_profiles;
c0a3dfc1 992 __le32 sk = cpu_to_le32(0);
0433ae55 993 int ret;
971cbe50 994 u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
e80bfd11 995 IWL_FW_CMD_VER_UNKNOWN);
a6bff3cb 996
45acebf8
NG
997 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) !=
998 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) ||
999 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) !=
97f8a3d1
AB
1000 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) ||
1001 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) !=
1002 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) ||
1003 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) !=
1004 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops));
1005
dd2a1256
LC
1006 /* the ops field is at the same spot for all versions, so set in v1 */
1007 cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
0c3d7282 1008
c0a3dfc1
MK
1009 /* Only set to South Korea if the table revision is 1 */
1010 if (mvm->fwrt.geo_rev == 1)
1011 sk = cpu_to_le32(1);
1012
97f8a3d1
AB
1013 if (cmd_ver == 5) {
1014 len = sizeof(cmd.v5);
1015 n_bands = ARRAY_SIZE(cmd.v5.table[0]);
2594e4d9 1016 n_profiles = BIOS_GEO_MAX_PROFILE_NUM;
c0a3dfc1 1017 cmd.v5.table_revision = sk;
97f8a3d1
AB
1018 } else if (cmd_ver == 4) {
1019 len = sizeof(cmd.v4);
1020 n_bands = ARRAY_SIZE(cmd.v4.table[0]);
2594e4d9 1021 n_profiles = BIOS_GEO_MAX_PROFILE_NUM;
c0a3dfc1 1022 cmd.v4.table_revision = sk;
97f8a3d1 1023 } else if (cmd_ver == 3) {
0ea788ed 1024 len = sizeof(cmd.v3);
45acebf8 1025 n_bands = ARRAY_SIZE(cmd.v3.table[0]);
2594e4d9 1026 n_profiles = BIOS_GEO_MIN_PROFILE_NUM;
c0a3dfc1 1027 cmd.v3.table_revision = sk;
0ea788ed
LC
1028 } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
1029 IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
dd2a1256 1030 len = sizeof(cmd.v2);
45acebf8 1031 n_bands = ARRAY_SIZE(cmd.v2.table[0]);
2594e4d9 1032 n_profiles = BIOS_GEO_MIN_PROFILE_NUM;
c0a3dfc1 1033 cmd.v2.table_revision = sk;
39c1a972 1034 } else {
dd2a1256 1035 len = sizeof(cmd.v1);
45acebf8 1036 n_bands = ARRAY_SIZE(cmd.v1.table[0]);
2594e4d9 1037 n_profiles = BIOS_GEO_MIN_PROFILE_NUM;
0c3d7282
HD
1038 }
1039
45acebf8
NG
1040 BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) !=
1041 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) ||
1042 offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) !=
97f8a3d1
AB
1043 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) ||
1044 offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) !=
1045 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) ||
1046 offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) !=
1047 offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table));
45acebf8 1048 /* the table is at the same position for all versions, so set use v1 */
2594e4d9
MK
1049 ret = iwl_sar_geo_fill_table(&mvm->fwrt, &cmd.v1.table[0][0],
1050 n_bands, n_profiles);
45acebf8
NG
1051
1052 /*
1053 * It is a valid scenario to not support SAR, or miss wgds table,
1054 * but in that case there is no need to send the command.
1055 */
1056 if (ret)
1057 return 0;
1058
971cbe50 1059 return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd);
6ce1e5c0
GA
1060}
1061
1062int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
1063{
8bdc52b9 1064 union iwl_ppag_table_cmd cmd;
e8e10a37 1065 int ret, cmd_size;
160bab43 1066
be3a8cbb 1067 ret = iwl_fill_ppag_table(&mvm->fwrt, &cmd, &cmd_size);
b20bdd9c 1068 /* Not supporting PPAG table is a valid scenario */
473bc264 1069 if (ret < 0)
b20bdd9c 1070 return 0;
6ce1e5c0 1071
f2134f66 1072 IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
6ce1e5c0
GA
1073 ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
1074 PER_PLATFORM_ANT_GAIN_CMD),
8bdc52b9 1075 0, cmd_size, &cmd);
6ce1e5c0
GA
1076 if (ret < 0)
1077 IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
1078 ret);
1079
1080 return ret;
1081}
1082
1083static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
1084{
78a19d52 1085 /* no need to read the table, done in INIT stage */
09059c67 1086 if (!(iwl_is_ppag_approved(&mvm->fwrt)))
a2ac0f48 1087 return 0;
a2ac0f48 1088
6ce1e5c0
GA
1089 return iwl_mvm_ppag_send_cmd(mvm);
1090}
1091
c3f40c3e
MK
1092static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc)
1093{
1094 int i;
1095 u32 size = le32_to_cpu(*le_size);
1096
1097 /* Verify that there is room for another country */
ad5a85d8 1098 if (size >= IWL_WTAS_BLACK_LIST_MAX)
c3f40c3e
MK
1099 return false;
1100
1101 for (i = 0; i < size; i++) {
1102 if (list[i] == cpu_to_le32(mcc))
1103 return true;
1104 }
1105
1106 list[size++] = cpu_to_le32(mcc);
1107 *le_size = cpu_to_le32(size);
1108 return true;
1109}
1110
28dd7ccd
MG
1111static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
1112{
971cbe50 1113 u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG);
28dd7ccd 1114 int ret;
3bc67e7c
MK
1115 struct iwl_tas_data data = {};
1116 struct iwl_tas_config_cmd cmd = {};
6da7ba3a 1117 int cmd_size, fw_ver;
28dd7ccd 1118
3bc67e7c
MK
1119 BUILD_BUG_ON(ARRAY_SIZE(data.block_list_array) !=
1120 IWL_WTAS_BLACK_LIST_MAX);
1121 BUILD_BUG_ON(ARRAY_SIZE(cmd.common.block_list_array) !=
ad5a85d8 1122 IWL_WTAS_BLACK_LIST_MAX);
28dd7ccd
MG
1123
1124 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
1125 IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
1126 return;
1127 }
1128
084e0452 1129 ret = iwl_bios_get_tas_table(&mvm->fwrt, &data);
28dd7ccd
MG
1130 if (ret < 0) {
1131 IWL_DEBUG_RADIO(mvm,
1132 "TAS table invalid or unavailable. (%d)\n",
1133 ret);
1134 return;
1135 }
1136
7c530588 1137 if (ret == 0)
28dd7ccd
MG
1138 return;
1139
ad5a85d8 1140 if (!iwl_is_tas_approved()) {
c3f40c3e
MK
1141 IWL_DEBUG_RADIO(mvm,
1142 "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
6256760f 1143 dmi_get_system_info(DMI_SYS_VENDOR) ?: "<unknown>");
3bc67e7c
MK
1144 if ((!iwl_mvm_add_to_tas_block_list(data.block_list_array,
1145 &data.block_list_size,
1146 IWL_MCC_US)) ||
1147 (!iwl_mvm_add_to_tas_block_list(data.block_list_array,
1148 &data.block_list_size,
1149 IWL_MCC_CANADA))) {
c3f40c3e
MK
1150 IWL_DEBUG_RADIO(mvm,
1151 "Unable to add US/Canada to TAS block list, disabling TAS\n");
1152 return;
1153 }
06471b67
AG
1154 } else {
1155 IWL_DEBUG_RADIO(mvm,
1156 "System vendor '%s' is in the approved list.\n",
6256760f 1157 dmi_get_system_info(DMI_SYS_VENDOR) ?: "<unknown>");
c3f40c3e
MK
1158 }
1159
3bc67e7c
MK
1160 fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
1161 IWL_FW_CMD_VER_UNKNOWN);
1162
1163 memcpy(&cmd.common, &data, sizeof(struct iwl_tas_config_cmd_common));
1164
1165 /* Set v3 or v4 specific parts. will be trunctated for fw_ver < 3 */
1166 if (fw_ver == 4) {
1167 cmd.v4.override_tas_iec = data.override_tas_iec;
1168 cmd.v4.enable_tas_iec = data.enable_tas_iec;
1169 cmd.v4.usa_tas_uhb_allowed = data.usa_tas_uhb_allowed;
1170 } else {
1171 cmd.v3.override_tas_iec = cpu_to_le16(data.override_tas_iec);
1172 cmd.v3.enable_tas_iec = cpu_to_le16(data.enable_tas_iec);
1173 }
1174
1175 cmd_size = sizeof(struct iwl_tas_config_cmd_common);
1176 if (fw_ver >= 3)
1177 /* v4 is the same size as v3 */
1178 cmd_size += sizeof(struct iwl_tas_config_cmd_v3);
28dd7ccd 1179
971cbe50 1180 ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd);
28dd7ccd
MG
1181 if (ret < 0)
1182 IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
1183}
f5b1cb2e 1184
dc2b94a1 1185static bool iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
4e8fe214 1186{
091d8942 1187 u32 value = 0;
dc2b94a1
MK
1188 /* default behaviour is disabled */
1189 bool bios_enable_rfi = false;
fc7214c3 1190 int ret = iwl_bios_get_dsm(&mvm->fwrt, DSM_FUNC_RFI_CONFIG, &value);
091d8942 1191
4e8fe214
GG
1192
1193 if (ret < 0) {
1194 IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
dc2b94a1
MK
1195 return bios_enable_rfi;
1196 }
4e8fe214 1197
dc2b94a1
MK
1198 value &= DSM_VALUE_RFI_DISABLE;
1199 /* RFI BIOS CONFIG value can be 0 or 3 only.
1200 * i.e 0 means DDR and DLVR enabled. 3 means DDR and DLVR disabled.
1201 * 1 and 2 are invalid BIOS configurations, So, it's not possible to
1202 * disable ddr/dlvr separately.
1203 */
1204 if (!value) {
4e8fe214 1205 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
dc2b94a1
MK
1206 bios_enable_rfi = true;
1207 } else if (value == DSM_VALUE_RFI_DISABLE) {
1208 IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to disable\n");
1209 } else {
1210 IWL_DEBUG_RADIO(mvm,
1211 "DSM RFI got invalid value, value=%d\n", value);
4e8fe214
GG
1212 }
1213
dc2b94a1 1214 return bios_enable_rfi;
4e8fe214
GG
1215}
1216
f5b1cb2e
GA
1217static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1218{
332ff432 1219 struct iwl_lari_config_change_cmd cmd;
aa80f484 1220 size_t cmd_size;
332ff432 1221 int ret;
54b4fda5 1222
aa80f484 1223 ret = iwl_fill_lari_config(&mvm->fwrt, &cmd, &cmd_size);
c3e5f5f6 1224 if (!ret) {
7119f02b
MK
1225 ret = iwl_mvm_send_cmd_pdu(mvm,
1226 WIDE_ID(REGULATORY_AND_NVM_GROUP,
1227 LARI_CONFIG_CHANGE),
1228 0, cmd_size, &cmd);
1229 if (ret < 0)
f5b1cb2e
GA
1230 IWL_DEBUG_RADIO(mvm,
1231 "Failed to send LARI_CONFIG_CHANGE (%d)\n",
7119f02b 1232 ret);
f5b1cb2e 1233 }
4a9bb5b4
MS
1234
1235 if (le32_to_cpu(cmd.oem_uhb_allow_bitmap) & IWL_UATS_VLP_AP_SUPPORTED ||
1236 le32_to_cpu(cmd.oem_uhb_allow_bitmap) & IWL_UATS_AFC_AP_SUPPORTED)
8efadbc3 1237 mvm->fwrt.uats_enabled = true;
f5b1cb2e 1238}
78a19d52 1239
427661e4 1240void iwl_mvm_get_bios_tables(struct iwl_mvm *mvm)
78a19d52
MK
1241{
1242 int ret;
1243
ebe8f413
MK
1244 iwl_acpi_get_guid_lock_status(&mvm->fwrt);
1245
78a19d52 1246 /* read PPAG table */
bc8d0a45 1247 ret = iwl_bios_get_ppag_table(&mvm->fwrt);
78a19d52
MK
1248 if (ret < 0) {
1249 IWL_DEBUG_RADIO(mvm,
1250 "PPAG BIOS table invalid or unavailable. (%d)\n",
1251 ret);
1252 }
1253
1254 /* read SAR tables */
427661e4 1255 ret = iwl_bios_get_wrds_table(&mvm->fwrt);
78a19d52
MK
1256 if (ret < 0) {
1257 IWL_DEBUG_RADIO(mvm,
1258 "WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1259 ret);
1260 /*
1261 * If not available, don't fail and don't bother with EWRD and
1262 * WGDS */
1263
427661e4 1264 if (!iwl_bios_get_wgds_table(&mvm->fwrt)) {
78a19d52
MK
1265 /*
1266 * If basic SAR is not available, we check for WGDS,
1267 * which should *not* be available either. If it is
1268 * available, issue an error, because we can't use SAR
1269 * Geo without basic SAR.
1270 */
1271 IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
1272 }
1273
1274 } else {
427661e4 1275 ret = iwl_bios_get_ewrd_table(&mvm->fwrt);
78a19d52
MK
1276 /* if EWRD is not available, we can still use
1277 * WRDS, so don't fail */
1278 if (ret < 0)
1279 IWL_DEBUG_RADIO(mvm,
1280 "EWRD SAR BIOS table invalid or unavailable. (%d)\n",
1281 ret);
1282
1283 /* read geo SAR table */
1284 if (iwl_sar_geo_support(&mvm->fwrt)) {
427661e4 1285 ret = iwl_bios_get_wgds_table(&mvm->fwrt);
78a19d52
MK
1286 if (ret < 0)
1287 IWL_DEBUG_RADIO(mvm,
1288 "Geo SAR BIOS table invalid or unavailable. (%d)\n",
1289 ret);
1290 /* we don't fail if the table is not available */
1291 }
1292 }
c4c95454
JB
1293
1294 iwl_acpi_get_phy_filters(&mvm->fwrt, &mvm->phy_filters);
20935f3e
MK
1295
1296 if (iwl_bios_get_eckv(&mvm->fwrt, &mvm->ext_clock_valid))
1297 IWL_DEBUG_RADIO(mvm, "ECKV table doesn't exist in BIOS\n");
78a19d52 1298}
69964905 1299
e50a88e5
EG
1300static void iwl_mvm_disconnect_iterator(void *data, u8 *mac,
1301 struct ieee80211_vif *vif)
1302{
1303 if (vif->type == NL80211_IFTYPE_STATION)
1304 ieee80211_hw_restart_disconnect(vif);
1305}
1306
f130bb75
MG
1307void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1308{
1309 u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1310 int ret;
1311 u32 resp;
1312
1313 struct iwl_fw_error_recovery_cmd recovery_cmd = {
1314 .flags = cpu_to_le32(flags),
1315 .buf_size = 0,
1316 };
1317 struct iwl_host_cmd host_cmd = {
1318 .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1319 .flags = CMD_WANT_SKB,
1320 .data = {&recovery_cmd, },
1321 .len = {sizeof(recovery_cmd), },
1322 };
1323
1324 /* no error log was defined in TLV */
1325 if (!error_log_size)
1326 return;
1327
1328 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1329 /* no buf was allocated while HW reset */
1330 if (!mvm->error_recovery_buf)
1331 return;
1332
1333 host_cmd.data[1] = mvm->error_recovery_buf;
1334 host_cmd.len[1] = error_log_size;
1335 host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1336 recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1337 }
1338
1339 ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1340 kfree(mvm->error_recovery_buf);
1341 mvm->error_recovery_buf = NULL;
1342
1343 if (ret) {
1344 IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1345 return;
1346 }
1347
1348 /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1349 if (flags & ERROR_RECOVERY_UPDATE_DB) {
1350 resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
e50a88e5 1351 if (resp) {
f130bb75
MG
1352 IWL_ERR(mvm,
1353 "Failed to send recovery cmd blob was invalid %d\n",
1354 resp);
e50a88e5
EG
1355
1356 ieee80211_iterate_interfaces(mvm->hw, 0,
1357 iwl_mvm_disconnect_iterator,
1358 mvm);
1359 }
f130bb75
MG
1360 }
1361}
1362
42ce76d6
LC
1363static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
1364{
1edd56e6 1365 return iwl_mvm_sar_select_profile(mvm, 1, 1);
da2830ac
LC
1366}
1367
1f370650 1368static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
8ca151b5 1369{
1f370650 1370 int ret;
8ca151b5 1371
7d6222e2 1372 if (iwl_mvm_has_unified_ucode(mvm))
52b15521 1373 return iwl_run_unified_mvm_ucode(mvm);
8ca151b5 1374
3b25f1af 1375 ret = iwl_run_init_mvm_ucode(mvm);
f2082a53 1376
f2082a53 1377 if (ret) {
8d193ca2 1378 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
f4744258
LK
1379
1380 if (iwlmvm_mod_params.init_dbg)
1381 return 0;
1f370650 1382 return ret;
8d193ca2 1383 }
8ca151b5 1384
203c83d3 1385 iwl_fw_dbg_stop_sync(&mvm->fwrt);
bab3cb92
EG
1386 iwl_trans_stop_device(mvm->trans);
1387 ret = iwl_trans_start_hw(mvm->trans);
f2082a53 1388 if (ret)
1f370650 1389 return ret;
8ca151b5 1390
94022562 1391 mvm->rfkill_safe_init_done = false;
8ca151b5 1392 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
1f370650
SS
1393 if (ret)
1394 return ret;
1395
94022562
EG
1396 mvm->rfkill_safe_init_done = true;
1397
b108d8c7
SM
1398 iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1399 NULL);
da2eb669 1400
702e975d 1401 return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
1f370650
SS
1402}
1403
1404int iwl_mvm_up(struct iwl_mvm *mvm)
1405{
1406 int ret, i;
dd36a507 1407 struct ieee80211_supported_band *sband = NULL;
1f370650
SS
1408
1409 lockdep_assert_held(&mvm->mutex);
1410
1411 ret = iwl_trans_start_hw(mvm->trans);
1412 if (ret)
1413 return ret;
733eb54f 1414
1f370650 1415 ret = iwl_mvm_load_rt_fw(mvm);
8ca151b5
JB
1416 if (ret) {
1417 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
b8133439 1418 if (ret != -ERFKILL && !mvm->pldr_sync)
72d3c7bb
JB
1419 iwl_fw_dbg_error_collect(&mvm->fwrt,
1420 FW_DBG_TRIGGER_DRIVER);
8ca151b5
JB
1421 goto error;
1422 }
1423
b8133439
AS
1424 /* FW loaded successfully */
1425 mvm->pldr_sync = false;
1426
fc2fe0a5 1427 iwl_fw_disable_dbg_asserts(&mvm->fwrt);
d0b813fc 1428 iwl_get_shared_mem_conf(&mvm->fwrt);
04fd2c28 1429
1f3b0ff8
LE
1430 ret = iwl_mvm_sf_update(mvm, NULL, false);
1431 if (ret)
1432 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1433
a1af4c48 1434 if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
7a14c23d
SS
1435 mvm->fwrt.dump.conf = FW_DBG_INVALID;
1436 /* if we have a destination, assume EARLY START */
1437 if (mvm->fw->dbg.dest_tlv)
1438 mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
1439 iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
1440 }
6a951267 1441
a0544272 1442 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1443 if (ret)
1444 goto error;
1445
7d6222e2
JB
1446 if (!iwl_mvm_has_unified_ucode(mvm)) {
1447 /* Send phy db control command and then phy db calibration */
1f370650
SS
1448 ret = iwl_send_phy_db_data(mvm->phy_db);
1449 if (ret)
1450 goto error;
d2ccc5c1
MS
1451 ret = iwl_send_phy_cfg_cmd(mvm);
1452 if (ret)
1453 goto error;
1f370650 1454 }
8ca151b5 1455
b3de3ef4
EG
1456 ret = iwl_mvm_send_bt_init_conf(mvm);
1457 if (ret)
1458 goto error;
1459
cceb4507
SM
1460 if (fw_has_capa(&mvm->fw->ucode_capa,
1461 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
a8eb340f 1462 ret = iwl_set_soc_latency(&mvm->fwrt);
cceb4507
SM
1463 if (ret)
1464 goto error;
1465 }
1466
c0a2f819
BB
1467 iwl_mvm_lari_cfg(mvm);
1468
43413a97 1469 /* Init RSS configuration */
9cd243f2
MG
1470 ret = iwl_configure_rxq(&mvm->fwrt);
1471 if (ret)
1472 goto error;
8edbfaa1
SS
1473
1474 if (iwl_mvm_has_new_rx_api(mvm)) {
43413a97
SS
1475 ret = iwl_send_rss_cfg_cmd(mvm);
1476 if (ret) {
1477 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
1478 ret);
1479 goto error;
1480 }
1481 }
1482
8ca151b5 1483 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1484 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1485 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB
1486 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1487 }
8ca151b5 1488
d464550b
YB
1489 for (i = 0; i < IWL_MVM_FW_MAX_LINK_ID + 1; i++)
1490 RCU_INIT_POINTER(mvm->link_id_to_link_conf[i], NULL);
1491
d6f6b0d8
GG
1492 memset(&mvm->fw_link_ids_map, 0, sizeof(mvm->fw_link_ids_map));
1493
0ae98812 1494 mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1d3c3f63 1495
b2b7875b
JB
1496 /* reset quota debouncing buffer - 0xff will yield invalid data */
1497 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1498
79660869
IL
1499 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
1500 ret = iwl_mvm_send_dqa_cmd(mvm);
1501 if (ret)
1502 goto error;
1503 }
97d5be7e 1504
2c2c3647
NE
1505 /*
1506 * Add auxiliary station for scanning.
1507 * Newer versions of this command implies that the fw uses
1508 * internal aux station for all aux activities that don't
1509 * requires a dedicated data queue.
1510 */
1724fc78 1511 if (!iwl_mvm_has_new_station_api(mvm->fw)) {
2c2c3647
NE
1512 /*
1513 * In old version the aux station uses mac id like other
1514 * station and not lmac id
1515 */
1516 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1517 if (ret)
1518 goto error;
1519 }
8ca151b5 1520
53a9d61e 1521 /* Add all the PHY contexts */
dd36a507
TM
1522 i = 0;
1523 while (!sband && i < NUM_NL80211_BANDS)
1524 sband = mvm->hw->wiphy->bands[i++];
1525
583d1833
DC
1526 if (WARN_ON_ONCE(!sband)) {
1527 ret = -ENODEV;
dd36a507 1528 goto error;
583d1833 1529 }
dd36a507 1530
c221daf2
CRI
1531 if (iwl_mvm_is_tt_in_fw(mvm)) {
1532 /* in order to give the responsibility of ct-kill and
1533 * TX backoff to FW we need to send empty temperature reporting
1534 * cmd during init time
1535 */
1536 iwl_mvm_send_temp_report_ths_cmd(mvm);
1537 } else {
1538 /* Initialize tx backoffs to the minimal possible */
1539 iwl_mvm_tt_tx_backoff(mvm, 0);
1540 }
5c89e7bc 1541
242d9c8b 1542#ifdef CONFIG_THERMAL
5c89e7bc 1543 /* TODO: read the budget from BIOS / Platform NVM */
944eafc2
CRI
1544
1545 /*
1546 * In case there is no budget from BIOS / Platform NVM the default
1547 * budget should be 2000mW (cooling state 0).
1548 */
1549 if (iwl_mvm_is_ctdp_supported(mvm)) {
5c89e7bc
CRI
1550 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
1551 mvm->cooling_dev.cur_state);
75cfe338
LC
1552 if (ret)
1553 goto error;
1554 }
c221daf2 1555#endif
0c0e2c71 1556
aa43ae12
AM
1557 if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1558 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1559
c1cb92fc 1560 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB
1561 if (ret)
1562 goto error;
1563
35af15d1
AN
1564 /*
1565 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1566 * anyway, so don't init MCC.
1567 */
1568 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1569 ret = iwl_mvm_init_mcc(mvm);
1570 if (ret)
1571 goto error;
1572 }
90d4f7db 1573
859d914c 1574 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 1575 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
b66b5817 1576 mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS
1577 ret = iwl_mvm_config_scan(mvm);
1578 if (ret)
1579 goto error;
1580 }
1581
cf85123a 1582 if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) {
f130bb75 1583 iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
ead65aa2
JB
1584
1585 if (mvm->time_sync.active)
1586 iwl_mvm_time_sync_config(mvm, mvm->time_sync.peer_addr,
1587 IWL_TIME_SYNC_PROTOCOL_TM |
1588 IWL_TIME_SYNC_PROTOCOL_FTM);
cf85123a 1589 }
f130bb75 1590
1595ecce
KP
1591 if (!mvm->ptp_data.ptp_clock)
1592 iwl_mvm_ptp_init(mvm);
1593
6ce1e5c0
GA
1594 ret = iwl_mvm_ppag_init(mvm);
1595 if (ret)
1596 goto error;
1597
da2830ac 1598 ret = iwl_mvm_sar_init(mvm);
78a19d52 1599 if (ret == 0)
5d041c46 1600 ret = iwl_mvm_sar_geo_init(mvm);
5f06f6bf 1601 if (ret < 0)
a6bff3cb
HD
1602 goto error;
1603
c593d2fa
AB
1604 ret = iwl_mvm_sgom_init(mvm);
1605 if (ret)
1606 goto error;
1607
28dd7ccd 1608 iwl_mvm_tas_init(mvm);
7089ae63 1609 iwl_mvm_leds_sync(mvm);
4a9bb5b4 1610 iwl_mvm_uats_init(mvm);
7089ae63 1611
9e26f098 1612 if (iwl_rfi_supported(mvm)) {
dc2b94a1 1613 if (iwl_mvm_eval_dsm_rfi(mvm))
4e8fe214
GG
1614 iwl_rfi_send_config_cmd(mvm, NULL);
1615 }
1616
5aa7ce31
AS
1617 iwl_mvm_mei_device_state(mvm, true);
1618
53a9d61e 1619 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB
1620 return 0;
1621 error:
f4744258 1622 if (!iwlmvm_mod_params.init_dbg || !ret)
de8ba41b 1623 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1624 return ret;
1625}
1626
1627int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1628{
1629 int ret, i;
1630
1631 lockdep_assert_held(&mvm->mutex);
1632
1633 ret = iwl_trans_start_hw(mvm->trans);
1634 if (ret)
1635 return ret;
1636
1637 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1638 if (ret) {
1639 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1640 goto error;
1641 }
1642
a0544272 1643 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB
1644 if (ret)
1645 goto error;
1646
1647 /* Send phy db control command and then phy db calibration*/
1648 ret = iwl_send_phy_db_data(mvm->phy_db);
1649 if (ret)
1650 goto error;
1651
1652 ret = iwl_send_phy_cfg_cmd(mvm);
1653 if (ret)
1654 goto error;
1655
1656 /* init the fw <-> mac80211 STA mapping */
b8a85a1d 1657 for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
8ca151b5 1658 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
b8a85a1d
JB
1659 RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
1660 }
8ca151b5 1661
1724fc78 1662 if (!iwl_mvm_has_new_station_api(mvm->fw)) {
2c2c3647
NE
1663 /*
1664 * Add auxiliary station for scanning.
1665 * Newer versions of this command implies that the fw uses
1666 * internal aux station for all aux activities that don't
1667 * requires a dedicated data queue.
1668 * In old version the aux station uses mac id like other
1669 * station and not lmac id
1670 */
1671 ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX);
1672 if (ret)
1673 goto error;
1674 }
8ca151b5
JB
1675
1676 return 0;
1677 error:
fcb6b92a 1678 iwl_mvm_stop_device(mvm);
8ca151b5
JB
1679 return ret;
1680}
1681
0416841d
JB
1682void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1683 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI
1684{
1685 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1686 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1687
0c8d0a47
GBA
1688 IWL_DEBUG_INFO(mvm,
1689 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1690 le32_to_cpu(mfuart_notif->installed_ver),
1691 le32_to_cpu(mfuart_notif->external_ver),
1692 le32_to_cpu(mfuart_notif->status),
1693 le32_to_cpu(mfuart_notif->duration));
1694
19f63c53
GBA
1695 if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
1696 IWL_DEBUG_INFO(mvm,
0c8d0a47 1697 "MFUART: image size: 0x%08x\n",
19f63c53 1698 le32_to_cpu(mfuart_notif->image_size));
30269c12 1699}