projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cfg80211: remove enum ieee80211_band
[linux-block.git] / drivers / net / wireless / intel / iwlwifi / iwl-nvm-parse.c
CommitLineData
b1e1adfa
JB		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
5f0d98f2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afd5b170 10 * Copyright(c) 2016 Intel Deutschland GmbH
b1e1adfa
JB		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
b1e1adfa
JB		 28 *
29 * Contact Information:
d01c5366 30 * Intel Linux Wireless <linuxwifi@intel.com>
b1e1adfa
JB		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
51368bf7 35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
5f0d98f2 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
b1e1adfa
JB		 37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *****************************************************************************/
65#include <linux/types.h>
66#include <linux/slab.h>
67#include <linux/export.h>
9f32e017 68#include <linux/etherdevice.h>
1e0b393a 69#include <linux/pci.h>
48e29340 70#include "iwl-drv.h"
b1e1adfa
JB		 71#include "iwl-modparams.h"
72#include "iwl-nvm-parse.h"
afd5b170 73#include "iwl-prph.h"
17c867bf
SS		 74#include "iwl-io.h"
75#include "iwl-csr.h"
b1e1adfa
JB		 76
77/* NVM offsets (in words) definitions */
78enum wkp_nvm_offsets {
79 /* NVM HW-Section offset (in words) definitions */
80 HW_ADDR = 0x15,
81
77db0a3c 82 /* NVM SW-Section offset (in words) definitions */
b1e1adfa
JB		 83 NVM_SW_SECTION = 0x1C0,
84 NVM_VERSION = 0,
85 RADIO_CFG = 1,
86 SKU = 2,
87 N_HW_ADDRS = 3,
88 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
89
77db0a3c 90 /* NVM calibration section offset (in words) definitions */
b1e1adfa
JB		 91 NVM_CALIB_SECTION = 0x2B8,
92 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
93};
94
77db0a3c
EH		 95enum family_8000_nvm_offsets {
96 /* NVM HW-Section offset (in words) definitions */
1e0b393a
EH		 97 HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
98 HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
99 HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
100 HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
77db0a3c
EH		 101 MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
102
103 /* NVM SW-Section offset (in words) definitions */
104 NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
105 NVM_VERSION_FAMILY_8000 = 0,
5dd9c68a
EG		 106 RADIO_CFG_FAMILY_8000 = 0,
107 SKU_FAMILY_8000 = 2,
108 N_HW_ADDRS_FAMILY_8000 = 3,
ce500071 109
77db0a3c
EH		 110 /* NVM REGULATORY -Section offset (in words) definitions */
111 NVM_CHANNELS_FAMILY_8000 = 0,
f5528631
AN		 112 NVM_LAR_OFFSET_FAMILY_8000_OLD = 0x4C7,
113 NVM_LAR_OFFSET_FAMILY_8000 = 0x507,
d0d15197 114 NVM_LAR_ENABLED_FAMILY_8000 = 0x7,
77db0a3c
EH		 115
116 /* NVM calibration section offset (in words) definitions */
117 NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
118 XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
119};
120
b1e1adfa
JB		 121/* SKU Capabilities (actual values from NVM definition) */
122enum nvm_sku_bits {
5f0d98f2
EG		 123 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
124 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
125 NVM_SKU_CAP_11N_ENABLE = BIT(2),
126 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
b1e1adfa
JB		 128};
129
b1e1adfa
JB		 130/*
131 * These are the channel numbers in the order that they are stored in the NVM
132 */
133static const u8 iwl_nvm_channels[] = {
134 /* 2.4 GHz */
135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
136 /* 5 GHz */
137 36, 40, 44 , 48, 52, 56, 60, 64,
138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
139 149, 153, 157, 161, 165
140};
141
77db0a3c
EH		 142static const u8 iwl_nvm_channels_family_8000[] = {
143 /* 2.4 GHz */
9b1c9a66 144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
77db0a3c
EH		 145 /* 5 GHz */
146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
148 149, 153, 157, 161, 165, 169, 173, 177, 181
149};
150
749f1fe1 151#define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
77db0a3c 152#define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
749f1fe1 153#define NUM_2GHZ_CHANNELS 14
9b1c9a66 154#define NUM_2GHZ_CHANNELS_FAMILY_8000 14
749f1fe1
EH		 155#define FIRST_2GHZ_HT_MINUS 5
156#define LAST_2GHZ_HT_PLUS 9
b281c93d
MG		 157#define LAST_5GHZ_HT 165
158#define LAST_5GHZ_HT_FAMILY_8000 181
ce500071 159#define N_HW_ADDR_MASK 0xF
b1e1adfa 160
b1e1adfa
JB		 161/* rate data (static) */
162static struct ieee80211_rate iwl_cfg80211_rates[] = {
163 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
164 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
165 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
166 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
167 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
168 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
169 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
170 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
171 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
172 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
173 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
174 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
175 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
176 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
177 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
178};
179#define RATES_24_OFFS 0
180#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
181#define RATES_52_OFFS 4
182#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
183
184/**
185 * enum iwl_nvm_channel_flags - channel flags in NVM
186 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
187 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
188 * @NVM_CHANNEL_ACTIVE: active scanning allowed
189 * @NVM_CHANNEL_RADAR: radar detection required
9ee6dace
DS		 190 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
191 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
192 * on same channel on 2.4 or same UNII band on 5.2
b1e1adfa
JB		 193 * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
194 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
33158fef
EL		 195 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
196 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
b1e1adfa
JB		 197 */
198enum iwl_nvm_channel_flags {
199 NVM_CHANNEL_VALID = BIT(0),
200 NVM_CHANNEL_IBSS = BIT(1),
201 NVM_CHANNEL_ACTIVE = BIT(3),
202 NVM_CHANNEL_RADAR = BIT(4),
9ee6dace
DS		 203 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
204 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
b1e1adfa
JB		 205 NVM_CHANNEL_WIDE = BIT(8),
206 NVM_CHANNEL_40MHZ = BIT(9),
33158fef
EL		 207 NVM_CHANNEL_80MHZ = BIT(10),
208 NVM_CHANNEL_160MHZ = BIT(11),
b1e1adfa
JB		 209};
210
211#define CHECK_AND_PRINT_I(x) \
212 ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
213
770ceda6 214static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
b281c93d 215 u16 nvm_flags, const struct iwl_cfg *cfg)
770ceda6
AN		 216{
217 u32 flags = IEEE80211_CHAN_NO_HT40;
b281c93d
MG		 218 u32 last_5ghz_ht = LAST_5GHZ_HT;
219
220 if (cfg->device_family == IWL_DEVICE_FAMILY_8000)
221 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
770ceda6
AN		 222
223 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
224 if (ch_num <= LAST_2GHZ_HT_PLUS)
225 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
226 if (ch_num >= FIRST_2GHZ_HT_MINUS)
227 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
b281c93d 228 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
770ceda6
AN		 229 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
230 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
231 else
232 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
233 }
234 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
235 flags |= IEEE80211_CHAN_NO_80MHZ;
236 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
237 flags |= IEEE80211_CHAN_NO_160MHZ;
238
239 if (!(nvm_flags & NVM_CHANNEL_IBSS))
240 flags |= IEEE80211_CHAN_NO_IR;
241
242 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
243 flags |= IEEE80211_CHAN_NO_IR;
244
245 if (nvm_flags & NVM_CHANNEL_RADAR)
246 flags |= IEEE80211_CHAN_RADAR;
247
248 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
249 flags |= IEEE80211_CHAN_INDOOR_ONLY;
250
251 /* Set the GO concurrent flag only in case that NO_IR is set.
252 * Otherwise it is meaningless
253 */
254 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
255 (flags & IEEE80211_CHAN_NO_IR))
06f207fc 256 flags |= IEEE80211_CHAN_IR_CONCURRENT;
770ceda6
AN		 257
258 return flags;
259}
260
b1e1adfa
JB		 261static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
262 struct iwl_nvm_data *data,
770ceda6
AN		 263 const __le16 * const nvm_ch_flags,
264 bool lar_supported)
b1e1adfa
JB		 265{
266 int ch_idx;
267 int n_channels = 0;
268 struct ieee80211_channel *channel;
269 u16 ch_flags;
270 bool is_5ghz;
749f1fe1 271 int num_of_ch, num_2ghz_channels;
77db0a3c
EH		 272 const u8 *nvm_chan;
273
274 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
275 num_of_ch = IWL_NUM_CHANNELS;
276 nvm_chan = &iwl_nvm_channels[0];
749f1fe1 277 num_2ghz_channels = NUM_2GHZ_CHANNELS;
77db0a3c
EH		 278 } else {
279 num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
280 nvm_chan = &iwl_nvm_channels_family_8000[0];
749f1fe1 281 num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
77db0a3c 282 }
b1e1adfa 283
77db0a3c 284 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
b1e1adfa 285 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
c5128654 286
749f1fe1 287 if (ch_idx >= num_2ghz_channels &&
c5128654 288 !data->sku_cap_band_52GHz_enable)
a76f3bfe 289 continue;
c5128654 290
770ceda6 291 if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
a76f3bfe
EP		 292 /*
293 * Channels might become valid later if lar is
294 * supported, hence we still want to add them to
295 * the list of supported channels to cfg80211.
296 */
b1e1adfa
JB		 297 IWL_DEBUG_EEPROM(dev,
298 "Ch. %d Flags %x [%sGHz] - No traffic\n",
77db0a3c 299 nvm_chan[ch_idx],
b1e1adfa 300 ch_flags,
749f1fe1 301 (ch_idx >= num_2ghz_channels) ?
b1e1adfa
JB		 302 "5.2" : "2.4");
303 continue;
304 }
305
306 channel = &data->channels[n_channels];
307 n_channels++;
308
77db0a3c 309 channel->hw_value = nvm_chan[ch_idx];
749f1fe1 310 channel->band = (ch_idx < num_2ghz_channels) ?
57fbcce3 311 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
b1e1adfa
JB		 312 channel->center_freq =
313 ieee80211_channel_to_frequency(
314 channel->hw_value, channel->band);
315
b1e1adfa
JB		 316 /* Initialize regulatory-based run-time data */
317
88f2fd73
MG		 318 /*
319 * Default value - highest tx power value. max_power
320 * is not used in mvm, and is used for backwards compatibility
321 */
22d059a5 322 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
57fbcce3 323 is_5ghz = channel->band == NL80211_BAND_5GHZ;
770ceda6
AN		 324
325 /* don't put limitations in case we're using LAR */
326 if (!lar_supported)
327 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
328 ch_idx, is_5ghz,
b281c93d 329 ch_flags, cfg);
770ceda6
AN		 330 else
331 channel->flags = 0;
332
b1e1adfa 333 IWL_DEBUG_EEPROM(dev,
9ee6dace 334 "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
b1e1adfa
JB		 335 channel->hw_value,
336 is_5ghz ? "5.2" : "2.4",
337 CHECK_AND_PRINT_I(VALID),
338 CHECK_AND_PRINT_I(IBSS),
339 CHECK_AND_PRINT_I(ACTIVE),
340 CHECK_AND_PRINT_I(RADAR),
341 CHECK_AND_PRINT_I(WIDE),
9ee6dace
DS		 342 CHECK_AND_PRINT_I(INDOOR_ONLY),
343 CHECK_AND_PRINT_I(GO_CONCURRENT),
b1e1adfa
JB		 344 ch_flags,
345 channel->max_power,
346 ((ch_flags & NVM_CHANNEL_IBSS) &&
347 !(ch_flags & NVM_CHANNEL_RADAR))
348 ? "" : "not ");
349 }
350
351 return n_channels;
352}
353
33158fef
EL		 354static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
355 struct iwl_nvm_data *data,
6ca89f1f
JB		 356 struct ieee80211_sta_vht_cap *vht_cap,
357 u8 tx_chains, u8 rx_chains)
33158fef 358{
6ca89f1f
JB		 359 int num_rx_ants = num_of_ant(rx_chains);
360 int num_tx_ants = num_of_ant(tx_chains);
c064ddf3
EH		 361 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
362 IEEE80211_VHT_MAX_AMPDU_1024K);
48e6de61 363
33158fef
EL		 364 vht_cap->vht_supported = true;
365
366 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
367 IEEE80211_VHT_CAP_RXSTBC_1 |
368 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
e36b766d 369 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
c064ddf3
EH		 370 max_ampdu_exponent <<
371 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
33158fef 372
e48c947f
SS		 373 if (cfg->vht_mu_mimo_supported)
374 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
375
a3576ff2
ES		 376 if (cfg->ht_params->ldpc)
377 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
378
5f0d98f2
EG		 379 if (data->sku_cap_mimo_disabled) {
380 num_rx_ants = 1;
381 num_tx_ants = 1;
382 }
383
6ca89f1f 384 if (num_tx_ants > 1)
5f7a6f9b 385 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
6ca89f1f
JB		 386 else
387 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
5f7a6f9b 388
6c4fbcbc
EG		 389 switch (iwlwifi_mod_params.amsdu_size) {
390 case IWL_AMSDU_4K:
391 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
392 break;
393 case IWL_AMSDU_8K:
33158fef 394 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
6c4fbcbc
EG		 395 break;
396 case IWL_AMSDU_12K:
397 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
398 break;
399 default:
400 break;
401 }
33158fef
EL		 402
403 vht_cap->vht_mcs.rx_mcs_map =
404 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
405 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
406 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
407 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
408 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
409 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
410 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
411 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
412
6ca89f1f
JB		 413 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
414 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
33158fef
EL		 415 /* this works because NOT_SUPPORTED == 3 */
416 vht_cap->vht_mcs.rx_mcs_map |=
417 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
418 }
419
420 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
421}
422
b1e1adfa 423static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
77db0a3c 424 struct iwl_nvm_data *data,
2926f958 425 const __le16 *ch_section,
770ceda6 426 u8 tx_chains, u8 rx_chains, bool lar_supported)
b1e1adfa 427{
77db0a3c 428 int n_channels;
b1e1adfa
JB		 429 int n_used = 0;
430 struct ieee80211_supported_band *sband;
431
77db0a3c
EH		 432 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
433 n_channels = iwl_init_channel_map(
434 dev, cfg, data,
770ceda6 435 &ch_section[NVM_CHANNELS], lar_supported);
77db0a3c
EH		 436 else
437 n_channels = iwl_init_channel_map(
438 dev, cfg, data,
770ceda6
AN		 439 &ch_section[NVM_CHANNELS_FAMILY_8000],
440 lar_supported);
77db0a3c 441
57fbcce3
JB		 442 sband = &data->bands[NL80211_BAND_2GHZ];
443 sband->band = NL80211_BAND_2GHZ;
b1e1adfa
JB		 444 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
445 sband->n_bitrates = N_RATES_24;
446 n_used += iwl_init_sband_channels(data, sband, n_channels,
57fbcce3
JB		 447 NL80211_BAND_2GHZ);
448 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ,
9ce4fa72 449 tx_chains, rx_chains);
b1e1adfa 450
57fbcce3
JB		 451 sband = &data->bands[NL80211_BAND_5GHZ];
452 sband->band = NL80211_BAND_5GHZ;
b1e1adfa
JB		 453 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
454 sband->n_bitrates = N_RATES_52;
455 n_used += iwl_init_sband_channels(data, sband, n_channels,
57fbcce3
JB		 456 NL80211_BAND_5GHZ);
457 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ,
9ce4fa72 458 tx_chains, rx_chains);
0d0985ad 459 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
6ca89f1f
JB		 460 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
461 tx_chains, rx_chains);
b1e1adfa
JB		 462
463 if (n_channels != n_used)
464 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
465 n_used, n_channels);
466}
467
5dd9c68a
EG		 468static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
469 const __le16 *phy_sku)
77db0a3c
EH		 470{
471 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
472 return le16_to_cpup(nvm_sw + SKU);
ce500071 473
5dd9c68a 474 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
77db0a3c
EH		 475}
476
5dd9c68a 477static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
77db0a3c
EH		 478{
479 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
480 return le16_to_cpup(nvm_sw + NVM_VERSION);
481 else
482 return le32_to_cpup((__le32 *)(nvm_sw +
483 NVM_VERSION_FAMILY_8000));
484}
485
5dd9c68a
EG		 486static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
487 const __le16 *phy_sku)
77db0a3c
EH		 488{
489 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
490 return le16_to_cpup(nvm_sw + RADIO_CFG);
ce500071 491
f115fdfd 492 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_8000));
ce500071 493
77db0a3c
EH		 494}
495
5dd9c68a 496static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
77db0a3c 497{
ce500071
EH		 498 int n_hw_addr;
499
77db0a3c
EH		 500 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
501 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
ce500071 502
5dd9c68a 503 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
ce500071
EH		 504
505 return n_hw_addr & N_HW_ADDR_MASK;
77db0a3c
EH		 506}
507
508static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
509 struct iwl_nvm_data *data,
510 u32 radio_cfg)
511{
512 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
513 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
514 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
515 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
516 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
77db0a3c
EH		 517 return;
518 }
519
520 /* set the radio configuration for family 8000 */
521 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
522 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
523 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
524 data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
a0544272
MH		 525 data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK_FAMILY_8000(radio_cfg);
526 data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK_FAMILY_8000(radio_cfg);
77db0a3c
EH		 527}
528
17c867bf
SS		 529static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
530{
531 const u8 *hw_addr;
532
533 hw_addr = (const u8 *)&mac_addr0;
534 dest[0] = hw_addr[3];
535 dest[1] = hw_addr[2];
536 dest[2] = hw_addr[1];
537 dest[3] = hw_addr[0];
538
539 hw_addr = (const u8 *)&mac_addr1;
540 dest[4] = hw_addr[1];
541 dest[5] = hw_addr[0];
542}
543
544static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
545 struct iwl_nvm_data *data)
546{
547 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
548 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
549
550 /* If OEM did not fuse address - get it from OTP */
551 if (!mac_addr0 && !mac_addr1) {
552 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
553 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
554 }
555
556 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
557}
558
afd5b170 559static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
6a68a39f 560 const struct iwl_cfg *cfg,
9f32e017
EH		 561 struct iwl_nvm_data *data,
562 const __le16 *mac_override,
afd5b170 563 const __le16 *nvm_hw)
9f32e017
EH		 564{
565 const u8 *hw_addr;
566
567 if (mac_override) {
18f84673
LK		 568 static const u8 reserved_mac[] = {
569 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
570 };
571
9f32e017
EH		 572 hw_addr = (const u8 *)(mac_override +
573 MAC_ADDRESS_OVERRIDE_FAMILY_8000);
574
be88a1ad
LK		 575 /*
576 * Store the MAC address from MAO section.
577 * No byte swapping is required in MAO section
578 */
579 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
9f32e017 580
18f84673
LK		 581 /*
582 * Force the use of the OTP MAC address in case of reserved MAC
583 * address in the NVM, or if address is given but invalid.
584 */
585 if (is_valid_ether_addr(data->hw_addr) &&
586 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
9f32e017 587 return;
6a68a39f 588
afd5b170
SS		 589 IWL_ERR(trans,
590 "mac address from nvm override section is not valid\n");
9f32e017
EH		 591 }
592
6a68a39f 593 if (nvm_hw) {
afd5b170
SS		 594 /* read the mac address from WFMP registers */
595 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
596 WFMP_MAC_ADDR_0));
597 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
598 WFMP_MAC_ADDR_1));
17c867bf
SS		 599
600 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1e0b393a 601
6a68a39f
EH		 602 return;
603 }
9f32e017 604
afd5b170
SS		 605 IWL_ERR(trans, "mac address is not found\n");
606}
607
17c867bf
SS		 608static int iwl_set_hw_address(struct iwl_trans *trans,
609 const struct iwl_cfg *cfg,
610 struct iwl_nvm_data *data, const __le16 *nvm_hw,
611 const __le16 *mac_override)
afd5b170 612{
17c867bf
SS		 613 if (cfg->mac_addr_from_csr) {
614 iwl_set_hw_address_from_csr(trans, data);
615 } else if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
afd5b170
SS		 616 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
617
618 /* The byte order is little endian 16 bit, meaning 214365 */
619 data->hw_addr[0] = hw_addr[1];
620 data->hw_addr[1] = hw_addr[0];
621 data->hw_addr[2] = hw_addr[3];
622 data->hw_addr[3] = hw_addr[2];
623 data->hw_addr[4] = hw_addr[5];
624 data->hw_addr[5] = hw_addr[4];
625 } else {
626 iwl_set_hw_address_family_8000(trans, cfg, data,
627 mac_override, nvm_hw);
628 }
17c867bf
SS		 629
630 if (!is_valid_ether_addr(data->hw_addr)) {
631 IWL_ERR(trans, "no valid mac address was found\n");
632 return -EINVAL;
633 }
634
635 return 0;
9f32e017
EH		 636}
637
b1e1adfa 638struct iwl_nvm_data *
afd5b170 639iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
b1e1adfa 640 const __le16 *nvm_hw, const __le16 *nvm_sw,
77db0a3c 641 const __le16 *nvm_calib, const __le16 *regulatory,
ce500071 642 const __le16 *mac_override, const __le16 *phy_sku,
afd5b170 643 u8 tx_chains, u8 rx_chains, bool lar_fw_supported)
b1e1adfa 644{
afd5b170 645 struct device *dev = trans->dev;
b1e1adfa 646 struct iwl_nvm_data *data;
afd5b170
SS		 647 bool lar_enabled;
648 u32 sku, radio_cfg;
d0d15197 649 u16 lar_config;
afd5b170 650 const __le16 *ch_section;
77db0a3c
EH		 651
652 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
653 data = kzalloc(sizeof(*data) +
654 sizeof(struct ieee80211_channel) *
655 IWL_NUM_CHANNELS,
656 GFP_KERNEL);
657 else
658 data = kzalloc(sizeof(*data) +
659 sizeof(struct ieee80211_channel) *
660 IWL_NUM_CHANNELS_FAMILY_8000,
661 GFP_KERNEL);
b1e1adfa
JB		 662 if (!data)
663 return NULL;
664
77db0a3c 665 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
b1e1adfa 666
5dd9c68a 667 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
77db0a3c 668 iwl_set_radio_cfg(cfg, data, radio_cfg);
a0544272
MH		 669 if (data->valid_tx_ant)
670 tx_chains &= data->valid_tx_ant;
671 if (data->valid_rx_ant)
672 rx_chains &= data->valid_rx_ant;
b1e1adfa 673
5dd9c68a 674 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
b1e1adfa
JB		 675 data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
676 data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
677 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
678 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
679 data->sku_cap_11n_enable = false;
2926f958
EP		 680 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
681 (sku & NVM_SKU_CAP_11AC_ENABLE);
5f0d98f2 682 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
b1e1adfa 683
5dd9c68a 684 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
b1e1adfa 685
77db0a3c
EH		 686 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
687 /* Checking for required sections */
688 if (!nvm_calib) {
afd5b170
SS		 689 IWL_ERR(trans,
690 "Can't parse empty Calib NVM sections\n");
1270c416 691 kfree(data);
77db0a3c
EH		 692 return NULL;
693 }
694 /* in family 8000 Xtal calibration values moved to OTP */
695 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
696 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
afd5b170
SS		 697 lar_enabled = true;
698 ch_section = nvm_sw;
77db0a3c 699 } else {
f5528631
AN		 700 u16 lar_offset = data->nvm_version < 0xE39 ?
701 NVM_LAR_OFFSET_FAMILY_8000_OLD :
702 NVM_LAR_OFFSET_FAMILY_8000;
703
704 lar_config = le16_to_cpup(regulatory + lar_offset);
d0d15197
MG		 705 data->lar_enabled = !!(lar_config &
706 NVM_LAR_ENABLED_FAMILY_8000);
afd5b170
SS		 707 lar_enabled = data->lar_enabled;
708 ch_section = regulatory;
77db0a3c 709 }
b1e1adfa 710
17c867bf
SS		 711 /* If no valid mac address was found - bail out */
712 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
713 kfree(data);
714 return NULL;
715 }
716
afd5b170
SS		 717 iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains,
718 lar_fw_supported && lar_enabled);
33b2f684 719 data->calib_version = 255;
b1e1adfa
JB		 720
721 return data;
722}
48e29340 723IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
af45a900
AN		 724
725static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
b281c93d
MG		 726 int ch_idx, u16 nvm_flags,
727 const struct iwl_cfg *cfg)
af45a900
AN		 728{
729 u32 flags = NL80211_RRF_NO_HT40;
b281c93d
MG		 730 u32 last_5ghz_ht = LAST_5GHZ_HT;
731
732 if (cfg->device_family == IWL_DEVICE_FAMILY_8000)
733 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
af45a900
AN		 734
735 if (ch_idx < NUM_2GHZ_CHANNELS &&
736 (nvm_flags & NVM_CHANNEL_40MHZ)) {
737 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
738 flags &= ~NL80211_RRF_NO_HT40PLUS;
739 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
740 flags &= ~NL80211_RRF_NO_HT40MINUS;
b281c93d 741 } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
af45a900
AN		 742 (nvm_flags & NVM_CHANNEL_40MHZ)) {
743 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
744 flags &= ~NL80211_RRF_NO_HT40PLUS;
745 else
746 flags &= ~NL80211_RRF_NO_HT40MINUS;
747 }
748
749 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
750 flags |= NL80211_RRF_NO_80MHZ;
751 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
752 flags |= NL80211_RRF_NO_160MHZ;
753
af45a900
AN		 754 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
755 flags |= NL80211_RRF_NO_IR;
756
757 if (nvm_flags & NVM_CHANNEL_RADAR)
758 flags |= NL80211_RRF_DFS;
759
760 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
761 flags |= NL80211_RRF_NO_OUTDOOR;
762
763 /* Set the GO concurrent flag only in case that NO_IR is set.
764 * Otherwise it is meaningless
765 */
766 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
767 (flags & NL80211_RRF_NO_IR))
768 flags |= NL80211_RRF_GO_CONCURRENT;
769
770 return flags;
771}
772
773struct ieee80211_regdomain *
162ee3c9
AN		 774iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
775 int num_of_ch, __le32 *channels, u16 fw_mcc)
af45a900
AN		 776{
777 int ch_idx;
778 u16 ch_flags, prev_ch_flags = 0;
162ee3c9
AN		 779 const u8 *nvm_chan = cfg->device_family == IWL_DEVICE_FAMILY_8000 ?
780 iwl_nvm_channels_family_8000 : iwl_nvm_channels;
af45a900
AN		 781 struct ieee80211_regdomain *regd;
782 int size_of_regd;
783 struct ieee80211_reg_rule *rule;
57fbcce3 784 enum nl80211_band band;
af45a900
AN		 785 int center_freq, prev_center_freq = 0;
786 int valid_rules = 0;
787 bool new_rule;
4557eaba
AN		 788 int max_num_ch = cfg->device_family == IWL_DEVICE_FAMILY_8000 ?
789 IWL_NUM_CHANNELS_FAMILY_8000 : IWL_NUM_CHANNELS;
af45a900
AN		 790
791 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
792 return ERR_PTR(-EINVAL);
793
4557eaba
AN		 794 if (WARN_ON(num_of_ch > max_num_ch))
795 num_of_ch = max_num_ch;
796
af45a900
AN		 797 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
798 num_of_ch);
799
800 /* build a regdomain rule for every valid channel */
801 size_of_regd =
802 sizeof(struct ieee80211_regdomain) +
803 num_of_ch * sizeof(struct ieee80211_reg_rule);
804
805 regd = kzalloc(size_of_regd, GFP_KERNEL);
806 if (!regd)
807 return ERR_PTR(-ENOMEM);
808
809 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
810 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
811 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
57fbcce3 812 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
af45a900
AN		 813 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
814 band);
815 new_rule = false;
816
817 if (!(ch_flags & NVM_CHANNEL_VALID)) {
818 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
819 "Ch. %d Flags %x [%sGHz] - No traffic\n",
820 nvm_chan[ch_idx],
821 ch_flags,
822 (ch_idx >= NUM_2GHZ_CHANNELS) ?
823 "5.2" : "2.4");
824 continue;
825 }
826
827 /* we can't continue the same rule */
828 if (ch_idx == 0 || prev_ch_flags != ch_flags ||
829 center_freq - prev_center_freq > 20) {
830 valid_rules++;
831 new_rule = true;
832 }
833
834 rule = &regd->reg_rules[valid_rules - 1];
835
836 if (new_rule)
837 rule->freq_range.start_freq_khz =
838 MHZ_TO_KHZ(center_freq - 10);
839
840 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
841
842 /* this doesn't matter - not used by FW */
843 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
02a50495
EP		 844 rule->power_rule.max_eirp =
845 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
af45a900
AN		 846
847 rule->flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
b281c93d 848 ch_flags, cfg);
af45a900
AN		 849
850 /* rely on auto-calculation to merge BW of contiguous chans */
851 rule->flags |= NL80211_RRF_AUTO_BW;
852 rule->freq_range.max_bandwidth_khz = 0;
853
854 prev_ch_flags = ch_flags;
855 prev_center_freq = center_freq;
856
857 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
bdf2fae8 858 "Ch. %d [%sGHz] %s%s%s%s%s%s%s%s%s(0x%02x): Ad-Hoc %ssupported\n",
af45a900 859 center_freq,
57fbcce3 860 band == NL80211_BAND_5GHZ ? "5.2" : "2.4",
af45a900 861 CHECK_AND_PRINT_I(VALID),
af45a900
AN		 862 CHECK_AND_PRINT_I(ACTIVE),
863 CHECK_AND_PRINT_I(RADAR),
864 CHECK_AND_PRINT_I(WIDE),
865 CHECK_AND_PRINT_I(40MHZ),
866 CHECK_AND_PRINT_I(80MHZ),
867 CHECK_AND_PRINT_I(160MHZ),
868 CHECK_AND_PRINT_I(INDOOR_ONLY),
869 CHECK_AND_PRINT_I(GO_CONCURRENT),
870 ch_flags,
bdf2fae8 871 ((ch_flags & NVM_CHANNEL_ACTIVE) &&
af45a900
AN		 872 !(ch_flags & NVM_CHANNEL_RADAR))
873 ? "" : "not ");
874 }
875
876 regd->n_reg_rules = valid_rules;
877
878 /* set alpha2 from FW. */
879 regd->alpha2[0] = fw_mcc >> 8;
880 regd->alpha2[1] = fw_mcc & 0xff;
881
882 return regd;
883}
884IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
Linux 6.x block layer and io_uring tree(s)